US20080122053A1 - Integrated Circuit Package and a Method for Forming an Integrated Circuit Package - Google Patents

Integrated Circuit Package and a Method for Forming an Integrated Circuit Package Download PDF

Info

Publication number
US20080122053A1
US20080122053A1 US12/025,556 US2555608A US2008122053A1 US 20080122053 A1 US20080122053 A1 US 20080122053A1 US 2555608 A US2555608 A US 2555608A US 2008122053 A1 US2008122053 A1 US 2008122053A1
Authority
US
United States
Prior art keywords
substrate
underfill material
die
integrated circuit
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/025,556
Other languages
English (en)
Inventor
Gerald Ofner
Swain Hong Yeo
Mary Teo
Pei Siang Lim
Khoon Lam Chua
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Assigned to INFINEON TECHNOLOGIES AG reassignment INFINEON TECHNOLOGIES AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: YEO, SWAIN HONG, CHUA, KHOON LAM, LIM, PEI SIANG, OFNER, GERALD, TEO, MARY
Publication of US20080122053A1 publication Critical patent/US20080122053A1/en
Priority to US12/896,647 priority Critical patent/US8357565B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]

Definitions

  • the present invention relates to a method of manufacturing an integrated circuit package, and to an integrated circuit package manufactured according to the method.
  • embodiments of the invention relate to a Flip Chip (FC) or Direct Chip Attach (DCA) package in which the chip is attached directly to the substrate, board or carrier by conductive bumps.
  • FC Flip Chip
  • DCA Direct Chip Attach
  • the electronic components are mounted on a substrate, circuit board or carrier.
  • the electrical connection between the components and the substrate can be achieved through wire bonds, or through connecting bumps, such as solder bumps.
  • the chip, substrate and interconnection are typically encapsulated to produce the final package.
  • Flip Chip packages also known as Direct Chip Attach packages
  • the electronic components are directly connected to the substrate, circuit board or carrier by means of conductive bumps on the chip bond pads.
  • the chip is normally turned face down (i.e., flipped) for connection to the substrate.
  • the bump provides a thermally conductive path for carrying heat from the chip to the substrate, as well as providing part of the mechanical mounting of the die to the substrate.
  • the bump also acts to space the chip from the substrate, thereby preventing electrical contact between the chip and the substrate.
  • a non-conductive underfill adhesive is provided under the chip filling the void between the chip and the substrate.
  • This underfill layer acts to protect the bumps from moisture or other environmental hazards, and provides additional mechanical strength to the assembly.
  • the underfill mechanically locks together the chip and substrate so that differences in the thermal expansion of the chip and substrate do not break or damage the electrical connection of the bumps. Accordingly, the underfill layer is important in maintaining the integrity of the package, and especially to maintain the integrity of the package despite the ambient conditions.
  • a method for producing an integrated circuit package in which the underfill material between a chip or die and substrate, circuit board or carrier on which it is mounted includes a void underneath a generally central portion of the chip.
  • the present inventors have found that popcorn-delamination in Flip Chip packages initiates from the center of the package, and progresses towards the edge of the package. By providing an area around the center of the package in which no underfill material is present, the possibility for delamination between the chip and the underfill layer in this central region can be avoided. By elimination of the initiation site, it is believed that the moisture performance of the package can be improved.
  • underfill material in the center region of the package does not result in a significant decrease in the performance of the functions of the underfill layer, in particular that this does not significantly decrease the mechanical strength of the assembly, or the ability to compensate for thermal expansion differences between the chip and substrate. Further, since the underfill material can still encapsulate the bumps connecting the chip and substrate, the underfill material is still able to protect the bumps from moisture or other environmental hazards.
  • the central void can be provided using a seal pass, in which the underfill material is provided along each side of the chip, entrapping the central void.
  • the seal pass is carried out quickly so that a volume of air or other ambient gas is trapped under the center of the chip preventing the underfill material from flowing into the central void.
  • the fast seal-pass is important when the underfill material has a low viscosity.
  • the underfill material may have a high viscosity, for example, a viscosity of at least 50 Pa.s. In this case, a seal-pass method is again used to deposit the underfill material along each side of the chip.
  • the use of a material of high viscosity minimizes the flow rate of the material, and therefore reduces the need for the seal-pass to be carried out at high speed.
  • an underfill material with a high filler loading for example, with a filler loading of at least 75%, the material will have a sufficiently high viscosity to avoid the need for the seal-pass to be completed quickly.
  • An additional advantage of using a material with a high filler loading is that the material will have improved moisture characteristics.
  • a suitable underfill material is an epoxy based material. This may be loaded with a filler material such as silica.
  • the underfill material By providing a central void in the underfill material, it is possible to reduce the amount of underfill material required, and therefore reduce material costs for production of the integrated circuit package. Further, since less material is required to be provided and cured between the chip and underlying substrate, the time for forming the underfill material layer can be reduced. In particular, this can be achieved as there is no requirement to provide underfill material beneath the entire chip surface, which can reduce the time required to deposit the material, and less curing is required since the amount of underfill material to be cured is reduced. This can also enable the use of a fast-seal pass.
  • an integrated circuit package comprising a chip or die bonded to a substrate, carrier or circuit board, and including an underfill layer between the chip or die and the substrate, carrier or circuit board, in which a void is provided containing no underfill material underneath a generally central part of the chip.
  • FIG. 1 shows a scanning acoustic microscopy image of a known Flip Chip package after moisture tests, showing popcorn delamination
  • FIG. 2 shows a cross-section of a conventional Flip Chip package
  • FIG. 3 shows a partially complete view illustrating an underfill process for a known Flip Chip package with L-line dispensing
  • FIG. 4 shows a cross-section of a Flip Chip package made in accordance with the method of an embodiment of the present invention.
  • FIG. 5 shows an underfill according to an embodiment of the present invention using scan pass dispensing.
  • a conventional Flip Chip package will be described with respect to FIGS. 2 and 3 .
  • a chip 2 is mounted on a substrate, carrier or circuit board 4 by means of conductive bumps 6 .
  • the bumps 6 are formed by sputtering, plating or printing a solderable material on the chip 2 , and these are connected and soldered to chip bond pads provided on the substrate 4 .
  • a non-conductive underfill layer 8 is provided under the chip 2 .
  • the underfill material surrounds the bumps 6 , and fills the entire region underneath the chip between the chip and the substrate.
  • the underfill extends beyond the outer periphery of the chip. It is typical to provide the underfill material by dispensing the material along one or two sides of the periphery of the chip, allowing the material to flow under the chip to fill the area between the chip and substrate. Where material is deposited along one side only, this is known as “single- line” dispensing. Where material is deposited along two adjacent sides, this is known as “L-line dispensing”.
  • FIG. 3 shows the situation in which the material is dispensed from the top and left hand sides of the chip, the flow covering the upper left hand corner of the chip as shown in the Figure. When the material has been dispensed underneath the chip, the material is cured.
  • FIG. 1 shows a scanning acoustic microscopy image of a conventional package after moisture tests.
  • the areas of failure can be seen as the light areas around the center of the package. The failure initiates from the center of the package and progresses outwardly towards the edge.
  • a void 12 (See FIG. 4 ) is provided underneath the chip 2 between the chip and the substrate, this void including no underfill material.
  • the central void 12 can be achieved by dispensing underfill material around the entire periphery of the chip. By rapidly depositing the material along all sides of the chip, a volume of air or other ambient gas is sealed in the central void defined by the material. This entrapped gas prevents the further inward flow of underfill material and therefore ensures that the central void remains. By using underfill material having a high viscosity, and supplying this around the entire circumference of the chip, the material can be deposited more slowly whilst retaining the central void.
  • this intentional central void removes the interfaces between the substrate 4 and the underfill material 8 , and between the underfill material 8 and chip 2 in the central region of the package. By removing the possible interfaces, it is not possible for delamination to occur between the interfaces in this area. As it has been found that the main problem associated with delamination is initiated in this central region, it will be appreciated that removal of the interfaces in this region removes this initiation site.
  • the inventors have found that retaining underfill material around the central void achieves the advantages of reducing the strain on the bumps to a level consistent with that achieved in existing Flip Chip packages, the strain being much less than associated with packages not having any underfill layer.
  • the results of the strain on the outermost bumps, where the strain is the largest, are given below for an existing chip including underfill, a chip with no underfill layer, and for an embodiment of the present invention.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
US12/025,556 2005-08-04 2008-02-04 Integrated Circuit Package and a Method for Forming an Integrated Circuit Package Abandoned US20080122053A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/896,647 US8357565B2 (en) 2005-08-04 2010-10-01 Integrated circuit package and a method for forming an integrated circuit package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/SG2005/000270 WO2007015683A1 (en) 2005-08-04 2005-08-04 An integrated circuit package and a method for forming an integrated circuit package

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
PCT/SG2005/000270 Continuation WO2007015683A1 (en) 2005-08-04 2005-08-04 An integrated circuit package and a method for forming an integrated circuit package

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/896,647 Division US8357565B2 (en) 2005-08-04 2010-10-01 Integrated circuit package and a method for forming an integrated circuit package

Publications (1)

Publication Number Publication Date
US20080122053A1 true US20080122053A1 (en) 2008-05-29

Family

ID=34978611

Family Applications (2)

Application Number Title Priority Date Filing Date
US12/025,556 Abandoned US20080122053A1 (en) 2005-08-04 2008-02-04 Integrated Circuit Package and a Method for Forming an Integrated Circuit Package
US12/896,647 Expired - Fee Related US8357565B2 (en) 2005-08-04 2010-10-01 Integrated circuit package and a method for forming an integrated circuit package

Family Applications After (1)

Application Number Title Priority Date Filing Date
US12/896,647 Expired - Fee Related US8357565B2 (en) 2005-08-04 2010-10-01 Integrated circuit package and a method for forming an integrated circuit package

Country Status (3)

Country Link
US (2) US20080122053A1 (de)
DE (1) DE112005003634T5 (de)
WO (1) WO2007015683A1 (de)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7816181B1 (en) * 2009-06-30 2010-10-19 Sandisk Corporation Method of under-filling semiconductor die in a die stack and semiconductor device formed thereby
US20110001233A1 (en) * 2006-10-19 2011-01-06 Teppei Iwase Semiconductor device mounted structure and semiconductor device mounting method
US20160056119A1 (en) * 2014-08-20 2016-02-25 Samsung Electro-Mechanics Co., Ltd. Flip chip package and manufacturing method thereof
CN115579300A (zh) * 2022-11-24 2023-01-06 河北北芯半导体科技有限公司 一种倒装芯片封装堆叠方法

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8039957B2 (en) * 2009-03-11 2011-10-18 Raytheon Company System for improving flip chip performance
US8451620B2 (en) * 2009-11-30 2013-05-28 Micron Technology, Inc. Package including an underfill material in a portion of an area between the package and a substrate or another package
US9627346B2 (en) * 2013-12-11 2017-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Underfill pattern with gap
US9373559B2 (en) 2014-03-05 2016-06-21 International Business Machines Corporation Low-stress dual underfill packaging
CN106415826A (zh) * 2014-06-26 2017-02-15 索尼公司 半导体器件和制造半导体器件的方法
US20170276383A1 (en) * 2014-09-08 2017-09-28 Seeley International Pty Ltd Compact indirect evaporative cooler
KR102306673B1 (ko) * 2014-09-22 2021-09-29 삼성전자주식회사 반도체 패키지 및 그 제조 방법
KR102285332B1 (ko) 2014-11-11 2021-08-04 삼성전자주식회사 반도체 패키지 및 이를 포함하는 반도체 장치
US20180122777A1 (en) * 2016-10-31 2018-05-03 Raytheon Company Hybrid micro-circuit device with stacked chip components
US11715928B2 (en) * 2019-08-29 2023-08-01 Intel Corporation Decoupling layer to reduce underfill stress in semiconductor devices

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5612576A (en) * 1992-10-13 1997-03-18 Motorola Self-opening vent hole in an overmolded semiconductor device
US5864178A (en) * 1995-01-12 1999-01-26 Kabushiki Kaisha Toshiba Semiconductor device with improved encapsulating resin
US6074897A (en) * 1996-05-01 2000-06-13 Lucent Technologies Inc. Integrated circuit bonding method and apparatus
US6093972A (en) * 1997-05-19 2000-07-25 Motorola, Inc. Microelectronic package including a polymer encapsulated die
US20020043728A1 (en) * 2000-08-24 2002-04-18 Tadaaki Harada Resin composition for sealing semiconductor, semiconductor device using the same, semiconductor wafer and mounted structure of semiconductor device
US6519844B1 (en) * 2001-08-27 2003-02-18 Lsi Logic Corporation Overmold integrated circuit package
US6663943B2 (en) * 2000-06-27 2003-12-16 Murata Manufacturing Co., Ltd. Surface acoustic wave device and method for making the same
US6693239B2 (en) * 2001-09-06 2004-02-17 Delphi Technologies Inc. Overmolded circuit board with underfilled surface-mount component and method therefor
US6700209B1 (en) * 1999-12-29 2004-03-02 Intel Corporation Partial underfill for flip-chip electronic packages
US6956165B1 (en) * 2004-06-28 2005-10-18 Altera Corporation Underfill for maximum flip chip package reliability
US7119449B2 (en) * 2003-12-08 2006-10-10 Delphi Technologies, Inc. Enhancement of underfill physical properties by the addition of thermotropic cellulose

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5766982A (en) * 1996-03-07 1998-06-16 Micron Technology, Inc. Method and apparatus for underfill of bumped or raised die
JP3565485B2 (ja) * 1999-03-30 2004-09-15 新光電気工業株式会社 半導体チップの実装方法
US6628679B1 (en) * 1999-12-29 2003-09-30 Intel Corporation SERDES (serializer/deserializer) time domain multiplexing/demultiplexing technique
US6632704B2 (en) * 2000-12-19 2003-10-14 Intel Corporation Molded flip chip package
US6800946B2 (en) * 2002-12-23 2004-10-05 Motorola, Inc Selective underfill for flip chips and flip-chip assemblies
US7141452B2 (en) * 2003-12-01 2006-11-28 Intel Corporation Methods of reducing bleed-out of underfill and adhesive materials

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5612576A (en) * 1992-10-13 1997-03-18 Motorola Self-opening vent hole in an overmolded semiconductor device
US5864178A (en) * 1995-01-12 1999-01-26 Kabushiki Kaisha Toshiba Semiconductor device with improved encapsulating resin
US6074897A (en) * 1996-05-01 2000-06-13 Lucent Technologies Inc. Integrated circuit bonding method and apparatus
US6093972A (en) * 1997-05-19 2000-07-25 Motorola, Inc. Microelectronic package including a polymer encapsulated die
US6700209B1 (en) * 1999-12-29 2004-03-02 Intel Corporation Partial underfill for flip-chip electronic packages
US6663943B2 (en) * 2000-06-27 2003-12-16 Murata Manufacturing Co., Ltd. Surface acoustic wave device and method for making the same
US20020043728A1 (en) * 2000-08-24 2002-04-18 Tadaaki Harada Resin composition for sealing semiconductor, semiconductor device using the same, semiconductor wafer and mounted structure of semiconductor device
US6519844B1 (en) * 2001-08-27 2003-02-18 Lsi Logic Corporation Overmold integrated circuit package
US6693239B2 (en) * 2001-09-06 2004-02-17 Delphi Technologies Inc. Overmolded circuit board with underfilled surface-mount component and method therefor
US7119449B2 (en) * 2003-12-08 2006-10-10 Delphi Technologies, Inc. Enhancement of underfill physical properties by the addition of thermotropic cellulose
US6956165B1 (en) * 2004-06-28 2005-10-18 Altera Corporation Underfill for maximum flip chip package reliability

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110001233A1 (en) * 2006-10-19 2011-01-06 Teppei Iwase Semiconductor device mounted structure and semiconductor device mounting method
US8106521B2 (en) * 2006-10-19 2012-01-31 Panasonic Corporation Semiconductor device mounted structure with an underfill sealing-bonding resin with voids
US7816181B1 (en) * 2009-06-30 2010-10-19 Sandisk Corporation Method of under-filling semiconductor die in a die stack and semiconductor device formed thereby
US20110024881A1 (en) * 2009-06-30 2011-02-03 Shrikar Bhagath Semiconductor device having under-filled die in a die stack
US8575724B2 (en) 2009-06-30 2013-11-05 Sandisk Technologies Inc. Semiconductor device having under-filled die in a die stack
US20160056119A1 (en) * 2014-08-20 2016-02-25 Samsung Electro-Mechanics Co., Ltd. Flip chip package and manufacturing method thereof
US9583368B2 (en) 2014-08-20 2017-02-28 Samsung Electro-Mechanics Co., Ltd. Flip chip package and manufacturing method thereof
CN115579300A (zh) * 2022-11-24 2023-01-06 河北北芯半导体科技有限公司 一种倒装芯片封装堆叠方法

Also Published As

Publication number Publication date
DE112005003634T5 (de) 2008-06-12
US20110020985A1 (en) 2011-01-27
US8357565B2 (en) 2013-01-22
WO2007015683A1 (en) 2007-02-08

Similar Documents

Publication Publication Date Title
US8357565B2 (en) Integrated circuit package and a method for forming an integrated circuit package
JP3718205B2 (ja) チップ積層型半導体装置およびその製造方法
KR100809693B1 (ko) 하부 반도체 칩에 대한 신뢰도가 개선된 수직 적층형멀티칩 패키지 및 그 제조방법
KR100341104B1 (ko) 반도체장치의 어셈블리방법 및 이 방법에 의해 제조된 반도체 장치
US8962395B2 (en) QFN package and manufacturing process thereof
CN101221946B (zh) 半导体封装、及系统级封装模块的制造方法
US5385869A (en) Semiconductor chip bonded to a substrate and method of making
US6093972A (en) Microelectronic package including a polymer encapsulated die
US7268436B2 (en) Electronic device with cavity and a method for producing the same
CN101017786B (zh) 半导体封装的制造方法
CN100421251C (zh) 半导体装置及其制造方法
US20070273019A1 (en) Semiconductor package, chip carrier structure thereof, and method for fabricating the chip carrier
US9721865B2 (en) Semiconductor device with a semiconductor chip connected in a flip chip manner
KR100586208B1 (ko) 반도체 장치 및 그 제조방법
US20070166879A1 (en) Multi-chip stack package and fabricating method thereof
KR20050119414A (ko) 에지 패드형 반도체 칩의 스택 패키지 및 그 제조방법
US20150318228A1 (en) Module and method for producing module
US20110316150A1 (en) Semiconductor package and method for manufacturing semiconductor package
KR20090019751A (ko) 반도체 장치 및 그 제조 방법
US20200211978A1 (en) Package device and method of manufacturing the same
US20040235220A1 (en) Flip chip mounting method
US20110298124A1 (en) Semiconductor Structure
US7713791B2 (en) Panel and semiconductor device having a composite plate with semiconductor chips
US6900080B2 (en) Microelectronic package with reduced underfill and methods for forming such packages
JP2003158215A (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
AS Assignment

Owner name: INFINEON TECHNOLOGIES AG, GERMANY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:OFNER, GERALD;YEO, SWAIN HONG;TEO, MARY;AND OTHERS;REEL/FRAME:020636/0167;SIGNING DATES FROM 20050912 TO 20050915

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION