US20060281314A1 - Wafer Holder And Method Of Holding A Wafer - Google Patents

Wafer Holder And Method Of Holding A Wafer Download PDF

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Publication number
US20060281314A1
US20060281314A1 US11/307,284 US30728406A US2006281314A1 US 20060281314 A1 US20060281314 A1 US 20060281314A1 US 30728406 A US30728406 A US 30728406A US 2006281314 A1 US2006281314 A1 US 2006281314A1
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Prior art keywords
wafer
wafer stage
ring
diameter
inner diameter
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Abandoned
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US11/307,284
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English (en)
Inventor
Sunil Wickramanayaka
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Canon Anelva Corp
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Canon Anelva Corp
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Assigned to CANON ANELVA CORPORATION reassignment CANON ANELVA CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: WICKRAMANAYAKA, SUNIL
Publication of US20060281314A1 publication Critical patent/US20060281314A1/en
Assigned to CANON ANELVA CORPORATION reassignment CANON ANELVA CORPORATION CHANGE OF ADDRESS Assignors: CANON ANELVA CORPORATION
Priority to US13/169,831 priority Critical patent/US8986522B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68735—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by edge profile or support profile
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04—Coating on selected surface areas, e.g. using masks
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/225—Oblique incidence of vaporised material on substrate
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/50—Substrate holders
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/50—Substrate holders
    • C23C14/505—Substrate holders for rotation of the substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/34—Gas-filled discharge tubes operating with cathodic sputtering
    • H01J37/3411—Constructional aspects of the reactor
    • H01J37/3414—Targets
    • H01J37/3417—Arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H01L21/67103—Apparatus for thermal treatment mainly by conduction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H01L21/67109—Apparatus for thermal treatment mainly by convection

Definitions

  • the present invention relates generally to a wafer holder and a method of holding a wafer, and in one aspect, the present invention relates to a wafer holder including wafer stage and a wafer stage outer-ring surrounding the wafer stage and provided in a plasma processing chamber such as a plasma processing chamber of an angled sputtering system.
  • PVD physical vapor deposition
  • An angled sputtering is one of the PVD techniques where the target and wafer are placed not in parallel but with an angle. See JP 2002-194540.
  • the advantage of this sputtering technique is it yields extremely uniform film.
  • the disadvantage of this technique is that edge exclusion (hereinafter referred to “EE”) for a film deposited on a wafer surface trades-off with film wrapping around the wafer edge. This is explained in details with reference to FIGS. 5 to 9 of the present application.
  • FIGS. 5 to 8 A cross sectional diagram of an example of an angled sputtering system and a conventional wafer holder 50 adopted in the angled sputtering system are shown in FIGS. 5 to 8 , respectively.
  • the process chamber of this angled sputtering system has a vacuum port 66 and a wafer in/out port 67 .
  • the wafer holder 50 is comprised of wafer stage 51 , insulating shield 52 surrounding wafer stage 51 , metallic outer-shield 53 , shaft 54 supporting the metallic outer-shield 53 and a masking outer-ring 55 .
  • the masking outer-ring 55 is attached to several metallic or insulating pins 56 , usually 3 (three) metallic or insulating pins, in order to move the masking outer-ring 55 up and down. In FIG. 5 , the insulating pins 56 , 56 are moved up and down by lift-up pin controller 65 .
  • the masking outer-ring 55 While the wafer 57 is loaded on to the wafer stage 51 , the masking outer-ring 55 is raised up. After the wafer 57 is placed on the wafer stage 51 , the masking outer-ring 55 is lowered until the separation between the upper surface of wafer 57 and the backside surface of the masking outer-ring 55 is less than 1 mm. Usually, the masking outer-ring 55 is not lowered until the backside surface of it touches the wafer 57 , since it causes a generation of particles on the surface of wafer 57 by the fraction.
  • the masking outer-ring 55 covers a few millimeters, usually less than 5 mm, on the wafer edge 62 ( FIG. 7 ). This covered region is denoted by X (denoted by numeral 63 ) in FIGS. 7 and 8 .
  • FIG. 9 The configuration of other conventional and commonly used wafer holder is given in FIG. 9 wherein there is no masking outer-ring.
  • FIGS. 7 and 8 show the film deposition characteristics at the most close and most far positions on wafer 57 with respect to the target 58 when the film is deposited by the angled sputtering system shown in FIG. 5 . These positions are labeled as A (denoted by numeral 59 ) and B (denoted by numeral 60 ) in FIG. 6 .
  • A deposition by numeral 59
  • B deposition by numeral 60
  • FIGS. 7 and 8 show the film deposition characteristics at the most close and most far positions on wafer 57 with respect to the target 58 when the film is deposited by the angled sputtering system shown in FIG. 5 .
  • These positions are labeled as A (denoted by numeral 59 ) and B (denoted by numeral 60 ) in FIG. 6 .
  • A deposition of the atoms 61 from the sputtering target 58 go through the space between the wafer 57 and the masking outer-ring 55 , as shown in FIG.
  • This shadowed region is defined as Y (denoted by numeral 64 ) in FIG. 8 . Films are not deposited in this shadowed region Y ( 64 ) at position B ( 60 ). Because of these different deposition characteristics at positions A ( 59 ) and B ( 60 ), the film is non-uniform at the wafer edge 62 . Further this non-uniform region is larger than X ( 63 ), which is the region that is physically covered by the masking outer-ring 55 .
  • This non-uniform region may be extended up to y ( 64 ).
  • Y ( 64 ) may be as large as 10 mm resulting in a 10 mm edge exclusion (EE).
  • EE edge exclusion
  • films deposit all over the wafer resulting in almost 0 EE. However, in this condition films wrap around the wafer edge and deposit on wafer stage 51 . This contaminates the backside of the wafer 57 . Film deposition on the wafer stage 51 is an undesirable feature since that film gets thicker and thicker with time. This accelerates and increases the wafer backside contamination with the increase of process time.
  • one aspect of the present invention provides a wafer holder including a wafer stage and a wafer stage outer-ring surrounding the wafer stage wherein the wafer stage has a diameter smaller than the diameter loaded on the wafer stage, the inner diameter at the upper side of the outer-ring is larger than the diameter of wafer loaded on the wafer stage, and the upper surface of the wafer stage outer-ring lies above the upper surface of wafer loaded on the wafer stage.
  • the inner diameter at the upper side of the wafer stage outer-ring is slightly larger than the diameter of wafer loaded on the wafer stage and the wafer stage has a diameter smaller than the diameter of the wafer loaded on the wafer stage so that a narrow space is formed between the outer peripheral of the wafer and the inner peripheral wall of the wafer stage outer-ring.
  • edge exclusion for example it is possible to reduce edge exclusion (EE) to less than 2 mm by the before described slightly larger inner diameter at the upper side of the wafer stage outer-ring.
  • edge exclusion for example it is possible to reduce edge exclusion (EE) to less than 2 mm by the before described slightly larger inner diameter at the upper side of the wafer stage outer-ring.
  • the wafer backside contamination which is caused when the wafer holder as shown in FIG. 9 is used, can be minimized.
  • the wafer holder outer-ring may further have a different inner diameter at the lower side. That is to say, in the above-described wafer holder, the wafer stage outer-ring may be modified to have two different inner diameters, the one is the inner diameter at the upper side of the outer-ring and the other is the inner diameter at the lower side of the outer-ring.
  • the above-described inner diameter at the upper side of the wafer stage outer-ring is slightly larger than the diameter of wafer loaded on the wafer stage as described above, while the inner diameter at the lower side of the wafer stage outer-ring is slightly smaller than the diameter of wafer but slightly larger than the diameter of the wafer stage.
  • the above-described narrow space between the outer peripheral wall of the wafer and the inner peripheral wall of the wafer stage outer-ring continues and extends to the narrow space between the outer peripheral wall of the wafer stage and the inner peripheral wall of the wafer stage outer-ring.
  • the wafer stage outer-ring may be modified to have a horizontal plane formed between one inner peripheral wall defining the inner diameter at the upper side of outer-ring and the other inner peripheral wall defining the inner diameter at lower side of outer-ring, and the horizontal plane lies below the backside surface of the wafer loaded on the wafer stage without contacting the backside surface of wafer.
  • the wafer stage may be modified to be made of two or more separate pieces for adjusting the height of the wafer stage thereby adjusting the space between the upper surface of the wafer stage and the upper surface of the wafer stage outer-ring.
  • This configuration may be modified in that the wafer stage outer-ring can be moved up and down, thereby the shadowed area which is formed at the wafer edge owing to the existence of wafer stage outer-ring may be reduced for reducing edge exclusion (EE) by adjusting the space between the upper surface of wafer stage and the upper surface of wafer stage outer-ring by moving the wafer stage outer-ring up and down.
  • EE edge exclusion
  • the wafer stage of two or more separate pieces for adjusting the height of the wafer stage, and make the wafer stage outer-ring which can be moved up and down.
  • a wafer holder in which the edge exclusion (EE) can be reduced to less than a 2 mm edge exclusion (EE). It is also possible to reduce the probability of contaminating the backside of wafer, which is loaded on the wafer holder, with depositing material.
  • FIG. 1 shows a cross sectional diagram of an angled sputtering system in which a wafer holder according to an embodiment of the present invention is adopted and provided in the angled sputtering system.
  • FIG. 2 shows an enlarged cross sectional diagram showing the position A ( 15 ) labeled in FIG. 1 .
  • FIG. 3 shows an enlarged cross sectional diagram showing the position B ( 16 ) labeled in FIG. 1 .
  • FIG. 4 shows a cross sectional diagram of another embodiment of a wafer holder of the present invention.
  • FIG. 5 shows a cross sectional diagram of an angled sputtering system in which a conventional wafer holder is adopted and provided in the angled sputtering system.
  • FIG. 6 shows an enlarged cross sectional diagram of the conventional wafer holder shown in FIG. 5 .
  • FIG. 7 shows an enlarged cross sectional diagram showing the position A ( 59 ) labeled in FIG. 6 .
  • FIG. 8 shows an enlarged cross sectional diagram showing the position B ( 60 ) labeled in FIG. 6 .
  • FIG. 9 shows a cross sectional diagram of another conventional wafer holder.
  • FIG. 1 shows a cross sectional diagram of an angled sputtering system in which the wafer holder 25 is one embodiment of the present invention.
  • the wafer holder 25 is placed in a plasma processing chamber where the target 11 and wafer holder 25 are off axis, and a target 11 is placed in the ceiling of the process chamber with an angle with respect to the surface of the wafer 5 which is loaded on the wafer holder 25 as shown in FIG. 1 .
  • the target 11 can be fixed to the ceiling of the process chamber. Although it is not shown, the target 11 may be placed parallel to the surface of wafer 5 which is located on the wafer holder 25 .
  • the process chamber has a vacuum port 17 and wafer in/out port 18 .
  • the wafer holder 25 is comprised of a wafer stage 1 , a wafer stage outer-ring 2 surrounding wafer stage 1 , an insulating block 3 , and an outer shield 4 .
  • the insulating block 3 is placed below the wafer stage 1 and the outer-ring 2 , and supports them. Also, the insulating block 3 supporting the wafer stage 1 and the outer-ring 2 is inserted in the cylindrical outer shield 4 .
  • the outer-ring 2 is an o-ring shaped wafer-stage outer-ring.
  • the wafer stage 1 and the wafer stage outer-ring 2 are an integrated part of the wafer holder 25 placed in a plasma processing chamber, and the wafer holder 25 can rotate around its central axis.
  • the wafer stage 1 is usually made of a metal, for example aluminum.
  • the diameter of the wafer stage 1 is a few millimeters, for example 10 mm, smaller than the diameter of the wafer 5 which is loaded onto the wafer stage 1 . Therefore, when a wafer 5 is placed on the wafer stage 1 , the outer area of the wafer 5 extends outside of the wafer stage 1 as shown in FIGS. 1, 2 and 3 .
  • the wafer stage outer-ring 2 has two different inner diameters. One is the inner diameter at the upper side of the outer-ring 2 , and the other is the inner diameter at the lower side of the outer-ring 2 .
  • the inner diameter at the upper side of the outer-ring 2 is a few millimeters, for example 4 mm, larger than the diameter of the wafer 5 . While the inner diameter at the lower side of the outer-ring 2 is few millimeters, for example 3 mm, smaller than the diameter of the wafer 5 , but a few millimeters, for example 3 mm, larger than the diameter of wafer stage 1 .
  • the inner diameter at the upper side of the outer-ring 2 is larger than the diameter of the wafer 5 while the inner diameter at the lower side of the outer-ring 2 is smaller than the diameter of wafer 5 , but larger than the diameter of wafer stage 1 .
  • the outer diameter of wafer stage outer-ring 2 is not critical and is usually 10-30 mm larger than the diameter of the wafer 5 .
  • the outer-ring 2 since the outer-ring 2 has two different inner diameters, there is a horizontal plane between one inner peripheral wall defining the inner diameter at the upper side of outer-ring 2 and the other inner peripheral wall defining the inner diameter at lower side of outer-ring 2 . It is preferable that the position of this horizontal plane is adjusted to lie just below the backside of the wafer 5 with a small separation, so that this horizontal plane is not in physical contact with the backside of wafer 5 .
  • the separation between the horizontal plane and the backside of the wafer 5 is not critical and can be in the region of 0.2 mm to 10 mm, usually larger than 0.5 mm.
  • the height of the upper surface of the outer-ring 2 is important to get the best results.
  • the upper surface of the outer-ring 2 should be slightly above the upper surface of the wafer 5 as shown in FIGS. 1 to 3 .
  • the edge exclusion (EE) and wrapping film around the wafer edge are affected by the distance between upper surface of outer-ring 2 and the upper surface of the wafer 5 , denoted by letter H (denoted by numeral 14 ) in FIGS. 2 and 3 . It is preferable to maintain the distance H within the range of 1 mm to 10 mm.
  • the outer-ring 2 is made of a metal, typically aluminum.
  • the surface of outer-ring 2 may be coated with a dielectric material, for example Al2O3.
  • the outer-ring 2 is configured to be in an electrically floating state. However, it should be noted that the electrical status of the outer-ring 2 does not affect its intended properties with this invention.
  • the wafer stage 1 is placed on the insulating block 3 , preferably a dielectric block.
  • the insulating block 3 preferably a dielectric block.
  • the only reason to place the wafer stage 1 on an insulating block 3 is to control the deposition properties by applying electrical power to wafer stage 1 , when it is necessary.
  • FIGS. 1, 2 and 3 show that the wafer stage 1 is in an electrically floating state. However, it should be noted that the electrically floating state of the wafer stage 1 does not affect its intended properties with this invention.
  • ESC electrostatic chuck
  • the height of the wafer stage 1 is not critical, but can be varied in the range of 1 mm to 50 mm.
  • the wafer stage 1 does not have to be made of a single material, instead one can use a composite configuration made of different materials, for example a combination of metal and dielectrics as shown in FIG. 4 .
  • the wafer stage 1 is comprised of a metal disk 21 , insulating disk 20 and metal disk 19 . That is to say, in FIG. 4 , the wafer stage 1 is made of three separate pieces, so that the height of wafer stage 1 can be adjusted by removing the insulating disk 20 , for example. Also, the height of the wafer stage 1 can be adjusted by inserting a further insulating disk, for example, so that the space between the upper surface of wafer stage 1 and the upper surface of wafer stage outer-ring 2 can be adjusted easily.
  • the wafer stage 1 may or may not be heated or cooled during film deposition.
  • the heating or cooling mechanism of the wafer stage 1 is not shown in diagrams for simplicity.
  • the outer shield 4 is made of a metal.
  • the inner diameter of the outer shield 4 is slightly larger than the outer diameter of the outer ring 2 , so that there is a few millimeter separation between the inner peripheral wall of outer shield 4 and the outer peripheral wall outer ring 2 .
  • the insulating block 3 may extend up to the inside wall of the outer shield 4 , although it is not shown.
  • the narrow space 6 between the outer shield 4 and the outer-ring 2 is important in order to maintain the electrical status of the outer-ring 2 when it is in an electrically floating state.
  • the wafer holder may include three or four wafer lift-up pins. These wafer lift-up pins are not shown in diagrams for simplicity.
  • the wafer fabricating process is carried out as follows, for example.
  • FIGS. 2 and 3 represent positions A ( 15 ) and B ( 16 ) labeled in FIG. 1 , respectively.
  • this PVD process is carried out at very low pressures, lower than 0.1 Pa. At these pressures the mean free path of gaseous species including sputtered atoms 12 becomes very short compared with the distance between the target 11 and the wafer 5 . Therefore, almost all depositing atoms can be considered as coming with the angle as shown in FIGS. 2 and 3 , which the target 11 is placed with respect to the wafer 5 as shown in FIG. 1 .
  • a film deposits up to the wafer edge at position A ( 15 ) as shown in FIG. 2 .
  • the atoms 12 are coming in at an angle, which the target 11 is placed with respect to the wafer 5 , as shown in FIG. 1 .
  • any shadowed region is not generated as shown in FIG. 2 . So that films can be deposited at the wafer edge, and a very small edge exclusion (EE) such as less than 2 mm EE can be obtained at position A ( 15 ).
  • EE edge exclusion
  • the height of the separation 10 is 0.5 mm.
  • the narrow space 7 extends up to the insulating block 3 , as shown in FIG. 2 . This is in order to assure that no film is deposited on the insulating block 3 supporting the outer-ring 2 and the wafer stage 1 . The reason is, if a metal film is deposited so as to connect the outer-ring 2 and the wafer stage 1 , the electrical potential of both the wafer stage 1 and the outer-ring 2 becomes the same. This creates problems if the wafer stage 1 is given RF or DC bias as a means to control the deposition.
  • the extension of the narrow space 7 up to the insulating block 3 further reduces the probability in contaminating the backside of the wafer 5 with depositing material.
  • Film deposition process at position B ( 16 ) is shown in FIG. 3 .
  • atoms 12 are coming in at an angle, which the target 11 is placed with respect to the wafer 5 as shown in FIG. 1 , so that the outer-ring 2 may make a shadow on the wafer edge.
  • the length of the shadow depends on the height of the upper surface of outer-ring 2 with respect to the upper surface of the wafer 5 , the distance of the narrow space 7 between the outer-ring 2 and the wafer 5 , and the angle of target 11 with respect to the wafer 5 .
  • the inner diameter at the upper side of the outer-ring 2 is larger than the diameter of the wafer 5 , it is easy to select the height of the upper surface of outer-ring 2 with respect to the upper surface of the wafer 5 , which is denoted as H (denoted by numeral 14 ) in FIG. 3 , in order to reduce the shadowed region, which may be generated by the existence of the outer-ring 2 .
  • H denoted by numeral 14
  • EE edge exclusion
US11/307,284 2005-02-25 2006-01-30 Wafer Holder And Method Of Holding A Wafer Abandoned US20060281314A1 (en)

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JP2005050064A JP4336320B2 (ja) 2005-02-25 2005-02-25 ウエハホルダ

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KR (1) KR101089766B1 (ja)
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070000614A1 (en) * 2003-03-21 2007-01-04 Tokyo Electron Limited Method and apparatus for reducing substrate backside deposition during processing
US20110042209A1 (en) * 2008-06-25 2011-02-24 Canon Anelva Corporation Sputtering apparatus and recording medium for recording control program thereof
WO2014099252A1 (en) * 2012-12-21 2014-06-26 Applied Materials, Inc. Wafer edge protection and efficiency using inert gas and ring

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4705816B2 (ja) 2005-07-27 2011-06-22 株式会社日立ハイテクノロジーズ プラズマ処理装置
JP2009260041A (ja) * 2008-04-17 2009-11-05 Fuji Electric Device Technology Co Ltd 半導体装置の製造方法および成膜装置
JP6088780B2 (ja) * 2012-10-02 2017-03-01 株式会社アルバック プラズマ処理方法及びプラズマ処理装置
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CN1825556B (zh) 2010-10-13
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JP2006233283A (ja) 2006-09-07
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