US20060104799A1 - Methods and apparatus for reducing an electronic device manufacturing tool footprint - Google Patents

Methods and apparatus for reducing an electronic device manufacturing tool footprint Download PDF

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Publication number
US20060104799A1
US20060104799A1 US11/179,037 US17903705A US2006104799A1 US 20060104799 A1 US20060104799 A1 US 20060104799A1 US 17903705 A US17903705 A US 17903705A US 2006104799 A1 US2006104799 A1 US 2006104799A1
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US
United States
Prior art keywords
floor area
electronic device
device manufacturing
mainframe
manufacturing tool
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/179,037
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English (en)
Inventor
Janusz Jozwiak
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Priority to US11/179,037 priority Critical patent/US20060104799A1/en
Assigned to APPLIED MATERIALS, INC. reassignment APPLIED MATERIALS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JOZWIAK, JANUSZ
Publication of US20060104799A1 publication Critical patent/US20060104799A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/6719—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the construction of the processing chambers, e.g. modular processing chambers

Definitions

  • the present invention relates generally to electronic device manufacturing, and more particularly to methods and apparatus for reducing an electronic device manufacturing tool footprint.
  • FIG. 1 illustrates a conventional electronic device manufacturing tool (or system) 101 .
  • the electronic device manufacturing tool 101 includes components, such as a mainframe power supply (e.g., a mainframe power box) 103 and a mainframe controller 105 , coupled to a mainframe 107 .
  • the mainframe 107 may include one or more processing chambers 109 , each of which is coupled to a respective processing chamber power box 110 and processing chamber controller 111 , and a transfer chamber 112 coupled to a load lock 113 .
  • a footprint of the electronic device manufacturing tool 101 is the area of a floor (e.g., in a clean room) 115 occupied by the electronic device manufacturing tool 101 .
  • the mainframe power box 103 and mainframe controller 105 are coupled to a rack 117 (e.g., an enclosure rack) separate from the mainframe 107 . Therefore, the mainframe power box 103 and controller 105 occupy a floor space 118 separate from the mainframe of the electronic device manufacturing tool 101 , thereby increasing the electronic device manufacturing tool's footprint.
  • a rack 117 e.g., an enclosure rack
  • mainframe power box 103 and controller 105 are coupled to the mainframe 107 via wiring 119 , which extends from the separate rack 117 to the mainframe 107 . Therefore, the farther the separate rack 117 is located from the mainframe 107 , the more wiring 119 is required by the electronic device manufacturing tool 101 , which reduces system integration. As described below, reducing the electronic device manufacturing tool footprint may increase tool (or system) integration.
  • a first method for reducing an electronic device manufacturing tool's footprint.
  • the first method includes the steps of (1) positioning a load lock of an electronic device manufacturing tool such that the load lock occupies a first floor area; and (2) positioning a mainframe power supply in a second floor area, wherein a substantial portion of the second floor area is within the first floor area, thereby reducing the electronic device manufacturing tool footprint.
  • a second method for reducing an electronic device manufacturing tool footprint.
  • the second method includes the steps of (1) positioning a load lock of an electronic device manufacturing tool such that the load lock occupies a first floor area; and (2) positioning a mainframe controller in a second floor area, wherein a substantial portion of the second floor area is within the first floor area, thereby reducing the electronic device manufacturing tool footprint.
  • a third method for reducing an electronic device manufacturing tool shipping cost.
  • the third method includes the steps of (1) placing a load lock and a mainframe power supply of an electronic device manufacturing tool into a container; and (2) shipping the container.
  • a fourth method for reducing an electronic device manufacturing tool shipping cost.
  • the fourth method includes the steps of (1) placing a load lock and a mainframe controller of an electronic device manufacturing tool into a container; and (2) shipping the container.
  • a first apparatus for reducing an electronic device manufacturing tool footprint.
  • the first apparatus includes (1) a load lock frame; (2) a load lock of an electronic device manufacturing tool coupled to the load lock frame such that the load lock occupies a first floor area; and (3) a mainframe power supply coupled to the load lock frame such that the mainframe power supply occupies a second floor area. A substantial portion of the second floor area is within the first floor area, thereby reducing the electronic device manufacturing tool footprint.
  • a second apparatus for reducing an electronic device manufacturing tool footprint.
  • the second apparatus includes (1) a load lock frame; (2) a load lock of an electronic device manufacturing tool coupled to the load lock frame such that the load lock occupies a first floor area; and (3) a mainframe controller coupled to the load lock frame such that the mainframe controller occupies a second floor area. A substantial portion of the second floor area is within the first floor area, thereby reducing the electronic device manufacturing tool footprint.
  • a third apparatus includes (1) an electronic device manufacturing tool having a mainframe that occupies a first footprint, and (2) a mainframe power supply that occupies a second footprint that substantially overlaps the first footprint.
  • a fourth apparatus includes (1) an electronic device manufacturing tool having a mainframe that occupies a first footprint, and (2) a mainframe controller that occupies a second footprint that substantially overlaps the first footprint.
  • FIG. 1 illustrates a conventional electronic device manufacturing tool.
  • FIG. 2 illustrates an exemplary electronic device manufacturing tool in accordance with an embodiment of the present invention.
  • FIG. 2 illustrates an exemplary electronic device manufacturing tool (or system) 201 in accordance with an embodiment of the present invention.
  • the electronic device manufacturing tool 201 may be employed to manufacture and/or process substrates such as glass or polymer substrates used to manufacture flat panel displays, semiconductor wafers, etc.
  • the configuration of the exemplary electronic device manufacturing tool 201 is similar to the configuration of the conventional electronic device manufacturing tool 101 of FIG. 1 .
  • the exemplary electronic device manufacturing tool 201 includes a mainframe 203 .
  • the mainframe 203 includes one or more processing chambers 205 , each of which is coupled to a respective processing chamber power box 206 and processing chamber controller 207 , a transfer chamber 208 and a load lock 209 .
  • the load lock 209 is supported by a load lock rack 211 .
  • a mainframe power box (e.g., power supply) 213 of the exemplary electronic device manufacturing tool 201 which provides power to the mainframe 203 and to each processing chamber power box 206 , is positioned differently than is the mainframe power box 103 of the conventional electronic device manufacturing tool 101 .
  • the load lock 209 is positioned (e.g., on the load lock rack 211 ) such that the load lock 209 occupies a first floor area 215
  • the mainframe power box 213 is positioned to occupy a second floor area 217 , a substantial portion of which is included in the first floor area 215 .
  • the first floor area 215 may include the entire second floor area 217 .
  • the mainframe power box 213 is adapted to couple to the load lock rack 211 .
  • the mainframe power box 213 may couple to and be supported by the load lock rack 211 and/or be an integral part of the load lock 209 .
  • the mainframe power box 213 may be positioned below the load lock 209 .
  • the mainframe power box 213 may assume other positions, such as above the load lock 209 . Therefore, according to the configuration of the exemplary electronic device manufacturing tool 201 , the load lock 209 and the mainframe power box 213 occupy at least substantially overlapping floor areas. In this manner, the footprint of the electronic device manufacturing tool 201 is reduced. Reducing the electronic device manufacturing tool footprint may reduce a required clean room size, which may lower the cost of operating the tool.
  • a mainframe controller 218 of the exemplary electronic device manufacturing tool 201 may be positioned differently than is the mainframe controller 105 of the conventional electronic device manufacturing tool 101 .
  • the mainframe controller 218 is positioned to occupy a floor area (e.g., a third floor area) 219 , a substantial portion of which is included within the first floor area 215 .
  • the first floor area 215 may include at least 50 percent of, or preferably the entire third floor area 219 .
  • the mainframe controller 218 may be adapted to couple to and be supported by the load lock rack 211 .
  • the mainframe controller 218 may couple to a side of the load lock rack 211 opposite the side of the load lock rack 211 to which the mainframe power box 213 is coupled.
  • the mainframe controller 218 may be coupled to other portions or sides of the load lock rack 211 .
  • the mainframe controller 218 may be positioned above or below the load lock 209 . Therefore, according to the exemplary configuration shown in FIG. 2 , the load lock 209 and the mainframe controller 218 occupy overlapping floor areas. In this manner, the footprint of the electronic device manufacturing tool 201 is reduced.
  • the position of the mainframe power box 213 and/or the mainframe controller 218 of the inventive electronic device manufacturing tool 201 may allow wiring 220 between the mainframe power box 213 and/or the mainframe controller 218 and other components of the electronic device manufacturing tool 201 to be reduced. More specifically, because of the position of the mainframe power box 213 and/or the mainframe controller 218 , the electronic device manufacturing tool 201 does not require wiring to be run from a separate enclosure to the mainframe 203 in order to couple the mainframe power box 213 and/or the mainframe controller 218 to the mainframe 203 .
  • the wiring 220 between the mainframe power box 213 and/or the mainframe controller 218 and the mainframe 203 may fit compactly within the mainframe footprint. Therefore, in addition to reducing the footprint of the electronic device manufacturing tool, the present methods and apparatus may increase system integration and reduce system complexity.
  • the exemplary electronic device manufacturing tool 201 may be transported (e.g., shipped) more efficiently than the conventional electronic device manufacturing tool 101 . More specifically, conventionally, the mainframe power box 103 and mainframe controller 105 are shipped separately from the load lock 113 of the conventional electronic device manufacturing tool 101 . In contrast, the mainframe power box 213 of the inventive electronic device manufacturing tool 201 may be shipped with the load lock 209 . As described above, the mainframe power box 213 may be adapted to couple to the load lock rack 211 and occupy an overlapping footprint with the load lock 209 .
  • the load lock 209 and the mainframe power box 213 of the inventive electronic device manufacturing tool 201 may be shipped in the same container.
  • the load lock 209 and the mainframe power box 213 of the inventive electronic device manufacturing tool 201 may be shipped in the same container.
  • the mainframe controller 218 may be shipped in the same container as the load lock 209 .
  • a substantial portion e.g., at least 50 percent, and preferably 100 percent
  • the floor area occupied by the mainframe power box 213 and/or the mainframe controller 218 e.g., a second and/or third floor area, respectively
  • the load lock 209 e.g., a first floor area 215 .
  • a substantial portion of the floor area occupied by the mainframe power box 213 and/or the mainframe controller 218 may be within the floor area occupied by another component of the electronic device manufacturing tool 201 .
  • the mainframe power box 213 and/or the mainframe controller 218 may be coupled to another component of the electronic device manufacturing tool 201 or to a support rack of that component.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Supply And Installment Of Electrical Components (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Casings For Electric Apparatus (AREA)
US11/179,037 2004-07-12 2005-07-11 Methods and apparatus for reducing an electronic device manufacturing tool footprint Abandoned US20060104799A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/179,037 US20060104799A1 (en) 2004-07-12 2005-07-11 Methods and apparatus for reducing an electronic device manufacturing tool footprint

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US58711004P 2004-07-12 2004-07-12
US11/179,037 US20060104799A1 (en) 2004-07-12 2005-07-11 Methods and apparatus for reducing an electronic device manufacturing tool footprint

Publications (1)

Publication Number Publication Date
US20060104799A1 true US20060104799A1 (en) 2006-05-18

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Family Applications (1)

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US11/179,037 Abandoned US20060104799A1 (en) 2004-07-12 2005-07-11 Methods and apparatus for reducing an electronic device manufacturing tool footprint

Country Status (5)

Country Link
US (1) US20060104799A1 (ko)
JP (1) JP4567541B2 (ko)
KR (1) KR100648321B1 (ko)
CN (1) CN1802084B (ko)
TW (1) TWI297906B (ko)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6463220B2 (ja) * 2015-05-21 2019-01-30 東京エレクトロン株式会社 処理システム

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5855681A (en) * 1996-11-18 1999-01-05 Applied Materials, Inc. Ultra high throughput wafer vacuum processing system
US6303906B1 (en) * 1999-11-30 2001-10-16 Wafermasters, Inc. Resistively heated single wafer furnace
US20030213560A1 (en) * 2002-05-16 2003-11-20 Yaxin Wang Tandem wafer processing system and process
US20040088145A1 (en) * 2002-11-06 2004-05-06 Rosenthal Richard Edwin Methods and apparatus for designing the racking and wiring configurations for pieces of hardware
US6860965B1 (en) * 2000-06-23 2005-03-01 Novellus Systems, Inc. High throughput architecture for semiconductor processing

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5909994A (en) * 1996-11-18 1999-06-08 Applied Materials, Inc. Vertical dual loadlock chamber
US5838121A (en) * 1996-11-18 1998-11-17 Applied Materials, Inc. Dual blade robot
US6059507A (en) * 1997-04-21 2000-05-09 Brooks Automation, Inc. Substrate processing apparatus with small batch load lock
JP3582330B2 (ja) * 1997-11-14 2004-10-27 東京エレクトロン株式会社 処理装置及びこれを用いた処理システム
JP4316752B2 (ja) * 1999-11-30 2009-08-19 キヤノンアネルバ株式会社 真空搬送処理装置
EP1338028A1 (en) * 2000-12-01 2003-08-27 Wafermasters, Incorporated Wafer processing system including a robot
JP2002343720A (ja) * 2001-05-11 2002-11-29 Hitachi Kokusai Electric Inc 熱処理装置
JP2003017543A (ja) * 2001-06-28 2003-01-17 Hitachi Kokusai Electric Inc 基板処理装置、基板処理方法、半導体装置の製造方法および搬送装置
JP2003092329A (ja) * 2001-09-18 2003-03-28 Hitachi Kokusai Electric Inc 基板処理装置
JP2003133388A (ja) * 2001-10-25 2003-05-09 Ulvac Japan Ltd 基板搬送装置
JP2004119401A (ja) * 2002-09-20 2004-04-15 Foi:Kk 基板処理装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5855681A (en) * 1996-11-18 1999-01-05 Applied Materials, Inc. Ultra high throughput wafer vacuum processing system
US6303906B1 (en) * 1999-11-30 2001-10-16 Wafermasters, Inc. Resistively heated single wafer furnace
US6860965B1 (en) * 2000-06-23 2005-03-01 Novellus Systems, Inc. High throughput architecture for semiconductor processing
US20030213560A1 (en) * 2002-05-16 2003-11-20 Yaxin Wang Tandem wafer processing system and process
US20040088145A1 (en) * 2002-11-06 2004-05-06 Rosenthal Richard Edwin Methods and apparatus for designing the racking and wiring configurations for pieces of hardware

Also Published As

Publication number Publication date
JP2006041509A (ja) 2006-02-09
KR20060050063A (ko) 2006-05-19
KR100648321B1 (ko) 2006-11-23
JP4567541B2 (ja) 2010-10-20
TW200614328A (en) 2006-05-01
TWI297906B (en) 2008-06-11
CN1802084A (zh) 2006-07-12
CN1802084B (zh) 2011-08-10

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AS Assignment

Owner name: APPLIED MATERIALS, INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:JOZWIAK, JANUSZ;REEL/FRAME:016854/0470

Effective date: 20050831

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION