US20050176168A1 - Package structure of optical device and method for manufacturing the same - Google Patents
Package structure of optical device and method for manufacturing the same Download PDFInfo
- Publication number
- US20050176168A1 US20050176168A1 US10/906,095 US90609505A US2005176168A1 US 20050176168 A1 US20050176168 A1 US 20050176168A1 US 90609505 A US90609505 A US 90609505A US 2005176168 A1 US2005176168 A1 US 2005176168A1
- Authority
- US
- United States
- Prior art keywords
- optical device
- wafer
- package structure
- cover
- connection pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 230000003287 optical effect Effects 0.000 title claims abstract description 65
- 238000000034 method Methods 0.000 title claims description 33
- 238000004519 manufacturing process Methods 0.000 title claims description 28
- 239000000758 substrate Substances 0.000 claims abstract description 74
- 239000000565 sealant Substances 0.000 claims abstract description 26
- 239000008393 encapsulating agent Substances 0.000 claims abstract description 10
- 238000005520 cutting process Methods 0.000 claims description 30
- 238000000465 moulding Methods 0.000 claims description 7
- 238000001914 filtration Methods 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 6
- 238000004806 packaging method and process Methods 0.000 claims description 2
- 239000000919 ceramic Substances 0.000 description 6
- 150000001875 compounds Chemical class 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14618—Containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Definitions
- the present invention relates to a package structure of optical semiconductor integrated circuit device. More particularly, the invention relates to a package structure of optical semiconductor integrated circuit device having a cover and a transparent encapsulant.
- the image sensor chip in practical situation is disposed in a package structure.
- the package structure has an opening, which is sealed by a transparent cover, so that the image sensor chip can sense the optical signals.
- the image sensor chip usually is implemented on a ceramic substrate with protruding pins by using a molding layer.
- the molding layer usually needs the curing process, so as to firmly implement the image sensing device on the ceramic substrate. After bonding wire and window sealing, the pins are cut to have a proper length. The final structure is achieved and the package process is accomplished.
- the fabrication process about sealing the window typically uses a work process by distributing or molding, so that the molding compound encloses the image sensing device, which is then implemented on the substrate. After then, a transparent cover is disposed over the molding compound, so as to seal the image sensing device between the substrate and the cover.
- a transparent cover is disposed over the molding compound, so as to seal the image sensing device between the substrate and the cover.
- the U.S. Pat. No. 5,811,799 issued to Wu on Sep. 22, 1998 by a title “Image Sensor Package Having A Wall with A Sealed Cover” has disclosed a package structure of image sensor, in which a pre-molded wall is used to package an image sensor chip on a ceramic substrate.
- the foregoing package structure of the optical device is easily warped, and therefore it needs the ceramic substrate that is rather expansive.
- the invention provides a package structure of optical semiconductor integrated circuit device, so as to reduce the fabrication cost.
- the invention provides a package structure of optical device, including a chip, a sealant, a cover, a substrate, multiple bonding wires, and a transparent encapsulant.
- the chip has an optical device and multiple chip connection pads.
- the sealant is disposed to enclose the optical device.
- the cover is disposed on the sealant.
- the substrate supports the chips and has multiple connection pads.
- the bonding wires are used to electrically connect the chip connection pads of the chip to the connection pads of the substrate.
- the transparent encapsulant is formed over the substrate and the cover, and enclosing the bonding wires.
- the package structure of optical device has a cover, which covers over the optical device of the chip, so that it is helpful to prevent from the moisture and reduce the warpage.
- the package structure of optical device can use a usual substrate in completion without need of the expensive ceramic or bisma-leimide triazine resin as the substrate. As a result, the fabrication cost is greatly reduced.
- FIG. 1 is a cross-sectional view, schematically illustrating a package structure of optical device, according to preferred embodiment of the invention.
- FIG. 2 is a top view, schematically illustrating a package structure of optical device of FIG. 1 , according to preferred embodiment of the invention.
- FIGS. 3-9 are drawings, schematically illustrating the fabrication processes for the package structure of optical device, according to the invention.
- FIG. 1 it is a cross-sectional view, schematically illustrating a package structure of optical device 100 , according to preferred embodiment of the invention.
- the package structure of optical device 100 includes a chip 110 , having an active surface 112 and back surface 114 in opposites side.
- the active surface 112 of the chip 110 has an active zone 116 , having multiple optical devices, such as the optical sensor, used for conversion between the optical signals and the electrical signals.
- a sealant 122 encloses the optical devices 100 and is disposed on the active surface 112 of the chip 110 .
- a cover 120 is disposed on the sealant 122 , and is firmly adhered to the chip 110 by the sealant 122 .
- the sealant 122 is mixed with spacers (not shown in figure), so as to allow the cover 120 to have a fixed gap from the chip 110 .
- the cover 120 can be a simple transparent cover, or a cover 120 that can also provide some optical properties, such as filtering or focusing. In other words, the cover 120 can be a filter plate or a lens.
- the chip 110 can be firmly adhered to a substrate 150 by an adhering layer 142 .
- Multiple chip connection pads 118 are additionally disposed on the active surface 112 of the chip 110 , so as to electrically connect to the first connection pads 156 on the upper surface of the substrate 150 by multiple bonding wires 140 .
- the substrate 150 also has multiple circuit line 152 , so as to electrically connect the first connection pads 156 to the second connection pads 154 on the lower surface of the substrate 150 .
- a transparent encapsulant 130 encloses the chip 110 , the cover 120 , the bonding wires 140 and the upper surface of the substrate 150 .
- the second connection pad 154 can be electrically connected and firmly mounted on an external printed circuit board (not shown) by a surface mounting technology.
- the package structure of optical device 100 has the package structure of land grid array.
- the ordinary skilled artisans can understand that the second connection pad 154 can be easily changed with solder balls or connection pins, so as to form the structures of the ball grid array or pin grid
- FIGS. 3-9 they are the drawings schematically illustrating the fabrication processes for the package structure of optical device 100 , according to an embodiment of the invention.
- a wafer 160 is provided.
- the wafer 160 has multiple chips 110 and multiple first cutting lines 162 , so as to define the chips 110 .
- Each chip 110 has an active zone 116 and multiple chip connection pads 118 , which are disposed around the active zone 116 .
- a sealant 122 is dispensed to each chip 110 by a dispenser (not shown), so as to enclose the active zone 116 .
- the chip connection pads 118 are located at outside of the sealant 122 , as shown in FIG. 4 in detail.
- a cover substrate 170 is disposed over the wafer 160 .
- the cover substrate 170 has multiple covers 120 and multiple second cutting lines 172 , so as to define the covers 120 .
- the cover substrate 170 can be a transparent plate, an optical filtering plate, or can have multiple lenses.
- the sealant 122 can be ultraviolet cure adhesive, mixed with spacers (not shown). After the cover substrate 170 is aligned with the wafer 160 and is disposed over the wafer 160 , the sealant 122 can be cured by the ultraviolet light. As a result, the cover 120 can be adhered onto the chips 110 by a substantially uniform spacing, and a cavity with uniform spacing is formed above the active zone 116 .
- the cutting devices 180 and 182 cut the wafer 160 and the cover substrate 170 along the first and second cutting lines 162 and 172 respectively on the wafer 160 and the cover substrate 170 .
- the wafer 160 and the cover substrate 170 are cut into several singulated pieces, and then the multiple package structures 190 are formed.
- the wafer 160 and the cover substrate 170 are processed to form multiple grooves 184 , 186 .
- the wafer 160 and the cover substrate 170 are broken at the grooves 184 , 186 by a breaking process, and then the package structures 190 are formed as shown in FIG. 7 .
- a substrate strip 192 is provided, in which multiple substrates 150 are included, and are arranged by an array manner.
- the package structures 190 can be respectively adhered to the substrates 150 of the substrate strip 192 by multiple adhering layers 142 .
- the bonding wires 140 are used to electrically connect the chip connection pads 118 of the chip 110 to the first connection pads 156 of the substrates 150 .
- the transparent encapsulant 130 is formed by a transparent molding compound to mold onto the substrate strip 192 , so as to encapsulate the package structure 190 , the bonding wires 140 , and the upper surface of the substrate 150 . After then, the substrate strip 192 is cut and the package structure of optical device 100 is formed.
- the package structure of optical device is a land grid array structure.
- the ordinary skilled artisans can understand that the second connection pads 154 can be easily changed with solder balls or connection pins, so as to form the structures of the ball grid array or pin grid array.
- the package structure of optical device has a cover, covering over the optical device of the chip, whereby it is helpful to avoid the moisture and reduce warpage.
- the package structure of optical device can use a usual substrate without need of expensive ceramic or bisma-leimide triasine resin as the substrate. As a result, the fabrication cost can be greatly reduced. Moreover, since the package structure has no the outer pins, the signal transmitting path is shorter and thereby it has better electric properties.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Light Receiving Elements (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/471,455 US8003426B2 (en) | 2004-02-06 | 2009-05-25 | Method for manufacturing package structure of optical device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW93102847 | 2004-02-06 | ||
TW093102847A TWI324829B (en) | 2004-02-06 | 2004-02-06 | Optical semiconductor package and method for manufacturing the same |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/471,455 Division US8003426B2 (en) | 2004-02-06 | 2009-05-25 | Method for manufacturing package structure of optical device |
Publications (1)
Publication Number | Publication Date |
---|---|
US20050176168A1 true US20050176168A1 (en) | 2005-08-11 |
Family
ID=34825391
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/906,095 Abandoned US20050176168A1 (en) | 2004-02-06 | 2005-02-03 | Package structure of optical device and method for manufacturing the same |
US12/471,455 Active 2025-07-08 US8003426B2 (en) | 2004-02-06 | 2009-05-25 | Method for manufacturing package structure of optical device |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/471,455 Active 2025-07-08 US8003426B2 (en) | 2004-02-06 | 2009-05-25 | Method for manufacturing package structure of optical device |
Country Status (3)
Country | Link |
---|---|
US (2) | US20050176168A1 (ja) |
JP (1) | JP4166759B2 (ja) |
TW (1) | TWI324829B (ja) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040161871A1 (en) * | 2002-11-27 | 2004-08-19 | Seiko Epson Corporation | Semiconductor device, method of manufacturing the same, circuit substrate and electronic equipment |
US20080102552A1 (en) * | 2006-10-30 | 2008-05-01 | Warren Farnworth | Wafer level method of locating focal plane of imager devices |
US20080254558A1 (en) * | 2005-06-01 | 2008-10-16 | Samsung Electro-Mechanics Co., Ltd. | Side-emitting LED package and method of manufacturing the same |
CN102194714A (zh) * | 2010-03-05 | 2011-09-21 | 铜陵三佳科技股份有限公司 | 一种带树脂上料光电检测装置的半导体封装设备 |
US20130203200A1 (en) * | 2010-01-20 | 2013-08-08 | Siliconware Precision Industries Co., Ltd. | Fabrication method of package structure having mems element |
US20220037206A1 (en) * | 2020-07-28 | 2022-02-03 | Socionext Inc. | Method for producing semiconductor device, semiconductor package, and method for producing semiconductor package |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9488779B2 (en) * | 2013-11-11 | 2016-11-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Apparatus and method of forming laser chip package with waveguide for light coupling |
JP6748501B2 (ja) * | 2016-07-14 | 2020-09-02 | ローム株式会社 | 電子部品およびその製造方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US5729437A (en) * | 1994-06-22 | 1998-03-17 | Seiko Epson Corporation | Electronic part including a thin body of molding resin |
US5811799A (en) * | 1997-07-31 | 1998-09-22 | Wu; Liang-Chung | Image sensor package having a wall with a sealed cover |
US7273765B2 (en) * | 2003-04-28 | 2007-09-25 | Matsushita Electric Industrial Co., Ltd. | Solid-state imaging device and method for producing the same |
Family Cites Families (13)
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JPH0724287B2 (ja) * | 1987-02-12 | 1995-03-15 | 三菱電機株式会社 | 光透過用窓を有する半導体装置とその製造方法 |
JP2656336B2 (ja) * | 1989-01-18 | 1997-09-24 | 日東電工株式会社 | 光半導体装置およびそれに用いる光半導体封止用エポキシ樹脂組成物 |
EP0678904A1 (en) * | 1994-04-12 | 1995-10-25 | Lsi Logic Corporation | Multicut wafer saw process |
US5904548A (en) * | 1996-11-21 | 1999-05-18 | Texas Instruments Incorporated | Trench scribe line for decreased chip spacing |
US6271102B1 (en) * | 1998-02-27 | 2001-08-07 | International Business Machines Corporation | Method and system for dicing wafers, and semiconductor structures incorporating the products thereof |
JP3139462B2 (ja) * | 1998-07-17 | 2001-02-26 | 日本電気株式会社 | 有機薄膜elデバイスの製造方法 |
JP2000216413A (ja) * | 1999-01-26 | 2000-08-04 | Apic Yamada Corp | Bga型透明プラスチック半導体パッケ―ジ |
JP2001185657A (ja) * | 1999-12-10 | 2001-07-06 | Amkor Technology Korea Inc | 半導体パッケージ及びその製造方法 |
JP2001308349A (ja) * | 2000-04-14 | 2001-11-02 | Hiroaki Hayashi | フォトセンサチップの組立体およびその製造方法 |
US6518079B2 (en) * | 2000-12-20 | 2003-02-11 | Lumileds Lighting, U.S., Llc | Separation method for gallium nitride devices on lattice-mismatched substrates |
JP3881888B2 (ja) * | 2001-12-27 | 2007-02-14 | セイコーエプソン株式会社 | 光デバイスの製造方法 |
US6818532B2 (en) * | 2002-04-09 | 2004-11-16 | Oriol, Inc. | Method of etching substrates |
US7002241B1 (en) * | 2003-02-12 | 2006-02-21 | National Semiconductor Corporation | Packaging of semiconductor device with a non-opaque cover |
-
2004
- 2004-02-06 TW TW093102847A patent/TWI324829B/zh not_active IP Right Cessation
-
2005
- 2005-02-03 US US10/906,095 patent/US20050176168A1/en not_active Abandoned
- 2005-02-04 JP JP2005029743A patent/JP4166759B2/ja not_active Expired - Fee Related
-
2009
- 2009-05-25 US US12/471,455 patent/US8003426B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5729437A (en) * | 1994-06-22 | 1998-03-17 | Seiko Epson Corporation | Electronic part including a thin body of molding resin |
US5811799A (en) * | 1997-07-31 | 1998-09-22 | Wu; Liang-Chung | Image sensor package having a wall with a sealed cover |
US7273765B2 (en) * | 2003-04-28 | 2007-09-25 | Matsushita Electric Industrial Co., Ltd. | Solid-state imaging device and method for producing the same |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040161871A1 (en) * | 2002-11-27 | 2004-08-19 | Seiko Epson Corporation | Semiconductor device, method of manufacturing the same, circuit substrate and electronic equipment |
US20080254558A1 (en) * | 2005-06-01 | 2008-10-16 | Samsung Electro-Mechanics Co., Ltd. | Side-emitting LED package and method of manufacturing the same |
US7833811B2 (en) * | 2005-06-01 | 2010-11-16 | Samsung Led Co., Ltd. | Side-emitting LED package and method of manufacturing the same |
US20080102552A1 (en) * | 2006-10-30 | 2008-05-01 | Warren Farnworth | Wafer level method of locating focal plane of imager devices |
US7785915B2 (en) * | 2006-10-30 | 2010-08-31 | Aptina Imaging Corporation | Wafer level method of locating focal plane of imager devices |
US20130203200A1 (en) * | 2010-01-20 | 2013-08-08 | Siliconware Precision Industries Co., Ltd. | Fabrication method of package structure having mems element |
US8716070B2 (en) * | 2010-01-20 | 2014-05-06 | Siliconware Precision Industries Co. Ltd. | Fabrication method of package structure having MEMS element |
CN102194714A (zh) * | 2010-03-05 | 2011-09-21 | 铜陵三佳科技股份有限公司 | 一种带树脂上料光电检测装置的半导体封装设备 |
US20220037206A1 (en) * | 2020-07-28 | 2022-02-03 | Socionext Inc. | Method for producing semiconductor device, semiconductor package, and method for producing semiconductor package |
US11621193B2 (en) * | 2020-07-28 | 2023-04-04 | Socionext Inc. | Method for producing semiconductor device, semiconductor package, and method for producing semiconductor package |
US11990373B2 (en) * | 2020-07-28 | 2024-05-21 | Socionext Inc. | Method for producing semiconductor device, semiconductor package, and method for producing semiconductor package |
Also Published As
Publication number | Publication date |
---|---|
TW200527690A (en) | 2005-08-16 |
JP4166759B2 (ja) | 2008-10-15 |
US20090239329A1 (en) | 2009-09-24 |
TWI324829B (en) | 2010-05-11 |
JP2005328028A (ja) | 2005-11-24 |
US8003426B2 (en) | 2011-08-23 |
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