US20050139961A1 - Semiconductor substrate and method for production thereof - Google Patents

Semiconductor substrate and method for production thereof Download PDF

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Publication number
US20050139961A1
US20050139961A1 US11/012,935 US1293504A US2005139961A1 US 20050139961 A1 US20050139961 A1 US 20050139961A1 US 1293504 A US1293504 A US 1293504A US 2005139961 A1 US2005139961 A1 US 2005139961A1
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US
United States
Prior art keywords
layer
germanium
concentration
semiconductor substrate
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/012,935
Other languages
English (en)
Inventor
Josef Brunner
Hiroyuki Deai
Atsushi Ikari
Martin Grassl
Atsuki Matsumura
Wilfried Ammon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siltronic AG
Original Assignee
Siltronic AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siltronic AG filed Critical Siltronic AG
Assigned to SILTRONIC AG reassignment SILTRONIC AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DEAI, HIROYUKI, IKARI, ATSUSHI, MATSUMURA, ATSUKI, BRUNNER, JOSEF, GRASSL, MARTIN, VON AMMON, WILFRIED
Publication of US20050139961A1 publication Critical patent/US20050139961A1/en
Priority to US12/120,285 priority Critical patent/US8043929B2/en
Abandoned legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26533—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02323—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
    • H01L21/02351—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to corpuscular radiation, e.g. exposure to electrons, alpha-particles, protons or ions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
    • H01L21/31658—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
US11/012,935 2003-12-25 2004-12-15 Semiconductor substrate and method for production thereof Abandoned US20050139961A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/120,285 US8043929B2 (en) 2003-12-25 2008-05-14 Semiconductor substrate and method for production thereof

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2003-430323 2003-12-25
JP2003430323 2003-12-25
JP2004314701A JP4700324B2 (ja) 2003-12-25 2004-10-28 半導体基板の製造方法
JP2004-314701 2004-10-28

Related Child Applications (1)

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US12/120,285 Division US8043929B2 (en) 2003-12-25 2008-05-14 Semiconductor substrate and method for production thereof

Publications (1)

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US20050139961A1 true US20050139961A1 (en) 2005-06-30

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US12/120,285 Expired - Fee Related US8043929B2 (en) 2003-12-25 2008-05-14 Semiconductor substrate and method for production thereof

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Country Status (6)

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US (2) US20050139961A1 (zh)
EP (1) EP1553624A1 (zh)
JP (1) JP4700324B2 (zh)
KR (1) KR100729372B1 (zh)
CN (1) CN1638133B (zh)
TW (1) TWI295502B (zh)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060281234A1 (en) * 2005-06-13 2006-12-14 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US20070212859A1 (en) * 2006-03-08 2007-09-13 Paul Carey Method of thermal processing structures formed on a substrate
WO2007103643A2 (en) * 2006-03-08 2007-09-13 Applied Materials, Inc. Method and apparatus for thermal processing structures formed on a substrate
US20070224774A1 (en) * 2006-03-27 2007-09-27 Sumco Corporation Method of producing SIMOX wafer
US20080025354A1 (en) * 2006-07-31 2008-01-31 Dean Jennings Ultra-Fast Beam Dithering with Surface Acoustic Wave Modulator
US7548364B2 (en) 2006-07-31 2009-06-16 Applied Materials, Inc. Ultra-fast beam dithering with surface acoustic wave modulator
US20100221883A1 (en) * 2009-02-27 2010-09-02 Stephan Kronholz Adjusting of a non-silicon fraction in a semiconductor alloy during transistor fabrication by an intermediate oxidation process
WO2016100373A1 (en) * 2014-12-15 2016-06-23 Stratio, Inc. Reduction of surface roughness in epitaxially grown germanium by controlled thermal oxidation

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2893446B1 (fr) * 2005-11-16 2008-02-15 Soitec Silicon Insulator Techn TRAITEMENT DE COUCHE DE SiGe POUR GRAVURE SELECTIVE
CN104752433A (zh) * 2013-12-30 2015-07-01 中芯国际集成电路制造(上海)有限公司 非易失性存储单元及其形成方法
CN103887149B (zh) * 2014-03-20 2017-01-04 上海华力微电子有限公司 一种降低镍管道缺陷的方法

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4975387A (en) * 1989-12-15 1990-12-04 The United States Of America As Represented By The Secretary Of The Navy Formation of epitaxial si-ge heterostructures by solid phase epitaxy
US6039803A (en) * 1996-06-28 2000-03-21 Massachusetts Institute Of Technology Utilization of miscut substrates to improve relaxed graded silicon-germanium and germanium layers on silicon
US20010048119A1 (en) * 2000-03-17 2001-12-06 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US20020022348A1 (en) * 1998-07-08 2002-02-21 Kiyofumi Sakaguchi Semiconductor substrate and production method thereof
US20030139000A1 (en) * 2002-01-23 2003-07-24 International Business Machines Corporation Method of creating high-quality relaxed SiGe-on-insulator for strained Si CMOS applications
US20030218189A1 (en) * 2001-06-12 2003-11-27 International Business Machines Corporation Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
US20040002200A1 (en) * 2002-06-28 2004-01-01 Koveshnikov Sergei V. Method of producing an SOI wafer
US20050003633A1 (en) * 2003-07-02 2005-01-06 Texas Instruments Incorporated Method for reducing stress concentrations on a semiconductor wafer by surface laser treatment
US6905771B2 (en) * 2002-11-11 2005-06-14 Sumitomo Mitsubishi Silicon Corporation Silicon wafer

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3376211B2 (ja) * 1996-05-29 2003-02-10 株式会社東芝 半導体装置、半導体基板の製造方法及び半導体装置の製造方法
JP3712599B2 (ja) * 2000-08-25 2005-11-02 株式会社東芝 半導体装置及び半導体基板
US6524935B1 (en) * 2000-09-29 2003-02-25 International Business Machines Corporation Preparation of strained Si/SiGe on insulator by hydrogen induced layer transfer technique
US6890835B1 (en) * 2000-10-19 2005-05-10 International Business Machines Corporation Layer transfer of low defect SiGe using an etch-back process

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4975387A (en) * 1989-12-15 1990-12-04 The United States Of America As Represented By The Secretary Of The Navy Formation of epitaxial si-ge heterostructures by solid phase epitaxy
US6039803A (en) * 1996-06-28 2000-03-21 Massachusetts Institute Of Technology Utilization of miscut substrates to improve relaxed graded silicon-germanium and germanium layers on silicon
US20020022348A1 (en) * 1998-07-08 2002-02-21 Kiyofumi Sakaguchi Semiconductor substrate and production method thereof
US20010048119A1 (en) * 2000-03-17 2001-12-06 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US20030218189A1 (en) * 2001-06-12 2003-11-27 International Business Machines Corporation Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
US20030139000A1 (en) * 2002-01-23 2003-07-24 International Business Machines Corporation Method of creating high-quality relaxed SiGe-on-insulator for strained Si CMOS applications
US20040002200A1 (en) * 2002-06-28 2004-01-01 Koveshnikov Sergei V. Method of producing an SOI wafer
US6905771B2 (en) * 2002-11-11 2005-06-14 Sumitomo Mitsubishi Silicon Corporation Silicon wafer
US20050003633A1 (en) * 2003-07-02 2005-01-06 Texas Instruments Incorporated Method for reducing stress concentrations on a semiconductor wafer by surface laser treatment

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060281234A1 (en) * 2005-06-13 2006-12-14 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US7759228B2 (en) * 2005-06-13 2010-07-20 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US20100323532A1 (en) * 2006-03-08 2010-12-23 Paul Carey Method of thermal processing structures formed on a substrate
US20070212859A1 (en) * 2006-03-08 2007-09-13 Paul Carey Method of thermal processing structures formed on a substrate
WO2007103643A2 (en) * 2006-03-08 2007-09-13 Applied Materials, Inc. Method and apparatus for thermal processing structures formed on a substrate
US20070218644A1 (en) * 2006-03-08 2007-09-20 Applied Materials, Inc. Method of thermal processing structures formed on a substrate
US20070221640A1 (en) * 2006-03-08 2007-09-27 Dean Jennings Apparatus for thermal processing structures formed on a substrate
US10840100B2 (en) 2006-03-08 2020-11-17 Applied Materials, Inc. Method of thermal processing structures formed on a substrate
WO2007103643A3 (en) * 2006-03-08 2008-05-08 Applied Materials Inc Method and apparatus for thermal processing structures formed on a substrate
US10141191B2 (en) 2006-03-08 2018-11-27 Applied Materials, Inc. Method of thermal processing structures formed on a substrate
US8518838B2 (en) 2006-03-08 2013-08-27 Applied Materials, Inc. Method of thermal processing structures formed on a substrate
US7569463B2 (en) 2006-03-08 2009-08-04 Applied Materials, Inc. Method of thermal processing structures formed on a substrate
US20070224774A1 (en) * 2006-03-27 2007-09-27 Sumco Corporation Method of producing SIMOX wafer
US7550371B2 (en) * 2006-03-27 2009-06-23 Sumco Corporation Method of producing SIMOX wafer
US7548364B2 (en) 2006-07-31 2009-06-16 Applied Materials, Inc. Ultra-fast beam dithering with surface acoustic wave modulator
US20080025354A1 (en) * 2006-07-31 2008-01-31 Dean Jennings Ultra-Fast Beam Dithering with Surface Acoustic Wave Modulator
US20100221883A1 (en) * 2009-02-27 2010-09-02 Stephan Kronholz Adjusting of a non-silicon fraction in a semiconductor alloy during transistor fabrication by an intermediate oxidation process
US8735253B2 (en) * 2009-02-27 2014-05-27 Globalfoundries Inc. Adjusting of a non-silicon fraction in a semiconductor alloy during transistor fabrication by an intermediate oxidation process
WO2016100373A1 (en) * 2014-12-15 2016-06-23 Stratio, Inc. Reduction of surface roughness in epitaxially grown germanium by controlled thermal oxidation
US10600640B2 (en) 2014-12-15 2020-03-24 Stratio, Inc. Reduction of surface roughness in epitaxially grown germanium by controlled thermal oxidation

Also Published As

Publication number Publication date
TWI295502B (en) 2008-04-01
US8043929B2 (en) 2011-10-25
CN1638133A (zh) 2005-07-13
KR100729372B1 (ko) 2007-06-15
KR20050065435A (ko) 2005-06-29
US20080268613A1 (en) 2008-10-30
TW200524146A (en) 2005-07-16
EP1553624A1 (en) 2005-07-13
CN1638133B (zh) 2010-05-26
JP2005210071A (ja) 2005-08-04
JP4700324B2 (ja) 2011-06-15

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