US20040054877A1 - Method and apparatus for shuffling data - Google Patents

Method and apparatus for shuffling data Download PDF

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Publication number
US20040054877A1
US20040054877A1 US10/611,344 US61134403A US2004054877A1 US 20040054877 A1 US20040054877 A1 US 20040054877A1 US 61134403 A US61134403 A US 61134403A US 2004054877 A1 US2004054877 A1 US 2004054877A1
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United States
Prior art keywords
data
operand
shuffle
data element
resultant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/611,344
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English (en)
Inventor
William Macy
Eric Debes
Patrice Roussel
Huy Nguyen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
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Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/952,891 external-priority patent/US7085795B2/en
Priority to US10/611,344 priority Critical patent/US20040054877A1/en
Application filed by Intel Corp filed Critical Intel Corp
Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DEBES, ERIC L., MACY, WILLIAM W. JR., NGUYEN, HUY V., ROUSSEL, PATRICE L.
Publication of US20040054877A1 publication Critical patent/US20040054877A1/en
Priority to CNB2004800184438A priority patent/CN100492278C/zh
Priority to CN200910130582.4A priority patent/CN101620525B/zh
Priority to AT04756204T priority patent/ATE442624T1/de
Priority to JP2006515370A priority patent/JP4607105B2/ja
Priority to KR20057025313A priority patent/KR100831472B1/ko
Priority to EP04756204A priority patent/EP1639452B1/en
Priority to PCT/US2004/020601 priority patent/WO2005006183A2/en
Priority to RU2006102503A priority patent/RU2316808C2/ru
Priority to DE602004023081T priority patent/DE602004023081D1/de
Priority to TW93118830A priority patent/TWI270007B/zh
Priority to HK06105784.3A priority patent/HK1083657A1/xx
Priority to US12/387,958 priority patent/US8214626B2/en
Priority to JP2010180413A priority patent/JP5490645B2/ja
Priority to US12/901,336 priority patent/US8225075B2/en
Priority to JP2011045001A priority patent/JP5535965B2/ja
Priority to US13/540,576 priority patent/US9477472B2/en
Priority to US13/608,953 priority patent/US8688959B2/en
Priority to JP2013115254A priority patent/JP5567181B2/ja
Priority to US14/586,581 priority patent/US9229719B2/en
Priority to US14/586,558 priority patent/US9229718B2/en
Priority to US15/299,914 priority patent/US10152323B2/en
Abandoned legal-status Critical Current

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Definitions

  • the present invention relates generally to the field of microprocessors and computer systems. More particularly, the present invention relates to a method and apparatus for shuffling data.
  • FIG. 1A is a block diagram of a computer system formed with a processor that includes execution units to execute an instruction for shuffling data in accordance with one embodiment of the present invention
  • FIG. 1C is a block diagram of yet another exemplary computer system in accordance with another alternative embodiment of the present invention.
  • FIG. 2 is a block diagram of the micro-architecture for a processor of one embodiment that includes logic circuits to perform data shuffle operations in accordance with the present invention
  • FIGS. 3 A-C are illustrations of shuffle masks according to various embodiments of the present invention.
  • FIG. 4A is an illustration of various packed data type representations in multimedia registers according to one embodiment of the present invention.
  • FIG. 4B illustrates packed data-types in accordance with an alternative embodiment
  • FIG. 4C illustrates one embodiment of an operation encoding (opcode) format for a shuffle instruction
  • FIG. 4D illustrates an alternative operation encoding format
  • FIG. 4E illustrates yet another alternative operation encoding format
  • FIG. 5 is a block diagram of one embodiment of logic to perform a shuffle operation on a data operand based on a shuffle mask in accordance with the present invention
  • FIG. 6 is a block diagram of one embodiment of a circuit for performing a data shuffling operation in accordance with the present invention
  • FIG. 7 illustrates the operation of a data shuffle on byte wide data elements in accordance with one embodiment of the present invention
  • FIG. 8 illustrates the operation of a data shuffle operation on word wide data elements in accordance with another embodiment of the present invention
  • FIGS. 10 A-H illustrate the operation of a parallel table lookup algorithm using SIMD instructions
  • the methods of the present invention are embodied in machine-executable instructions.
  • the instructions can be used to cause a general-purpose or special-purpose processor that is programmed with the instructions to perform the steps of the present invention.
  • the steps of the present invention might be performed by specific hardware components that contain hardwired logic for performing the steps, or by any combination of programmed computer components and custom hardware components.
  • the present invention may be provided as a computer program product or software which may include a machine or computer-readable medium having stored thereon instructions which may be used to program a computer (or other electronic devices) to perform a process according to the present invention.
  • Such software can be stored within a memory in the system.
  • the code can be distributed via a network or by way of other computer readable media.
  • a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), but is not limited to, floppy diskettes, optical disks, Compact Disc, Read-Only Memory (CD-ROMs), and magneto-optical disks, Read-Only Memory (ROMs), Random Access Memory (RAM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), magnetic or optical cards, flash memory, a transmission over the Internet, electrical, optical, acoustical or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.) or the like.
  • a machine e.g., a computer
  • ROMs Read-Only Memory
  • RAM Random Access Memory
  • EPROM Erasable Programmable Read-Only Memory
  • EEPROM Electrically Erasable Programmable Read-Only Memory
  • embodiments of integrated circuit designs in accordance with the present inventions can be communicated or transferred in electronic form as a database on a tape or other machine readable media.
  • the electronic form of an integrated circuit design of a processor in one embodiment can be processed or manufactured via a fab to obtain a computer component.
  • an integrated circuit design in electronic form can be processed by a machine to simulate a computer component.
  • the circuit layout plans and/or designs of processors in some embodiments can be distributed via machine readable mediums or embodied thereon for fabrication into a circuit or for simulation of an integrated circuit which, when processed by a machine, simulates a processor.
  • a machine readable medium is also capable of storing data representing predetermined functions in accordance with the present invention in other embodiments.
  • SIMD Single Instruction, Multiple Data
  • SSE Streaming SIMD Extensions
  • the mnemonic for the one implementation is “PSHUFB register 1 , register 2 / memory”, wherein the first and second operands are SIMD registers.
  • the register of the second operand can also be replaced with a memory location.
  • the first operand includes the source data for shuffling.
  • the register for the first operand is also the destination register.
  • Embodiments in accordance to the present invention also include a capability of setting selected bytes to zero in addition to changing their position.
  • the second operand includes the set of shuffle control mask bytes to designate the shuffle pattern.
  • the number of bits used to select a source data element is log 2 of the number of data elements in the source operand. For instance, the number of bytes in a 128 bit register embodiment is sixteen. The log 2 of sixteen is four. Thus four bits, or a nibble, is needed.
  • the [ 3 : 0 ] index in the code below refers to the four bits. If the most significant bit (MSB), bit 7 in this embodiment, of the shuffle control byte is set, a constant zero is written in the result byte.
  • MSB most significant bit
  • FIG. 1A is a block diagram of an exemplary computer system formed with a processor that includes execution units to execute an instruction for shuffling data in accordance with one embodiment of the present invention.
  • System 100 includes a component, such as a processor 102 to employ execution units including logic to perform algorithms for shuffling data, in accordance with the present invention, such as in the embodiment described herein.
  • System 100 is representative of processing systems based on the PENTIUM® III, PENTIUM® 4 , Celeron®, XeonTM, Itanium®, XScaleTM and/or StrongARMTM microprocessors available from Intel Corporation of Santa Clara, Calif., although other systems (including PCs having other microprocessors, engineering workstations, set-top boxes and the like) may also be used.
  • sample system 100 may execute a version of the WINDOWSTM operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (UNIX and Linux for example), embedded software, and/or graphical user interfaces, may also be used.
  • the present invention is not limited to any specific combination of hardware circuitry and software.
  • the present enhancement is not limited to computer systems.
  • Alternative embodiments of the present invention can be used in other devices such as handheld devices and embedded applications.
  • Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs.
  • Embedded applications can include a micro controller, a digital signal processor (DSP), system on a chip, network computers (NetPC), set-top boxes, network hubs, wide area network (WAN) switches, or any other system that performs integer shuffle operations on operands.
  • DSP digital signal processor
  • NetPC network computers
  • Set-top boxes network hubs
  • WAN wide area network
  • some architectures have been implemented to enable instructions to operate on several data simultaneously to improve the efficiency of multimedia applications. As the type and volume of data increases, computers and their processors have to be enhanced to manipulate data in more efficient methods.
  • FIG. 1A is a block diagram of a computer system 100 formed with a processor 102 that includes one or more execution units 108 to perform a data shuffle algorithm in accordance with the present invention.
  • the present embodiment is described in the context of a single processor desktop or server system, but alternative embodiments can be included in a multiprocessor system.
  • System 100 is an example of a hub architecture.
  • the computer system 100 includes a processor 102 to process data signals.
  • the processor 102 can be a complex instruction set computer (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor, for example.
  • the processor 102 is coupled to a processor bus 110 that can transmit data signals between the processor 102 and other components in the system 100 .
  • the elements of system 100 perform their conventional functions that are well known to those familiar with the art.
  • the processor 102 includes a Level 1 (L 1 ) internal cache memory 104 .
  • the processor 102 can have a single internal cache or multiple levels of internal cache.
  • the cache memory can reside external to the processor 102 .
  • Other embodiments can also include a combination of both internal and external caches depending on the particular implementation and needs.
  • Register file 106 can store different types of data in various registers including integer registers, floating point registers, status registers, and instruction pointer register.
  • Execution unit 108 including logic to perform integer and floating point operations, also resides in the processor 102 .
  • the processor 102 also includes a microcode (ucode) ROM that stores microcode for certain macroinstructions.
  • execution unit 108 includes logic to handle a packed instruction set 109 .
  • the packed instruction set 109 includes a packed shuffle instruction for organizing data.
  • System 100 includes a memory 120 .
  • Memory 120 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, flash memory device, or other memory device.
  • DRAM dynamic random access memory
  • SRAM static random access memory
  • Memory 120 can store instructions and/or data represented by data signals that can be executed by the processor 102 .
  • a system logic chip 116 is coupled to the processor bus 110 and memory 120 .
  • the system logic chip 116 in the illustrated embodiment is a memory controller hub (MCH).
  • the processor 102 can communicate to the MCH 116 via a processor bus 110 .
  • the MCH 116 provides a high bandwidth memory path 118 to memory 120 for instruction and data storage and for storage of graphics commands, data and textures.
  • the MCH 116 is to direct data signals between the processor 102 , memory 120 , and other components in the system 100 and to bridge the data signals between processor bus 110 , memory 120 , and system I/O 122 .
  • the system logic chip 116 can provide a graphics port for coupling to a graphics controller 112 .
  • the MCH 116 is coupled to memory 120 through a memory interface 118 .
  • the graphics card 112 is coupled to the MCH 116 through an Accelerated Graphics Port (AGP) interconnect 114 .
  • AGP Accelerated Graphics Port
  • System 100 uses a proprietary hub interface bus 122 to couple the MCH 116 to the I/O controller hub (ICH) 130 .
  • the ICH 130 provides direct connections to some I/O devices via a local I/O bus.
  • the local I/O bus is a high-speed I/O bus for connecting peripherals to the memory 120 , chipset, and processor 102 .
  • Some examples are the audio controller, firmware hub (flash BIOS) 128 , wireless transceiver 126 , data storage 124 , legacy I/O controller containing user input and keyboard interfaces, a serial expansion port such as Universal Serial Bus (USB), and a network controller 134 .
  • the data storage device 124 can comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.
  • FIG. 1B illustrates an alternative embodiment of a data processing system 140 which implements the principles of the present invention.
  • data processing system 140 is an Intel® Personal Internet Client Architecture (Intel® PCA) applications processors with Intel XScaleTM technology (as described on the world-wide web at developer.intel.com). It will be readily appreciated by one of skill in the art that the embodiments described herein can be used with alternative processing systems without departure from the scope of the invention.
  • Intel® PCA Intel® Personal Internet Client Architecture
  • Computer system 140 comprises a processing core 159 capable of performing SIMD operations including a shuffle.
  • processing core 159 represents a processing unit of any type of architecture, including but not limited to a CISC, a RISC or a VLIW type architecture.
  • Processing core 159 may also be suitable for manufacture in one or more process technologies and by being represented on a machine readable media in sufficient detail, may be suitable to facilitate said manufacture.
  • Processing core 159 comprises an execution unit 142 , a set of register file(s) 145 , and a decoder 144 .
  • Processing core 159 also includes additional circuitry (not shown) which is not necessary to the understanding of the present invention.
  • Execution unit 142 is used for executing instructions received by processing core 159 .
  • execution unit 142 can recognize instructions in packed instruction set 143 for performing operations on packed data formats.
  • Packed instruction set 143 includes instructions for supporting shuffle operations, and may also include other packed instructions.
  • Execution unit 142 is coupled to register file 145 by an internal bus.
  • Register file 145 represents a storage area on processing core 159 for storing information, including data.
  • Execution unit 142 is coupled to decoder 144 .
  • Decoder 144 is used for decoding instructions received by processing core 159 into control signals and/or microcode entry points. In response to these control signals and/or microcode entry points, execution unit 142 performs the appropriate operations.
  • FIG. 1C illustrates yet alternative embodiments of a data processing system capable of performing SIMD shuffle operations.
  • data processing system 160 may include a main processor 166 , a SIMD coprocessor 161 , a cache memory 167 , and an input/output system 168 .
  • the input/output system 168 may optionally be coupled to a wireless interface 169 .
  • SIMD coprocessor 161 is capable of performing SIMD operations including data shuffles.
  • Processing core 170 may be suitable for manufacture in one or more process technologies and by being represented on a machine readable media in sufficient detail, may be suitable to facilitate the manufacture of all or part of data processing system 160 including processing core 170 .
  • the main processor 166 executes a stream of data processing instructions that control data processing operations of a general type including interactions with the cache memory 167 , and the input/output system 168 .
  • Embedded within the stream of data processing instructions are SIMD coprocessor instructions.
  • the decoder 165 of main processor 166 recognizes these SIMD coprocessor instructions as being of a type that should be executed by an attached SIMD coprocessor 161 . Accordingly, the main processor 166 issues these SIMD coprocessor instructions (or control signals representing SIMD coprocessor instructions) on the coprocessor bus 166 where from they are received by any attached SIMD coprocessors. In this case, the SIMD coprocessor 161 will accept and execute any received SIMD coprocessor instructions intended for it.
  • processing core 170 main processor 166 , and a SIMD coprocessor 161 are integrated into a single processing core 170 comprising an execution unit 162 , a set of register file(s) 164 , and a decoder 165 to recognize instructions of instruction set 163 including SIMD shuffle instructions.
  • micro-instructions are converted into a single micro-op, and others need several micro-ops to complete the full operation.
  • the decoder 228 accesses the microcode ROM 232 to do the macro-instruction.
  • a packed shuffle instruction can be decoded into a small number of micro ops for processing at the instruction decoder 228 .
  • an instruction for a packed data shuffle algorithm can be stored within the microcode ROM 232 should a number of micro-ops be needed to accomplish the operation.
  • the trace cache 230 refers to a entry point programmable logic array (PLA) to determine a correct micro-instruction pointer for reading the micro-code sequences for the shuffle algorithms in the micro-code ROM 232 .
  • PLA programmable logic array
  • Some SIMD and other multimedia types of instructions are considered complex instructions. Most floating point related instructions are also complex instructions. As such, when the instruction decoder 228 encounters a complex macro-instruction, the microcode ROM 232 is accessed at the appropriate location to retrieve the microcode sequence for that macro-instruction. The various micro-ops needed for performing that macro-instruction are communicated to the out-of-order execution engine 203 for execution at the appropriate integer and floating point execution units.
  • the out-of-order execution engine 203 is where the micro-instructions are prepared for execution.
  • the out-of-order execution logic has a number of buffers to smooth out and re-order the flow of micro-instructions to optimize performance as they go down the pipeline and get scheduled for execution.
  • the allocator logic allocates the machine buffers and resources that each uop needs in order to execute.
  • the register renaming logic renames logic registers onto entries in a register file.
  • the allocator also allocates an entry for each uop in one of the two uop queues, one for memory operations and one for non-memory operations, in front of the instruction schedulers: memory scheduler, fast scheduler 202 , slow/general floating point scheduler 204 , and simple floating point scheduler 206 .
  • the uop schedulers 202 , 204 , 206 determine when a uop is ready to execute based on the readiness of their dependent input register operand sources and the availability of the execution resources the uops need to complete their operation.
  • the fast scheduler 202 of this embodiment can schedule on each half of the main clock cycle while the other schedulers can only schedule once per main processor clock cycle.
  • the schedulers arbitrate for the dispatch ports to schedule uops for execution.
  • Register files 208 , 210 sit between the schedulers 202 , 204 , 206 , and the execution units 212 , 214 , 216 , 218 , 220 , 222 , 224 in the execution block 211 .
  • Each register file 208 , 210 of this embodiment also includes a bypass network that can bypass or forward just completed results that have not yet been written into the register file to new dependent uops.
  • the integer register file 208 and the floating point register file 210 are also capable of communicating data with the other.
  • the integer register file 208 is split into two separate register files, one register file for the low order 32 bits of data and a second register file for the high order 32 bits of data.
  • the floating point register file 210 of one embodiment has 128 bit wide entries because floating point instructions typically have operands from 64 to 128 bits in width.
  • data element 312 used to describe the contents of an example shuffle mask for one embodiment.
  • the shuffle mask 318 for one embodiment is comprised of three portions: a ‘set to zero flag’ field 315 , a ‘reserved’ field 316 , and a ‘selections bits’ field 317 .
  • the ‘set to zero flag’ field 315 is to indicate whether the resultant data element position designated by the present mask should be zeroed out, or in other words, replaced with a value of zero (‘0’).
  • the mask 318 of data element 312 corresponds to the second leftmost data element position. If the selection bits 317 of this mask 318 contain a value of ‘X’, the data element from data element position ‘X’ in the source data operand is shuffled into the second leftmost data element position in the resultant. But if the ‘set to zero flag’ field 315 is set, the second leftmost data element position in the resultant is replaced with ‘0’ and the designation of the selection bits 317 ignored.
  • FIG. 3C illustrates the structure of a mask 338 for another embodiment that operates with byte size data elements and 128 bit wide packed operands, but with multiple data element sources.
  • the mask 338 is comprised of a ‘set to zero’ field 335 , a ‘source (src) select’ field 336 , and a ‘selection’ field 337 .
  • the ‘set to zero’ field 335 and ‘selection’ field 337 function similar to the descriptions above.
  • the ‘source select’ field 336 of this embodiment is to indicate from which data source the data operand specified by the selection bits should be obtained.
  • the same set of masks may be used with multiple data sources such as a plurality of multimedia registers.
  • destination operand identifier 476 is the same as source operand identifier 474 .
  • destination operand identifier 476 is the same as source operand identifier 475 . Therefore, for embodiments of shuffle operations, one of the source operands identified by source operand identifiers 474 and 475 is overwritten by the results of the shuffle operations.
  • Opcode formats 460 and 470 allow register to register, memory to register, register by memory, register by register, register by immediate, register to memory addressing specified in part by MOD fields 463 and 473 and by optional scale-index-base and displacement bytes.
  • sIMED single instruction multiple data
  • CDP coprocessor data processing
  • Operation encoding (opcode) format 480 depicts one such CDP instruction having CDP opcode fields 482 and 489 .
  • the type of CDP instruction for alternative embodiments of shuffle operations, may be encoded by one or more of fields 483 , 484 , 487 , and 488 . Up to three operand locations per instruction may be identified, including up to two source operand identifiers 485 and 490 and one destination operand identifier 486 .
  • One embodiment of the coprocessor can operate on 8, 16, 32, and 64 bit values.
  • the shuffle operation is performed on fixed-point or integer data elements.
  • a shuffle instruction may be executed conditionally, using condition field 481 .
  • source data sizes may be encoded by field 483 .
  • Zero (Z), negative (N), carry (C), and overflow (V) detection can be done on SIMD fields.
  • the type of saturation may be encoded by field 484 .
  • FIG. 5 is a block diagram of one embodiment of logic to perform a shuffle operation on a data operand based on a shuffle mask in accordance with the present invention.
  • the instruction (PSHUFB) for shuffle operation with a set to zero capability of this embodiment begins with two pieces of information a first (mask) operand 510 and a second (data) operand 520 .
  • MASK, DATA, and RESULTANT are generally referred to as operands or data blocks, but not restricted as such, and also include registers, register files, and memory locations.
  • the shuffle PSHUFB instruction is decoded into one micro-operation.
  • the instruction may be decoded into a various number of micro-ops to perform the shuffle operation on the data operands.
  • the operands 510 , 520 are 128 bit wide pieces of information stored in a source register/memory having byte wide data elements.
  • the operands 510 , 520 are held in 128 bit long SIMD registers, such as 128 bit SSE 2 XMM registers.
  • the RESULTANT 540 is also a MMX or XMM data register.
  • RESULTANT 540 may also be the same register or memory location as one of the source operands.
  • the operands and registers can be other widths such as 32, 64, and 256 bits, and have word, doubleword, or quadword sized data elements.
  • the first operand 510 in this example is comprised of a set of sixteen masks (in hexadecimal format): 0x0E, 0x0A, 0x09, 0x8F, 0x02, 0x0E, 0x06, 0x06, 0x06, 0xF0, 0x04, 0x08, 0x08, 0x06, 0x0D, and 0x00.
  • Each individual mask is to specify the contents of its corresponding data element position in the resultant 540 .
  • the second operand 520 is comprised of sixteen data segments: P, O, N, M, L, K, J, I, H, G, F, E, D, C, B, and A. Each data segment in the second operand 520 is also labeled with a data element position value in hex format.
  • the data segments here are of equal length and each comprise of a single byte (8 bits) of data. If each data element was a word (16 bits), doubleword (32 bits), or a quadword (64 bits), the 128 bit operands would have eight word wide, four doubleword wide, or two quadword wide data elements, respectively.
  • another embodiment of the present invention can operate with other sizes of operands and data segments. Embodiments of the present invention are not restricted to particular length data operands, data segments, or shift counts, and can be sized appropriately for each implementation.
  • the operands 510 , 520 can reside either in a register or a memory location or a register file or a mix.
  • the data operands 510 , 520 are sent to the shuffle logic 530 of an execution unit in the processor along with a shuffle instruction.
  • the shuffle instruction can be in the form of a micro operation (uop) or some other decoded format.
  • the two data operands 510 , 520 are received at shuffle logic 530 .
  • the shuffle logic 530 selects data elements from the source data operand 520 based on the values in the mask operand 510 and arranges/shuffles the selected data elements into the appropriate positions in the resultant 540 .
  • the shuffle logic 530 also zeroes out the given data element positions in the resultant 540 as specified.
  • the resultant 540 is comprised of sixteen data segments: O, K, J, ‘0’, C, O, G, G, F, ‘0’, E, I, I, G, N, and A.
  • the mask at the second leftmost data element position in the mask operand 510 is 0x0A.
  • the shuffle logic 530 interprets the mask for that position. This selection field has a hex value of ‘A’.
  • the shuffle logic 530 copies the data, K, in the data element position ‘0xA’ of the data operand 520 to the second leftmost data element position of the resultant 540 .
  • the shuffle logic 530 of this embodiment also supports the flush to zero function of the shuffle instruction.
  • the shuffle mask at the fourth data element position from the left for the mask operand 510 is 0x8F.
  • the shuffle logic 510 recognizes that the ‘set to zero’ field is set as indicated by a ‘1’ at bit 8 of the mask.
  • the flush to zero directive trumps the selection field and the shuffle logic 510 ignores the hex value ‘F’ in the selection field of that mask.
  • a ‘0’ is placed in the corresponding fourth data element position from the left in the resultant 540 .
  • each shuffle mask can be used to designate the content of a single data element position in the resultant.
  • each individual byte wide shuffle mask corresponds to a byte wide data element position in the resultant 540 .
  • combinations of multiple masks can be used to designate blocks of data elements together.
  • two byte wide masks can be used together to designate a word wide data element.
  • Shuffle masks are not restricted to being byte wide and can be any other size needed in that particular implementation.
  • data elements and data element positions can possess other granularities other than bytes.
  • FIG. 6 is a block diagram of one embodiment of a circuit 600 for performing a data shuffling operation in accordance with the present invention.
  • the circuit of this embodiment comprises a multiplexing structure to select the correct result byte from the first source operand based on decoding shuffle mask of the second operand.
  • the source data operand here is comprised of the upper packed data elements and the lower packed data elements.
  • the multiplexing structure of this embodiment is relatively simpler than other multiplexing structures used to implement other packed instructions. As a result, the multiplexing structure of this embodiment does not introduce any new critical timing path.
  • the circuit 600 of this embodiment includes a shuffle mask block, blocks to hold lower/upper packed data elements from source operands, a first plurality of eight to one (8:1) muxes for initial selection of data elements, another plurality of three to one (3:1) muxes for selection of upper and lower data elements, mux select & zero logic and a multitude of control signals.
  • a limited number of the 8:1 and 3:1 muxes are shown in FIG. 6 and represented by dots. However, their function is similar to those illustrated and can be understood from the description below.
  • shuffle handling circuit 600 two operands are received at this shuffle handling circuit 600 : a first operand with a set of packed data elements and a second operand with a set of shuffle masks.
  • the shuffle masks are propagated to shuffle mask block 602 .
  • the set of shuffle masks are decoded at the mux select and zero logic block 604 to generate a variety of select signals (SELECT A 606 , SELECT B 608 , SELECT C 610 ) and a set to zero signal (ZERO) 611 . These signals are used to control the operation of the muxes in piecing together the resultant 632 .
  • the mask operand and data operand are both 128 bits long and each are packed with of sixteen byte size data segments.
  • the value N as shown on various signals is sixteen in this case.
  • the data elements are separated into a set of lower and upper packed data elements, each set having eight data elements. This allows for the use of smaller 8 : 1 muxes during the data element selection rather than 16:1 muxes.
  • These lower and upper sets of packed data elements are held at lower and upper storage areas 612 , 622 , respectively.
  • each of the eight data elements are sent to the first set of sixteen individual 8:1 muxes 618 A-D via a set of lines such as routing lines 614 .
  • Each of the sixteen 8:1 muxes 618 A-D are controlled with one of the N SELECT A signals 606 . Depending on the value of its SELECT A 606 , that mux is to output one of the eight lower data elements 614 for further processing.
  • Each of the sixteen 8:1 muxes is for one of the sixteen resultant data element positions.
  • sixteen 8:1 muxes are present for the upper packed data elements. The eight upper data elements are sent to each of the second set of sixteen 8:1 muxes 624 A-D.
  • Each of the sixteen 3:1 muxes 628 A-D corresponds to a data element position in the resultant 632 .
  • the sixteen outputs 620 A-D from the sixteen lower data muxes 618 A-D are routed to a set of sixteen 3:1 upper/lower selection muxes 628 A-D as are the outputs 626 A-D from the upper data muxes 624 A-D.
  • Each of these 3:1 selection muxes 628 D-D receives its own SELECT C 610 and a ZERO 611 signals from the mux select & zero logic 604 .
  • the value on the SELECT C 610 for that 3:1 mux is to indicate whether the mux is to output the selected data operand from the lower data set or from the upper data set.
  • the control signal ZERO 611 to each 3:1 mux is to indicate whether that mux should force its output to zero (‘0’).
  • the control signal ZERO 611 supercedes the selection on SELECT C 610 and forces the output for that data element position to ‘0’ in the resultant 632 .
  • 3:1 mux 628 A receives the selected lower data element 620 A from 8:1 mux 618 A and the selected upper data element 626 A from 8:1 mux 624 A for that data element position.
  • SELECT C 610 controls which of the data elements to shuffle at its output 630 A into the data element position it manages in the resultant 632 .
  • signal ZERO 611 to the mux 628 A is active, indicated that the shuffle mask for that data element position states that a ‘0’ is desired, the mux output 630 A is ‘0’ and neither of the data element inputs 620 A, 626 A, are used.
  • the resultant 632 of the shuffle operation is composed of the outputs 630 A-D from the sixteen 3:1 muxes 628 A-D, wherein each output corresponds to a specific data element position and is either a data element or a ‘0’.
  • each 3:1 mux output is a byte wide and the resultant is a data block composed of sixteen packed bytes of data.
  • FIG. 7 illustrates the operation of a data shuffle on byte wide data elements in accordance with one embodiment of the present invention.
  • This is an example of the instruction “PSHUFB DATA, MASK”. Note that the most significant bit of shuffle masks for byte positions 0x6 and 0xC of MASK 701 are set so the result in resultant 741 for those positions are zero.
  • source data is organized into a destination data storage device 721 , which in one embodiment is also the source data storage device 721 , in view of a set of masks 701 that specify the address wherein respective data elements from the source operand 721 are to be stored in the destination register 741 .
  • the two source operands, mask 701 and data 721 each comprise of sixteen packed data elements in this example, as does the resultant 741 .
  • each of the data elements involved is a eight bits or a byte wide.
  • mask 701 , data 721 , and resultant 741 data blocks are each 128 bits long.
  • these data blocks can reside in memory or registers.
  • the arrangement of the masks is based on the desired data processing operation, which may include for example, a filtering operation or a convolution operation.
  • data operand 721 includes source data elements of: P 722 , O 723 , N 724 , M 725 , L 726 , K 727 , J 728 , I 729 , H 730 , G 731 , F 732 , E 733 , D 734 , C 735 , B 736 , A 737 .
  • the data element position is also noted under the data as a hex value. Accordingly, a packed shuffle operation is performed with the mask 701 and data 721 . Using the set of shuffle masks 701 , processing of the data 721 can be performed in parallel.
  • the data operand 821 includes source data elements of: H 822 , G 823 , F 824 , E 835 , D 836 , C 827 , B 828 , A 829 .
  • the data element position is also noted under the data as a hex value.
  • each of the word size data elements in the data operand 821 have data position addresses it occupies two byte size positions.
  • data H 822 takes up byte size data element positions 0xF and 0xE.
  • a packed shuffle operation is performed with the mask 801 and data 821 .
  • the arrows in FIG. 8 illustrate the shuffling of the data elements per the shuffle masks in mask 801 .
  • the appropriate data from the designated data element position of the data operand 821 or a ‘0’ is shuffled to the corresponding data element position in the resultant 831 for that particular shuffle mask.
  • the byte size shuffle masks operate in pairs in order to designate word size data elements.
  • FIG. 9 is a flow chart 900 illustrating one embodiment of a method to shuffle data.
  • the length value of L is generally used here to represent the width of the operands and data blocks. Depending on the particular embodiment, L can be used to designate the width in terms of number of data segments, bits, bytes, words, etc.
  • a first length L packed data operand is received for use with a shuffle operation.
  • a length L set of M length shuffle masks designating a shuffle pattern is received at block 920 .
  • L is 128 bits and M is 8 bits or a byte. In another embodiment, L and M can also be other values, such as 256 and 16, respectively.
  • the shuffle operation is performed wherein data elements from the data operand are shuffled arranged into a resultant in accordance to the shuffle pattern.
  • the shuffle operation makes use of three separate registers or memory locations: two source and one destination.
  • the destination in an alternative embodiment is a register or memory location that is different from either of the source operands.
  • the source table data is not overridden and can be reused.
  • the table data is treated as coming from different portions of a larger table.
  • LOW TABLE DATA 1021 is from a lower address region of the table
  • HIGH TABLE DATA 1051 is from a higher address region of the table.
  • Embodiments of the present invention are not restrictive as to where the table data can originates.
  • the data blocks 1021 , 1051 can be adjacent, far apart, or even overlapping.
  • table data can also be from different data tables or different memory sources.
  • FIG. 10C illustrates a logical packed AND operation involving SELECT FILTER 1043 and the set of shuffle masks MASK 1001 .
  • a mask to selects data values accessed from the first table section with indices zero to fifteen is computed with a packed compare equal operation for this embodiment in FIG. 10D by selecting the shuffle control bytes whose fifth bit is a zero.
  • FIG. 10D illustrates a packed “compare equal operation” of LOW FILTER 1045 and TABLE SELECT MASK 1044 .
  • the low table select mask produced in FIG. 10D for the first table section selects data elements accessed from the first table section with another packed shuffle operation.
  • LOW FILTER 1045 in this instance is a mask to pull out or highlight the data element positions indicated by the shuffle masks as coming from the first data set 1021 .
  • FIG. 11 is a flow chart illustrating one embodiment of a method to perform a table lookup using SIMD instructions.
  • the flow described here generally follows the methodology of FIGS. 10 A-H, but is not restricted as such. Some of these operations can also be performed in different order or using various types of SIMD instructions.
  • a set of shuffle masks designating a shuffle pattern is received. These shuffle masks also include source fields to indicate from which table or source to shuffle data elements to obtain the desired resultant.
  • the data elements for a first portion of a table or a first data set is loaded. The first portion data elements are shuffled in accordance to the shuffle pattern of block 1102 at block 1106 .
  • FIG. 13A illustrates a first packed data shuffle operation of a first mask, MASK A 1302 , on a first source data operand, DATA A 1304 .
  • the desired interleaved resultant 1314 is to include an interleaved pattern of one data element from a first data source 1304 and another data element from a second data source 1310 .
  • the fifth byte of DATA A 1304 is to be interleaved with the twelfth byte of DATA B 1310 .
  • MASK A 1302 includes a repeated pattern of “0x80” and “0x05” in this embodiment.
  • FIG. 15F illustrates the resultant data, INTERLEAVED A & B DATA 1530 , for the packed logical OR-ing of MASKED DATA A 1522 and MASKED DATA B 1524 .
  • the shuffled blue data is now merged together with the interleaved red and green data with another packed logical OR operation.
  • FIG. 15G illustrates the new resultant, INTERLEAVED A, B, & C DATA 1532 , from the packed logic OR-ing of MASKED DATA C 1526 and MASKED DATA A & B 1530 .
  • the resultant data block of FIG. 15G contains the interleaved RGB data for the first five pixels and a portion of the sixth pixel. Subsequent iterations of the algorithm of this embodiment will yield the interleaved RGB data for the rest of the sixteen pixels.
  • the rightmost two data elements relate to the sixth pixel, which already had its red data R 5 arranged with the first interleaved data set 1532 .
  • the raw pixel color data is shifted again by the appropriate number of places per the processing results of the second pass.
  • data for five additional pixels has been processed for red and blue, so the data elements for red data operand DATA A′ 1546 and for blue data operand DATA C′ 1544 are shifted to the right by five data element positions.
  • Data for six pixels has been processed for green, so the data elements for green data operand DATA B′ 1542 is shifted to the right by six positions.
  • the shifted data for this third pass is illustrated in FIG. 15J.
  • a repeat of the packed shuffle and logical OR operations above are applied to DATA C′′ 1552 , DATA A′′ 1554 , and DATA B′′ 1556 .
  • the resultant interleaved RGB data for the last of the sixteen pixels is illustrated in FIG. 15K as INTERLEAVED A′, B′ DATA 1558 .
  • the rightmost data element with B 10 relates to the eleventh pixel, which already has its green data G 10 and red data R 10 arranged with the second interleaved data set 1548 .
  • data from multiple sources 1512 , 1514 , 1516 can be merged and rearranged together in a desired fashion for further use or processing like these resultants 1532 , 1548 , 1558 .
  • FIG. 16 is a flow chart illustrating one embodiment of a method to shuffle data between multiple registers to generate interleaved data.
  • embodiments of the present method can be applied to the generation of interleaved pixel data as discussed in FIGS. 15 A-K.
  • the present embodiment is described in the context of three data sources or planes of data, other embodiments can operate with two or more planes of data. These planes of data can include color data for one or more image frames.
  • frame data for a first, second, and third plane are loaded.
  • RGB color data for a plurality of pixels are available as individual colors from three different planes.
  • an appropriate control pattern is selected for each plane of data.
  • the shuffle pattern is selected based on which order the color data is desired and which iteration is presently being executed.
  • the frame data from the first data set, red is shuffled with a first shuffle control pattern at block 1608 to obtain shuffled red data.
  • the second data set, green is shuffled at block 1610 with a second shuffle control pattern to obtain shuffled green data.
  • the third data set, blue is shuffled with a third shuffle control pattern to achieve shuffled blue data.
  • the shuffled data of blocks 1608 , 1610 , 1612 , for the three data sets are merged together to form the interleaved resultant for this pass.
  • the resultant of the first pass can look like the interleaved data 1532 of FIG. 15G, wherein the RGB data for each pixel is grouped together as a set.
  • a check is made to determine whether there is more frame data loaded in the registers to shuffling. If not, a check is made at block 1620 to determine whether there is more data from the three planes of data to be interleaved. If not, the method is done. If there is more plane data available at block 1620 , the process proceeds back to block 1602 to load more frame data for shuffling.
  • Embodiments of algorithms using packed shuffle instructions in accordance with the present invention can also improve processor and system performance with present hardware resources. But as technology continues to improve, embodiments of the present invention when combined with greater amounts of hardware resources and faster, more efficient logic circuits, can have an even more profound impact on improving performance. Thus, one efficient embodiment of a packed shuffle instruction having byte granularity and a flush to zero option can have different and greater impact across processor generations. Simply adding more resources in modem processor architectures alone does not guarantee better performance improvement. By also maintaining the efficiency of applications like one embodiment of the parallel table lookup and the packed byte shuffle instruction (PSHUFB), larger performance improvements can be possible.
  • PSHUFB packed byte shuffle instruction
US10/611,344 2001-10-29 2003-06-30 Method and apparatus for shuffling data Abandoned US20040054877A1 (en)

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US10/611,344 US20040054877A1 (en) 2001-10-29 2003-06-30 Method and apparatus for shuffling data
DE602004023081T DE602004023081D1 (de) 2003-06-30 2004-06-24 Verfahren und vorrichtung zum mischen von daten
RU2006102503A RU2316808C2 (ru) 2003-06-30 2004-06-24 Способ и устройство тасования данных
PCT/US2004/020601 WO2005006183A2 (en) 2003-06-30 2004-06-24 Method and apparatus for shuffling data
CN200910130582.4A CN101620525B (zh) 2003-06-30 2004-06-24 混洗数据的方法和装置
CNB2004800184438A CN100492278C (zh) 2003-06-30 2004-06-24 混洗数据的方法和装置
AT04756204T ATE442624T1 (de) 2003-06-30 2004-06-24 Verfahren und vorrichtung zum mischen von daten
JP2006515370A JP4607105B2 (ja) 2003-06-30 2004-06-24 データをシャッフルするための方法及び装置
KR20057025313A KR100831472B1 (ko) 2003-06-30 2004-06-24 데이터 셔플링을 위한 방법 및 장치
EP04756204A EP1639452B1 (en) 2003-06-30 2004-06-24 Method and apparatus for shuffling data
TW93118830A TWI270007B (en) 2003-06-30 2004-06-28 Method and apparatus for shuffling data
HK06105784.3A HK1083657A1 (en) 2003-06-30 2006-05-18 Method and apparatus for shuffling data
US12/387,958 US8214626B2 (en) 2001-10-29 2009-03-31 Method and apparatus for shuffling data
JP2010180413A JP5490645B2 (ja) 2003-06-30 2010-08-11 データをシャッフルするための方法及び装置
US12/901,336 US8225075B2 (en) 2001-10-29 2010-10-08 Method and apparatus for shuffling data
JP2011045001A JP5535965B2 (ja) 2003-06-30 2011-03-02 データをシャッフルするための方法及び装置
US13/540,576 US9477472B2 (en) 2001-10-29 2012-07-02 Method and apparatus for shuffling data
US13/608,953 US8688959B2 (en) 2001-10-29 2012-09-10 Method and apparatus for shuffling data
JP2013115254A JP5567181B2 (ja) 2003-06-30 2013-05-31 データをシャッフルするための方法及び装置
US14/586,581 US9229719B2 (en) 2001-10-29 2014-12-30 Method and apparatus for shuffling data
US14/586,558 US9229718B2 (en) 2001-10-29 2014-12-30 Method and apparatus for shuffling data
US15/299,914 US10152323B2 (en) 2001-10-29 2016-10-21 Method and apparatus for shuffling data

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US09/952,891 US7085795B2 (en) 2001-10-29 2001-10-29 Apparatus and method for efficient filtering and convolution of content data
US10/611,344 US20040054877A1 (en) 2001-10-29 2003-06-30 Method and apparatus for shuffling data

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US12/901,336 Expired - Lifetime US8225075B2 (en) 2001-10-29 2010-10-08 Method and apparatus for shuffling data
US13/540,576 Expired - Lifetime US9477472B2 (en) 2001-10-29 2012-07-02 Method and apparatus for shuffling data
US13/608,953 Expired - Lifetime US8688959B2 (en) 2001-10-29 2012-09-10 Method and apparatus for shuffling data
US14/586,581 Expired - Fee Related US9229719B2 (en) 2001-10-29 2014-12-30 Method and apparatus for shuffling data
US14/586,558 Expired - Fee Related US9229718B2 (en) 2001-10-29 2014-12-30 Method and apparatus for shuffling data
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US13/540,576 Expired - Lifetime US9477472B2 (en) 2001-10-29 2012-07-02 Method and apparatus for shuffling data
US13/608,953 Expired - Lifetime US8688959B2 (en) 2001-10-29 2012-09-10 Method and apparatus for shuffling data
US14/586,581 Expired - Fee Related US9229719B2 (en) 2001-10-29 2014-12-30 Method and apparatus for shuffling data
US14/586,558 Expired - Fee Related US9229718B2 (en) 2001-10-29 2014-12-30 Method and apparatus for shuffling data
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