US3711692A  Determination of number of ones in a data field by addition  Google Patents
Determination of number of ones in a data field by addition Download PDFInfo
 Publication number
 US3711692A US3711692A US3711692DA US3711692A US 3711692 A US3711692 A US 3711692A US 3711692D A US3711692D A US 3711692DA US 3711692 A US3711692 A US 3711692A
 Authority
 US
 United States
 Prior art keywords
 full
 significant digit
 output
 subsets
 count
 Prior art date
 Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
 Expired  Lifetime
Links
 238000007792 addition Methods 0 claims description title 7
 241001442055 Vipera berus Species 0 abstract claims description 118
 230000000063 preceeding Effects 0 claims description 6
 239000000460 chlorine Substances 0 description 2
 230000001934 delay Effects 0 description 2
 238000003860 storage Methods 0 description 2
 230000015654 memory Effects 0 description 1
 239000000047 products Substances 0 description 1
 230000004044 response Effects 0 description 1
 239000004065 semiconductor Substances 0 description 1
 239000011800 void materials Substances 0 description 1
Images
Classifications

 G—PHYSICS
 G11—INFORMATION STORAGE
 G11C—STATIC STORES
 G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is readout by searching for one or more of these characteristic parts, i.e. associative or contentaddressed stores
 G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is readout by searching for one or more of these characteristic parts, i.e. associative or contentaddressed stores using semiconductor elements

 G—PHYSICS
 G06—COMPUTING; CALCULATING; COUNTING
 G06F—ELECTRIC DIGITAL DATA PROCESSING
 G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
 G06F7/60—Methods or arrangements for performing computations using a digital nondenominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and nondenominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
 G06F7/607—Methods or arrangements for performing computations using a digital nondenominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and nondenominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers numberofones counters, i.e. devices for counting the number of input lines set to ONE among a plurality of input lines, also called bit counters or parallel counters
Abstract
Description
United States Patent Batcher [451 Jan. 16, 1973 [54] DETERMINATION OF NUMBER OF 3.466.433 9/969 Dudact al .235/l75 3,603,776 9/!97] Wcinherger ..235/l75 ONES IN A DATA FIELD BY ADDITION [75] Inventor: Kenneth E. Batcher, Stow, Ohio [73] Assignee: Goodyear Aerospace Corporation,
Akron, Ohio [22] Filed: March 15, 1971 [2]] Appl. No.: l24,08 9
[52] US. Cl ..235/l75 [51] Int. Cl ..G06f 7/50 [58] Field of Search ..235/l75, 92, 92 CP, 92 SA [56] References Cited UNITED STATES PATENTS 3,535,502 l0/l970 Clapper ..235/l75 X Primary ExaminerEugene G. Botz Assistant ExaminerDavid H. Malzahn Att0rney.l. G. Pere and L. A. Germain [57] ABSTRACT An arrangement for counting the number of a given data such as ones in a data field. The system employs full adders which count the number of ones in basic three element subsets of the data field. Additional full adders total the results of the first series of full adders and also count any additional ones of the data field.
5 Claims, 3 Drawing Figures OUTPUT PATENTEDJAN 1 6 I973 SHEET 2 0F 2 mmE INVENTOR KENNETH E. BATCHER WWW,
ATTORNEYS DETERMINATION OF NUMBER OF ONES IN A DATA FIELD BY ADDITION It is the primary object of the present invention to provide means for counting the number of occurrences ofa given value in a data field.
It is also an object of the invention to provide means for counting the number of occurrences of a given value in a data field which provides for the fast counting of the selected value occurrences.
The above and other objects of the invention which will become apparent in the following detailed description are achieved by providing a counting arrangement in which a first series of full adders count the number of occurrences of a selected value simultaneously in three element subsets of the data field, and includes an additional series of full adders for combining the totals produced by each of the adders of the first series.
For a more complete understanding of the invention and the objects and advantages thereof reference should be had to the following detailed descriptionand the accompanying drawings wherein there is shown a preferred embodiment of the invention.
In the drawing:
FIG. 1 is a schematic showing of the counting arrangement of the present invention for a six element field;
FIG. 2 is a schematic showing of the counting arrangement for a seven element field; and
FIG. 3 is a schematic showing of a counting arrangement for a fifteen element field.
The data fields referred to in the following description may be stored in any suitable data storage means, such as the response store of an associative memory or associative processor. Regardless of the particular storage device involved, the data is stored as individual bits in the usual digital manner each having a O or 1 value.
FIG. 1 shows a six element data field 10 and illustrates the basic concept of the present invention. Each of the elements b of the data field 10 may have either a or. I value. While the elements are shown grouped into two sets of three elements each, this is for illustration only and the data field is not necessarily so arranged physically. In order to count the total number of bits b which are of a particular value, for example which have the value 1, there is provided an arrangement of full adders 1218. A typical full adder would be a MCl0l9 integrated circuit manufactured by Motorola Semiconductor Products, Inc.. Each of the full adders 1218 is capable of receiving three binary inputs and adding these inputs to produce the two digit binary sum thereof, with the least significant digit of the sum being produced at the output s and the more significant digit being produced at the output 0. The full adder 12 receives as inputs the values of three of the bits of the data field 10 and the full adder 14 receives as inputs the values of the remaining three data bits. If the data field is expressed in a form other than a binary code, converting means may be provided between the elements of the field and the full adders. Such converting means produces a 0 output if the element is not of the selected value and a 1 output if the element is of the selected value. Thus, the full adders 12 and 14 will simultaneously produce the total count of the 1's in their respective subsets of the data field 10. A third full adder 16 receives as inputs the least significant digit outputs of the first full adders l2 and 14. The output of this full adder 16 represents the sum of the least significant digits of the outputs of the adders I2 and 14. The least significant digit of the output of the adder 16 is thus the least significant digit of the sum of the 1's in the data field 10. This digit is supplied to the output device 20. A fourth full adder 18 receives as inputs the most significant digit output of the full adder l6 and the most significant digit outputs of the full adders I2 and 14. The least significant digit of the addition performed by the full adder 18 is the second significant digit of the total count while the most significant digit of the output is the most significant digit of the full count. Thus, the output of the least significant digit of the full adder l6 and the full output of the adder 18 comprise the full count of the number of ones in the data field 10.
FIG. 2 illustrates the arrangement of full adders employed with a data field 22 having seven elements. A first set of full adders 24 and 26 each count the values of three positions of the data field 22. An additional set of full adders 28 and 30 count, respectively, the single previously uncounted bit value of the data field 22, the least significant digits of the outputs of the counters 24 and 26, and the most significant digit of the output of the counter 28 and the most significant digits of the outputs of the counters 24 and 26. Again, the least significant digit output of the counter 28 is the least significant digit of the total count while the outputs of the full adder 30 provide the second and third significant digits of the total count. These three outputs are supplied to the output device 32 and represent the total count of the number of l s in the data field 22.
The basic counting system described in the above paragraphs may be expanded to count the number of ls in a field of any length. Essentially, this is accomplished by dividing the data field into subsets which may be counted by one of the counting arrangements described above and by adding the totals achieved for each subset by means of additional full adders. Thus, as is shown in FIG. 3, a fifteen element data field 48 may be divided into three subsets: S, which consists ofa single bit of the data field 48, S which consists of the next seven data bits of the field 48; and S which consists of the remaining seven data bits. It should be noted that the order in which the data field 48 is divided into the subsets S S and S is purely arbitrary. The arrangement shown in which the first element is assigned to the subset the next seven elements to the subset S ,and the remaining seven elements to subset S is chosen for convenience of illustration. However, any other arrangement may be employed so long as the subsets S and 8;, are of equal length and the subset S, contains not more than one element.
The total count of 1's in the subsets S and 8;, may be determined by full counters 50 and 52 which are each equivalent to the full adder arrangement of FIG. 2. The counts produced by the seven position counters 50 and 52 and the count of the least significant bit subset S are added by means of additional full adders 5458. These full adders 5458 add, respectively, the least significant digit values, the next most significant digit values and the carry value of the previous adder, and the most significant digit values and the carry value from the previous adder. The outputs of the full adders 5458 provide the successively higher ranked significant digits of the total count and these outputs are furnished to the output device 60. It should be noted that the maximum time required to achieve the total count of the number of I s in the data field is equal to the delay imposed by a full adder multiplied by the total number of full adders involved in producing one digit of the output or final count. Referring again to the arrangement of FIG. 3 it will be seen that the maximum delay is five times the delay of one full adder. Since the adders 62 and 64 operate simultaneiously these two full adders impose only one time delay in the count. The adder 68, however, receives inputs both from the adder 62 and from the full adder 66. As a result, two additional delays are imposed. Likewise, the full adder 56 receives inputs both from the adder 68 and the adder 54 so that two additional time delays are again imposed. In general, if a field having 11 bit positions can be counted with a maximum delay of P full adders, a field having 2n 1 bit positions can be counted with a maximum delay off 2 full adders. For a field having 2" 1 bit positions, where m is greater than or equal to 2, the maximum delay will be 2m 3 multiplied by the delay of one full adder.
The counting arrangement of the present invention is applicable to date fields of any length. The data field is first divided into three primary subsets S S and S with the subsets S and 8;, being of equal length and the subset S containing at most a single element. The subsets S,, S and 8;, are mutually exclusive and exhaust the elements of the data field. lf the primary subsets S and 8;, each contain more than three elements, they are further divided into secondary subsets S S and S and S S and S respectively. The secondary subsets are also mutually exclusive and exhaustive of the elements of their respective primary subsets. The division of the primary subsets is accomplished in the same manner as the original division of the data field. Thus, the subsets S and S are of equal length and the subset S is either void or contains a single element, depending on whether the primary subset S contains an even or odd number of elements. Division of the multiple element subsets is continued in the same manner until a series of ultimate subsets, none of which contains more than three elements of the data field, is achieved.
A full adder is provided for each of the ultimate subsets which contains more than a single element. The full adders produce the counts of the number of 1's in the multiple element ultimate subsets. The counts of the penultimate subsets are obtained by means of additional full adders, two additional full adders being provided for each penultimate subset with one full adder combining the count of the single element subset, if present, and the least significant digit outputs of the ultimate subset adders and the second full adder combining the most significant digit of the output of the first full adder and the most significant digits of the ultimate subset full adders. By means of additional full adders arranged in the same manner, the counts of the successive subsets of the hierarchical rank of the subsets are obtained. The final series of adders combines the counts of the subsets 5,, S and S to produce the total count for the entire data field.
It will be understood that while only the best known embodiment of the invention has been described in detail, in accordance with the Patent Statutes, the invention is not so limited. Reference should therefore be had to the appended claims in determining the true scope of the invention.
What is claimed is:
1. The method of determining the number of occurrences of a selected value in a data field having at least fifteen elements, which comprises the steps of l. dividing the data field into mutually exclusive, ex
haustive subsets S S and S where S, and S, are of equal length and 8, includes at most one element of the data field;
2. counting the occurrences of the selected value in each of the subsets S, and S 3. adding, by means ofa full adder, the number of occurrences of the selected value in subset S and the least significant digit of the count of each of the subsets S and S 4. adding, by means of an additional full adder, the most significant digit of the output of the previous full adder and the next significant digit of the count of each of the subsets S and S 5. repeating step (4) until all the digits of the count of each of the subsets S, and 5;, have been exhausted, an additional full adder being employed for each addition; and
6. transmitting to an output device the least significant digit of the output of each full adder and both digits of the output of the last full adder, the least significant digit of the output of the first full adder being the least significant digit of the total count, the least significant digits of the outputs of successive full adders being the successive digits of the full count, and the most significant digit of the output of the final full adder being the most significant digit of the full count.
2. The method according to claim 1 wherein the count of each multiple element subset of the data field is determined by the steps of:
a. dividing .the subset into three mutually exclusive, exhaustive subsets, the firstof which has at most one element, a second and third of which are of equal length;
b. determining if any subset produced in the immediately preceeding division contains more than three elements;
c. dividing all elements produced in the immediately preceeding division which contain more than three elements into three subsets satisfying the conditions of step (a);
. repeating steps (b) and (0) until an ultimate series of subsets no one of which contains more than three elements is obtained;
e. summing, by means of full adders, the number of occurrences of the selected value of each ultimate subset having more than one element; and
f. by means of additional full adders, progressively combining andadding to the sums the number of occurrences of the selected value in those subsets having one element in the reverse order of their creation in steps (a) through (d) until the total count of each multiple element subset has been achieved.
3. Apparatus for counting the number of occurrences of a predetermined value in a data field of at least fifteen elements, comprising:
first and second counting means for counting the number of occurrences in first and second portions, respectively, of the data field, the first and second portions being nonoverlapping, of equal length, and including at least all but one element of the data field;
a first full adder receiving as inputs the value of the data field element excluded from the first and second portions and the least significant digits of the output of the first and second counting means;
additional full adders receiving as inputs, respectively, the more significant digit output of the preceeding full adder and the succeedingly more significant digits of the outputs of the first and second counting means; and
an output device receiving the least significant digit outputs of each full adder and the most significant digit output of the final full adder, the output of the first full adder being the least significant digit of the total and the outputs of successive full adders being the successively more significant digits of the total.
4. Apparatus according to claim 3 wherein the first and second counting means each comprise a plurality of full adders.
5. Apparatus according to claim 4 wherein the full adders comprising each counting means are arranged in a plurality of series, the full adders of the first series counting the occurrences in two to three element subsets of the portion, the full adders of successive series combining the totals of the previous series of full adders.
Claims (10)
Priority Applications (1)
Application Number  Priority Date  Filing Date  Title 

US12408971A true  19710315  19710315 
Publications (1)
Publication Number  Publication Date 

US3711692A true US3711692A (en)  19730116 
Family
ID=22412705
Family Applications (1)
Application Number  Title  Priority Date  Filing Date 

US3711692D Expired  Lifetime US3711692A (en)  19710315  19710315  Determination of number of ones in a data field by addition 
Country Status (1)
Country  Link 

US (1)  US3711692A (en) 
Cited By (84)
Publication number  Priority date  Publication date  Assignee  Title 

FR2385146A1 (en) *  19770324  19781020  Western Electric Co  Counting circuit the number of "1" in a digital word 
US4336600A (en) *  19790412  19820622  ThomsonCsf  Binary word processing method using a highspeed sequential adder 
US4399517A (en) *  19810319  19830816  Texas Instruments Incorporated  Multipleinput binary adder 
US4488253A (en) *  19810508  19841211  Itt Industries, Inc.  Parallel counter and application to binary adders 
EP0195284A2 (en) *  19850320  19860924  Siemens Aktiengesellschaft  Device for counting the number of 1/0 bits contained in an nbits binary word 
US4713786A (en) *  19850215  19871215  Harris Corporation  Digital hardware selection filter 
EP0388506A2 (en) *  19890320  19900926  Digital Equipment Corporation  Normalizer 
US5148388A (en) *  19910517  19920915  Advanced Micro Devices, Inc.  7 to 3 counter circuit 
WO1996017289A1 (en) *  19941201  19960606  Intel Corporation  A novel processor having shift operations 
US5539683A (en) *  19930810  19960723  Fujitsu Limited  Method and device for processing, and detecting a state of, binary data 
US5541865A (en) *  19931230  19960730  Intel Corporation  Method and apparatus for performing a population count operation 
US5619437A (en) *  19940930  19970408  Ando Electric Co., Ltd.  Parallel data counter circuit 
US5642306A (en) *  19940727  19970624  Intel Corporation  Method and apparatus for a single instruction multiple data earlyout zeroskip multiplier 
US5675526A (en) *  19941201  19971007  Intel Corporation  Processor performing packed data multiplication 
US5701508A (en) *  19951219  19971223  Intel Corporation  Executing different instructions that cause different data type operations to be performed on single logical register file 
US5721892A (en) *  19950831  19980224  Intel Corporation  Method and apparatus for performing multiplysubtract operations on packed data 
US5740392A (en) *  19951227  19980414  Intel Corporation  Method and apparatus for fast decoding of 00H and OFH mapped instructions 
US5742529A (en) *  19951221  19980421  Intel Corporation  Method and an apparatus for providing the absolute difference of unsigned values 
US5752001A (en) *  19950601  19980512  Intel Corporation  Method and apparatus employing Viterbi scoring using SIMD instructions for data recognition 
US5757432A (en) *  19951218  19980526  Intel Corporation  Manipulating video and audio signals using a processor which supports SIMD instructions 
US5764943A (en) *  19951228  19980609  Intel Corporation  Data path circuitry for processor having multiple instruction pipelines 
US5787026A (en) *  19951220  19980728  Intel Corporation  Method and apparatus for providing memory access in a processor pipeline 
US5793661A (en) *  19951226  19980811  Intel Corporation  Method and apparatus for performing multiply and accumulate operations on packed data 
US5802336A (en) *  19941202  19980901  Intel Corporation  Microprocessor capable of unpacking packed data 
US5815421A (en) *  19951218  19980929  Intel Corporation  Method for transposing a twodimensional array 
US5819101A (en) *  19941202  19981006  Intel Corporation  Method for packing a plurality of packed data elements in response to a pack instruction 
US5822232A (en) *  19960301  19981013  Intel Corporation  Method for performing box filter 
US5822459A (en) *  19950928  19981013  Intel Corporation  Method for processing wavelet bands 
US5831885A (en) *  19960304  19981103  Intel Corporation  Computer implemented method for performing division emulation 
US5835392A (en) *  19951228  19981110  Intel Corporation  Method for performing complex fast fourier transforms (FFT's) 
US5835782A (en) *  19960304  19981110  Intel Corporation  Packed/add and packed subtract operations 
US5835748A (en) *  19951219  19981110  Intel Corporation  Method for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register file 
US5852726A (en) *  19951219  19981222  Intel Corporation  Method and apparatus for executing two types of instructions that specify registers of a shared logical register file in a stack and a nonstack referenced manner 
US5857096A (en) *  19951219  19990105  Intel Corporation  Microarchitecture for implementing an instruction to clear the tags of a stack reference register file 
US5862067A (en) *  19951229  19990119  Intel Corporation  Method and apparatus for providing high numerical accuracy with packed multiplyadd or multiplysubtract operations 
US5881279A (en) *  19961125  19990309  Intel Corporation  Method and apparatus for handling invalid opcode faults via execution of an eventsignaling microoperation 
US5880979A (en) *  19951221  19990309  Intel Corporation  System for providing the absolute difference of unsigned values 
US5898601A (en) *  19960215  19990427  Intel Corporation  Computer implemented method for compressing 24 bit pixels to 16 bit pixels 
US5907842A (en) *  19951220  19990525  Intel Corporation  Method of sorting numbers to obtain maxima/minima values with ordering 
US5936872A (en) *  19950905  19990810  Intel Corporation  Method and apparatus for storing complex numbers to allow for efficient complex multiplication operations and performing such complex multiplication operations 
US5935240A (en) *  19951215  19990810  Intel Corporation  Computer implemented method for transferring packed data between register files and memory 
US5940859A (en) *  19951219  19990817  Intel Corporation  Emptying packed data state during execution of packed data instructions 
US5959636A (en) *  19960223  19990928  Intel Corporation  Method and apparatus for performing saturation instructions using saturation limit values 
US5983253A (en) *  19950905  19991109  Intel Corporation  Computer system for performing complex digital filters 
US5983257A (en) *  19951226  19991109  Intel Corporation  System for signal processing using multiplyadd operations 
US5983256A (en) *  19950831  19991109  Intel Corporation  Apparatus for performing multiplyadd operations on packed data 
US5984515A (en) *  19951215  19991116  Intel Corporation  Computer implemented method for providing a two dimensional rotation of packed data 
US6009191A (en) *  19960215  19991228  Intel Corporation  Computer implemented method for compressing 48bit pixels to 16bit pixels 
US6014684A (en) *  19970324  20000111  Intel Corporation  Method and apparatus for performing N bit by 2*N1 bit signed multiplication 
US6018351A (en) *  19951219  20000125  Intel Corporation  Computer system performing a twodimensional rotation of packed data representing multimedia information 
US6036350A (en) *  19951220  20000314  Intel Corporation  Method of sorting signed numbers and solving absolute differences using packed instructions 
US6049864A (en) *  19960820  20000411  Intel Corporation  Method for scheduling a flag generating instruction and a subsequent instruction by executing the flag generating instruction in a microprocessor 
US6058408A (en) *  19950905  20000502  Intel Corporation  Method and apparatus for multiplying and accumulating complex numbers in a digital filter 
US6067034A (en) *  19970407  20000523  Vocal Technologies Ltd.  Maximal bit packing method 
US6070237A (en) *  19960304  20000530  Intel Corporation  Method for performing population counts on packed data types 
US6081824A (en) *  19980305  20000627  Intel Corporation  Method and apparatus for fast unsigned integral division 
US6092184A (en) *  19951228  20000718  Intel Corporation  Parallel processing of pipelined instructions having register dependencies 
US6237016B1 (en)  19950905  20010522  Intel Corporation  Method and apparatus for multiplying and accumulating data samples and complex coefficients 
US6275834B1 (en)  19941201  20010814  Intel Corporation  Apparatus for performing packed shift operations 
US6418529B1 (en)  19980331  20020709  Intel Corporation  Apparatus and method for performing intraadd operation 
US6430251B1 (en) *  20001024  20020806  Sun Microsystems, Inc.  4Bit population count circuit 
US20020112147A1 (en) *  20010214  20020815  Srinivas Chennupaty  Shuffle instructions 
US6470370B2 (en)  19950905  20021022  Intel Corporation  Method and apparatus for multiplying and accumulating complex numbers in a digital filter 
US20030123748A1 (en) *  20011029  20030703  Intel Corporation  Fast full search motion estimation with SIMD merge instruction 
US20040010676A1 (en) *  20020711  20040115  Maciukenas Thomas B.  Byte swap operation for a 64 bit operand 
US20040054878A1 (en) *  20011029  20040318  Debes Eric L.  Method and apparatus for rearranging data between multiple registers 
US20040054879A1 (en) *  20011029  20040318  Macy William W.  Method and apparatus for parallel table lookup using SIMD instructions 
US20040059889A1 (en) *  19980331  20040325  Macy William W.  Method and apparatus for performing efficient transformations with horizontal addition and subtraction 
US6738793B2 (en)  19941201  20040518  Intel Corporation  Processor capable of executing packed shift operations 
US20040117422A1 (en) *  19950831  20040617  Eric Debes  Method and apparatus for performing multiplyadd operations on packed data 
US20040133617A1 (en) *  20011029  20040708  YenKuang Chen  Method and apparatus for computing matrix transformations 
WO2004064254A2 (en) *  20030114  20040729  Arithmatica Limited  A logic circuit 
US20040153490A1 (en) *  20021223  20040805  Sunil Talwar  Logic circuit and method for carry and sum generation and method of designing such a logic circuit 
US6792523B1 (en)  19951219  20040914  Intel Corporation  Processor with instructions that operate on different data types stored in the same single logical register file 
US20040223580A1 (en) *  20030425  20041111  J. Barry Shackleford  Ones counter employing two dimensional cellular array 
US20050108312A1 (en) *  20011029  20050519  YenKuang Chen  Bitstream buffer manipulation with a SIMD merge instruction 
US7395302B2 (en)  19980331  20080701  Intel Corporation  Method and apparatus for performing horizontal addition and subtraction 
US7430578B2 (en)  20011029  20080930  Intel Corporation  Method and apparatus for performing multiplyadd operations on packed byte data 
US7624138B2 (en)  20011029  20091124  Intel Corporation  Method and apparatus for efficient integer transform 
US20110029759A1 (en) *  20011029  20110203  Macy Jr William W  Method and apparatus for shuffling data 
US20110238717A1 (en) *  20100329  20110929  Meltin Bell  Linear Bit Counting Implementations 
US8078836B2 (en)  20071230  20111213  Intel Corporation  Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a common set of perlane control bits 
USRE45458E1 (en)  19980331  20150407  Intel Corporation  Dual function system and method for shuffling packed data elements 
US10146537B2 (en) *  20150313  20181204  Micron Technology, Inc.  Vector population count determination in memory 
Citations (3)
Publication number  Priority date  Publication date  Assignee  Title 

US3466433A (en) *  19651214  19690909  Ibm  Optical parallel adder 
US3535502A (en) *  19671115  19701020  Ibm  Multiple input binary adder 
US3603776A (en) *  19690115  19710907  Ibm  Binary batch adder utilizing threshold counters 

1971
 19710315 US US3711692D patent/US3711692A/en not_active Expired  Lifetime
Patent Citations (3)
Publication number  Priority date  Publication date  Assignee  Title 

US3466433A (en) *  19651214  19690909  Ibm  Optical parallel adder 
US3535502A (en) *  19671115  19701020  Ibm  Multiple input binary adder 
US3603776A (en) *  19690115  19710907  Ibm  Binary batch adder utilizing threshold counters 
Cited By (187)
Publication number  Priority date  Publication date  Assignee  Title 

FR2385146A1 (en) *  19770324  19781020  Western Electric Co  Counting circuit the number of "1" in a digital word 
US4336600A (en) *  19790412  19820622  ThomsonCsf  Binary word processing method using a highspeed sequential adder 
US4399517A (en) *  19810319  19830816  Texas Instruments Incorporated  Multipleinput binary adder 
US4488253A (en) *  19810508  19841211  Itt Industries, Inc.  Parallel counter and application to binary adders 
US4713786A (en) *  19850215  19871215  Harris Corporation  Digital hardware selection filter 
EP0195284A2 (en) *  19850320  19860924  Siemens Aktiengesellschaft  Device for counting the number of 1/0 bits contained in an nbits binary word 
EP0195284A3 (en) *  19850320  19890201  Siemens Aktiengesellschaft  Device for counting the number of 1/0 bits contained in an nbits binary word 
EP0388506A2 (en) *  19890320  19900926  Digital Equipment Corporation  Normalizer 
EP0388506A3 (en) *  19890320  19920429  Digital Equipment Corporation  Normalizer 
US5148388A (en) *  19910517  19920915  Advanced Micro Devices, Inc.  7 to 3 counter circuit 
US5539683A (en) *  19930810  19960723  Fujitsu Limited  Method and device for processing, and detecting a state of, binary data 
US5541865A (en) *  19931230  19960730  Intel Corporation  Method and apparatus for performing a population count operation 
US5642306A (en) *  19940727  19970624  Intel Corporation  Method and apparatus for a single instruction multiple data earlyout zeroskip multiplier 
US5619437A (en) *  19940930  19970408  Ando Electric Co., Ltd.  Parallel data counter circuit 
US20040024800A1 (en) *  19941201  20040205  Lin Derrick Chu  Method and apparatus for performing packed shift operations 
US5666298A (en) *  19941201  19970909  Intel Corporation  Method for performing shift operations on packed data 
US5675526A (en) *  19941201  19971007  Intel Corporation  Processor performing packed data multiplication 
US5677862A (en) *  19941201  19971014  Intel Corporation  Method for multiplying packed data 
US6901420B2 (en)  19941201  20050531  Intel Corporation  Method and apparatus for performing packed shift operations 
US20050219897A1 (en) *  19941201  20051006  Lin Derrick C  Method and apparatus for providing packed shift operations in a processor 
US6275834B1 (en)  19941201  20010814  Intel Corporation  Apparatus for performing packed shift operations 
US7480686B2 (en)  19941201  20090120  Intel Corporation  Method and apparatus for executing packed shift operations 
US7117232B2 (en)  19941201  20061003  Intel Corporation  Method and apparatus for providing packed shift operations in a processor 
US20040215681A1 (en) *  19941201  20041028  Lin Derrick Chu  Method and apparatus for executing packed shift operations 
US6738793B2 (en)  19941201  20040518  Intel Corporation  Processor capable of executing packed shift operations 
US7461109B2 (en)  19941201  20081202  Intel Corporation  Method and apparatus for providing packed shift operations in a processor 
US7451169B2 (en)  19941201  20081111  Intel Corporation  Method and apparatus for providing packed shift operations in a processor 
WO1996017289A1 (en) *  19941201  19960606  Intel Corporation  A novel processor having shift operations 
US20060235914A1 (en) *  19941201  20061019  Lin Derrick C  Method and apparatus for providing packed shift operations in a processor 
US5818739A (en) *  19941201  19981006  Intel Corporation  Processor for performing shift operations on packed data 
US6631389B2 (en)  19941201  20031007  Intel Corporation  Apparatus for performing packed shift operations 
US20070239810A1 (en) *  19941201  20071011  Lin Derrick C  Method and apparatus for providing packed shift operations in a processor 
US5802336A (en) *  19941202  19980901  Intel Corporation  Microprocessor capable of unpacking packed data 
US9015453B2 (en)  19941202  20150421  Intel Corporation  Packing odd bytes from two source registers of packed data 
US20060236076A1 (en) *  19941202  20061019  Alexander Peleg  Method and apparatus for packing data 
US8838946B2 (en)  19941202  20140916  Intel Corporation  Packing lower half bits of signed data elements in two source registers in a destination register with saturation 
US9116687B2 (en)  19941202  20150825  Intel Corporation  Packing in destination register half of each element with saturation from two source packed data registers 
US20110219214A1 (en) *  19941202  20110908  Alexander Peleg  Microprocessor having novel operations 
US5819101A (en) *  19941202  19981006  Intel Corporation  Method for packing a plurality of packed data elements in response to a pack instruction 
US20030131219A1 (en) *  19941202  20030710  Alexander Peleg  Method and apparatus for unpacking packed data 
US20030115441A1 (en) *  19941202  20030619  Alexander Peleg  Method and apparatus for packing data 
US8793475B2 (en)  19941202  20140729  Intel Corporation  Method and apparatus for unpacking and moving packed data 
US6516406B1 (en)  19941202  20030204  Intel Corporation  Processor executing unpack instruction to interleave data elements from two packed data 
US9141387B2 (en)  19941202  20150922  Intel Corporation  Processor executing unpack and pack instructions specifying two source packed data operands and saturation 
US8639914B2 (en)  19941202  20140128  Intel Corporation  Packing signed word elements from two source registers to saturated signed byte elements in destination register 
US9182983B2 (en)  19941202  20151110  Intel Corporation  Executing unpack instruction and pack instruction with saturation on packed data elements from two source operand registers 
US9361100B2 (en)  19941202  20160607  Intel Corporation  Packing saturated lower 8bit elements from two source registers of packed 16bit elements 
US9389858B2 (en)  19941202  20160712  Intel Corporation  Orderly storing of corresponding packed bytes from first and second source registers in result register 
US20110093682A1 (en) *  19941202  20110421  Alexander Peleg  Method and apparatus for packing data 
US8495346B2 (en)  19941202  20130723  Intel Corporation  Processor executing pack and unpack instructions 
US8601246B2 (en)  19941202  20131203  Intel Corporation  Execution of instruction with element size control bit to interleavingly store half packed data elements of source registers in same size destination register 
US7966482B2 (en)  19941202  20110621  Intel Corporation  Interleaving saturated lower half of data elements from two source registers of packed data 
US8190867B2 (en)  19941202  20120529  Intel Corporation  Packing two packed signed data in registers with saturation 
US8521994B2 (en)  19941202  20130827  Intel Corporation  Interleaving corresponding data elements from part of two source registers to destination register in processor operable to perform saturation 
US9223572B2 (en)  19941202  20151229  Intel Corporation  Interleaving half of packed data elements of size specified in instruction and stored in two source registers 
US5752001A (en) *  19950601  19980512  Intel Corporation  Method and apparatus employing Viterbi scoring using SIMD instructions for data recognition 
US8725787B2 (en)  19950831  20140513  Intel Corporation  Processor for performing multiplyadd operations on packed data 
US8495123B2 (en)  19950831  20130723  Intel Corporation  Processor for performing multiplyadd operations on packed data 
US8396915B2 (en)  19950831  20130312  Intel Corporation  Processor for performing multiplyadd operations on packed data 
US5859997A (en) *  19950831  19990112  Intel Corporation  Method for performing multiplysubstrate operations on packed data 
US7395298B2 (en)  19950831  20080701  Intel Corporation  Method and apparatus for performing multiplyadd operations on packed data 
US8793299B2 (en)  19950831  20140729  Intel Corporation  Processor for performing multiplyadd operations on packed data 
US5983256A (en) *  19950831  19991109  Intel Corporation  Apparatus for performing multiplyadd operations on packed data 
US8626814B2 (en)  19950831  20140107  Intel Corporation  Method and apparatus for performing multiplyadd operations on packed data 
US20090265409A1 (en) *  19950831  20091022  Peleg Alexander D  Processor for performing multiplyadd operations on packed data 
US5721892A (en) *  19950831  19980224  Intel Corporation  Method and apparatus for performing multiplysubtract operations on packed data 
US8745119B2 (en)  19950831  20140603  Intel Corporation  Processor for performing multiplyadd operations on packed data 
US6035316A (en) *  19950831  20000307  Intel Corporation  Apparatus for performing multiplyadd operations on packed data 
US20040117422A1 (en) *  19950831  20040617  Eric Debes  Method and apparatus for performing multiplyadd operations on packed data 
US7509367B2 (en)  19950831  20090324  Intel Corporation  Method and apparatus for performing multiplyadd operations on packed data 
US6385634B1 (en)  19950831  20020507  Intel Corporation  Method for performing multiplyadd operations on packed data 
US20020059355A1 (en) *  19950831  20020516  Intel Corporation  Method and apparatus for performing multiplyadd operations on packed data 
US7424505B2 (en)  19950831  20080909  Intel Corporation  Method and apparatus for performing multiplyadd operations on packed data 
US8185571B2 (en)  19950831  20120522  Intel Corporation  Processor for performing multiplyadd operations on packed data 
US5936872A (en) *  19950905  19990810  Intel Corporation  Method and apparatus for storing complex numbers to allow for efficient complex multiplication operations and performing such complex multiplication operations 
US6470370B2 (en)  19950905  20021022  Intel Corporation  Method and apparatus for multiplying and accumulating complex numbers in a digital filter 
US6237016B1 (en)  19950905  20010522  Intel Corporation  Method and apparatus for multiplying and accumulating data samples and complex coefficients 
US5983253A (en) *  19950905  19991109  Intel Corporation  Computer system for performing complex digital filters 
US6058408A (en) *  19950905  20000502  Intel Corporation  Method and apparatus for multiplying and accumulating complex numbers in a digital filter 
US6823353B2 (en)  19950905  20041123  Intel Corporation  Method and apparatus for multiplying and accumulating complex numbers in a digital filter 
US5822459A (en) *  19950928  19981013  Intel Corporation  Method for processing wavelet bands 
US5984515A (en) *  19951215  19991116  Intel Corporation  Computer implemented method for providing a two dimensional rotation of packed data 
US5935240A (en) *  19951215  19990810  Intel Corporation  Computer implemented method for transferring packed data between register files and memory 
US5815421A (en) *  19951218  19980929  Intel Corporation  Method for transposing a twodimensional array 
US5757432A (en) *  19951218  19980526  Intel Corporation  Manipulating video and audio signals using a processor which supports SIMD instructions 
US7149882B2 (en)  19951219  20061212  Intel Corporation  Processor with instructions that operate on different data types stored in the same single logical register file 
US5835748A (en) *  19951219  19981110  Intel Corporation  Method for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register file 
US5857096A (en) *  19951219  19990105  Intel Corporation  Microarchitecture for implementing an instruction to clear the tags of a stack reference register file 
US6751725B2 (en)  19951219  20040615  Intel Corporation  Methods and apparatuses to clear state for operation of a stack 
US5940859A (en) *  19951219  19990817  Intel Corporation  Emptying packed data state during execution of packed data instructions 
US6266686B1 (en)  19951219  20010724  Intel Corporation  Emptying packed data state during execution of packed data instructions 
US6170997B1 (en)  19951219  20010109  Intel Corporation  Method for executing instructions that operate on different data types stored in the same single logical register file 
US5701508A (en) *  19951219  19971223  Intel Corporation  Executing different instructions that cause different data type operations to be performed on single logical register file 
US5852726A (en) *  19951219  19981222  Intel Corporation  Method and apparatus for executing two types of instructions that specify registers of a shared logical register file in a stack and a nonstack referenced manner 
US6792523B1 (en)  19951219  20040914  Intel Corporation  Processor with instructions that operate on different data types stored in the same single logical register file 
US20040181649A1 (en) *  19951219  20040916  David Bistry  Emptying packed data state during execution of packed data instructions 
US20050038977A1 (en) *  19951219  20050217  Glew Andrew F.  Processor with instructions that operate on different data types stored in the same single logical register file 
US20040210741A1 (en) *  19951219  20041021  Glew Andrew F.  Processor with instructions that operate on different data types stored in the same single logical register file 
US6018351A (en) *  19951219  20000125  Intel Corporation  Computer system performing a twodimensional rotation of packed data representing multimedia information 
US7373490B2 (en)  19951219  20080513  Intel Corporation  Emptying packed data state during execution of packed data instructions 
US6128614A (en) *  19951220  20001003  Intel Corporation  Method of sorting numbers to obtain maxima/minima values with ordering 
US6036350A (en) *  19951220  20000314  Intel Corporation  Method of sorting signed numbers and solving absolute differences using packed instructions 
US5907842A (en) *  19951220  19990525  Intel Corporation  Method of sorting numbers to obtain maxima/minima values with ordering 
US5787026A (en) *  19951220  19980728  Intel Corporation  Method and apparatus for providing memory access in a processor pipeline 
US5742529A (en) *  19951221  19980421  Intel Corporation  Method and an apparatus for providing the absolute difference of unsigned values 
US5880979A (en) *  19951221  19990309  Intel Corporation  System for providing the absolute difference of unsigned values 
US5983257A (en) *  19951226  19991109  Intel Corporation  System for signal processing using multiplyadd operations 
US5793661A (en) *  19951226  19980811  Intel Corporation  Method and apparatus for performing multiply and accumulate operations on packed data 
US5740392A (en) *  19951227  19980414  Intel Corporation  Method and apparatus for fast decoding of 00H and OFH mapped instructions 
US5764943A (en) *  19951228  19980609  Intel Corporation  Data path circuitry for processor having multiple instruction pipelines 
US5835392A (en) *  19951228  19981110  Intel Corporation  Method for performing complex fast fourier transforms (FFT's) 
US6092184A (en) *  19951228  20000718  Intel Corporation  Parallel processing of pipelined instructions having register dependencies 
US5862067A (en) *  19951229  19990119  Intel Corporation  Method and apparatus for providing high numerical accuracy with packed multiplyadd or multiplysubtract operations 
US5898601A (en) *  19960215  19990427  Intel Corporation  Computer implemented method for compressing 24 bit pixels to 16 bit pixels 
US6009191A (en) *  19960215  19991228  Intel Corporation  Computer implemented method for compressing 48bit pixels to 16bit pixels 
US5959636A (en) *  19960223  19990928  Intel Corporation  Method and apparatus for performing saturation instructions using saturation limit values 
US5822232A (en) *  19960301  19981013  Intel Corporation  Method for performing box filter 
US5831885A (en) *  19960304  19981103  Intel Corporation  Computer implemented method for performing division emulation 
US6070237A (en) *  19960304  20000530  Intel Corporation  Method for performing population counts on packed data types 
US5835782A (en) *  19960304  19981110  Intel Corporation  Packed/add and packed subtract operations 
US6049864A (en) *  19960820  20000411  Intel Corporation  Method for scheduling a flag generating instruction and a subsequent instruction by executing the flag generating instruction in a microprocessor 
US5881279A (en) *  19961125  19990309  Intel Corporation  Method and apparatus for handling invalid opcode faults via execution of an eventsignaling microoperation 
US6014684A (en) *  19970324  20000111  Intel Corporation  Method and apparatus for performing N bit by 2*N1 bit signed multiplication 
US6370559B1 (en)  19970324  20020409  Intel Corportion  Method and apparatus for performing N bit by 2*N−1 bit signed multiplications 
US6067034A (en) *  19970407  20000523  Vocal Technologies Ltd.  Maximal bit packing method 
US6081824A (en) *  19980305  20000627  Intel Corporation  Method and apparatus for fast unsigned integral division 
US20040059889A1 (en) *  19980331  20040325  Macy William W.  Method and apparatus for performing efficient transformations with horizontal addition and subtraction 
US20030050941A1 (en) *  19980331  20030313  Patrice Roussel  Apparatus and method for performing intraadd operation 
US6418529B1 (en)  19980331  20020709  Intel Corporation  Apparatus and method for performing intraadd operation 
US7395302B2 (en)  19980331  20080701  Intel Corporation  Method and apparatus for performing horizontal addition and subtraction 
US7392275B2 (en)  19980331  20080624  Intel Corporation  Method and apparatus for performing efficient transformations with horizontal addition and subtraction 
US6961845B2 (en)  19980331  20051101  Intel Corporation  System to perform horizontal additions 
USRE45458E1 (en)  19980331  20150407  Intel Corporation  Dual function system and method for shuffling packed data elements 
US6430251B1 (en) *  20001024  20020806  Sun Microsystems, Inc.  4Bit population count circuit 
US7155601B2 (en)  20010214  20061226  Intel Corporation  Multielement operand subportion shuffle instruction execution 
US20020112147A1 (en) *  20010214  20020815  Srinivas Chennupaty  Shuffle instructions 
US9170815B2 (en)  20011029  20151027  Intel Corporation  Bitstream buffer manipulation with a SIMD merge instruction 
US7685212B2 (en)  20011029  20100323  Intel Corporation  Fast full search motion estimation with SIMD merge instruction 
US10146541B2 (en)  20011029  20181204  Intel Corporation  Processor to execute shift right merge instructions 
US7725521B2 (en)  20011029  20100525  Intel Corporation  Method and apparatus for computing matrix transformations 
US10152323B2 (en)  20011029  20181211  Intel Corporation  Method and apparatus for shuffling data 
US7631025B2 (en)  20011029  20091208  Intel Corporation  Method and apparatus for rearranging data between multiple registers 
US8214626B2 (en)  20011029  20120703  Intel Corporation  Method and apparatus for shuffling data 
US7624138B2 (en)  20011029  20091124  Intel Corporation  Method and apparatus for efficient integer transform 
US8346838B2 (en)  20011029  20130101  Intel Corporation  Method and apparatus for efficient integer transform 
US9477472B2 (en)  20011029  20161025  Intel Corporation  Method and apparatus for shuffling data 
US7739319B2 (en)  20011029  20100615  Intel Corporation  Method and apparatus for parallel table lookup using SIMD instructions 
US7430578B2 (en)  20011029  20080930  Intel Corporation  Method and apparatus for performing multiplyadd operations on packed byte data 
US8510355B2 (en)  20011029  20130813  Intel Corporation  Bitstream buffer manipulation with a SIMD merge instruction 
US20050108312A1 (en) *  20011029  20050519  YenKuang Chen  Bitstream buffer manipulation with a SIMD merge instruction 
US9229719B2 (en)  20011029  20160105  Intel Corporation  Method and apparatus for shuffling data 
US20030123748A1 (en) *  20011029  20030703  Intel Corporation  Fast full search motion estimation with SIMD merge instruction 
US9229718B2 (en)  20011029  20160105  Intel Corporation  Method and apparatus for shuffling data 
US8225075B2 (en)  20011029  20120717  Intel Corporation  Method and apparatus for shuffling data 
US8688959B2 (en)  20011029  20140401  Intel Corporation  Method and apparatus for shuffling data 
US9189237B2 (en)  20011029  20151117  Intel Corporation  Bitstream buffer manipulation with a SIMD merge instruction 
US9189238B2 (en)  20011029  20151117  Intel Corporation  Bitstream buffer manipulation with a SIMD merge instruction 
US8745358B2 (en)  20011029  20140603  Intel Corporation  Processor to execute shift right merge instructions 
US8782377B2 (en)  20011029  20140715  Intel Corporation  Processor to execute shift right merge instructions 
US20110035426A1 (en) *  20011029  20110210  YenKuang Chen  Bitstream Buffer Manipulation with a SIMD Merge Instruction 
US20040054878A1 (en) *  20011029  20040318  Debes Eric L.  Method and apparatus for rearranging data between multiple registers 
US20040054879A1 (en) *  20011029  20040318  Macy William W.  Method and apparatus for parallel table lookup using SIMD instructions 
US9182988B2 (en)  20011029  20151110  Intel Corporation  Bitstream buffer manipulation with a SIMD merge instruction 
US20040133617A1 (en) *  20011029  20040708  YenKuang Chen  Method and apparatus for computing matrix transformations 
US9182985B2 (en)  20011029  20151110  Intel Corporation  Bitstream buffer manipulation with a SIMD merge instruction 
US9182987B2 (en)  20011029  20151110  Intel Corporation  Bitstream buffer manipulation with a SIMD merge instruction 
US9218184B2 (en)  20011029  20151222  Intel Corporation  Processor to execute shift right merge instructions 
US9152420B2 (en)  20011029  20151006  Intel Corporation  Bitstream buffer manipulation with a SIMD merge instruction 
US9170814B2 (en)  20011029  20151027  Intel Corporation  Bitstream buffer manipulation with a SIMD merge instruction 
US7818356B2 (en)  20011029  20101019  Intel Corporation  Bitstream buffer manipulation with a SIMD merge instruction 
US20110029759A1 (en) *  20011029  20110203  Macy Jr William W  Method and apparatus for shuffling data 
US7047383B2 (en)  20020711  20060516  Intel Corporation  Byte swap operation for a 64 bit operand 
US20040010676A1 (en) *  20020711  20040115  Maciukenas Thomas B.  Byte swap operation for a 64 bit operand 
US7260595B2 (en)  20021223  20070821  Arithmatica Limited  Logic circuit and method for carry and sum generation and method of designing such a logic circuit 
US20040153490A1 (en) *  20021223  20040805  Sunil Talwar  Logic circuit and method for carry and sum generation and method of designing such a logic circuit 
US6909767B2 (en)  20030114  20050621  Arithmatica Limited  Logic circuit 
US20040201411A1 (en) *  20030114  20041014  White Benjamin Earle  Logic circuit 
WO2004064254A3 (en) *  20030114  20040910  Arithmatica Ltd  A logic circuit 
WO2004064254A2 (en) *  20030114  20040729  Arithmatica Limited  A logic circuit 
US6904114B2 (en) *  20030425  20050607  J. Barry Shackleford  Ones counter employing two dimensional cellular array 
US20040223580A1 (en) *  20030425  20041111  J. Barry Shackleford  Ones counter employing two dimensional cellular array 
US8914613B2 (en)  20071230  20141216  Intel Corporation  Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a same set of perlane control bits 
US8078836B2 (en)  20071230  20111213  Intel Corporation  Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a common set of perlane control bits 
US9672034B2 (en)  20071230  20170606  Intel Corporation  Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a same set of perlane control bits 
US8560586B2 (en) *  20100329  20131015  Meltin Bell  Linear bit counting implementations 
US20110238717A1 (en) *  20100329  20110929  Meltin Bell  Linear Bit Counting Implementations 
US10146537B2 (en) *  20150313  20181204  Micron Technology, Inc.  Vector population count determination in memory 
Similar Documents
Publication  Publication Date  Title 

Garner  Number systems and arithmetic  
US3316393A (en)  Conditional sum and/or carry adder  
Hasan et al.  A modified MasseyOmura parallel multiplier for a class of finite fields  
Even  Algorithmic combinatorics  
US6692534B1 (en)  Specialized booth decoding apparatus  
Laws et al.  A cellulararray multiplier for GF (2 m)  
EP0066768B1 (en)  Apparatus for generation of random numbers  
US20040267863A1 (en)  Method and apparatus for performing singlecycle addition or subtraction and comparison in redundant form arithmetic  
US4682303A (en)  Parallel binary adder  
US3515344A (en)  Apparatus for accumulating the sum of a plurality of operands  
US3648038A (en)  Apparatus and method for obtaining the reciprocal of a number and the quotient of two numbers  
EP0149248B1 (en)  Method and apparatus for division using interpolation approximation  
US5347482A (en)  Multiplier tree using ninetothree adders  
US4573137A (en)  Adder circuit  
US3723715A (en)  Fast modulo threshold operator binary adder for multinumber additions  
US20030009504A1 (en)  Adder and multiplier circuits employing logic gates having discrete, weighted inputs and methods of performing combinatorial operations therewith  
Lu et al.  A novel division algorithm for the residue number system  
CA1120595A (en)  Sequential galois multiplication in gf(2.sup.n) with gf(2.sup.m) galois multiplication gates  
US4616330A (en)  Pipelined multiplyaccumulate unit  
Swartzlander  The quasiserial multiplier  
US4037093A (en)  Matrix multiplier in GF(2m)  
US4525797A (en)  Nbit carry select adder circuit having only one full adder per bit  
Urbano et al.  A topological method for the determination of the minimal forms of a Boolean function  
EP1025486A4 (en)  Fast regular multiplier architecture  
US4163211A (en)  Treetype combinatorial logic circuit 
Legal Events
Date  Code  Title  Description 

AS  Assignment 
Owner name: LORAL CORPORATION, 600 THIRD AVENUE, NEW YORK, NEW Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:GOODYEAR AEROSPACE CORPORATION;REEL/FRAME:004869/0167 Effective date: 19871218 Owner name: LORAL CORPORATION,NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GOODYEAR AEROSPACE CORPORATION;REEL/FRAME:004869/0167 