US20030213994A1 - Thin film memory, array, and operation method and manufacture method therefor - Google Patents

Thin film memory, array, and operation method and manufacture method therefor Download PDF

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US20030213994A1
US20030213994A1 US10/410,239 US41023903A US2003213994A1 US 20030213994 A1 US20030213994 A1 US 20030213994A1 US 41023903 A US41023903 A US 41023903A US 2003213994 A1 US2003213994 A1 US 2003213994A1
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thin film
semiconductor region
electric potential
semiconductor
gate
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Yutaka Hayashi
Hisashi Hasegawa
Yoshifumi Yoshida
Jun Osanai
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/908—Dram configuration with transistors and capacitors of pairs of cells along a straight line between adjacent bit lines

Definitions

  • the present invention relates to a semiconductor memory and an integrated circuit built therefrom, and more specifically, to a technique which uses for a channel formation region a semiconductor thin film such as SOI (Semiconductor On Insulator) or SON (Semiconductor On None).
  • SOI semiconductor On Insulator
  • SON semiconductor On None
  • the semiconductor thin film is formed on an insulating substrate (SOI) in some cases, is suspended and held at both ends by substrates in a hollow state (SON) in some other cases, and has a projecting portion which is connected at one end to a substrate in still other cases.
  • PD SOI partially depleted SOI
  • PD SOI SOI in which a depletion layer spreads only partially in the depth direction of its semiconductor thin film to give it a neutral region.
  • Body is a simplified term for the above semiconductor thin film in which a channel is formed.
  • FD SOI fully depleted SOI
  • FD SOI fully depleted SOI
  • the term FD (fully depleted) SOI refers to SOI having such thickness and impurity concentration that makes the depletion layer cover the entire depth of the semiconductor thin film.
  • the method of utilizing carrier multiplication in a drain high electric field portion also causes carrier multiplication of a small degree in a not-selected cell which is connected to a bit line for driving at high voltage a drain of a cell to which a signal is to be written. This leads to erroneous, albeit mild, writing called write disturb and thereforemakes it difficult to assemble a large array in which a large number of cells are connected to each bit line.
  • the present invention has been made in view of the above, and an object of the present invention is therefore to provide a capacitor-less SOI or other semiconductor thin film memory cell and memory cell array which are applicable to FDSOI. Another object of the present invention is to provide an SOI or other semiconductor thin film memory cell and memory cell array in which data is written or erased without using carrier multiplication in a drain high electric field portion, as well as an operation method and manufacture method for the memory cell and array.
  • the present invention employs a method of supplying carriers from a third semiconductor region, which is not a drain or a source, ( 1 ) to a body ( 2 ) without using carrier multiplication in a drain high electric field portion.
  • FIG. 1 is a sectional view showing a principle of the present invention
  • FIGS. 2A and 2B are a plan view showing an embodiment of the present invention and a sectional view thereof, respectively;
  • FIG. 3 is a plan view showing another embodiment of the present invention in which a first conductive gate and a second conductive gate are continuous;
  • FIGS. 4A and 4B are a plan view and a sectional view, respectively, showing another embodiment of the present invention in which a third conductive gate is placed on a second principal surface of a semiconductor thin film;
  • FIGS. 5A and 5B are a plan view of an embodiment in which memory cells of the present invention are arranged and connected to form an array structure and a sectional view of a cell portion, respectively;
  • FIGS. 6A to 6 G are sectional views showing an example of a process of manufacturing the memory cells and array of the embodiment shown in FIGS. 5A and 5B;
  • FIG. 7 is an equivalent circuit diagram of the memory cell array shown in FIGS. 5A and 5B;
  • FIG. 8 is a plan view of memory cells and array in which a writing bit line and a reading bit line are shared.
  • FIG. 9 is an equivalent circuit diagram of the memory cell array of FIG. 8.
  • FIG. 1 is an example of a sectional view thereof.
  • FIG. 2A is an example of a plan view thereof and
  • FIG. 2B is a sectional view taken along the line X-X′ of FIG. 2A.
  • the memory cell includes:
  • a semiconductor thin film 100 having a first principal surface 101 and a second principal surface 102 that faces the first principal surface;
  • a first semiconductor region 110 and a second semiconductor region 120 which face each other across the first conductive gate, which are insulated from the first conductive gate, which are in contact with the semiconductor thin film 100 , and which have a first conductivity type;
  • a third semiconductor region 130 which has the opposite conductivity type and which is in contact with the semiconductor thin film.
  • the semiconductor thin film 100 has such a combination of thickness and impurity concentration relation that the first conductive gate electric potential causes depletion of carriers between the first principal surface 101 and the second principal surface 102 between the first and second semiconductor regions below the first conductive gate.
  • the semiconductor thin film is extended to the third semiconductor region 130 from a semiconductor thin film portion which is sandwiched between the first semiconductor region 110 and the second semiconductor region 120 and which is denoted by 103 , and on the extended portion of the semiconductor thin film which is denoted by 104 , a second gate insulating film 320 is formed and a second conductive gate is formed on the second gate insulating film 320 .
  • reference symbol 421 represents an inter-gate insulating film which is provided, if necessary, to insulate the first conductive gate and the second conductive gate.
  • Denoted by 400 is a so-called field insulating film.
  • 413 and 431 represent an insulating film formed on the third semiconductor region and an insulating film on the first conductive gate, respectively.
  • 113 , 123 , 133 , 313 , and 323 are provided, if necessary, to serve as contacts leading to the first, second, and third semiconductor regions and contacts leading to the first and conductive gates.
  • FIG. 1 corresponds to a sectional view taken along the line Y-Y′ in FIG. 2A. It is not always necessary for each cell to have the above contacts. In particular, a contact leading to a conductive gate can be shared among a large number of cells since a conductive gate often constitutes a part of a word line.
  • a first conductivity type channel is induced in the semiconductor thin film portion 103 that is sandwiched between the first semiconductor region 110 and the second semiconductor region 120 by the electric potential exceeding the gate threshold voltage of the first conductive gate.
  • the semiconductor thin film portion 103 is called a first channel formation semiconductor thin film portion.
  • the semiconductor thin film extended portion 104 carriers of the opposite conductivity type are induced, or a channel for carriers of the opposite conductivity type is formed by the electric potential relation between the second conductive gate and the third semiconductor region.
  • the extended portion 104 is called in the present invention as a second channel formation semiconductor thin film portion.
  • a portion 105 which is different in conductivity type or impurity concentration from the extended portion 104 may be formed in the extended portion 104 in order to adjust the gate threshold voltage of the opposite conductivity type carrier channel which is viewed from the second conductive gate.
  • the above expression ‘electric potential exceeding the gate threshold voltage’ means an electric potential whose absolute value is larger than the gate threshold voltage in the positive direction if the transistor is an n-channel transistor and an electric potential whose absolute value is larger than the gate threshold voltage in the negative direction if the transistor is a p-channel transistor.
  • the distance between the first principal surface and the second principal surface is called in the present invention as the thickness of the semiconductor thin film.
  • a value obtained by subtracting the electric potential of the third semiconductor region from the electric potential of the second conductive gate exceeds a gate threshold voltage Vth 2r of the channel that is placed in the second channel formation semiconductor thin film portion to deliver the opposite conductivity type carriers from the third semiconductor region.
  • Vth 2r is the gate threshold voltage viewed from the second conductive gate.
  • a gate voltage necessary for the first conductive gate to induce the first conductivity channel is reduced by a level corresponding to the number of the implanted carriers of the opposite conductivity type or electric charges. This means that the gate threshold voltage has shifted toward the depression side equivalently. If the gate threshold voltage changes in an enhancement type range, it means that the absolute value of the gate threshold voltage is reduced.
  • the first electric potential combination allows multilevel setting. For example, on the premise that a value obtained by subtracting the electric potential of the third semiconductor region from the electric potential of the second conductive gate sufficiently exceeds a gate threshold voltage Vth 2r of the channel that is placed in the second channel formation semiconductor thin film portion to deliver the opposite conductivity type carriers from the third semiconductor region which is viewed from the second conductive gate, the electric potential of the third semiconductor region with respect to the gate electric potential is set to multilevel.
  • This makes it possible to change the gate threshold voltage of the first conductive channel which is viewed from the first conductive gate into multilevel values Vth 11 , Vth 12 , Vth 13 . . . for writing. In short, this makes it possible to store plural bit information in one cell.
  • the opposite conductivity type carriers 2 implanted into the first channel formation semiconductor thin film portion gradually diminish because of recombination with carriers of the first conductivity type or efflux from the first channel formation semiconductor thin film portion due to self-field. Accordingly, it is necessary to read the amount of opposite conductivity carriers accumulated in the first channel formation semiconductor thin film portion and re-write based on the readout. This is called ‘refreshing’.
  • the carriers 2 of the opposite conductivity type are drawn into the third semiconductor region from the first channel formation semiconductor thin film portion to change the gate threshold voltage of the first conductive channel in the first channel formation semiconductor thin film portion which is viewed from the first conductive gate into a second value Vth 10 .
  • This operation is called ‘erasing’ in the present invention.
  • the erasing operation is achieved by giving an electric potential of a direction that attracts carriers of the opposite conductivity type to the first or second semiconductor region (for instance, 0.6 V or higher in the negative direction for holes).
  • carries of the first conductivity type are also supplied to the first channel formation semiconductor thin film portion to accelerate a decrease of carriers of the opposite conductivity type through recombination.
  • data is erased from every cell whose second semiconductor region or first semiconductor region is connected to a common line or bit line.
  • Information stored in a memory cell of the present invention is judged by whether or not carriers of the opposite conductivity type are accumulated in the first channel formation semiconductor thin film portion of the memory cell or from the accumulation amount.
  • the voltage of the first conductive gate with respect to the second semiconductor region is set to a prescribed value that exceeds one or both of the first gate threshold voltage and the second gate threshold voltage and whether a current flowing between the first semiconductor region and the second semiconductor region is large or small is detected (‘small’ including zero).
  • the voltage of the first conductive gate with respect to the second semiconductor region is set to a level between the first gate threshold voltage and the second gate threshold voltage and whether or not a current flows between the first semiconductor region and the second semiconductor region is detected to judge the stored information.
  • the voltage of the first conductive gate is set to a level between any two out of those levels to identify the stored data.
  • the voltage of the first conductive gate with respect to the second semiconductor region is set to a voltage that exceeds both the first gate threshold voltage and the second gate threshold voltage and the stored information is judged from the amount of current flowing between the first semiconductor region and the second semiconductor region.
  • a known method such as comparative detection using a reference current and a comparative circuit, or detection by time constant of charging or discharging a bit line or other capacitance can be employed. This operation is called ‘reading’.
  • the electric potential of the valence band or conduction band in the energy band of the first channel formation semiconductor thin film portion is moved in a direction that eliminates carriers of the opposite conductivity type.
  • a large amount of first conductivity type carriers are supplied to first channel formation semiconductor thin film portion to accelerate recombination of opposite conductivity type carriers accumulated in the first channel formation semiconductor thin film portion and to cause information loss in some cases.
  • the refreshing operation has to be conducted immediately after reading.
  • the semiconductor thin film 100 in FIG. 1 is supported by a substrate 10 having an insulating layer 20 formed on its surface.
  • the substrate 10 is formed of silicon and the insulating layer 20 is a silicon oxide film.
  • the supporting substrate that has an insulating layer on its surface is called an insulating substrate.
  • An insulating substrate that is entirely formed of an insulating material, such as a quartz substrate, can also serve as the supporting substrate.
  • An alternative structure is that at least one end of the semiconductor thin film, or an end of the first semiconductor region, the second semiconductor region, or the third semiconductor region, is supported by a substrate.
  • the present invention if voltages of the first conductive gate and the second conductive gate during the writing, erasing, and reading operations are chosen carefully, the same voltage can be used for each operation mode. Then the first and second conductive gates can be made continuous or shared as FIG. 3 shows its example. Furthermore, the same material and thickness can be employed for the gate insulating films. As a result, the number of manufacture steps and the area the cell occupies are reduced. In this case, by replacing the ‘second conductive gate’ in the description on the writing and erasing operations of the present invention with the ‘first conductive gate’, it becomes possible to realize the writing and erasing operations.
  • the first gate threshold voltage value is written when a value obtained by subtracting the electric potential of the third semiconductor region from the electric potential of the second conductive gate sufficiently exceeds a gate threshold voltage Vth 2r of the channel that is placed in the second channel formation semiconductor thin film portion to deliver the opposite conductivity type carriers from the third semiconductor region which is viewed from the second conductive gate while the electric potential of the third semiconductor region is biased forward with respect to the electric potential of the second semiconductor region.
  • the second gate threshold voltage is written (equals to erasing) when the electric potential of the third semiconductor region is zero-biased or biased backward with respect to the second gate voltage.
  • FIGS. 4 A and 4 B Another mode of a preferred memory cell for effectively carrying out the present invention is a memory cell shown in FIGS. 4 A and 4 B.
  • the memory cell is characterized by including at least:
  • a semiconductor thin film (broken into portions 103 and 104 ) having a first principal surface 101 and a second principal surface 102 that faces the first principal surface;
  • a first semiconductor region 110 and a second semiconductor region 120 which face each other across the first conductive gate, which are insulated from the first conductive gate, which are in contact with the semiconductor thin film, and which have a first conductivity type;
  • a third semiconductor region 130 which has the opposite conductivity type and which is in contact with the semiconductor thin film;
  • a third conductive gate 330 which is in contact with the third gate insulating film 230 .
  • the semiconductor thin film portion 104 is also called as a second channel formation semiconductor thin film portion in the present invention.
  • Carriers of the opposite conductivity type are stably accumulated in the first channel formation semiconductor thin film portion if the third conductive gate is given an electric potential exceeding a gate threshold voltage Vth 3r , which is the gate threshold voltage viewed from the third conductive gate with respect to opposite conductivity type carriers induced in the first channel formation semiconductor thin film portion.
  • Vth 3r the gate threshold voltage viewed from the third conductive gate with respect to opposite conductivity type carriers induced in the first channel formation semiconductor thin film portion.
  • the refreshing operation is necessary in this case too, for carriers of the opposite conductivity type are gradually generated and accumulated in the first channel formation semiconductor thin film portion by thermal excitation, slight carrier multiplication in normal electric field, and the like after the erasing operation.
  • FIG. 4A is a plan view of the thin film memory cell of the above embodiment and FIG. 4B is a sectional view taken along the dot-dash line X-X′ of the plan view of FIG. 4B.
  • reference symbol 10 denotes a supporting substrate and 20 , an insulating film on a surface of the supporting substrate 10 .
  • Denoted by 103 and 104 are the first and second channel formation semiconductor thin film portions, respectively, which are a part of the semiconductor thin film 100 .
  • 210 and 220 represent gate insulating films formed on the semiconductor thin film portions 103 and 104 .
  • the gate insulating films 210 and 220 in the drawing are continuous.
  • Denoted by 310 is the first conductive gate, which is also continuous from the second conductive gate.
  • 110 and 120 are the first and second semiconductor regions, respectively. 130 denotes the third semiconductor region.
  • 113 and 123 represent wiring contacts leading to the first and second semiconductor regions, respectively.
  • 133 represents a wiring contact leading to the third semiconductor region.
  • Denoted by 400 is a so-called field insulating film which is placed under a wire or the like.
  • 431 denotes an insulating film placed on the first conductive gate, and 410 , an insulating film placed between the semiconductor thin film 100 and the insulating film 20 .
  • 313 denotes a wiring contact leading to the first conductive gate.
  • 333 denotes a wiring contact provided, if necessary, to lead to the third conductive gate.
  • each cell it is not always necessary for each cell to have the above contacts.
  • a contact leading to a conductive gate can be shared among a large number of cells since a conductive gate often constitutes a part of a word line.
  • An impurity region 105 is not always necessary if the electric field of the third conductive gate influences the portion 104 less than the portion 103 (in other words, if the third conductive gate does not overlap the portion 104 as shown in FIG. 4B or if the third conductive film overlaps the portion 104 while an insulating film thicker than the film 230 is sandwiched between the two).
  • the first and second conductive gates can have different gate threshold voltages if the conductivity type of an impurity or impurity concentration of the second channel formation semiconductor thin film portion, or the second conductive gate material is different from the conductivity type of an impurity or impurity concentration of the first channel formation semiconductor thin film portion, or the first conductive gate material.
  • Opposite conductivity type carriers implanted to the second channel formation semiconductor thin film portion is prevented from flowing back to the third semiconductor region if the gate threshold voltage of the second conductive gate with respect to the channel for opposite conductivity type carriers from the third semiconductor region is set to a level further in the enhancement type direction than the gate threshold voltage of the first conductive gate.
  • FIG. 5A is a plan view of an embodiment of memory cells of the present invention and an array of the memory cells.
  • FIG. 5B is a sectional view taken along the dot-dash line X-X′ of the plan view of FIG. 5A.
  • Reference symbol 10 denotes a supporting substrate, which, in this example, is an n type silicon ⁇ 100> plane wafer of high resistance.
  • Denoted by 20 is a silicon oxide film with a thickness of about 100 nm.
  • 103 represents a semiconductor thin film about 30 nm in thickness which serves as a first channel formation semiconductor thin film portion of a thin film memory cell 1000 of this embodiment.
  • 104 represents a second channel formation semiconductor thin film portion.
  • 105 represents a high impurity concentration portion in the second channel formation semiconductor thin film portion.
  • 110 represents a drain (first semiconductor region).
  • 114 is a drain extension.
  • 120 is a source (second semiconductor region).
  • 124 represents a source extension.
  • 130 is a third semiconductor region of the opposite conductivity type.
  • 210 is a first gate oxynitride film with a thickness of 2.7 nm.
  • 220 is a second gate oxynitride film.
  • 310 and 320 are a first conductive gate and a second conductive gate that is continuous from the first conductive gate.
  • 300 is a symbol as a conductive gate thin film.
  • 1001 is a functional symbol as a local (partial) word line.
  • 210 and 220 are continuous gates.
  • the first conductive gate is about 100 nm in length and, in this embodiment, is formed from a silicon thin film doped with boron.
  • the first, second, and third semiconductor regions include a semiconductor film that is formed on the semiconductor thin film through epitaxial growth.
  • the first and second channel formation semiconductor thin film portions 103 and 104 in one cell are separated from the first and second channel formation semiconductor thin film portions 103 and 104 in an adjacent cell by a separation insulating film 401 .
  • 113 Denoted by 113 is a contact leading to the first semiconductor region, and the contact is connected to a reading bit line 1005 .
  • 113 represents a contact leading to the third semiconductor region and the contact is connected to a writing bit line 1004 .
  • the continuous first and second conductive electrodes 310 ( 320 ) are continuously extended between cells in the word direction, thereby forming a partial common line 1001 .
  • the second semiconductor region is extended between cells in the word direction, thereby forming a partial common line 1003 .
  • the partial word line and the partial common line are extended as long as the direct resistance does not affect the array operation, and are respectively connected to a global word line and a global common line through a selection transistor or directly. In a large capacitance array, the above two types of bit lines are also connected to their respective global bit lines through a selection transistor.
  • FIG. 5A shows two cells in the word direction and four cells in the bit direction, eight cells in total (a cell 1000 (j, k), . . . , a cell 1000 (j+1, k+3)).
  • the mirror image arrangement of cells is also employed in an embodiment of FIG. 8 which will be described later.
  • a highly resistive silicon wafer is used as a supporting substrate 10 and a silicon oxide film 20 with a thickness of about 100 nm and a silicon thin film 100 which has an n type impurity concentration of about 2 ⁇ 10 17 atoms/cc and which has a thickness of about 35 nm are layered on the substrate to prepare an SOI substrate.
  • an oxide film 41 is let grow until it reaches a thickness of about 7 nm by thermal oxidation and a silicon nitride film 42 with a thickness of about 50 nm is formed thereon by CVD. Thereafter, a photoresist pattern 51 is formed by known photolithography to leave necessary portions of the silicon thin film such as regions where memory cells are connected in the word direction and the bit direction, selection transistor regions, and peripheral circuit regions.
  • the silicon nitride film is etched under etching conditions that provide a selective ratio with respect to the silicon oxide film.
  • the photoresist pattern is then removed and the substrate surface is cleaned.
  • the exposed surface of the silicon oxide film which is exposed by the removal of the silicon nitride film is oxidized by pyrogenic oxidation until a silicon oxide film 401 grows to a thickness of about 60 nm.
  • the silicon thin film 100 is divided into pieces leaving the necessary portions given in the above.
  • STI shallow trench isolation
  • the silicon nitride film 42 is removed by a hot phosphoric acid-based etchant and the silicon oxide film 41 is removed by a buffer hydrofluoric acid-based etchant to expose the surface of the silicon thin film 100 .
  • a silicon oxide film 200 is formed on the surface of the silicon thin film 100 by thermal oxidation to a thickness of 2.7 nm. Thereafter, ECR (Electron Cyclotron Resonance), ICP (Inductively Coupled Plasma), or like other high density plasma apparatus is used for surface nitrogenization at a nitrogenization ratio of 5 to 7% by introducing nitrogen radical from plasma of nitrogen gas, hydrogen gas, or xenon gas to the substrate surface and setting the substrate temperature to 400° C. Then the substrate is transferred in a highly pure nitrogen gas atmosphere and subjected to heat treatment at 800° C. in nitrogen to anneal surface defects. The silicon oxide film thus nitrigenized is used as the first and second gate oxide films.
  • a conductive gate thin film 300 is formed by deposition.
  • pure silicon is deposited to form a pure silicon thin film 301 .
  • a boron-doped silicon thin film 302 is formed by deposition to a thickness of 200 nm.
  • the material gas used are mono-silane (SiH 4 ) and di-borane (B 2 H 6 )
  • a silicon nitride film 43 is formed thereon by deposition to a thickness of about 100 nm. Ion implantation may be employed for the above boron doping.
  • a gate-shaped photoresist pattern for a conductive gate/local word line having a gate length of about 100 nm is formed on the above silicon nitride film/conductive gate thin film.
  • the photoresist pattern is used as a mask to etch the silicon nitride film and the conductive gate thin film in order by the RIE technique.
  • a photoresist film shaped by photolithography and the silicon nitride film/conductive gate thin film are used as selection masks to selectively form, by ion implantation at low acceleration voltage (about 15 KeV for arsenic), an extension region ( 114 ) of the n type drain (the first semiconductor region) and an extension region ( 124 ) of the source (the second semiconductor region).
  • the dose is set so as to obtain an impurity concentration of about 1 ⁇ 10 19 atoms/cc (which is about 3 ⁇ 10 13 atoms/cm 2 ).
  • a photoresist film shaped by photolithography and the silicon nitride film/conductive gate thin film are used as selection masks to selectively implant arsenic in the portion that forms the third semiconductor region at a dose of about 8.5 ⁇ 10 12 atoms/cc.
  • a high impurity concentration region 105 is thus formed in the second channel formation semiconductor thin film portion so that it is in contact with the third semiconductor region formed in the subsequent step. This shifts the gate threshold voltage Vth 2r of the channel for holes from the third semiconductor region which is viewed from the second conductive gate to the enhancement side.
  • insulating film side walls 403 each having a thickness of about 30 nm are formed on the side faces of the first and second conductive gates.
  • the side walls are a two-layer laminate consisting of a silicon nitride film 404 with a thickness of about 7 nm and a silicon oxide film 405 with a thickness of about 23 nm. At this stage, the silicon nitride film 404 is left on the semiconductor thin film.
  • Lithography is used to form a photoresist pattern having an opening in the portion where the third semiconductor region is to be formed.
  • a portion of the silicon nitride film 404 under the opening is etched by RIE. Then the photoresist is removed and the silicon oxide film remaining in the opening is subjected to wet etching, followed by hydrogen termination.
  • a boron-doped silicon crystal film 135 is selectively grown in the opening until it reaches a thickness of about 100 nm.
  • the boron concentration is about 4 ⁇ 10 19 atoms/cc.
  • an oxide film 406 with a thickness of about 30 nm is let grow on the top and side faces of the p type silicon crystal film.
  • boron is diffused at this point from the silicon crystal film 135 into the semiconductor thin film 100 to give a portion of the semiconductor thin film that is under 135 the p type conductivity. In FIG. 6E, the portion is distinguished from the silicon crystal film selectively grown.
  • Arsenic-doped silicon crystal films 115 and 125 are selectively grown in the opening to a thickness of about 100 nm each.
  • the arsenic concentration is about 5 ⁇ 1020 atoms/cc.
  • the oxide film 406 on the side face separates the p type high impurity concentration silicon crystal film 135 from the n type high impurity concentration silicon crystal films 115 and 125 .
  • a silicon oxide film is formed as a wiring interlayer insulating film 440 by CVD on the surface. Contact holes are opened in the film as needed and contact plugs 133 and 113 are formed from titanium nitride, tungsten, or the like. Then a TiN thin film and a tungsten thin film are formed by evaporation. A wiring pattern is formed by photolithography and RIE (reactive ion etching) to obtain a local writing bit line 1004 and a local reading bit line 1005 (at this point, the state of FIG. 5B is reached) Thereafter, an interlayer insulating film and a multi-layer wire composed of an Al wire, a copper wire or the like are formed as needed and, lastly, a passivation film is formed.
  • RIE reactive ion etching
  • the features of this embodiment are (1) that the third semiconductor region and the first semiconductor region are insulated by the insulating film 406 formed on the side face of the crystal thin film that is obtained by selective epitaxial growth and (2) that the gate threshold voltage for inducing carriers of the opposite type differs from the first channel formation semiconductor thin film portion to the opposite conductivity type carrier channel which leads to the first channel formation semiconductor thin film portion from the third semiconductor region.
  • the opposite conductivity type carrier channel which leads to the first channel formation semiconductor thin film portion from the third semiconductor region crosses the high impurity concentration region 105 in contact with the first channel formation thin film portion, the impurity concentration of the second channel formation thin film portion differs from that of the first channel formation thin film portion.
  • the gate threshold voltage which induces the carriers of the opposite conductivity type differs between the first channel formation thin film portion and the opposite conductivity type carrier channel which leads to the first channel formation semiconductor thin film portion from the third semiconductor region.
  • the first semiconductor regions of cells arranged in the longitudinal direction are connected to the reading bit line 1005 and the third semiconductor regions of these cells are connected to the writing bit line 1004 .
  • the first and second common conductive gates of cells arranged in the lateral direction are connected to the word line 1001 .
  • the second semiconductor regions of the cells arranged in the lateral direction are connected to the common line 1003 .
  • the reading bit line and the writing bit line extend in the longitudinal direction whereas the word line and the common line stretch in the lateral direction. Alignment of cells and the vertical and horizontal relation of the bit line and the word line can be reversed without causing any problem.
  • Vth r2 is about ⁇ 0.5 V when the electric potential of the second semiconductor region is 0 V and therefore it is desirable to set the electric potential of the third semiconductor region to 0.2 to 0.3 V while setting the second conductive gate to ⁇ 0.3 to —0.4 V.
  • setting the first conductive gate to 0 to 0.2 V and giving the first semiconductor region the same electric potential as the second semiconductor region are desirable.
  • the second semiconductor region is set to ⁇ 0.6 V or lower (when the electric potential of the first semiconductor region is 0 V and the first conductive gate is 0 V), or the electric potential of the third semiconductor region is set to 0 to ⁇ 0.4 V and the electric potential of the second conductive gate is set to ⁇ 0.55 V or lower.
  • opposite conductivity type carriers (holes) accumulated in the first channel formation semiconductor thin film portion are drawn into the second semiconductor region or into the third semiconductor region.
  • the intermediate current value between the current of a cell to which data is written and the current of a cell from which data is erased is taken to serve as the criterion.
  • a voltage between one stored threshold voltage and another stored threshold voltage is applied to the first conductive gate, information is judged from the presence or absence of the cell current.
  • Embodiment 1 cells of the present invention in FIGS. 5A and 5B are connected as shown in an equivalent circuit diagram of FIG. 7 to obtain a memory array.
  • the memory array is operated by combination of voltages shown in Table 1 below.
  • This array is suitable as a memory for a specific use because data can be written in cells of a word while data is read from cells of another word.
  • the array is also suited for high speed refreshing operation.
  • Table 1 shows the voltage relation among the word line, the writing bit line, the reading bit line, and the common line when the array is operated by a unipolar power supply of 1.2 V. Operation on a unipolar power supply is made possible by biasing the common line at a positive electric potential, usually, 0.5 V.
  • the third semiconductor region and the first semiconductor region are connected to the same bit line (one bit line doubles as a writing bit line and a reading bit line in the memory array of FIGS. 5A and 5B).
  • FIG. 8 is a plan view of memory cells used in this array connection and the cell area thereof is 6F 2 to 4F 2 . To achieve a cell area of 4F 2 , a self-alignment contact technique is needed.
  • the cell arrangement in the array of FIG. 8 is similar to the one in FIGS. 5A and 5B; the conductive gates in one cell are above the first, second, and third semiconductor regions and this positional relation is reversed in every other cell in the longitudinal direction while the first, second, and third semiconductor regions in one cell are continuous with those in its adjacent cells in the vertical direction.
  • the first and third semiconductor regions of the k-th cell in the longitudinal direction are continuous with those in the (k+1)-th cell.
  • the second semiconductor region of the j-th cell is continuous with that of the (j+1)-th cell.
  • the first semiconductor region in one cell and the first semiconductor region in a cell adjacent to the one cell in the word direction are electrically insulated from each other by the third semiconductor region of their adjacent cell with respect to backward bias and a slight forward voltage.
  • the semiconductor thin film 100 extending in the word direction which includes the first semiconductor region and the third semiconductor region is physically continuous.
  • the first semiconductor regions in adjacent cells in the word direction are separated by an insulating film.
  • FIGS. 5A and 5B can also take a structure in which the semiconductor thin film is continuous on the first semiconductor region side too and the first semiconductor region is electrically insulated by the third semiconductor region.
  • the first channel formation semiconductor thin film portion or the second channel formation semiconductor thin film portion of one cell is separated from that of a cell adjacent to the one cell in the word direction.
  • the first conductive gate and the second conductive gate are continuous and are further continued to the first or second conductive gate of a cell adjacent in the lateral direction.
  • the gate has a series resistance component and therefore limits the operation speed.
  • a metal wire is used as a main word line and is connected to the conductive gates of a group of-cells (for example, 32 to 512 cells form one group) before the series resistance reaches the limit value.
  • Embodiment 2 cells of the present invention in FIG. 8 are connected as shown in an equivalent circuit diagram of FIG. 9 to obtain a memory array.
  • the memory array of Embodiment 2 is operated by combination of voltages shown in Table 3 below.
  • Table 3 shows an example of the voltage relation among the word line, the bit line, and the common line when the array is operated by a unipolar power supply of 1 V. Operation on a unipolar power supply is made possible by biasing the common line at a positive electric potential, usually, 0.5 V.
  • the word line voltage upon reading is supplied before the bit line voltage.
  • An acceptable change in voltage of one line is within ⁇ 0.1 V when the voltage of another line has the standard value. If the voltage of every line is changed in the same direction, the acceptable electric potential change is larger.
  • the semiconductor thin film may be a silicon germanium single crystal thin film or a strained silicon/silicon germanium laminate other than a silicon single crystal thin film.
  • the gate insulating film may be a silicon oxynitride film, a silicon nitride film, an alumina film, a hafnium oxide film, a film of a silicon-hafnium oxide mixture, a zirconium oxide film, or a film of a silicon-zirconium oxide mixture other than a silicon oxide film.
  • the conductive gates may be a tungsten film, a titanium nitride film, or a titanium/titanium nitride laminate other than a polysilicon film or a silicon germanium film.
  • the first, second, and third semiconductor regions may be formed not only in the semiconductor thin film but also on top of the semiconductor thin film, and a metal silicide film or a metal thin film may be added thereon to form a laminate.
  • a metal silicide film or a metal thin film may be added thereon to form a laminate.
  • the first, second, and third semiconductor regions are described in this specification as “being in contact with” the semiconductor thin film. This contact state is obtained either by introducing impurity atoms into the semiconductor thin film and forming the first, second, and third semiconductor regions in the film or by forming the first, second, and third semiconductor regions on the semiconductor thin film by deposition.
  • the present invention may employ a structure for capacitance coupling of the second principal surface or the side face to the first channel formation semiconductor thin film portion, so that data stored is kept longer and the amount of opposite conductivity type carriers accumulated is increased.
  • the present invention is applicable to both PDSOI and FDSOI and, when applied to FDSOI, the present invention can provide effects that have been difficult to attain in prior art.
  • the present invention can provide a memory cell having the FDSOIMOS structure and the FDSONMIS structure as well as the PDSOIMIS structure, and a memory array using the memory cell.
  • the memory cell does not need a large capacitor.
  • the memory can be mounted together with FDSOI logic that is capable of low power operation, and the operation voltage of the memory is in a range that matches the range of the low power logic.
  • the cell takes a so-called double gate MIS structure, carriers of the opposite conductivity type are securely accumulated in the memory cell by the electric potential given to the third conductive gate of the cell.

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