US20020132416A1 - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

Info

Publication number
US20020132416A1
US20020132416A1 US09/922,786 US92278601A US2002132416A1 US 20020132416 A1 US20020132416 A1 US 20020132416A1 US 92278601 A US92278601 A US 92278601A US 2002132416 A1 US2002132416 A1 US 2002132416A1
Authority
US
United States
Prior art keywords
semiconductor substrate
film
substance
source
drain regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US09/922,786
Other languages
English (en)
Inventor
Yasuo Gamo
Koji Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Monterey Research LLC
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Assigned to FUJITSU LIMITED reassignment FUJITSU LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GAMO, YASUO, TAKAHASHI, KOJI
Publication of US20020132416A1 publication Critical patent/US20020132416A1/en
Priority to US10/986,652 priority Critical patent/US7084037B2/en
Assigned to MONTEREY RESEARCH, LLC reassignment MONTEREY RESEARCH, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CYPRESS SEMICONDUCTOR CORPORATION
Assigned to CYPRESS SEMICONDUCTOR CORPORATION reassignment CYPRESS SEMICONDUCTOR CORPORATION RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: MORGAN STANLEY SENIOR FUNDING, INC.
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
    • H01L21/3144—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
    • H01L21/3145—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers formed by deposition from a gas or vapour

Definitions

  • the present invention relates to semiconductor devices provided between semiconductor substrates and gate electrodes with multilayer films each including an insulating film having a charge trap function and sandwiched by upper and lower insulating films, and methods of manufacturing the same.
  • a semiconductor memory which includes an impurity diffusion layer formed in a semiconductor substrate to serve as bit lines (buried bit lines), and word lines formed over the semiconductor substrate with a capacitive insulating film being interposed between them, so as to run perpendicularly to the bit lines.
  • the structure can be simpler than a two-layer electrode structure such as an EEPROM and is expected to cope with further size reduction and micropatterning of elements.
  • the capacitive insulating film preferably has a multilayer structure made up from at least three layers, in which an insulating film having a charge trap function, such as a silicon nitride film, is sandwiched by upper and lower insulating films, such as silicon oxide films.
  • an insulating film having a charge trap function such as a silicon nitride film
  • upper and lower insulating films such as silicon oxide films.
  • the multilayer film known is a structure of silicon oxide film/silicon nitride film/silicon oxide film, i.e., a so-called ONO film, in which a silicon nitride film having a charge trap function is sandwiched by upper and lower silicon oxide films.
  • a silicon oxide film 111 , a silicon nitride film 112 , and a silicon oxide film 113 are sequentially stacked in this order in an active region on, e.g., a p-type silicon semiconductor substrate 101 to form an ONO film 102 .
  • n-type impurities such as arsenic are ion-implanted into a surface layer of the semiconductor substrate 101 using the resist pattern 103 as a mask under such conditions that the ions can pass through the ONO film 102 .
  • the resist pattern 103 is then removed through an ashing process or the like, and the semiconductor substrate 101 is annealed, thereby forming buried bit lines 104 that serve also as sources and drains.
  • an electrode material is deposited onto the ONO film 102 and patterned to form word lines 105 that cross the buried bit lines 104 with the ONO film 102 being interposed between them.
  • the word lines 105 serve also as gate electrodes.
  • an ONO film 102 is formed in an active region on, e.g., a p-type silicon semiconductor substrate 101 .
  • a resist pattern 103 is formed on the ONO film 102
  • the upper silicon oxide film 113 and the silicon nitride film 112 of the ONO film 102 are patterned using the resist pattern 103 as a mask, thereby leaving only the lowermost silicon oxide film 111 as it is.
  • Impurities of n-type such as arsenic are then ion-implanted into a surface layer of the semiconductor substrate 101 using the resist pattern 103 as a mask under such conditions that the ions can pass through the lowermost silicon oxide film 111 .
  • the resist pattern 103 is then removed, and the semiconductor substrate 101 is annealed in an oxidative atmosphere, thereby forming buried bit lines 104 that serve also as sources and drains.
  • accelerated oxidation occurs at portions of the silicon oxide film 111 above the bit lines 104 through the annealing process due to the presence of arsenic ions in the semiconductor substrate 101 .
  • the silicon oxide film 111 thereby has a thickness of about 40 to 60 nm at those portions.
  • an electrode material is then deposited and patterned to form word lines 105 that cross the buried bit lines 104 with the silicon oxide film 111 being interposed between them.
  • the word lines serve also as gate electrodes.
  • bit lines are formed with a thick silicon oxide film provided. thereon.
  • a thin sacrificial oxide film 106 is formed in an active region on, e.g., a p-type silicon semiconductor substrate 101 .
  • n-type impurities such as arsenic are ion-implanted into a surface layer of the semiconductor substrate 101 using the resist pattern 103 as a mask under such conditions that the ions can pass through the sacrificial oxide film 106 .
  • the resist pattern 103 is then removed, and the semiconductor substrate 101 is annealed in an oxidative atmosphere, thereby forming buried bit lines 104 that serve also as sources and drains.
  • accelerated oxidation occurs at portions of the sacrificial oxide film 106 above the bit lines 104 through the annealing process due to the presence of arsenic ions in the semiconductor substrate 101 .
  • the sacrificial oxide film 106 thereby has a thickness of about 40 to 60 nm at those portions.
  • an electrode material is then deposited and patterned to form word lines 105 that cross the buried bit lines 104 with the sacrificial oxide film 106 being interposed between them.
  • the word lines serve also as gate electrodes.
  • the sacrificial oxide film 106 above the bit lines 104 may increase its thickness, and large bird's beaks may also grow.
  • An object of the present invention is to provide a semiconductor device that can sufficiently ensure electrical insulation between bit lines and word lines and realize an excellent charge holding characteristic by suppressing undesirable bird's beak formation, and a method of manufacturing the semiconductor device, in particular, to provide a semiconductor memory having a buried bit line structure.
  • the present invention provides a semiconductor device in which source and drain regions are formed in a surface layer of a semiconductor substrate, and a gate electrode is formed between the source and drain regions over the semiconductor substrate with a multilayer film being interposed between the gate electrode and the semiconductor substrate.
  • the multilayer film is made up from at least three layers, in which a first insulating film having a charge trap function is sandwiched by second and third insulating films from the upper and lower sides of the first insulating film.
  • the present invention also provides a method of manufacturing the semiconductor device.
  • a semiconductor device manufacturing method comprising a first step of introducing impurities into a surface layer in an active region of a semiconductor substrate and annealing the semiconductor substrate to form source and drain regions, a second step of, after the first step, forming a multilayer film made up from at least three layers, in which a first insulating film having a charge trap function is sandwiched by second and third insulating films from the upper and lower sides of the first insulating film, so as to cover the active region, and a third step of depositing an electrode material on the multilayer film and patterning the electrode material and the multilayer film to form a gate electrode over the semiconductor substrate with the multilayer film being interposed between the gate electrode and the semiconductor substrate.
  • a substance having an accelerated oxidation suppressing function is introduced into the active region, and the semiconductor substrate is annealed to form the source and drain regions.
  • the substance having the accelerated oxidation suppressing function is preferably ion-implanted obliquely to the surface of the active region.
  • the gate electrode is formed over the semiconductor substrate with the multilayer film being interposed between them, to cross the source and drain regions, and the source and drain regions contain the substance having an accelerated oxidation suppressing function, as well as the impurities.
  • FIGS. 1A to 1 C are schematic sectional views illustrating manufacturing steps of a buried bit line type flash memory according to the first embodiment of the present invention
  • FIGS. 2A and 2B are schematic sectional views illustrating manufacturing steps of the buried bit line type flash memory according to the first embodiment, subsequent to FIG. 1C;
  • FIG. 3 is a schematic plan view showing a structure in which bit lines and word lines perpendicularly cross each other;
  • FIG. 4 is a schematic sectional view illustrating a data write operation in the flash memory according to the first embodiment
  • FIGS. 5A and 5B are schematic sectional views illustrating a data erase operation in the flash memory according to the first embodiment
  • FIGS. 6A and 6B are schematic sectional views illustrating a data read operation in the flash memory according to the first embodiment
  • FIG. 7 is a graph showing the relation between the leakage current and the voltage between the source/drain and the gate electrode in the flash memory according to each of the first embodiment and comparative examples;
  • FIG. 8 is a graph showing the relation between the charge holding characteristic and the number of times of data erase/write operations in the flash memory according to each of the first embodiment and the comparative examples;
  • FIGS. 9A to 9 C are graphs each showing the relation between the threshold voltage (V th ) and the number of times of data erase/write operations in the flash memory according to the first embodiment and the comparative examples;
  • FIGS. 10A to 10 C are schematic sectional views illustrating manufacturing steps of a buried bit line type flash memory according to the second embodiment of the present invention.
  • FIGS. 11A and 11B are schematic sectional views illustrating manufacturing steps of the buried bit line type flash memory according to the second embodiment, subsequent to FIG. 10C;
  • FIGS. 12A to 12 C are schematic sectional views illustrating manufacturing steps of a buried bit line type flash memory according to the third embodiment of the present invention.
  • FIGS. 13A and 13B are schematic sectional views illustrating manufacturing steps of the buried bit line type flash memory according to the third embodiment, subsequent to FIG. 12C;
  • FIGS. 14A and 14B are schematic sectional views illustrating manufacturing steps of a buried bit line type flash memory according to prior art 1 ;
  • FIGS. 15A to 15 C are schematic sectional views illustrating manufacturing steps of a buried bit line type flash memory according to prior art 2 ;
  • FIGS. 16A to 16 D are schematic sectional views illustrating manufacturing steps of a buried bit line type flash memory according to prior art 3 .
  • FIGS. 1A to 1 C and 2 A and 2 B are schematic sectional views illustrating manufacturing steps of the buried bit line type flash memory according to this first embodiment in order.
  • a p-type silicon semiconductor substrate 1 is prepared.
  • Field oxide films (not shown) are formed in the element isolation regions on the surface of the semiconductor substrate 1 through, e.g., a LOCOS process for element isolation, thereby defining each active region 2 within a memory cell region and each active region (not shown) within a peripheral circuit region where a CMOS transistor and the like are to be formed.
  • trenches may be formed in the element isolation regions of the semiconductor substrate 1 , and the trenches may be filled with an insulating material to define active regions.
  • Annealing is then performed in an oxidative atmosphere at 900° C. to 1,100° C. to form an about 2 to 50 nm-thick sacrificial oxide film 3 on the active region 2 .
  • a resist is applied onto the sacrificial oxide film 3 and processed by photolithography to form a resist pattern 4 with band-shape portions separated at predetermined intervals.
  • n-type impurities such as arsenic (As) are ion-implanted into a surface layer of the semiconductor substrate 1 under such conditions that the ions can pass through the sacrificial oxide film 3 , in this example, at an acceleration energy of 50 keV and a dose of 2 to 3 ⁇ 10 15 /cm 2 .
  • annealing is performed in a nitrogen atmosphere (or an inert gas atmosphere) at 1,050° C. for 10 min to activate the implanted arsenic ions, thereby forming band-shape bit lines 5 .
  • These bit lines 5 serves also as the sources and drains of the flash memory.
  • an ONO film 6 having a three-layer structure of silicon oxide film/silicon nitride film/silicon oxide film is formed on the semiconductor substrate 1 .
  • a silicon oxide film 21 having a thickness of about 7 to 8 nm is formed on the semiconductor substrate 1 by thermal oxidation.
  • the portions of the silicon oxide film 21 above the bit lines 5 is acceleratingly oxidized through the annealing process due to the presence of arsenic ions in the bit lines 5 , thereby increasing the thickness to about 30 to 50 nm.
  • a silicon nitride film 22 having a thickness of about 5 nm is then formed on the silicon oxide film 21 through a CVD process at 600° C. to 800° C.
  • a silicon oxide film 23 having a thickness of about 10 nm is then formed on the silicon nitride film 22 through a CVD process.
  • the ONO film 6 is formed thus.
  • the active region 2 of the memory cell region is masked by a resist, and the portions of the ONO film 6 present on the active regions of the peripheral circuit region are all removed using CF 4 +CHF 3 /O 2 gas or the like.
  • a gate insulating film (not shown) is formed on the active regions of the peripheral circuit region by thermal oxidation.
  • the influence of the annealing process in the formation of the gate insulating film is little. Any further accelerated oxidation of the silicon oxide film 21 at the portions above the bit lines 5 is suppressed, and an increase in thickness is hardly observed.
  • DASi amorphous silicon
  • P phosphorus
  • the DASi film is then annealed to form a polysilicon film, and the polysilicon film and the ONO film 6 are patterned by photolithography and subsequent dry etching, thereby forming band-shap word lines 7 that perpendicularly cross the bit lines 5 with the ONO film 6 being interposed between them and serve also as gate electrodes.
  • a tungsten silicide (WSi) film may be formed on the polysilicon film to form word lines having a polycide structure and thereby decrease the resistance of electrical interconnections.
  • a high-temperature CVD oxide film (HTO film) 8 and a BPSG film 9 are sequentially formed in this order to cover the word lines 7 .
  • an aluminum alloy film is formed by sputtering on the BPSG film 9 , which has been planarized by a reflow process, so as to fill the contact holes.
  • the aluminum alloy film is patterned by photolithography and subsequent dry etching to form upper interconnecting lines 11 .
  • a protective film 12 is formed to cover the upper interconnecting lines 11 , and formation processes for an insulating interlayer, contact holes (via holes), and interconnecting lines are executed, thereby completing a buried bit line type flash memory.
  • electrons are injected into the drain terminal with channel hot electrons (CHEs) or drain avalanche hot carriers (DAHCs), as shown in FIG. 4.
  • CHEs channel hot electrons
  • DAHCs drain avalanche hot carriers
  • electrons can be injected into the source terminal by exchanging the source and drain voltages with each other. That is, write operations (electron injection) to two portions in one memory cell can be executed.
  • FIGS. 6A and 6B A method of reading out data from this flash memory will be described with reference to FIGS. 6A and 6B. While negative charges are present in the silicon nitride film 22 , the channel is cut off, and no current flows between the source and the drain (FIG. 6A). This state is defined as data “0”. While no electrons are present in the silicon nitride film 22 , the channel is connected, and a current flows (FIG. 6B). This state is defined as data “1”.
  • FIGS. 7, 8, and 9 A to 9 C show the experimental results, in which the above-described prior arts 1 and 2 are respectively referred to as prior arts ⁇ circle over ( 1 ) ⁇ and ⁇ circle over ( 2 ) ⁇ as comparative examples, and the first embodiment of the present invention is referred to as invention ⁇ circle over ( 1 ) ⁇ .
  • the breakdown voltage of the ONO film had to be about 15 V.
  • the ensured breakdown voltage was almost the same as that in prior art ⁇ circle over ( 2 ) ⁇ which had the thickest silicon oxide film above the bit lines (sources and drains).
  • the ONO film 6 is formed after the impurities (arsenic) in the bit lines 5 are activated.
  • the silicon oxide film 21 as a component of the ONO film 6 is formed thick only above the bit lines 5 by accelerated oxidation, so that sufficient electrical insulation is ensured between the bit lines 5 and the word lines 7 .
  • the thickness of the ONO film 6 above the bit lines 5 is kept within an optimum range in which sufficient electrical insulation is ensured between the bit lines 5 and the word lines 7 and no bird's beak that may degrade the charge holding characteristic is formed. Hence, a very reliable flash memory with improved transistor characteristics can be implemented.
  • this second embodiment a so-called buried bit line type flash memory will be described, like the first embodiment, though this second embodiment differs from the first embodiment in the bit line formation process.
  • the components of the flash memory according to this second embodiment corresponding to those in the first embodiment are denoted by the same reference numerals as those in the first embodiment.
  • FIGS. 10A to 10 C and 11 A and 11 B are schematic sectional views illustrating manufacturing steps of the buried bit line type flash memory according to this second embodiment in order.
  • a p-type silicon semiconductor substrate 1 is prepared.
  • Field oxide films (not shown) are formed in the element isolation regions on the surface of the semiconductor substrate 1 through, e.g., a LOCOS process for element isolation, thereby defining each active region 2 within a memory cell region and each active region (not shown) within a peripheral circuit region where a CMOS transistor and the like are to be formed.
  • trenches may be formed in the element isolation regions of the semiconductor substrate 1 , and the trenches may be filled with an insulating material to define active regions.
  • Annealing is then performed in an oxidative atmosphere at 900° C. to 1,100° C. to form an about 2 to 50 nm-thick sacrificial oxide film 3 on the active region 2 .
  • a resist is applied onto the sacrificial oxide film 3 and processed by photolithography to form a resist pattern 4 with band-shape portions separated at predetermined intervals.
  • n-type impurities such as arsenic (As) are ion-implanted into a surface layer of the semiconductor substrate 1 under such conditions that the ions can pass through the sacrificial oxide film 3 , in this example, at an acceleration energy of 50 keV and a dose of 2 to 3 ⁇ 10 15 /cm 2 .
  • a substance having an accelerated oxidation suppressing function in this example, nitrogen ions are implanted at an acceleration energy of 2 to 10 keV and a dose of 0.5 to 4 ⁇ 10 15 /cm 2 .
  • the substance having the accelerated oxidation suppressing function can be one selected from nitrogen, carbon, and compounds containing nitrogen or carbon.
  • the impurities may concentrate in a surface layer of the semiconductor substrate 1 to form SiN or SiC and thereby suppress the diffusion of oxygen atoms into the semiconductor substrate 1 .
  • carbon may suitably be ion-implanted instead of nitrogen.
  • the introducing method of such a substance is not limited to the ion implantation method.
  • annealing may be performed in an atmosphere of such a substance to dope the semiconductor substrate 1 with the substance.
  • the substance having the accelerated oxidation suppressing function is preferably selected from NO 2 , NO, NH 3 , and C x H y (x and y are appropriate numbers) due to the above-described reason for accelerated oxidation suppression.
  • bit lines 5 serves also as the sources and drains of the flash memory.
  • an ONO film 6 having a three-layer structure of silicon oxide film/silicon nitride film/silicon oxide film is formed on the semiconductor substrate 1 .
  • a silicon oxide film 21 having a thickness of about 7 to 8 nm is formed on the semiconductor substrate 1 by thermal oxidation.
  • the portions of the silicon oxide film 21 above the bit lines 5 is acceleratingly oxidized through the annealing process due to the presence of arsenic ions in the bit lines 5 , thereby increasing the thickness to about 30 to 50 nm.
  • the accelerated oxidation suppressing function of the implanted nitrogen ions further suppresses the increase in thickness of the silicon oxide film 21 in comparison with the first embodiment in which no nitrogen ion implantation is performed.
  • a silicon nitride film 22 having a thickness of about 5 nm is then formed on the silicon oxide film 21 through a CVD process at 600° C. to 800° C.
  • a silicon oxide film 23 having a thickness of about 10 nm is then formed on the silicon nitride film 22 through a CVD process.
  • the ONO film 6 is formed thus.
  • the active region 2 of the memory cell region is masked by a resist, and the portions of the ONO film 6 present on the active regions of the peripheral circuit region are all removed using CF 4 +CHF 3 /O 2 gas or the like.
  • a gate insulating film (not shown) is formed on the active regions of the peripheral circuit region by thermal oxidation.
  • the influence of the annealing process in the formation of the gate insulating film is little. Any further accelerated oxidation of the silicon oxide film 21 at the portions above the bit lines 5 is suppressed, and an increase in thickness is hardly observed.
  • DASi amorphous silicon
  • P phosphorus
  • the DASi film is then annealed to form a polysilicon film, and the polysilicon film and the ONO film 6 are patterned by photolithography and subsequent dry etching, thereby forming band-shape word lines 7 that perpendicularly cross the bit lines 5 with the ONO film 6 being interposed between them and serve also as gate electrodes.
  • a tungsten silicide (WSi) film may be formed on the polysilicon film to form word lines having a polycide structure and thereby decrease the resistance of electrical interconnections.
  • a high-temperature CVD oxide film (HTO film) 8 and a BPSG film 9 are sequentially formed in this order to cover the word lines 7 .
  • an aluminum alloy film is formed by sputtering on the BPSG film 9 , which has been planarized by a reflow process, so as to fill the contact holes.
  • the aluminum alloy film is patterned by photolithography and subsequent dry etching to form upper interconnecting lines 11 .
  • a protective film 12 is formed to cover the upper interconnecting lines 11 , and formation processes for an insulating interlayer, contact holes (via holes), and interconnecting lines are executed, thereby completing a buried bit line type flash memory.
  • the ONO film 6 is formed after the impurities (arsenic) in the bit lines 5 are activated, and nitrogen (carbon) having the accelerated oxidation suppressing function is ion-implanted.
  • the silicon oxide film 21 as a component of the ONO film 6 is formed thick only above the bit lines 5 by accelerated oxidation, so that sufficient electrical insulation is ensured between the bit lines 5 and the word lines 7 .
  • the thickness of the ONO film 6 above the bit lines 5 is kept within an optimum range in which sufficient electrical insulation is ensured between the bit lines 5 and the word lines 7 and no bird's beak that may degrade the charge holding characteristic is formed. Additionally, the thickness can be controlled thinner by the accelerated oxidation suppressing function of nitrogen (carbon). Hence, a very reliable flash memory with improved transistor characteristics can be implemented.
  • this third embodiment a so-called buried bit line type flash memory will be described, like the first embodiment, though this third embodiment differs from the first embodiment in the bit line formation process.
  • the components of the flash memory according to this third embodiment corresponding to those in the first or second embodiment are denoted by the same reference numerals as those in the first or second embodiment.
  • FIGS. 12A to 12 C and 13 A and 13 B are schematic sectional views illustrating manufacturing steps of the buried bit line type flash memory according to this third embodiment in order.
  • a p-type silicon semiconductor substrate 1 is prepared.
  • Field oxide films are formed in the element isolation regions on the surface of the semiconductor substrate 1 through, e.g., a LOCOS process for element isolation, thereby defining each active region 2 within a memory cell region and each active region (not shown) within a peripheral circuit region where a CMOS transistor and the like are to be formed.
  • trenches may be formed in the element isolation regions of the semiconductor substrate 1 , and the trenches may be filled with an insulating material to define active regions.
  • Annealing is then performed in an oxidative atmosphere at 900° C. to 1,100° C. to form an about 2 to 50 nm-thick sacrificial oxide film 3 on the active region 2 .
  • a resist is applied onto the sacrificial oxide film 3 and processed by photolithography to form a resist pattern 4 with band-shape portions separated at predetermined intervals.
  • n-type impurities such as arsenic (As) are ion-implanted into a surface layer of the semiconductor substrate 1 under such conditions that the ions can pass through the sacrificial oxide film 3 , in this example, at an acceleration energy of 50 keV and a dose of 2 to 3 ⁇ 10 15 /cm 2 .
  • a substance having an accelerated oxidation suppressing function in this example, nitrogen ions are ion-implanted obliquely to the surface of the semiconductor substrate 1 at an acceleration energy of 2 to 30 keV and a dose of 1 to 5 ⁇ 10 15 /cm 2 .
  • x represents the distance between neighboring resist pattern portions 4 (the width of each bit line 5 )
  • y represents the thickness of the resist pattern 4 , using an angle ⁇ that generally satisfies;
  • the angle ⁇ for implantation of nitrogen ions preferably falls within the range of;
  • the substance having the accelerated oxidation suppressing function can be one selected from nitrogen, carbon, and compounds containing nitrogen or carbon.
  • the impurities may concentrate in a surface layer of the semiconductor substrate 1 to form SiN or SiC and thereby suppress the diffusion of oxygen atoms into the semiconductor substrate 1 .
  • carbon may suitably be ion-implanted instead of nitrogen.
  • the introducing method of such a substance is not limited to the ion implantation method.
  • annealing may be performed in an atmosphere of such a substance to dope the semiconductor substrate 1 with the substance.
  • the substance having the accelerated oxidation suppressing function is preferably selected from NO 2 , NO, NH 3 , and C x H y (x and y are appropriate numbers) due to the above-described reason for accelerated oxidation suppression.
  • bit lines 5 serves also as the sources and drains of the flash memory.
  • an ONO film 6 having a three-layer structure of silicon oxide film/silicon nitride film/silicon oxide film is formed on the semiconductor substrate 1 .
  • a silicon oxide film 21 having a thickness of about 7 to 8 nm is formed on the semiconductor substrate 1 by thermal oxidation.
  • the portions of the silicon oxide film 21 above the bit lines 5 is acceleratingly oxidized through the annealing process due to the presence of arsenic ions in the bit lines 5 , thereby increasing the thickness to about 30 to 50 nm.
  • the accelerated oxidation suppressing function of the implanted nitrogen ions further suppresses the increase in thickness of the silicon oxide film 21 in comparison with the first embodiment in which no nitrogen ion implantation is performed.
  • a silicon nitride film 22 having a thickness of about 5 nm is then formed on the silicon oxide film 21 through a CVD process at 600° C. to 800° C.
  • a silicon oxide film 23 having a thickness of about 10 nm is then formed on the silicon nitride film 22 through a CVD process.
  • the ONO film 6 is formed thus.
  • the active region 2 of the memory cell region is masked by a resist, and the portions of the ONO film 6 present on the active regions of the peripheral circuit region are all removed using CF 4 +CHF 3 /O 2 gas or the like.
  • a gate insulating film (not shown) is formed on the active regions of the peripheral circuit region by thermal oxidation.
  • the influence of the annealing process in the formation of the gate insulating film is little. Any further accelerated oxidation of the silicon oxide film 21 at the portions above the bit lines 5 is suppressed, and an increase in thickness is hardly observed.
  • DASi amorphous silicon
  • P phosphorus
  • the DASi film is then annealed to form a polysilicon film, and the polysilicon film and the ONO film 6 are patterned by photolithography and subsequent dry etching, thereby forming band-shape word lines 7 that perpendicularly cross the bit lines 5 with the ONO film 6 being interposed between them and serve also as gate electrodes.
  • a tungsten silicide (WSi) film may be formed on the polysilicon film to form word lines having a polycide structure and thereby decrease the resistance of electrical interconnections.
  • a high-temperature CVD oxide film (HTO film) 8 and a BPSG film 9 are sequentially formed in this order to cover the word lines 7 .
  • an aluminum alloy film is formed by sputtering on the BPSG film 9 , which has been planarized by a reflow process, so as to fill the contact holes.
  • the aluminum alloy film is patterned by photolithography and subsequent dry etching to form upper interconnecting lines 11 .
  • a protective film 12 is formed to cover the upper interconnecting lines 11 , and formation processes for an insulating interlayer, contact holes (via holes), and interconnecting lines are executed, thereby completing a buried bit line type flash memory.
  • the ONO film 6 is formed after the impurities (arsenic) in the bit lines 5 are activated, and nitrogen (carbon) having the accelerated oxidation suppressing function is ion-implanted.
  • the silicon oxide film 21 as a component of the ONO film 6 is formed thick only above the bit lines 5 by accelerated oxidation, so that sufficient electrical insulation is ensured between the bit lines 5 and the word lines 7 .
  • nitrogen (carbon) is ion-implanted obliquely to the surface of the semiconductor substrate 1 .
  • nitrogen (carbon) can be introduced also into the end portions between the source and drain (channel) of the semiconductor substrate 1 .
  • nitrogen can be more deeply introduced into the channel ends, and thereby formation of bird's beaks is suppressed.
  • the resist pattern 4 above the bit lines 5 serves as a mask, it prevents nitrogen ion implantation. At these portions, therefore, accelerated oxidation is not suppressed, and the silicon oxide film 21 becomes thick and may contribute to ensure a sufficient breakdown voltage.
  • the interface level in the region where electrons are injected upon a data write operation is terminated, and the charge holding characteristic is improved.
  • the thickness of the ONO film 6 above the bit lines 5 is kept within the optimum range in which sufficient electrical insulation is ensured between the bit lines 5 and the word lines 7 and no bird's beak that may degrade the charge holding characteristic is formed. Additionally, the thickness can be controlled thinner by the accelerated oxidation suppressing function of nitrogen (carbon). Furthermore, since nitrogen (carbon) is obliquely ion-implanted, the charge holding characteristic can be further improved. Hence, a very reliable flash memory with improved transistor characteristics can be implemented.
  • the present invention is not limited to the above-described first to third embodiments.
  • the present invention can be applied not only to single-level type memories that use data of “0” and “1”, but also to binary memories that use data of “00”, “01”, “10”, and “11”, or to further multi-level type memories.
  • the present invention makes it possible to provide a semiconductor device, in particular, a semiconductor memory having a buried bit line structure, and a manufacturing method of the same, wherein electrical insulation between bit and word lines is sufficiently ensured and an excellent charge holding characteristic is realized by suppressing undesirable bird's beak formation.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
US09/922,786 2001-03-16 2001-08-07 Semiconductor device and method of manufacturing the same Abandoned US20020132416A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/986,652 US7084037B2 (en) 2001-03-16 2004-11-12 Semiconductor device and method of manufacturing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001076585A JP4152598B2 (ja) 2001-03-16 2001-03-16 半導体装置の製造方法
JP2001-076585 2001-03-16

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US10/986,652 Division US7084037B2 (en) 2001-03-16 2004-11-12 Semiconductor device and method of manufacturing the same

Publications (1)

Publication Number Publication Date
US20020132416A1 true US20020132416A1 (en) 2002-09-19

Family

ID=18933492

Family Applications (2)

Application Number Title Priority Date Filing Date
US09/922,786 Abandoned US20020132416A1 (en) 2001-03-16 2001-08-07 Semiconductor device and method of manufacturing the same
US10/986,652 Expired - Lifetime US7084037B2 (en) 2001-03-16 2004-11-12 Semiconductor device and method of manufacturing the same

Family Applications After (1)

Application Number Title Priority Date Filing Date
US10/986,652 Expired - Lifetime US7084037B2 (en) 2001-03-16 2004-11-12 Semiconductor device and method of manufacturing the same

Country Status (5)

Country Link
US (2) US20020132416A1 (de)
JP (1) JP4152598B2 (de)
KR (1) KR100739084B1 (de)
DE (1) DE10146013B4 (de)
TW (1) TW519675B (de)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050205948A1 (en) * 2002-07-31 2005-09-22 Rotondaro Antonio L Gate dielectric and method
US20060091458A1 (en) * 2004-11-03 2006-05-04 Samsung Electronics Co., Ltd. Nonvolatile memory device and method of manufacturing the same
US20060202260A1 (en) * 2005-03-14 2006-09-14 Masaru Seto Semiconductor memory device and method of manufacturing the same
US20060292800A1 (en) * 2005-06-23 2006-12-28 Yen-Hao Shih ONO formation of semiconductor memory device and method of fabricating the same
US20070007583A1 (en) * 2005-07-11 2007-01-11 Sung-Hae Lee Gate structure and related non-volatile memory device and method
US20070293006A1 (en) * 2006-06-20 2007-12-20 Macronix International Co., Ltd. Method for fabricating a charg trapping memory device
US20080079095A1 (en) * 2006-09-30 2008-04-03 Semiconductor Manufacturing International (Shanghai) Corporation Metal oxide semiconductor device and method for manufacturing the same
EP1962332A2 (de) 2007-02-22 2008-08-27 Fujitsu Ltd. Halbleiterbauelement und Herstellungsverfahren dafür
US9111985B1 (en) * 2007-01-11 2015-08-18 Cypress Semiconductor Corporation Shallow bipolar junction transistor

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100426488B1 (ko) * 2001-12-29 2004-04-14 주식회사 하이닉스반도체 플래시 메모리 셀과 그 제조 방법 및 프로그램/소거/독출방법
JP2004193226A (ja) 2002-12-09 2004-07-08 Nec Electronics Corp 不揮発性半導体記憶装置およびその製造方法
JP4572500B2 (ja) * 2002-12-27 2010-11-04 ソニー株式会社 不揮発性半導体メモリ装置およびその動作方法
US8199222B2 (en) 2007-03-05 2012-06-12 DigitalOptics Corporation Europe Limited Low-light video frame enhancement
US8989516B2 (en) 2007-09-18 2015-03-24 Fotonation Limited Image processing method and apparatus
US7636486B2 (en) 2004-11-10 2009-12-22 Fotonation Ireland Ltd. Method of determining PSF using multiple instances of a nominally similar scene
US8264576B2 (en) * 2007-03-05 2012-09-11 DigitalOptics Corporation Europe Limited RGBW sensor array
US7639889B2 (en) 2004-11-10 2009-12-29 Fotonation Ireland Ltd. Method of notifying users regarding motion artifacts based on image analysis
US9160897B2 (en) 2007-06-14 2015-10-13 Fotonation Limited Fast motion estimation method
US8417055B2 (en) 2007-03-05 2013-04-09 DigitalOptics Corporation Europe Limited Image processing method and apparatus
US8180173B2 (en) * 2007-09-21 2012-05-15 DigitalOptics Corporation Europe Limited Flash artifact eye defect correction in blurred images using anisotropic blurring
US7639888B2 (en) 2004-11-10 2009-12-29 Fotonation Ireland Ltd. Method and apparatus for initiating subsequent exposures based on determination of motion blurring artifacts
KR100582421B1 (ko) * 2004-11-24 2006-05-22 에스티마이크로일렉트로닉스 엔.브이. 낸드 플래쉬 메모리소자의 제조방법
US7638393B2 (en) * 2006-05-02 2009-12-29 Macronix International Co., Ltd. Non-volatile memory device including nitrogen pocket implants and methods for making the same
IES20070229A2 (en) 2006-06-05 2007-10-03 Fotonation Vision Ltd Image acquisition method and apparatus
US7773118B2 (en) 2007-03-25 2010-08-10 Fotonation Vision Limited Handheld article with movement discrimination
KR101386433B1 (ko) * 2007-09-17 2014-04-21 삼성전자주식회사 반도체 소자 및 그 제조방법
JP4973463B2 (ja) * 2007-11-16 2012-07-11 トヨタ自動車株式会社 半導体装置
JP4994437B2 (ja) * 2009-11-18 2012-08-08 ルネサスエレクトロニクス株式会社 半導体集積回路装置及びその製造方法
CN102299074B (zh) * 2010-06-22 2013-04-17 中国科学院微电子研究所 一种半导体器件及其形成方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5168334A (en) * 1987-07-31 1992-12-01 Texas Instruments, Incorporated Non-volatile semiconductor memory

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06283721A (ja) 1992-03-06 1994-10-07 Oko Denshi Kofun Yugenkoshi 不揮発性メモリ・セル、アレー装置、製造方法、及びそのメモリ回路
JPH0722524A (ja) 1993-07-06 1995-01-24 Nippon Steel Corp 不揮発性半導体記憶装置及びその製造方法
US5516707A (en) 1995-06-12 1996-05-14 Vlsi Technology, Inc. Large-tilted-angle nitrogen implant into dielectric regions overlaying source/drain regions of a transistor
JPH09148542A (ja) * 1995-11-17 1997-06-06 Sharp Corp 半導体記憶装置及びその製造方法
US5937310A (en) * 1996-04-29 1999-08-10 Advanced Micro Devices, Inc. Reduced bird's beak field oxidation process using nitrogen implanted into active region
JP3400267B2 (ja) 1996-10-09 2003-04-28 シャープ株式会社 不揮発性半導体メモリの製造方法
KR100246364B1 (ko) * 1997-12-02 2000-03-15 김영환 게이트산화막 형성방법
US5962914A (en) 1998-01-14 1999-10-05 Advanced Micro Devices, Inc. Reduced bird's beak field oxidation process using nitrogen implanted into active region
US6188101B1 (en) 1998-01-14 2001-02-13 Advanced Micro Devices, Inc. Flash EPROM cell with reduced short channel effect and method for providing same
US6166958A (en) * 1998-07-09 2000-12-26 Kabushiki Kaisha Toshiba Semiconductor memory device, method for manufacturing the same, and method for controlling the same
US6387766B1 (en) * 1998-11-06 2002-05-14 Infineon Technologies Ag Method for manufacturing an integrated circuit with low threshold voltage differences of the transistors therein
JP2000332237A (ja) 1999-05-17 2000-11-30 Mitsubishi Electric Corp 半導体装置の製造方法
US6284603B1 (en) * 2000-07-12 2001-09-04 Chartered Semiconductor Manufacturing Inc. Flash memory cell structure with improved channel punch-through characteristics

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5168334A (en) * 1987-07-31 1992-12-01 Texas Instruments, Incorporated Non-volatile semiconductor memory

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050205948A1 (en) * 2002-07-31 2005-09-22 Rotondaro Antonio L Gate dielectric and method
US7423326B2 (en) * 2002-07-31 2008-09-09 Texas Instruments Incorporated Integrated circuits with composite gate dielectric
US20060091458A1 (en) * 2004-11-03 2006-05-04 Samsung Electronics Co., Ltd. Nonvolatile memory device and method of manufacturing the same
US7368349B2 (en) 2005-03-14 2008-05-06 Oki Electric Industry Co., Ltd. Semiconductor memory device and method of manufacturing the same
US20060202260A1 (en) * 2005-03-14 2006-09-14 Masaru Seto Semiconductor memory device and method of manufacturing the same
US20060292800A1 (en) * 2005-06-23 2006-12-28 Yen-Hao Shih ONO formation of semiconductor memory device and method of fabricating the same
US7763935B2 (en) * 2005-06-23 2010-07-27 Macronix International Co., Ltd. ONO formation of semiconductor memory device and method of fabricating the same
US20070007583A1 (en) * 2005-07-11 2007-01-11 Sung-Hae Lee Gate structure and related non-volatile memory device and method
US20070293006A1 (en) * 2006-06-20 2007-12-20 Macronix International Co., Ltd. Method for fabricating a charg trapping memory device
US7863132B2 (en) * 2006-06-20 2011-01-04 Macronix International Co., Ltd. Method for fabricating a charge trapping memory device
US20080079095A1 (en) * 2006-09-30 2008-04-03 Semiconductor Manufacturing International (Shanghai) Corporation Metal oxide semiconductor device and method for manufacturing the same
US9111985B1 (en) * 2007-01-11 2015-08-18 Cypress Semiconductor Corporation Shallow bipolar junction transistor
EP1962332A2 (de) 2007-02-22 2008-08-27 Fujitsu Ltd. Halbleiterbauelement und Herstellungsverfahren dafür
US20080203465A1 (en) * 2007-02-22 2008-08-28 Fujitsu Limited Semiconductor device and method for manufacturing the same
EP1962332A3 (de) * 2007-02-22 2009-04-29 Fujitsu Microelectronics Limited Halbleiterbauelement und Herstellungsverfahren dafür
US8466509B2 (en) 2007-02-22 2013-06-18 Fujitsu Semiconductor Limited Semiconductor device having a contact plug connecting to a silicide film formed on a diffusion region of a flash memory cell
US8865546B2 (en) 2007-02-22 2014-10-21 Fujitsu Semiconductor Limited Method for manufacturing a non-volatile semiconductor memory device having contact plug formed on silicided source/drain region

Also Published As

Publication number Publication date
KR20020074052A (ko) 2002-09-28
TW519675B (en) 2003-02-01
US7084037B2 (en) 2006-08-01
JP4152598B2 (ja) 2008-09-17
DE10146013B4 (de) 2009-01-29
JP2002280464A (ja) 2002-09-27
DE10146013A1 (de) 2002-10-02
US20050087778A1 (en) 2005-04-28
KR100739084B1 (ko) 2007-07-13

Similar Documents

Publication Publication Date Title
US7084037B2 (en) Semiconductor device and method of manufacturing the same
US6063666A (en) RTCVD oxide and N2 O anneal for top oxide of ONO film
EP1274132B1 (de) Nichtflüchtige Halbleiterspeicheranordnung und Verfahren zur Herstellung
KR100773994B1 (ko) 밀봉된 텅스텐 게이트 ｍｏｓ 트랜지스터와 메모리 셀 및 그 제조 방법
US20070228498A1 (en) Semiconductor device and a method of manufacturing the same
US20050285219A1 (en) Nonvolatile semiconductor memory and method of fabricating the same
US20090050953A1 (en) Non-volatile memory device and method for manufacturing the same
KR100482711B1 (ko) 반도체 기억 장치 및 그 제조 방법
JP2008504681A (ja) ナノクラスタ電荷蓄積デバイスの形成方法
US20030032239A1 (en) Processes and structures for self-aligned contact non-volatile memory with peripheral transistors easily modifiable for various technologies and applications
US7595237B2 (en) Non-volatile memory cell with a hybrid access transistor
US6380029B1 (en) Method of forming ono stacked films and DCS tungsten silicide gate to improve polycide gate performance for flash memory devices
US7741179B2 (en) Method of manufacturing flash semiconductor device
JP3745297B2 (ja) 不揮発性半導体記憶装置の製造方法
US6759296B2 (en) Method of manufacturing a flash memory cell
US20120267698A1 (en) Floating-gate nonvolatile semiconductor memory device and method of making
US6162684A (en) Ammonia annealed and wet oxidized LPCVD oxide to replace ono films for high integrated flash memory devices
US8258027B2 (en) Method for integrating SONOS non-volatile memory into a standard CMOS foundry process flow
US6900085B2 (en) ESD implant following spacer deposition
US20070004122A1 (en) Method for fabricating semiconductor memory device
KR100343137B1 (ko) 불휘발성 메모리 장치 및 그 제조방법
KR101983682B1 (ko) 에지가 둥근 전계 효과 트랜지스터 및 제조 방법
US8729635B2 (en) Semiconductor device having a high stress material layer
WO2005122246A1 (ja) 半導体装置および半導体装置の製造方法
US6184084B1 (en) Method to elimate silicide cracking for nand type flash memory devices by implanting a polish rate improver into the second polysilicon layer and polishing it

Legal Events

Date Code Title Description
AS Assignment

Owner name: FUJITSU LIMITED, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GAMO, YASUO;TAKAHASHI, KOJI;REEL/FRAME:012056/0099

Effective date: 20010713

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION

AS Assignment

Owner name: MONTEREY RESEARCH, LLC, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CYPRESS SEMICONDUCTOR CORPORATION;REEL/FRAME:042108/0880

Effective date: 20170322

AS Assignment

Owner name: CYPRESS SEMICONDUCTOR CORPORATION, CALIFORNIA

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:042769/0227

Effective date: 20170322