US20020010823A1 - Multimaster bus system and method for operating the multimaster bus system - Google Patents

Multimaster bus system and method for operating the multimaster bus system Download PDF

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Publication number
US20020010823A1
US20020010823A1 US09/879,242 US87924201A US2002010823A1 US 20020010823 A1 US20020010823 A1 US 20020010823A1 US 87924201 A US87924201 A US 87924201A US 2002010823 A1 US2002010823 A1 US 2002010823A1
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Prior art keywords
bus
master
default
units
stipulation
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Abandoned
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US09/879,242
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English (en)
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Andreas Wenzel
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Individual
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Individual
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/374—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a self-select method with individual priority code comparator
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

Definitions

  • the present invention relates to a multimaster bus system having a bus and units which can be connected by means of the bus, where one of the units can be stipulated as default master, and to a method for operating such a multimaster bus system.
  • a multimaster bus system is a bus system in which various ones of the units connected to the bus may be the bus master alternately during operation.
  • bus master Of the units which can be bus master, one is usually stipulated as the default bus master or default master. This unit is the bus master whenever none of the other units are requesting the bus (want to be the bus master).
  • bus systems have been known for a long time in many different embodiments and require no more detailed explanation.
  • the fact that various units can be the bus master alternately means that bus systems of this type can be used with great flexibility.
  • a multimaster bus system that includes: a bus; a plurality of units that can be connected using the bus; and a default master that is selected from the plurality of the units in a dynamically modifiable default-master stipulation.
  • the default-master stipulation is based on criteria selected from the group consisting of: when the plurality of the units are used on the bus, how often the plurality of the units are used on the bus, and how long the plurality of the units are used on the bus.
  • a multimaster bus system that includes: a bus; a plurality of units that can be connected using the bus; and a default master that is selected from the plurality of the units in a dynamically modifiable default-master stipulation.
  • the one of the plurality of the units that has used the bus last is stipulated as the default master in the dynamically modifiable default-master stipulation.
  • a multimaster bus system that includes: a bus; a plurality of units that can be connected using the bus; and a default master that is selected from the plurality of the units in a dynamically modifiable default-master stipulation.
  • the one of the plurality of the units that needed the bus more frequently than any others of the plurality of the units in a preceding predetermined time period is stipulated as the default master in the dynamically modifiable default-master stipulation.
  • a multimaster bus system that includes: a bus; a plurality of units that can be connected using the bus; and a default master that is selected from the plurality of the units in a dynamically modifiable default-master stipulation.
  • the default master is selected, in the dynamically modifiable default-master stipulation, from the group consisting of: a particular one of the plurality of the units that is expected to need to access the bus frequently, and a particular one of the plurality of the units that is expected to need to access the bus rapidly.
  • a program-controlled unit that needs bus access.
  • the default-master stipulation is based on an analysis selected from the group consisting of an analysis of an actual program cycle of the program-controlled unit and an analysis of an expected program cycle of the program-controlled unit.
  • the dynamically modifiable default-master stipulation is based upon variable criteria and variable parameters.
  • a method for operating a multimaster bus system that includes: providing a bus and a plurality of units that can be connected using the bus; selecting a default master from the plurality of the units in a default-master stipulation that can be dynamically modified; and in the default master stipulation, selecting the default master based on criteria selected from the group consisting of: when the plurality of the units are used on the bus, how often the plurality of the units are used on the bus, and how long the plurality of the units are used on the bus.
  • a method for operating a multimaster bus system that includes: providing a bus and units that can be connected using the bus; selecting a default master from the plurality of the units in a default-master stipulation that can be dynamically modified; and in the default master stipulation, selecting the default master as one of the plurality of the units that has last used the bus.
  • a method for operating a multimaster bus system that includes: providing a bus and units that can be connected using the bus; selecting a default master from the plurality of the units in a default-master stipulation that can be dynamically modified; and in the default master stipulation, selecting the default master as one of the plurality of the units that needed the bus more frequently than any others of the plurality of the units in a preceding predetermined time period.
  • a method for operating a multimaster bus system that includes: providing a bus and units that can be connected using the bus; selecting a default master from the plurality of the units in a default-master stipulation that can be dynamically modified; and in the default master stipulation, selecting the default master from the group consisting of: a particular one of the plurality of the units that is expected to need to access the bus frequently, and a particular one of the plurality of the units that is expected to need to access the bus rapidly.
  • Suitable stipulation of the default master or suitable modification of the default-master stipulation thus allows the bus system to be optimally matched to the prevailing conditions under all circumstances; this means that the system containing the bus system can operate with a maximum of speed and efficiency.
  • FIGURE is a schematic illustration of a system including a microcontroller.
  • the system includes a microcontroller 1 and an external memory 2 .
  • the microcontroller 1 includes a first bus 20 , a second bus 21 , and a third bus 22 .
  • the microcontroller 1 also includes a core 11 , an instruction memory 12 , a data memory 13 , a first peripheral unit 14 , a second peripheral unit 15 , a third peripheral unit 16 , a bus controller 17 , an instruction bridge 18 (a bus protocol conversion unit) provided between the second bus 21 and the third bus 22 , and a data bridge 19 (a bus protocol conversion unit) provided between the first bus 20 and the third bus 22 .
  • the first bus 20 connects the core 11 , the data memory 13 and the data bridge 19 .
  • the second bus 21 connects the core 11 , the instruction memory 12 and the instruction bridge 18 .
  • the third bus 22 connects the first peripheral unit 14 , the second peripheral unit 15 , the third peripheral unit 16 , and the bus controller 17 , to the instruction bridge 18 , and to the data bridge 19 .
  • the bus controller 17 is the bus controller for an external bus provided outside the microcontroller 1 .
  • the external memory 2 (and possibly other external units) are connected to this external bus.
  • the external memory 2 is an external data and/or program memory for the microcontroller 1 .
  • Instruction data required by the core 11 may optionally be fetched from the internal instruction memory 12 or from the external memory 2 via the second bus 21 , the instruction bridge 18 , the third bus 22 and the bus controller 17 .
  • Data transfers prompted by the core 11 may optionally have the internal data memory 13 or the external memory 2 as the data source and/or the data destination. Data which are to be transferred between the core 11 and the external memory 2 are routed via the first bus 20 , the data bridge 19 , the third bus 22 , and the bus controller 17 .
  • the third bus 22 and the units connected by means of the latter form the bus system of particular interest in the present case. It is a multimaster bus system and is distinguished in that there is the possibility of dynamically setting which of the units connected by means of the bus is to be the default master.
  • the unit used as default master is the bus master if and so long as there is no bus request from the units connected by means of the bus.
  • the unit which is bus master at the instant at which it needs the bus has the advantage that it is able to use the bus immediately, that is to say without a prior bus request.
  • a unit which is not the bus master at the instant at which it needs the bus must first request the bus, which means that the required bus access is delayed by at least one bus cycle.
  • the unit which needs the bus most frequently is stipulated as the default master.
  • the unit which needs the bus most frequently can then access the bus most rapidly on average. Such a bus system operates very efficiently.
  • the data bridge 19 is permanently set as default master for the third bus 22 .
  • the data bridge 19 can then generally access the third bus 22 immediately when data transfer needs to be carried out between the core 11 and one of the units connected to the third bus 22 .
  • Such data transfers can therefore be carried out extremely rapidly and efficiently.
  • supplying instruction data stored in the external memory 2 to the core 11 is relatively complex.
  • the instruction bridge 18 needs to become bus master. Since the default master, that is to say the data bridge 19 in the example under consideration, is usually the bus master, the instruction bridge 18 first needs to request the bus.
  • the request for the third bus 22 delays the instruction data transfer by at least one bus cycle. In practice, fetching the data representing an instruction may also require more than one instruction data transfer. Fetching the data representing the instruction in question is then delayed even more. This is because the instruction bridge 18 needs to request the third bus 22 again for each instruction data transfer, because as soon as the instruction bridge 18 no longer requires the third bus 22 , that is to say after each individual instruction data transfer, the default master, that is to say the data bridge 19 , automatically becomes the bus master again. The instruction data transfer could be speeded up by stipulating the instruction bridge 18 as the default master for the third bus 22 . The data transfers which need to be executed by means of the data bridge 19 could then no longer be executed as rapidly and efficiently, however.
  • default-master stipulation can be effected on the basis of past uses of the bus by the units connected thereto, for example, on the basis of when and/or how often and/or how long the individual units used the bus.
  • the unit which can be expected to have to access the bus particularly frequently and or particularly rapidly in the near future could also be stipulated as the default master.
  • such predictions can be made using analyses of the actual program cycle, or of that which can be expected, in the microcontroller 1 (or other program-controlled unit or subunit which needs the bus).
  • Such default-master stipulation can also be used for multiprocessor systems, more precisely for a bus system which connects a plurality of program-controlled units.
  • the default-master stipulation described can also be used for bus systems which are not a component part of program-controlled units and/or systems containing program-controlled units.
US09/879,242 1998-12-07 2001-06-07 Multimaster bus system and method for operating the multimaster bus system Abandoned US20020010823A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19856403.1 1998-12-07
DE19856403 1998-12-07
PCT/DE1999/003843 WO2000034876A1 (de) 1998-12-07 1999-12-01 Multimaster-bussystem und verfahren zum betreiben desselben

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1999/003843 Continuation WO2000034876A1 (de) 1998-12-07 1999-12-01 Multimaster-bussystem und verfahren zum betreiben desselben

Publications (1)

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US20020010823A1 true US20020010823A1 (en) 2002-01-24

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US09/879,242 Abandoned US20020010823A1 (en) 1998-12-07 2001-06-07 Multimaster bus system and method for operating the multimaster bus system

Country Status (7)

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US (1) US20020010823A1 (de)
EP (1) EP1137997B1 (de)
JP (1) JP2002532780A (de)
KR (1) KR20010080706A (de)
CN (1) CN1329729A (de)
DE (1) DE59903433D1 (de)
WO (1) WO2000034876A1 (de)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050223147A1 (en) * 2004-03-19 2005-10-06 Infineon Technologies Ag Method and apparatus for allocating bus access rights in multimaster bus systems
US7600065B2 (en) 2005-10-05 2009-10-06 Samsung Electronics Co., Ltd. Arbitration scheme for shared memory device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6957290B1 (en) 2000-10-06 2005-10-18 Broadcom Corporation Fast arbitration scheme for a bus
US7076586B1 (en) 2000-10-06 2006-07-11 Broadcom Corporation Default bus grant to a bus agent

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5481680A (en) * 1993-05-17 1996-01-02 At&T Corp. Dynamically programmable bus arbiter with provisions for historical feedback and error detection and correction
US5560016A (en) * 1994-10-06 1996-09-24 Dell Usa, L.P. System and method for dynamic bus access prioritization and arbitration based on changing bus master request frequency
US5572686A (en) * 1995-06-05 1996-11-05 Apple Computer, Inc. Bus arbitration scheme with priority switching and timer
US5845096A (en) * 1996-08-26 1998-12-01 Vlsi Technology, Inc. Adaptive arbitration mechanism for a shared multi-master bus
US5845097A (en) * 1996-06-03 1998-12-01 Samsung Electronics Co., Ltd. Bus recovery apparatus and method of recovery in a multi-master bus system
US6473817B2 (en) * 1998-10-15 2002-10-29 Micron Technology, Inc. Method and apparatus for efficient bus arbitration

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5195089A (en) * 1990-12-31 1993-03-16 Sun Microsystems, Inc. Apparatus and method for a synchronous, high speed, packet-switched bus
JPH1125035A (ja) * 1997-07-08 1999-01-29 Oki Electric Ind Co Ltd バス調停装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5481680A (en) * 1993-05-17 1996-01-02 At&T Corp. Dynamically programmable bus arbiter with provisions for historical feedback and error detection and correction
US5560016A (en) * 1994-10-06 1996-09-24 Dell Usa, L.P. System and method for dynamic bus access prioritization and arbitration based on changing bus master request frequency
US5572686A (en) * 1995-06-05 1996-11-05 Apple Computer, Inc. Bus arbitration scheme with priority switching and timer
US5845097A (en) * 1996-06-03 1998-12-01 Samsung Electronics Co., Ltd. Bus recovery apparatus and method of recovery in a multi-master bus system
US5845096A (en) * 1996-08-26 1998-12-01 Vlsi Technology, Inc. Adaptive arbitration mechanism for a shared multi-master bus
US6473817B2 (en) * 1998-10-15 2002-10-29 Micron Technology, Inc. Method and apparatus for efficient bus arbitration

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050223147A1 (en) * 2004-03-19 2005-10-06 Infineon Technologies Ag Method and apparatus for allocating bus access rights in multimaster bus systems
US7373445B2 (en) 2004-03-19 2008-05-13 Infineon Technologies Ag Method and apparatus for allocating bus access rights in multimaster bus systems
US7600065B2 (en) 2005-10-05 2009-10-06 Samsung Electronics Co., Ltd. Arbitration scheme for shared memory device

Also Published As

Publication number Publication date
KR20010080706A (ko) 2001-08-22
JP2002532780A (ja) 2002-10-02
EP1137997B1 (de) 2002-11-13
DE59903433D1 (de) 2002-12-19
WO2000034876A1 (de) 2000-06-15
CN1329729A (zh) 2002-01-02
EP1137997A1 (de) 2001-10-04

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