US11854904B2 - Different source/drain profiles for n-type FinFETs and p-type FinFETs - Google Patents

Different source/drain profiles for n-type FinFETs and p-type FinFETs Download PDF

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US11854904B2
US11854904B2 US17/124,047 US202017124047A US11854904B2 US 11854904 B2 US11854904 B2 US 11854904B2 US 202017124047 A US202017124047 A US 202017124047A US 11854904 B2 US11854904 B2 US 11854904B2
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layer
semiconductor fin
recess
epitaxy
drain region
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US20220051947A1 (en
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Shahaji B. More
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority to US17/124,047 priority Critical patent/US11854904B2/en
Priority to DE102020135016.3A priority patent/DE102020135016A1/de
Priority to KR1020210018846A priority patent/KR102629827B1/ko
Priority to TW110115623A priority patent/TW202207313A/zh
Priority to CN202110625083.3A priority patent/CN113745163A/zh
Publication of US20220051947A1 publication Critical patent/US20220051947A1/en
Priority to US18/363,350 priority patent/US20230377988A1/en
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Definitions

  • n-type Fin Field-Effect Transistor FinFET
  • p-type FinFET n-type Fin Field-Effect Transistor
  • the method of forming the same are provided.
  • the n-type source/drain regions of the n-type FinFET are deposited as having a wavy-shaped top surface, while the p-type source/drain regions of the p-type FinFET are deposited as having a cone shape. This may reduce the fin bending of the semiconductor fins in p-type FinFETs, while the contact areas of contact plugs to both of the n-type source/drain regions and the p-type source/drain regions are reduced.
  • the silicide regions formed on both of the n-type source/drain regions and the p-type source/drain regions may have recessed middle portions (with V-shapes).
  • FIGS. 1 , 2 , 3 A, 3 B, 3 C, 4 A, 4 B, 4 C, 5 , 6 , 7 A, 7 B, 8 A, 8 B, 9 , 10 , 11 A, 11 B , and 11 C illustrate the perspective views and cross-sectional views of intermediate stages in the formation of the n-type FinFET and the p-type FinFET in accordance with some embodiments of the present disclosure.
  • the corresponding processes are also reflected schematically in the process flow shown in FIG. 12 .
  • STI regions 22 may include a liner oxide (not shown), which may be a thermal oxide formed through a thermal oxidation of a surface layer of substrate 20 .
  • the liner oxide may also be a deposited silicon oxide layer formed using, for example, Atomic Layer Deposition (ALD), High-Density Plasma Chemical Vapor Deposition (HDPCVD), or Chemical Vapor Deposition (CVD).
  • STI regions 22 may also include a dielectric material over the liner oxide, wherein the dielectric material may be formed using Flowable Chemical Vapor Deposition (FCVD), spin-on, or the like.
  • FCVD Flowable Chemical Vapor Deposition
  • STI regions 22 are recessed, so that the top portions of semiconductor strips 24 N and 24 P protrude higher than the top surfaces 22 A of STI regions 22 to form protruding fins 24 N′ and 24 P′.
  • the respective process is illustrated as process 202 in the process flow shown in FIG. 12 .
  • the portions of semiconductor strips 24 N and 24 P in STI regions 22 are still referred to as semiconductor strips.
  • the etching may be performed using a dry etching process, wherein a mixture of HF and NH 3 may be used as the etching gases.
  • the etching may also be performed using a mixture of NF 3 and NH 3 as the etching gases. During the etching process, plasma may be generated. Argon may also be included.
  • the recessing of STI regions 22 is performed using a wet etching process.
  • the etching chemical may include HF solution, for example.
  • the fins for forming the FinFETs may be formed/patterned by any suitable method.
  • the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes.
  • double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process.
  • a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers, or mandrels, may then be used to pattern the fins.
  • a fin-group for forming a FinFET may include a plurality of fins tightly grouped together.
  • the example shown in FIG. 3 A illustrates a 2-fin-group on the left, and a single fin (or a multi-fin fin-group) on the right.
  • the fins in the same fin-group may have spacings (referred to as inner-group spacing) smaller than the inter-group spacings between neighboring fin-groups.
  • Dummy gate stacks 30 may include dummy gate dielectrics 32 ( FIG. 3 B ) and dummy gate electrodes 34 over dummy gate dielectrics 32 .
  • Dummy gate electrodes 34 may be formed using, for example, amorphous silicon or polysilicon, and other materials may also be used.
  • Each of dummy gate stacks 30 may also include one (or a plurality of) hard mask layer 36 over dummy gate electrode 34 .
  • Hard mask layers 36 may be formed of silicon nitride, silicon carbo-nitride, or the like.
  • Dummy gate stacks 30 also have lengthwise directions perpendicular to the lengthwise directions of protruding fins 24 ′.
  • gate spacers 38 are multi-layer gate spacers.
  • each of gate spacers 38 may include a SiN layer, and a SiOCN layer over the SiN layer.
  • FIGS. 3 A and 3 C also illustrate fin spacers 39 formed on the sidewalls of protruding fins 24 ′. The respective process is also illustrated as process 206 in the process flow shown in FIG. 12 .
  • fin spacers 39 are formed by the same processes for forming gate spacers 38 .
  • the blanket dielectric layer(s) that are deposited for forming gate spacers 38 when etched, may have some portions left on the sidewalls of protruding fins 24 ′N and 24 P′, hence forming fin spacers 39 .
  • the fin spacers 39 include outer fin spacers such as fin spacers 39 A and 39 C ( FIG. 3 C ), which are on the outer side of the outmost fin in the fin-group.
  • the fin spacers 39 further include inner fin spacers such as fin spacer 39 B, with the inner fin spacer being between the fins 24 ′N and 24 P′ in the same fin-group.
  • n-type source/drain regions 42 N and p-type source/drain regions 42 P are formed in separate processes.
  • n-type source/drain regions 42 N are formed first, followed by the formation of p-type source/drain regions 42 P, which means the processes shown in the n-type device region 100 N in FIGS. 4 A, 4 B, 4 C, 5 , 6 , 7 A, and 7 B are performed first, followed by the processes shown in the p-type device region 100 P in FIGS. 4 A, 4 B, 4 C, 5 , 6 , 7 A, and 7 B .
  • p-type source/drain regions 42 P is formed first, followed by the formation of n-type source/drain region 42 N.
  • etching processes also referred to as a source/drain recessing process hereinafter
  • etching processes are performed to recess the portions of protruding fins 24 N′ and 24 P′ that are not covered by dummy gate stacks 30 and gate spacers 38 .
  • Recesses 40 N and 40 P are thus formed.
  • the respective processes are illustrated as process 208 N and 208 P in the process flow shown in FIG. 12 .
  • FIGS. 4 B and 4 C illustrate the cross-sectional views obtained from reference cross-sections B-B and C-C, respectively, in FIG. 4 A .
  • FIG. 4 C illustrate the portions of protruding fins 24 N′ and 24 P′ directly underlying gate spacers 38 and gate stacks 30 , and are shown as dashed since they are not in the illustrated plane. Also, the dashed lines also illustrate the recesses 40 N and 40 P.
  • the recessing may be anisotropic, and hence the portions of fins 24 N′ and 24 P′ directly underlying dummy gate stacks 30 and gate spacers 38 are protected, and are not etched.
  • Recesses 40 N and 40 P are also located on opposite sides of dummy gate stacks 30 , as shown in FIG. 4 A . It is appreciated that although shown in same Figures, recesses 40 N may be formed in a separate process from the formation of recesses 40 P, as shown in the process flow shown in FIG. 12 .
  • the sidewalls of protruding fins 24 N′ and 24 P′ facing recesses 40 N and 40 P may be on (110) surface planes.
  • the bottoms of recesses 40 N and 40 P are higher than the top surfaces 22 A of STI regions 22 .
  • the bottoms of recesses 40 N and 40 P may be level with or lower than the top surfaces 22 A of STI regions 22 .
  • the deposition of epitaxy layer 42 NA may be performed using Reduced Pressure Chemical Vapor Deposition (RPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), or the like.
  • RPCVD Reduced Pressure Chemical Vapor Deposition
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • phosphorous is discussed as an example of the n-type dopants, while other n-type dopant such as arsenic, antimony, or the like, or combinations thereof, may be used.
  • boron is discussed as an example of the p-type dopants, while other p-type dopant such as indium may be used.
  • epitaxy layer 42 NA is formed of or comprises SiP. In accordance with alternative embodiments, epitaxy layer 42 NA is formed of or comprises SiAs. In accordance with yet alternative embodiments, epitaxy layer 42 NA is formed of or comprises a SiAs layer and a SiP layer over the SiAs layer.
  • the process gas for depositing epitaxy layer 42 NA may include a silicon-containing gas such as silane, dicholorosilane (DCS), or the like, and a dopant-containing process gas such as PH 3 , AsH 3 , or the like, depending on the desirable composition of epitaxy layer 42 NA.
  • Epitaxy layer 42 NA may have a first doping concentration (such as P or As) in the range between about 1 ⁇ 10 20 /cm 3 and about 8 ⁇ 10 20 /cm 3 .
  • a first doping concentration such as P or As
  • an etching gas such as HCl is added into the process gases to achieve selective deposition on semiconductor, but not on dielectric.
  • Carrier gas(es) such as H 2 and/or N 2 may also be included in the process gas, for example, with a flow rate in the range between about 50 sccm and about 500 sccm.
  • epitaxy layers 42 PA (which are also referred to as epitaxy layers L 1 ) are deposited in p-type FinFET region 100 P through an epitaxy process.
  • the respective process is illustrated as process 210 P in the process flow shown in FIG. 12 .
  • the deposition is also performed through a non-conformal deposition process, so that the bottom portion of first layer 42 PA is thicker than the sidewall portions.
  • the deposition may be performed using RPCVD, PECVD, or the like.
  • epitaxy layer 42 PA is formed of or comprises SiGeB.
  • the process gas for depositing epitaxy layer 42 PA may include a silicon-containing gas such as silane, disilane (Si 2 H 6 ) dicholorosilane (DCS), or the like, a germanium-containing gas such as germane (GeH 4 ), digermane (Ge 2 H 6 ), or the like, and a dopant-containing process gas such as B 2 H 6 or the like, depending on the desirable composition of epitaxy layer 42 PA.
  • Epitaxy layer 42 PA may have a boron concentration in the range between about 1 ⁇ 10 20 /cm 3 and about 6 ⁇ 10 20 /cm 3 .
  • the germanium atomic percentage may be in the range between about 15 percent and about 40 percent.
  • the epitaxy layer 42 NB grown from neighboring recesses are merged, with air gap 44 N being sealed under epitaxy layer 42 NB.
  • the top surface of the merged epitaxy layer 42 NB may have a non-planar profile (also referred to as having a wavy shape), with the middle portion between neighboring semiconductor fins 24 N′ being lower than the portions on its opposite sides.
  • the germanium atomic percentage in epitaxy layer 42 PB is higher than the germanium atomic percentage in epitaxy layers 42 PA.
  • the germanium atomic percentage in epitaxy layer 42 PB may be in the range between about 40 percent and about 60 percent in accordance with some embodiments.
  • the process gas for forming epitaxy layer 42 PB may be similar to the process gas in the formation of epitaxy layer 42 PA, except the flow rates of the process gases may be different from the flow rates of the corresponding process gases in the formation of epitaxy layer 42 PA.
  • FIG. 11 B illustrates the cross-sectional views of the reference cross-sections B-B in FIG. 6 , which shows that the opposite ends of epitaxy layer 42 PB are level with the top surfaces of protruding fins 24 P′, while the middle portion of the top surface of epitaxy layer 42 PB may be lower than the top surfaces of protruding fins 24 N′.
  • the epitaxy layer 42 PB grown from neighboring recesses are merged, with air gap 44 P being sealed under epitaxy layer 42 PB.
  • the top surface of the merged epitaxy layer 42 PB may have a non-planar profile (also referred to as having a wavy shape), with the middle portion between neighboring fins 24 P′ (and the corresponding recesses 40 P) being lower than the portions on its opposite sides.
  • the top surface of the merged epitaxy layer 42 PB may have a planar profile (also referred to as having a non-wavy shape), and the corresponding planar top surface is demonstrated by dashed line 43 .
  • FIG. 7 A illustrates the epitaxy process for depositing epitaxy layer 42 NC (which is also referred to as epitaxy layer L 3 or a capping layer).
  • the respective process is illustrated as process 214 N in the process flow shown in FIG. 12 .
  • the deposition process may be performed using RPCVD, PECVD, or the like.
  • epitaxy layer 42 NC includes silicon phosphorous.
  • germanium may be incorporated, for example, with a germanium atomic percentage in the range between about 1 percent and about 5 percent.
  • the phosphorous concentration in epitaxy regions 42 NC may be in the range between about 1 ⁇ 10 21 /cm 3 and about 3 ⁇ 10 21 /cm 3 .
  • the process gas for forming epitaxy layer 42 NC may be similar to the process gas in the formation of epitaxy layer 42 NB, except a germanium-containing gas such as germane, digermane, or the like may be added.
  • epitaxy layers 42 NA, 42 NB, and 42 NC are collectively and individually referred to as epitaxy layers or epitaxy regions 42 N, which are collectively referred to as source/drain regions 42 N hereinafter.
  • FIG. 7 A further illustrates the epitaxy process for depositing epitaxy layer 42 PC (which is also referred to as epitaxy layer L 3 or a capping layer).
  • the respective process is illustrated as process 214 P in the process flow shown in FIG. 12 .
  • the deposition process may be performed using RPCVD, PECVD, or the like.
  • the top surface of epitaxy layer 42 PC has a non-wavy shape, with a middle portion of the top surface being the highest, and the opposite portions of the top surface being increasingly lower.
  • epitaxy layer 42 PC includes SiGeB.
  • the boron concentration in epitaxy regions 42 PC may be in the range between about 8 ⁇ 10 20 /cm 3 and about 1 ⁇ 10 21 /cm 3 .
  • the germanium atomic percentage in epitaxy layer 42 PC is lower than the germanium atomic percentage in epitaxy layers 42 PB.
  • the germanium atomic percentage in epitaxy layers 42 PC may be in the range between about 45 percent and about 55 percent in accordance with some embodiments.
  • epitaxy layers 42 PA, 42 PB, and 42 PC are collectively and individually referred to as epitaxy layers (regions) 42 P, which are collectively referred to as source/drain region 42 P hereinafter.
  • FIG. 7 B illustrates perspective views of source/drain regions 42 N and 42 P.
  • the top surface of epitaxy layer 42 NC maintains the wavy shape, with the middle portion of the top surface of the epitaxy layer 42 NC being lower than opposing portions.
  • the top surface of epitaxy layer 42 NC may include a V-shaped portion.
  • epitaxy layer 42 PC is grown thicker, and the top surface of epitaxy layer 42 PC has a non-wavy shape.
  • source/drain region 42 P has a cone-shaped cross-sectional view in the cross-section shown in FIG. 7 A .
  • Forming epitaxy layer 42 NC as having a wavy top surface and epitaxy layer 42 PC as having a non-wavy (for example, cone shape) has some advantageous features.
  • the wavy shape of epitaxy layer 42 NC results in the increase in the contact area between source/drain contact plug ( 66 N in FIG. 11 A ) and source/drain region 42 , and hence the reduction of contact resistance.
  • source/drain region 42 P is formed as having the wavy shape, there will be severe outward bending of protruding fins 24 P′. Experiment results have revealed that the bending may be reduced by increasing the raising height RH of source/drain region 42 P (and hence resulting in the cone shape). Accordingly, source/drain region 42 P is formed as non-wavy.
  • fin bending is not an issue for n-type FinFETs, so source/drain region 42 N may be formed as having wavy shapes.
  • the wavy height WH may be in the range between about 3 nm and about 15 nm in accordance with some embodiments.
  • the merge height MHN may be in the range between about 7 nm and about 20 nm, and may be smaller than about 50 percent of height H 1 of protruding fins 24 N′, wherein height H 1 may be in the range between about 40 nm and about 100 nm.
  • the ratio WH/(WH+MHN) may be in the range between about 0.1 and about 0.4.
  • outer width WON of epitaxy region 42 N which outer width WON is measured on the outer side of protruding fins 24 N′, is smaller than a half of the inner width WIN, which inner width WIN is the width of epitaxy region 42 N between protruding fins 24 N′.
  • outer width WON is in the range between about 5 nm and about 15 nm
  • half inner width WIN/2 is in the range between about 10 nm and about 30 nm. Having outer width WON being smaller than half inner width WIN/2 helps the formation of wavy shape.
  • the total width TWN of epitaxy region 42 N (based on two fins) may be in the range between about 40 nm and about 80 nm.
  • the raise height RH (which is the height difference between the topmost point of source/drain region 42 P and the top surface level of protruding fins 24 P′) is controlled to be in a certain range.
  • raise height RH is too small, in the subsequent formation of contact opening ( FIG. 10 ), epitaxy layers 42 PC and 42 PB may both be etched-through, and contact plug may land on epitaxy layer 42 PA, and may cause series boron loss issue.
  • raise height RH is too large, epitaxy layer 42 PC may not be etched-through, and the contact will land on epitaxy layer 42 PC, which has lower dopant concentration than epitaxy layer 42 PB.
  • raise height RH is in the range between about 5 nm and about 15 nm.
  • the merge height MHP may be in the range between about 40 nm and about 80 nm, and may be greater than about 50 percent of height H 1 of protruding fins 24 P′, wherein height H 1 may be in the range between about 40 nm and about 100 nm.
  • the ratio RH/MHP may be in the range between about 0.1 and about 0.4.
  • outer width WOP of epitaxy region 42 P which outer width WOP is on the outer side of protruding fins 24 P′, is greater than WIP/2, wherein inner width WIP is the width of the part of epitaxy region 42 P between protruding fins 24 P′.
  • outer width WOP is in the range between about 15 nm and about 30 nm
  • inner width WI 1 is in the range between about 20 nm and about 40 nm.
  • the total width TWP of epitaxy region 42 P may be in the range between about 40 nm and about 80 nm.
  • Ratio MHN/MHP may be in the range between about 0.15 and about 0.6.
  • CMP Chemical Mechanical Polish
  • replacement gate stacks 56 include gate dielectrics 52 , which further include interfacial layers on the top surfaces and sidewalls of protruding fins 24 ′, and high-k dielectrics on the interfacial layers. Replacement gate stacks 56 further include gate electrodes 54 over high-k dielectrics 52 . After the formation of replacement gate stacks 56 , replacement gate stacks 56 are recessed to form trenches between gate spacers 38 . A dielectric material such as silicon nitride, silicon oxynitride, or the like, is filled into the resulting trenches to form hard masks 58 .
  • a dielectric material such as silicon nitride, silicon oxynitride, or the like, is filled into the resulting trenches to form hard masks 58 .
  • the exposed top surface of epitaxy layer 42 NB is wavy, with the middle portion being recessed lower than the opposing portions on the opposite sides of the middle portion, so that the exposed top surface of epitaxy layer 42 NB has a V-shape in the cross-sectional view.
  • source/drain region 42 has a cone shape
  • epitaxy layer 42 PC is thicker than epitaxy layer 42 NC
  • the etching rate of epitaxy layer 42 PC is higher (for example, two times higher) than epitaxy layer 42 NC. This compensates for the greater thickness of epitaxy layer 42 PC, so that when epitaxy layer 42 NC is etched-through, epitaxy layer 42 PC is also etched-through, and the exposed top surface of epitaxy layer 42 PB also has a concave (wavy) shape.
  • FIGS. 11 A and 11 B source/drain silicide regions 64 N and 64 P and source/drain contact plugs 66 N and 66 P are formed.
  • FIG. 11 B illustrates the cross-sectional view in reference cross-section B-B in FIG. 11 A
  • FIG. 11 A illustrates the cross-sectional view in reference cross-section C-C in FIG. 11 B
  • the reference cross-sections B-B and C-C are also the same as in FIG. 4 A .
  • the formation of the source/drain silicide regions 64 N and 64 P includes depositing a metal layer such as a titanium layer, a cobalt layer, or the like, extending into both of openings 60 N and 60 P ( FIG. 10 ), and then performing an annealing process so that the bottom portions of the metal layer react with epitaxy layers 42 NB and 42 PB to form the silicide regions 64 N and 64 P, respectively.
  • the respective process is illustrated as process 222 in the process flow shown in FIG. 12 .
  • the remaining un-reacted metal layer may be removed.
  • Source/drain contact plugs 66 N and 66 P are then formed in trenches 60 N and 60 P, respectively, and are electrically connected to the respective source/drain silicide region 64 N and 64 P, respectively.
  • the respective process is illustrated as process 224 in the process flow shown in FIG. 12 .
  • depth DSN of the recess in silicide region 64 N which is also the depth of the concave recess of the top surface of epitaxy layer 42 NB, is greater than depth DSP, which is the depth of the recess in silicide region 64 N.
  • Depth DSP is also equal to the depth of the concave recess of the top surface of epitaxy layer 42 PB.
  • N-type FinFET 68 N and p-type FinFET 68 P are thus formed.
  • depth DSP is equal to 0, which means silicide region 64 N, instead of having a recess, is planar.
  • the embodiments of the present disclosure have some advantageous features.
  • the contact resistance which is the resistance of the source/drain contact plug and the source/drain regions is reduced since the wavy shape has increased contact area than planar shapes.
  • the p-type source/drain regions as having cone-shapes, the fin bending in the fins of the p-type FinFET is reduced.
  • the contact resistance of the source/drain contact plugs to the p-type source/drain regions is not increased (and actually also reduced) since the contact areas also have the wavy shape.
  • the source/drain regions of p-type FinFETs have a boost of strain, and hence a boost of current.
  • a method comprises forming an n-type FinFET comprising forming a first gate stack on a first semiconductor fin and a second semiconductor fin; etching first portions of the first semiconductor fin and the second semiconductor fin to form a first recess and a second recess, respectively; and performing first epitaxy processes to form an n-type source/drain region, wherein the n-type source/drain region comprises a first portion grown from the first recess and a second portion grown from the second recess, and a first middle portion joined to the first portion and the second portion, wherein the first middle portion has a concave top surface; and forming a p-type FinFET comprising forming a second gate stack on a third semiconductor fin and a fourth semiconductor fin; etching second portions of the third semiconductor fin and the fourth semiconductor fin to form a third recess and a fourth recess, respectively; and performing second epitaxy processes to form a p-type source/drain
  • the method further comprises forming a first source/drain silicide region on the n-type source/drain region; and forming a second source/drain silicide region on the p-type source/drain region, wherein the first source/drain silicide region and the second source/drain silicide region have a first downward-pointing V-shape and a second downward-pointing V-shape, respectively.
  • the first downward-pointing V-shape has a greater height than the second downward-pointing V-shape.
  • the p-type source/drain region comprises a first layer, a second layer over the first layer, and a third layer over the second layer, and wherein the first layer grows laterally to form facets.
  • the n-type source/drain region comprises a fourth layer, a fifth layer over the fourth layer, and a sixth layer over the fifth layer, wherein portions of the fourth layer grown from the first recess and the second recess are limited in the first recess and the second recess.
  • the p-type source/drain region comprises SiGeB, and the third layer has a lower germanium atomic percentage than the second layer, and wherein the method further comprises etching-through the third layer to expose the second layer, and the exposed second epitaxy layer has an additional concave top surface.
  • the p-type source/drain region comprises a p-type capping layer as a top part of the second middle portion, and wherein the p-type capping layer comprises the convex top surface, and a concave bottom surface.
  • the first epitaxy processes and the second epitaxy processes are performed using remote plasma chemical vapor deposition.
  • the first capping layer and the first epitaxy layer comprise silicon phosphorus, and the first capping layer has a lower phosphorous concentration than the first epitaxy layer.
  • the second capping layer and the second epitaxy layer comprise silicon germanium boron, and the second capping layer has a lower germanium atomic percentage than the second epitaxy layer.
  • a method comprises etching a first semiconductor fin and a second semiconductor fin to form a first recess and a second recess, respectively; epitaxially growing an n-type source/drain region comprising a first portion grown from the first recess; a second portion grown from the second recess; and a first middle portion between the first portion and the second portion, wherein the first middle portion has a concave top surface; forming a first contact opening extending into the n-type source/drain region, wherein the first contact opening comprises a first V-shaped bottom; etching a third semiconductor fin and a fourth semiconductor fin to form a third recess and a fourth recess, respectively; forming a p-type source/drain region comprising a third portion grown from the third recess; a fourth portion grown from the fourth recess; and a second middle portion between the third portion and the fourth portion, wherein the second middle portion has a convex top surface
  • the etched second middle portion has a middle part thicker than parts on opposing sides of the middle part. In an embodiment, the second middle portion has a highest point higher than top surfaces of the third semiconductor fin and the fourth semiconductor fin. In an embodiment, the first V-shaped bottom has a first height greater than a second height of the second V-shaped bottom.

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KR1020210018846A KR102629827B1 (ko) 2020-08-13 2021-02-10 N-타입 finfet들 및 p-타입 finfet들을 위한 상이한 소스/드레인 프로파일들
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