US11355685B2 - Light emitting diode, light emitting diode module, and display device having the light emitting diode module - Google Patents

Light emitting diode, light emitting diode module, and display device having the light emitting diode module Download PDF

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US11355685B2
US11355685B2 US16/557,184 US201916557184A US11355685B2 US 11355685 B2 US11355685 B2 US 11355685B2 US 201916557184 A US201916557184 A US 201916557184A US 11355685 B2 US11355685 B2 US 11355685B2
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light emitting
emitting diode
diode chip
solder
disposed
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US20190393392A1 (en
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Seung Li CHOI
Se Min Bang
Se Won Tae
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Seoul Semiconductor Co Ltd
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Seoul Semiconductor Co Ltd
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Priority claimed from PCT/KR2019/005826 external-priority patent/WO2019221508A1/ko
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336—Illuminating devices
    • G02F1/133602—Direct backlight
    • G02F1/133603—Direct backlight with LEDs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336—Illuminating devices
    • G02F1/133602—Direct backlight
    • G02F1/133608—Direct backlight including particular frames or supporting means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/387—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape with a plurality of electrode regions in direct contact with the semiconductor body and being electrically interconnected by another electrode layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/50—Wavelength conversion elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/50—Wavelength conversion elements
    • H01L33/501—Wavelength conversion elements characterised by the materials, e.g. binder
    • H01L33/502—Wavelength conversion materials
    • H01L33/504—Elements with two or more wavelength conversion materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09472—Recessed pad for surface mounting; Recessed electrode of component

Definitions

  • Exemplary embodiments of the invention relate generally to a light emitting diode, a light emitting diode module, and a display device having the light emitting diode module and, more specifically, to a light emitting diode, a light emitting diode module, and a display device having the same with improved reliability.
  • a light emitting diode is broadly classified into a top-emission type light emitting diode and a side-emission type light emitting diode.
  • a side-emission type light emitting diode package in which light is incident into a side surface of a light guide plate, is widely used as a light source for a backlight of a display device.
  • the side-emission type light emitting diode package is becoming more widely used and applied in many fields in addition to a backlight of a conventional display device.
  • a thickness of the side-emission type light emitting diode package is also becoming thinner.
  • a space between a light emitting diode chip and a reflector becomes narrower.
  • a design for heat dissipation is required according to a temperature rise from the narrowed space.
  • a light emitting diode, a light emitting diode module, and a display device having the light emitting diode module constructed according to exemplary embodiments of the invention are free from disconnection and have excellent heat resistance.
  • a light emitting diode, a light emitting diode module, and a display device having the light emitting diode module according to exemplary embodiments also have a thin thickness and a high degree of integration.
  • a light emitting diode includes a lead frame unit, and a light source unit disposed on the lead frame unit, the lead frame unit including a body portion having a first surface contacting the light source unit and a second surface opposite to the first surface, the body portion including at least one solder hole recessed from the second surface of the body portion, a first conductive layer disposed on the first surface of the body portion and including a circular portion having a substantially circular shape and an elongated portion provided integrally with the circular portion and elongating in one direction from the circular portion, a second conductive layer disposed on the second surface of the body portion, and a connection portion disposed between the first conductive layer and the second conductive layer and penetrating through the body portion.
  • the elongated portion may have a width less than a diameter of the circular portion.
  • connection portion may overlap at least a portion of the circular portion in a plan view.
  • connection portion may be disposed on a through hole defined through the body portion and may include a connection portion conductive layer disposed on a surface of the through hole, a plug disposed on the connection portion conductive layer and filling the through hole, and a cover plate disposed on the through hole to cover the through hole.
  • the cover plate may have a same shape as the connection portion conductive layer on the first surface and the second surface of the body portion.
  • the lead frame unit may have a third surface connecting the first surface and the second surface, and the solder hole may be defined over the second surface and the third surface.
  • the solder hole may have a substantially semi-circular or substantially semi-elliptical shape in the second surface of the body portion, and may have a substantially pentagonal shape in the third surface, and at least one internal angle defined by the pentagonal shape may be in a range from about 120 degrees to about 170 degrees.
  • the solder hole may have a substantially semi-circular or substantially semi-elliptical shape in the second surface of the body portion, and a radius of the substantially semi-circular or substantially semi-elliptical shape may be in a range from about 10% to about 50% of a thickness of the body portion.
  • the light emitting diode may further include a solder insulating layer disposed on the second surface, in which the solder insulating layer may cover at least a portion of the second conductive layer disposed between the solder holes.
  • solder hole and the connection portion may be spaced apart from each other by at least about 50 ⁇ m when viewed from the second surface.
  • the light source unit may include a first light emitting diode chip and a second light emitting diode chip disposed on the lead frame unit to be substantially parallel to each other.
  • the light emitting diode may further include a first wavelength converter and a second wavelength converter configured to emit light having a same wavelength as each other, the first wavelength converter may be disposed on the first light emitting diode chip to convert a wavelength of light emitted from the first light emitting diode chip to a first wavelength band, the second wavelength converter may be disposed on the second light emitting diode chip to convert a wavelength of light emitted from the second light emitting diode chip to a second wavelength band different from the first wavelength band.
  • the first wavelength converter may be disposed on the first light emitting diode chip to convert a wavelength of light emitted from the first light emitting diode chip to a first wavelength band
  • the second wavelength converter may be disposed on the second light emitting diode chip to convert a wavelength of light emitted from the second light emitting diode chip to a second wavelength band different from the first wavelength band.
  • a light transmission portion may be disposed on the first wavelength converter and the second wavelength converter, and the first wavelength converter and the second wavelength converter may have a thickness smaller than a thickness of the light transmission portion.
  • the first light emitting diode chip and the second light emitting diode chip may be configured to emit light having a same wavelength as each other.
  • the first conductive layer may include a first upper electrode electrically connected to the first light emitting diode chip, a second upper electrode electrically connected to the first light emitting diode chip, a third upper electrode electrically connected to the second light emitting diode chip, and a fourth upper electrode electrically connected to the second light emitting diode chip.
  • the first light emitting diode chip and the second light emitting diode chip may overlap at least a portion of the first conductive layer in a plan view.
  • the light source unit may include a first light emitting diode chip and a second light emitting diode chip, and the first light emitting diode chip and the second light emitting diode chip may be spaced apart from each other by a first interval when viewed from a top of the light source unit. At least one of the first light emitting diode chip and the second light emitting diode chip may be spaced apart from an edge of the light source unit by a light emitting diode chip margin when viewed from a top of the light source unit, and the first interval may be greater than the light emitting diode chip margin.
  • the light source unit may have substantially a rectangular shape with long sides and short sides when viewed in a top view, the first light emitting diode chip and one short side of the light source unit adjacent to the first light emitting diode chip may be spaced apart from each other by a second interval, and the second light emitting diode chip and the other short side of the light source unit adjacent to the second light emitting diode chip may be spaced apart from each other by a third interval.
  • the first interval is greater than the second interval and the third interval.
  • a light emitting diode package includes a lead frame unit, a light source unit disposed on the lead frame unit, an external frame disposed at one side portion of the lead frame unit, and a solder ball connecting the lead frame unit to the external frame, in which the lead frame unit includes a body portion having a first surface contacting the light source unit, a second surface opposite to the first surface, and a third surface connecting the first surface and the second surface, the body portion including at least one solder hole recessed from the second surface and the third surface, a first conductive layer disposed on the first surface of the body portion, a second conductive layer disposed on the second surface of the body portion, and a through hole disposed between the first conductive layer and the second conductive layer and penetrating the body portion.
  • a shape of the solder hole from the second surface may be different from a shape of the solder hole from the third surface.
  • the external frame may be disposed to face the third surface of the body portion, the light source unit may include at least one light emitting diode chip, and a direction to which light emitted from the light emitting diode chip travels is substantially perpendicular to a direction in which the external frame is coupled to the body portion.
  • the through hole may be defined to be substantially parallel to the external frame, and the through hole and the solder hole may be spaced apart from each other.
  • the solder paste may be disposed in a first area between the second conductive layer and the external frame and a second area outside the body portion, and the solder paste disposed in the second area may cover at least a portion of the second conductive layer.
  • the light emitting diode package may further include a solder insulating layer disposed on the second surface, in which the solder insulating layer may cover at least a portion of the second conductive layer disposed between the solder holes.
  • FIG. 1 is a perspective view of a light emitting diode according to an exemplary embodiment.
  • FIG. 2A is a perspective view of a light emitting diode according to an exemplary embodiment.
  • FIG. 2B is a cross-sectional view taken along line I-I′ of FIG. 2A according to an exemplary embodiment.
  • FIG. 2C is a cross-sectional view taken along line I-I′ of FIG. 2A according to another exemplary embodiment.
  • FIG. 2D is a cross-sectional view of a light emitting diode in which a lead frame unit and a light emitting unit are coupled to each other of FIG. 2A .
  • FIGS. 3A, 3B, 3C, 3D, and 3E are plan views of a first surface and a second surface of a lead frame unit according to exemplary embodiments.
  • FIGS. 4A, 4B, 4C, 4D, 4E, 4F, and 4G are plan views of a second surface of a lead frame unit according to exemplary embodiments.
  • FIG. 5A is a side view of a third surface of a lead frame unit according to an exemplary embodiment.
  • FIG. 5B is a cross-sectional view of a lead frame unit according to an exemplary embodiment.
  • FIG. 6 is a plan view of a light emitting diode according to an exemplary embodiment.
  • FIG. 7 is a perspective view of a light emitting diode according to an exemplary embodiment.
  • FIG. 8A is a perspective view of a light emitting diode according to an exemplary embodiment.
  • FIG. 8B is a cross-sectional view taken along line II-II′ of FIG. 8A .
  • FIGS. 9A and 9B are plan views of a first surface and a second surface of a lead frame unit according to an exemplary embodiment, respectively.
  • FIG. 10A is a plan view of a light source unit according to an exemplary embodiment.
  • FIG. 10B is a cross-sectional view taken along line A-A′ of FIG. 10A .
  • FIG. 10C is a cross-sectional view taken along line B-B′ of FIG. 10A .
  • FIG. 10D is a cross-sectional view taken along line C-C′ of FIG. 10A .
  • FIG. 10E is a magnified view of M 1 in FIG. 10D .
  • FIGS. 11A and 11B are perspective views of a light emitting diode module according to an exemplary embodiment.
  • FIGS. 12A and 12B are cross-sectional views of a light emitting diode module according to an exemplary embodiment.
  • FIG. 13 is a perspective view of a light emitting diode module according to an exemplary embodiment.
  • FIG. 14 is a cross-sectional view of a display device to which a light emitting diode module is applied according to an exemplary embodiment.
  • FIGS. 15A, 15B, 15C, and 15D are plan views of an upper surface of a mother substrate according to an exemplary embodiment.
  • FIGS. 16A and 16B are plan views of an upper surface of a mother substrate according to an exemplary embodiment.
  • FIG. 17 is a plan view of a lower surface of a body portion according to an exemplary embodiment.
  • the illustrated exemplary embodiments are to be understood as providing exemplary features of varying detail of some ways in which the inventive concepts may be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions, and/or aspects, etc. (hereinafter individually or collectively referred to as “elements”), of the various embodiments may be otherwise combined, separated, interchanged, and/or rearranged without departing from the inventive concepts.
  • an element such as a layer
  • it may be directly on, connected to, or coupled to the other element or layer or intervening elements or layers may be present.
  • an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present.
  • the term “connected” may refer to physical, electrical, and/or fluid connection, with or without intervening elements.
  • the D1-axis, the D2-axis, and the D3-axis are not limited to three axes of a rectangular coordinate system, such as the x, y, and z-axes, and may be interpreted in a broader sense.
  • the D1-axis, the D2-axis, and the D3-axis may be perpendicular to one another, or may represent different directions that are not perpendicular to one another.
  • “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be construed as X only, Y only, Z only, or any combination of two or more of X, Y, and Z, such as, for instance, XYZ, XYY, YZ, and ZZ.
  • the term “and/or” includes any and all combinations of one or more of the associated listed items.
  • Spatially relative terms such as “beneath,” “below,” “under,” “lower,” “above,” “upper,” “over,” “higher,” “side” (e.g., as in “sidewall”), and the like, may be used herein for descriptive purposes, and, thereby, to describe one elements relationship to another element(s) as illustrated in the drawings.
  • Spatially relative terms are intended to encompass different orientations of an apparatus in use, operation, and/or manufacture in addition to the orientation depicted in the drawings. For example, if the apparatus in the drawings is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features.
  • the exemplary term “below” can encompass both an orientation of above and below.
  • the apparatus may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and, as such, the spatially relative descriptors used herein interpreted accordingly.
  • exemplary embodiments are described herein with reference to sectional and/or exploded illustrations that are schematic illustrations of idealized exemplary embodiments and/or intermediate structures. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, exemplary embodiments disclosed herein should not necessarily be construed as limited to the particular illustrated shapes of regions, but are to include deviations in shapes that result from, for instance, manufacturing. In this manner, regions illustrated in the drawings may be schematic in nature and the shapes of these regions may not reflect actual shapes of regions of a device and, as such, are not necessarily intended to be limiting.
  • FIG. 1 is a perspective view of a light emitting diode 10 according to an exemplary embodiment.
  • the light emitting diode 10 includes a lead frame unit 100 and a light source unit 200 mounted on the lead frame unit 100 .
  • the light source unit 200 is disposed on an upper surface of the lead frame unit 100 , which provides a lead frame structure for connecting a light emitting diode chip included in the light source unit 200 to an external circuit. More particularly, the lead frame unit 100 is connected to first and second electrode pads of the light emitting diode chip included in the light source unit 200 , and supplies a power necessary to emit light from the light source unit 200 .
  • the light source unit 200 emits a light with a predetermined wavelength in response to the power applied thereto from the outside.
  • the light source unit 200 includes the light emitting diode chip, a transparent portion disposed on a front surface of the light emitting diode chip, and a housing surrounding the light emitting diode chip and the transparent portion, and emits light with the predetermined wavelength through the transparent portion.
  • the light source unit 200 may further include, for example, a wavelength converter that converts the wavelength of light emitted from the light emitting diode chip.
  • FIG. 2A is a perspective view of the light emitting diode according to an exemplary embodiment.
  • FIG. 2B is a cross-sectional view taken along line I-I′ of FIG. 2A according to an exemplary embodiment
  • FIG. 2C is a cross-sectional view taken along line I-I′ of FIG. 2A according to another exemplary embodiment.
  • FIG. 2D is a cross-sectional view of a light emitting diode in which a lead frame unit and a light emitting unit are coupled to each other of FIG. 2A .
  • the lead frame unit 100 includes a body portion 110 , a first conductive layer 120 , a second conductive layer 130 , a connection portion 140 , a solder hole 150 , and a solder insulating layer 160 .
  • the body portion 110 has an insulating property and serves as a base, on which the first conductive layer 120 , the second conductive layer 130 , the connection portion 140 , and the solder hole 150 are provided.
  • the body portion 110 may be formed of a material having the insulating property.
  • the body portion 110 may include an organic polymer material.
  • the organic polymer material at least one resin selected from an acrylic-based resin, a polyester-based resin, a polyurethane-based resin, an epoxy-based resin, a vinyl-based resin, a polystyrene-based resin, a polyamide-based resin, and a urea-based resin may be used.
  • the inventive concepts are not limited thereto, as long as the material for the body portion 110 has an insulating property.
  • the body portion 110 may have a substantially rectangular parallelepiped shape.
  • the body portion 110 may have a shape defined by a relatively long length and a relatively small height, and thickness to mount a plurality of light emitting diode chips 20 and 20 ′.
  • the inventive concepts are not limited to on shape of the body portion 110 , and in some exemplary embodiments, the body portion 110 may have various shapes other than the rectangular parallelepiped shape.
  • the body portion 110 may include a first surface, a second surface, and a third surface.
  • the first surface of the body portion 110 may be a surface that makes contact with the light source unit 200
  • the second surface may be a surface that is opposite to the first surface
  • the third surface may be a surface that connects the first surface and the second surface.
  • the first surface may be referred to as the upper surface of the body portion 110
  • the second surface may be referred to as the lower surface of the body portion 110
  • the third surface may be referred to as the side surface of the body portion 110 .
  • the first conductive layer 120 is disposed on the upper surface of the body portion 110 and electrically connected to the light emitting diode chips 20 and 20 ′.
  • the first conductive layer 120 may be electrically connected to pad portions 39 a , 39 b , 39 a ′, and 39 b ′ of the light emitting diode chips 20 and 20 ′.
  • the power may be supplied to the light emitting diode chips 20 and 20 ′ via the first conductive layer 120 .
  • the first conductive layer 120 may be formed of a material having a conductivity.
  • the first conductive layer 120 may include metal, such as Au, Pt, Pd, Rh, Ni, W, Mo, Cr, Ti, Fe, Cu, Al, Ag, In, and Sn, oxides thereof, and/or nitrides thereof.
  • the first conductive layer 120 may have a single-layer or multi-layer structure.
  • the first conductive layer 120 may include a plurality of cathodes and anodes.
  • the first conductive layer 120 may include a first upper electrode 121 , a second upper electrode 122 , a third upper electrode 123 , and a fourth upper electrode 124 , and each of the first, second, third, and fourth upper electrodes 121 , 122 , 123 , and 124 may serve as the cathode or the anode.
  • the first upper electrode 121 , the second upper electrode 122 , the third upper electrode 123 , and the fourth upper electrode 124 may be disposed on the upper surface of the body portion 110 to be parallel to each other.
  • the first conductive layer 120 may be provided such that the first upper electrode 121 and the fourth upper electrode 124 are disposed at outermost positions of the body portion 110 , and the second upper electrode 122 and the third upper electrode 123 are disposed between the first upper electrode 121 and the fourth upper electrode 124 .
  • a first electrode pad 39 a of a first light emitting diode chip 20 connected to the first upper electrode 121 may be a p-type
  • a second electrode pad 39 b of the first light emitting diode chip 20 connected to the second upper electrode 122 may be an n-type
  • a first electrode pad 39 a ′ of a second light emitting diode chip 20 ′ may be the p-type
  • a second electrode pad 39 b ′ of the second light emitting diode chip 20 ′ may be the n-type.
  • a user may identify whether the first light emitting diode chip 20 and the second light emitting diode chip 20 ′ disposed on the lead frame unit 100 are normally operated by substantially simultaneously applying signals to the first, second, third, and fourth upper electrodes 121 , 122 , 123 , and 124 .
  • a driving signal provided via a first lower electrode 131 is discharged to a third lower electrode 133 after sequentially passing through the first, second, third, and fourth upper electrodes 121 , 122 , 123 , and 124 .
  • the user may identify whether the first light emitting diode chip 20 and the second light emitting diode chip 20 ′ are normally operated.
  • first light emitting diode chip 20 and the second light emitting diode chip 20 ′ may be independently operated.
  • the first light emitting diode chip 20 and the second light emitting diode chip 20 ′ may be independently operated by respectively connecting an anode and a cathode of a first external power source to the first upper electrode 121 and the second upper electrode 122 , respectively connecting an anode and a cathode of a second external power source to the third upper electrode 123 and the fourth upper electrode 124 , and controlling on/off of the first external power source and the second external power source.
  • inventive concepts are not limited to a particular arrangement of the first upper electrode 121 , the second upper electrode 122 , the third upper electrode 123 , and the fourth upper electrode 124 , and the arrangement thereof may be various modified.
  • the first, second, third, and fourth upper electrodes 121 , 122 , 123 , and 124 may be arranged to be spaced apart from each other to prevent the first, second, third, and fourth upper electrodes 121 , 122 , 123 , and 124 from being short-circuited with each other.
  • the first conductive layer 120 may include a cover plate and a bump.
  • the first upper electrode 121 may include a first cover plate 141 _ 3 and a first bump 41 .
  • the first bump 41 may be omitted.
  • the first cover plate 141 _ 3 may form the first upper electrode 121 .
  • the bumps may be formed in the first, second, third, and fourth upper electrodes 121 , 122 , 123 , and 124 , and in particular, first, second, third, and fourth bumps 41 , 42 , 43 , and 44 may be respectively included in the first, second, third, and fourth upper electrodes 121 , 122 , 123 , and 124 .
  • the first, second, third, and fourth bumps 41 , 42 , 43 , and 44 are disposed between the first and second light emitting diode chips 20 and 20 ′ and the body portion 110 to assist electrical connection between the first and second light emitting diode chips 20 and 20 ′ and the body portion 110 .
  • the first, second, third, and fourth bumps 41 , 42 , 43 , and 44 may be formed of a conductive paste.
  • the first, second, third, and fourth bumps 41 , 42 , 43 , and 44 may include metal, such as Cu, AuSn, Al, Au, and Ag.
  • the second conductive layer 130 is disposed on the lower surface of the body portion 110 and electrically connected to an electrode of an external frame.
  • the second surface or the lower surface of the body portion 110 may be a surface opposite to the first surface or the upper surface of the body portion 110 , on which the first conductive layer 120 is disposed.
  • the second conductive layer 130 is disposed above at least a portion of the solder hole 150 defined in the body portion 110 . Accordingly, the second conductive layer 130 has a shape that covers a portion of the lower surface of the body portion 110 and the solder hole 150 .
  • the second conductive layer 130 may be formed of a material having a conductivity.
  • the second conductive layer 130 may include metal, such as Au, Pt, Pd, Rh, Ni, W, Mo, Cr, Ti, Fe, Cu, Al, Ag, In, and Sn, oxides thereof, and/or nitrides thereof.
  • the second conductive layer 130 may have a single-layer or multi-layer structure.
  • the second conductive layer 130 may include Cu, Ni, and Au sequentially stacked one on another.
  • Au may be disposed at an outermost position
  • Cu may be disposed at an innermost position.
  • the second conductive layer 130 may be formed by an electroless plating method.
  • Cu in the second conductive layer 130 may enhance electrical conductivity
  • Au in the second conductive layer 130 may increase a bonding force or a solderability between the solder paste, which is provided on the second conductive layer 130 .
  • Ni provided between Cu and Au may serve as a barrier metal that prevents Au from being diffused into Cu.
  • the second conductive layer 130 has the multi-layer structure of Cu, Ni, and Au, the electrical conductivity and the bonding force with the solder paste may be improved.
  • the second conductive layer 130 may include a plurality of conductive patterns spaced apart from each other.
  • the second conductive layer 130 may include the first lower electrode 131 , a second lower electrode 132 , and the third lower electrode 133 .
  • the first lower electrode 131 , the second lower electrode 132 , and the third lower electrode 133 may be disposed on the lower surface of the body portion 110 to be parallel to each other.
  • the first lower electrode 131 , the second lower electrode 132 , and the third lower electrode 133 may be spaced apart from each other by a predetermined distance to prevent the first lower electrode 131 , the second lower electrode 132 , and the third lower electrode 133 from being short-circuited with each other.
  • the second lower electrode 132 may be provided as two portions spaced apart from each other or as a single portion. When the second lower electrode 132 is provided as two portions spaced apart from each other, the two portions may be connected to a second connection portion 142 and a third connection portion 143 , respectively.
  • the first lower electrode 131 , the second lower electrode 132 , and the third lower electrode 133 may be disposed to overlap with the first upper electrode 121 , the second upper electrode 122 , the third upper electrode 123 , and the fourth upper electrode 124 when viewed in a plan view.
  • the first lower electrode 131 may be disposed to overlap with the first upper electrode 121 when viewed in a plan view
  • the third lower electrode 133 may be disposed to overlap with the fourth upper electrode 124 when viewed in a plan view
  • the second lower electrode 132 may be disposed to overlap with the second and third upper electrodes 122 and 123 when viewed in a plan view.
  • the first lower electrode 131 , the second lower electrode 132 , and the third lower electrode 133 may perform different functions from each other on the lead frame unit 100 .
  • the first lower electrode 131 may serve as the cathode
  • the third lower electrode 133 may serve as the anode.
  • the second lower electrode 132 may be provided as two portions spaced apart from each other, and the portion closer to the first lower electrode 131 may serve as the anode, and the portion closer to the third lower electrode 133 may serve as the cathode.
  • the first lower electrode 131 and the third lower electrode 133 may serve as the cathode, and the second lower electrode 132 provided as a single portion may serve as the anode.
  • connection portion 140 is disposed between the first conductive layer 120 and the second conductive layer 130 and penetrates through the body portion 110 .
  • the connection portion 140 has a conductivity. Therefore, the first conductive layer 120 and the second conductive layer 130 may be electrically connected to each other by the connection portion 140 .
  • connection portion 140 may be disposed above a through hole defined through the body portion 110 , and a portion of the connection portion 140 may have a shape determined by the shape of the through hole.
  • the connection portion 140 may be provided in a plural number.
  • the connection portion 140 may include a first connection portion 141 , the second connection portion 142 , the third connection portion 143 , and a fourth connection portion 144 .
  • the first, second, third, and fourth connection portions 141 , 142 , 143 , and 144 may be connected to the first conductive layer 120 and the second conductive layer 130 .
  • the first connection portion 141 may connect the first upper electrode 121 of the first conductive layer 120 to the first lower electrode 131 of the second conductive layer 130 .
  • the second and third connection portions 142 and 143 may connect the second and third upper electrodes 122 and 123 to the second lower electrode 132 .
  • the fourth connection portion 144 may connect the fourth upper electrode 124 to the third lower electrode 133 .
  • connection portion 140 connects the electrodes disposed on the upper and lower surfaces of the body portion 110
  • the driving signal and the power from the outside may be applied to the light emitting diode chips 20 and 20 ′ through the second conductive layer 130 , the connection portion 140 , and the first conductive layer 120 .
  • the same driving signal and power may be applied to the two upper electrodes 122 and 123 .
  • the first light emitting diode chip 20 mounted on the second upper electrode 122 and the second light emitting diode chip 20 ′ mounted on the third upper electrode 123 may be connected to each other in series.
  • connection portion 140 may be provided in a VIA plug form.
  • the first connection portion 141 may include a connection portion conductive layer 141 _ 1 , a plug 141 _ 2 , and a cover plate 141 _ 3 .
  • connection portion conductive layer 141 _ 1 is electrically connected to the first conductive layer 120 on the upper surface of the body portion 110 and electrically connected to the second conductive layer 130 on the lower surface of the body portion 110 .
  • the plug 141 _ 2 may be formed by filling an electrically conductive material or an electrically nonconductive material in the through hole and on the connection portion conductive layer 141 _ 1 . Accordingly, the shape of the plug 141 _ 2 may be changed depending on the shape of the through hole and the connection portion conductive layer 141 _ 1 . For example, when the through hole has a cylindrical shape, the plug 141 _ 2 filled in the through hole may also have a substantially cylindrical shape.
  • the plug 141 _ 2 may fill the through hole tightly. As the plug 141 _ 2 fills the through hole, a structural stability of the connection portion 140 may be improved.
  • connection portion conductive layer 141 _ 1 having a thin film shape may be broken by a distortion of the body portion 110 or an external impact.
  • the plug 141 _ 2 provided with the connection portion conductive layer 141 _ 1 buffers the distortion of the body portion 110 or the external impact, the connection portion conductive layer 141 _ 1 may be protected therefrom. As such, the structural stability of the connection portion 140 may be improved.
  • the cover plate 141 _ 3 is disposed above the upper surface and/or the lower surface of the body portion 110 to cover the through hole.
  • the cover plate 141 _ 3 may reinforce the electrical connection and the mechanical connection between the connection portion 140 and the first and second conductive layers 120 and 130 .
  • the cover plate 141 _ 3 is provided to cover an upper surface and/or a lower surface of the connection portion conductive layer 141 _ 1 and prevents the connection portion conductive layer 141 _ 1 from being disconnected from the first conductive layer 120 or the second conductive layer 130 .
  • the cover plate 141 _ 3 may overlap with the connection portion conductive layer 141 _ 1 when viewed in a plan view.
  • the connection portion conductive layer 141 _ 1 may not be exposed on the upper surface or the lower surface of the body portion 110 .
  • the cover plate 141 _ 3 may have substantially the same shape as the connection portion conductive layer 141 _ 1 on the upper surface and the lower surface of the body portion 110 .
  • the solder hole 150 may have a shape recessed from the lower surface of the body portion 110 by removing a portion of the lower surface of the body portion 110 .
  • the solder hole 150 may have a shape, in which a portion of the lower surface is removed to a predetermined depth, and thus, the solder hole 150 formed over the second surface (or the bottom surface) and the third surface (or the side surface) of the body portion 110 may be provided.
  • the solder hole 150 may have different shapes when viewed from the second and third sides of the body portion 110 .
  • the solder hole 150 may have a semi-circular shape or a semi-elliptical shape when viewed from the second side of the body portion 110 .
  • the solder hole 150 may have a pentagonal shape when viewed on the third side of the body portion 110 . Detailed descriptions of the shape of the solder hole 150 will be described later.
  • the solder hole 150 allows the light emitting diode 10 to be connected to an external frame.
  • the light emitting diode 10 and the external frame may be connected to each other by the solder paste provided in the solder hole 150 .
  • the solder hole 150 may be provided in a plural number.
  • the solder hole 150 may include a first solder hole 151 , a second solder hole 152 , and a third solder hole 153 .
  • the first, second, and third solder holes 151 , 152 , and 153 may be provided to be spaced apart from each other.
  • the first, second, and third solder holes 151 , 152 , and 153 may have the same or different shapes.
  • the solder hole 150 may be spaced apart from the through hole. Accordingly, an unnecessary connection between the solder hole 150 and the through hole may be prevented from occurring.
  • the second conductive layer 130 may be provided in the solder hole 150 . Accordingly, when the solder paste is provided in the solder hole 150 , the second conductive layer 130 and the solder paste may be connected to each other.
  • the second conductive layer 130 provided in the solder hole 150 may be connected to at least one of the first lower electrode 131 , the second lower electrode 132 , and the third lower electrode 133 .
  • the solder hole 150 may have the semi-circular or semi-elliptical shape when viewed on the lower surface of the body portion 110 , and may have the pentagonal shape when viewed on the side surface of the body portion 110 , and thus, the light emitting diode 10 and the external frame may be more stably connected to each other.
  • the shape of the solder hole 150 will be described in detail later.
  • the solder insulating layer 160 is disposed between the first, second, and third solder holes 151 , 152 , and 153 to prevent a short circuit between the second conductive layer 130 and/or the solder paste provided in the first, second, and third solder holes 151 , 152 and 153 .
  • the solder insulating layer 160 may have various shapes. The shape of the solder insulating layer 160 will be described in detail later.
  • the light source unit 200 may include a light transmission portion 220 and the first and second light emitting diode chips 20 and 20 ′.
  • the first and second light emitting diode chips 20 and 20 ′ may emit lights having the same wavelength or different wavelengths.
  • the first and second light emitting diode chips 20 and 20 ′ may emit lights having the wavelength of about 449 nm.
  • the first and second light emitting diode chips 20 and 20 ′ may emit lights having the wavelengths of about 448 nm and about 450 nm, respectively, or lights having the wavelengths of about 447 nm and about 451 nm, respectively.
  • the light source unit 200 may be manufactured such that an average wavelength of lights emitted from the first light emitting diode chip 20 and the second light emitting diode chip 20 ′ is about 449 nm.
  • the inventive concepts are not limited thereto, and in some exemplary embodiments, each of the first light emitting diode chip 20 and the second light emitting diode chip 20 ′ may emit light having a wavelength different from the wavelength of about 449 nm.
  • the first light emitting diode chip 20 and the second light emitting diode chip 20 ′ may be substantially simultaneously operated or independently operated.
  • the first light emitting diode chip 20 includes the first electrode pad 39 a and the second electrode pad 39 b .
  • the second light emitting diode chip 20 ′ includes two electrode pads 39 a ′ and 39 b ′.
  • the first electrode pad 39 a is electrically connected to the first upper electrode 121
  • the second electrode pad 39 b is electrically connected to the second upper electrode 122 . Accordingly, the electrical signal may be applied to the first light emitting diode chip 20 via the first electrode pad 39 a and the second electrode pad 39 b.
  • a first bump conductive layer and a second bump conductive layer may be further disposed above the first bump 41 .
  • the first bump conductive layer and the second bump conductive layer may be sequentially stacked above the first bump 41 .
  • the first bump conductive layer and the second bump conductive layer may assist the electrical connection and the mechanical connection between the first upper electrode 121 and the first electrode pad 39 a .
  • the first bump conductive layer may cover a side surface of the first bump 41 , thereby rendering the electrical connection and the mechanical connection more stable.
  • the first bump conductive layer may include nickel (Ni), and the second bump conductive layer may include gold (Au).
  • the light source unit 200 may include the first light emitting diode chip 20 , the second light source diode chip 20 ′, the wavelength converter 210 , and the light transmission portion 220 .
  • the wavelength converter 210 may be disposed on the first light emitting diode chip 20 and the second light source diode chip 20 ′ and may convert the wavelength of the light emitted from the first light emitting diode chip 20 and the second light source diode chip 20 ′ to a specific wavelength band.
  • the fluorescent material included in the wavelength converter 210 may be, but not limited to, a fluorine-based fluorescent material.
  • a wavelength conversion efficiency may be superior, but the fluorescent material may be vulnerable to moisture. Since the light emitting diode according to an exemplary embodiment of the present disclosure has a structure that prevents the moisture from entering the wavelength converter 210 , there is no risk of deterioration of the fluorescent material by moisture while using a highly efficient fluorescent material. The structure of the wavelength converter 210 that performs the above-described function will be described in detail hereinbelow.
  • the first light emitting diode chip 20 and the second light emitting diode chip 20 ′ emit the lights having the same wavelength
  • the lights emitted from the light transmission portion 220 after passing through the wavelength converter 210 may have different wavelengths from each other.
  • the first light emitting diode chip 20 and the second light emitting diode chip 20 ′ emit a white light
  • light exiting from an area provided with the first light emitting diode chip 20 may be light having a blue wavelength band
  • light exiting from an area provided with the second light emitting diode chip 20 ′ may be light having a red wavelength band.
  • the light transmission portion 220 transmits lights emitted from the first light emitting diode chip 20 and the second light emitting diode chip 20 ′ to the outside. Therefore, the light transmission portion 220 may be optically transparent.
  • the light transmission portion 220 may perform a protective function to prevent the first light emitting diode chip 20 and the second light emitting diode chip 20 ′ from being damaged by external impact or moisture.
  • the light transmission portion 220 may include a partition wall disposed between the first light emitting diode chip 20 and the second light emitting diode chip 20 ′.
  • the partition wall may prevent a color mixture of light emitted from the first light emitting diode chip 20 and the second light emitting diode chip 20 ′.
  • the wavelength converter 210 has a wavelength converter thickness T 1 in a cross-section, and the light transmission portion 220 has a light transmission portion thickness T 2 .
  • the wavelength converter thickness T 1 may be smaller than the light transmission portion thickness T 2 .
  • the wavelength converter 210 may be configured to have a relatively high density of the fluorescent material, and thus the wavelength conversion may sufficiently occur even when the wavelength converter 210 having a relatively small thickness is used. Therefore, the wavelength conversion may be sufficiently performed even though the wavelength converter thickness T 1 is smaller than the light transmission portion thickness T 2 . Since the wavelength converter thickness T 1 is smaller than the light transmission portion thickness T 2 , the light emitting diode may be slim.
  • the light transmission portion width H 3 is greater than the wavelength converter width H 2 in the light source unit 200 , moisture may be prevented from entering the wavelength converter 210 along an edge of the light transmission portion 220 .
  • the light transmission portion thickness T 2 is relatively large, moisture may be prevented from entering the wavelength converter 210 after passing through the light transmission portion 220 . Accordingly, although the density of the fluorescent material in the wavelength converter 210 is high, there is no risk of deformation and deterioration of the fluorescent material by moisture.
  • the wavelength converter width H 2 is greater than the light emitting diode chip width H 1 in the light source unit 200 , the light emitted from the first light emitting diode chip 20 and/or the second light emitting diode chip 20 ′ may be incident into the wavelength converter 210 without loss. Therefore, the light efficiency of the light emitting diode is superior because no light is lost.
  • the light transmission portion width H 3 is greater than the wavelength converter width H 2 in the light source unit 200 , a high efficiency wavelength converter 210 having the high fluorescent material density may be used, and thus the wavelength converter thickness T 1 may become relatively thin. Accordingly, the light emitting diode according to the exemplary embodiment may be slim with excellent light efficiency.
  • first conductive layer 120 and the second conductive layer 130 provided on the upper and lower surfaces of the body portion 110 will be more described in detail.
  • FIGS. 3A to 3E are plan views showing a first surface and a second surface of a lead frame unit according to exemplary embodiments.
  • the first conductive layer 120 is disposed on the first surface (or the upper surface) of the body portion 110 .
  • the first conductive layer 120 may include a plurality of patterns spaced apart from each other.
  • the first conductive layer 120 may include the first upper electrode 121 , the second upper electrode 122 , the third upper electrode 123 , and the fourth upper electrode 124 .
  • first conductive layer 120 the structure and functions of the first conductive layer 120 according to an exemplary embodiment will be described with reference to the first upper electrode 121 . It is noted that, however, the structures and functions of the first upper electrode 121 may be applied to the second upper electrode 122 , the third upper electrode 123 , and the fourth upper electrode 124 .
  • the first upper electrode 121 includes a circular portion 121 _ 1 and an elongated portion 121 _ 2 .
  • the circular portion 121 _ 1 has a substantially circular shape and is provided integrally with the elongated portion 121 _ 2 . As shown in FIG. 3A , the circular portion 121 _ 1 has a diameter Wp greater than a width We of the elongated portion 121 _ 2 . Since the diameter Wp of the circular portion 121 _ 1 is greater than the width We of the elongated portion 121 _ 2 , the through hole may be easily formed in the circular portion 121 _ 1 .
  • the circular portion 121 _ 1 and the connection portion 140 may be disposed to overlap with each other when viewed in a plan view. Accordingly, a position of the circular portion 121 _ 1 may be determined depending on a position of the connection portion 140 .
  • the circular portions of the first and second upper electrodes 121 and 122 are disposed to be spaced apart from each other with the elongated portions of the first and second upper electrodes 121 and 122 interposed therebetween, and the circular portions of the second and third upper electrodes 122 and 123 are disposed to be closer to each other without the elongated portions of the second and third upper electrodes 122 and 123 interposed therebetween.
  • the circular portions is disposed as shown in FIG. 3A because the second and third upper electrodes 122 and 123 share one second lower electrode 132 .
  • the second connection portion 142 and the third connection portion 143 are required to overlap with the second lower electrode 132 when viewed in a plan view to connect the second and third upper electrodes 122 and 123 to the second lower electrode 132 .
  • the second connection portion 142 and the third connection portion 143 are positioned close to each other, and the circular portions corresponding to the second connection portion 142 and the third connection portion 143 are also positioned close to each other.
  • the inventive concepts are not limited thereto, and the positions of the circular portions may be changed depending on the arrangement of the anode and cathode.
  • the elongated portion 121 _ 2 is disposed at one side of the circular portion 121 _ 1 and formed integrally with the circular portion 121 _ 1 .
  • the elongated portion 121 _ 2 connects the light emitting diode chip disposed on the first conductive layer 120 to the first conductive layer 120 .
  • the pad portion disposed under the light emitting diode chip may be placed on the elongated portion 121 _ 2 of the first conductive layer 120 . Accordingly, the driving signal and the power may be applied to the light emitting diode chip via the elongated portion 121 _ 2 .
  • the elongated portion 121 _ 2 has the width We smaller than that of the circular portion 121 _ 1 but has a length longer than that of the circular portion 121 _ 1 .
  • the elongated portion 121 _ 2 may have a shape elongated substantially parallel to a longitudinal direction of the upper surface of the body portion 110 . Since the elongated portion 121 _ 2 has a shape elongated substantially parallel to the longitudinal direction, the pad portion of the light emitting diode chip may be easily placed on the elongated portion 121 _ 2 .
  • the light emitting diode chip may be easily mounted on the elongated portion 121 _ 2 .
  • the circular portion 121 _ 1 and the elongated portion 121 _ 2 may be disposed in the body portion 110 when viewed in a plan view. Accordingly, when the light emitting diode is viewed from the side surface, the elongated portion 121 _ 2 and the circular portion 121 _ 1 may not be exposed to the outside.
  • the diameter Wp of the circular portion 121 _ 1 may be smaller than the thickness Wt of the body portion 110 so as not to expose the elongated portion 121 _ 2 and the circular portion 121 _ 1 at the side surface of the body portion 110 .
  • the diameter Wp of the circular portion 121 _ 1 may be within a range from about 30% to about 60% of the thickness Wt of the body portion 110 .
  • the through hole may be more easily formed, and the circular portion 121 _ 1 may not be exposed at the side surface of the body portion 110 .
  • the first upper electrode 121 since the first upper electrode 121 is not exposed at the side surface of the body portion 110 , the first upper electrode 121 may be prevented from being oxidized by external oxygen and moisture. Further, the moisture may be prevented from entering the lead frame unit 100 along the first upper electrode 121 , and the exposed first upper electrode 121 and other components may be prevented from being short-circuited with each other.
  • a thickness We of the elongated portion 121 _ 2 may be within a range from about 30% to about 60% of the thickness Wt of the body portion 110 . Since the thickness We of the elongated portion 121 _ 2 is relatively smaller than the thickness Wt of the body portion 110 , the elongated portion 121 _ 2 may be stick out from the body portion 110 . Thus, the elongated portion 121 _ 2 may be prevented from being short-circuited with other components.
  • the width We of the elongated portion 121 _ 2 may be smaller than the diameter Wp of the circular portion 121 _ 1 . Accordingly, a via hole may be stably formed in the circular portion 121 _ 1 having a relatively large diameter. However, in some exemplary embodiments, the width of the elongated portion 121 _ 2 may be equal to the diameter of the circular portion 121 _ 1 .
  • Various shapes of the circular portion 121 _ 1 and the elongated portion 121 _ 2 will be described in more detail later.
  • the first light emitting diode chip 20 and the second light emitting diode chip 20 ′ are mounted on the upper surface of the body portion 110 .
  • the first light emitting diode chip 20 and the second light emitting diode chip 20 ′ are disposed such that at least a portion of the first light emitting diode chip 20 and the second light emitting diode chip 20 ′ overlaps with the first, second, third, and fourth upper electrodes 121 , 122 , 123 , and 124 when viewed in a plan view.
  • the first light emitting diode chip 20 and the second light emitting diode chip 20 ′ cover some portions of the first, second, third, and fourth upper electrodes 121 , 122 , 123 , and 124 when viewed in a plan view, while exposing some portions of the first, second, third, and fourth upper electrodes 121 , 122 , 123 , and 124 when viewed in a plan view.
  • the elongated portions of the first, second, third, and fourth upper electrodes 121 , 122 , 123 , and 124 may be covered by the first light emitting diode chip 20 and the second light emitting diode chip 20 ′, however, some portions of the circular portions of the first, second, third, and fourth upper electrodes 121 , 122 , 123 , and 124 may be exposed.
  • the first light emitting diode chip 20 and the second light emitting diode chip 20 ′ having relatively small sizes may be easily mounted on the first, second, third, and fourth upper electrodes 121 , 122 , 123 , and 124 , which occupy a relatively larger area.
  • the first light emitting diode chip 20 and the second light emitting diode chip 20 ′ are disposed to completely cover the first, second, third, and fourth upper electrodes 121 , 122 , 123 , and 124 when viewed in a plan view.
  • the areas at which the first light emitting diode chip 20 and the second light emitting diode chip 20 ′ overlap the first, second, third, and fourth upper electrodes 121 , 122 , 123 , and 124 may be increased.
  • the electrical connection between the components may be maintained more stably, and the heat dissipation efficiency may be improved.
  • FIGS. 3D and 3E are plan views of the second surface of the lead frame unit according to exemplary embodiments.
  • the second conductive layer 130 is disposed on the second surface (or the lower surface) of the body portion 110 .
  • the second conductive layer 130 includes a plurality of patterns spaced apart from each other.
  • the second conductive layer 130 includes the first, second, and third lower electrodes 131 , 132 , and 133 .
  • the second conductive layer 130 according to an exemplary embodiment will be described with reference to the first lower electrode 131 .
  • the first lower electrode 131 includes a lower circular portion 131 _ 1 and a lower elongated portion 131 _ 2 .
  • the lower circular portion 131 _ 1 and the lower elongated portion 131 _ 2 of FIG. 3D are substantially similar to the circular portion 121 _ 1 and the elongated portion 121 _ 2 of the first conductive layer 120 of FIG. 3A , respectively. As such, the same or substantially similar components will be assigned with the same or similar reference numerals, and repeated or redundant descriptions thereof will be omitted.
  • the lower circular portion 131 _ 1 has a substantially circular shape and is provided integrally with the lower elongated portion 131 _ 2 .
  • the lower circular portion 131 _ 1 has a diameter greater than a width of the lower elongated portion 131 _ 2 .
  • the lower circular portion 131 _ 1 may be disposed to overlap with the circular portion 121 _ 1 of the first conductive layer 120 when viewed in a plan view. Accordingly, the first connection portion 141 may be provided in a shape extending from the circular portion 121 _ 1 to the lower circular portion 131 _ 1 .
  • the lower elongated portion 131 _ 2 may be disposed at one side of the lower circular portion 131 _ 1 and may surround the first solder hole 151 .
  • the lower elongated portion 131 _ 2 may be disposed along an edge of the first solder hole 151 . Therefore, when the solder paste is provided in the first solder hole 151 , the solder paste may be electrically connected to the lower elongated portion 131 _ 2 disposed at the edge of the first solder hole 151 .
  • the second lower electrode 132 may include two lower circular portions.
  • the two lower circular portions are respectively connected to the second connection portion 142 and the third connection portion 143 . Further, the two lower circular portions of the second lower electrode 132 may be connected to the circular portion of the second upper electrode 122 and the circular portion of the third upper electrode 123 , respectively.
  • the second lower electrode 132 may be divided into two portions with respect to the second solder hole 152 .
  • the second connection portion 142 and the third connection portion 143 may be electrically independent from each other. Accordingly, in some implementations, an electricity may be applied only to the second connection portion 142 and the first connection portion 141 , and the electricity may not be applied to the third connection portion 143 and the fourth connection portion 144 .
  • the plug 141 _ 2 of the first connection portion 141 and the first solder hole 151 may be separated from each other by a predetermined distance.
  • the plug 141 _ 2 of the first connection portion 141 and the first solder hole 151 may be separated from each other by about 40 ⁇ m to about 50 ⁇ m.
  • the through hole may penetrate the first solder hole 151 due to a process error during the process of forming the through hole for the plug 141 _ 2 .
  • the separation distance between the plug 141 _ 2 of the first connection portion 141 and the first solder hole 151 exceeds about 50 ⁇ m, the size of the lead frame unit 100 may be excessively large.
  • the second connection portion 142 and the third connection portion 143 may be disposed to be spaced apart from the second solder hole 152 by about 50 ⁇ m or more when viewed from the lower surface (or the second surface) of the body portion 110 .
  • the second connection portion 142 and the third connection portion 143 are spaced apart from the second solder hole 152 by the above-described minimum distance, unintended electrical connections may be prevented from occurring.
  • the first, second, and third solder holes 151 , 152 , and 153 may have a semi-circular or semi-elliptical shape when viewed from the lower surface (or the second surface) of the body portion 110 .
  • the first, second, and third solder holes 151 , 152 , and 153 may have a shape recessed inward from the third surface of the body portion 110 when viewed from the second surface.
  • the semi-circular or semi-elliptical shape of the first, second, and third solder holes 151 , 152 , and 153 when viewed from the second surface may have a chord parallel to the third surface and a round arc inside the body portion 110 .
  • the third solder hole 153 may have a solder hole height Ws, which is a depth of the third solder hole 153 , in a range from about 10% to about 50% of the thickness Wt of the body portion 110 .
  • a crack may occur in the body portion 110 when external impacts are applied to the light emitting diode or the external frame, and the solder paste penetrates along the crack, thereby causing the short circuit.
  • solder hole height Ws exceeds about 50% of the thickness Wt of the body portion 110 , an excessive amount of the solder paste may be used considering a contact area of the solder paste, and thus, the light emitting diode may not be fixed to and may be separated from the external frame.
  • the solder hole height Ws is within the range from about 10% to about 50% of the thickness Wt of the body portion 110 , the short circuit caused by the crack may be prevented, and the light emitting diode may be stably fixed to the external frame.
  • a second conductive layer 130 ′ including first, second, and third lower electrodes 131 ′, 132 ′, and 133 ′, and first, second, and third solder holes 151 ′, 152 ′, and 153 ′ according to another exemplary embodiment have different shapes from those of the second conductive layer 130 and the first, second, and third solder holes 151 , 152 , and 153 shown in FIG. 3D .
  • each of the first, second, and third solder holes 151 ′, 152 ′, and 153 ′ has a solder hole diameter Ds and a solder hole height Ws, and the solder hole diameter Ds may be at least two times or more than the solder hole height Ws. Accordingly, each of the first, second, and third solder holes 151 ′, 152 ′, and 153 ′ may have a semi-elliptical shape.
  • the area of the first, second, and third lower electrodes 131 ′, 132 ′, and 133 ′ may be widened at the lower surface of the body portion. In this manner, the heat dissipation efficiency via the first, second, and third lower electrodes 131 ′, 132 ′, and 133 ′ may be improved.
  • the second lower electrode 132 ′ may be provided as a single unitary form without being divided into two portions with respect to the second solder hole 152 .
  • the electricity applied to the second lower electrode 132 ′ may be substantially simultaneously applied to the second connection portion 142 and the third connection portion 143 .
  • FIGS. 4A to 4G are plan views showing the second surface of the lead frame unit according to exemplary embodiments.
  • the first, second, and third solder holes 151 , 152 , and 153 and the solder insulating layer 160 are disposed on the second surface (or the lower surface) of the body portion 110 .
  • the solder insulating layer 160 may be disposed between the first, second, and third solder holes 151 , 152 , and 153 to prevent the short circuit from occurring between the first, second, and third solder holes 151 , 152 , and 153 . Accordingly, the solder insulating layer 160 may be disposed to surround peripheries of the first, second, and third solder holes 151 , 152 , and 153 . For example, the solder insulating layer 160 may be disposed outside the first solder hole 151 and the third solder hole 153 , and between the first, second, and third solder holes 151 , 152 , and 153 .
  • the solder insulating layer 160 may be disposed to cover at least a portion of the second conductive layer formed between the first, second, and third solder holes 151 , 152 , and 153 on the second surface of the body portion 110 .
  • the second conductive layer has the first, second, and third lower electrodes 131 , 132 , and 133 on the second surface of the body portion 110 , and the first, second, and third lower electrodes 131 , 132 , and 133 may be disposed to surround the first, second, and third solder holes 151 , 152 , and 153 , respectively.
  • the solder insulating layer 160 may be disposed between the first, second, and third lower electrodes 131 , 132 , and 133 that surround the first, second, and third solder holes 151 , 152 , and 153 , respectively.
  • the solder insulating layer 160 may be disposed between the first lower electrode 131 surrounding the first solder hole 151 and the second lower electrode 132 surrounding the second solder hole 152 , and between the second lower electrode 132 and the third lower electrode 133 surrounding the third solder hole 153 .
  • the short circuit may not occur between the first, second, and third lower electrodes 131 , 132 , and 133 even when different electrical signals are applied to the first, second, and third lower electrodes 131 , 132 , and 133 .
  • the solder insulating layer 160 may include an insulating material.
  • the solder insulating layer 160 may include various insulating materials, such as polyamide, polyimide, polypropylene, ethylene vinyl acetate, polystyrene, polyvinyl chloride, epoxy resin, urethane resin, and phenol resin.
  • the first, second, and third solder holes 151 , 152 , and 153 may have the solder hole height Ws on the second surface.
  • each of the first, second, and third lower electrodes 131 , 132 , and 133 may have a lower electrode width Wb from one end of a corresponding of a solder hole among the first, second, and third solder holes 151 , 152 , and 153 to the other end facing the one end of the corresponding solder hole.
  • the body portion 110 may have a body portion margin We from one end of each of the first, second, and third solder holes 151 , 152 , and 153 to a facing end of the body portion 110 .
  • a predetermined relationship may be established between the above-described solder hole height Ws, the lower electrode width Wb, and the body portion margin Wc, and thus the structural stability of the light emitting diode may be secured.
  • the solder hole height Ws may be greater than the lower electrode width Wb
  • the body portion margin Wc may be greater than the solder hole height Ws.
  • the body portion 110 when the body portion 110 is coupled to the external frame by the solder paste, the body portion 110 may be prevented from being separated since the solder hole height Ws is set greater than the lower electrode width Wb.
  • the solder paste provided in the first, second, and third solder holes 151 , 152 , and 153 may be spread too wide on the second surface of the body portion 110 .
  • the body portion 110 may be pulled toward the external frame while the spreading solder paste hardens, and thus, a portion of the body portion 110 and the light source unit may be separated from the external frame.
  • the body portion margin Wc may be greater than the solder hole height Ws.
  • the rigidity of the body portion 110 may be secured.
  • the solder hole height Ws is equal to or greater than the body portion margin Wc, an empty space may be excessively increased in the body portion 110 , and the rigidity of the body portion 110 may be lowered.
  • the body portion 110 may be easily bent or damaged particularly due to an external force applied to a lateral direction (a direction perpendicular to the solder hole height Ws) of the body portion 110 .
  • a portion of the body portion 110 may be exposed on the lower surface of the body portion 110 .
  • the solder insulating layer 160 and/or the first, second, and third lower electrodes 131 , 132 , and 133 may not be provided on a portion of the lower surface of the body portion 110 .
  • solder insulating layers 160 ′, 160 ′′, 160 ′′′, and 160 ′′′′ may have various shapes.
  • the shape of the solder insulating layers 160 ′, 160 ′′, 160 ′, and 160 ′′′′ disposed adjacent to the first solder hole 151 may be different from the shape of the solder insulating layers 160 ′, 160 ′′, 160 ′, and 160 ′′′′ disposed adjacent to the second solder hole 152 or the third solder hole 153 .
  • the types of electrode may be easily identified, and thus, the electrode may be prevented from being connected incorrectly.
  • the first solder hole 151 is connected to the cathode based on the shape of the solder insulating layers 160 ′, 160 ′′, 160 ′, and 160 ′′′′, and thus, the first solder hole 151 may be prevented from being incorrectly connected to the anode of the external frame.
  • the inventive concepts are not limited to the shape change of only the solder insulating layers 160 ′, 160 ′′, 160 ′′′, and 160 ′′′′ disposed adjacent to the first solder hole 151 .
  • the solder insulating layers 160 ′, 160 ′′, 160 ′′′, and 160 ′′′′ disposed adjacent to the second solder hole 152 connected to the anode may have a different shape from that of the solder insulating layers 160 ′, 160 ′′, 160 ′′′, and 160 ′′′′ disposed adjacent to the first solder hole 151 or the third solder hole 153 .
  • the solder insulating layers 160 ′, 160 ′′, 160 ′, and 160 ′′′′ may have be formed to have various shapes as long as the electrical connection between the first, second, and third solder holes 151 , 152 , and 153 and the external frame is not impeded.
  • the solder insulating layers 160 ′, 160 ′′, 160 ′′′, and 160 ′′′′ may be disposed to completely cover the first, second, and third solder holes 151 , 152 , and 153 .
  • solder insulating layers 160 ′, 160 ′′, 160 ′′′, and 160 ′′′′ may mechanically assist the components provided in the first, second, and third solder holes 151 , 152 , and 153 to not protrude out from the first, second, and third solder holes 151 , 152 and 153 due to an external pressure.
  • first, second, and third lower electrodes 131 , 132 , and 133 may have a bent shape in areas facing the first, second, and third solder holes 151 , 152 and 153 , respectively.
  • the first, second, and third lower electrodes 131 , 132 , and 133 may have a shape protruding from an opposite surface to the surface provided with the first, second, and third solder holes 151 , 152 , and 153 in areas adjacent to the solder insulating layer 160 .
  • the body portion 110 which is exposed without being covered by the first, second, and third lower electrodes 131 , 132 , and 133 and the solder insulating layer 160 , may have substantially a hexagonal shape as shown in figures.
  • the electrical connection between the first to fourth connection portions e.g., the connection conductive layer of the first to fourth connection portions provided via the through hole, and the first, second, and third lower electrodes 131 , 132 , and 133 may be secured.
  • the body portion 110 and the light source unit may be prevented from being separated from the external frame when the body portion 110 is connected to the external frame by the solder paste.
  • solder paste provided in the first, second, and third solder holes 151 , 152 , and 153 may not pull the body portion 110 toward the external frame, when the solder paste provided in the first, second, and third solder holes 151 , 152 , and 153 penetrates into the first, second, and third lower electrodes 131 , 132 , and 133 and hardens.
  • the first, second, and third lower electrodes 131 , 132 , and 133 have a different shape from those shown in FIG. 4F .
  • the first, second, and third lower electrodes 131 , 132 , and 133 may have a bent shape, e.g., a gentle curved shape, in areas facing the first, second, and third solder holes 151 , 152 and 153 , respectively. Therefore, the exposed portion of the body portion 110 may have a semi-circular shape.
  • an additional solder insulating layer 161 may be disposed on the exposed portion of the body portion 110 .
  • the additional solder insulating layer 161 covers the exposed portion of the body portion 110 and prevents the solder paste provided in the first, second, and third solder holes 151 , 152 and 153 from penetrating into the exposed portion of the body portion 110 beyond the first, second, and third lower electrodes 131 , 132 , and 133 .
  • the body portion 110 and the light source unit may be prevented from being separated from the external frame when the body portion 110 is connected to the external frame, even though the solder paste is provided in an excessively large area as described above.
  • FIG. 5A is a plan view of the third surface of the lead frame unit according to an exemplary embodiment
  • FIG. 5B is a cross-sectional view of a light emitting diode according to an exemplary embodiment.
  • the body portion 110 may include the first, second, and third solder holes 151 , 152 and 153 .
  • the first, second, and third solder holes 151 , 152 and 153 may have a substantially pentagonal shape when viewed from the third surface (or the side surface) of the body portion 110 .
  • the first, second, and third solder holes 151 , 152 and 153 may have the substantially pentagonal shape extending from the second surface to the first surface when viewed from the third surface.
  • the pentagonal shape of the first, second, and third solder holes 151 , 152 and 153 may have one side parallel to the second surface, and a vertex opposite to the one side of the pentagonal shape may face the first surface.
  • first, second, and third solder holes 151 , 152 and 153 have the substantially pentagonal shape, a superior heat dissipation characteristic and mechanical stability may be secured when the light emitting diode is connected to the external frame by the solder paste.
  • the first solder hole 151 having the substantially pentagonal shape may have at least one internal angle of about 120 degrees to about 170 degrees when viewed from the side surface.
  • the internal angle of the pentagonal shape having the angle of the above-mentioned range may be referred to as a vertex angle ⁇ .
  • the vertex angle ⁇ of the first solder hole 151 may be located at a position closest to the upper surface of the body portion 110 .
  • the solder paste and the light emitting diode may be stably coupled to each other.
  • the vertex angle is each less than about 120 degrees
  • an area corresponding to the vertex angle ⁇ may be filled with less solder paste.
  • bubbles may be formed in the area of the vertex angle ⁇ , and thermal characteristics of the light emitting diode and the external frame may be degraded.
  • the first solder hole 151 may not be completely filled with the solder paste.
  • the light emitting diode may be tilted, shifted, or rotated with respect to the external frame without being fixed to the external frame.
  • the first solder hole 151 according the illustrated exemplary embodiment may have the substantially pentagonal shape having the vertex angle from about 120 degrees to about 170 degrees, and thus not only the thermal characteristics may be improved but also the light emitting diode may be stably fixed to the external frame.
  • the inventive concepts are not limited thereto, and in some exemplary embodiments, the first solder hole 151 may have a shape different from the shape shown in FIG. 5A .
  • the area corresponding to the vertex angle ⁇ of the first solder hole 151 may be rounded or chamfered.
  • the vertex angle ⁇ may be an angle formed by extension lines of two straight lines that define the area corresponding to the vertex angle ⁇ .
  • a height hs of the first solder hole 151 may be within a range from about 50% to about 80% of a height ht of the body portion 110 . As described above, when the height hs of the first solder hole 151 is within the range from about 50% to about 80% of the height ht of the body portion 110 , the light emitting diode may be stably fixed to the external frame without degrading the structural stability of the body portion 110 .
  • a second insulating layer may be disposed around the first, second, and third solder holes 151 , 152 and 153 along edges of the first, second, and third solder holes 151 , 152 and 153 .
  • the second insulating layer may be formed between the first, second, and third lower electrodes 131 , 132 , and 133 , which are spaced apart from each other and respectively disposed in the first, second, and third solder holes 151 , 152 and 153 .
  • the first, second, and third lower electrodes 131 , 132 , and 133 may be disposed to cover portions of the body portion 110 , which define the first, second, and third solder holes 151 , 152 and 153 , and portions of the lower surface of the body portion 110 , which are adjacent to the first, second, and third solder holes 151 , 152 and 153 . Accordingly, when the solder paste is provided in the first, second, and third solder holes 151 , 152 and 153 , the light emitting diode and the external frame may be electrically and stably connected to each other by the solder paste.
  • the lead frame unit of FIG. 5A has been described with reference to the first solder hole 151 , it is noted that, however, the second solder hole 152 and/or the third solder hole 153 may have substantially the same structure as that of the first solder hole 151 .
  • the first, second, and third lower electrodes 131 , 132 , and 133 may have a lower electrode thickness T when viewed from the third surface.
  • the lower electrode thickness T may be within a range from about 10 ⁇ m to about 30 ⁇ m.
  • an adhesive force between the first, second, and third lower electrodes 131 , 132 , and 133 and the body portion 110 may be insufficient, and thus, the first, second, and third lower electrodes 131 , 132 , and 133 may be separated from the body portion 110 .
  • the lower electrode thickness T is less than about 10 ⁇ m, defects, such as the first, second, and third lower electrodes 131 , 132 , and 133 are not being formed in some portions of the first, second, and third lower electrodes 131 , 132 , and 133 may occur, even with small errors in the process, which may significantly reduce the electrical conductivity.
  • the first, second, and third solder holes may have the solder hole height Ws and a solder hole depth hx in the cross-section.
  • the solder hole depth hx may be greater than the solder hole height Ws. Since the solder hole depth hx of the first, second, and third solder holes are greater than the corresponding solder hole height Ws, the adhesive force between the lead frame unit 100 and an external frame 300 may be secured by the solder paste provided in the first, second, and third solder holes.
  • the lead frame unit 100 since the lead frame unit 100 is attached to the external frame 300 by the solder paste in the relatively large surface, the lead frame unit 100 and the light source unit 200 may be prevented from being separated due to the reduction of the adhesive force.
  • the lead frame unit 100 may have a first height Wd and a second height We in the cross-section.
  • the first height Wd may be a distance from a surface of the lead frame unit 100 that meets the external frame 300 to the first, second, and third lower electrodes surrounding the first, second, and third solder holes.
  • the second height We may be a height obtained by subtracting the first height Wd from the thickness of the body portion, e.g., a distance from the first, second, and third lower electrodes to a front surface of the lead frame unit 100 .
  • a relationship between the first height Wd and the second height We may be established, such that the first height Wd is smaller than the second height We. Accordingly, the size of the empty space of the lead frame unit 100 for providing the first, second, and third solder holes may be relatively small, and thus, the rigidity of the lead frame unit 100 may be secured.
  • FIG. 6 is a plan view of a light emitting diode according to an exemplary embodiment.
  • the light emitting diode may include the first light emitting diode chip 20 and the second light emitting diode chip 20 ′.
  • the first light emitting diode chip 20 and the second light emitting diode chip 20 ′ are disposed to be spaced apart from each other.
  • the first light emitting diode chip 20 and the second light emitting diode chip 20 ′ may be disposed to be spaced apart from each other by a first interval IV 1 .
  • the first interval IV 1 may be within a range from about 470 nm to about 500 nm.
  • the first interval IV 1 is less than about 470 nm, light emitted from the first light emitting diode chip 20 interferes with light emitted from the second light emitting diode chip 20 ′, and light may not be emitted in a desired form.
  • the first interval IV 1 exceeds about 500 nm, the size of the light emitting diode may become excessively large, and thus, a usability of the light emitting diode may be deteriorated.
  • the first light emitting diode chip 20 and the second light emitting diode chip 20 ′ may be disposed to be spaced apart from an edge of the light source unit 200 by a predetermined distance.
  • a distance between the edge of the light source unit 200 and the first light emitting diode chip 20 and the second light emitting diode chip 20 ′ may be referred to as a “light emitting diode chip margin”.
  • the light emitting diode chip margin may vary depending on positions of the first light emitting diode chip 20 and the second light emitting diode chip 20 ′.
  • the light emitting diode chip margin may be referred to as second, third, fourth, and fifth intervals IV 2 , IV 3 , IV 4 , and IV 5 depending on positions of the first light emitting diode chip 20 and the second light emitting diode chip 20 ′.
  • the first light emitting diode chip 20 may be disposed to be spaced apart from one end of the light source unit 200 by a second interval IV 2 .
  • the term “one end of the light source unit 200 ” may refer to a surface adjacent to the first light emitting diode chip 20 among short surfaces of the light emitting diode.
  • the light transmission portion When the light transmission portion is provided to cover the first light emitting diode chip 20 , the light transmission portion may be disposed to be spaced apart from the one end of the light source unit 200 by the second interval IV 2 when viewed from the upper surface of the light emitting diode.
  • the second interval IV 2 may be within a range from about 90 nm to about 110 nm.
  • the second interval IV 2 is less than about 90 nm, the external force provided from the outside of the light emitting diode or the light source unit 200 may be applied to the first light emitting diode chip 20 without being buffered, and the first light emitting diode chip 20 may be damaged.
  • the second interval IV 2 exceeds about 110 nm, the size of the light emitting diode may become excessively large, and thus, a usability of the light emitting diode may be deteriorated.
  • the second light emitting diode chip 20 ′ may be disposed to be spaced apart from the other end of the light source unit 200 by a third interval IV 3 .
  • the term “the other end of the light source unit 200 ” may refer to a surface adjacent to the second light emitting diode chip 20 ′ among the short surfaces of the light emitting diode.
  • the third interval IV 3 may be within a range from about 100 nm to about 120 nm.
  • the third interval IV 3 is less than about 100 nm, the external force provided from the outside of the light emitting diode or the light source unit 200 may be applied to the second light emitting diode chip 20 ′ without being buffered, and the second light emitting diode chip 20 ′ may be damaged.
  • the third interval IV 3 exceeds about 120 nm, the size of the light emitting diode may become excessively large, and thus, the usability of the light emitting diode may be deteriorated.
  • the third interval IV 3 may be greater than the second interval IV 2 . This is because the surface on which the second light emitting diode chip 20 ′ of the light emitting diode is located may be arranged close to the outside or other components when the light emitting diode is connected to the external frame and applied to other components. Accordingly, the second light emitting diode chip 20 ′ may be exposed to the external force relatively more than the first light emitting diode chip 20 . As such, the third interval IV 3 may be greater than the second interval IV 2 to prevent the second light emitting diode chip 20 ′ from being damaged due to the external force.
  • the first interval V 1 may be greater than the second interval IV 2 and the third interval IV 3 . Accordingly, when viewed from the top of the light source unit 200 , the first light emitting diode chip 20 and the second light emitting diode chip 20 ′ may be respectively inclined to different sides of the light source unit 200 . Since the first interval V 1 may be greater than the second interval IV 2 and the third interval IV 3 , it is possible to prevent unnecessary interference between the light emitted from the first light emitting diode chip 20 and the light emitted from the second light emitting diode chip 20 ′.
  • the first light emitting diode chip 20 and/or the second light emitting diode chip 20 ′ may be disposed to be spaced apart from a rear surface of the light emitting diode by a fourth interval IV 4 .
  • the fourth interval IV 4 may be about 40 nm.
  • unnecessary electrical connection may be prevented from occurring between the first light emitting diode chip 20 and/or the second light emitting diode chip 20 ′ and the electrodes on the external frame, and the size of the light emitting diode may be formed slim.
  • first light emitting diode chip 20 and/or the second light emitting diode chip 20 ′ may be disposed to be spaced apart from a front surface of the light emitting diode by a fifth interval IV 5 .
  • the fifth interval IV 5 may be within a range from about 45 nm to about 50 nm.
  • the fifth interval IV 5 is less than about 45 nm, the first light emitting diode chip 20 and/or the second light emitting diode chip 20 ′ may be easily damaged due to the external force applied to the front surface of the light emitting diode.
  • the fifth interval IV 5 exceeds about 50 nm, the light emitting diode may become excessively thick.
  • the fifth interval IV 5 may be greater than the fourth interval IV 4 .
  • the fourth interval IV 4 may be relatively small since the fourth interval IV 4 is provided to prevent unnecessary electrical connection from occurring between the first and/or second light emitting diode chips 20 and/or 20 ′ and the external frame by separating the first and/or second light emitting diode chips 20 and/or 20 ′ from the external frame.
  • the fifth interval IV 5 may be relatively large because the fifth interval IV 5 may serve to buffer the external force. As the fifth interval IV 5 is greater than the fourth interval IV 4 , the unnecessary electrical connection may be prevented from occurring, the external force may be buffered, and the light emitting diode may be formed slim.
  • the light emitting diode since the first light emitting diode chip 20 and/or the second light emitting diode chip 20 ′ are designed to satisfy a specific distance relationship on the light source unit 200 , the light emitting diode may be formed slim, and the light emitting diode may have improved structural stability.
  • FIG. 7 is a perspective view of a light emitting diode according to an exemplary embodiment
  • FIG. 8A is a perspective view of the light emitting diode of FIG. 7 according to an exemplary embodiment
  • FIG. 8B is a cross-sectional view taken along line II-II′ of FIG. 8A .
  • the light emitting diode of FIGS. 7, 8A, and 8B is substantially similar to the light emitting diode of FIGS. 1, 2A, and 2B . Accordingly, the same or similar components will be assigned with the same or similar reference numerals, and repeated or redundant descriptions thereof will be omitted to avoid redundancy.
  • a lead frame unit 100 ′ includes a first solder hole 151 ′ and a second solder hole 152 ′, and a light source unit 200 ′ includes one light emitting diode chip 20 .
  • the light source unit 200 ′ As compared to the light source unit 200 of FIGS. 1 to 5B that includes two light emitting diode chips, the light source unit 200 ′ according to the illustrated exemplary embodiment shown in FIGS. 7 to 8B includes one light emitting diode chip. As such, the shapes of a first conductive layer 120 ′ and a second conductive layer may be changed.
  • the first conductive layer 120 ′ may include one first upper electrode 121 ′ and one second upper electrode 122 ′.
  • Pad portions 39 a and 39 b of the light emitting diode chip 20 may be respectively mounted on the first upper electrode 121 ′ and the second upper electrode 122 ′.
  • the second conductive layer may include one first lower electrode 131 ′ and one second lower electrode 132 ′.
  • the first lower electrode 131 ′ and the second lower electrode 132 ′ may be disposed to overlap with the first upper electrode 121 ′ and the second upper electrode 122 ′, respectively, when viewed in a plan view.
  • the first upper electrode 121 ′ and the first lower electrode 131 ′ may have substantially the same function as each other.
  • the first upper electrode 121 ′ and the first lower electrode 131 ′ may serve as a cathode.
  • the second upper electrode 122 ′ and the second lower electrode 132 ′ may serve as an anode.
  • the first upper electrode 121 ′ and the first lower electrode 131 ′ may serve as the anode
  • the second upper electrode 122 ′ and the second lower electrode 132 ′ may serve as the cathode.
  • the first upper electrode 121 ′ and the second upper electrode 122 ′ may include a cover plate 141 _ 3 described below. However, according to another exemplary embodiments, the first upper electrode 121 ′ and the second upper electrode 122 ′ may include the cover plate 141 _ 3 and a bump disposed on the cover plate 141 _ 3 . In some exemplary embodiments, however, the bump may be omitted to thin the lead frame unit 100 ′.
  • a first connection portion 141 ′ and a second connection portion 142 ′ may be provided to connect the first conductive layer 120 ′ and the second conductive layer.
  • the first connection portion 141 ′ may connect the first upper electrode 121 ′ and the first lower electrode 131 ′
  • the second connection portion 142 ′ may connect the second upper electrode 122 ′ and the second lower electrode 132 ′.
  • the first connection portion 141 ′ and the second connection portion 142 ′ may be disposed to penetrate the body portion 110 ′.
  • a first through hole 151 ′ and a second through hole 152 ′ are defined in a lower surface of the body portion 110 ′. According to the illustrated exemplary embodiment, only two through holes 151 ′ and 152 ′ may be defined in the body portion 110 ′. However, the inventive concepts are not limited thereto, and in some exemplary embodiments, more through holes may be provided in the body portion 110 ′ in addition to the first through hole 151 ′ and the second through hole 152 ′ for heat dissipation, for example.
  • the first lower electrode 131 ′ may be disposed in the first through hole 151 ′, and the second lower electrode 132 ′ maybe disposed in the second through hole 152 ′.
  • the first lower electrode 131 ′ and the second lower electrode 132 ′ may be electrically connected to an external frame by a solder paste provided in the first through hole 151 ′ and the second through is hole 152 ′.
  • a driving signal and power provided from the external frame may be applied to the light emitting diode chip 20 via the first lower electrode 131 ′ and the second lower electrode 132 ′ disposed in the first through hole 151 ′ and the second through hole 152 ′.
  • a solder insulating layer may be further disposed on the lower surface of the body portion 110 ′.
  • the solder insulating layer may be omitted to keep the lead frame unit slim.
  • the light emitting diode according to the illustrated exemplary embodiment may be formed so that one light emitting diode chip is mounted.
  • FIGS. 9A and 9B are plan views of a first surface and a second surface of the lead frame unit of FIG. 8 , respectively according to an exemplary embodiment.
  • the first upper electrode 121 ′ and the second upper electrode 122 ′ are disposed on a first surface (or an upper surface) of the body portion 110 ′.
  • the first upper electrode 121 ′ includes a circular portion 121 _ 1 ′ and an elongated portion 121 _ 2 ′.
  • the first connection portion 141 ′ may be disposed in the circular portion 121 _ 1 ′. Since the first connection portion 141 ′ is disposed in the circular portion 121 _ 1 ′ having a relatively large diameter, a through hole required to provide the first connection portion 141 ′ may be easily formed.
  • the pad portion of the light emitting diode chip may be mounted on the elongated portion 121 _ 2 ′. Since the light emitting diode chip is mounted on the elongated portion 121 _ 2 ′ having a relatively long length, the light emitting diode chip may be easily mounted.
  • the first lower electrode 131 ′ and the second lower electrode 132 ′ are disposed on a second surface (or a lower surface) of the body portion 110 ′.
  • the first lower electrode 131 ′ and the second lower electrode 132 ′ may be disposed to surround an edge of the first through hole 151 ′ and the second through hole 152 ′, respectively.
  • the first lower electrode 131 ′ may include a lower circular portion 131 _ 1 ′ and a lower elongated portion 131 _ 2 ′.
  • the first connection portion 141 may be disposed in the lower circular portion 131 _ 1 ′.
  • the lower circular portion 131 _ 1 ′ may be disposed to overlap with the circular portion 121 _ 1 ′ when viewed in a plan view.
  • one first upper electrode 121 ′ and one second upper electrode 122 ′ may be provided on the upper surface of the body portion 110 ′, and one first lower electrode 131 ′ and one second lower electrode 132 ′ may be provided on the lower surface of the body portion 110 ′.
  • FIG. 10A is a plan view of a light source unit according to an exemplary embodiment
  • FIG. 10B is a cross-sectional view taken along line A-A′ of FIG. 10A
  • FIG. 10C is a cross-sectional view taken along line B-B′ of FIG. 10A
  • FIG. 10D is a cross-sectional view taken along line C-C′ of FIG. 10A
  • FIG. 10E is a magnified view of M 1 in FIG. 10D .
  • FIGS. 10A to 10E the light emitting diode chip 20 of the light source unit is shown in more detail.
  • FIG. 10A shows the plan view of the light emitting diode chip 20
  • FIGS. 10B, 10C, and 10D show cross-sectional views respectively taken along lines A-A′, B-B′, and C-C′ of FIG. 10A .
  • the light emitting diode chip 20 includes a substrate 21 , a first light emitting cell C 1 , a second light emitting cell C 2 , a reflective structure 31 , first, second, and third contact layers 35 a , 35 b , and 35 c , a first electrode pad 39 a , and a second electrode pad 39 b .
  • the light emitting diode chip 20 may include a preliminary insulating layer 29 , a lower insulating layer 33 , and a resin layer 37 .
  • each of the first and second light emitting cells C 1 and C 2 includes an n-type semiconductor layer 23 , an active layer 25 , and a p-type semiconductor layer 27 .
  • the light emitting diode chip has a series multi junction structure, however, the inventive concepts are not limited thereto, and in some exemplary embodiments, and the light emitting diode chip may have another structure.
  • the substrate 21 may be a growth substrate for growing a group III-V nitride-based semiconductor layer, for example, a sapphire substrate, in particular, a patterned sapphire substrate.
  • the substrate 21 may be an insulating substrate, without being limited thereto.
  • an insulating material layer may be disposed between the substrate 21 and the first and second light emitting cells C 1 and C 2 , such that the first and second light emitting cells C 1 and C 2 are insulated from the substrate 21 .
  • the substrate 21 may have a substantially rectangular shape as shown in FIG. 10A .
  • a side surface of the substrate 21 may be formed by a laser scribing process and a cracking process using the laser scribing process, for example.
  • the substrate 21 may be removed from the first and second light emitting cells C 1 and C 2 by using a process, such as a laser lift-off process, a chemical lift-off process, or a grinding process.
  • the first and second light emitting cells C 1 and C 2 are disposed on the substrate 21 .
  • the first and second light emitting cells C 1 and C 2 are separated from each other by a separation area I through which the substrate 21 is partially exposed.
  • the separation area I refers to an area provided to separate the first and second light emitting cells C 1 and C 2 from each other, and is distinguished from a scribing or dicing area for separating the substrate 21 .
  • Semiconductor layers of the first and second light emitting cells C 1 and C 2 are spaced apart from each other by the separation area I.
  • the first and second light emitting cells C 1 and C 2 may be disposed to face each other and may have a substantially square shape or a substantially rectangular shape. In particular, the first and second light emitting cells C 1 and C 2 may have the substantially rectangular shape elongated in a direction in which the first and second light emitting cells C 1 and C 2 face each other.
  • Each of the first and second light emitting cells C 1 and C 2 includes the n-type semiconductor layer 23 , the active layer 25 , and the p-type semiconductor layer 27 .
  • the n-type semiconductor layer 23 , the active layer 25 , and the p-type semiconductor layer 27 may be formed of the group III-V nitride-based semiconductor, for example, a nitride-based semiconductor, such as (Al, Ga, In)N.
  • the n-type semiconductor layer 23 , the active layer 25 , and the p-type semiconductor layer 27 may be grown on the substrate 21 by a metal organic chemical vapor deposition (MOCVD) method in a chamber, for example.
  • MOCVD metal organic chemical vapor deposition
  • the n-type semiconductor layer 23 includes an n-type dopant, such as Si, Ge, or Sn
  • the p-type semiconductor layer 27 includes a p-type dopant, such as Mg, Sr, or Ba.
  • the n-type semiconductor layer 23 may include GaN or AlGaN, which includes Si as the dopant
  • the p-type semiconductor layer 27 may include GaN or AlGaN, which includes Mg as the dopant.
  • Each of the n-type semiconductor layer 23 and the p-type semiconductor layer 27 is shown as having a single-layer structure, however, the inventive concepts are not limited thereto, and in some exemplary embodiments, these layers may have a multi-layer structure or may include a superlattice layer.
  • the active layer 25 may have a single quantum well structure or a multiple quantum well structure, and a composition ratio of the nitride-based semiconductor may be adjusted to emit a light having a desired wavelength.
  • the active layer 25 may emit a blue light or an ultraviolet light.
  • the separation area I separates the first and second light emitting cells C 1 and C 2 from each other.
  • the substrate 21 is exposed through the semiconductor layers in the separation area I.
  • the separation area I is formed by using a photolithography process.
  • a photoresist is reflowed using a high-temperature baking process to form a photoresist pattern having a gentle slope, the photoresist pattern is used as a mask to etch the semiconductor layers, and thus, side surfaces may be formed in the separation area I with relatively gentle inclination.
  • a stepped inclined surface may be formed in the separation area I.
  • the stepped inclined surface may be formed in the separation area I during a process for forming a mesa that exposes the n-type semiconductor layer 23 , and by forming the separation area I that exposes the substrate 21 .
  • the first and second light emitting cells C 1 and C 2 face each other with the separation area I interposed therebetween.
  • side surfaces of the first and second light emitting cells C 1 and C 2 facing each other will be referred to as inner side surfaces.
  • side surfaces of the first and second light emitting cells C 1 and C 2 except for the inner side surfaces will be referred to as outer side surfaces.
  • the n-type semiconductor layers 23 of the first and second light emitting cells C 1 and C 2 include the inner and outer side surfaces as well.
  • the n-type semiconductor layer 23 may include one inner side surface and three outer side surfaces. As shown in FIG. 10D , the outer side surfaces of the n-type semiconductor layers 23 may have a steep slope relative to the inner side surface. In the illustrated exemplary embodiment, the outer side surfaces of the n-type semiconductor layers 23 are described to have the steep slope relative to the inner side surface, however, the inventive concepts are not limited thereto. For example, at least one outer side surface may have the steep slope relative to the inner side surface. As another example, only both outer side surfaces perpendicular to the separation area I may be relatively steeply inclined, and the outer side surface parallel to the separation area I may be inclined gently as the separation area I.
  • outer side surfaces which are relatively steeply inclined, may be substantially parallel to the side surface of the substrate 21 .
  • the outer side surfaces of the n-type semiconductor layers 23 may be formed by scribing the n-type semiconductor layer 23 together with the substrate 21 , and thus, may be formed with the side surfaces of the substrate 21 .
  • the mesa M is disposed on each n-type semiconductor layer 23 .
  • the mesa M may be disposed within an area surrounded by the n-type semiconductor layer 23 , and thus, areas near edges adjacent to the outer side surfaces of the n-type semiconductor layer 23 are exposed to the outside without being covered by the mesa M.
  • a side surface of the mesa M and the side surface of the n-type semiconductor layer 23 are discontinuous to each other on a sidewall of the separation area I, so that the above-mentioned stepped inclined surface may be formed.
  • the mesa M includes the p-type semiconductor layer 27 and the active layer 25 .
  • the active layer 25 is disposed between the n-type semiconductor layer 23 and the p-type semiconductor layer 27 .
  • An inner side surface of the mesa M is shown as being inclined as the outer surfaces thereof, however, the inventive concepts are not limited thereto.
  • the inner side surface of the mesa M may be more gently inclined than the outer surfaces thereof. In this manner, a stability of the second contact layer 35 b , which will be described later, may be improved.
  • the mesa M may be provided with a through hole 27 a defined through the p-type semiconductor layer 27 and the active layer 25 .
  • a plurality of through holes may be formed in the mesa M, however, the single through hole 27 a may be formed in the mesa M as shown in FIG. 10A .
  • the through hole 27 a may have a substantially circular shape at a center of the mesa M, without being limited thereto.
  • the through hole 27 a may have an elongated shape passing through the center of the mesa M.
  • the reflective structure 31 is disposed on each of the p-type semiconductor layers 27 of the first and second light emitting cells C 1 and C 2 .
  • the reflective structure 31 makes contact with the p-type semiconductor layer 27 .
  • the reflective structure 31 may be provided with an opening that exposes the through hole 27 a , and may be disposed over substantially the entire area of the mesa M in an upper area of the mesa M.
  • the reflective structure 31 may cover about 80% or more, specifically about 90% or more, of the upper area of the mesa M.
  • the reflective structure 31 may include a reflective metal layer having a reflective property, and thus, may reflect light generated from the active layer 25 and traveling to the reflective structure 31 .
  • the reflective metal layer may include Ag or Al.
  • an Ni layer may be disposed between the reflective metal layer and the p-type semiconductor layer 27 to help the reflective structure 31 making an ohmic contact with the p-type semiconductor layer 27 .
  • the reflective structure 31 may include a transparent oxide layer, such as indium tin oxide (ITO) or zinc oxide (ZnO).
  • the preliminary insulating layer 29 may cover the mesa M around the reflective structure 31 .
  • the preliminary insulating layer 29 may be formed of SiO 2 using a chemical vapor deposition method or the like, and may cover the side surface of the mesa M and some areas of the n-type semiconductor layer 23 .
  • the preliminary insulating layer 29 may be removed from a lower portion of the inclined surface of the separation area I, and may be remained on an upper portion of the inclined surface and a stepped portion of the separation area I as shown in FIG. 10D .
  • the lower insulating layer 33 covers the mesa M, the reflective structure 31 , and the preliminary insulating layer 29 .
  • the lower insulating layer 33 covers the separation area I, the sidewall of the mesa M, and portions of the n-type semiconductor layer 23 around the mesa M.
  • the lower insulating layer 33 may be formed along a shape of protrusions formed on the substrate 21 in the separation area I.
  • the lower insulating layer 33 may be disposed between the first, second, and third contact layers 35 a , 35 b , and 35 c .
  • the first and second light emitting cells C 1 and C 2 may provide a passage through which the first, second, and third contact layers 35 a , 35 b , and 35 c make contact with the n-type semiconductor layer 23 or the reflective structure 31 .
  • the lower insulating layer 33 may include a hole 33 a through which the reflective structure 31 is exposed on the first light emitting cell C 1 , a hole 33 b through which the reflective structure 31 is exposed on the second light emitting cell C 2 , and an opening 33 c through which the n-type semiconductor layer 23 is exposed in the through hole 27 a .
  • the lower insulating layer 33 exposes areas near the edge of the n-type semiconductor layer 23 while covering a periphery of the mesa M.
  • the hole 33 a may have an elongated shape that is substantially parallel to the separation area I as shown in FIG. 10A , and may be disposed closer to the separation area I than the through hole 27 a . Accordingly, a current may be injected into a wider area in the reflective structure 31 on the first light emitting cell C 1 .
  • the reflective structure 31 disposed on the first light emitting cell C 1 is exposed through the single hole 33 a , however, in some exemplary embodiments, the hole 33 a may be provided in a plural number.
  • the hole 33 b may be defined above the second light emitting cell C 2 and may be provided in a plural number as shown in FIG. 10A .
  • five holes 33 b are shown, however, the inventive concepts are not limited to a particular number of the holes 33 b , and in some exemplary embodiments, less number of holes 33 b or more number of holes 33 b than the five holes 33 b may be arranged.
  • a center of the entire holes 33 b is located farther from the separation area I than the center of the mesa M. Therefore, the current may be prevented from concentrating near the separation area I, and may be distributed in the wide area of the second light emitting cell C 2 .
  • the opening 33 C exposes the n-type semiconductor layer 23 in the through hole 27 a to provide a passage through which the first contact layer 35 a and the second contact layer 35 b make contact with the n-type semiconductor layer 23 .
  • the lower insulating layer 33 may include an insulating material, such as SiO 2 or Si 3 N 4 , and may have a single-layer or multi-layer structure.
  • the lower insulating layer 33 may include a distributed Bragg reflector formed by repeatedly stacking material layers having different refractive indices from each other, for example, SiO 2 /TiO 2 .
  • the first contact layer 35 a is disposed on the first light emitting cell C 1 and is in ohmic contact with the n-type semiconductor layer 23 .
  • the first contact layer 35 a may be in ohmic contact with the n-type semiconductor layer 23 along the periphery of the mesa M between the outer side surface of the n-type semiconductor layer 23 and the mesa M.
  • the first contact layer 35 a may be in ohmic contact with the n-type semiconductor layer 23 exposed through the opening 33 c of the lower insulating layer 33 in the through hole 27 a of the mesa M.
  • the first contact layer 35 a may cover the upper area and the side surface of the mesa M except for some areas around the hole 33 a.
  • the second contact layer 35 b is in ohmic contact with the n-type semiconductor layer 23 of the second light emitting cell C 2 , and makes contact with the reflective structure 31 of the first light emitting cell C 1 . Accordingly, the second contact layer 35 b electrically connects the p-type semiconductor layer 27 of the first light emitting cell C 1 and the n-type semiconductor layer 23 of the second light emitting cell C 2 .
  • the second contact layer 35 b may be in ohmic contact with the n-type semiconductor layer 23 along the periphery of the mesa M between the outer side surface of the n-type semiconductor layer 23 and the mesa M.
  • the second contact layer 35 b may be in ohmic contact with the n-type semiconductor layer 23 exposed through the opening 33 c of the lower insulating layer 33 in the through hole 27 a of the mesa M.
  • the second contact layer 35 b makes contact with the reflective structure 31 exposed through the hole 33 a .
  • the second contact layer 35 b extends from the second light emitting cell C 2 to the first light emitting cell C 1 after passing through the upper portion of the separation area I.
  • the second contact layer 35 b which passes through the upper portion of the separation area I, is disposed within a width of the mesa M as shown in FIG. 10A .
  • the second contact layer 35 b may be prevented from being short-circuited with the n-type semiconductor layer 23 of the first light emitting cell C 1 .
  • the second contact layer 35 b since the second contact layer 35 b is relatively gently inclined and passes through the separation area I that has a step structure, a process stability may be improved.
  • the second contact layer 35 b may be disposed on the lower insulating layer 33 in the separation area I, and may be formed to have concave-convex portions along the shape of the lower insulating layer 33 .
  • the third contact layer 35 c is disposed on the lower insulating layer 33 above the second light emitting cell C 2 .
  • the third contact layer 35 c makes contact with the reflective structure 31 via the holes 33 b of the lower insulating layer 33 , and is electrically connected to the p-type semiconductor layer 27 through the reflective structure 31 .
  • the third contact layer 35 c may be disposed in an area surrounded by the second contact layer 35 b , and may have a shape partially surrounding the second through hole 27 a .
  • the third contact layer 35 c is disposed at the same level as the first and second contact layers 35 a and 35 b , and helps the resin layer 37 and the first and second electrode pads 39 a and 39 b to be easily formed thereon. In some exemplary embodiments, the third contact layer 35 c may be omitted.
  • the first, second, and third contact layers 35 a , 35 b , and 35 c may be formed by the same process using the same material.
  • the first, second, and third contact layers 35 a , 35 b , and 35 c may include a high-reflectance metal layer, such as an Al layer, and the high-reflectance metal layer may be formed on an adhesive layer, e.g., a Ti, Cr, or Ni layer.
  • a protective layer having a single-layer or multi-layer structure of Ni, Cr, and/or Au may be disposed on the high-reflectance metal layer.
  • the first, second, and third contact layers 35 a , 35 b , and 35 c may have a multi-layer structure of Cr/Al/Ni/Ti/Ni/Ti/Au/Ti.
  • the resin layer 37 is disposed on the first contact layer 35 a and the second contact layer 35 b .
  • the resin layer 37 is provided with a first via hole 37 a defined therethrough to expose the first contact layer 35 a , and a second via hole 37 b defined therethrough to expose the third contact layer 35 c .
  • the first and second via holes 37 a and 37 b are formed in a shape partially surrounding the first through hole 27 a and the second through hole.
  • the third contact layer 35 c is omitted in some exemplary embodiments, the lower insulating layer 33 and the holes 33 b of the lower insulating layer 33 may be exposed through the second via hole 37 b.
  • the resin layer 37 may include concave portions 37 c above the first through hole 27 a and the second through hole 27 b .
  • the concave portions 37 c may be formed to correspond to the first through hole 27 a and the second through hole 27 b.
  • the resin layer 37 covers the first and second contact layers 35 a and 35 b that make contact with the n-type semiconductor layer 23 in the periphery of the mesa M. As shown in FIGS. 10B to 10D , an area between the first and second contact layers 35 a and 35 b and the edge of the n-type semiconductor layer 23 may be covered by the resin layer 37 . Accordingly, the first and second contact layers 35 a and 35 b may be protected from an external environment, such as moisture, by the resin layer 37 .
  • the resin layer 37 may cover the second contact layer 35 b on the separation area I and may be formed on the separation area I to have a concave portion along the shape of the second contact layer 35 b.
  • the resin layer 37 may include a photosensitive resin, such as a photoresist, and may be formed by a spin coating method, for example. Meanwhile, the first and second via holes 37 a and 37 b may be formed by a photo-development process, without being limited thereto.
  • the first electrode pad 39 a fills the first via hole 37 a of the resin layer 37 and is electrically connected to the first contact layer 35 a .
  • the second electrode pad 39 b fills the second via hole 37 b and is electrically connected to the third contact layer 35 c .
  • the second electrode pad 39 b may be directly connected to the reflective structure 31 .
  • the first electrode pad 39 a and the second electrode pad 39 b may partially surround the first through hole 27 a and the second through hole 27 b , respectively, when viewed in a plan view.
  • the first electrode pad 39 a and the second electrode pad 39 b partially surround the concave portions 37 c .
  • the first electrode pad 39 a and the second electrode pad 39 b may surround at least 1 ⁇ 2 of a circumference of the first through hole 27 a and the second through hole 27 b , and in some exemplary embodiments, 2 ⁇ 3 or more of the circumference of the first through hole 27 a and the second through hole 27 b .
  • the first electrode pad 39 a and the second electrode pad 39 b may protrude upward from the resin layer 37 . Accordingly, deep grooves may be formed above the areas corresponding to the first and second through holes 27 a and 27 b .
  • the solder When the light emitting diode chip 20 is bonded with a conductive adhesive, such as solder, using the grooves, the solder is trapped in the grooves, and thus, the solder may be prevented from overflowing to the outside.
  • the first electrode pad 39 a and the second electrode pad 39 b may be confined within the upper area of the mesa M.
  • FIGS. 11A and 11B are perspective views of a light emitting diode module according to an exemplary embodiment.
  • FIG. 11A is a view exemplarily illustrating a process of attaching the light emitting diode 10 to the external frame 300 using the solder paste 1 .
  • FIG. 11B is a view of a completed light emitting diode module according to an exemplary embodiment.
  • the light emitting diode 10 , the external frame 300 , and the solder paste 1 attaching the light emitting diode 10 to the external frame 300 are provided.
  • the solder paste 1 is provided in the first solder hole 151 , the second solder hole 152 , and the third solder hole 153 of the light emitting diode 10 .
  • the first lower electrode of the light emitting diode 10 is electrically connected to a first electrode 310 of the external frame 300 by the solder paste 1 provided in the first solder hole 151
  • a lower anode of the light emitting diode 10 is electrically connected to a third electrode 330 of the external frame 300 by the solder paste 1 provided in the second solder hole 152 .
  • the third lower electrode of the light emitting diode 10 is electrically connected to a second electrode 320 by the solder paste 1 provided in the third solder hole 153 .
  • the light emitting diode module may minimize the area occupied by the solder paste 1 , thereby providing a greater degree of miniaturization.
  • solder paste 1 is provided in the first, second, and third solder holes 151 , 152 , and 153 defined over the second surface and the third surface of the body portion 110 . Accordingly, the contact area between the solder paste 1 and the body portion 110 may be increased. Accordingly, the connection between the external frame 300 and the body portion 110 by the solder paste 1 may become more stable.
  • the “solder paste” refers to a final adhesive layer formed using a paste that is a mixture of metal powder, flux, and organic material.
  • the “solder paste” may also refer to the paste that is the mixture of the metal powder, the flux, and the organic material.
  • the solder paste 1 may include Sn and another metal.
  • the solder paste 1 may include about 50% or more, about 60% or more, or about 90% or more of Sn relative to the total metal weight.
  • the solder paste 1 may include a lead-containing solder alloy, such as Sn—Pb or Sn—Pb—Ag alloy, or a lead-free solder alloy, such as Sn—Ag alloy, Sn—Bi alloy, Sn—Zn alloy, Sn—Sb, or Sn—Ag—Cu alloy.
  • a lead-containing solder alloy such as Sn—Pb or Sn—Pb—Ag alloy
  • a lead-free solder alloy such as Sn—Ag alloy, Sn—Bi alloy, Sn—Zn alloy, Sn—Sb, or Sn—Ag—Cu alloy.
  • FIG. 11B shows the light emitting diode module according to an exemplary embodiment.
  • the light emitting diode module may irradiate light in a direction parallel to the external frame 300 , and thus, the light emitting diode module may be a side-type light emitting diode module.
  • FIGS. 12A and 12B are cross-sectional views of a light emitting diode module according to an exemplary embodiment.
  • FIGS. 12A and 12B show the form of the solder paste in more detail.
  • the solder paste 1 may be disposed to completely cover the first, second, and third solder holes 151 , 152 , and 153 when viewed from the side surface.
  • the solder paste 1 may have a height corresponding to about 150% to about 180% of a height of the first, second, and third solder holes 151 , 152 , and 153 .
  • the lead frame unit 100 and the external frame 300 may be stably connected to each other while preventing unintended electrical connection (e.g., short circuit) from occurring.
  • the solder paste 1 may be disposed to fill the first solder hole 151 .
  • at least a portion of the solder paste 1 may extend to the outside of the lead frame unit 100 .
  • a portion of the solder paste 1 may be provided in the form of gentle parabola outside the lead frame unit 100 .
  • the solder paste 1 may be disposed in the first solder hole 151 or in a first area 1 a between the second conductive layer and the external frame 300 and a second area 1 b outside the first solder hole 151 .
  • the second area 1 b in which the solder paste 1 is provided may include at least a portion of the second conductive layer, and thus, the solder paste 1 provided in the second area 1 b may cover at least the portion of the second conductive layer.
  • solder paste 1 When the solder paste 1 is disposed as described above, a horizontal or vertical movement of the external frame 300 may be limited. In addition, the electrical connection between the second conductive layer and the external frame 300 by the solder paste may be further strengthened.
  • the electrical and mechanical stability may be improved by providing more solder paste 1 than the capacity of the first, second, and third solder holes 151 , 152 , and 153 .
  • the first electrode 310 may be embedded in the external frame 300 . Accordingly, although the first electrode 310 is provided, the external frame 300 and the backlight unit including the external frame 300 may maintain slim thickness.
  • FIG. 13 is a perspective view of a light emitting diode module according to an exemplary embodiment.
  • the solder insulating layer 160 is disposed on the second surface of the body portion 110 of the lead frame unit 100 and protrudes toward the external frame 300 .
  • the solder insulating layer 160 may be disposed between the first, second, and third lower electrodes of the body portion 110 .
  • the solder insulating layer 160 disposed between the first, second, and third lower electrodes may have a first width D1.
  • the protruding portion of the solder insulating layer 160 may make contact with the external frame 300 .
  • the protruding portion of the solder insulating layer 160 may be disposed between the solder pastes 1 .
  • the solder insulating layer 160 disposed between the solder pastes 1 may prevent the lead frame unit 100 and the external frame 300 from moving in a horizontal direction, e.g., a direction substantially perpendicular to a direction in which the lead frame unit 100 and the external frame 300 are attached to each other.
  • a concave portion 360 may be disposed on the external frame 300 .
  • the concave portion 360 may be disposed between the first electrode 310 and the second electrode 320 and between the second electrode 320 and the third electrode 330 .
  • the concave portion 360 may have a shape corresponding to the protruding portion of the solder insulating layer 160 . In this manner, when the lead frame unit 100 is coupled to the external frame 300 , at least a portion of the protruding portion of the solder insulating layer 160 may be inserted into the concave portion 360 .
  • the concave portion 360 may have a second width D2, which may be substantially equal to the first width D1 of the solder insulating layer 160 .
  • the protruding portion of the solder insulating layer 160 which is inserted into the concave portion 360 , may be prevented from moving to the left and right, and the lateral external force applied to the solder paste 1 may be reduced.
  • the structural stability of the light emitting diode may be improved.
  • FIG. 14 is a cross-sectional view of a display device to which a light emitting diode module is applied according to an exemplary embodiment.
  • a display device 1000 includes a liquid crystal panel 1110 , a backlight unit 1120 , a support main 1130 , a cover bottom 1150 , and a top cover 1140 .
  • the liquid crystal panel 1110 may be a main component to display an image, and includes first and second substrates 1112 and 1114 coupled to each other with a liquid crystal layer interposed therebetween.
  • the backlight unit is disposed at a rear side of the liquid crystal panel 1110 .
  • the backlight unit 1120 includes a light emitting diode module 1160 arranged along a longitudinal direction of at least one edge of the support main 1130 , a reflective plate 1125 having a white or silver color, for example, and disposed on the cover bottom 1150 , a light guide plate 1123 disposed on the reflective plate 1125 , and a plurality of optical sheets 1121 disposed above the light guide plate 1123 .
  • the light emitting diode module may include the light emitting diode described with reference to FIGS. 1 to 12B , and may be implemented as the side-type light emitting diode module.
  • the light emitting diode module of the backlight unit 1120 may effectively dissipate heat, and thus, the display device 1000 of FIG. 14 may have a small temperature rise width even when used for a long time, and may stably display an image without a luminance change.
  • FIGS. 15A to 15D are plan views showing an upper surface of a mother substrate MS according to an exemplary embodiment.
  • the mother substrate MS includes a plurality of substrate patterns 110 a , 110 b , and 110 c , and an alignment mark 111 .
  • the substrate included in the light emitting diode may be manufactured by dicing the mother substrate MS.
  • the mother substrate MS is provided with the substrate patterns 110 a , 110 b and 110 c that may become substrates after the dicing process.
  • the mother substrate MS may include first, second, and third substrate patterns 110 a , 110 b , and 110 c .
  • the inventive concepts are not limited thereto, and in some exemplary embodiments, the mother substrate MS may include more number of substrate patterns or less number of substrate patterns than the first to third substrate patterns 110 a , 110 b , and 110 c.
  • the first substrate pattern 110 a has the same edge as the substrate on the mother substrate MS.
  • the edge may not perform any electrical function when the substrate is manufactured, and the edge is used to distinguish substrates different from each other during the dicing and patterning processes.
  • the substrates may be substantially simultaneously manufactured.
  • the substrates may be manufactured by forming the substrate patterns 110 a , 110 b , and 110 c , which are distinguished from each other by the edge, on one mother substrate MS and dicing between the substrate patterns 110 a , 110 b , and 110 c . Accordingly, multiple substrates may be substantially simultaneously manufactured as long as there is a space to perform the dicing process. Therefore, the illustrated processes according to the exemplary embodiments may manufacture a greater number of substrates substantially simultaneously as compared with the conventional processes.
  • the first substrate pattern 110 a may include a first upper electrode pattern 121 a , a second upper electrode pattern 122 a , a third upper electrode pattern 123 a , and a fourth upper electrode pattern 124 a .
  • the first upper electrode pattern 121 a , the second upper electrode pattern 122 a , the third upper electrode pattern 123 a , and the fourth upper electrode pattern 124 a may be formed by forming a conductive layer on the mother substrate MS and patterning the conductive layer.
  • the first upper electrode pattern 121 a will be described as a representative example.
  • the first upper electrode pattern 121 a may include a circular portion and an elongated portion.
  • the circular portion may have a circular shape and may be provided integrally with the elongated portion at one side of the elongated portion.
  • the first upper electrode pattern 121 a may not stick out from the first substrate pattern 110 a .
  • the first upper electrode pattern 121 a may be inclined due to process errors.
  • the corner may protrude to the outside of the first substrate pattern 110 a even though the first upper electrode pattern 121 a is slightly inclined.
  • the first upper electrode When a portion of the first upper electrode pattern 121 a protrudes to the outside of the first substrate pattern 110 a , the first upper electrode may be exposed to a side surface of a first substrate after the dicing process, and thus, unintended short-circuit may occur via the first upper electrode.
  • the probability that the end of the first upper electrode pattern 121 a is exposed to the outside of the first substrate pattern 110 a is lowered even though the first upper electrode pattern 121 a is inclined. Therefore, the probability that the unintended short-circuit occurs via the first upper electrode formed by the dicing process may be lowered.
  • the first upper electrode pattern 121 a has been described as a representative example among the first upper electrode pattern 121 a , the second upper electrode pattern 122 a , the third upper electrode pattern 123 a , and the fourth upper electrode pattern 124 a .
  • the structures and functions of the first upper electrode pattern 121 a may be applied equally to the second upper electrode pattern 122 a , the third upper electrode pattern 123 a , and the fourth upper electrode pattern 124 a.
  • the alignment mark 111 is disposed between the first, second, and third substrate patterns 110 a , 110 b , and 110 c .
  • the alignment mark 111 allows the mother substrate MS to be accurately aligned in the dicing process.
  • the term “accurately aligned” refers that the mother substrate MS is located such that the first, second, and third substrate patterns 110 a , 110 b , and 110 c remain intact without being cut off by the dicing process.
  • the alignment mark 111 may be formed with the first, second, and third substrate patterns 110 a , 110 b , and 110 c through the same process.
  • a conductive layer is formed on the mother substrate MS and patterned to remain the first, second, and third substrate patterns 110 a , 110 b , and 110 c and the alignment mark 111 .
  • the alignment mark 111 may have a width smaller than a width between the first, second, and third substrate patterns 110 a , 110 b , and 110 c .
  • the alignment mark 111 is inclined in the patterning process of the alignment mark 111 , the inclined alignment mark 111 is not connected to the first, second, and third substrate patterns 110 a , 110 b , and 110 c.
  • the width of the alignment mark 111 may be smaller than a width of a blade used in the dicing process. Therefore, the alignment mark 111 may be removed in the process of dicing the mother substrate MS along the alignment mark 111 . When the alignment mark 111 is not removed in the dicing process, the remaining alignment mark 111 may be exposed at the side surface of the substrate. In particular, since the alignment mark 111 may have a conductivity as the first upper electrode pattern 121 a , the exposed alignment mark 111 may cause short-circuit. Accordingly, the alignment mark 111 according to an exemplary embodiment has the width smaller than the width of the dicing blade, and thus, the alignment mark 111 is prevented from remaining on the substrate, thereby preventing the unintended short-circuit from occurring.
  • a second upper electrode pattern 122 a ′ and a third upper electrode pattern 123 a ′ have a different shape from a first upper electrode pattern 121 a ′ and a fourth upper electrode pattern 124 a ′, respectively.
  • the shape of the mask used in the patterning process may be changed to change the shape of the second upper electrode pattern 122 a ′ and the third upper electrode pattern 123 a ′ to be different from the shape of the first upper electrode pattern 121 a ′ and the fourth upper electrode pattern 124 a′.
  • the cathode and the anode may be easily distinguished from each other after the dicing process. Accordingly, when mounting the light emitting diode chip on the lead frame unit, the pad portion of the light emitting diode chip and the electrode of the lead frame unit may be prevented from being matched incorrectly.
  • the second substrate pattern 110 b ′ may be rotated by about 180 degrees when the dicing process is performed and the light emitting diode is mounted.
  • a mother substrate MS′′ includes a first alignment mark 111 ′′ and a second alignment mark 112 ′′.
  • the second alignment mark 112 ′′ may be disposed between a first anode mark 122 a ′′ and a second anode mark 123 a ′′.
  • the second alignment marks 112 ′′ is used together with the first alignment mark 111 ′′ to align the mother substrate MS′′ such that first, second, and third substrate patterns 110 a ′′′, 110 b ′′′, 110 c ′′ are not damaged in the dicing process.
  • the second alignment mark 112 ′′ may be formed together with a first cathode pattern 121 a ′′ through the same process when the first cathode pattern 121 a ′′ is formed. Accordingly, the second alignment mark 112 ′′ may have conductivity. As such, the second alignment mark 112 ′′ may be formed so as not to cross the first substrate pattern 110 a ′′ or not to meet the first anode pattern 122 a ′′ or the second anode pattern 123 a ′′.
  • the shape of the second alignment mark 112 ′′ is not particularly limited, and thus, in some exemplary embodiments, the second alignment mark 112 ′′ having various shapes other than a cross shape may be manufactured.
  • each of a first upper electrode pattern 121 a ′′′, a second upper electrode pattern 122 a ′′′, a third upper electrode pattern 123 a ′′′, and a fourth upper electrode pattern 124 a ′′′ has a substantially rectangular shape having one rounded end.
  • the first upper electrode pattern 121 a ′′′, the second upper electrode pattern 122 a ′′′, the third upper electrode pattern 123 a ′′′, and the fourth upper electrode pattern 124 a ′′′ have the substantially rectangular shape with one rounded end, the ease in operation of digging the via hole may be secured, and the first to fourth upper electrode patterns 121 a ′′′ to 124 a ′′′ may be prevented from being exposed to the outside of the substrate.
  • FIGS. 16A and 16B are plan views of an upper surface of a mother substrate according to an exemplary embodiment.
  • a first substrate pattern 110 a ′′′ includes a cathode pattern 123 a ′′′ and an anode pattern 124 a ′′′. Since the first substrate pattern 110 a ′′′ includes one cathode pattern 123 a ′′′ and one anode pattern 124 a ′′′, a plurality of substrate patterns 110 a ′′′, 110 b ′′′, and 110 c ′′′ may be arranged in a matrix form.
  • a first alignment mark 111 ′′′ and a second alignment mark 112 ′′′ may be disposed between the substrate patterns 110 a ′′′, 110 b ′′′, and 110 c ′′′.
  • the first alignment mark 111 ′′′ may be arranged in a column direction of the substrate patterns 110 a ′′′, 110 b ′′′, and 110 c ′′
  • the second alignment mark 112 ′′′ may be arranged in a row direction of the substrate patterns 110 a ′′′, 110 b ′′′, and 110 c′′.
  • the cathode pattern 123 a ′′′ and the anode pattern 124 a ′′′ may have different shapes from each other.
  • the cathode pattern 123 a ′′′ and the anode pattern 124 a ′′′ have different shapes from each other, the light emitting diode chip may be easily mounted.
  • FIG. 17 is a plan view of a lower surface of a body portion according to an exemplary embodiment.
  • a first body portion 110 _ 1 and a second body portion 110 _ 2 are disposed to be substantially symmetrical with each other with respect to a horizontal direction.
  • a first body portion through hole 151 _ 1 and a second body portion through hole 151 _ 2 may be substantially simultaneously formed through the first body portion 110 _ 1 and the second body portion 110 _ 2 , respectively.
  • first body portion through hole 151 _ 1 and the second body portion through hole 151 _ 2 are substantially simultaneously formed through the first body portion 110 _ 1 and the second body portion 110 _ 2 , respectively, the process efficiency may be improved.
  • a thinner light emitting diode and a thinner light emitting diode module may be provided, with a higher degree of integration.
  • the occurrence of short-circuit occurs in the light emitting diode and light emitting diode module may be substantially prevented or suppressed, and heat resistance of the light emitting diode and the light emitting diode module may be improved.

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PCT/KR2019/005826 WO2019221508A1 (ko) 2018-05-18 2019-05-15 발광 다이오드, 발광 다이오드 모듈 및 그것을 갖는 표시 장치

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Families Citing this family (7)

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Publication number Priority date Publication date Assignee Title
DE102018125138A1 (de) * 2018-10-11 2020-04-16 Osram Opto Semiconductors Gmbh Strahlungsemittierendes bauteil und verfahren zur herstellung eines strahlungsemittierenden bauteils
TWI726685B (zh) 2020-04-16 2021-05-01 錼創顯示科技股份有限公司 微型發光元件顯示裝置
CN111463233B (zh) * 2020-04-16 2022-09-13 錼创显示科技股份有限公司 微型发光元件显示装置
CN111583820B (zh) * 2020-05-14 2022-04-08 Tcl华星光电技术有限公司 一种led灯板及其制备方法
CN112331638B (zh) * 2020-09-28 2023-06-06 惠州市聚飞光电有限公司 发光二极管及背光模组
JP7368771B2 (ja) * 2021-09-30 2023-10-25 日亜化学工業株式会社 発光装置、線状光源およびその駆動方法
CN114388673B (zh) * 2021-12-08 2023-11-14 华灿光电（浙江）有限公司 微型发光二极管芯片及其制备方法

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009044112A (ja) 2007-07-13 2009-02-26 Sharp Corp 素子搭載基板、電子部品、発光装置、液晶バックライト装置、電子部品の実装方法
KR20090083202A (ko) 2008-01-29 2009-08-03 (주) 아모엘이디 엘이디 패키지 및 이를 이용한 백라이트 유니트
JP2011054736A (ja) 2009-09-01 2011-03-17 Sharp Corp 発光装置、平面光源および液晶表示装置
US20120205677A1 (en) * 2011-02-10 2012-08-16 Rohm Co., Ltd. Led module
WO2013027568A1 (ja) 2011-08-23 2013-02-28 シャープ株式会社 発光装置
JP2013110179A (ja) 2011-11-18 2013-06-06 Citizen Holdings Co Ltd 半導体発光装置
US20150060903A1 (en) 2013-08-27 2015-03-05 Glo Ab Molded led package and method of making same
US20170244010A1 (en) * 2016-02-24 2017-08-24 Samsung Electronics Co., Ltd. Light-emitting device packages and methods of manufacturing the same
JP2017188589A (ja) 2016-04-06 2017-10-12 日亜化学工業株式会社 発光装置
US20180080641A1 (en) * 2016-09-21 2018-03-22 Toyota Gosei Co., Ltd. Light source and method of mounting light-emitting device
US20180315897A1 (en) * 2017-04-28 2018-11-01 Nichia Corporation Light-emitting device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103003966B (zh) * 2010-05-18 2016-08-10 首尔半导体株式会社 具有波长变换层的发光二级管芯片及其制造方法，以及包括其的封装件及其制造方法
CN205944139U (zh) * 2016-03-30 2017-02-08 首尔伟傲世有限公司 紫外线发光二极管封装件以及包含此的发光二极管模块
KR102554231B1 (ko) * 2016-06-16 2023-07-12 서울바이오시스 주식회사 전극 구조를 갖는 수직형 발광 다이오드 및 그것을 갖는 발광 다이오드 패키지
MA46359A (fr) 2016-09-29 2019-08-07 Amgen Inc Protéines de liaison à l'antigène à viscosité faible et leurs procédés de préparation
KR20180056896A (ko) 2016-11-21 2018-05-30 박순희 한국인 모유로부터 분리한 락토바실러스 가세리 제이12피4 와 스타필로코커스 에피더미디스 제이4피1로 제조한 인공영양아용 미생물제제 및 이를 사용한 장염 억제 방법

Patent Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009044112A (ja) 2007-07-13 2009-02-26 Sharp Corp 素子搭載基板、電子部品、発光装置、液晶バックライト装置、電子部品の実装方法
KR20090083202A (ko) 2008-01-29 2009-08-03 (주) 아모엘이디 엘이디 패키지 및 이를 이용한 백라이트 유니트
JP2011054736A (ja) 2009-09-01 2011-03-17 Sharp Corp 発光装置、平面光源および液晶表示装置
US8410502B2 (en) 2009-09-01 2013-04-02 Sharp Kabushiki Kaisha Light-emitting device, planar light source including the light-emitting device, and liquid crystal display device including the planar light source
US20170186735A1 (en) 2011-02-10 2017-06-29 Rohm Co., Ltd. Led module
US20120205677A1 (en) * 2011-02-10 2012-08-16 Rohm Co., Ltd. Led module
WO2013027568A1 (ja) 2011-08-23 2013-02-28 シャープ株式会社 発光装置
US20140197447A1 (en) 2011-08-23 2014-07-17 Sharp Kabushiki Kaisha Light emitting device
JP2013110179A (ja) 2011-11-18 2013-06-06 Citizen Holdings Co Ltd 半導体発光装置
US20150060903A1 (en) 2013-08-27 2015-03-05 Glo Ab Molded led package and method of making same
US20170244010A1 (en) * 2016-02-24 2017-08-24 Samsung Electronics Co., Ltd. Light-emitting device packages and methods of manufacturing the same
JP2017188589A (ja) 2016-04-06 2017-10-12 日亜化学工業株式会社 発光装置
US10026718B2 (en) 2016-04-06 2018-07-17 Nichia Corporation Light emitting device
US20180080641A1 (en) * 2016-09-21 2018-03-22 Toyota Gosei Co., Ltd. Light source and method of mounting light-emitting device
JP2018049953A (ja) 2016-09-21 2018-03-29 豊田合成株式会社 光源および発光装置の実装方法
US10041663B2 (en) 2016-09-21 2018-08-07 Toyoda Gosei Co., Ltd. Light source and method of mounting light-emitting device
US20180315897A1 (en) * 2017-04-28 2018-11-01 Nichia Corporation Light-emitting device

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Extended European Search Report dated Dec. 6, 2021, issued in European Patent Application No. 19804513.0.
Office Action dated Feb. 14, 2022 for Indian Patent Application No. 202037051820 (with English Translation).

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US20190393392A1 (en) 2019-12-26
CN110993768A (zh) 2020-04-10
KR20190132215A (ko) 2019-11-27

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