US10867542B2 - Electroluminescence display - Google Patents

Electroluminescence display Download PDF

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Publication number
US10867542B2
US10867542B2 US16/027,323 US201816027323A US10867542B2 US 10867542 B2 US10867542 B2 US 10867542B2 US 201816027323 A US201816027323 A US 201816027323A US 10867542 B2 US10867542 B2 US 10867542B2
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contact point
subpixels
layer
source
repair
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US20190019444A1 (en
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Sunghak Jo
Jaehee Park
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LG Display Co Ltd
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LG Display Co Ltd
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Assigned to LG DISPLAY CO., LTD. reassignment LG DISPLAY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JO, SUNGHAK, PARK, JAEHEE
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2003—Display of colours
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    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/861—Repairing

Definitions

  • the present disclosure relates to an electroluminescence display.
  • a display device comprises a display panel including a plurality of subpixels, drivers displaying the display panel, and a power supply part supplying electric power to the display panel.
  • the drivers include a scan driver supplying scan signals (or gate signals) and a data driver supplying data signals to the display panel.
  • a process of manufacturing a display panel includes a deposition process and a repair process.
  • the deposition process is a process in which a conductive layer, a metal layer, and an insulating layer are deposited on a substrate to form structures such as elements (including electrodes), power supply lines, and signal lines.
  • the repair process is a process in which defects on the structures formed on the substrate are repaired or defective subpixels are turned into dark dots.
  • the present disclosure provides an electroluminescence display comprising: a first substrate; subpixels arranged on the first substrate; and repair lines located on the first substrate, one for at least every two subpixels that emit light of the same color and are adjacent to each other, wherein the repair lines comprise one side having a contact point with an electrode of a first subpixel and the other side having a non-contact point with an electrode of a second subpixel.
  • FIG. 1 is a schematic block diagram of an organic electroluminescence display
  • FIG. 2 is a schematic circuit diagram of a subpixel
  • FIG. 3 is a plan view of the arrangement of subpixels to which a repair method according to a first exemplary aspect of the present disclosure is applicable;
  • FIG. 4 is a plan view of the layout of subpixels according to the first exemplary aspect of FIG. 3 ;
  • FIG. 5 is a plan view of the arrangement of subpixels to which a repair method according to a second exemplary aspect of the present disclosure is applicable;
  • FIG. 6 is a plan view of the layout of subpixels according to the second exemplary aspect of FIG. 5 ;
  • FIG. 7 is a plan view of the arrangement of subpixels to which a repair method according to a third exemplary aspect of the present disclosure is applicable;
  • FIG. 8 is a plan view of the layout of subpixels according to the third exemplary aspect of FIG. 7 ;
  • FIG. 9 is a plan view of the arrangement of subpixels to which a repair method according to the third exemplary aspect of the present disclosure is applicable.
  • FIG. 10 is a cross-sectional view of the region A 1 -A 2 in FIG. 9 ;
  • FIG. 11 is a cross-section of the region B 1 -B 2 in FIG. 9 ;
  • FIG. 12 is a cross-sectional view of the region A 1 -A 2 in FIG. 9 after laser welding;
  • FIG. 13 is a cross-sectional view of the region B 1 -B 2 in FIG. 9 after laser welding.
  • FIG. 14 is a photograph of electrodes that have turned into a conducting state after a repair process according to the present disclosure.
  • An electroluminescence display to be described below may be implemented as a television, a video player, a personal computer (PC), a home theater, a smartphone, a virtual reality device (VR), etc.
  • the electroluminescence display to be described below is an organic electroluminescence display implemented based on an organic light-emitting diode (light-emitting element), for example.
  • the electroluminescence display to be described below may be implemented based on an inorganic light-emitting diode.
  • source and drain electrodes of thin-film transistors of the organic light-emitting display to be described below may be used interchangeably for different types, but the term “gate electrode” is not interchangeable. Hence, the source and drain electrodes may be termed first and second electrodes so as not to limit them.
  • FIG. 1 is a schematic block diagram of an organic electroluminescence display.
  • FIG. 2 is a schematic circuit diagram of a subpixel.
  • the organic electroluminescence display includes an image processor 110 , a timing controller 120 , a data driver 130 , a scan driver 140 , a display panel 150 , and a power supply part 160 .
  • the image processor 110 outputs a data enable signal DE, along with externally supplied data signals DATA.
  • the image processor 110 may output one or more among a vertical synchronization signal, a horizontal synchronization signal, and a clock signal, in addition to the data enable signal DE. These signals may be omitted in the drawings for convenience of explanation.
  • the timing controller 120 receives data signals DATA, along with the data enable signal DE or drive signals comprising a vertical synchronization signal, a horizontal synchronization signal, and a clock signal, from the image processor 110 .
  • the timing controller 120 outputs a gate timing control signal GDC for controlling the operation timing of the scan driver 140 and a data timing control signal DDC for controlling the operation timing of the data driver 130 , based on the drive signals.
  • the data driver 140 samples and latches a data signal DATA supplied from the timing controller 120 in response to a data timing control signal DDC supplied from the timing controller 120 , and converts it into a gamma reference voltage.
  • the data driver 130 outputs data signals DATA through data lines DL 1 to DLn.
  • the data driver 130 may be provided in the form of an IC (integrated circuit).
  • the scan driver 140 outputs scan signals in response to a gate timing control signal GDC supplied from the timing controller 120 .
  • the scan driver 140 outputs scan signals through scan lines GL 1 to GLm.
  • the scan driver 140 may be provided in the form of an IC (integrated circuit) or formed on the display panel 150 using the gate-in-panel technology.
  • the power supply part 160 outputs a high-level voltage and a low-level voltage.
  • the high-level voltage and low-level voltage outputted from the power supply part 160 are supplied to the display panel 150 .
  • the high-level voltage is supplied to the display panel 150 via a first power supply line EVDD, and the low-level voltage is supplied to the display panel 150 via a second power supply line EVSS.
  • the display panel 150 displays an image in response to data signals DATA and scan signals respectively supplied from the data driver 130 and scan driver 140 and power supplied from the power supply part 160 .
  • the display panel 150 comprises a first substrate, subpixels SP formed on the first substrate that work to display an image, and a second substrate that seals the subpixels SP along with the first substrate.
  • the first substrate and the second substrate may be made of rigid material such as glass or flexible material such as resin.
  • the subpixels SP may include red subpixels, green subpixels, and blue subpixels, or may include white subpixels, red subpixels, green subpixels, and blue subpixels.
  • the subpixels SP may have one or more different light-emission areas depending on the light-emission characteristics.
  • a single subpixel includes a switching transistor SW, a driving transistor DR, a capacitor Cst, and an organic light-emitting diode OLED.
  • a single subpixel may further comprise a compensation circuit CC.
  • the switching transistor SW switches to store a data voltage supplied via the first data line DL 1 as a data voltage in the capacitor Cst, in response to a scan signal supplied via the first scan line GL 1 .
  • the driving transistor DR works in such a way that a drive current flows between the first power supply line EVDD (high-level voltage) and the second power supply line EVSS (low-level voltage) in response to the data voltage stored in the capacitor Cst.
  • the organic light-emitting diode OLED works in such a way as to emit light in response to the drive current formed by the driving transistor DR.
  • the compensation circuit CC is a circuit that is added into the subpixel to compensate for the threshold voltage, etc. of the driving transistor DR.
  • the compensation circuit CC consists of one or more transistors.
  • the compensation circuit CC may have many configurations depending on the method of compensation, so a description thereof will be omitted.
  • a process of manufacturing the aforementioned display panel may include a deposition process and a repair process.
  • the deposition process is a process in which a conductive layer, a metal layer, and an insulating layer are deposited on a substrate to form structures such as elements (including electrodes), power supply lines, and signal lines.
  • the repair process is a process in which defects on the structures formed on the substrate are repaired or defective subpixels are turned into dark dots.
  • the conventionally proposed repair method involves the risk of aperture ratio loss (or transmission loss) and requires the structures used in the repair process to be cut away or removed. Thus, there is a need for improvements in production yield and tact time. Accordingly, exemplary aspects for improving the conventionally proposed repair method will be described below.
  • FIG. 3 is a plan view of the arrangement of subpixels to which a repair method according to a first exemplary aspect of the present disclosure is applicable.
  • FIG. 4 is a plan view of the layout of subpixels according to the first exemplary aspect of FIG. 3 .
  • the first exemplary aspect of the present disclosure is based on red, green, blue, and white subpixels R, G, B, and W.
  • the red, green, blue, and white subpixels R, G, B, and W are arranged as a unit pixel. That is, a single pixel can be defined by red, green, blue, and white subpixels R, G, B, and W.
  • red and green subpixels R and G are arranged on first and third scan lines, respectively, and blue and white subpixels B and W are arranged on second and fourth scan lines, respectively.
  • this is merely an example, but the sequence of these subpixels may differ according to the light-emission characteristics, the lifetime of the elements, the specification of the device, and so on, and the present disclosure is not limited to this example.
  • repair lines RRL, GRL, BRL, and WRL may be vertically arranged. As viewed from the plane, the repair lines RRL, GRL, BRL, and WRL have no overlapping regions. That is, the repair lines RRL, GRL, BRL, and WRL may be arranged in such a way that they do not overlap (non-overlap). Thus, all the repair lines RRL, GRL, BRL, and WRL are formed by electrodes on the same layer. For example, an electrode layer may be selected as source and drain electrodes of thin-film transistors.
  • One repair line RRL, GRL, BRL, and WRL may be allocated for at least every two subpixels that emit light of the same color and are vertically adjacent to each other.
  • the repair lines RRL, GRL, BRL, and WRL serve to electrically connect at least two subpixels through the repair process.
  • One side of the repair lines RRL, GRL, BRL, and WRL has a contact point CP that makes contact with an electrode of a first subpixel, and the other side has a non-contact point WP that does not make contact with an electrode of a second subpixel.
  • the electrode of the second subpixel and the non-contact point WP are electrically connected, and the electrode of the first subpixel and the electrode of the second subpixel become conductive via a repair line.
  • the repair lines RRL, GRL, BRL, and WRL include red repair lines RRL, green repair lines GRL, blue repair lines BRL, and white repair lines WRL.
  • a green subpixel G arranged on a first scan line has a non-contact point WP and is connected to one side of a green repair line GRL
  • a green subpixel G arranged on a third scan line has a contact point CP and is connected to the other side of the green repair line GRL.
  • a blue subpixel B arranged on a second scan line has a non-contact point WP and is connected to one side of a blue repair line BRL
  • a blue subpixel B arranged on a fourth scan line has a contact point CP and is connected to the other side of the blue repair line BRL.
  • the red repair lines RRL, green repair lines GRL, blue repair lines BRL, and white repair line WRL are vertically arranged along non-light emission areas defined in the direction of the long axis of the subpixels R, G, B, and W.
  • the red repair lines RRL, green repair lines GRL, blue repair lines BRL, and white repair line WRL are arranged in such a way that they do not overlap, in order to bypass the contact points CP or non-contact points WP of other repair lines.
  • the contact points CP and the non-contact points WP are located on one side and the other side of the repair lines RRL, GRL, BRL, and WRL. Also, the contact points CP and the non-contact points WP are not fixed in position, but their positions may be changed, considering the arrangement of the subpixels R, G, B, and W and other repair lines.
  • the contact points CP and the non-contact points WP may be arrayed in pairs on either side of the repair lines RRL, GRL, BRL, and WRL. The reason is because, by forming the contact points CP and the non-contact points WP in pairs, there is no need to cut away or remove the structures (repair lines) used in the repair process, and, as a result, production yield and process tact time can be improved. A description about this will be given in further details below.
  • FIG. 4 is a plan view of the layout of subpixels according to the first exemplary aspect of FIG. 3 , which is attached to show the actual configuration of subpixels and repair lines without specifying them and used only for reference.
  • ARL is a repair line
  • WP is a non-contact point
  • CP is a contact point.
  • the foregoing first exemplary aspect has the advantage of repairing a defect occurring in a subpixel at a specific position by making contact with one terminal (contact point) in advance, but not the other terminal (non-contact point or open position), and welding the non-contact point once.
  • FIG. 5 is a plan view of the arrangement of subpixels to which a repair method according to a second exemplary aspect of the present disclosure is applicable.
  • FIG. 6 is a plan view of the layout of subpixels according to the second exemplary aspect of FIG. 5 .
  • the second exemplary aspect of the present disclosure is based on red, green, blue, and white subpixels R, G, B, and W.
  • the red, green, blue, and white subpixels R, G, B, and W are arranged as a unit pixel. That is, a single pixel is defined by red, green, blue, and white subpixels R, G, B, and W.
  • red and green subpixels R and G are arranged on first and third scan lines, respectively, and blue and white subpixels B and W are arranged on second and fourth scan lines, respectively.
  • this is merely an example, but the sequence of these subpixels may differ according to the light-emission characteristics, the lifetime of the elements, the specification of the device, and so on, and the present disclosure is not limited to this example.
  • repair lines RRL, GRL, BRL, and WRL may be vertically arranged.
  • the repair lines RRL, GRL, BRL, and WRL have overlapping regions OVA. That is, the repair lines RRL, GRL, BRL, and WRL may be arranged in such a way that they overlap—for example, they are allocated one overlapping region OVA for at least every two lines (e.g., one for every two scan lines if the repair lines are vertically arranged, or one for every two data lines if the repair lines are horizontally arranged).
  • repair lines RRL, GRL, BRL, and WRL are formed by lower electrodes on a lower layer, and the others are formed by upper electrodes on an upper layer.
  • a lower electrode layer may be selected as source and drain electrodes of thin-film transistors
  • an upper electrode layer may be selected as lower electrodes (e.g., anodes) of organic light-emitting.
  • One repair line RRL, GRL, BRL, and WRL is allocated for at least every two subpixels that emit light of the same color and are vertically adjacent to each other.
  • the repair lines RRL, GRL, BRL, and WRL serve to electrically connect at least two subpixels through the repair process.
  • One side of the repair lines RRL, GRL, BRL, and WRL has a contact point CP that makes contact with an electrode of a first subpixel, and the other side has a non-contact point WP that does not make contact with an electrode of a second subpixel.
  • the electrode of the second subpixel and the non-contact point WP are electrically connected, and the electrode of the first subpixel and the electrode of the second subpixel become conductive via a repair line.
  • the repair lines RRL, GRL, BRL, and WRL comprise red repair lines RRL, green repair lines GRL, blue repair lines BRL, and white repair lines WRL.
  • a green subpixel G arranged on a first scan line has a non-contact point WP and is connected to one side of a green repair line GRL
  • a green subpixel G arranged on a third scan line has a contact point CP and is connected to the other side of the green repair line GRL.
  • the green repair line GRL and the white repair line WRL have a partially overlapping region OVA.
  • a blue subpixel B arranged on a second scan line has a non-contact point WP and is connected to one side of a blue repair line BRL
  • a blue subpixel B arranged on a fourth scan line has a contact point CP and is connected to the other side of the blue repair line BRL.
  • the blue repair line BRL and the red repair line RRL have a partially overlapping region OVA.
  • the contact points CP and the non-contact points WP are located on one side and the other side of the repair lines RRL, GRL, BRL, and WRL. Also, the contact points CP and the non-contact points WP are not fixed in position, but their positions may be changed, considering the arrangement of the subpixels R, G, B, and W and other repair lines.
  • the contact points CP and the non-contact points WP may be arrayed in pairs on either side of the repair lines RRL, GRL, BRL, and WRL. The reason is because, by forming the contact points CP and the non-contact points WP in pairs, there is no need to cut away or remove the structures (repair lines) used in the repair process, and, as a result, production yield and process tact time can be improved. A description about this will be given in further details below.
  • FIG. 6 is a plan view of the layout of subpixels according to the second exemplary aspect of FIG. 5 , which is attached to show the actual configuration of subpixels and repair lines without specifying them and used only for reference.
  • ARL is a repair line
  • WP is a non-contact point
  • CP is a contact point
  • OVA is an overlapping region between repair lines on different layers.
  • the foregoing second exemplary aspect has the advantage of repairing a defect occurring in a subpixel at a specific position by making contact with one terminal (contact point) in advance, but not the other terminal (non-contact point or open position), and welding the non-contact point once.
  • the second exemplary aspect can minimize the reduction in aperture ratio caused by the addition of repair lines since the repair lines are formed on different layers and overlap.
  • the second exemplary aspect has been described with an example in which contact points and non-contact points are formed respectively on either side of the repair lines.
  • this is merely an example, and the non-contact points may be formed on both sides of the repair lines.
  • laser welding has to be carried out twice because there are two non-contact points.
  • FIG. 7 is a plan view of the arrangement of subpixels to which a repair method according to a third exemplary aspect of the present disclosure is applicable.
  • FIG. 8 is a plan view of the layout of subpixels according to the third exemplary aspect of FIG. 7 .
  • the third exemplary aspect of the present disclosure is based on red, green, blue, and white subpixels R, G, B, and W.
  • the red, green, blue, and white subpixels R, G, B, and W are arranged as a unit pixel. That is, a single pixel is defined by red, green, blue, and white subpixels R, G, B, and W.
  • red and green subpixels R and G are arranged on first and third scan lines, respectively, and blue and white subpixels B and W are arranged on second and fourth scan lines, respectively.
  • this is merely an example, but the sequence of these subpixels may differ according to the light-emission characteristics, the lifetime of the elements, the specification of the device, and so on, and the present disclosure is not limited to this example.
  • repair lines RRL, GRL, BRL, and WRL may be vertically arranged. As viewed from the plane, the repair lines RRL, GRL, BRL, and WRL have no overlapping regions. That is, the repair lines RRL, GRL, BRL, and WRL may be arranged in such a way that they do not overlap (non-overlap). Thus, all the repair lines RRL, GRL, BRL, and WRL are formed by electrodes on the same layer. For example, an electrode layer may be selected as lower electrodes (e.g., transparent electrodes) of organic light-emitting diodes.
  • One repair line RRL, GRL, BRL, and WRL is allocated for at least every two subpixels that emit light of the same color and are vertically adjacent to each other.
  • the repair lines RRL, GRL, BRL, and WRL serve to electrically connect at least two subpixels through the repair process.
  • One side of the repair lines RRL, GRL, BRL, and WRL has a contact point CP that makes contact with an electrode of a first subpixel, and the other side has a non-contact point WP that does not make contact with an electrode of a second subpixel.
  • the electrode of the second subpixel and the non-contact point WP are electrically connected, and the electrode of the first subpixel and the electrode of the second subpixel become conductive via a repair line.
  • the repair lines RRL, GRL, BRL, and WRL comprise red repair lines RRL, green repair lines GRL, blue repair lines BRL, and white repair lines WRL.
  • a green subpixel G arranged on a first scan line has a non-contact point WP and is connected to one side of a green repair line GRL
  • a green subpixel G arranged on a third scan line has a contact point CP and is connected to the other side of the green repair line GRL.
  • a blue subpixel B arranged on a second scan line has a non-contact point WP and is connected to one side of a blue repair line BRL
  • a blue subpixel B arranged on a fourth scan line has a contact point CP and is connected to the other side of the blue repair line BRL.
  • the contact points CP and the non-contact points WP are located on one side and the other side of the repair lines RRL, GRL, BRL, and WRL. Also, the contact points CP and the non-contact points WP are not fixed in position, but their positions may be changed, considering the arrangement of the subpixels R, G, B, and W and other repair lines.
  • the contact points CP and the non-contact points WP may be arrayed in pairs on either side of the repair lines RRL, GRL, BRL, and WRL. The reason is because, by forming the contact points CP and the non-contact points WP in pairs, there is no need to cut away or remove the structures (repair lines) used in the repair process, and, as a result, production yield and process tact time can be improved. A description about this will be given in further details below.
  • FIG. 8 is a plan view of the layout of subpixels according to the third exemplary aspect of FIG. 7 , which is attached to show the actual configuration of subpixels and repair lines without specifying them and used only for reference.
  • ARL is a repair line
  • WP is a non-contact point
  • CP is a contact point.
  • the foregoing third exemplary aspect has the advantage of repairing a defect occurring in a subpixel at a specific position by making contact with one terminal (contact point) in advance, but not the other terminal (non-contact point or open position), and welding the non-contact point once. Moreover, the third exemplary aspect can minimize the reduction in aperture ratio caused by the addition of repair lines since the repair lines are formed of transparent electrodes that allow light to pass through.
  • FIG. 9 is a plan view of the arrangement of subpixels to which a repair method according to the third exemplary aspect of the present disclosure is applicable.
  • FIG. 10 is a cross-sectional view of the region A 1 -A 2 in FIG. 9 .
  • FIG. 11 is a cross-section of the region B 1 -B 2 in FIG. 9 .
  • a lower electrode layer E 1 and source-drain electrode layer SD located at a non-contact point WP are electrically separated by an insulating material.
  • the structures shown at the non-contact point WP are as follows.
  • a light blocking layer LS is located on a first substrate 150 a .
  • the light blocking layer LS serves to block (prevent) light from entering a channel region (semiconductor region) of a thin-film transistor.
  • the light blocking layer LS is made of a metal material capable of blocking light transmission.
  • the light blocking layer LS may be omitted depending on the thin-film transistor structure.
  • a buffer layer BUF is located on the first substrate 150 a .
  • the buffer layer BUF serves to electrically insulate the light blocking layer LS or prevent effects of material leaking from the first substrate 150 a .
  • the buffer layer BUF is configured to cover the light blocking layer LS.
  • a first insulating layer ILD is located on the buffer layer BUF.
  • the first insulating layer ILD may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers of silicon nitride (SiNx) and silicon oxide (SiOx).
  • the source-drain electrode layer SD is located on the first insulating layer ILD.
  • the source-drain electrode layer SD may be formed of one of molybdenum (Mo), aluminum (Al), chrome (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu) or an alloy thereof, and may be composed of a single layer or multiple layers.
  • the source-drain electrode layer SD is made of the same metal material as the source and drain electrodes of the thin-film transistor.
  • the source-drain electrode layer SD is an extension from an electrode of a driving transistor included in a green subpixel G on a first scan line (an electrode connected to the organic light-emitting diode).
  • a passivation layer PAS is located on the source-drain electrode layer SD.
  • the passivation layer PAS may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers of silicon nitride (SiNx) and silicon oxide (SiOx).
  • a planarization layer OC with a recessed contact hole corresponding to the non-contact point WP is located on the passivation layer PAS.
  • the planarization layer OC planarizes the surface of a transistor array including thin-film transistors.
  • the planarization layer OC may be made of organic material such as an overcoat layer, polyimide, benzocyclobutene series resin, acrylate, and photoacryl.
  • the lower electrode layer E 1 is located on the planarization layer OC.
  • the lower electrode layer E 1 is located within the contact hole in the planarization layer OC.
  • the lower electrode layer E 1 may be formed of transparent electrodes that allow light to pass through—for example, oxides such as ITO (indium tin oxide) and IZO (indium zinc oxide).
  • the lower electrode layer E 1 is made of the same layer and same material as the electrode of the organic light-emitting diode included in the green subpixel G on the first scan line, but is separated from it.
  • a bank layer BNK is located on the lower electrode layer E 1 .
  • the bank layer BNK defines light emission areas (or aperture areas) of subpixels.
  • the bank layer BNK may be made of organic material or inorganic material.
  • a lower electrode layer E 1 and source-drain electrode layer SD located at a contact point CP are electrically connected.
  • the structures shown at the non-contact point WP are as follows.
  • a light blocking layer LS is located on a first substrate 150 a .
  • the light blocking layer LS serves to block (prevent) light from entering a channel region (semiconductor region) of a thin-film transistor.
  • the light blocking layer LS is made of a metal material capable of blocking light transmission.
  • the light blocking layer LS may be omitted depending on the thin-film transistor structure.
  • a buffer layer BUF is located on the first substrate 150 a .
  • the buffer layer BUF serves to electrically insulate the light blocking layer LS or prevent effects of material leaking from the first substrate 150 a .
  • the buffer layer BUF is configured to cover the light blocking layer LS.
  • a first insulating layer ILD is located on the buffer layer BUF.
  • the first insulating layer ILD may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers of silicon nitride (SiNx) and silicon oxide (SiOx).
  • the source-drain electrode layer SD is located on the first insulating layer ILD.
  • the source-drain electrode layer SD may be formed of one of molybdenum (Mo), aluminum (Al), chrome (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu) or an alloy thereof, and may be composed of a single layer or multiple layers.
  • the source-drain electrode layer SD is made of the same metal material as the source and drain electrodes of the thin-film transistor.
  • the source-drain electrode layer SD is an extension from an electrode of a driving transistor included in a green subpixel G on the first scan line (an electrode connected to the organic light-emitting diode).
  • a passivation layer PAS with a contact hole corresponding to a contact point CP is located on the source-drain electrode layer SD.
  • the passivation layer PAS may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers of silicon nitride (SiNx) and silicon oxide (SiOx).
  • a planarization layer OC with a recessed contact hole corresponding to the contact point CP is located on the passivation layer PAS.
  • the planarization layer OC planarizes the surface of a transistor array including thin-film transistors.
  • the planarization layer OC may be made of organic material such as an overcoat layer, polyimide, benzocyclobutene series resin, acrylate, and photoacryl.
  • the lower electrode layer E 1 is located on the planarization layer OC.
  • the lower electrode layer E 1 is located within the contact hole in the planarization layer OC.
  • the lower electrode layer E 1 may be formed of transparent electrodes that allow light to pass through—for example, oxides such as ITO (indium tin oxide) and IZO (indium zinc oxide).
  • the lower electrode layer E 1 is electrically connected to the source-drain electrode layer SD via the contact holes formed in the planarization layer OC and passivation layer PAS.
  • a bank layer BNK is located on the lower electrode layer E 1 .
  • the bank layer BNK defines light emission areas (or aperture areas) of subpixels.
  • the bank layer BNK may be made of organic material or inorganic material.
  • FIG. 12 is a cross-sectional view of the region A 1 -A 2 in FIG. 9 after laser welding.
  • FIG. 13 is a cross-sectional view of the region B 1 -B 2 in FIG. 9 after laser welding.
  • FIG. 14 is a photograph of electrodes that have turned into a conducting state after a repair process according to the present disclosure.
  • the non-contact point WP in the non-light emission area of the green subpixel G on the first scan line may be irradiated with a laser.
  • the source-drain electrode SD and the passivation layer PAS are melted.
  • the source-drain electrode SD and the lower electrode E 1 are electrically connected.
  • the lower electrode layer E 1 allows the green subpixels G on the first and third scan lines to share the electrodes of the driving transistors. As a result, even if one of the two subpixels becomes operationally defective (inoperable), normal driving can be done by
  • FIG. 12 Since FIG. 12 , by its nature, cannot clearly depict the source-drain electrode layer SD and passivation layer PAS in a melted state, this melted state will be shown clearly with reference to FIG. 14 .
  • the source/drain electrodes layer SD and the passivation layer PAS are melted when irradiated with a laser. As the passivation layer PAS is melted, the insulation between the source-drain electrode layer SD and the anode electrode layer (lower electrode layer E 1 of this disclosure) breaks down. The melted source-drain electrode layer SD comes into contact with the anode electrode layer (lower electrode layer E 1 of this disclosure) located above it.
  • one repair line is allocated for at least every two subpixels that emit light of the same color and are adjacent to each other, which allows for easy repair of any operational defect occurring in one of the two subpixels by a one-time repair process.
  • the present disclosure can improve production yield and process tact time, since there is no need to cut away or remove repair lines used in the repair process. Additionally, the present disclosure can minimize the reduction in aperture ratio caused by the addition of repair lines.

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US11645957B1 (en) * 2020-09-10 2023-05-09 Apple Inc. Defective display source driver screening and repair

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KR20210038224A (ko) * 2019-09-30 2021-04-07 엘지디스플레이 주식회사 표시 장치
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TW202218144A (zh) * 2020-10-30 2022-05-01 群創光電股份有限公司 顯示裝置
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CN109273485B (zh) 2023-09-29
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