US10720337B2 - Pre-cleaning for etching of dielectric materials - Google Patents

Pre-cleaning for etching of dielectric materials Download PDF

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US10720337B2
US10720337B2 US16/040,859 US201816040859A US10720337B2 US 10720337 B2 US10720337 B2 US 10720337B2 US 201816040859 A US201816040859 A US 201816040859A US 10720337 B2 US10720337 B2 US 10720337B2
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plasma
cleaning
oxide
etch
cyclic
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US20200027746A1 (en
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Rene Henricus Jozef Vervuurt
Nobuyoshi Kobayashi
Takayoshi Tsutsumi
Masaru Hori
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ASM IP Holding BV
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ASM IP Holding BV
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Priority to KR1020190086736A priority patent/KR102550244B1/ko
Assigned to ASM IP HOLDING B.V. reassignment ASM IP HOLDING B.V. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HORI, MASARU, TSUTSUMI, TAKAYOSHI, KOBAYASHI, NOBUYOSHI, VERVUURT, RENE HENRICUS JOZEF
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H—ELECTRICITY
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    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082—Radio frequency generated discharge
    • H01J37/32091—Radio frequency generated discharge the radio frequency energy being capacitively coupled to the plasma
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    • H01J37/32—Gas-filled discharge tubes
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    • H01J37/32724—Temperature
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    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32798—Further details of plasma apparatus not provided for in groups H01J37/3244 - H01J37/32788; special provisions for cleaning or maintenance of the apparatus
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    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
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    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
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    • H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
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    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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Definitions

  • the present application relates to dry etch processing of dielectric materials.
  • etch or remove material from the top of a material such as a dielectric layer.
  • One such process is atomic layer etching, which can include both dry and wet layer etching.
  • a highly uniform and selective cyclic dry etch process can be performed by cyclic etch by adding a pre-clean process to remove a surface oxide of the dielectric material.
  • the removal of the oxide can be executed through thermal reaction and/or plasma process before the dry etch process.
  • the removal of the oxide increases cyclic etch process control and reproducibility and can improve the selectivity of etching a surface that contains oxide versus without oxide.
  • a dry etch process can occur on the pre-cleaned dielectric surface. The process can be repeated in any number of rounds.
  • the dry etch process comprises cyclic dry etching.
  • pre-cleaning comprises a fluorine or chlorine containing plasma treatment to remove a surface oxide and the dry etching comprises at least one round of H 2 plasma treatment and fluorine or chlorine containing radical treatment.
  • the pre-clean process is sufficient (e.g., conducted for long enough or repeated enough times) to achieve at least one of the following: (a) a superior etch profile control, (b) enhanced etch selectivity between different dielectric materials and oxides, (c) consistent etch thickness per cycle of cyclic dry etching, (d) cyclic etching of SiN, SiC, and SiCOH, with selectivity of etching between each, or (e) reduced surface and sidewall roughness.
  • a film on a substrate is etched in a reaction chamber by cyclic etch comprising one or more cycles.
  • the etching is dry etching involving at least one round of dry etching.
  • the dry etching comprises one or more rounds of providing a H 2 plasma and providing a fluorine or chlorine containing plasma.
  • the cyclic dry etch process comprises repeated cycles of fluorination or chlorination and ligand exchange with a first reactant gas and repeated cycles of modification by thermal reaction with a second reactant gas and etching by thermal reaction with fluorine or chlorine containing gas.
  • the first reactant gas can be a fluorine containing gas.
  • the fluorine-containing gas can comprise HF or XeF 2 .
  • the second reactant gas can also be a fluorine containing gas.
  • the fluorine-containing gas can comprise HF or XeF 2
  • the chlorine containing gas can comprise BCl 3 , CCl 4 or SOCl 2 .
  • the first reactant gas can be the same as the second reactant gas.
  • the first reactant gas can be different from the second reactant gas.
  • the reactants can be removed from the reaction chamber, such as by purging with an inert gas. The cyclic dry etching may be repeated until a desired level of etching has been obtained.
  • HF surface oxide removal can also be done wet chemically outside of the system
  • the surface oxide that is to be removed during the pre-clean can comprise silicon oxide or metal oxide.
  • the cyclic dry etching may comprise repeated cycles of fluorine containing film (CxFy) deposition and irradiation by Ar ions and/or other inert ions such as He.
  • the surface oxide may comprise a metal oxide.
  • the metal oxide may comprise a group consisting at least one of titanium oxide, hafnium oxide, tungsten oxide, molybdenum oxide, aluminum oxide and zirconium oxide.
  • pre-cleaning comprises a thermal reaction with a reactant gas. In some embodiments, pre-cleaning further comprises a plasma-assisted process comprising fluorine or chlorine ions or radicals. In some embodiments, pre-cleaning further comprises a plasma-assisted process comprising ions with sufficient energy to sputter the surface oxide.
  • the temperature of the dielectric material is nearly equal to the deposition temperature of the dielectric material or lower where the pre-cleaning is conducted in the same reactor used for the dielectric material deposition.
  • the pressure of the atmosphere is nearly equal to the deposition pressure of the dielectrics material or less where the pre-cleaning is conducted in the same reactor used for the dielectric material deposition.
  • the cyclic dry etching process further comprises providing a dielectric film prior to the pre-clean process.
  • the dielectric material comprises silicon.
  • the dielectric material may comprise at least one of SiN, SiON, SiC, SiCN, SiCO, SiCOH, or SiCON.
  • the dielectric material comprises a metal.
  • the dielectric material may comprise at least one of TiN, TiC, HfN, HfC, WC, WN, MoC, MoN, AlN, AlC, ZrN, or ZiC.
  • the dielectric material can be present on a recess pattern.
  • the recess pattern can comprise trenches having a width of 5 nm to 1000 nm and an aspect ratio of 1 to 100.
  • the dielectric film has a thickness of 100 nm or less.
  • FIG. 1 illustrates a pre-clean process before cyclic dry etch process.
  • FIG. 2 illustrates an XPS spectrum of Si bonding configuration for SiN. It shows the presence of a surface oxide.
  • FIG. 3A illustrates a pre-cleaning process of the cyclic dry etch process of SiN using H 2 and SF 6 plasma.
  • FIG. 3B illustrates the dry etch process of the cyclic dry etch process of SiN using H 2 and SF 6 radicals (plasma) which can be repeated any number of times (“n”).
  • FIG. 4 is a graph illustrating a comparison between the etched thickness of SiN with a pre-clean process and the etched thickness of SiN without a pre-clean process.
  • FIG. 5 is a graph illustrating the difference in etched thickness of different dielectric materials.
  • FIG. 6A is an image illustrating a Si 3 N 4 substrate's uniformity and surface roughness without pre-clean.
  • FIG. 6B is an image illustrating a Si 3 N 4 substrate's uniformity and surface roughness with pre-clean.
  • FIG. 7 is a flow chart illustrating some embodiments of processing of a substrate.
  • FIGS. 8A-8C illustrate cross-sectional views of substrates according to some embodiments provided herein.
  • FIGS. 9A-9D illustrate cross-sectional views of substrates according to some embodiments of the disclosed technology.
  • FIG. 10 is a schematic representation of an apparatus for various methods provided herein.
  • Cyclic etching of dielectric materials is often hindered by the presence of a surface oxide on top of these materials.
  • the surface oxide layers can be formed due to air exposure from the oxygen containing atmosphere as well as other conditions difficult to control.
  • the surface oxide involves nitrogen or carbon when the dielectric material is nitride or carbide of silicon and metal.
  • the presence of the surface oxide can reduce EPC (etched thickness per cycle) and degrade the etch selectivity especially between the dielectric material and oxide.
  • a cyclic dry etch process that can comprise a pre-clean process and at least one etching process.
  • the pre-clean process comprises removing a surface oxide from a dielectric material to provide a pre-cleaned dielectric material.
  • the pre-clean process can be achieved by a thermal reaction, or a plasma process, or a combination of a thermal reaction and a plasma process.
  • the pre-clean process comprises a thermal reaction with a reactant gas.
  • the reactant gas can be a fluorine-containing gas.
  • the fluorine-containing can be HF, XeF 2 , or a combination of HF and XeF 2 .
  • the HF reactant denotes the wet chemical etching of the oxide before transferring the wafer to the reactor.
  • the thermal reaction comprises repeated cycles of fluorination and ligand exchange with the reactant gas.
  • the pre-clean process comprises a plasma process, and can be a plasma-assisted process.
  • the plasma-assisted process can be a SF 6 plasma treatment.
  • the plasma-assisted process comprises fluorine ions and radicals.
  • the reactant gas can be a chlorine containing gas.
  • the pre-clean process is sufficient to achieve at least one of the following: a) superior etch profile control, b) enhanced etch selectivity between different dielectric materials and oxides, c) consistent etch thickness per cycle of cyclic dry etching, d) cyclic etching of SiN, SiC, and SiCOH, with selectivity of etching between each, or e) reduced surface and sidewall roughness.
  • the superior etch profile is at least as smooth as that shown in FIG. 6B , as compared to FIG. 6A . The reduction of surface roughness is quantitatively confirmed by AFM (Atomic Force Microscopy).
  • the enhanced etch selectivity is at least as good as that shown in FIG. 5 , e.g., a) SiO vs SiCOH, SiC, and/or SiN; or b) SiCOH vs. SiC, vs. SiN.
  • ALE utilizes sequential pulses of vapor phase reactants to remove material from a substrate in each reaction cycle. In some embodiments up to a monolayer of material is removed in each etch cycle. A sub-monolayer or more of material can be removed from a substrate by ALE processes comprising contacting the substrate surface in a reaction space with at least one vapor-phase reactant. The ALE can follow the pre-cleaning process noted herein for a superior product. In some embodiments, the ALE is a dry etch process. In some embodiments, the ALE is a wet etch process.
  • the substrate comprises a dielectric layer on which a pre-clean process is performed to remove a surface oxide from the surface of the dielectric layer.
  • the method can include applying the dielectric layer to the substrate to provide a dielectric material on the substrate.
  • the dielectric layer can comprise silicon or a metal.
  • the dielectric layer may comprise one or more of SiN, SiON, SiC, SiCN, SiCO, SiCOH, or SiCON.
  • the dielectric layer may comprise one or more of TiN, TiC, HfN, HfC, WC, WN, MoC, MoN, AlN, AlC, ZrO or ZrC.
  • the surface oxide to be removed may comprise a silicon oxide or a metal oxide.
  • the metal oxide to be removed can be selected from at least one of: titanium oxide, hafnium oxide, tungsten oxide, or molybdenum oxide. In some embodiments, any oxide can be removed from the surface of the dielectric layer via the pre-cleaning process.
  • the dielectric layer is present on a recess pattern.
  • the recess pattern can comprise trenches having a width of between 10 nm and 100 nm.
  • the recess pattern may comprise trenches having a width of 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, or more.
  • the recess pattern may comprise trenches having a width of less than 10 nm.
  • the recess pattern may also comprise trenches having a width of more than 100 nm.
  • the recess pattern can have an aspect ratio of between 1 and 10.
  • the recess pattern can have an aspect ratio of 1, 2, 3, 4, 5, 6, 7, 8, 9, or 10.
  • the width and the aspect ratio is dependent on the application area.
  • the width ranges from 5 nm to 100 nm and the aspect ratio from 2 to 100 corresponds to nanometer-level logic and memory devices
  • the width ranges from 100 to 1000 nm and the aspect ratio from 1 to 100 corresponds to TSV (Through Silicon Via) for connecting nanometer-level devices in three dimensions.
  • the dielectric material can have a temperature of 100° C. or lower.
  • the dielectric material can have a temperature of 100° C., 90° C., 80° C., 70° C., 60° C., 50° C., 40° C., 30° C., 20° C., or 10° C.
  • the pressure of the atmosphere can be 10 Pa or less.
  • the pressure can be 10 Pa, 9 Pa, 8 Pa, 7 Pa, 6 Pa, 5 Pa, 4 Pa, 3 Pa, 2 Pa, 1 Pa, 0.5, or 0.1 Pa.
  • the initial dielectric material can have a thickness of 20 nm or less.
  • the dielectric material can have a thickness of 20 nm, 15 nm, 10 nm, 5 nm, 1 nm or a thickness less than 1 nm.
  • 100 MHz is used, for example, 200, 190, 180, 170, 160, 150, 140, 130, 120, 110, 100, 90, 80, 70, 60, 50, 40, 30, 20, 15, 10, or 5 MHz is used with CCP (Capacitor Coupled Plasma)-type reactor
  • 100 W is used, for example, 200, 190, 180, 170, 160, 150, 140, 130, 120, 110, 100, 90, 80, 70, 60, or 50 W is used.
  • 0 W bias is present during the pre-cleaning. In some embodiments, some bias is present during the pre-cleaning.
  • the temperature of the dielectric material is nearly equal to the deposition temperature of the dielectric material or lower where the pre-cleaning is conducted in the same reactor used for the dielectric material deposition. In some embodiments, the pressure of the atmosphere is nearly equal to the deposition pressure of the dielectrics material or less where the pre-cleaning is conducted in the same reactor used for the dielectric material deposition.
  • CCP plasma vs Microwave plasma
  • the type of plasma can be switched to reduce the ion energy.
  • the pre-cleaning if a plasma is used
  • the cyclic etch process can then be used with a lower ion energy to improve the selectivity between oxide and dielectric.
  • FIG. 10 depicts a CCP-type reactor that can be used for pre-cleaning.
  • FIG. 10 by providing a pair of electrically conductive flat-plate electrodes 4 , 2 in parallel and facing each other in the interior 11 (reaction zone) of a reaction chamber 3 , applying HRF power (13.56 MHz or 27 MHz) 25 to one side, and electrically grounding the other side 12 , a plasma is excited between the electrodes.
  • HRF power 13.56 MHz or 27 MHz
  • a temperature regulator is provided in a lower stage 2 (the lower electrode), and a temperature of a substrate 1 placed thereon is kept constant at a given temperature.
  • the upper electrode 4 serves as a shower plate as well, and reactant gas and/or dilution gas, if any, and precursor gas are introduced into the reaction chamber 3 through a gas line 21 and a gas line 22 , respectively, and through the shower plate 4 . Additionally, in the reaction chamber 3 , a circular duct 13 with an exhaust line 7 is provided, through which gas in the interior 11 of the reaction chamber 3 is exhausted.
  • a transfer chamber 5 disposed below the reaction chamber 3 is provided with a seal gas line 24 to introduce seal gas into the interior 11 of the reaction chamber 3 via the interior 16 (transfer zone) of the transfer chamber 5 wherein a separation plate 14 for separating the reaction zone and the transfer zone is provided (a gate valve through which a wafer is transferred into or from the transfer chamber 5 is omitted from this figure).
  • the transfer chamber is also provided with an exhaust line 6 .
  • a substrate bias 25 is provided.
  • the pre-cleaning with a plasma-assisted process can be conducted with inductively couple plasma (ICP), electron cyclotron resonance (ECR), or a surface-wave-sustained-type (SWP-type) reactor.
  • ICP inductively couple plasma
  • ECR electron cyclotron resonance
  • SWP-type surface-wave-sustained-type
  • the type of plasma (CCP plasma vs Microwave plasma) is switched between pre-cleaning and etching to reduce the ion energy.
  • the pre-cleaning (if a plasma is used) will take place at lower pressure, higher plasma power, and/or even with biasing. This can allow for a higher ion energy which is useful to remove the surface oxide (when not chemically activated).
  • the cyclic etch process can then be used with a lower ion energy to improve the selectivity between oxide and dielectric.
  • the pre-cleaning process results in removal of at least some amount of the surface oxide. In some embodiments, at least 1, 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 65, 70, 75, 80, 85, 90, 95, 96, 97, 98, 99, 99.9, 99.99% or greater of the surface oxide layer is removed by the pre-cleaning. In some embodiments, effectively all of the surface oxide is removed. In some embodiments, about 100% of the material is etched. In some embodiments, sufficient amount of the surface oxide is removed such that further pre-cleaning does not provide any increased effectiveness of a subsequent etching process.
  • the pre-clean process comprises a plasma-assisted process comprising ions with sufficient energy to sputter the surface oxide.
  • the reaction chamber is purged between the pre-clean process and the etch process.
  • an etch process (e.g., cyclic etch, dry etch, wet etch, ALE, etc.) can occur.
  • the process can occur by using the clustering reactor system between the pre-clean and etching reactors.
  • the pre-clean process can occur in the same reactor where the etch process is conducted.
  • the etch process comprises a cyclic dry etching process. For example, all the dry etch process are repeated any number of times. For example, all the dry etch processes are repeated two, three, four, five, six seven, eight, nine, ten, or more times.
  • the dry etch process comprises one cycle of dry etch.
  • the dry etch process comprises a plasma process.
  • the plasma process can comprise a H 2 plasma treatment and fluorine containing plasma treatment.
  • the plasma process can comprise a H 2 plasma treatment and a fluorine ions or radical treatment.
  • the fluorine ions or radical treatment can comprise SF 6 ions or radical treatment.
  • the dry etch process comprises repeated cycles of modification by thermal reaction with a reactant gas and etching by thermal reaction with fluorine containing gas.
  • the dry etch process comprises repeated cycles of modification can be repeated cycles of fluorine containing film (CxFy) deposition by plasma process and plasma irradiation using Ar, He or other inert ions and radicals.
  • FIG. 1 illustrates a pre-clean process that removes a surface oxide before a cyclic dry etch process.
  • the cyclic dry etch process can comprises any number of steps (e.g., step A, step B, step C and other steps) that can be repeated any number of times (or rounds, e.g., 1, 10, 20, 30, 40, 50 or more rounds). In some embodiments, the process is repeated until the desired layer thickness reduction (etch) is achieved.
  • the pre-clean process and the cyclic dry etch process may improve the etch profile control and enhance etch selectivity between various dielectric materials and oxides.
  • FIG. 2 is an XPS spectrum image of Si bonding configuration for SiN. It shows the presence of a surface oxide that can be removed by the processing according to an embodiment the disclosed technology.
  • FIG. 3A illustrates some embodiments involving a first pre-cleaning process of the cyclic dry etch process of SiN using H 2 and SF 6 plasma.
  • the first pre-cleaning process comprises removing surface oxides from a Si 3 N 4 substrate by treating the Si 3 N 4 substrate with a SF 6 plasma.
  • the SF 6 plasma can come from a capacitively coupled plasma (CCP) source and can be applied at 100 MHz, 100 W, 2 Pa, with 0 W bias. This represents some embodiments of the pre-clean process.
  • CCP capacitively coupled plasma
  • FIG. 3B illustrates a dry etch process of the cyclic dry etch process of SiN using H 2 and SF 6 radicals (plasma).
  • the dry etch process comprises treating the Si 3 N 4 substrate, after the first pre-cleaning process, with a H 2 plasma.
  • the H 2 plasma can come from a CCP source and can be applied at, for example 100 MHz, 100 W, 2 Pa, with 0 W bias.
  • the Si 3 N 4 substrate can be cyclically treated by SF 6 radicals.
  • the SF 6 radicals can come from a remote plasma source and can be applied at 2.45 GHz, 50 W, and 2 Pa.
  • FIG. 7 illustrates a process flow diagram showing the processing of a substrate according to some embodiments of the disclosed technology.
  • a pre-clean process may comprise providing a dielectric onto a substrate and removing a surface oxide from the substrate. Subsequently, a dry etch process, which can involve any number of steps (e.g., step A, step B and step C) and can optionally be repeated any number of times, (for example, 1, 10, 100, or more times) is performed.
  • FIGS. 8A-8C illustrate cross-sectional views of a Si substrate 830 going through some embodiments of the disclosed technology.
  • FIG. 8A illustrates a material that comprises a surface oxide layer 810 , a SiC layer 820 , and a Si substrate layer 830 .
  • the 50 nm thick SiC layer is deposited on the Si substrate by PECVD at 300 C.
  • FIG. 8B illustrates pre-cleaning the material illustrated in FIG. 8A .
  • the pre-cleaning using NF 3 plasma is conducted at 300 C in the same reactor where the SiC layer is deposited.
  • FIG. 8C illustrates the material after the pre-clean process, in which the surface oxide layer 810 is removed and the material comprises the dielectric 820 and the substrate 830 .
  • the dielectric layer 820 can then be etched as desired by, for example, cyclic etching in the same reactor
  • FIGS. 9A-9D illustrate cross-sectional views of substrates of going through some embodiments of the disclosed technology for Si 3 N 4 spacer formation.
  • FIG. 9A illustrates a material that comprises a surface oxide 910 , a Si 3 N 4 layer 920 , an etch stop of SiON layer 930 and a Si substrate 940 , and a hard mask of carbon layer.
  • the 5 nm thick SiON layer 930 was deposited on the Si substrate by PECVD, and followed by the 50 nm thick carbon layer deposition by PECVD.
  • the carbon layer was patterned by the immersion ArF lithography and dry etch.
  • the 20 nm thick Si 3 N 4 layer 920 was deposited on the patterned carbon layers by ALD.
  • the surface 910 oxide is formed during the substrate transfer to the etch reactor by air exposure.
  • FIG. 9B illustrates the material after the pre-cleaning process of SF 6 plasma, in which the surface oxide 910 has been removed.
  • FIG. 9C illustrates the Si 3 N 4 layer after an asotropic cyclic etch process of SF 6 radicals, after which the S3N4 layer 920 has been partially and selectively etched away.
  • FIG. 9D illustrates the Si3N3 spacer after another etch process using O2 plasma, after which the carbon layer is further partially and selectively etched away.
  • the cyclic etch methods disclosed herein are thermal etching processes, as opposed to plasma etching processes. Thus, plasma reactants need not be used in the etch cycles. In some embodiments, the cyclic etch methods are plasma processes. Thermal etch methods can be more desirable in some situations than plasma cyclic etch methods because thermal cyclic etch methods can be less damaging to the underlying substrate. Also, thermal cyclic etch methods allow for isotropic etching of non-line of sight (NLOS) features. For example, HF vapor can remove a surface oxide on a dielectric material at low temperature ⁇ 100 C.
  • NLOS non-line of sight
  • the cyclic etch processes disclosed herein (which follow the pre-clean process) utilize particular reactants or combinations of reactants that have been found to allow for controlled etching in the absence of the use of plasma.
  • the cyclic etch can be a wet cyclic etch or a dry cyclic etch.
  • excess first vapor phase reactant and any reaction byproducts are removed from the proximity of the substrate surface.
  • the first vapor phase reactant and any reaction byproducts may be removed from the proximity of the substrate or substrate surface with the aid of a purge gas and/or vacuum.
  • excess reactant and/or reactant byproducts are removed from the reaction space by purging, for example, with an inert gas.
  • the substrate may be moved in order to facilitate removal of the reactant and/or reactant byproducts from the vicinity of the substrate or substrate surface, for example, by moving the substrate to a different reaction chamber.
  • the conformality of the etching process can be very good, and material can be removed evenly from all surfaces of a three-dimensional structure.
  • the conformality of etching vertically is greater than about 90% and the conformality of etching horizontally is greater than about 92%.
  • conformality of etching in vertical openings is about 50% or greater, about 75% or greater, about 85% or greater, about 90% or greater, about 95% or greater, about 98% or greater, about 99% or greater, and even up to about 100%.
  • conformality of etching in openings extending horizontally is about 50% or greater, about 75% or greater, about 85% or greater, about 90% or greater, about 95% or greater, about 98% or greater, about 99% or greater, and even up to about 100%.
  • conformality for a 3D structure such as a horizontal or lateral cavity, can be greater than 50%, or greater than 80%, or even greater than 90%, or even higher than 99% and even up to about 100%. Conformality can sometimes be even greater than 100%.
  • the substrate comprising a material to be etched is loaded into a reaction space or reactor.
  • the reactor may be part of a cluster tool in which a variety of different processes in the formation of an integrated circuit are carried out.
  • a flow-type reactor is utilized.
  • a cross-flow reactor is used.
  • a shower head type of reactor is utilized.
  • a space divided reactor is utilized.
  • a high-volume manufacturing-capable single wafer atomic layer deposition reactor is used.
  • a batch reactor comprising multiple substrates is used.
  • suitable reactors include commercially available equipment such as the F-120® reactor, F-450® reactor, Pulsar® reactors—such as the Pulsar® 2000 and the Pulsar® 3000—EmerALD® reactor and Advance® 400 Series reactors, available from ASM America, Inc. of Phoenix, Ariz. and ASM Europe B.V., Almere, Netherlands.
  • Other commercially available reactors include those from ASM Japan K.K (Tokyo, Japan) under the tradename Eagle® XP and XP8.
  • the reactor is an etch reactor.
  • the exposed surfaces of the workpiece can be treated to provide reactive sites to react with the first phase of the cyclic etch process. In some embodiments, a separate treatment process is not required.
  • the substrate is treated to provide a desired surface termination. In some embodiments the substrate is treated with plasma.
  • etch cycles may be performed at temperatures ranging from about 20 to about 1200° C., about 50 to about 800° C., about 75 to about 600° C., about 300° C. to about 500° C., or from about 350° C. to about 450° C.
  • the temperature is greater than about 20, 50 or 100° C., but less than about 1000, 800, 600 or 500° C.
  • the cycles are carried out at a temperature of about 450° C.
  • the pressure in the reaction chamber for the etch cycles for some embodiments can be typically from about 10E-9 torr to about 760 torr, or about 0.001 to about 100 torr. However, in some cases, the pressure will be higher or lower than this range, as can be determined by the skilled artisan given the particular circumstances. In some embodiments, a pressure of less than 2 torr is utilized.
  • the reactor can be operated either in isothermal (such as hot-wall) or non-isothermal (such as cold-wall) conditions. In some embodiments the reactor itself does not interact with etching chemistries and may also not interact with substrates. In some cases reactor can comprise a hot-wall, cold-wall or warm-wall type of reaction chamber.
  • the etch cycle has an average etch rate of about 0.01 to about 5 ⁇ /cycle.
  • Etch rate is defined as amount of material or thickness of film is removed after each cycle.
  • the average etch rate is about 0.01 to 0.1 ⁇ /cycle or from 0.1 to about 2 ⁇ /cycle or in some cases even higher than 2 ⁇ /cycle.
  • the average etch rate is more than about 0.1 ⁇ /cycle, more than about 0.5 ⁇ /cycle, more than about 1.0 ⁇ /cycle, more than about 2.0 ⁇ /cycle, more than about 3.0 ⁇ /cycle, more than about 5.0 ⁇ /cycle, more than about 10 ⁇ /cycle or more than about 20 ⁇ /cycle and in some instances if continuous flow is applied with flow rate modification or the exposure times are long enough the etch rates can be more than about 30 ⁇ /cycle, more than about 50 ⁇ /cycle or about 100 ⁇ /cycle.
  • the present pre-cleaning process is not limited by any particular form of cyclic etching.
  • the plasma etch cycle can have an etch rate of about ⁇ 50 ⁇ /cycle.
  • the modification relies on the ion implantation depth for the process. For H2 this can be several nm.
  • the EPC can be increased by increasing the substrate bias.
  • etch rates of 100 A/cycle can be obtained. In thermal etch cycle (e.g., ALE), the etch rate can be in the 0.1-3 A/cycle range as this relies more heavily on surface reactions.
  • the etch selectivity i.e. the ratio of material (thickness, mass or amount of atoms/molecules) removed from the desired surface/material to material removed from the non-desired surface/materials or surfaces/materials, is from more than about 2:1, more than about 3:1, more than about 5:1, more than about 7:1, more than about 10:1, more than about 15:1, more than about 20:1, more than about 30:1, more than about 50:1, more than about 100:1, more than about 1000:1, more than about 10,000:1 or greater. In some embodiments no substantial amount of material is removed from the non-desired surface/material. In some embodiments, this ratio is cyclic etch process dependent.
  • the flow of the first or second reactant can be equal to or higher than 2 sccm, can be equal to or greater than 10 sccm or sometimes even higher than 50 sccm or can be more than 100 sccm or more than 500 sccm.
  • first reactant can be continuously flown into the reaction chamber while second reactant is flown intermittently.
  • a SiC dielectric layer is added onto a substrate such that the substrate has a dielectric top layer.
  • a surface oxide is removed from the dielectric layer by a thermal reaction in the first pre-clean process. This thermal reaction involves dipping the wafer in HF solution (100:1) for 5 min and drying.
  • the substrate is loaded into the reactor where the second dry etching process is performed.
  • the dry etching process comprises several rounds of H 2 plasma treatment and SF 6 radical treatment. After the dry etching process, the substrate has a superior etch profile and reduced sidewall roughness.
  • a dielectric SiCN substrate has a surface oxide layer. This surface oxide layer is removed by a pre-clean process involving a plasma-assisted process.
  • the plasma assisted process involves SF 6 radical treatment.
  • a dry etch process comprising repeated cycles of fluorine containing film (CxFy) film deposition by plasma process and plasma irradiation using fluorine ions and radicals is performed for twenty rounds.
  • the SiCN substrate has an enhanced etch selectivity relative to oxides and a consistent etch thickness per cycle of cyclic dry etching.
  • a dielectric coated substrate was treated as outlined in FIG. 3A , using H 2 and SF 6 plasma.
  • the first pre-cleaning process removed surface oxides from a Si 3 N 4 substrate by treating the Si 3 N 4 substrate with a SF 6 plasma.
  • the SF 6 plasma was from a capacitively coupled plasma (CCP) source and was be applied at 100 MHz, 100 W, 2 Pa, with 0 W bias.
  • CCP capacitively coupled plasma
  • the material was dry etched, as outlined in FIG. 3B (cyclic dry etch process of SiN using H 2 and SF 6 radicals (plasma)).
  • the dry etch process comprised treating the Si 3 N 4 substrate, after the first pre-cleaning process, with a H 2 plasma.
  • the H 2 plasma came from a CCP source and was applied at, 100 MHz, 100 W, 2 Pa, with 0 W bias.
  • the Si 3 N 4 substrate was cyclically treated by SF 6 radicals.
  • the SF 6 radicals came from a remote plasma source and was be applied at 2.45 GHz, 50 W, and 2 Pa.
  • FIG. 4 illustrates the resulting product as a comparison of the etched thickness of SiN with a pre-clean process and the etched thickness of SiN without a pre-clean process.
  • FIG. 5 illustrates the etched thickness of various dielectric materials.
  • the same conditions as described above for FIG. 4 were used for SiC, SiN, SiCOH & SiO atomic layer etching with pre-clean for the results shown in FIG. 5 .
  • the dielectric materials included SiO, SiN, SiC and SiCOH. All of these dielectric materials were deposited on a Si substrate by PECVD at around 300 C. A first pre-clean process was performed to remove surface oxide. A cyclic dry-etch was then performed on the pre-cleaned dielectric surface using H 2 plasma and fluorine radicals. After surface oxide removal, SiN, SiC and SiCOH substrates were etched. Selectivity of these substrates differed. The selectivity can be improved by changing bias, pressure or other conditions during the etching process. For SiO substrate, a cyclic dry etch process was not possible. This illustrates the selectivity versus oxides (SiO) after the surface oxide has been removed.
  • FIGS. 6A and 6B are STEM photographs that show the effect of the surface oxide removal on the uniformity and roughness of a dielectric film after two repetitions of a cyclic etch process.
  • FIG. 6A illustrates a Si 3 N 4 substrate's uniformity and surface roughness without pre-clean. The surface oxide was not removed prior to the cyclic etch process.
  • FIG. 6B illustrates a Si 3 N 4 substrate's uniformity and surface roughness with pre-clean. The surface oxide was removed by a fluorine plasma etch before initiating the cyclic etch process. With the pre-clean process, the Si 3 N 4 substrate as illustrated in FIG.
  • FIG. 6B showed a smooth surface and has improved etch uniformity and reduced sidewall roughness as compared to the Si 3 N 4 substrate as illustrated in FIG. 6A , which has not undergone a pre-clean process.
  • the Si 3 N 4 substrate in FIG. 6A shows a rough surface.
  • the SiN without pre-clean whose results are shown in FIG. 6A used a CCP SF 6 (50 W, 40 Pa, 0 W bias) plasma instead of a remote plasma to achieve etching of SiN even with native oxide present, but resulted in a very non-uniform etch. This is because at higher pressures >40 Pa and below 50 W the SF 6 CCP plasma was not as efficient in removing the surface oxide.
  • CCP SF 6 50 W, 40 Pa, 0 W bias
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