US10672646B2 - Method for fabricating a strained semiconductor-on-insulator substrate - Google Patents

Method for fabricating a strained semiconductor-on-insulator substrate Download PDF

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US10672646B2
US10672646B2 US16/301,260 US201716301260A US10672646B2 US 10672646 B2 US10672646 B2 US 10672646B2 US 201716301260 A US201716301260 A US 201716301260A US 10672646 B2 US10672646 B2 US 10672646B2
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layer
strained
substrate
monocrystalline semiconductor
bonding
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US20190181035A1 (en
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Walter Schwarzenbach
Guillaume Chabanne
Nicolas Daval
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Soitec SA
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Soitec SA
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI

Definitions

  • the present disclosure relates to a method for fabricating a strained semiconductor-on-insulator substrate, as well as such a substrate.
  • FDSOI monolithic for fully depleted silicon-on-insulator substrates feature a very thin (i.e., typically less than 50 nm thick) layer of silicon on a buried electrically insulating layer, the silicon layer potentially being used to form the channel of a CMOS transistor.
  • Strained silicon-on-insulator has been identified as a solution allowing the mobility of charge carriers in the silicon layer to be enhanced and good performance thereof has been demonstrated.
  • Document US 2014/0225160 discloses, in particular, a method allowing at least part of a strain present in a silicon-germanium layer located on the surface of a receiving substrate to be transferred to an initially relaxed silicon layer bonded to the receiving substrate via a dielectric layer that is intended to form the buried insulating layer of the SOI.
  • This strain transfer occurs when a portion of the stack is cut by means of trenches that extend into the receiving substrate at least beyond the strained silicon-germanium layer.
  • a relaxation of the compressive strain of the silicon-germanium layer is at least partially transmitted in the form of a tensile strain of the silicon layer.
  • an sSOI substrate can be manufactured according to the following steps:
  • the cutting operation results in the at least partial relaxation of the silicon-germanium and the transmission of at least part of the strain to the transferred silicon layer in the portion, thus allowing the strained semiconductor-on-insulator substrate, denoted by sSOI, to be formed.
  • the thickness of the buried dielectric layer should be less than or equal to 25 nm.
  • the final defectivity of the sSOI substrate heavily depends on the bonding conditions and, in particular, on the materials present at the bonding interface.
  • One aim of the present disclosure is to design a method for fabricating a strained semiconductor-on-insulator substrate that makes it possible to decrease the defectivity of the substrate linked to the conditions of bonding the donor substrate to the receiving layer.
  • a method for fabricating a strained semiconductor-on-insulator substrate comprises:
  • the present text is concerned with the strain in a plane parallel to the main surface of the layers in question.
  • the bonding layer formed on the receiving substrate allows materials providing optimum bonding quality in terms of final defectivity to be brought into contact at the bonding interface.
  • Another aim of the disclosure relates to a strained semiconductor-on-insulator substrate obtained by means of a method such as described above.
  • the substrate comprises, in succession, a strained monocrystalline semiconductor layer, an electrically insulating layer, an at least partially relaxed layer of the same material as the strained semiconductor layer, and a relaxed layer of a semiconductor material that differs from that of the strained semiconductor layer.
  • the thickness of the electrically insulating layer is less than or equal to 50 nm, preferably less than or equal to 25 nm, and the thickness of the at least partially relaxed layer of the same material as the strained semiconductor layer is between 1 nm and 20 nm.
  • FIGS. 1A to 1F schematically illustrate steps of a method for fabricating a strained silicon-on-insulator substrate leading to overly high defectivity
  • FIGS. 2A to 2G schematically illustrate steps of a method for fabricating a strained semiconductor-on-insulator substrate according to a first embodiment of the disclosure
  • FIGS. 3A to 3G schematically illustrate steps of a method for fabricating a strained semiconductor-on-insulator substrate according to a second embodiment of the disclosure.
  • FIGS. 4A to 4G schematically illustrate steps of a method for fabricating a strained semiconductor-on-insulator substrate according to a third embodiment of the disclosure.
  • a donor substrate comprises at least one monocrystalline semiconductor layer.
  • the substrate may be a bulk semiconductor substrate or a composite substrate, i.e., that consists of at least two layers of different materials including the monocrystalline semiconductor layer, which is arranged on the surface of the substrate.
  • the material of the monocrystalline semiconductor layer may be, in particular, silicon, germanium or silicon-germanium.
  • the monocrystalline semiconductor layer is in the relaxed state.
  • the monocrystalline semiconductor layer is covered by a dielectric layer.
  • the dielectric layer may be, in particular, a layer of an oxide or of a nitride of a semiconductor material.
  • the dielectric layer may be a silicon oxide (SiO 2 ) layer.
  • the dielectric layer will form all or part of the buried insulating layer of the strained semiconductor-on-insulator substrate.
  • the monocrystalline semiconductor layer is not covered by such a dielectric layer and it is the free surface thereof that forms the surface of the donor substrate.
  • a receiving substrate that comprises a surface layer of a strained semiconductor material is also provided.
  • the layer may be formed by epitaxy on a carrier substrate having a lattice parameter that differs from that of the material of the strained layer.
  • the strain in this layer may be, depending on the materials used and on the nature of the strain to which it is desired to subject the semiconductor layer of the strained semiconductor-on-insulator substrate, compressive or tensile.
  • the strained semiconductor material layer may be a silicon-germanium layer, formed by epitaxy on a silicon carrier substrate.
  • the germanium content of the layer is typically of the order of 20% to 40%, although these values are not limiting, the choice thereof potentially being made according to the thickness of the layer.
  • the strain in the silicon-germanium layer is compressive.
  • the monocrystalline semiconductor layer of the donor substrate should be transferred to the receiver substrate, this transfer comprising an operation of bonding the donor substrate to the receiver substrate, the monocrystalline semiconductor layer of the donor substrate and the strained semiconductor material layer being located on the bonding interface side.
  • a bonding layer is formed beforehand on the strained semiconductor material layer of the receiving substrate, which bonding layer allows materials providing optimum bonding quality in terms of final defectivity to be brought into contact at the bonding interface.
  • the bonding layer is a dielectric layer.
  • the bonding interface will consist of the first dielectric layer and of the bonding layer (referred to as the second dielectric layer).
  • the first and second dielectric layers thus together form the buried insulating layer of the final sSOI.
  • the bonding interface will consist of the monocrystalline semiconductor layer and of the bonding layer. It is then the bonding layer alone that forms the buried insulating layer of the final sSOI.
  • the bonding layer comprises an oxide or a nitride of a semiconductor material.
  • the bonding layer is formed by deposition on the strained semiconductor material layer of the receiving substrate. Any suitable deposition technique may be used. In a non-limiting manner, the vapor phase deposition variants known by the acronyms PE-CVD or PE-ALD may thus be cited.
  • the thickness of the bonding layer is chosen according to whether a first dielectric layer is present on the monocrystalline semiconductor layer of the donor substrate so as to obtain the desired thickness of the buried insulating layer, which is generally less than or equal to 50 nm, preferably less than or equal to 25 nm.
  • the thickness is also chosen while taking the thermal budget applied to the receiving substrate during the deposition of the layer into consideration, in order to limit the relaxation of the strain in the strained semiconductor material layer caused by this thermal budget.
  • the thermal budget should, therefore, be limited in order to avoid a substantial decrease in the strain and thus retain the strain that will be imparted to the monocrystalline semiconductor layer of the sSOI substrate.
  • the thickness of the bonding layer is typically between 1 nm and 30 nm.
  • the bonding layer consists of the same monocrystalline material, in the relaxed or partially relaxed state, as the monocrystalline semiconductor layer of the donor substrate.
  • the monocrystalline semiconductor layer is covered by a dielectric layer that will form the buried insulating layer of the sSOI substrate.
  • the bonding layer is formed by epitaxy on the strained semiconductor material layer, of the same semiconductor material as the monocrystalline semiconductor layer of the donor substrate.
  • the thickness of the bonding layer is advantageously chosen so that it is thin enough to offer the desired level of protection between the SiGe layer and the bonding interface, while taking, as in the preceding embodiment, the thermal budget applied to the receiving substrate during the deposition of the layer into consideration, in order to limit the relaxation of the strain in the strained semiconductor material layer caused by this thermal budget.
  • the thickness also takes into account the removal of material caused by the pre-bonding surface preparation treatment, which may include wet or dry etching.
  • the thickness of such a silicon bonding layer is between 1 nm and 20 nm.
  • the bonding interface makes either contact between two dielectric layers or contact between a dielectric layer and a layer of the same monocrystalline material, in the relaxed or partially relaxed state, as the monocrystalline semiconductor layer of the donor substrate.
  • the monocrystalline semiconductor layer is transferred to the receiving substrate.
  • the transfer involves the SMART CUT® method.
  • this transfer comprises:
  • the transfer involves thinning the donor substrate on its back face, i.e., the face opposite the bonding interface.
  • a thinning operation may involve one or more steps of dry or wet etching and/or polishing, especially chemical-mechanical polishing, etc.
  • the disclosure is not limited with respect to the transfer technique used.
  • the transferred semiconductor layer can undergo a finishing treatment allowing residual defects linked to the transfer process to be removed and the transferred monocrystalline semiconductor layer to be smoothed and thinned to the desired thickness.
  • This type of treatment is known to those skilled in the art and, as such, will not be described in detail here.
  • the final thickness of the monocrystalline semiconductor layer of the sSOI substrate is between 5 nm and 50 nm.
  • a portion of the stack consisting of the transferred semiconductor layer, of the buried insulating layer (which is formed, as disclosed above, from the bonding layer and/or from a dielectric layer of the donor substrate) and of the strained semiconductor material layer is cut in order to form the sSOI substrate.
  • the cutting operation is advantageously carried out by etching trench isolations around the portion.
  • the trenches should extend into the thickness of the receiving substrate beyond the strained semiconductor material layer.
  • the technique for fabricating the trenches is well known to those skilled in the art and, as such, does not need to be described in detail in the present text.
  • the resulting structure comprises, from its base to its surface, the carrier substrate, the initially strained semiconductor material layer, which is now in the relaxed state, the buried insulating layer and the transferred semiconductor monocrystalline layer, which is now in the strained state. If the bonding layer is made of a dielectric material, it forms at least part (or even all) of the buried insulating layer. If the bonding layer is made of the same material, in the relaxed or partially relaxed state, as the transferred semiconductor layer, the bonding layer is intercalated between the initially strained semiconductor material layer, which is now in the relaxed state, and the buried insulating layer.
  • an sSOI substrate obtained via the method illustrated in FIGS. 1A to 1F with the same cleaning, donor substrate preparation and bonding conditions exhibits, upon visual inspection, a much lower degree of defectivity, which results, in particular, in a substantial decrease in the number of holes corresponding to non-transferred zones of the monocrystalline semiconductor layer.
  • FIGS. 2A to 2G schematically illustrate steps of the fabrication of a strained semiconductor-on-insulator substrate according to one form of execution of the disclosure.
  • FIG. 2A illustrates the provision of the donor substrate 1 that, in this illustration, is a bulk substrate of a monocrystalline semiconductor material.
  • the substrate could be a composite and comprise, on one of its faces, a monocrystalline semiconductor layer.
  • the donor substrate 1 is covered by a dielectric layer 11 .
  • FIG. 2B illustrates the implementation of an implantation of ionic species into the donor substrate 1 so as to form a weakened zone 12 defining a monocrystalline semiconductor layer 13 to be transferred by means of the SMART CUT® method.
  • This step is optional, the transfer potentially being carried out by means of a method other than the SMART CUT® method, for example, by thinning the donor substrate on its back face.
  • FIG. 2C illustrates the provision of the receiving substrate 2 that comprises a surface layer 20 of a strained monocrystalline semiconductor material on a carrier substrate 21 .
  • FIG. 2D illustrates the formation of the dielectric bonding layer 22 that, in this case, consists of a dielectric material deposited on the strained monocrystalline semiconductor material layer 20 .
  • FIG. 2E illustrates the bonding of the donor substrate to the receiving substrate, the dielectric layers 11 and 22 together forming the buried insulating layer (referred to as a single layer 30 in the following figures) of the final strained semiconductor-on-insulator substrate.
  • the bonding interface is denoted by the reference I.
  • FIG. 2F illustrates the structure obtained after detaching the donor substrate along the weakened zone and, if applicable, after the transferred monocrystalline semiconductor layer 13 has undergone the finishing treatment.
  • the structure may be obtained by thinning the back face of the donor substrate up to the monocrystalline semiconductor layer 13 and smoothing the surface of the layer.
  • FIG. 2G illustrates the sSOI substrate obtained after cutting trenches T around the stack of layers 13 , 30 , 20 up to within the thickness of the carrier substrate 21 .
  • FIGS. 3A to 3G schematically illustrate steps of the fabrication of a strained semiconductor-on-insulator substrate according to another form of execution of the disclosure.
  • FIGS. 3A to 3C are similar to those of FIGS. 2A to 2C .
  • FIG. 3D illustrates the formation of a bonding layer 23 that, in this case, consists of the same material as that of the monocrystalline semiconductor layer 13 , in the relaxed or partially relaxed state, by epitaxy on the strained monocrystalline semiconductor material layer 20 .
  • FIGS. 3E to 3G are similar to those of FIGS. 2E to 2G , except in that the buried insulating layer of the sSOI substrate consists of the single dielectric layer 11 of the donor substrate, and that the bonding layer 23 is intercalated between the strained monocrystalline semiconductor material layer 20 and the buried insulating layer.
  • FIGS. 4A to 4G schematically illustrate steps of the fabrication of a strained semiconductor-on-insulator substrate according to another form of execution of the disclosure.
  • FIGS. 4A to 4C are similar to those of FIGS. 2A to 2C , except in that the donor substrate 1 is not covered by a dielectric layer. Stated otherwise, it is the semiconductor surface of the monocrystalline semiconductor layer 13 to be transferred that is exposed.
  • FIG. 4D illustrates the formation of a dielectric bonding layer 22 that, in this case, consists of a dielectric material deposited on the strained monocrystalline semiconductor material layer 20 .
  • FIGS. 4E to 4G are similar to those of FIGS. 2E to 2G , except in that the buried insulating layer of the sSOI substrate consists of the single dielectric bonding layer 22 .

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FR1654368 2016-05-17
FR1654368A FR3051595B1 (fr) 2016-05-17 2016-05-17 Procede de fabrication d'un substrat de type semi-conducteur contraint sur isolant
PCT/EP2017/061792 WO2017198686A1 (en) 2016-05-17 2017-05-17 Method for fabricating a strained semiconductor-on-insulator substrate

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CN (1) CN109155277B (ja)
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Cited By (1)

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WO2023049172A1 (en) 2021-09-22 2023-03-30 Acorn Semi, Llc MULTI-FINGER RF nFET HAVING BURIED STRESSOR LAYER AND ISOLATION TRENCHES BETWEEN GATES

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US10833194B2 (en) 2010-08-27 2020-11-10 Acorn Semi, Llc SOI wafers and devices with buried stressor
FR3051596B1 (fr) * 2016-05-17 2022-11-18 Soitec Silicon On Insulator Procede de fabrication d'un substrat de type semi-conducteur contraint sur isolant
US10903332B2 (en) 2018-08-22 2021-01-26 International Business Machines Corporation Fully depleted SOI transistor with a buried ferroelectric layer in back-gate
US10553474B1 (en) * 2018-08-29 2020-02-04 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a semiconductor-on-insulator (SOI) substrate

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Publication number Priority date Publication date Assignee Title
WO2023049172A1 (en) 2021-09-22 2023-03-30 Acorn Semi, Llc MULTI-FINGER RF nFET HAVING BURIED STRESSOR LAYER AND ISOLATION TRENCHES BETWEEN GATES

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FR3051595B1 (fr) 2022-11-18
CN109155277B (zh) 2023-10-24
TW201806074A (zh) 2018-02-16
TWI746555B (zh) 2021-11-21
EP3459106A1 (en) 2019-03-27
JP6888028B2 (ja) 2021-06-16
EP3459106B1 (en) 2023-07-19
EP3459106C0 (en) 2023-07-19
SG11201809911WA (en) 2018-12-28
JP2019521509A (ja) 2019-07-25
WO2017198686A1 (en) 2017-11-23
US20190181035A1 (en) 2019-06-13
FR3051595A1 (fr) 2017-11-24
CN109155277A (zh) 2019-01-04

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