TWM602761U - Chip-type switching device - Google Patents
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- TWM602761U TWM602761U TW109204680U TW109204680U TWM602761U TW M602761 U TWM602761 U TW M602761U TW 109204680 U TW109204680 U TW 109204680U TW 109204680 U TW109204680 U TW 109204680U TW M602761 U TWM602761 U TW M602761U
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
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Abstract
Description
本新型創作是有關於一種訊號切換裝置，且特別是有關於一種具備繼電器的多種切換操作的晶片型切換裝置。The present invention relates to a signal switching device, and in particular to a chip-type switching device with multiple switching operations with relays.
在訊號的傳輸運用上，切換裝置會被設計以執行訊號傳輸路徑或訊號切換。上述的需求也是本領域技術人員努力研究的課題之一。In the signal transmission application, the switching device will be designed to perform signal transmission path or signal switching. The above-mentioned requirements are also one of the subjects studied by those skilled in the art.
本新型創作提供一種具備多種切換操作的晶片型切換裝置。The present invention provides a chip-type switching device with multiple switching operations.
本新型創作的晶片型切換裝置包括至少一輸入腳墊、多個控制腳墊、多個輸出腳墊以及多個接地腳墊。輸入腳墊經配置以接收輸入訊號。所述多個控制腳墊分別經配置以接收多個控制訊號。晶片型切換裝置具備繼電器的多種操作，並受控於控制訊號來透過輸出腳墊輸出關聯於輸入訊號的輸出訊號。The chip-type switching device created by the present invention includes at least one input pad, a plurality of control pads, a plurality of output pads and a plurality of grounding pads. The input pad is configured to receive input signals. The plurality of control pads are respectively configured to receive a plurality of control signals. The chip-type switching device has multiple operations of the relay and is controlled by the control signal to output the output signal related to the input signal through the output pad.
基於上述，本新型創作的晶片型切換裝置能夠受控於控制訊號而具備繼電器的多種接點操作。Based on the above, the chip-type switching device of the present invention can be controlled by the control signal and has multiple contact operations of the relay.
為讓本新型創作的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the new creation more obvious and understandable, the following embodiments are specially cited, and the accompanying drawings are described in detail as follows.
請參考圖1，圖1是依據本新型創作的一實施例所繪示的晶片型切換裝置的腳墊配置示意圖。在本實施例中，晶片型切換裝置100具有4個側邊EG1~EG4以及平面PL。側邊EG1~EG4中各包括10個腳墊。平面PL上包括1個腳墊。然本新型創作並不以此為限。本實施例的多個腳墊分別以腳墊號碼(1)~(41)來表示。在本實施例中，設置於側邊EG1的10個腳墊分別以墊號碼(1)~(10)來表示。設置於側邊EG2的10個腳墊分別以腳墊號碼(11)~(20)來表示，依此類推。設置於平面PL上的腳墊以腳墊號碼(41)來表示。Please refer to FIG. 1, which is a schematic diagram of the pad configuration of the chip-type switching device according to an embodiment of the invention. In this embodiment, the wafer-
在本實施例中，晶片型切換裝置100被設計以包括輸入腳墊PIin（腳墊號碼(36)）、4個控制腳墊PVin1~PVin4（分別為腳墊號碼(23)、(26)、(5)、(8)）以及4個輸出腳墊PIo1~PIo4（分別為腳墊號碼(19)、(29)、(2)、(12)）。輸入腳墊PIin被設置於側邊EG4。輸入腳墊PIin接收輸入訊號Iin。在本實施例中，輸入訊號Iin可以是電流訊號，然本新型創作並不以此為限。在一些實施例中，輸入訊號Iin可以是電壓訊號。控制腳墊PVin1~PVin4分別接收控制訊號Vin1~Vin4。舉例來說，控制腳墊PVin1接收控制訊號Vin1。控制腳墊PVin2接收控制訊號Vin2，依此類推。在本實施例中，晶片型切換裝置100具備繼電器（relay）的多種接點操作，並依據控制訊號Vin1~Vin4來透過輸出腳墊PIo1~PIo4輸出關聯於輸入訊號Iin的輸出訊號Io1~Io4。在本實施例中，晶片型切換裝置100會依據控制訊號Vin1~Vin4而至少具備繼電器的A接點操作以及C接點操作的其中之一。由此可知，晶片型切換裝置100能夠依據控制訊號Vin1~Vin4而具備多種切換操作。In this embodiment, the chip-
在本實施例中，晶片型切換裝置100還包括多個接地腳墊GND。所述多個接地腳墊GND分別耦接至接地電位。所述多個接地腳墊GND中的多個第一接地腳墊GND1（分別為腳墊號碼(35)、(37)）分別被設置於輸入腳墊PIin的鄰近兩側。所述多個接地腳墊GND中的多個第二接地腳墊GND2（分別為腳墊號碼(4)、(6)、(7)、(9)、(22)、(24)、(25)、(27)）分別被設置於控制腳墊PVin1~PVin4的鄰近兩側。此外，所述多個接地腳墊GND中的第三接地腳墊GND3（分別為腳墊號碼(1)、(3)、(11)、(13)、(18)、(20)、(28)、(30)）分別被設置於輸出腳墊PIo1~PIo4的鄰近兩側。In this embodiment, the chip-
表1示出了本實施例的晶片型切換裝置100的腳墊配置。Table 1 shows the pad configuration of the wafer-
表1：
在此值得一提的是，在高頻的應用領域中，輸入腳墊PIin、控制腳墊PVin1~PVin4以及輸出腳墊PIo1~PIo4的其中二者能夠藉由接地腳墊GND中的其中二者間隔開。所述接地腳墊GND中的其中二者能夠有效屏蔽高頻訊號所造成的高頻干擾。如此一來，晶片型切換裝置100能夠具有較高的傳輸效率。It is worth mentioning here that in high-frequency applications, two of the input pads PIin, control pads PVin1~PVin4, and output pads PIo1~PIo4 can be grounded by two of the GND Spaced apart. Two of the grounding pads GND can effectively shield high-frequency interference caused by high-frequency signals. In this way, the chip-
在本實施例中，接地腳墊GND中的第四接地腳墊GND4（腳墊號碼(41)）。第四接地腳墊作為晶片型切換裝置100的主要接地腳墊。第四接地腳墊GND4被設置於晶片型切換裝置100的平面PL上。因此，接地腳墊GND的數量等於輸入腳墊PIin、控制腳墊PVin1~PVin4以及輸出腳墊PIo1~PIo4的總數的兩倍加1。基於本實施例的輸入腳墊PIin、控制腳墊PVin1~PVin4以及輸出腳墊PIo1~PIo4之間的腳墊數量比例，接地腳墊GND的數量可依據以下的公式一來獲得。In this embodiment, the fourth ground pad GND4 of the ground pads GND (foot pad number (41)). The fourth grounding pad serves as the main grounding pad of the chip-
N_GND=2×A×(N_Iin+4×N_Vin+4×N_Io)+1……（公式一）N_GND=2×A×(N_Iin+4×N_Vin+4×N_Io)+1……(Formula 1)
N_GND為接地腳墊GND的數量。A為輸入腳墊PIin的數量。以圖1的配置態樣為例，A等於1。N_Iin= N_Vin= N_Io= 1。因此基於公式一，接地腳墊GND的數量是19個。以其他的配置態樣上，A可以是2。接地腳墊GND的數量是37個。N_GND is the number of grounding pads GND. A is the number of input pads PIin. Taking the configuration of Figure 1 as an example, A is equal to 1. N_Iin= N_Vin= N_Io=1. Therefore, based on
在一些實施例中，在沒有第四接地腳墊GND4的情況下。接地腳墊GND的數量則可以依據以下的公式二來獲得。In some embodiments, there is no fourth ground pad GND4. The number of grounding pads GND can be obtained according to the following
N_GND=2×A×(N_Iin+4×N_Vin+4×N_Io)………（公式二）N_GND=2×A×(N_Iin+4×N_Vin+4×N_Io)………(Formula 2)
進一步舉例來說明，以側邊EG1為例，輸出腳墊PIo3的兩側鄰近腳墊（腳墊號碼(1)、(3)）被設計為第三接地腳墊GND3。控制腳墊PVin3的兩側鄰近腳墊（腳墊號碼(4)、(6)）被設計為第二接地腳墊GND2。控制腳墊PVin4的兩側鄰近腳墊（腳墊號碼(7)、(9)）被設計為第二接地腳墊GND2。輸出腳墊PIo3與控制腳墊PVin3之間具有用以接地的第二接地腳墊GND2以及第三接地腳墊GND3。控制腳墊PVin3與控制腳墊PVin4之間具有用以接地的第二接地腳墊GND2以及第三接地腳墊GND3。由此可知，晶片型切換裝置100會藉由兩個接地腳墊來屏蔽輸出腳墊PIo3與控制腳墊PVin3之間的高頻干擾。晶片型切換裝置100也會藉由兩個接地腳墊來屏蔽控制腳墊PVin3與控制腳墊PVin4之間的高頻干擾。To further illustrate, taking the side EG1 as an example, the adjacent pads (pad numbers (1), (3)) on both sides of the output pad PIo3 are designed as the third ground pad GND3. The adjacent foot pads on both sides of the control foot pad PVin3 (foot pad numbers (4), (6)) are designed as the second ground foot pad GND2. The adjacent pads on both sides of the control pad PVin4 (pad numbers (7), (9)) are designed as the second grounding pad GND2. The output pad PIo3 and the control pad PVin3 have a second ground pad GND2 and a third ground pad GND3 for grounding. A second grounding pad GND2 and a third grounding pad GND3 are provided between the control pad PVin3 and the control pad PVin4. It can be seen that the chip-
在本實施例中，控制腳墊PVin1~PVin4與輸出腳墊PIo2、PIo3被對稱地設置於晶片型切換裝置100不同於側邊EG4的相對兩側邊EG1、EG3。輸出腳墊PIo1、PIo4被對稱地設置於晶片型切換裝置100不同於側邊EG4的相對側邊EG2。舉例來說，被設置於側邊EG1的控制腳墊PVin3會與被設置於側邊EG3的控制腳墊PVin2對稱配置。被設置於側邊EG1的控制腳墊PVin4會與被設置於側邊EG3的控制腳墊PVin1對稱配置。被設置於側邊EG1的輸出腳墊PIo3會與被設置於側邊EG3的輸出腳墊PIo2對稱配置。被設置於側邊EG2的輸出腳墊PIo1、PIo4會被對稱配置。在本實施例中，被設置於側邊EG1的控制腳墊PVin3可用以接收第一控制訊號對的第一控制訊號，而同樣被設置於側邊EG1的控制腳墊PVin4可用以接收第一控制訊號對的第二控制訊號。相似地，被設置於側邊EG3的控制腳墊PVin1可用以接收第二控制訊號對的第一控制訊號，而同樣被設置於側邊EG3的控制腳墊PVin2可用以接收第二控制訊號對的第二控制訊號。也就是說，控制訊號Vin3、Vin4可以分別是第一控制訊號對的第一控制訊號以及第二控制訊號，而控制訊號Vin1、Vin2可以分別是第二控制訊號對的第一控制訊號以及第二控制訊號。In this embodiment, the control pads PVin1 to PVin4 and the output pads PIo2 and PIo3 are symmetrically arranged on opposite sides EG1 and EG3 of the chip-
接下來舉例說明晶片型切換裝置100的切換操作。請參考圖2以及表2，圖2是依據本新型創作的一實施例所繪示的晶片型切換裝置的操作示意圖。表2是本新型創作的一實施例的真值表。Next, the switching operation of the wafer-
表2：
在本實施例中，晶片型切換裝置100的輸入腳墊PIin接收輸入訊號Iin。控制腳墊PVin1接收控制訊號對的控制訊號Vin1。控制腳墊PVin2接收控制訊號對的另一控制訊號Vin2。控制腳墊PVin3、PVin4分別被電性連接到接地電位。表2所示出的真值表適用於單一輸入的晶片型切換裝置100。在本實施例中，晶片型切換裝置100能夠反應於控制訊號Vin1、Vin2的控制來決定輸出腳墊輸出腳墊PIo1~PIo4是否輸出輸出訊號Io1~Io4。In this embodiment, the input pad PIin of the chip-
舉例來說明，請同時參考圖2、3A、3B以及表2。圖3A、3B分別是依據本新型創作的一實施例所繪示的晶片型切換裝置執行C接點操作的操作示意圖。當控制訊號Vin1的邏輯準位為第一邏輯準位（例如是高邏輯準位「1」），並且控制訊號Vin2的邏輯準位為第二邏輯準位（例如是高邏輯準位「0」）時，晶片型切換裝置100會執行繼電器（relay）的C接點的「ON」操作，如圖3A所示。舉例來說，當控制訊號Vin1的邏輯準位為第一邏輯準位並且控制訊號Vin2的邏輯準位為第二邏輯準位時，晶片型切換裝置100會選擇出輸出腳墊PIo3、PIo4以作為選中輸出腳墊。因此，晶片型切換裝置100會藉由輸出腳墊PIo3、PIo4輸出輸出訊號Io3、Io4（在表二中被表示為「1」）。輸出訊號Io3、Io4實質上會關聯於Iin。未被選中的輸出腳墊PIo1、PIo2則不會輸出輸出訊號Io1、Io2（在表二中被表示為「0」）。For example, please refer to Figure 2, 3A, 3B and Table 2 at the same time. 3A and 3B are respectively schematic diagrams of the operation of the chip-type switching device according to an embodiment of the present invention to perform C-contact operations. When the logic level of the control signal Vin1 is the first logic level (for example, the high logic level "1"), and the logic level of the control signal Vin2 is the second logic level (for example, the high logic level "0") ), the chip-
當控制訊號Vin1的邏輯準位為第二邏輯準位，並且控制訊號Vin2的邏輯準位為第一邏輯準位時，晶片型切換裝置100會執行繼電器的C接點的「OFF」操作，如圖3B所示。舉例來說，當控制訊號Vin1的邏輯準位為第二邏輯準位並且控制訊號Vin2的邏輯準位為第一邏輯準位時，晶片型切換裝置100會選擇出輸出腳墊PIo1、PIo2以作為選中輸出腳墊。因此，晶片型切換裝置100會藉由輸出腳墊PIo1、PIo2輸出輸出訊號Io1、Io2。輸出訊號Io1、Io2實質上會關聯於Iin。未被選中的輸出腳墊PIo3、PIo4則不會輸出輸出訊號Io3、Io4。When the logic level of the control signal Vin1 is the second logic level, and the logic level of the control signal Vin2 is the first logic level, the chip-
另舉例來說明，請同時參考圖2、3C、3D以及表2。圖3C、3D分別是依據本新型創作的一實施例所繪示的晶片型切換裝置執行A接點操作的操作示意圖。當控制訊號Vin1、Vin2的邏輯準位都為第二邏輯準位時，晶片型切換裝置100會執行繼電器的A接點的「OFF」操作，如圖3C所示。舉例來說，當控制訊號Vin1、Vin2的邏輯準位都為第二邏輯準位時，晶片型切換裝置100不會將輸出腳墊PIo1~PIo4作為選中輸出腳墊。因此，晶片型切換裝置100不會藉由輸出腳墊PIo1~PIo4輸出輸出訊號Io1~Io4。For another example, please refer to Figure 2, 3C, 3D and Table 2 at the same time. 3C and 3D are respectively schematic diagrams of the operation of performing A contact operation of the chip-type switching device according to an embodiment of the invention. When the logic levels of the control signals Vin1 and Vin2 are both at the second logic level, the chip-
當控制訊號Vin1、Vin2的邏輯準位都為第一邏輯準位時，晶片型切換裝置100會執行繼電器的A接點的「ON」操作，如圖3D所示。舉例來說，當控制訊號Vin1、Vin2的邏輯準位都為第一邏輯準位時，晶片型切換裝置100會將輸出腳墊PIo1~PIo4作為選中輸出腳墊。因此，晶片型切換裝置100會藉由輸出腳墊PIo1~PIo4輸出輸出訊號Io1~Io4。輸出訊號Io1、Io2實質上會關聯於Iin。When the logic levels of the control signals Vin1 and Vin2 are both at the first logic level, the chip-
基於上述的教示，晶片型切換裝置100受控於控制訊號Vin1、Vin2以在繼電器的A接點操作以及C接點操作之間進行切換。也就是說，晶片型切換裝置100受控於控制訊號Vin1、Vin2以執行繼電器的A接點操作以及C接點操作的其中之一。Based on the above teaching, the chip-
在本新型創作中，表二所示出的真值表也適用於兩個晶片型切換裝置。舉例來說明，請同時參考表二以及圖4，圖4是依據本新型創作的一實施例所繪示的多個晶片型切換裝置的操作示意圖。在本實施例中，圖4示出了晶片型切換裝置100_1、100_2的操作範例。晶片型切換裝置100_1、100_2分別例如是由圖1的晶片型切換裝置100來實現。晶片型切換裝置100_1的輸入腳墊PIin接收輸入訊號Iin1。晶片型切換裝置100_2的輸入腳墊PIin接收輸入訊號Iin2。輸入訊號Iin1不同於輸入訊號Iin2。晶片型切換裝置100_1的控制腳墊PVin1以及晶片型切換裝置100_2的控制腳墊PVin1共同接收控制訊號對的控制訊號Vin1。晶片型切換裝置100_1的控制腳墊PVin2以及晶片型切換裝置100_2的控制腳墊PVin2接收控制訊號對的另一控制訊號Vin2。晶片型切換裝置100_1的控制腳墊PVin3、PVin4以及晶片型切換裝置100_2的控制腳墊PVin3、PVin4分別被電性連接到接地電位。此外，晶片型切換裝置100_1的輸出腳墊PIo2、PIo3以及晶片型切換裝置100_2的輸出腳墊PIo2、PIo3分別被電性連接到接地電位。In the present invention, the truth table shown in Table 2 is also applicable to two chip-type switching devices. For example, please refer to Table 2 and FIG. 4 at the same time. FIG. 4 is a schematic diagram of the operation of multiple chip-type switching devices according to an embodiment of the present invention. In this embodiment, FIG. 4 shows an operation example of the chip-type switching devices 100_1 and 100_2. The chip-type switching devices 100_1 and 100_2 are respectively implemented by, for example, the chip-
當控制訊號Vin1的邏輯準位為第一邏輯準位（例如是高邏輯準位「1」），並且控制訊號Vin2的邏輯準位為第二邏輯準位（例如是高邏輯準位「0」）時，晶片型切換裝置100會執行繼電器的C接點的「ON」操作。舉例來說，當控制訊號Vin1的邏輯準位為第一邏輯準位並且控制訊號Vin2的邏輯準位為第二邏輯準位時，晶片型切換裝置100_1會選擇出輸出腳墊PIo1作為選中輸出腳墊，藉以輸出輸出訊號Io3。晶片型切換裝置100_2會選擇出輸出腳墊PIo4作為選中輸出腳墊，藉以輸出輸出訊號Io4。輸出訊號Io3實質上會關聯於Iin1。輸出訊號Io4實質上會關聯於Iin2。也就是說，輸出訊號Io3、Io4實質上會關聯於相異的輸入訊號Iin1、Iin2。晶片型切換裝置100_1會選擇出輸出腳墊PIo4不會輸出輸出訊號Io1。晶片型切換裝置100_2會選擇出輸出腳墊PIo1也不會輸出輸出訊號Io2。When the logic level of the control signal Vin1 is the first logic level (for example, the high logic level "1"), and the logic level of the control signal Vin2 is the second logic level (for example, the high logic level "0") ), the chip-
當控制訊號Vin1的邏輯準位為第二邏輯準位，並且控制訊號Vin2的邏輯準位為第一邏輯準位時，晶片型切換裝置100_1、100_2會共同執行繼電器的C接點的「OFF」操作。舉例來說，當控制訊號Vin1的邏輯準位為第二邏輯準位並且控制訊號Vin2的邏輯準位為第一邏輯準位時，晶片型切換裝置100_1會選擇出輸出腳墊PIo4作為選中輸出腳墊，藉以輸出輸出訊號Io1。晶片型切換裝置100_2會選擇出輸出腳墊PIo1作為選中輸出腳墊，藉以輸出輸出訊號Io2。輸出訊號Io1實質上會關聯於Iin1。輸出訊號Io2實質上會關聯於Iin2。晶片型切換裝置100_1會選擇出輸出腳墊PIo1不會輸出輸出訊號Io3。晶片型切換裝置100_2會選擇出輸出腳墊PIo4也不會輸出輸出訊號Io4。When the logic level of the control signal Vin1 is the second logic level and the logic level of the control signal Vin2 is the first logic level, the chip-type switching devices 100_1 and 100_2 will jointly perform the "OFF" of the C contact of the relay operating. For example, when the logic level of the control signal Vin1 is the second logic level and the logic level of the control signal Vin2 is the first logic level, the chip-type switching device 100_1 will select the output pad PIo4 as the selected output Foot pad to output the output signal Io1. The chip-type switching device 100_2 selects the output pad PIo1 as the selected output pad, thereby outputting the output signal Io2. The output signal Io1 is essentially related to Iin1. The output signal Io2 is essentially related to Iin2. The chip type switching device 100_1 selects the output pad PIo1 and does not output the output signal Io3. The chip-type switching device 100_2 selects the output pad PIo4 and does not output the output signal Io4.
當控制訊號Vin1、Vin2的邏輯準位都為第二邏輯準位時，晶片型切換裝置100_1、100_2會共同執行繼電器的A接點的「OFF」操作。舉例來說，當控制訊號Vin1、Vin2的邏輯準位都為第二邏輯準位時，晶片型切換裝置100_1不會將輸出腳墊PIo1、PIo4作為選中輸出腳墊。晶片型切換裝置100_2也不會將輸出腳墊PIo1、PIo4作為選中輸出腳墊。因此，晶片型切換裝置100_1、100_2兩者不會藉由輸出腳墊PIo1、PIo4輸出輸出訊號Io1~Io4。When the logic levels of the control signals Vin1 and Vin2 are both at the second logic level, the chip-type switching devices 100_1 and 100_2 will jointly perform the "OFF" operation of the A contact of the relay. For example, when the logic levels of the control signals Vin1 and Vin2 are both at the second logic level, the chip-type switching device 100_1 will not use the output pads PIo1 and PIo4 as selected output pads. The chip-type switching device 100_2 also does not use the output pads PIo1 and PIo4 as selected output pads. Therefore, the chip-type switching devices 100_1 and 100_2 will not output the output signals Io1 to Io4 through the output pads PIo1 and PIo4.
當控制訊號Vin1、Vin2的邏輯準位都為第一邏輯準位時，晶片型切換裝置100_1、100_2會共同執行繼電器的A接點的「ON」操作。舉例來說，當控制訊號Vin1、Vin2的邏輯準位都為第一邏輯準位時，晶片型切換裝置100_1、100_2兩者會將輸出腳墊PIo1、PIo4作為選中輸出腳墊。因此，晶片型切換裝置100_1、100_2兩者會藉由輸出腳墊PIo1、PIo4輸出輸出訊號Io1~Io4。輸出訊號Io1、Io3實質上會關聯於Iin1。輸出訊號Io2、Io4實質上會關聯於Iin2。也就是說，輸出訊號Io1~Io4實質上會關聯於相異的輸入訊號Iin1、Iin2。When the logic levels of the control signals Vin1 and Vin2 are both at the first logic level, the chip-type switching devices 100_1 and 100_2 will jointly perform the "ON" operation of the A contact of the relay. For example, when the logic levels of the control signals Vin1 and Vin2 are both at the first logic level, both chip-type switching devices 100_1 and 100_2 will use the output pads PIo1 and PIo4 as selected output pads. Therefore, both the chip-type switching devices 100_1 and 100_2 output output signals Io1 to Io4 through the output pads PIo1 and PIo4. The output signals Io1 and Io3 are essentially related to Iin1. The output signals Io2 and Io4 are essentially related to Iin2. In other words, the output signals Io1 to Io4 are substantially related to the different input signals Iin1 and Iin2.
接下來介紹晶片型切換裝置的製作。請參考圖5，圖5是依據本新型創作的一實施例所繪示的多個晶片型切換裝置被製作於同一基板的示意圖。在本實施例中，2 N個晶片型切換裝置100_1~100_4是以晶片(chip或die)製作流程被製作於同一基板SB上。N為正整數。為了便於說明，本實施例以N等於2為範例。在另一些實施例中，N 2個晶片型切換裝置以陣列的佈局方式被製作於同一基板SB上。本實施例的基板SB例如是矽晶圓，然本新型創作並不以基板的材料、類型為限。 Next, the production of the wafer-type switching device is introduced. Please refer to FIG. 5. FIG. 5 is a schematic diagram of a plurality of chip-type switching devices produced on the same substrate according to an embodiment of the present invention. In this embodiment, 2 N chip-type switching devices 100_1 to 100_4 are fabricated on the same substrate SB in a chip or die fabrication process. N is a positive integer. For ease of description, this embodiment takes N equal to 2 as an example. In other embodiments, N 2 chip-type switching devices are fabricated on the same substrate SB in an array layout. The substrate SB of this embodiment is, for example, a silicon wafer, but the invention of the present invention is not limited to the material and type of the substrate.
在本實施例中，2 N個晶片型切換裝置100_1~100_4以單一個晶片型切換裝置為單位被進行適當的切割。被切割下來的晶片型切換裝置100_1~100_4會被設置於相同或不同載體上。載體可以是電路硬板、軟性印刷電路板、軟硬複合板。本新型創作並不以載體的材料、類型為限。在本實施例中，晶片型切換裝置100_1為例，被設置於載體上的晶片型切換裝置100_1被鋪設封裝膠體。晶片型切換裝置100_1的輸入腳墊、控制腳墊、輸出腳墊以及接地腳墊則外露於封裝膠體。 In this embodiment, 2 N wafer-type switching devices 100_1 to 100_4 are appropriately diced in units of a single wafer-type switching device. The chip-type switching devices 100_1 to 100_4 that have been cut will be arranged on the same or different carriers. The carrier can be a rigid circuit board, a flexible printed circuit board, and a flexible and rigid composite board. The new creation is not limited to the material and type of the carrier. In this embodiment, the chip-type switching device 100_1 is taken as an example, and the chip-type switching device 100_1 arranged on the carrier is coated with packaging glue. The input pads, control pads, output pads and grounding pads of the chip-type switching device 100_1 are exposed to the packaging compound.
請參考圖6A，圖6A是依據本新型創作一實施例所繪示的多個抗靜電放電（Electrostatic Discharge，ESD）元件的配置示意圖。在本實施例中，以晶片型切換裝置100_3抗ESD元件110_1~110_5在上述晶片製作流程中被分別製作於晶片型切換裝置100_3內，使得抗ESD元件110_1~110_5分別與晶片型切換裝置100_3的輸入腳墊PIin以及輸出腳墊PIo1~PIo4耦接。進一步來說，輸入腳墊PIin以及輸出腳墊PIo1~PIo4會分別與抗ESD元件110_1~110_5並聯耦接。舉例來說，抗ESD元件110_1與輸入腳墊PIin並聯耦接。抗ESD元件110_2與輸出腳墊PIo1並聯耦接。抗ESD元件110_3與輸出腳墊PIo2並聯耦接，依此類推。如此一來，輸入腳墊PIin以及輸出腳墊PIo1~PIo4可避免受到靜電放電的破壞。Please refer to FIG. 6A. FIG. 6A is a schematic diagram of the configuration of multiple Electrostatic Discharge (ESD) components according to an embodiment of the present invention. In this embodiment, the anti-ESD elements 110_1~110_5 of the chip-type switching device 100_3 are respectively fabricated in the chip-type switching device 100_3 in the above-mentioned chip manufacturing process, so that the anti-ESD elements 110_1~110_5 are respectively the same as those of the chip-type switching device 100_3. The input pad PIin and the output pads PIo1~PIo4 are coupled. Furthermore, the input pads PIin and the output pads PIo1~PIo4 are respectively coupled in parallel with the anti-ESD components 110_1~110_5. For example, the anti-ESD element 110_1 is coupled in parallel with the input pad PIin. The anti-ESD element 110_2 is coupled in parallel with the output pad PIo1. The anti-ESD component 110_3 is coupled in parallel with the output pad PIo2, and so on. In this way, the input pad PIin and the output pads PIo1~PIo4 can avoid being damaged by electrostatic discharge.
請參考圖6B，圖6B是依據本新型創作另一實施例所繪示的多個抗靜電放電元件的配置示意圖。在本實施例中，抗ESD元件110_1~110_5可以被設計以製作在載板上，使得抗ESD元件110_1~110_5分別從晶片型切換裝置100_3的外部與晶片型切換裝置100_3的輸入腳墊PIin以及輸出腳墊PIo1~PIo4耦接。進一步來說，輸入腳墊PIin以及輸出腳墊PIo1~PIo4會分別與抗ESD元件110_1~110_5並聯耦接。舉例來說，抗ESD元件110_1與輸入腳墊PIin並聯耦接。抗ESD元件110_2與輸出腳墊PIo1並聯耦接。抗ESD元件110_3與輸出腳墊PIo2並聯耦接，依此類推。Please refer to FIG. 6B. FIG. 6B is a schematic diagram showing the configuration of a plurality of anti-static discharge elements according to another embodiment of the present invention. In this embodiment, the anti-ESD elements 110_1~110_5 can be designed to be fabricated on a carrier board, so that the anti-ESD elements 110_1~110_5 are respectively from the outside of the chip-type switching device 100_3 and the input pad PIin and the chip-type switching device 100_3 The output pads PIo1~PIo4 are coupled. Furthermore, the input pads PIin and the output pads PIo1~PIo4 are respectively coupled in parallel with the anti-ESD components 110_1~110_5. For example, the anti-ESD element 110_1 is coupled in parallel with the input pad PIin. The anti-ESD element 110_2 is coupled in parallel with the output pad PIo1. The anti-ESD component 110_3 is coupled in parallel with the output pad PIo2, and so on.
請參考圖7，圖7是依據本新型創作另一實施例所繪示的晶片型切換裝置的腳墊配置示意圖。在本實施例中，晶片型切換裝置200具有4個側邊EG1~EG4以及平面PL。側邊EG1~EG4中各包括8個腳墊。平面PL上包括1個腳墊。本實施例的多個腳墊分別以腳墊號碼(1)~(33)來表示。在本實施例中，設置於側邊EG1的8個腳墊分別以墊號碼(1)~(8)來表示。設置於側邊EG2的8個腳墊分別以腳墊號碼(9)~(16)來表示，依此類推。設置於平面PL上的腳墊以腳墊號碼(33)來表示。Please refer to FIG. 7, which is a schematic diagram of the pad configuration of a chip-type switching device according to another embodiment of the present invention. In this embodiment, the wafer-
在本實施例中，晶片型切換裝置200被設計以包括輸入腳墊PIin（腳墊號碼(29)）、4個控制腳墊PVin1~PVin4（分別為腳墊號碼(5)、(7)、(18)、(20)）以及4個輸出腳墊PIo1~PIo4（分別為腳墊號碼(2)、(10)、(15)、(23)）。其餘的腳墊被設計以作為接地腳墊。在本實施例中，被設置於晶片型切換裝置200的同一側邊的輸入腳墊PIin、控制腳墊PVin1~PVin4以及輸出腳墊PIo1~PIo4的其中二者會被至少一個接地腳墊GND間隔開。舉例來說，在側邊EG1，輸出腳墊PIo3與控制腳墊PVin3被2個接地腳墊GND間隔開。控制腳墊PVin3、PVin4被1個接地腳墊GND間隔開。在側邊EG2，輸出腳墊PIo1、PIo4被4個接地腳墊GND間隔開。在側邊EG3，輸出腳墊PIo2與控制腳墊PVin2被2個接地腳墊GND間隔開。控制腳墊PVin1、PVin2被1個接地腳墊GND間隔開。In this embodiment, the chip-
相似於晶片型切換裝置100，在本實施例中，控制腳墊PVin1~PVin4與輸出腳墊PIo2、PIo3被對稱地設置於晶片型切換裝置200不同於側邊EG4的相對兩側邊EG1、EG3。輸出腳墊PIo1、PIo4被對稱地設置於晶片型切換裝置100不同於側邊EG4的相對側邊EG2。Similar to the chip-
表2示出了本實施例的晶片型切換裝置200的腳墊配置。Table 2 shows the pad configuration of the wafer-
表2：
在本實施例中，輸入腳墊PIin、控制腳墊PVin1~PVin4以及輸出腳墊PIo1~PIo4的實施方式以及晶片型切換裝置200的操作方式可以由圖1至圖4的多個實施例中獲致足夠的教示，因此恕不再次重述。在本實施例中，晶片型切換裝置200能夠具備繼電器的多種接點操作，並依據控制訊號Vin1~Vin4來透過輸出腳墊PIo1~PIo4輸出關聯於輸入訊號Iin的輸出訊號Io1~Io4。In this embodiment, the implementation of the input pads PIin, the control pads PVin1~PVin4, and the output pads PIo1~PIo4 and the operation mode of the chip-
請參考圖8，圖8是依據本新型創作再一實施例所繪示的晶片型切換裝置的腳墊配置示意圖。在本實施例中，晶片型切換裝置300具有側邊EG1、EG2以及平面PL。側邊EG1、EG2彼此相對。側邊EG1、EG2中各包括10個腳墊。平面PL上包括1個腳墊。本實施例的多個腳墊分別以腳墊號碼(1)~(21)來表示。在本實施例中，設置於側邊EG2的10個腳墊分別以墊號碼(1)~(10)來表示。設置於側邊EG1的10個腳墊分別以腳墊號碼(11)~(20)來表示。設置於平面PL上的腳墊則以腳墊號碼(21)來表示。Please refer to FIG. 8. FIG. 8 is a schematic diagram of the pad configuration of the chip-type switching device according to another embodiment of the present invention. In this embodiment, the wafer-
在本實施例中，晶片型切換裝置300被設計以包括2個輸入腳墊PIin1、PIin2（腳墊號碼(14)、(17)）、2個控制腳墊PVin1、PVin2（分別為腳墊號碼(11)、(20)）以及4個輸出腳墊PIo1~PIo4（分別為腳墊號碼(2)、(4)、(7)、(9)）。其餘的腳墊被設計以作為接地腳墊。在本實施例中，輸入腳墊PIin1、PIin2與控制腳墊PVin1、PVin2被對稱地設置於在側邊EG1。輸出腳墊PIo1~PIo4被對稱地設置於側邊EG2。在本實施例中，被設置於晶片型切換裝置300的側邊EG1的輸入腳墊PIin1、PIin2與控制腳墊PVin1、PVin2彼此間會被至少一個接地腳墊GND間隔開。被設置於晶片型切換裝置300的側邊EG2的輸出腳墊PIo1~PIo4會被至少一個接地腳墊GND間隔開。舉例來說，在側邊EG1，輸入腳墊PIin1、PIin2與控制腳墊PVin1、PVin2彼此間會被2個接地腳墊GND間隔開。在側邊EG2，輸出腳墊PIo1、PIo2被1個接地腳墊GND間隔開。輸出腳墊PIo2、PIo3被2個接地腳墊GND間隔開。輸出腳墊PIo3、PIo4被1個接地腳墊GND間隔開。In this embodiment, the chip-
表3示出了本實施例的晶片型切換裝置300的腳墊配置。Table 3 shows the pad configuration of the wafer-
表3：
在本實施例中，輸入腳墊PIin1、PIin2、控制腳墊PVin1、PVin2以及輸出腳墊PIo1~PIo4的實施方式以及晶片型切換裝置300的操作方式可以由圖1至圖4的多個實施例中獲致足夠的教示，因此恕不再次重述。在本實施例中，晶片型切換裝置300能夠具備繼電器的多種接點操作，並依據控制訊號Vin1、Vin2來透過輸出腳墊PIo1~PIo4輸出關聯於輸入訊號Iin1、Iin2的輸出訊號Io1~Io4。In this embodiment, the implementation of the input pads PIin1, PIin2, the control pads PVin1, PVin2, and the output pads PIo1~PIo4 and the operation mode of the chip-
綜上所述，本新型創作的晶片型切換裝置能夠依據控制訊號執行多種切換操作。在高頻的應用領域中，輸入腳墊、控制腳墊以及輸出腳墊的其中二者能夠藉由接地腳墊中的其中二者間隔開。所述接地腳墊中的其中二者能夠有效屏蔽高頻訊號所造成的高頻干擾。如此一來，晶片型切換裝置能夠具有較高的傳輸效率。除此之外，輸入腳墊以及所述多個輸出腳墊會分別配置抗靜電放電元件。如此一來，輸入腳墊以及輸出腳墊可避免受到靜電放電的破壞。因此，本新型創作的晶片型切換裝置不但可執行多種切換操作，還具有較佳的可靠度。In summary, the chip-type switching device created by the present invention can perform various switching operations according to the control signal. In the high-frequency application field, two of the input foot pad, the control foot pad, and the output foot pad can be separated by two of the ground foot pads. Two of the grounding pads can effectively shield high-frequency interference caused by high-frequency signals. As a result, the chip-type switching device can have higher transmission efficiency. In addition, the input pads and the multiple output pads are respectively equipped with anti-static discharge components. In this way, the input pads and the output pads can be prevented from being damaged by electrostatic discharge. Therefore, the chip-type switching device created by the present invention can not only perform multiple switching operations, but also has better reliability.
雖然本新型創作已以實施例揭露如上，然其並非用以限定本新型創作，任何所屬技術領域中具有通常知識者，在不脫離本新型創作的精神和範圍內，當可作些許的更動與潤飾，故本新型創作的保護範圍當視後附的申請專利範圍所界定者為準。Although the creation of this new type has been disclosed in the above embodiments, it is not intended to limit the creation of this new type. Anyone with ordinary knowledge in the technical field can make some changes and changes without departing from the spirit and scope of the new creation. Retouching, therefore, the scope of protection of the creation of the new model shall be subject to the scope of the attached patent application.
(1)~(41):腳墊號碼
100、100_1、100_2、100_3、100_4、200、300:晶片型切換裝置
110_1、110_2、110_3、110_4、110_5:抗靜電放電元件
EG1、EG2、EG3、EG4:側邊
GND:接地腳墊
GND1:第一接地腳墊
GND2:第二接地腳墊
GND3:第三接地腳墊
GND4:第四接地腳墊
Iin、Iin1、Iin2:輸入訊號
Io1、Io2、Io3、Io4:輸出訊號
PIin:輸入腳墊
PIo1、PIo2、PIo3、PIo4:輸出腳墊
PL:平面
PVin1、PVin2、PVin3、PVin4:控制腳墊
SB:基板
Vin1、Vin2、Vin3、Vin4:控制訊號
(1)~(41):
圖1是依據本新型創作的一實施例所繪示的晶片型切換裝置的腳墊配置示意圖。 圖2是依據本新型創作的一實施例所繪示的晶片型切換裝置的操作示意圖。 圖3A、3B分別是依據本新型創作的一實施例所繪示的晶片型切換裝置執行C接點操作的操作示意圖。 圖3C、3D分別是依據本新型創作的一實施例所繪示的晶片型切換裝置執行A接點操作的操作示意圖。 圖4是依據本新型創作的一實施例所繪示的多個晶片型切換裝置的操作示意圖。 圖5是依據本新型創作的一實施例所繪示的多個晶片型切換裝置被製作於同一基板的示意圖。 圖6A是依據本新型創作一實施例所繪示的多個抗靜電放電元件的配置示意圖。 圖6B是依據本新型創作另一實施例所繪示的多個抗靜電放電元件的配置示意圖。 圖7是依據本新型創作另一實施例所繪示的晶片型切換裝置的腳墊配置示意圖。 圖8是依據本新型創作再一實施例所繪示的晶片型切換裝置的腳墊配置示意圖。 FIG. 1 is a schematic diagram of the foot pad configuration of a chip-type switching device according to an embodiment of the invention. 2 is a schematic diagram of the operation of the chip-type switching device according to an embodiment of the present invention. 3A and 3B are respectively schematic diagrams of the operation of the chip-type switching device according to an embodiment of the present invention to perform C-contact operations. 3C and 3D are respectively schematic diagrams of the operation of performing A contact operation of the chip-type switching device according to an embodiment of the invention. FIG. 4 is a schematic diagram of the operation of multiple chip-type switching devices according to an embodiment of the invention. FIG. 5 is a schematic diagram of a plurality of chip-type switching devices drawn on the same substrate according to an embodiment of the invention. FIG. 6A is a schematic diagram showing the configuration of a plurality of anti-static discharge elements according to an embodiment of the invention. FIG. 6B is a schematic diagram showing the configuration of a plurality of anti-static discharge elements according to another embodiment of the invention. FIG. 7 is a schematic diagram of the foot pad configuration of a chip-type switching device according to another embodiment of the invention. FIG. 8 is a schematic diagram of the foot pad configuration of the chip-type switching device according to another embodiment of the invention.
(1)~(41):腳墊號碼 (1)~(41): Foot pad number
100:晶片型切換裝置 100: Wafer type switching device
EG1、EG2、EG3、EG4:側邊 EG1, EG2, EG3, EG4: side
GND:接地腳墊 GND: Grounding pad
GND1:第一接地腳墊 GND1: the first grounding pad
GND2:第二接地腳墊 GND2: second grounding pad
GND3:第三接地腳墊 GND3: third grounding pad
GND4:第四接地腳墊 GND4: Fourth grounding pad
Iin:輸入訊號 Iin: Input signal
Io1、Io2、Io3、Io4:輸出訊號 Io1, Io2, Io3, Io4: output signal
PIin:輸入腳墊 PIin: input foot pad
PIo1、PIo2、PIo3、PIo4:輸出腳墊 PIo1, PIo2, PIo3, PIo4: output pad
PL:平面 PL: plane
PVin1、PVin2、PVin3、PVin4:控制腳墊 PVin1, PVin2, PVin3, PVin4: control foot pad
Vin1、Vin2、Vin3、Vin4:控制訊號 Vin1, Vin2, Vin3, Vin4: control signal
Claims (10)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021104013.0U CN212181278U (en) | 2019-12-17 | 2020-06-15 | Chip type switching device |
| KR1020200156949A KR102517409B1 (en) | 2019-12-17 | 2020-11-20 | Chip-type switching device |
| JP2020005288U JP3234113U (en) | 2019-12-17 | 2020-12-07 | Chip type switching device |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201962948821P | 2019-12-17 | 2019-12-17 | |
| US62/948,821 | 2019-12-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TWM602761U true TWM602761U (en) | 2020-10-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW109204680U TWM602761U (en) | 2019-12-17 | 2020-04-21 | Chip-type switching device |
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| JP (1) | JP3234113U (en) |
| KR (1) | KR102517409B1 (en) |
| TW (1) | TWM602761U (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08172163A (en) * | 1994-12-19 | 1996-07-02 | Matsushita Electric Ind Co Ltd | One-input/multi-output switch and multi-input/one-output switch |
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2020
- 2020-04-21 TW TW109204680U patent/TWM602761U/en unknown
- 2020-11-20 KR KR1020200156949A patent/KR102517409B1/en active IP Right Grant
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| JP3234113U (en) | 2021-09-24 |
| KR20210078395A (en) | 2021-06-28 |
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