JP2013021249A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit in which the ESD protection circuit between different types of power supply between a common discharge path can be disposed closely to the pads of respective power supplies.SOLUTION: A semiconductor integrated circuit 1 includes an I/O cell IOC1 for power supply having a pad P, and an ESD protection circuit ESD1 for the power supply and being used for power supply of a VDDc system, and an I/O cell IOC2 for power supply having a pad P, an ESD protection circuit ESD1 for the power supply, and an ESD protection circuit ESD2 between different types of power supply and being used for power supply of VDDa, VDDb systems. The I/O cells IOC1 and IOC2 for power supply having external dimensions identical to those of the I/O cell IOC100 for signal input/output are arranged in the same row as the IOC100 arranged in row. A common discharge path CDL being connected with the ESD protection circuit ESD2 between different types of power supply of the I/O cell IOC2 for power supply penetrates the IOC100 arranged in row from the I/O cell IOC1 for power supply, and is wired to the I/O cell IOC2 for power supply.

Description

  Embodiments described herein relate generally to a semiconductor integrated device.

  2. Description of the Related Art Recent semiconductor integrated devices tend to be equipped with a plurality of internal circuits with different power supply systems due to progress in SoC (System On Chip), miniaturization of manufacturing processes, low power consumption, and the like.

  In a semiconductor integrated device including internal circuits driven from a plurality of power supply systems, in addition to providing a “self-power supply ESD protection circuit” for each power supply system, “ESD protection between different power supply systems” The “circuit” is inserted. Therefore, as the number of power supply systems increases, the number of ESD protection circuits between different power supply systems also increases. Therefore, in order to configure an ESD protection circuit insertion path between different power supply systems effectively and with a small circuit scale, one power supply system is used as a common discharge path, An inter-power supply ESD protection circuit is inserted between the power supply systems.

  Further, from the viewpoint of improving the surge withstand voltage, in the chip layout of the semiconductor integrated device, the ESD protection circuit between different power sources between the common discharge path may be disposed near the pad to which each power source is input. desirable.

  However, with the recent increase in the number of pins in a semiconductor integrated device, I / O cells constituting a circuit for signal input / output are substantially spaced in the peripheral region of the semiconductor integrated device, which is a region where power supply pads are arranged. It is laid down. Therefore, conventionally, there has been a problem that it is difficult to dispose the ESD protection circuit between different power sources between the common discharge paths in the vicinity of the pads to which the respective power sources are input in terms of the chip layout.

JP 2006-100606 A JP 2002-141415 A

  Therefore, an object of the present invention is to provide a semiconductor integrated device in which an ESD protection circuit between different power sources between a common discharge path can be arranged near each power supply pad.

  A semiconductor integrated device in which power is supplied from a first power supply system and second to nth power supply systems, and a large number of signal input / output I / O cells are arranged in a row in the peripheral region of the chip. The semiconductor integrated device of the embodiment has the same outer dimensions as the signal input / output I / O cell, has a pad, and a self-power ESD protection circuit, and is used for supplying power to the first power supply system. A first power supply I / O cell, a pad, a self-power supply ESD protection circuit, and a heterogeneous power supply ESD protection circuit having the same outer dimensions as the signal input / output I / O cell; And a second power I / O cell used for supplying power from the second to nth power supply systems. In this semiconductor integrated device, the first power I / O cell and the second power I / O cell are arranged in the same row as the signal input / output I / O cell. In this semiconductor integrated device, a common discharge path connected to the heterogeneous power supply ESD protection circuit of the second power I / O cell is arranged in a row from the first power I / O cell. The signal input / output I / O cell is passed through and wired to the second power I / O cell.

1 is a schematic layout diagram illustrating an example of a configuration of a semiconductor integrated device according to a first embodiment of the present invention. FIG. 3 is a schematic layout diagram illustrating an example of a configuration of a signal input / output I / O cell. FIG. 2 is a schematic layout diagram illustrating an example of a configuration of a power I / O cell serving as a connection source of a common discharge path in the semiconductor integrated device according to the first embodiment. FIG. 3 is a schematic layout diagram showing an example of the configuration of a power I / O cell having a heterogeneous power ESD protection circuit connected to a common discharge path in the semiconductor integrated device according to the first embodiment. The figure which shows typically the connection relation of the ESD protection circuit of each power supply of the semiconductor integrated device of 1st Embodiment. The figure which shows the example of the electrical connection of the common discharge path | route of the semiconductor integrated device of 1st Embodiment formed on the P-type board | substrate, and a board | substrate. The figure which shows the example of the electrical connection of the common discharge path | route of the semiconductor integrated device of 1st Embodiment formed on the N-type board | substrate, and a board | substrate. FIG. 8 is a schematic layout diagram illustrating an example of a configuration of a power I / O cell that is a connection source of a common discharge path in the semiconductor integrated device illustrated in FIG. 7. FIG. 8 is a schematic layout diagram showing an example of the configuration of a power I / O cell having an ESD protection circuit between different power sources connected to a common discharge path in the semiconductor integrated device shown in FIG. 7. FIG. 6 is a schematic layout diagram showing an example of the configuration of a semiconductor integrated device according to a second embodiment of the present invention. FIG. 6 is a schematic layout diagram illustrating an example of a configuration of a power I / O cell serving as a connection source of a common discharge path in a semiconductor integrated device according to a second embodiment. FIG. 9 is a schematic layout diagram illustrating an example of a configuration of a power I / O cell having an ESD protection circuit between different power sources connected to a common discharge path in the semiconductor integrated device according to the second embodiment. The figure which shows typically the connection relation of the ESD protection circuit of each power supply of the semiconductor integrated device of 2nd Embodiment. The figure which shows the example of the electrical connection of the common discharge path | route of the semiconductor integrated device of 2nd Embodiment formed on the P-type board | substrate, and a board | substrate. The figure which shows the example of the electrical connection of the common discharge path | route of the semiconductor integrated device of 2nd Embodiment formed on the N-type board | substrate, and a board | substrate.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

(First embodiment)
FIG. 1 is a schematic layout diagram showing an example of the configuration of the semiconductor integrated device according to the first embodiment of the present invention.

  The semiconductor integrated device 1 of this embodiment has an internal circuit A, an internal circuit B, and an internal circuit C that operate with different power supply systems, respectively, and a large number of signal input / output I / O cells IOC100 are arranged in the peripheral area of the chip. It is a semiconductor integrated device arranged in a shape.

  The power supply voltage VDDa and the reference voltage VSSa are supplied to the internal circuit A by the VDDa power supply system, and the power supply voltage VDDb and the reference voltage VSSb are supplied to the internal circuit B by the VDDb power supply system.

  Further, the power supply voltage VDDc and the reference voltage VSSc are supplied to the internal circuit C from the VDDc power supply system.

  In this embodiment, the reference voltage VSSc of the VDDc power supply system is used as a common discharge path CDL, and an ESD protection circuit between different power sources is connected between the common discharge path CDL and the VDDa power supply system and the VDDb power supply system. .

  Therefore, in this embodiment, different types of power I / O cells are used in the VDDc power supply system, the VDDa power supply system, and the VDDb power supply system.

  That is, the power supply I / O cell IOC1 having the pad P and the self power supply ESD protection circuit ESD1 is used for the VDDc power supply system, and the pad P and the self power supply are used for the VDDa power supply system and the VDDb power supply system. A power I / O cell IOC2 having an ESD protection circuit ESD1 and a heterogeneous power supply ESD protection circuit ESD2 is used.

  The power supply I / O cell IOC1 and the power supply I / O cell IOC2 have the same external dimensions as the signal input / output I / O cell IOC100 and are arranged in the same row as the signal input / output I / O cell IOC100. .

  In FIG. 1, power supply I / O cells IOC1 for supplying VDDc and VSSc are represented as IOC1-1 and IOC1-2, and power supply I / O cells IOC2 for supplying VDDa and VSSa are represented by IOC2-1, IOC2-2, The power supply I / O cells IOC2 for supplying VDDb and VSSb are represented as IOC2-3 and IOC2-4.

  Further, the common discharge path CDL is connected from the power supply I / O cell IOC1 (IOC1-2) for the reference voltage VSSc of the connection source to the power supply I / O cells IOC2 (IOC2-1 to IOC2-4) of the connection destination. The signal input / output I / O cell IOC 100 disposed therebetween is wired through.

  Next, the layout configuration of the signal input / output I / O cell IOC100, the power supply I / O cell IOC1, and the power supply I / O cell IOC2 will be described with reference to FIGS.

  FIG. 2 is a schematic layout diagram showing an example of the configuration of the signal input / output I / O cell IOC100.

  The signal input / output I / O cell IOC100 includes a pad P, an ESD protection circuit ESD100, and a signal processing unit CCT100. A wiring region for the common discharge path CDL is also provided.

  FIG. 2A shows an example in which the signal input / output I / O cell IOC 100 is used for an input signal. In this case, the ESD protection circuit ESD100 is provided with an ESD protection circuit ESDa to the power supply voltage VDD wiring, an ESD protection circuit ESDb to the reference voltage VSS wiring, and a protection resistor R. In the signal processing unit 100, an input buffer IBUF is formed.

  FIG. 2B shows an example in which the signal input / output I / O cell IOC 100 is used for an output signal. In this case, the ESD protection circuit ESD100 is provided with an ESD protection circuit ESDa to the power supply voltage VDD wiring and an ESD protection circuit ESDb to the reference voltage VSS wiring. In the signal processing unit 100, an output buffer OBUF is formed.

  FIG. 3A is a schematic layout diagram showing an example of the configuration of the power I / O cell IOC1. The power I / O cell IOC1 has a pad P and a self-power ESD protection circuit ESD1.

  The self-power supply ESD protection circuit ESD1 includes a positive direction ESD protection circuit ESDx and a negative direction ESD protection circuit ESDy.

  Further, the power supply I / O cell IOC1 is provided with a VDD power supply line and a VSS power supply line of its own power supply, and a common discharge path CDL is also provided.

  FIG. 3B shows a configuration example when the power I / O cell IOC1 is used for supplying the power supply voltage, taking the IOC 1-1 used for supplying the power supply voltage VDDc as an example.

  In this case, in the self-power ESD protection circuit ESD1, the positive direction ESD protection circuit ESDx is connected to the reference voltage VSSc power supply line of the self-power supply.

  FIG. 3C shows a configuration example when the power supply I / O cell IOC1 is used for supplying the reference voltage, taking the IOC1-2 used for supplying the reference voltage VSSc as an example.

  In this case, in the self-power ESD protection circuit ESD1, the negative direction ESD protection circuit ESDy is connected to the power supply voltage VDDc power supply line of the self-power supply.

  Further, the VSSc power supply line is connected to the common discharge path CDL.

  Here, when the layout of the power I / O cell IOC1 shown in FIG. 3A is compared with the layout of the signal input / output I / O cell IOC100 shown in FIG. In the IOC 1, an area where the signal processing unit 100 is formed in the signal input / output I / O cell IOC 100 is an empty space.

  Therefore, in this embodiment, the layout of the power I / O cell IOC2 is designed such that the ESD protection circuit ESD2 between different power sources is arranged in this empty space. Therefore, in this embodiment, the ESD protection circuit between different power sources can be disposed near the pad to which power is supplied, and a surge discharge path can be formed with a low resistance.

  FIG. 4A is a schematic layout diagram showing an example of the configuration of the power I / O cell IOC2. The power I / O cell IOC2 includes a pad P, a self-power ESD protection circuit ESD1, and a heterogeneous power ESD protection circuit ESD2.

  The self-power supply ESD protection circuit ESD1 includes a positive direction ESD protection circuit ESDx and a negative direction ESD protection circuit ESDy.

  The heterogeneous power supply ESD protection circuit ESD2 includes a positive direction ESD protection circuit ESDv and a negative direction ESD protection circuit ESDw.

  In addition, the power supply I / O cell IOC2 is provided with a VDD power supply line, a VSS power supply line, and a common discharge path CDL as its own power supply.

  FIG. 4B shows a configuration example when the power I / O cell IOC2 is used for supplying power supply voltage, taking IOC2-1 used for supplying power supply voltage VDDa as an example.

  In this case, in the self-power ESD protection circuit ESD1, the positive direction ESD protection circuit ESDx is connected to the reference voltage VSSa power line of the self-power supply.

  Further, in the ESD protection circuit ESD2 between different power sources, the positive direction ESD protection circuit ESDv is connected to the common discharge path CDL.

FIG. 4C shows a configuration example when the power I / O cell IOC2 is used for supplying the reference voltage, taking the IOC2-2 used for supplying the reference voltage VSSa as an example.

  In this case, in the self-power ESD protection circuit ESD1, the negative direction ESD protection circuit ESDy is connected to the power supply voltage VDDa power supply line of the self-power supply.

  Further, in the ESD protection circuit ESD2 between different power sources, the negative direction ESD protection circuit ESDw is connected to the common discharge path CDL.

  FIG. 5 shows the connection relation of the ESD protection circuit of each power supply system in the present embodiment. In this embodiment, a surge discharge path is formed by the self-power ESD protection circuit ESD1 in each power supply system, and a surge is generated by the ESD protection circuit ESD2 between different power supplies connected to the common discharge path CDL between the power supply systems. Discharge paths are formed mutually. The surge discharge path between each power supply system is connected as follows.

  VDDa and VDDb are connected by ESD2 (21) and ESD2 (23), and VDDa and VDDc are connected by ESD2 (21) and ESD1 (11). VDDa and VSSb are connected by ESD2 (21) and ESD2 (24), and VDDa and VSSc are connected by ESD2 (21).

  VDDb and VDDc are connected by ESD2 (23) and ESD1 (11), and VDDb and VSSc are connected by ESD2 (23).

  VSSa and VDDb are connected by ESD2 (22) and ESD2 (23), and VSSa and VDDc are connected by ESD2 (22) and ESD1 (11).

  VSSb and VDDc are connected by ESD2 (24) and ESD1 (11), and VSSb and VSSc are connected by ESD2 (24).

  FIG. 6 shows an example in which the semiconductor integrated device 1 is formed on a P-type substrate. Here, an example is shown in which the common discharge path CDL connected to the reference voltage VSSc power supply line is electrically connected to the P-type substrate by the substrate contact CNT1.

  By electrically connecting the common discharge path CDL to the semiconductor substrate, the wiring resistance of the common discharge path CDL can be reduced and the wiring parasitic capacitance can be increased, so that the ESD protection performance can be improved.

  On the other hand, FIG. 7 shows an example of the configuration of the semiconductor integrated device 1A formed on the N-type substrate.

  When formed on the N-type substrate, the common discharge path CDL can be electrically connected to the N-type substrate via the substrate contact CNT2 by connecting the common discharge path CDL to the power supply voltage VDDc power supply line. .

  FIG. 8A shows an example of the configuration of the power I / O cell IOC1 (IOC1-1A) used for supplying the power supply voltage VDDc in the semiconductor integrated device 1A. In the IOC 1-1A, unlike the IOC 1-1 shown in FIG. 3B, the VDDc power supply line is connected to the common discharge path CDL.

  FIG. 8B shows an example of the configuration of the power I / O cell IOC1 (IOC1-2A) used for supplying the reference voltage VSSc in the semiconductor integrated device 1A. In the IOC 2-1A, unlike the IOC 1-3 shown in FIG. 3C, the VSSc power supply line is not connected to the common discharge path CDL.

  FIG. 9A shows an example of the configuration of the power supply I / O cell IOC2 used for supplying the power supply voltage in the semiconductor integrated device 1A, taking the IOC2-1A used for supplying the power supply voltage VDDa as an example. In the IOC 2-1 A, unlike the IOC 2-1 shown in FIG. 4B, in the heterogeneous power source ESD protection circuit ESD 2, the negative direction ESD protection circuit ESDw is connected to the common discharge path CDL.

  FIG. 9B shows an example of the configuration of the power I / O cell IOC2 used for supplying the reference voltage in the semiconductor integrated device 1A, taking the IOC2-2A used for supplying the reference voltage VSSa as an example. In the IOC 2-2A, unlike the IOC 2-2 shown in FIG. 4C, in the ESD protection circuit ESD2 between different power sources, the positive direction ESD protection circuit ESDv is connected to the common discharge path CDL.

  According to the present embodiment as described above, the power supply I / O cell IOC1 for the power supply system connected to the common discharge path CDL and the power supply I having the heterogeneous power supply ESD protection circuit ESD2 for other power supply systems. / O cell IOC2 is formed with the same outer dimensions as signal I / O cell IOC100 for signal input / output, and is arranged in the same row as signal I / O cell IOC100 for signal input / output arranged in a column, / O cell IOC2 heterogeneous power supply ESD protection circuit ESD2 is connected to common discharge path CDL. As a result, the ESD protection circuit between different power sources can be disposed near the pad to which power is supplied, and a surge discharge path can be formed with low resistance.

  Further, a surge discharge path between the power supply systems is provided by the ESD protection circuit ESD2 between the different power sources connected to the common discharge path CDL and the self-power ESD protection circuit ESD1 included in each of the power I / O cells IOC1 and IOC2. Can be formed.

  Further, by electrically connecting the common discharge path CDL to the semiconductor substrate, the wiring resistance of the common discharge path CDL can be reduced and the wiring parasitic capacitance can be increased, and the ESD protection performance can be improved.

  When the signal input / output I / O cells IOC100 are arranged on the four sides of the chip, the common discharge path CDL can be routed around the peripheral area of the chip. Thus, when the signal input / output I / O cells IOC100 are arranged only on two opposite sides of the chip, the common discharge path CDL wired on each side is connected using the power supply network of the internal circuit. To do.

(Second Embodiment)
In the first embodiment, an example in which either the VSSc power supply line or the VDDc power supply line is used as a common discharge path is shown. However, in this embodiment, an example in which both the VSSc power supply line and the VDDc power supply line are used as a common discharge path is shown. Show.

  FIG. 10 is a schematic layout diagram showing an example of the configuration of the semiconductor integrated device according to the second embodiment of the present invention.

  The semiconductor integrated device 2 of this embodiment is different from the semiconductor integrated device of the first embodiment in that a common discharge path CDL1 connected to the VSSc power supply line, a common discharge path CDL2 connected to the VDDc power supply line, This is a point having two common discharge paths.

  In this embodiment, the power supply I / O cell IOC11 is used for the VDDc power supply system, and the power supply I / O cell IOC21 is used for the VDDa and VDDb power supply systems.

  The common discharge path CDL1 is from the power source I / O cell IOC11 (IOC11-2) for the connection source reference voltage VSSc, and the common discharge path CDL2 is the power source I / O cell for the power source voltage VDDc of the connection source. Wiring is performed from the IOC 11 (IOC 11-1) to the power I / O cells IOC 21 to be connected (IOC 21-1 to IOC 21-4) through the signal input / output I / O cells IOC 100 arranged therebetween. Is done.

  FIG. 11A is a schematic layout diagram showing an example of the configuration of the power I / O cell IOC11. The power I / O cell IOC11 has a pad P and a self power ESD protection circuit ESD1, and a common discharge path CDL1 and a common discharge path CDL2 are wired.

  FIG. 11B shows a configuration example when the power I / O cell IOC11 is used for supplying the power supply voltage, taking the IOC 11-1 used for supplying the power supply voltage VDDc as an example.

  In this case, in the self-power ESD protection circuit ESD1, the positive direction ESD protection circuit ESDx is connected to the reference voltage VSSc power supply line of the self-power supply. Further, the VDDc power supply line is connected to the common discharge path CDL2.

  FIG. 11C shows a configuration example when the power I / O cell IOC11 is used for supplying the reference voltage, taking the IOC 11-2 used for supplying the reference voltage VSSc as an example.

  In this case, in the self-power ESD protection circuit ESD1, the negative direction ESD protection circuit ESDy is connected to the power supply voltage VDDc power supply line of the self-power supply. In addition, the VSSc power supply line is connected to the common discharge path CDL1.

  FIG. 12A is a schematic layout diagram showing an example of the configuration of the power I / O cell IOC21. The power I / O cell IOC21 includes a pad P, a self-power ESD protection circuit ESD1, a heterogeneous power ESD protection circuit ESD21, and a heterogeneous power ESD protection circuit ESD22. The heterogeneous power supply ESD protection circuit ESD21 includes a positive direction ESD protection circuit ESDv, and the heterogeneous power supply ESD protection circuit ESD22 includes a negative direction ESD protection circuit ESDw.

  Further, the common discharge path CDL1 and the common discharge path CDL2 are wired.

  FIG. 12B shows a configuration example when the power I / O cell IOC21 is used for supplying the power supply voltage, taking the IOC 21-1 used for supplying the power supply voltage VDDa as an example.

  In this case, in the self-power ESD protection circuit ESD1, the positive direction ESD protection circuit ESDx is connected to the reference voltage VSSa power line of the self-power supply.

  Further, the different power supply ESD protection circuit ESD21 is connected to the common discharge path CDL1, and the different power supply ESD protection circuit ESD22 is connected to the common discharge path CDL2.

FIG. 12C shows a configuration example when the power I / O cell IOC21 is used for supplying the reference voltage, taking the IOC 21-2 used for supplying the reference voltage VSSa as an example.

  In this case, in the self-power ESD protection circuit ESD1, the negative direction ESD protection circuit ESDy is connected to the power supply voltage VDDa power supply line of the self-power supply.

  Further, the different power supply ESD protection circuit ESD21 is connected to the common discharge path CDL2, and the different power supply ESD protection circuit ESD22 is connected to the common discharge path CDL1.

  FIG. 13 shows the connection relation of the ESD protection circuit of each power supply system in this embodiment. In the present embodiment, a surge discharge path is formed by the self-power ESD protection circuit ESD1 in each power supply system, and an ESD protection circuit between different power sources connected to the common discharge path CDL1 or CDL2 between the power supply systems. A surge discharge path is formed by ESD21 and ESD22.

  When this is compared with the connection relationship of the ESD protection circuit of the first embodiment shown in FIG. 5, in FIG. 5, the surge discharge path of the VDDc power supply line and another power supply system is the self-power supply ESD protection circuit ESD1 (11 ) To connect the different power supply ESD protection circuit ESD2 of another power supply system. On the other hand, in FIG. 13, the surge discharge path of the VDDc power supply line and the other power supply system has a one-stage configuration of only the ESD protection circuit ESD21 or ESD22 between different power sources that is made the common discharge path CDL2.

  By configuring the surge discharge path in one stage, the ESD protection performance of the VDDc power supply line can be improved.

  FIG. 14 shows an example in which the semiconductor integrated device 2 is formed on a P-type substrate. Here, an example is shown in which the common discharge path CDL1 connected to the reference voltage VSSc power supply line is electrically connected to the P-type substrate by the substrate contact CNT1.

  By electrically connecting the common discharge path CDL1 to the semiconductor substrate, the wiring resistance of the common discharge path CDL1 can be reduced and the wiring parasitic capacitance can be increased, so that the ESD protection performance can be improved.

  On the other hand, FIG. 15 shows an example of the configuration of the semiconductor integrated device 2A formed on the N-type substrate.

  In this case, the common discharge path CDL2 connected to the power supply voltage VDDc power supply line is electrically connected to the N-type substrate by the substrate contact CNT2.

  By electrically connecting the common discharge path CDL2 to the semiconductor substrate, the wiring resistance of the common discharge path CDL2 can be decreased and the wiring parasitic capacitance can be increased, so that the ESD protection performance can be improved.

  According to this embodiment, by providing the common discharge path CDL1 connected to the VSSc power supply line and the common discharge path CDL2 connected to the VDDc power supply line, between the VSSc power supply system and another power supply system. The surge discharge path can be constituted by one stage of the ESD protection circuit ESD21 or ESD22 between different power sources, and the ESD protection performance can be improved.

  When the signal input / output I / O cells IOC100 are arranged on the four sides of the chip, the common discharge paths CDL1 and CDL2 can be routed around the peripheral area of the chip. When the signal input / output I / O cells IOC100 are arranged only on two opposite sides of the chip as in the above, the common discharge path CDL1 and the common discharge path CDL2 wired on each side are respectively connected to the power supply of the internal circuit. Try to connect using the network.

  According to the semiconductor integrated device of at least one embodiment described above, the ESD protection circuit between different types of power supplies between the common discharge paths can be arranged near the pads of the respective power supplies.

  Moreover, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

1, 1A, 2, 2A Semiconductor integrated devices IOC1, IOC11, IOC2, IOC21 Power supply I / O cell ESD1 Self power supply ESD protection circuit ESD2, ESD21, ESD22 Dissimilar power supply ESD protection circuit P Pad CDL, CDL1, CDL2 Common discharge Path CNT1, CNT2 Substrate contact

Claims (8)

A semiconductor integrated device in which power of a first power supply system and second to nth power supply systems is supplied, and a large number of signal input / output I / O cells are arranged in a row in a peripheral region of the chip,
A first power supply I / O having the same outer dimensions as the signal input / output I / O cell, including a pad and a self-power supply ESD protection circuit, and used for supplying power to the first power supply system. O cell,
It has the same external dimensions as the signal input / output I / O cell, has a pad, a self-power ESD protection circuit, and an ESD protection circuit between different power sources, and supplies power from the second to n-th power systems. A second power I / O cell used for supply,
The first power I / O cell and the second power I / O cell are arranged in the same row as the signal input / output I / O cell,
A common discharge path connected to the heterogeneous power ESD protection circuit of the second power I / O cell is the signal input / output arranged in a row from the first power I / O cell. A semiconductor integrated device, wherein the semiconductor integrated device is wired to the second power I / O cell through the I / O cell. 2. The semiconductor integrated device according to claim 1, wherein the common discharge path is a reference voltage line of the first power supply system. 2. The semiconductor integrated device according to claim 1, wherein the common discharge path is a power supply voltage line of the first power supply system. 4. The semiconductor integrated device according to claim 1, wherein the common discharge path is electrically connected to a substrate of the chip. 5. 2. When the signal input / output I / O cells are arranged only on opposite sides of a chip, the common discharge paths on the respective sides are connected using a power supply network in an internal circuit. 5. The semiconductor integrated device according to any one of 1 to 4. A semiconductor integrated device in which power of a first power supply system and second to nth power supply systems is supplied, and a large number of signal input / output I / O cells are arranged in a row in a peripheral region of the chip,
A first power supply I having the same outer dimensions as the signal input / output I / O cell, a pad, and a self-power ESD protection circuit, which is used to supply a reference voltage of the first power supply system. / O cell,
A second power supply I that has the same outer dimensions as the signal input / output I / O cell, has a pad, and a self-power supply ESD protection circuit, and is used to supply a power supply voltage of the first power supply system. / O cell,
A pad, a self-power ESD protection circuit, a first heterogeneous power ESD protection circuit, and a second heterogeneous power ESD protection circuit having the same external dimensions as the signal input / output I / O cell. A third power I / O cell used for power supply of the second to n-th power supply systems,
The first power I / O cell, the second power I / O cell, and the third power I / O cell are arranged in the same row as the signal I / O cell,
A first common discharge path connected to the first inter-power supply ESD protection circuit of the third power I / O cell is arranged in a row from the first power I / O cell. The signal input / output I / O cell is passed through to the third power I / O cell,
Second common discharge paths connected to the second inter-power supply ESD protection circuit of the third power I / O cell are arranged in a row from the second power I / O cell. A semiconductor integrated device, wherein the signal input / output I / O cell is penetrated and wired to the third power supply I / O cell. 7. The semiconductor integrated device according to claim 6, wherein either the first common discharge path or the second common discharge path is electrically connected to the substrate of the chip. When the signal input / output I / O cell is arranged only on the opposite side of the chip, the first common discharge path and the second common discharge path on each side are respectively connected to the power supply network in the internal circuit. The semiconductor integrated device according to claim 6 or 7, wherein the semiconductor integrated device is used for connection.

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