JP2013120857A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which can reduce a chip area of a semiconductor.SOLUTION: A master slice semiconductor integrated circuit of an embodiment comprises: an internal circuit 13 arranged on a central part of a semiconductor substrate 11; a plurality of input-output PADs 122 arranged on a peripheral part of the internal circuit 13; and a plurality of input-output buffers 121 arranged between the internal circuit 13 and the plurality of input-output PADs 122, respectively. The internal circuit 13 includes a plurality of electrostatic protection elements arranged in line with each other.

Description

  The present invention relates to a semiconductor integrated circuit.

  In a custom LSI (Large Scale Integration) in which devices such as a gate array are arranged on the array, an arrangement method of parts generally adopted in many cases is as follows. An input / output unit, a protection element, and a PAD are arranged in the peripheral portion of the LSI chip, and an element array actually used as a logic circuit is arranged in the LSI chip. Here, typically, a PAD, a protection element, and an input / output transistor (buffer) integrated are treated as a single I / O cell and arranged in the peripheral portion of the chip.

  FIG. 19 is an overall view of a chip, which is a semiconductor integrated circuit, showing an example of an array element arrangement. The chip 40 has an I / O cell 42 and an internal circuit 43 configured on a semiconductor substrate 41. The arrangement relationship of each part of the chip 40 is as follows. The internal circuit 43 is disposed at the center of the chip 40 (semiconductor substrate 41), and the I / O cell 42 is disposed at the periphery of the chip 40 (semiconductor substrate 41).

  FIG. 20A is a schematic diagram of the I / O cell 42 in the chip 40 shown in FIG. The I / O cell 42 includes an input / output buffer 421, a protective PMOS (Positive channel Metal Oxide Semiconductor) transistor region 422, a protective NMOS (Negative channel Metal Oxide Semiconductor) transistor region 423, a protective resistor / diode region 424, and a PAD 425. With elements. The input / output buffer 421 is connected to the internal circuit 43.

  FIG. 20B is an overall view showing a detailed structure of the I / O cell 42 shown in FIG. FIG. 20B shows an example of a typical element arrangement of an I / O cell in a gate array or a master slice LSI. The protective resistance / diode region 424 includes a protective resistive element portion 424A and a protective diode region 424B. In FIG. 20B, the protective resistance element portion 424A is disposed in the protective PMOS transistor region 422, and the protective diode region 424B is disposed in the protective NMOS transistor region 423.

  Here, in the master slicing method, a plurality of elements such as resistors, capacitors, transistors, etc. previously formed on the semiconductor substrate as described above are connected in a wiring process, thereby forming a desired circuit, thereby integrating the semiconductor integrated circuit. A circuit is manufactured.

  As an example of such a semiconductor integrated circuit, semiconductor integrated circuits described in Patent Documents 1 to 7 can be cited.

JP-A-6-85217 JP-A-3-30452 JP-A-8-186238 Japanese Patent Laid-Open No. 9-82928 JP-A-9-31345 JP-A-6-334045 Japanese Patent Laid-Open No. 3-195045

  In FIG. 19 and FIG. 20, the same I / O cells are uniformly arranged in an array around the chip periphery. Therefore, there is versatility of terminal arrangement in the chip. However, there is a problem in that the area of the entire region of the I / O cell 42 becomes so large that it cannot be ignored relative to the area of the entire chip. In particular, since the protective elements (protective MOS transistors, diodes, resistors) mounted in the I / O cell 42 to maintain the electrostatic protection tolerance occupy a large area, the chip size increases. This increases the chip cost of the entire circuit.

  In particular, when the required level of withstand electrostatic protection is high in a semiconductor integrated circuit, it is necessary to add an additional protective element or increase the size of the protective element, and the protective element may occupy a larger area. . In that case, the chip cost of the entire circuit is further increased.

  Further, in the chip shown in FIGS. 19 and 20, all necessary elements are mounted inside the I / O cell 42 so as to be compatible with any type of circuit design of input, output or bidirectional. Therefore, in an actual circuit operation, there is an element that is not used among elements that are arranged in advance, and there is a problem that the efficiency of use of the element deteriorates in a chip manufactured by the master slice method.

  In the integrated circuits of Patent Documents 1 to 7, since it is assumed that the electrostatic protection element is provided in the I / O cell, the area of the protection element cannot be reduced.

  A master slice type semiconductor integrated circuit according to the present invention includes an internal circuit disposed in a central portion of a semiconductor substrate, a plurality of input / output pads disposed in a peripheral portion of the internal circuit, the internal circuit, and the And a plurality of input / output buffers disposed between the plurality of input / output pads. The internal circuit has a plurality of electrostatic protection elements arranged in a line. With this configuration, since the electrostatic protection elements are arranged in a line in the internal circuit, it is not necessary to provide them in the peripheral portion of the internal circuit. Therefore, the area on the semiconductor substrate necessary for providing the electrostatic protection element having the same function is reduced, and the chip area of the semiconductor can be reduced.

  According to the present invention, a semiconductor integrated circuit that can reduce the chip area of a semiconductor can be provided.

1 is a general view showing an example of a chip according to a first embodiment and a schematic diagram showing an example of an I / O cell; 2 is a schematic diagram illustrating an example of an element arrangement of an internal circuit according to the first embodiment; FIG. 2 is a diagram illustrating a specific example of element arrangement of an internal circuit according to the first embodiment; FIG. FIG. 3 is a configuration diagram illustrating an example of an output buffer according to the first embodiment, and a configuration diagram illustrating an example of an output buffer according to a related technique. 3 is a chart comparing the configuration of the output buffer according to the first embodiment and the configuration of a protection transistor in the output buffer according to the related technology. It is the schematic diagram which compared the area of the I / O cell concerning related technology, and the area of the I / O cell concerning Embodiment 1. FIG. In the chip concerning Embodiment 1, it is the whole chip figure showing the effective area which increased when compared with the chip concerning related technology. FIG. 6 is an overall view showing an example of a chip according to a second embodiment. 6 is a schematic diagram illustrating an example of an element arrangement of an internal circuit according to a second embodiment; FIG. FIG. 10 is a configuration diagram illustrating an example of an output buffer according to a second embodiment; FIG. 3 is a configuration diagram illustrating an example of an analog switch according to a second embodiment and a configuration diagram illustrating an example of an analog amplifier output stage according to the second embodiment. In the chip concerning Embodiment 2, it is the whole chip figure showing the effective area increased when compared with the chip concerning related technology. FIG. 9 is a schematic diagram illustrating an example of an element arrangement of an internal circuit according to a third embodiment. FIG. 6 is a configuration diagram illustrating an example of an element arrangement of an internal circuit according to a third embodiment; FIG. 10 is a configuration diagram illustrating an example of an output buffer according to a third embodiment; FIG. 6 is an overall view showing an example of a chip according to a fourth embodiment. FIG. 9 is a configuration diagram illustrating an example of an element arrangement of an internal circuit according to a fourth embodiment; FIG. 10 is a configuration diagram illustrating an example of an output buffer according to a fourth embodiment; It is the whole chip | tip which showed the element arrangement | positioning concerning related technology. It is the schematic diagram which showed an example of the I / O cell concerning related technology, and the whole figure which showed the detailed structure.

Embodiment 1
Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1A is an overall view showing an example of an LSI chip (semiconductor integrated circuit) according to the first embodiment of the present invention. FIG. 1A shows an overall image of the arrangement of elements constituting the chip. In the chip 10 of FIG. 1A, an I / O cell 12 and an internal circuit 13 are mounted on a semiconductor substrate 11 made of silicon. The I / O cells 12 are arranged in an array on the periphery of the chip 10 (semiconductor substrate 11) so as to surround the four sides of the internal circuit 13. The internal circuit 13 is disposed at the center of the chip 10 (semiconductor substrate 11), and has an element array portion in which single elements are arranged in an array.

  FIG. 1B is a schematic diagram of the I / O cell 12. The type of the I / O cell 12 in FIG. 1B is single, and the I / O cell 12 includes only the input / output buffer 121 and the PAD 122. The input / output buffer 121 is a buffer circuit including transistors and the like, and the PAD 122 is an input or output terminal connected to the outside of the chip 10. In the I / O cell 12, the input / output buffer 121 is provided inside the chip 10 and the PAD 122 is provided outside. That is, a plurality of input / output buffers 121 are disposed between the internal circuit 13 and each of the plurality of input / output PADs 122.

  FIG. 2 is a schematic diagram showing an example of the arrangement structure of the array elements of the internal circuit 13. The internal circuit 13 includes a resistance region 131, PMOS transistor regions 132, 133, and 134, NMOS transistor regions 135, 136, and 137, a resistance region 138, a protective P / NMOS transistor region 139, a diode region 140, and a capacitance region 141. In each part of the internal circuit 13, elements constituting each part are arranged in a line.

  The protective P / NMOS transistor region 139 includes a protective PMOS transistor and a protective NMOS transistor. The protection PMOS transistor and the protection NMOS transistor are protection elements for countermeasures against static electricity connected to the PAD 122. The protection elements for electrostatic countermeasures are arranged in a predetermined ratio in the elements of the internal circuit 13 according to the configuration of the internal circuit 13.

  In the first embodiment of the present invention, an electrostatic protection element (a protection PMOS transistor region 422, a protection NMOS transistor region in FIG. 20) that has been conventionally arranged in the I / O cell 12 portion around the chip 10 conventionally. 423) is arranged as an array element of the internal circuit 13 (protective P / NMOS transistor region 139). For this reason, no electrostatic protection element is provided between the plurality of input / output buffers 121 and the plurality of input / output PADs 122.

  Signals input to or output from the PAD 122 connected to the outside of the chip 10 are statically arranged in an array in the input / output buffer 121 mounted in the I / O cell 12 and in the internal circuit 13. Input to or output from an input / output circuit composed of an electrical protection element. Details of the input / output circuit of the chip 10 will be described later.

  FIG. 3 is a configuration diagram showing a specific example of the element arrangement of the internal circuit 13. In FIG. 3, in the resistance region 131, the resistance elements are arranged in a line in an array. In the PMOS transistor region 132, PMOS transistors are arranged in an array in a row (not shown, but in the PMOS transistor regions 133 and 134, the PMOS transistors are similarly arranged in an array in a row. Yes.) In the NMOS transistor region 137, NMOS transistors are arranged in an array in a row (not shown, but in the NMOS transistor regions 135 and 136, similarly, NMOS transistors are arranged in an array in a row. Yes.) In the resistance region 138, resistance elements are arranged in two rows in an array. In the protective P / NMOS transistor region 139, protective PMOS transistors and protective NMOS transistors are arranged in a line in an array. In the diode region 140, the diodes are arranged in an array in two rows. In the capacitance region 141, capacitors are arranged in a line in an array.

  4A shows a configuration example of an equivalent circuit of an output buffer when an output buffer (input / output circuit) output to an external terminal is configured based on the configuration of the chip 10 shown in FIGS. It is. FIG. 4B is a configuration example of an equivalent circuit of an output buffer (input / output circuit) in the case where an output buffer is configured in the conventional chip element arrangement method shown in FIGS.

  4A, in the protection PMOS transistor 144 in the region of the internal circuit 13, the power supply voltage VDD is input to the source, the gate is short-circuited to the source, and the drain is connected to the PAD 122 in the I / O cell 12. ing. The protection NMOS transistor 145 has a drain connected to the PAD 122 in the I / O cell 12, a gate short-circuited to the source, and a ground voltage GND input to the source. That is, the protection PMOS transistor 144 and the protection NMOS transistor 145 are diode-connected. The protection PMOS transistor 144 and the protection NMOS transistor 145 are elements constituting the protection P / NMOS transistor region 139.

  In the output PMOS transistor 123 in the I / O cell 12 region, the power supply voltage VDD is input to the source, the gate is connected to the buffer 142 in the internal circuit 13, and the drain is connected to the PAD 122. The output NMOS transistor 124 has a drain connected to the PAD 122, a gate connected to the inversion buffer 143 in the internal circuit 13, and a ground voltage GND input to the source. The output PMOS transistor 123 and the output NMOS transistor 124 are elements constituting the input / output buffer 121.

  The signal line to which the drain of the protective PMOS transistor 144 and the drain of the protective NMOS transistor 145 are connected is connected in parallel with the signal line to which the drain of the output PMOS transistor 123 and the drain of the output NMOS transistor 124 are connected. It is connected to the PAD 122. With this configuration, even when an abnormal current due to ESD (Electrostatic Discharge) flows from the PAD 122, the abnormal current flows through the protection PMOS transistor 144 and the protection NMOS transistor 145, so that the internal circuit can be protected.

  4B, in the protection PMOS transistor 426 in the region of the I / O cell 42, the power supply voltage VDD is input to the source, the gate is short-circuited to the source, and the drain is connected to the PAD 425 in the I / O cell 12. It is connected. The protection NMOS transistor 427 has a drain connected to the PAD 425 in the I / O cell 42, a gate short-circuited to the source, and a ground voltage GND input to the source. That is, the protective PMOS transistor 426 and the protective NMOS transistor 427 are diode-connected. The protection PMOS transistor 426 is an element constituting the protection PMOS transistor region 422, and the protection NMOS transistor 427 is an element constituting the protection NMOS transistor region 423.

  In the output PMOS transistor 428 in the I / O cell 42, the power supply voltage VDD is input to the source, the gate is connected to the buffer 431 in the internal circuit 43, and the drain is connected to the PAD 425. The output NMOS transistor 429 has a drain connected to the PAD 425, a gate connected to the inverting buffer 432 in the internal circuit 43, and a ground voltage GND input to the source. The output PMOS transistor 428 and the output NMOS transistor 429 are elements constituting the input / output buffer 421.

  In FIG. 4B, the signal line to which the drain of the protection PMOS transistor 426 and the drain of the protection NMOS transistor 427 are connected is a signal to which the drain of the output PMOS transistor 428 and the drain of the output NMOS transistor 429 are connected. It is connected in parallel with the line and connected to the PAD 425. With this configuration, even when an abnormal current due to ESD flows from the PAD 425, the abnormal current flows through the protection PMOS transistor 426 and the protection NMOS transistor 427, so that the internal circuit 43 can be protected.

  The protection PMOS transistor 144 and the protection NMOS transistor 145 in FIG. 4A are disposed in the internal circuit 13, whereas the protection PMOS transistor 426 and the protection NMOS transistor 427 in FIG. Are disposed in the I / O cell 42.

  FIG. 5 shows the W (horizontal width) size of the protection PMOS transistor and the protection NMOS transistor in the input / output buffer shown in FIG. 4A and the input / output buffer shown in FIG. It is the chart which compared the number and total W size.

  In FIG. 4B, a protection PMOS transistor 426 and a protection NMOS transistor 427 each having a large W size are arranged in the I / O cell 42, and a protection function as a protection transistor is obtained by using them. Is realized. The W sizes of the protection PMOS transistor 426 and the protection NMOS transistor 427 are 500 μm and 250 μm, respectively. Further, in FIG. 4B, the fact that the number is 1 is described as m = 1. In other drawings, the number is similarly expressed.

  On the other hand, in FIG. 4A, a protection PMOS transistor 144 and a protection NMOS transistor 145, which are array elements in the internal circuit 13 and are single transistors for protection having a small W size, are connected in parallel. W size required for protection is realized. The W sizes of the protection PMOS transistor 144 and the protection NMOS transistor 145 are 20 μm and 10 μm, respectively. In the input / output buffer shown in FIG. 4A, 25 protection PMOS transistors 144 and 25 protection NMOS transistors 145 are connected in parallel. Accordingly, the total W size of the protection PMOS transistor 144 and the protection NMOS transistor 145 in FIG. 4A is changed to the total W size of the protection PMOS transistor 426 and the protection NMOS transistor 427 in FIG. Same value. As a result, the ESD protection function of the output buffer circuit in FIG. 4A is guaranteed to be equivalent to the ESD protection function of the output buffer circuit in FIG. 4B.

  As described above, the following effects can be obtained by applying the layout method shown in FIGS. 1 to 3 in a semiconductor integrated circuit employing the master slice method.

  In the chip, a plurality of electrostatic protection elements are arranged in a line in the internal circuit 13 rather than in the I / O cell 12. Thereby, it is possible to delete the input / output electrostatic protection element conventionally mounted in the I / O cell. 1 to 3, no electrostatic protection element is provided between the plurality of input / output PADs 122 and the plurality of input / output buffers 121. Therefore, the area of the I / O cell is greatly reduced.

  FIG. 6 is a schematic diagram comparing the area of the I / O cell 12 shown in FIG. 1 with the area of the conventional I / O cell 42 shown in FIG. It can be seen from FIG. 6 that the area of the I / O cell has been significantly reduced.

  By significantly reducing the area of the I / O cell, the effective area (area) in which elements can be arranged increases in the entire chip. If the required area of the electrostatic protection element is the same for chips of the same area, the electrostatic protection elements are arranged in a row in the internal circuit rather than arranging the electrostatic protection elements on the four sides of the chip periphery. This is because the area of the four corners of the chip on which no element is provided becomes smaller. FIG. 7 shows the effective area 15 increased when the chip 10 shown in FIG. 1 is compared with the conventional chip 40 shown in FIG. By mounting the elements used in the chip 10 in the effective area 15, the number of effective elements that can be mounted per chip area can be increased.

  On the contrary, if the number of effective elements mounted on the chip 10 is the same as the conventional one, the chip area can be reduced. Thereby, the chip cost can be reduced.

  As described above, in the chip according to the present embodiment, it is possible to efficiently use the element while preventing an increase in the chip cost while maintaining a high level of electrostatic protection tolerance and a certain level of input / output versatility.

Embodiment 2
Embodiments of the present invention will be described below with reference to the drawings. FIG. 8 is an overall view showing an example of an LSI chip according to the second embodiment of the present invention, and shows an overall image of the arrangement of elements constituting the LSI. In the chip 20 of FIG. 8, a PAD 22 and an internal circuit 23 are mounted on a semiconductor substrate 21. The PAD 22 is juxtaposed on the periphery of the chip 20 (semiconductor substrate 21) so as to surround the four sides of the internal circuit 23. The internal circuit 23 is an element array portion provided inside the chip 20 (semiconductor substrate 21) and in which single elements are regularly arranged in parallel.

  Note that the input / output buffer of the internal circuit 23 (the input / output buffer 121 in the first embodiment) is not provided between the PAD 22 and the internal circuit 23. In the second embodiment, the input / output buffer is configured using a transistor in the internal circuit 23 that is not used to realize the circuit operation of the internal circuit 23. Details of this will be described later.

  FIG. 9 is a schematic diagram illustrating an example of element arrangement in the internal circuit 23. The internal circuit 23 illustrated in FIG. 9 includes a resistance region 231, PMOS transistor regions 232, 233, and 234, NMOS transistor regions 235, 236, and 237, a resistance region 238, a diode region 239, and a capacitance region 240. In each part of the internal circuit 23, elements constituting each part are arranged in an array. The resistance region 231, the PMOS transistor regions 232, 233, 234, the NMOS transistor regions 235, 236, 237, the resistance region 238, and the diode region 239 are respectively the resistance region 131 and the PMOS transistor regions 132, 133, 134 in the first embodiment. , NMOS transistor regions 135, 136, 137, resistance region 138, and diode region 140. The specific element arrangement of each part is the same as the specific example of the element arrangement shown in FIG.

  Here, the array element arrangement portion of the internal circuit 23 is not provided with the protective P / NMOS transistor region 139 in the first embodiment. That is, the internal circuit 23 is not pre-installed with a special transistor for input / output electrostatic protection. In the second embodiment, the transistors for electrostatic protection for input / output are a plurality of transistors in the PMOS transistor region 234 and the NMOS transistor region 235 that are not used for realizing the circuit operation of the internal circuit 23. A transistor is used. The PMOS transistor region 234 and the NMOS transistor region 235 are configured by transistor elements arranged in a line.

  The input / output buffer is composed of transistors that are not used in the PMOS transistor region 233 and the NMOS transistor region 236 to realize the circuit operation inside the internal circuit 23. The PMOS transistor region 233 and the NMOS transistor region 236 are configured by transistor elements arranged in a line.

  FIG. 10 is a configuration example showing an equivalent circuit of an output buffer when an output buffer output to an external terminal is configured based on the configuration of the chip 20 shown in FIGS.

  In FIG. 10, the protection PMOS transistor 241 in the region of the internal circuit 23 has the source supplied with the power supply voltage VDD, the gate short-circuited to the source, and the drain connected to the PAD 22. The protection NMOS transistor 242 has a drain connected to the PAD 22, a gate short-circuited to the source, and a ground voltage GND input to the source. That is, the protection PMOS transistor 241 and the protection NMOS transistor 242 are diode-connected. The protection PMOS transistor 241 is an element constituting the PMOS transistor region 234, and the protection NMOS transistor 242 is an element constituting the NMOS transistor region 235, each of which is a standard array element.

  The output PMOS transistor 243 in the internal circuit 23 has the source supplied with the power supply voltage VDD, the gate connected to the buffer 245 in the internal circuit 23, and the drain connected to the PAD 22. The output NMOS transistor 244 has a drain connected to the PAD 22, a gate connected to the inverting buffer 246 in the internal circuit 13, and a ground voltage GND input to the source. The output PMOS transistor 243 is an element constituting the PMOS transistor region 233, and the output NMOS transistor 244 is an element constituting the NMOS transistor region 236.

  In FIG. 10, the signal line to which the drain of the protection PMOS transistor 241 and the drain of the protection NMOS transistor 242 are connected is in parallel with the signal line to which the drain of the output PMOS transistor 243 and the drain of the output NMOS transistor 244 are connected. Connected to PAD22. With this configuration, even when an abnormal current due to ESD flows from the PAD 22, the current flows through the protection PMOS transistor 241 and the protection NMOS transistor 242, so that the internal circuit 23 can be protected.

  In the output buffer of FIG. 10, similarly to the output buffer of FIG. 4A, the protection PMOS transistor 241 and the protection NMOS transistor 242 which are array elements in the internal circuit 23 and are single transistors for protection having a small W size are provided. By connecting them in parallel, the W size required for protection is realized. The W sizes of the protective PMOS transistor 241 and the protective NMOS transistor 242 are 20 μm and 10 μm, respectively. In the output buffer of FIG. 10, 25 protection PMOS transistors 241 and 25 protection NMOS transistors 242 are connected in parallel. Thus, as in the first embodiment, the ESD protection function of the output buffer circuit in FIG. 10 is guaranteed to be equivalent to the ESD protection function of the output buffer circuit in FIG.

  In FIG. 4A, an output PMOS transistor 123 and an output NMOS transistor 124 each having a large W size are arranged in the input / output buffer 121 of the I / O cell 12, and output is achieved by using them. The buffer function is realized. The W size of the output PMOS transistor 123 is 200 μm, and the W size of the output NMOS transistor 124 is 100 μm.

  On the other hand, in FIG. 10, a plurality of output PMOS transistors 243 and a plurality of output NMOS transistors 244 each having a small W size are connected in parallel, thereby realizing the W size necessary for the function of the output buffer. In the input / output buffer of FIG. 10, ten output PMOS transistors 243 and ten output NMOS transistors 244 are connected in parallel. As a result, the total W size of the output PMOS transistor 243 and the output NMOS transistor 244 in FIG. 10 is set to the same value as the total W size of the output PMOS transistor 123 and the output NMOS transistor 124 in FIG. ing. As a result, the function of the output buffer of the output buffer circuit in FIG. 10 is guaranteed to be equivalent to the function of the output buffer in FIG.

  Further, based on the configuration of the chip 20 shown in FIGS. 8 and 9, the configuration diagrams when the analog switch (transfer gate) and the analog amplifier output stage are configured are shown in FIGS. 11 (a) and 11 (b), respectively. Show.

  In FIG. 11A, a CMOS transfer gate is configured by connecting a switching PMOS transistor 247 and a switching NMOS transistor 248. The drain of the switching PMOS transistor 247 and the source of the switching NMOS transistor 248 are connected to a common input / output signal line in the internal circuit 23, and the source of the switching PMOS transistor 247 and the drain of the switching NMOS transistor 248 are Are connected to the PAD 22 by a common input / output signal line. A signal whose level is inverted is input to the gate of the switching PMOS transistor 247 and the gate of the switching NMOS transistor 248. Specifically, a gate signal is input from the gate signal line to the gate of the switching PMOS transistor 247 via the resistor 249, the inverting buffer 250, and the resistor 251 in the internal circuit 23. A gate signal is input from the gate signal line to the gate of the switching NMOS transistor 248 via the resistor 249, the inverting buffer 250, the resistor 252, the inverting buffer 253, and the resistor 254 in the internal circuit 23. Here, the gate signal input to the gate of the switching NMOS transistor 248 passes through the inversion buffer 253, so that the logic level of the gate signal input to the gate of the switching PMOS transistor 247 is inverted.

  In the protection PMOS transistor 241 and the protection NMOS transistor 242 in FIG. 11A, the drains are connected and connected to the PAD 22 in the same manner as the output buffer circuit shown in FIG. In FIG. 11A, a signal line to which the drain of the protective PMOS transistor 241 and the drain of the protective NMOS transistor 242 are connected is a signal in which the drain of the switching PMOS transistor 247 and the drain of the switching NMOS transistor 248 are connected. It is connected in parallel with the line and connected to the PAD 22.

  The switching PMOS transistor 247 is an element constituting the PMOS transistor region 233, and the switching NMOS transistor 248 is an element constituting the NMOS transistor region 236. The protection PMOS transistor 241 is an element constituting the PMOS transistor region 234, and the protection NMOS transistor 242 is an element constituting the NMOS transistor region 235. A guard ring is provided around the switching PMOS transistor 247, the switching NMOS transistor 248, and the inversion buffer 253.

  In FIG. 11B, an amplifier PMOS transistor 255 and an amplifier NMOS transistor 256 are connected to form an analog amplifier output stage. More specifically, the amplifier PMOS transistor 255 has a power supply voltage VDD input to the source, an input signal input to the gate, and a drain connected to the PAD 22. The amplifier NMOS transistor 256 has a drain connected to the PAD 22, an input signal input to the gate, and a ground voltage GND input to the source. The drains of the amplifier PMOS transistor 255 and the amplifier NMOS transistor 256 are connected to each other.

  Input signals divided in parallel are input to the gate and drain of the PMOS transistor 255 for amplifier. An input signal is input to the gate of the amplifier PMOS transistor 255 via the resistor 257 in the internal circuit 23, and input to the drain of the amplifier PMOS transistor 255 via the capacitor 258 and the resistor 259 in the internal circuit 23. A signal is input.

  Similarly, input signals separated in parallel are input to the gate and drain of the amplifier NMOS transistor 256. An input signal is input to the gate of the amplifier NMOS transistor 256 through the resistor 260 in the internal circuit 23, and input to the drain of the amplifier NMOS transistor 256 through the capacitor 261 and the resistor 262 in the internal circuit 23. A signal is input.

  Note that the protection PMOS transistor 263 and the protection NMOS transistor 264 in FIG. 11B are connected at their drains to the PAD 22 in the same manner as the output buffer circuit shown in FIG. In FIG. 11B, the signal line to which the drain of the protection PMOS transistor 263 and the drain of the protection NMOS transistor 264 are connected is a signal to which the drain of the amplifier PMOS transistor 255 and the drain of the amplifier NMOS transistor 256 are connected. It is connected in parallel with the line and connected to the PAD 22. With this connection configuration, even when an abnormal current flows from the PAD 22 in FIG. 11B, an abnormal current flows through the protective PMOS transistor 263 and the protective NMOS transistor 264, so that no abnormal current flows into the internal circuit 23 side. The internal circuit 23 can be protected.

  11A and 11B, resistors 249, 251, 252, 254, 257, 259, 260, and 262 are resistance elements in the resistance region 231, and capacitors 258 and 261 are in the capacitance region 240. It is a certain capacitive element. The amplifier PMOS transistor 255 is an element constituting the PMOS transistor region 233, and the amplifier NMOS transistor 256 is an element constituting the NMOS transistor region 236. The protection PMOS transistor 263 is an element constituting the PMOS transistor region 234, and the protection NMOS transistor 264 is an element constituting the NMOS transistor region 235. A guard ring is provided around each of the amplifier PMOS transistor 255, the amplifier NMOS transistor 256, the protection PMOS transistor 263, and the protection NMOS transistor 264.

  The switching PMOS transistor 247 and the switching NMOS transistor 248 in FIG. 11A and the amplifier PMOS transistor 255 and the amplifier NMOS transistor 256 in FIG. 11B are the output PMOS transistor 243 and the output NMOS transistor in FIG. Like 244, it is a transistor with a small W size. The W size of the switch PMOS transistor 247 and the amplifier PMOS transistor 255 is 20 μm, and the W size of the switch NMOS transistor 248 and the amplifier NMOS transistor 256 is 10 μm. In FIG. 11A, five switching PMOS transistors 247 and switching NMOS transistors 248 are connected in parallel. In FIG. 11B, ten amplifier PMOS transistors 255 and amplifier NMOS transistors 256 are connected in parallel. In this way, by connecting a plurality of small W-size MOS transistors in parallel, the W size required for the function of the CMOS transfer gate or the analog amplifier output stage is realized. Note that the W size and the number of connections of the protection PMOS transistor 263 and the protection NMOS transistor 264 are the same as those of the protection PMOS transistor 241 and the protection NMOS transistor 242.

  In the second embodiment described above, unlike the first embodiment, a special electrostatic protection transistor is not provided in the element array portion of the internal circuit 23 and is not used for the circuit operation of the internal circuit 23. Transistors in the element array section are used. Further, the transistors in the input / output buffer are not arranged in the I / O cell, and the transistors in the element array portion that are not used for the circuit operation of the internal circuit 23 are used. Therefore, as compared with the chip of the first embodiment, it is not necessary to provide a transistor for electrostatic protection and a transistor for an input / output buffer, so that the effective element arrangement region can be further increased.

  FIG. 12 shows an increased effective area 27 when the chip 20 shown in FIG. 8 is compared with the conventional chip 40 shown in FIG. By mounting elements in the effective area 27, the number of effective elements that can be mounted per chip area can be increased, so that the number of circuits that can be configured can be increased.

  On the contrary, if the number of effective elements mounted on the chip is the same as the conventional one, the chip area can be reduced. Thereby, the cost of the chip manufacturing process in the master slice method can be reduced.

  Furthermore, in the second embodiment, the transistors arranged in an array in the internal circuit 23 can be applied to transistors constituting a logic output buffer, a transfer gate, and an analog output in addition to the protective element. . Transistors arranged in an array in the chip 20 (internal circuit 23) have a smaller W size than transistors dedicated to input / output buffers arranged in I / O cells. Therefore, an optimal size and number of transistors can be selected and applied to circuits for various purposes. As described above, as in the conventional chip 40 shown in FIG. 19, the I / O cell 42 is provided with transistors dedicated to the respective functions such as an input / output protection transistor and an input / output buffer transistor. In comparison, the versatility of the transistor is improved.

  Furthermore, the use efficiency of the transistors on the chip can be increased. The transistors arranged in an array in the internal circuit 23 are set to an optimum size according to the application and performance of the chip 20 when manufactured in advance by the master slice method. When this transistor is not used in the circuit operation of the internal circuit 23, it can be diverted to an element of a circuit having another function such as an output buffer, a transfer gate, or an analog output, so that the use efficiency of the transistor can be improved.

  Here, the transistor is described as an example of the element, but the same effect can be obtained even when other general-purpose elements such as a diode are arranged in an array in the internal circuit 23.

Embodiment 3
The chip according to the third embodiment is obtained by replacing the protective P / NMOS transistors arranged in parallel in the array arrangement region of the internal circuit 13 according to the first embodiment with a protective diode or a Zener diode.

  FIG. 13 is a schematic diagram illustrating an example of an arrangement structure of array elements of the internal circuit 13 according to the third embodiment. The internal circuit 13 includes a resistance region 131, PMOS transistor regions 132, 133, 134, NMOS transistor regions 135, 136, 137, a resistance region 138, a protection diode region 146, a diode region 140, and a capacitance region 141. In each part of the internal circuit 13, elements constituting each part are arranged in parallel.

  FIG. 14 is a configuration diagram showing a specific example of the element arrangement of the internal circuit 13. In the protective diode region 146, protective diodes or Zener diodes are arranged in a line in an array. In the resistance region 131 to the capacitance region 141, elements such as a resistor, a PMOS transistor, an NMOS transistor, a protective diode, a diode, and a capacitor are arranged in an array as in FIG.

  Since the overall view of the LSI chip according to the third embodiment is the same as that of the first embodiment, description thereof is omitted.

  FIG. 15 is a configuration diagram of an equivalent circuit of the output buffer when an output buffer output to an external terminal is configured based on the configuration of the internal circuit 13 illustrated in FIGS.

  The protection diode 147 and the protection diode 148 in FIG. 15 correspond to the protection PMOS transistor 144 and the protection NMOS transistor 145 in FIG. Note that the protection diode 147 and the protection diode 148 are elements constituting the protection diode region 146. Other parts of the output buffer in FIG. 15 are the same as those in FIG.

  The chip according to the third embodiment described above has the same effect as the chip according to the first embodiment.

Embodiment 4
The fourth embodiment will be described below with reference to the drawings. FIG. 16 is an overall view of an LSI chip according to the fourth embodiment, and shows an overall image of the arrangement of elements constituting the LSI. In the chip 30 of FIG. 4, an I / O cell 32 and an internal circuit 33 are mounted on a semiconductor substrate 31. The I / O cells 32 are arranged in an array on the periphery of the chip 30 (semiconductor substrate 31) so as to surround the four sides of the internal circuit 33.

  The I / O cell 32 includes only an input / output buffer 321 and a PAD 322. The input / output buffer 321 and the PAD 322 are arranged on the chip 30 in the same manner as the input / output buffer 121 and the PAD 122 described in the first embodiment.

  The internal circuit 33 is an element array portion provided inside the chip 30 (semiconductor substrate 31) and having elements arranged in an array. The internal circuit 33 includes a power element region 34 and an array element region 35.

  In the power element region 34, a power PMOS transistor, a power NMOS transistor, a resistor, a protection diode, and the like, which are dedicated elements for power control, are mounted. FIG. 17 is a configuration diagram showing a specific example of the element arrangement in the power element region 34. In FIG. 17, the power element region 34 includes a protection diode region 341, a power PMOS transistor region 342, a resistance region 343, a power NMOS transistor region 344, and a protection diode region 345. In the protective diode regions 341 and 345, protective diodes are arranged in two rows in an array. In the power PMOS transistor region 342, power PMOS transistors are arranged in a line in an array. In the resistance region 343, resistors are arranged in an array in a line. In the power NMOS transistor region 344, power NMOS transistors are arranged in an array in a line. The elements in these parts are larger in size than the elements provided in the array element region 35. The protective diode can be replaced with a protective MOS transistor.

  In the array element region 35, other small elements having no power control function are arranged in an array.

  18A and 18B are configuration examples of an equivalent circuit of an output buffer in which the output of the power element region 34 is connected to an external terminal based on the configuration of the power element region 34 shown in FIGS. .

  The output buffer of FIG. 18A is the same as the output buffer of FIG. 10 except that the protection PMOS transistor 241 and the protection NMOS transistor 242 in the output buffer of FIG. 10 are replaced with a protection diode 348 and a protection diode 349. The circuit configuration is almost the same. 18B is a circuit in which the protection diode 348 and the protection diode 349 of FIG. 18A are replaced with a protection PMOS transistor 353 and a protection NMOS transistor 354, and is substantially the same circuit as the output buffer of FIG. It has a configuration.

  Note that the output PMOS transistor 351 and the output NMOS transistor 352 in FIGS. 18A and 18B correspond to the output PMOS transistor 243 and the output NMOS transistor 244 in the second embodiment. The output PMOS transistor 351 is a power element in the power PMOS transistor region 342, and the output NMOS transistor 352 is a power element in the power NMOS transistor region 344.

  In the configuration of the chip 30 shown in FIGS. 17 and 18, an internal circuit in which a large-size power element is arranged in parallel with a large-size electrostatic protection diode conventionally provided in an I / O cell. In parallel with the power element region 34 in 33. Thereby, in the power element region 34 and the array element region 35, the sizes of the elements arranged in parallel can be made relatively uniform. Therefore, compared with the case where elements of various sizes are arranged in parallel in the internal circuit 33, the area on the chip necessary for arranging the diodes for electrostatic protection in parallel can be reduced. . Thereby, compared with the conventional chip 40 described in FIGS. 19 and 20, the chip area occupied by the diode for electrostatic protection is reduced. As described above, since the number of effective elements that can be mounted per chip area can be increased, the same effect as in the first embodiment can be obtained.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, although the I / O cell 12 in the first embodiment includes only the input / output buffer 121 and the PAD 122, other elements other than the electrostatic protection element may be arranged in the I / O cell 12.

  In addition, the master slice semiconductor integrated circuit described in any of Embodiments 1 to 4 can be understood as an invention of a manufacturing method. For example, the layout method of the chip 10 shown in the first embodiment (FIG. 1) is as follows. First, an internal circuit 13 having a plurality of electrostatic protection elements (protective P / NMOS transistor regions) arranged in a line is disposed in the central portion of the semiconductor substrate 11. Next, a plurality of input / output PADs 122 are arranged around the internal circuit 13. A plurality of input / output buffers 121 are disposed between the internal circuit 13 and each of the plurality of input / output PADs 122. In this manner, a master slice type semiconductor integrated circuit can be manufactured. The order in which the elements are arranged is not limited to this method. Further, the chips shown in Embodiments 2 to 4 can be manufactured by a similar method.

10 chip 11 semiconductor substrate 12 I / O cell 121 input / output buffer 122 PAD
123 PMOS transistor for output 124 NMOS transistor for output 13 Internal circuit 131, 138 Resistance regions 132, 133, 134 PMOS transistor regions 135, 136, 137 NMOS transistor region 139 P / NMOS transistor region for protection 140 Diode region 141 Capacitance region 142 Buffer 143 Inversion buffer 144 Protection PMOS transistor 145 Protection NMOS transistor 146 Protection diode region 147, 148 Protection diode 15 Effective area 20 Chip 21 Semiconductor substrate 22 PAD
23 Internal circuit 231, 238 Resistance region 232, 233, 234 PMOS transistor region 235, 236, 237 NMOS transistor region 239 Diode region 240 Capacity region 241 Protection PMOS transistor 242 Protection NMOS transistor 243 Output PMOS transistor 244 Output NMOS transistor 245 Buffer 246, 250, 253 Inversion buffer 247 Switch NMOS transistor 248 Switch PMOS transistor 249, 251, 252, 254, 257, 259, 260, 262 Resistor 255 Amplifier PMOS transistor 256 Amplifier NMOS transistor 258, 261 Capacitor 263 Protective PMOS transistor 264 Protective NMOS transistor 27 Effective area 30 31 Semiconductor substrate 32 I / O cell 321 I / O buffer 322 PAD
33 Internal circuit 34 Power element region 341 Protection diode region 342 Power PMOS transistor region 343 Resistance region 344 Power NMOS transistor region 345 Protection diode region 346 Buffer 347 Inversion buffer 348, 349 Protection diode 35 Array element region 351 Output PMOS transistor 352 Output NMOS transistor 353 Protection PMOS transistor 354 Protection NMOS transistor

Claims (5)

An internal circuit disposed in the center of the semiconductor substrate;
A plurality of input / output pads disposed on the periphery of the internal circuit;
A plurality of input / output buffers disposed between the internal circuit and each of the plurality of input / output pads;
The internal circuit has a plurality of electrostatic protection elements arranged in a line,
Master slice semiconductor integrated circuit. No electrostatic protection element is provided between the plurality of input / output pads and the plurality of input / output buffers.
The semiconductor integrated circuit according to claim 1. The internal circuit is
An array element region having array elements arranged in parallel;
A power element arrangement region having a power element,
The plurality of electrostatic protection elements arranged in parallel in the row are provided in the power element region,
The semiconductor integrated circuit according to claim 1. The plurality of input / output buffers;
The plurality of electrostatic protection elements connected to each of the plurality of input / output buffers,
Configure the input / output circuit,
The semiconductor integrated circuit according to claim 1. The electrostatic protection element includes a PMOS transistor and an NMOS transistor, each of which is diode-connected.
The semiconductor integrated circuit according to claim 1.

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