TWM473610U - Transistor structure - Google Patents

Transistor structure Download PDF

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Publication number
TWM473610U
TWM473610U TW102215609U TW102215609U TWM473610U TW M473610 U TWM473610 U TW M473610U TW 102215609 U TW102215609 U TW 102215609U TW 102215609 U TW102215609 U TW 102215609U TW M473610 U TWM473610 U TW M473610U
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TW
Taiwan
Prior art keywords
pad
transistor
die
electrically
lead
Prior art date
Application number
TW102215609U
Other languages
Chinese (zh)
Inventor
Kuo-Fan Lin
Chi-Shang Lin
Original Assignee
Fsp Technology Inc
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Publication date
Priority to US201161533796P priority Critical
Priority to US201261682319P priority
Application filed by Fsp Technology Inc filed Critical Fsp Technology Inc
Publication of TWM473610U publication Critical patent/TWM473610U/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/4813Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A transistor structure includes a chip package and two pins, wherein the chip package includes a transistor die and a molding compound encapsulating the transistor die. One of the pins is electrically connected to a first bonding pad and a second bonding pad of the transistor die, and another of the pins is electrically connected to a third bonding pad of the transistor die. The transistor structure may be employed in a snubber circuit to connect an active component or a load in parallel to absorb spikes or noise generated by the active component while the active component is switching at a high frequency. Therefore, the packaging of the transistor structure could simplify the process, reduce size, increase the withstanding voltage, and improve the efficiency and reduce the spike voltage of the power supply of the snubber circuit.

Description

Crystal structure
The present invention relates to a crystal structure, and more particularly to a transistor structure having a two-lead leg.
In recent years, as the technology of electronic circuits has been continuously developed, various protection circuits for electric/electronic components have been widely implemented in many applications. In the conventional protection circuit, for example, an RCD damper circuit, as shown in FIG. 19, after the resistor R6 is connected to the capacitor C12, the diode D11 is connected in series to form an RCD damper circuit 400. However, the RCD damper circuit has high energy loss, low efficiency, and high surge voltage value, so the conventional RCD damper circuit is liable to cause damage to the semiconductor component. Therefore, there is a need for a novel electronic component that can replace the diode D11 to enhance the circuit protection performance of the damper circuit.
One of the aims of the present invention is to provide a transistor structure that can be used in a damper circuit to allow the damper circuit to effectively protect components and improve efficiency.
One of the purposes of this creation is to provide a transistor structure that simplifies the process, reduces the volume, and increases the withstand voltage.
In order to achieve the above object, the transistor structure of the present invention comprises a chip package and a second lead, wherein the chip package system comprises an oxide crystal grain and an encapsulant covering the crystal grain; and the conductive guide One of the first leg of the foot is electrically connected to the first pad and the second pad of the transistor die, and the second leg of the pin is electrically connected to the third pad of the transistor die pad.
The transistor structure as described above, wherein the first lead or the second lead of the transistor structure is connected to one end of a capacitor to form a snubber circuit to be connected to an active component or a load.
The transistor structure as described above, wherein the chip package further comprises a capacitor die, wherein the first pad of the capacitor die is electrically connected to the first pad or the third pad of the transistor die, The second pad of the capacitor die is electrically connected to the first lead or the second lead, and the encapsulant system covers the capacitor die.
The transistor structure as described above, wherein the chip package further comprises a Zener Diode die, wherein the first pad of the Zener diode die is electrically connected to the capacitor die a first pad or a first pad or a third pad of the transistor die, and a second pad of the Zener diode die is electrically connected to the second pad of the capacitor die or the a first pad or a third pad of the transistor die, and the encapsulant system encapsulates the Zener diode die.
The transistor structure as described above, wherein the chip package further comprises a resistor die, wherein the first pad of the resistor die is electrically connected to the first pad or the third pad of the transistor die, The second pad of the resistor die is electrically connected to the first pad of the capacitor die, and the package system covers the resistor die
The transistor structure as described above, wherein one end of the capacitor is further connected to one end of a Zener diode, and the other end of the capacitor is connected to the other end of the Zener diode to form a damping circuit to be connected in an active manner. Component or a load.
The transistor structure as described above, wherein the first lead or the second lead of the transistor structure is connected to one end of a resistor, and the other end of the resistor is connected to one end of a capacitor to form a damping circuit. Connect an active component or a load.
The transistor structure as described above, wherein the active device is a metal oxide semiconductor field effect transistor (MOSFET), a diode, a bipolar junction transistor (BJT), and an insulating gate double A polar transistor (IGBT), an electrostatic induction transistor (SIT), a thyristor or a circuit thereof, and the load is an inductor, a resistor, a capacitor or a circuit thereof.
The transistor structure as described above, wherein the transistor crystal grain is a bipolar junction transistor crystal grain.
a transistor structure as described above, wherein the first pad of the transistor die For an emitter pad, the second pad is a base pad, and the third pad is a collector pad.
The transistor structure as described above, wherein the chip package further comprises a wafer holder, and the transistor crystal grain is disposed on the wafer holder through an adhesive layer.
Thereby, the transistor structure of the present invention is electrically connected to the first pad and the second pad of the transistor die by using a lead pin, and the other lead is electrically connected to the third pad of the transistor die. Pad, the transistor structure can be used in the damper circuit, or the damper circuit can be directly packaged in the two-lead transistor structure to connect an active component or a load, and the absorbing active component can be switched at high frequency. The surge or noise generated makes the transistor structure on the package to simplify the process, reduce the volume and increase the withstand voltage, and can improve the efficiency and reduce the surge voltage by using the power supply of the damper circuit. The effect.
It is to be understood that the foregoing general description and the following claims
1‧‧‧ chip package
11‧‧‧Optocrystalline grains
111, 131, 141‧‧‧ first pad
112, 132, 142‧‧‧second solder pads
113‧‧‧ Third pad
114‧‧‧fourth pad
12‧‧‧Package colloid
13‧‧‧Capacitor crystal
14‧‧‧Zina diode grain
151~153‧‧‧ wire
16‧‧‧Adhesive layer
17‧‧‧ Wafer holder
18‧‧‧ solder
181‧‧‧First solder
182‧‧‧second solder
183‧‧‧ Third solder
184‧‧‧fourth solder
2, 3‧‧ ‧ lead
Q‧‧‧Optocrystal structure
C‧‧‧ capacitor
D‧‧‧Zina diode
The first A diagram is a schematic diagram of the structure of the transistor of the first embodiment of the creation.
The first B diagram is a schematic diagram of the structure of the transistor of the second embodiment of the creation.
The first C diagram is a schematic diagram of the structure of the transistor of the third embodiment of the creation.
The second A picture is a schematic diagram of the transistor crystal grain of the present invention being a bipolar junction transistor crystal grain.
The second B diagram is a schematic diagram of the transistor crystal grains of the present invention being bipolar junction transistor crystal grains.
The second C picture is a schematic diagram of the bipolar junction transistor die and the capacitor die connection.
The second D picture is a schematic diagram of the bipolar junction transistor crystal grain and the capacitor die and the Zener diode connected.
The third to seventh figures are schematic cross-sectional views of the transistor packages of the embodiments in which the lead wires and the pads are electrically connected by wire bonding.
The eighth to ninth drawings are schematic cross-sectional views of the transistor packages of the embodiments in which the lead pins and the pads are electrically connected by a flip chip bonding method.
10A to 11D are perspective views of the transistor package of the respective embodiments of the present invention.
The twelfth figure is the damper circuit to which the present transistor structure is applied.
The thirteenth figure is a flow chart of the first embodiment of the present invention.
The fourteenth embodiment is a flow chart of the second embodiment of the present invention.
The fifteenth figure is a flow chart of the third embodiment of the present invention.
The sixteenth embodiment is a flow chart of the fourth embodiment of the present invention.
The seventeenth embodiment is a flow chart of the fifth embodiment of the present invention.
The eighteenth figure is a flow chart of the sixth embodiment of the present invention.
The nineteenth diagram is a schematic diagram of a conventional RCD damper circuit.
Other features and embodiments of the present invention can be further understood from the following detailed description in conjunction with the drawings.
Referring to FIG. 1A, it is a schematic diagram of a transistor structure according to a first embodiment of the present invention. The transistor structure of the present invention comprises a chip package 1 and two lead pins 2, 3, wherein the chip package 1 The method includes a transistor die 11 and a package colloid 12 covering the transistor die 11; and a lead 2 electrically connected to the first pad 111 and the second pad 112 of the transistor die 11 The leg 3 is electrically connected to the third pad 113 of the transistor die 11.
The transistor crystal 11 of the transistor structure of the embodiment is a Bipolar Junction Transistor (BJT) crystal, and the bipolar junction crystal grain system can be an NPN bipolar. The junction transistor crystal grain or a PNP type bipolar junction transistor crystal grain, please refer to the first figure, the second A picture and the second B picture, the first pad 111 of the transistor crystal grain 11 It is an emitter (Emitter) pad, the second pad 112 is a base pad, and the third pad 113 is a collector pad, wherein the emitter pad is soldered. The pad and the base pad are electrically connected to the lead 2, and the collector pad is electrically connected to the lead 3.
Therefore, the base of the bipolar junction transistor crystal grain of the embodiment is electrically connected to the emitter system, and based on at least one junction characteristic between the base and the collector of the bipolar junction transistor crystal grain, The transistor structure has the characteristics of fast conduction, slow recovery time, moderate relaxation, and small base-collector junction capacitance C bc , and the transistor structure can be utilized as a fast diode for one Damper circuit.
The damper circuit can be configured as follows: (1) a CB damper circuit, which is connected to one end of a capacitor by using a lead 2 or a lead 3 of the transistor structure of the embodiment to form a damper circuit to be connected one after another. An active component or a load (not shown); (2) a ZCB damper circuit, which is connected to one end of a capacitor C and a Zener diode D by using a lead 2 or a lead 3 of the transistor structure Q of the present embodiment. One end, and the other end of the capacitor C is connected to the other end of the Zener diode D to form a damper circuit (as shown in FIG. 12) to be connected with an active component or a load; (2) The RCB damper circuit is connected to one end of a resistor by using the lead 2 or the lead 3 of the transistor structure of the embodiment, and the other end of the resistor is connected to one end of a capacitor to form a damper circuit for parallel connection. An active component or a load (not shown).
The active component is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a diode, a bipolar junction transistor (BJT), and an insulated gate bipolar. a transistor (IGBT), an electrostatic induction transistor (SIT), a thyristor or a circuit thereof, and the load is an inductor, a resistor, a capacitor or a circuit thereof, for example, a damper circuit and an exchange The primary side of the transformer of the power supply is connected in parallel with a metal oxide semiconductor field effect transistor, or the secondary side of the transformer of the damper circuit and the switching power supply, and a metal oxide semiconductor field effect transistor Parallel connection, or the damper circuit is connected with a metal oxide semiconductor field effect transistor and connected to the secondary side of the transformer of the switching power supply, and can absorb the surge generated by the active component during high frequency switching. (spike) or noise, thereby reducing the surge voltage generated by the active device and improving efficiency.
Referring to Table 1 and Table 2, Table 1 is the experimental test result of the conventional RCD damper circuit, and Table 2 is the experimental test result of the transistor structure of the present embodiment used for the above-mentioned RCB damper circuit, and The RCD damper circuit and the RCB damper circuit are both connected to the primary side of a transformer and a metal oxide semiconductor field effect transistor Serial connection, the test results listed in Table 1 and Table 2, this experiment can confirm that the RCB damper circuit of this embodiment (the test result is Table 2) is much more efficient than the conventional RCD damper circuit (the test result is a table) 1) Efficiency. In particular, the damper circuit is electrically connected to a light load, wherein the light load of the present invention is a percentage of the specified load (Percent of Rated Load) is small (equal) to 20%, that is, the load accounts for 20% of the full load. Below %, for example, the percentage of the specified load is 1% to 20%; and when the percentage of the specified load is 1%, Table 2 (RCB damper circuit) can be increased by 10.75 compared to Table 1 (RCD damper circuit). The efficiency of % (57.84% → 68.59%), and also the percentage of the specified load is 20%, Table 2 can also increase the efficiency of 1.23% (88.22% → 89.45%) compared with Table 1.
Thereby, the RCB damper circuit of the embodiment can achieve the effect of improving efficiency under light load compared with the conventional RCD damper circuit, wherein the damper circuit 300A of the embodiment has obvious efficiency except for light load. In addition, the Average_Efficiency of Tables 1 and 2 shows that the average efficiency during heavy load (25%~100%) is slightly increased by 0.3%. Therefore, the power supply using the present transistor structure as the damper circuit has higher conversion efficiency than the power supply using the RCD damper circuit, especially in the case of light load.
Referring to FIG. 2B, it is a schematic diagram of a transistor structure according to a second embodiment of the present invention. The transistor structure of the present invention comprises a chip package 1 and two lead pins 2 and 3. The chip package 1 includes a transistor die 11 , a capacitor die 13 , and a package colloid 12 covering the transistor die 11 and the capacitor die 13 . The transistor die 11 is the third. The pad 113 is electrically connected to the first pad 131 of the capacitor die 13 , and the pin 2 is electrically connected to the first pad 111 and the second pad 112 of the transistor die 11 , and the other pin 3 is electrically connected to the second pad 132 of the capacitor die 13; wherein, the transistor structure of the embodiment can electrically charge the first pad 111 (or the second pad 112) of the transistor die 11 The first pad 131 of the capacitor die 13 is connected, and the pin 2 is electrically connected to the second pad 132 of the capacitor die 13. The other leg 3 is electrically connected to the third die of the transistor die 11. Pad 113 (not shown), but not limited thereto; please refer to FIG. 2C at the same time, the transistor crystal 11 of the embodiment is a Bipolar Junction Transistor (BJT) crystal. The bipolar junction transistor crystal grain may be an NPN type bipolar junction transistor crystal grain or a PNP type bipolar junction transistor crystal grain.
Therefore, the base of the bipolar junction transistor crystal grain of the embodiment is electrically connected to the emitter system, and based on at least one junction characteristic between the base and the collector of the bipolar junction transistor crystal grain, The transistor structure has the characteristics of fast conduction, slow recovery time, moderate relaxation, and small base-collector junction capacitance C bc , and the transistor crystal grain can be utilized as a fast diode and transmitted through the capacitor die. The electrical connection makes the transistor structure form a CB damper circuit. Therefore, the transistor structure can achieve the effects of simplifying the process, reducing the volume, and increasing the withstand voltage in the use of the package and the application circuit; wherein the CB damper circuit An active component or a load (not shown) may be connected in parallel. The active component is a metal oxide semiconductor field effect transistor (MOSFET), a diode, and a bipolar junction transistor (BJT). An insulating gate bipolar transistor (IGBT), an electrostatic induction transistor (SIT), a gate fluid or a circuit thereof, and the load is an inductor, a resistor, a capacitor or a circuit thereof, for example The CB damper circuit is in contact with The primary side of the transformer of the power supply is connected in parallel with a gold-oxygen half-field effect transistor, and can absorb the spike or noise generated by the active component during high-frequency switching, thereby reducing the initiative. The surge voltage generated by the component and improved efficiency.
The chip package 1 of the transistor structure of the present embodiment may include a resistor die, and the resistor die is connected in series between the transistor die 11 and the capacitor die 13 . That is, the first pad of the resistor die is electrically connected to the first pad 111 or the third pad 113 of the transistor die 11, and the second pad of the resistor die is electrically connected to the capacitor. a first pad 131 (not shown) of the die 13 , and the encapsulant 12 encapsulates the resistor die to form an RCB damper circuit, so that the transistor structure is encapsulated and applied It can be used to simplify the process, reduce the volume and increase the pressure distance.
Please refer to the first C figure, which is a schematic diagram of a transistor structure according to a third embodiment of the present invention. The transistor structure of the present invention comprises a chip package 1 and two lead pins 2, 3, wherein the chip package 1 The method includes a transistor crystal grain 11 , a capacitor die 13 , a Zener diode die 14 , and a cladding of the transistor die 11 , the capacitor die 13 and the Zener diode die 14 . The third bonding pad 113 of the transistor die 11 is electrically connected to the first pad 131 of the capacitor die 13 and the first pad 141 of the Zener diode die 14; The foot 2 is electrically connected to the first pad 111 and the second pad 112 of the transistor die 11 , and the other pin 3 is electrically connected to the second pad 132 of the capacitor die 13 and the Zener II The second pad 142 of the electrode body 14; wherein the transistor structure of the embodiment can electrically connect the first pad 111 of the transistor die 11 and the second pad 112 to the capacitor die 13 The first pad 131 and the first pad 141 of the Zener diode die 14 , and the pin 2 is electrically connected to the second pad 132 of the capacitor die 13 and the Zener diode die 14 Two pads 142, other guide pin 3 electrically connected to the third electrical bonding pad 113 of 11 crystal grains.
That is, the Zener diode die 14 is connected to the capacitor die 13 in parallel with the capacitor die 13 , but not limited thereto. The Zener diode of the embodiment is not limited thereto. The second pad 142 of the die 14 is electrically connected to the first pad 111 or the third pad 113 of the transistor die 11, that is, the Zener diode die 14 can be connected to the transistor crystal. After the particles 11 are connected, the capacitor die 13 is connected in series; please refer to the second D diagram, the transistor crystal 11 of the embodiment is a Bipolar Junction Transistor (BJT) crystal. The bipolar junction transistor crystal grain may be an NPN type bipolar junction transistor crystal grain or a PNP type bipolar junction transistor crystal grain.
Therefore, the base of the bipolar junction transistor crystal grain of the embodiment is electrically connected to the emitter system, and based on at least one junction characteristic between the base and the collector of the bipolar junction transistor crystal grain, The transistor structure has the characteristics of fast conduction, slow recovery time, moderate relaxation, and small base-collector junction capacitance C bc , and the transistor crystal can be used as a fast diode and transmitted through the capacitor die, The electrical connection of the Zener diode dies allows the transistor structure to form a ZCB damper circuit (as shown in Figure 12). Therefore, the transistor structure can achieve a simplified process in the use of package and application circuits. The effect of reducing the volume and increasing the withstand voltage distance; wherein the ZCB damper circuit can be connected to an active component or a load (not shown), the active component is a metal oxide semiconductor field effect transistor (MOSFET), a diode, a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT), an electrostatic induction transistor (SIT), a thyristor or a circuit thereof, and the load Is an inductor, a resistor, a capacitor or a component thereof The circuit, for example, the ZCB damper circuit is connected in parallel with the primary side of the transformer of the switching power supply, and is connected in series with a metal oxide semiconductor field effect transistor, and the absorbing active element is generated when the high frequency is switched. Spiral or noise, which reduces the surge voltage and improves efficiency.
In addition, as shown in the third to seventh embodiments, the transistor structure of the first embodiment is electrically connected by a wire bonding method to each of the embodiments of the transistor and the pad. The transistor structure includes a chip package 1 and two lead pins 2 and 3, wherein the chip package 1 includes an oxide crystal chip 11, an encapsulant 12, an adhesive layer 16, a wafer holder 17, and The plurality of wires 151, 152, and 153 are connected to the first pad 111, the second pad 112, the third pad 113, and the lead pin 2 of the transistor die 11 through a plurality of wires 151, 152, and 153. 3, so that the transistor die 11 is electrically connected to the leads 2, 3; wherein the pins 2, 3 can be respectively provided with at least one contact (not shown) for electrically connecting the wires 151 152, 153, and the transistor die 11 is disposed on the wafer holder 17 through the adhesive layer 16, the encapsulant 12 coating the transistor die 11, the adhesive layer 16, the wafer holder 17, the wires 151, 152, 153 and one of the lead pins 2, 3, and partially enclose the portions of the lead pins 2, 3 in the encapsulant 12, and one end of each of the pins 2, 3 is exposed to the outside of the encapsulant 12, wherein the wire 151, 152, 153 can be a gold wire or other conductive material, and the adhesive layer 16 can be a silver Glue or other conductive colloid, the material of the encapsulant 12 may be epoxy or other Polymer Materials.
Referring to the third figure, the two ends of the wire 151 of the embodiment are electrically connected to the lead pin 2 and the second pad 112. The two ends of the wire 152 are electrically connected to the lead pin 2 and the first pad 111. Therefore, the first pad 111 and the second pad 112 are short-circuited at both ends, and the lead 153 is electrically connected between the lead 3 and the third pad 113. Further, the lead 2 and 3 are self-packaging colloids. The two sides of the 12 are horizontally extended, and the lead pins 2, 3 are parallel to the wafer holder 17, and the package appearance form of the crystal structure can be the appearance type as shown in the tenth to tenth Dth drawings. The shape of the encapsulant 12 can be cylindrical, semi-circular or flat, and the lead 153 can be a long lead, a short lead, a leadless or other contact type.
Referring to the fourth figure, the two ends of the wire 151 of the embodiment are electrically connected to the lead pin 2 and the second pad 112. The two ends of the wire 152 are electrically connected to the lead pin 2 and the first pad 111. Therefore, the first pad 111 and the second pad 112 are short-circuited at both ends, and the lead 153 is electrically connected between the lead 3 and the third pad 113. Further, the lead 2 and 3 are self-packaging colloids. The two sides of the 12 are extended downwards, so that the lead pins 2, 3 are perpendicular to the wafer holder 17, and the package appearance of the crystal structure can be as shown in FIG. 11A to FIG. The appearance of the encapsulant 12 can be cylindrical, semi-circular or flat, and the lead 15 can be a long lead, a short lead, a leadless or other contact type.
Referring to FIG. 5, the first pad 111 and the second pad 112 are electrically connected to both ends of the wire 151 of the embodiment, thereby short-circuiting the two ends of the first pad 111 and the second pad 112. The lead 152 is electrically connected to the lead 2 and the first pad 111, and the lead 153 is electrically connected between the lead 3 and the third pad 113. Further, the lead 2 and 3 are self-contained. The two sides of the encapsulant 12 are horizontally extended such that the leads 2, 3 are parallel to the wafer holder 17.
Referring to FIG. 6 , the first pad 111 and the second pad 112 are electrically connected to both ends of the wire 151 of the embodiment, thereby short-circuiting the two ends of the first pad 111 and the second pad 112 . The lead wires 152 are electrically connected to the lead pins 2 and the wires 151, and the lead wires 153 are electrically connected to the lead pins 3 and the third pads 113.
Please refer to the seventh figure, this embodiment is electrically transmitted through a fourth pad 114. The first pad 111 and the second pad 112 are connected to each other, thereby short-circuiting the two ends of the first pad 111 and the second pad 112. The two ends of the wire 152 are electrically connected to the lead 2 and the fourth pad. 114, and the two ends of the wire 153 are electrically connected to the lead pin 3 and the third pad 113.
Please refer to the eighth embodiment and the ninth embodiment at the same time. The transistor structure of the first embodiment is electrically connected to each of the embodiments of the transistor and the pad by a flip chip bonding. The transistor structure includes a chip package 1 and two lead pins 2, 3, wherein the chip package 1 includes an oxide crystal die 11, an encapsulant 12, and a solder 18, which are in the first solder. Solder 18 is formed on the surface of the pad 111 and the second pad 112. Then, after the transistor crystal grains are flipped, the first pad 111 and the second pad 112 of the transistor die 11 are connected through the solder 18. The third pad 113 and the lead pins 2 and 3 are electrically connected to the lead wires 2 and 3; wherein the lead pins 2 and 3 are respectively provided with at least one contact point (not shown). ) for electrically connecting the solder 18, and the encapsulant 12 covers the transistor die 11, the solder 18, and a portion of the pins 2, 3, and burying portions of the legs 2, 3 Embedded in the encapsulant 12, and one end of each of the leads 2, 3 is exposed to the outside of the encapsulant 12, wherein the material of the solder 18 System may be tin or other metallic materials.
Referring to FIG. 8 , the solder 18 of the present embodiment includes a first solder 181 , a second solder 182 , and a third solder 183 . The first solder 181 electrically connects the lead pin 2 and the third pad 113 . The second solder 182 and the third solder 183 electrically connect the lead pins 3 to the first pads 111 and the second pads 112 , thereby short-circuiting the first pads 111 and the second pads 112 .
Referring to FIG. 9 , the solder 18 of the embodiment includes a first solder 181 and a fourth solder 184 . The first solder 181 electrically connects the lead 2 and the third pad 113 , and the fourth solder The 184 series electrically connects the lead pins 3 with the first pads 111 and the second pads 112, thereby short-circuiting the first pads 111 and the second pads 112.
Please refer to the third embodiment and the thirteenth embodiment. The first embodiment of the present invention relates to the first embodiment of the present invention. The first embodiment includes the following steps: first, providing a first pad 111, a second pad 112, and a third pad. 113 one of the crystal grains 11 (S100); then, in the first A lead 151, 152 is electrically connected to a first lead 2 (S102) on the surface of the pad 111 and the second pad 112. Then, a wire 153 is formed on the surface of the third pad 113. A second lead 3 is connected (S104). Finally, an encapsulant 12 is provided to cover the transistor die 11, the wires 151-153 and one of the leads 2, 3 (S106).
Please refer to FIG. 5 and FIG. 14 simultaneously. The second embodiment of the present invention relates to a method for packaging a transistor comprising the following steps: first, providing a first pad 111, a second pad 112, and a third pad And forming a wire 151 on the surface of the first pad 111 to electrically connect the second pad 112 (S202); then, on the first pad 111 or A wire 152 is electrically connected to the first lead 2 on the surface of the second pad 112 (S204). Then, a wire 153 is electrically connected to the second lead 3 on the surface of the third pad 113. (S206) Finally, an encapsulant 12 is provided to coat the transistor crystal grains 11, the wires 13 to 15 and a portion of the pins 2, 3 (S208).
Please refer to the sixth figure and the fifteenth figure at the same time, the third embodiment of the present invention relates to the following steps: First, providing a first pad 111, a second pad 112 and a third pad And forming a wire 151 on the surface of the first pad 111 to electrically connect the second pad 112 (S302); then, in a first lead 2 A wire 152 is formed on the surface to electrically connect the wire 13 (S304); then, a wire 153 is electrically connected to a second lead 3 on the surface of the third pad 113 (S306); finally, a package is provided. The colloid 12 covers the transistor crystal grains 11, the wires 151 to 153, and a portion of the pins 2, 3 (S308).
Please refer to the seventh embodiment and the sixteenth embodiment at the same time. The fourth embodiment of the present invention relates to the fourth embodiment of the present invention. The first embodiment includes the following steps: first, providing a first pad 111, a second pad 112, and a third pad. And forming a fourth pad 114 electrically connected to the first pad 111 and the second pad on the surface of the first pad 111 and the second pad 112; Pad 112 (S402); then, a wire 14 is electrically connected to a first lead 2 on the surface of the fourth pad 114 (S404); then, a wire is formed on the surface of the third pad 113. 15 electrically connecting a second lead 3 (S406); finally, providing an encapsulant 12 covering the transistor die 11, the fourth pad 114, the wires 14, 15 and one of the legs 2, 3 (S408).
Please refer to the eighth embodiment and the seventeenth embodiment. The fifth embodiment of the present invention relates to the fifth embodiment of the present invention. The first embodiment includes the following steps: first, providing a first pad 111, a second pad 112, and a third pad. a first transistor 182 and a second solder 183 are electrically connected to a first lead on the surface of the first pad 111 and the second pad 112, respectively. 2 (S502); then, a third solder 181 is electrically connected to a second lead 3 on the surface of the third pad 113 (S504); finally, an encapsulant 12 is provided to coat the transistor crystal grain. 11. The solder 18 and one of the leads 2, 3 (S506)
Please refer to the ninth diagram and the eighteenth embodiment at the same time, the sixth embodiment of the present invention, the method for packaging the transistor includes the following steps: first, providing a first pad 111, a second pad 112, and a third pad a first transistor 184 is electrically connected to a first lead 2 (S602); and then a fourth solder 184 is electrically connected to the surface of the first pad 111 and the second pad 112 (S602); A first solder 181 is electrically connected to a second lead 3 on the surface of the third pad 113 (S604). Finally, an encapsulant 12 is provided to cover the transistor die 11, the solder 181. , 184 and one of the guide legs 2, 3 (S606).
The transistor crystal grain described in each embodiment of the transistor packaging method is a bipolar junction transistor (BJT) die.
In summary, according to the above disclosure, the present invention can achieve the new intended purpose, which uses a lead to electrically connect the first pad and the second pad of the transistor die, and the other guide The foot is electrically connected to the third pad of the transistor die, and the transistor structure can be used in the damper circuit, or the damper circuit can be directly encapsulated in the two-lead transistor structure to connect an active component Or a load, which can absorb the glitch or noise generated by the active component during high-frequency switching, so that the transistor structure can achieve the functions of simplifying the process, reducing the volume, and increasing the withstand voltage on the package, and can be used. The damper circuit of the crystal structure can effectively protect the components, and the power supply using the damper circuit has higher conversion efficiency than the power supply using the conventional damper circuit, and has practical value, and has industrial applicability. , novelty and progressive elements, 提出 file a new type of patent application.
The above is only the preferred embodiment of the present invention, and all the equivalent design changes made according to the scope of the patent application of this creation should be covered by the technical scope of the present invention.
1‧‧‧ chip package
11‧‧‧Optocrystalline grains
111‧‧‧First pad
112‧‧‧Second pad
113‧‧‧ Third pad
12‧‧‧Package colloid
2, 3‧‧ ‧ lead

Claims (11)

  1. A transistor structure comprising: a chip package comprising an oxide crystal grain and a package colloid covering the transistor crystal grain; and a second lead leg, wherein a first lead leg is electrically connected to the electric The first pad and the second pad of the crystal grain are electrically connected to the third pad of the transistor die.
  2. The transistor structure of claim 1, wherein the chip package further comprises: a capacitor die, wherein the first pad of the capacitor die is electrically connected to the first die of the transistor die a pad or a third pad, wherein the second pad of the capacitor die is electrically connected to the first lead or the second lead, and the encapsulant system covers the capacitor die.
  3. The transistor structure of claim 2, wherein the chip package further comprises: a Zener Diode die, wherein the first pad of the Zener diode die is electrically The first pad of the capacitor die is connected to the first pad or the third pad of the transistor die, and the second pad of the Zener diode die is electrically connected to the capacitor die a second pad or a first pad or a third pad of the transistor die, and the encapsulant system encapsulates the Zener diode die.
  4. The transistor structure of claim 2, wherein the chip package further comprises: a resistor die, wherein the first pad of the resistor die is electrically connected to the first pad of the transistor die a pad or a third pad, wherein the second pad of the resistor die is electrically connected to the first pad of the capacitor die, and the encapsulant system covers the resistor die.
  5. The transistor structure of claim 1, wherein the first lead or the second lead of the transistor structure is connected to one end of a capacitor to form a snubber circuit to be connected in an active manner. Component or a load.
  6. The transistor structure of claim 5, wherein one end of the capacitor is further connected to one end of a Zener diode, and the other end of the capacitor is connected to the other end of the Zener diode to form a damping. The circuit is connected in parallel with an active component or a load.
  7. The transistor structure of claim 1, wherein the first lead or the second lead of the transistor structure is connected to one end of a resistor, and the other end of the resistor is connected to one end of a capacitor. A damper circuit is formed to connect an active component or a load.
  8. The transistor structure of claim 5, 6, or 7, wherein the active device is a metal oxide semiconductor field effect transistor (MOSFET), a diode, or a diode a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT), an electrostatic induction transistor (SIT), a gate fluid or a circuit thereof, and the load is an inductor, a resistor, and a A capacitor or a circuit of its composition.
  9. The transistor structure of claim 1, wherein the transistor grain is a bipolar junction transistor (BJT) die.
  10. The transistor structure of claim 9, wherein the first pad of the transistor die is an emitter pad, and the second pad is a base pad. The pad, and the third pad is a collector pad.
  11. The transistor structure of claim 1, wherein the chip package further comprises a wafer holder, and the transistor crystal grain is disposed on the wafer holder through an adhesive layer.
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US5397934A (en) * 1993-04-05 1995-03-14 National Semiconductor Corporation Apparatus and method for adjusting the threshold voltage of MOS transistors
US5828559A (en) * 1997-02-03 1998-10-27 Chen; Keming Soft switching active snubber
JP2004273570A (en) * 2003-03-05 2004-09-30 Kanto Sanyo Semiconductors Co Ltd Resin sealed semiconductor device and its manufacturing method
US20040202215A1 (en) * 2003-04-09 2004-10-14 Elantec Semiconductor, Inc. Programmable damping for laser drivers
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US7190564B2 (en) * 2004-09-30 2007-03-13 The Bergquist Torrington Company Snubber circuit
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