TW201324768A - Transistor structure and related transistor packaging method thereof - Google Patents

Transistor structure and related transistor packaging method thereof Download PDF

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Publication number
TW201324768A
TW201324768A TW101133241A TW101133241A TW201324768A TW 201324768 A TW201324768 A TW 201324768A TW 101133241 A TW101133241 A TW 101133241A TW 101133241 A TW101133241 A TW 101133241A TW 201324768 A TW201324768 A TW 201324768A
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Taiwan
Prior art keywords
pad
transistor
die
electrically
lead
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TW101133241A
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Chinese (zh)
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TWI487100B (en
Inventor
Kuo-Fan Lin
Chi-Shang Lin
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Fsp Technology Inc
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Priority to US201261682319P priority
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Publication of TWI487100B publication Critical patent/TWI487100B/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/4813Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A transistor structure includes a chip package and two pins, wherein the chip package includes a transistor die and a molding compound encapsulating the transistor die. One of the pins is electrically connected to a first bonding pad and a second bonding pad of the transistor die, and another of the pins is electrically connected to a third bonding pad of the transistor die. The transistor structure may be employed in a snubber circuit to connect an active component or a load in parallel to absorb spikes or noise generated by the active component while the active component is switching at a high frequency. Therefore, the packaging of the transistor structure could simplify the process, reduce size, increase the withstanding voltage, and improve the efficiency and reduce the spike voltage of the power supply of the snubber circuit.

Description

Transistor structure and packaging method thereof
The present invention relates to a transistor structure and a method of packaging the same, and more particularly to a transistor structure having a two-lead leg and a method of packaging the same.
In recent years, as the technology of electronic circuits has been continuously developed, various protection circuits for electric/electronic components have been widely implemented in many applications. In the conventional protection circuit, for example, an RCD damper circuit, as shown in FIG. 19, after the resistor R6 is connected to the capacitor C12, the diode D11 is connected in series to form an RCD damper circuit 400. However, the RCD damper circuit has high energy loss, low efficiency, and high surge voltage value, so the conventional RCD damper circuit is liable to cause damage to the semiconductor component. Therefore, there is a need for a novel electronic component that can replace the diode D11 to enhance the circuit protection performance of the damper circuit.
It is an object of the present invention to provide a transistor structure and a method of packaging the same that can be used in a damper circuit to allow the damper circuit to effectively protect components and improve efficiency.
An object of the present invention is to provide a transistor structure and a method of packaging the same, which can simplify the process, reduce the volume, and increase the withstand voltage.
To achieve the above objective, the transistor structure of the present invention comprises a chip package and a second lead, wherein the chip package system comprises an oxide crystal grain and an encapsulant covering the crystal grain; and the conductive One of the feet is electrically connected to the first lead The first pad and the second pad of the transistor die are electrically connected to the third pad of the transistor die.
The transistor structure as described above, wherein the first lead or the second lead of the transistor structure is connected to one end of a capacitor to form a snubber circuit to be connected to an active component or a load.
The transistor structure as described above, wherein one end of the capacitor is further connected to one end of a Zener diode, and the other end of the capacitor is connected to the other end of the Zener diode to form a damping circuit to be connected in an active manner. Component or a load.
The transistor structure as described above, wherein the first lead or the second lead of the transistor structure is connected to one end of a resistor, and the other end of the resistor is connected to one end of a capacitor to form a damping circuit. Connect an active component or a load.
The transistor structure as described above, wherein the active device is a metal oxide semiconductor field effect transistor (MOSFET), a diode, a bipolar junction transistor (BJT), and an insulating gate double A polar transistor (IGBT), an electrostatic induction transistor (SIT), a thyristor or a circuit thereof, and the load is an inductor, a resistor, a capacitor or a circuit thereof.
The transistor structure as described above, wherein the transistor crystal grain is a bipolar junction transistor crystal grain.
The transistor structure as described above, wherein the first pad of the transistor die is an emitter pad, the second pad is a base pad, and the third pad is A set of pole pads.
The transistor structure as described above, wherein the first pad, the second pad, and the third pad are electrically connected to each of the leads by wire bonding.
The transistor structure as described above, wherein the wire bonding is performed by connecting the lead pins through three wires.
The transistor structure as described above, wherein the first pad and the second pad are electrically connected, and are connected to one of the lead pins through a wire, and the third pad is transmitted through one wire and the other lead connection.
The transistor structure as described above, wherein the first pad, the second pad, and the third pad are electrically connected to the lead pins through a flip chip bond.
The transistor structure as described above, wherein the chip package further comprises a wafer holder, and the transistor crystal grain is disposed on the wafer holder through an adhesive layer.
Thereby, the transistor structure of the present invention is electrically connected to the first pad and the second pad of the transistor die by using a lead pin, and the other leg is electrically connected to the third pad of the transistor die. Pad, the transistor structure can be used in the damper circuit, or the damper circuit can be directly packaged in the two-lead transistor structure to connect an active component or a load, and the absorbing active component can be switched at high frequency. The surge or noise generated makes the transistor structure on the package to simplify the process, reduce the volume and increase the withstand voltage, and can improve the efficiency and reduce the surge voltage by using the power supply of the damper circuit. The effect.
It is to be understood that the foregoing general description and claims
Other features and embodiments of the invention will be further understood from the following detailed description of the drawings.
The first embodiment of the present invention is a schematic view of a transistor structure according to a first embodiment of the present invention. The transistor structure of the present invention comprises a chip package 1 and two lead pins 2, 3, wherein the chip package 1 The method includes a transistor die 11 and a package colloid 12 covering the transistor die 11; and a lead 2 electrically connected to the first pad 111 and the second pad 112 of the transistor die 11 The leg 3 is electrically connected to the third pad 113 of the transistor die 11.
The transistor crystal 11 of the transistor structure of the embodiment is a Bipolar Junction Transistor (BJT) crystal, and the bipolar junction crystal grain system can be an NPN bipolar. The junction transistor crystal grain or a PNP type bipolar junction transistor crystal grain, please refer to the first figure, the second A picture and the second B picture, the first pad 111 of the transistor crystal grain 11 It is an emitter (Emitter) pad, the second pad 112 is a base pad, and the third pad 113 is a collector pad, wherein the emitter pad is soldered. The pad and the base pad are electrically connected to the lead 2, and the collector pad is electrically connected to the lead 3.
Therefore, the base of the bipolar junction transistor crystal grain of the embodiment is electrically connected to the emitter system, and based on at least one junction characteristic between the base and the collector of the bipolar junction transistor crystal grain, The transistor structure has the characteristics of fast conduction, slow recovery time, moderate relaxation, and small base-collector junction capacitance C bc , and the transistor structure can be utilized as a fast diode for one Damper circuit.
The damper circuit can be configured as follows: (1) a CB damper circuit, which is connected to one end of a capacitor by using a lead 2 or a lead 3 of the transistor structure of the embodiment to form a damper circuit to be connected one after another. An active component or a load (not shown); (2) a ZCB damper circuit, which is connected to one end of a capacitor C and a Zener diode D by using a lead 2 or a lead 3 of the transistor structure Q of the present embodiment. One end, and the other end of the capacitor C is connected to the other end of the Zener diode D to form a damper circuit (as shown in FIG. 12) to be connected with an active component or a load; (2) The RCB damper circuit is connected to one end of a resistor by using the lead 2 or the lead 3 of the transistor structure of the embodiment, and the other end of the resistor is connected to one end of a capacitor to form a damper circuit for parallel connection. An active component or a load (not shown).
The active component is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a diode, a bipolar junction transistor (BJT), and an insulated gate bipolar. Transistor (IGBT), a static induction transistor (SIT), a thyristor or a circuit thereof, and the load is an inductor, a resistor, a capacitor or a circuit thereof, for example, a damper circuit and an exchange power supply The primary side of the transformer is connected in parallel with a metal oxide semiconductor field effect transistor, or the damper circuit is connected to the secondary side of the transformer of the switching power supply, and a metal oxide semiconductor field effect transistor is connected. Or the damper circuit is connected in parallel with a metal oxide semiconductor field effect transistor and connected to the secondary side of the transformer of the switching power supply, and can absorb the surge generated by the active component during high frequency switching (spike) Or noise, by which the surge voltage generated by the active device can be reduced and the efficiency can be improved.
Referring to Table 1 and Table 2, Table 1 is the experimental test result of the conventional RCD damper circuit, and Table 2 is the experimental test result of the transistor structure of the present embodiment used for the above-mentioned RCB damper circuit, and The RCD damper circuit and the RCB damper circuit are both connected to the primary side of a transformer and connected to a metal oxide semiconductor field effect transistor. The test results listed in Table 1 and Table 2 can be confirmed by the experiment. The efficiency of the RCB damper circuit of this embodiment (the test result is Table 2) far exceeds the efficiency of the conventional RCD damper circuit (the test result is Table 1). In particular, the damper circuit is electrically connected to a light load, wherein the light load of the present invention is a percentage of a specified load (Percent of Rated Load) is less than 20%, that is, the load accounts for 20% of the full load. Below %, for example: the percentage of the specified load is 1% to 20%; and also when the percentage of the specified load is 1%, Table 2 (RCB damping) Compared with Table 1 (RCD damper circuit), it can increase the efficiency of 10.75% (57.84%→68.59%). Also, when the percentage of the specified load is 20%, Table 2 can also be compared with Table 1. Increase the efficiency of 1.23% (88.22% → 89.45%).
Thereby, the RCB damper circuit of the embodiment can achieve the effect of improving efficiency under light load compared with the conventional RCD damper circuit, wherein the damper circuit 300A of the embodiment has obvious efficiency except for light load. In addition, the Average_Efficiency of Tables 1 and 2 shows that the average efficiency during heavy load (25%~100%) is slightly increased by 0.3%. Therefore, the power supply using the transistor structure of the present invention as the damper circuit has higher conversion efficiency than the power supply using the RCD damper circuit, especially in the case of light load.
Please refer to FIG. B, which is a transistor structure according to a second embodiment of the present invention. The transistor structure of the present invention comprises a chip package 1 and two lead pins 2, 3, wherein the chip package 1 comprises an oxide crystal die 11, a capacitor die 13 and a cladding transistor. The die 11 and the package pad 12 of the capacitor die 13 are electrically connected to the first pad 131 of the capacitor die 13 and the pin 2 is electrically connected. The first pad 111 of the transistor die 11 and the second pad 112 are electrically connected to the second pad 132 of the capacitor die 13; wherein the transistor structure of the embodiment is The first pad 111 (or the second pad 112 ) of the transistor die 11 can be electrically connected to the first pad 131 of the capacitor die 13 , and the pin 2 is electrically connected to the capacitor die 13 . The second pad 132 is electrically connected to the third pad 113 (not shown) of the transistor die 11 (not shown), but not limited thereto; please refer to the second C diagram, this embodiment. The transistor crystal grain 11 is a Bipolar Junction Transistor (BJT) crystal grain, and the bipolar junction transistor crystal grain system can be an NPN type bipolar junction surface. Grains or a PNP-type bipolar junction transistor grains.
Therefore, the base of the bipolar junction transistor crystal grain of the embodiment is electrically connected to the emitter system, and based on at least one junction characteristic between the base and the collector of the bipolar junction transistor crystal grain, The transistor structure has the characteristics of fast conduction, slow recovery time, moderate relaxation, and small base-collector junction capacitance C bc , and the transistor crystal grain can be utilized as a fast diode and transmitted through the capacitor die. The electrical connection makes the transistor structure form a CB damper circuit. Therefore, the transistor structure can achieve the effects of simplifying the process, reducing the volume, and increasing the withstand voltage in the use of the package and the application circuit; wherein the CB damper circuit An active component or a load (not shown) may be connected in parallel. The active component is a metal oxide semiconductor field effect transistor (MOSFET), a diode, and a bipolar junction transistor (BJT). An insulating gate bipolar transistor (IGBT), an electrostatic induction transistor (SIT), a gate fluid or a circuit thereof, and the load is an inductor, a resistor, a capacitor or a circuit thereof, for example The CB damper circuit is in contact with The primary side of the transformer of the power supply is connected in parallel with a gold-oxygen half-field effect transistor, and can absorb the spike or noise generated by the active component during high-frequency switching, thereby reducing the initiative. The surge voltage generated by the component and improved efficiency.
The chip package 1 of the transistor structure of the present embodiment may include a resistor die, and the resistor die is serially connected between the transistor die 11 and the capacitor die 13, that is, the resistor. The first pad of the die is electrically connected to the first pad 111 or the third pad 113 of the transistor die 11, and the second pad of the resistor die is electrically connected to the capacitor die 13 a first pad 131 (not shown), and the encapsulant 12 is coated with the resistor die to form an RCB damper circuit, so that the transistor structure can be used in packaging and application circuits. Achieve simplification of the process, reduce the volume and increase the pressure distance.
Referring to FIG. C, the crystal structure of the third embodiment of the present invention is shown. The transistor structure of the present invention comprises a chip package 1 and two leads 2, 3, wherein the chip package 1 comprises an oxide crystal 11, a capacitor die 13, and a Zener diode. The granule 14 and the encapsulant 12 covering the transistor die 11, the capacitor die 13 and the Zener diode die 14 are electrically connected to the third pad 113 of the transistor die 11 a first pad 131 of the capacitor die 13 and a first pad 141 of the Zener diode die 14; and a pin 2 electrically connecting the first pad 111 and the second pad of the transistor die 11 a pad 112, the other lead 3 is electrically connected to the second pad 132 of the capacitor die 13 and the second pad 142 of the Zener diode die 14; wherein, the transistor structure of the embodiment The first pad 111 and the second pad 112 of the transistor die 11 are electrically connected to the first pad 131 of the capacitor die 13 and the first pad of the Zener diode die 14 141, the lead pin 2 is electrically connected to the second pad 132 of the capacitor die 13 and the second pad 142 of the Zener diode die 14, and the other lead 3 is electrically connected to the transistor die. 11th third pad 113.
That is, the Zener diode die 14 is connected to the capacitor die 13 in parallel with the capacitor die 13 , but not limited thereto. The Zener diode of the embodiment is not limited thereto. The second pad 142 of the die 14 is electrically connected to the first pad 111 or the third pad 113 of the transistor die 11, that is, the Zener diode die 14 can be connected to the transistor crystal. After the particles 11 are connected, they are connected in series with the capacitor die 13; please refer to the second D diagram, the transistor crystal 11 of the embodiment is a bipolar The Bipolar Junction Transistor (BJT) crystal grain may be an NPN type bipolar junction transistor crystal grain or a PNP type bipolar junction transistor crystal grain.
Therefore, the base of the bipolar junction transistor crystal grain of the embodiment is electrically connected to the emitter system, and based on at least one junction characteristic between the base and the collector of the bipolar junction transistor crystal grain, The transistor structure has the characteristics of fast conduction, slow recovery time, moderate relaxation, and small base-collector junction capacitance C bc , and the transistor crystal can be used as a fast diode and transmitted through the capacitor die, The electrical connection of the Zener diode dies allows the transistor structure to form a ZCB damper circuit (as shown in Figure 12). Therefore, the transistor structure can achieve a simplified process in the use of package and application circuits. The effect of reducing the volume and increasing the withstand voltage distance; wherein the ZCB damper circuit can be connected to an active component or a load (not shown), the active component is a metal oxide semiconductor field effect transistor (MOSFET), a diode, a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT), an electrostatic induction transistor (SIT), a thyristor or a circuit thereof, and the load Is an inductor, a resistor, a capacitor or a component thereof The circuit, for example, the ZCB damper circuit is connected in parallel with the primary side of the transformer of the switching power supply, and is connected in series with a metal oxide semiconductor field effect transistor, and the absorbing active element is generated when the high frequency is switched. Spiral or noise, which reduces the surge voltage and improves efficiency.
In addition, as shown in the third to seventh embodiments, the transistor structure of the first embodiment is electrically connected by a wire bonding method to each of the embodiments of the transistor and the pad. The transistor structure includes a chip package 1 and two lead pins 2 and 3, wherein the chip package 1 includes an oxide crystal chip 11, an encapsulant 12, an adhesive layer 16, a wafer holder 17, and The plurality of wires 151, 152, and 153 are connected to the first pad 111, the second pad 112, the third pad 113, and the lead pin 2 of the transistor die 11 through a plurality of wires 151, 152, and 153. 3, so that the transistor die 11 is electrically connected to the leads 2, 3; wherein the pins 2, 3 can be respectively provided with at least one contact (not shown) for electrically connecting the wires 151 152, 153, and the transistor die 11 is disposed on the wafer holder 17 through the adhesive layer 16, the encapsulant 12 coating the transistor die 11, the adhesive layer 16, the wafer holder 17, the wires 151, 152, 153 and one of the lead pins 2, 3, and partially enclose the portions of the lead pins 2, 3 in the encapsulant 12, and one end of each of the pins 2, 3 is exposed to the outside of the encapsulant 12, wherein the wire 151, 152, 153 can be a gold wire or other conductive material, and the adhesive layer 16 can be a silver For the glue or other conductive colloid, the material of the encapsulant 12 may be epoxy resin or other polymer material.
Referring to the third figure, the two ends of the wire 151 of the embodiment are electrically connected to the lead pin 2 and the second pad 112. The two ends of the wire 152 are electrically connected to the lead pin 2 and a first pad 111, thereby short-circuiting the two ends of the first pad 111 and the second pad 112, and the two ends of the wire 153 are electrically connected between the lead pin 3 and the third pad 113, and further, the lead pin 2. The 3 series extends horizontally from the two sides of the package body 12, so that the lead pins 2, 3 are parallel to the wafer holder 17, and the package appearance of the transistor structure can be as shown in FIG. 10A to FIG. The appearance of the encapsulant 12 can be cylindrical, semi-circular or flat, and the lead 153 can be a long lead, a short lead, a leadless or other contact type.
Referring to the fourth figure, the two ends of the wire 151 of the embodiment are electrically connected to the lead pin 2 and the second pad 112. The two ends of the wire 152 are electrically connected to the lead pin 2 and the first pad 111. Therefore, the first pad 111 and the second pad 112 are short-circuited at both ends, and the lead 153 is electrically connected between the lead 3 and the third pad 113. Further, the lead 2 and 3 are self-packaging colloids. The two sides of the 12 are extended downwards, so that the lead pins 2, 3 are perpendicular to the wafer holder 17, and the package appearance of the crystal structure can be as shown in FIG. 11A to FIG. The appearance of the encapsulant 12 can be cylindrical, semi-circular or flat, and the lead 15 can be a long lead, a short lead, a leadless or other contact type.
Referring to FIG. 5, the first pad 111 and the second pad 112 are electrically connected to both ends of the wire 151 of the embodiment, thereby short-circuiting the two ends of the first pad 111 and the second pad 112. The two ends of the wire 152 are electrically connected to the lead pin 2 and the first pad 111, and the two ends of the wire 153 are electrically connected to the lead pin 3 and the third pad 113. In addition, the lead pins 2, 3 are horizontally extended from the two sides of the encapsulant 12, so that the lead pins 2, 3 are parallel to the wafer holder 17.
Referring to FIG. 6 , the first pad 111 and the second pad 112 are electrically connected to both ends of the wire 151 of the embodiment, thereby short-circuiting the two ends of the first pad 111 and the second pad 112 . The lead wires 152 are electrically connected to the lead pins 2 and the wires 151, and the lead wires 153 are electrically connected to the lead pins 3 and the third pads 113.
Referring to FIG. 7 , in this embodiment, the first pad 111 and the second pad 112 are electrically connected through a fourth pad 114 , thereby making the first pad 111 and the second pad 112 both ends. A short circuit is provided, and both ends of the wire 152 are electrically connected to the lead pin 2 and the fourth pad 114, and the lead wires 153 are electrically connected to the lead pin 3 and the third pad 113.
Please refer to the eighth embodiment and the ninth embodiment at the same time. The transistor structure of the first embodiment is electrically connected to each of the embodiments of the transistor and the pad by a flip chip bonding. The transistor structure includes a chip package 1 and two lead pins 2, 3, wherein the chip package 1 includes an oxide crystal die 11, an encapsulant 12, and a solder 18, which are in the first solder. Solder 18 is formed on the surface of the pad 111 and the second pad 112. Then, after the transistor crystal grains are flipped, the first pad 111 and the second pad 112 of the transistor die 11 are connected through the solder 18. a third pad 113 and the lead pins 2, 3, so that the transistor crystal grains 11 are electrically connected to the lead pins 2, 3; wherein the lead pins 2, 3 are At least one contact (not shown) may be separately disposed to electrically connect the solder 18, and the encapsulant 12 covers the transistor die 11, the solder 18, and a portion of the pins 2, 3, thereby enabling A portion of the leads 2, 3 is embedded in the encapsulant 12, and one end of each of the leads 2, 3 is exposed to the outside of the encapsulant 12, wherein the material of the solder 18 can be tin or Other metal materials.
Referring to FIG. 8 , the solder 18 of the present embodiment includes a first solder 181 , a second solder 182 , and a third solder 183 . The first solder 181 electrically connects the lead pin 2 and the third pad 113 . The second solder 182 and the third solder 183 electrically connect the lead pins 3 to the first pads 111 and the second pads 112 , thereby short-circuiting the first pads 111 and the second pads 112 .
Referring to FIG. 9 , the solder 18 of the embodiment includes a first solder 181 and a fourth solder 184 . The first solder 181 electrically connects the lead 2 and the third pad 113 , and the fourth solder The 184 series electrically connects the lead pins 3 with the first pads 111 and the second pads 112, thereby short-circuiting the first pads 111 and the second pads 112.
Referring to the third and thirteenth drawings, the first embodiment of the transistor packaging method of the present invention comprises the following steps: First, providing a first pad 111, a second pad 112, and a third pad 113 a transistor crystal 11 (S100); then, a surface of the first pad 111 and the second pad 112 respectively formed a wire 151, 152 is electrically connected to a first lead 2 (S102); Then, in the first A lead 153 is electrically connected to a second lead 3 on the surface of the third pad 113 (S104). Finally, an encapsulant 12 is provided to cover the transistor die 11, the wires 151-153, and the like. One of the feet 2, 3 (S106).
Referring to FIG. 5 and FIG. 14 simultaneously, the second embodiment of the transistor packaging method of the present invention comprises the following steps: First, providing a first pad 111, a second pad 112, and a third pad And forming a wire 151 on the surface of the first pad 111 to electrically connect the second pad 112 (S202); then, on the first pad 111 or A wire 152 is electrically connected to the first lead 2 on the surface of the second pad 112 (S204). Then, a wire 153 is electrically connected to the second lead 3 on the surface of the third pad 113. (S206) Finally, an encapsulant 12 is provided to coat the transistor crystal grains 11, the wires 13 to 15 and a portion of the pins 2, 3 (S208).
Referring to FIG. 6 and FIG. 15 simultaneously, the third embodiment of the transistor packaging method of the present invention comprises the following steps: First, providing a first pad 111, a second pad 112, and a third pad. And forming a wire 151 on the surface of the first pad 111 to electrically connect the second pad 112 (S302); then, in a first lead 2 A wire 152 is formed on the surface to electrically connect the wire 13 (S304); then, a wire 153 is electrically connected to a second lead 3 on the surface of the third pad 113 (S306); finally, a package is provided. The colloid 12 covers the transistor crystal grain 11, the wires 151~153 and one of the guide pins 2, 3 (S308).
Referring to FIG. 7 and FIG. 16 simultaneously, the fourth embodiment of the transistor packaging method of the present invention comprises the following steps: First, providing a first pad 111, a second pad 112, and a third pad And forming a fourth pad 114 electrically connected to the first pad 111 and the second pad on the surface of the first pad 111 and the second pad 112; Pad 112 (S402); then, a wire 14 is electrically connected to a first lead 2 on the surface of the fourth pad 114 (S404); then, a wire is formed on the surface of the third pad 113. 15 is electrically connected to a second lead 3 (S406); finally, an encapsulant 12 is provided to cover the transistor die 11, the fourth pad 114, the wires 14, 15 and the leads 2 One part of 3 (S408).
Referring to FIG. 8 and FIG. 17 simultaneously, the fifth embodiment of the transistor packaging method of the present invention comprises the following steps: First, providing a first pad 111, a second pad 112, and a third pad a first transistor 182 and a second solder 183 are electrically connected to a first lead on the surface of the first pad 111 and the second pad 112, respectively. 2 (S502); then, a third solder 181 is electrically connected to a second lead 3 on the surface of the third pad 113 (S504); finally, an encapsulant 12 is provided to coat the transistor crystal grain. 11. The solder 18 and a portion of the leads 2, 3 (S506).
Referring to FIG. 9 and FIG. 18 simultaneously, the sixth embodiment of the transistor packaging method of the present invention comprises the following steps: First, providing a first pad 111, a second pad 112, and a third pad a first transistor 184 is electrically connected to a first lead 2 (S602); and then a fourth solder 184 is electrically connected to the surface of the first pad 111 and the second pad 112 (S602); A first solder 181 is electrically connected to a second lead 3 on the surface of the third pad 113 (S604). Finally, an encapsulant 12 is provided to cover the transistor die 11, the solder 181. , 184 and one of the guide legs 2, 3 (S606).
The transistor crystal grain described in each embodiment of the transistor packaging method is a bipolar junction transistor (BJT) die.
In summary, according to the above disclosure, the present invention can achieve the intended purpose of the invention, which utilizes a lead to electrically connect the first pad and the second pad of the transistor die, and the other guide The foot is electrically connected to the third pad of the transistor die, and the transistor structure can be used in the damper circuit, or the damper circuit can be directly encapsulated in the two-lead transistor structure to connect an active component Or a load, which can absorb the glitch or noise generated by the active component during high-frequency switching, so that the transistor structure can achieve the functions of simplifying the process, reducing the volume, and increasing the withstand voltage on the package, and can be used. The damper circuit of the crystal structure can effectively protect the components, and the power supply using the damper circuit has higher conversion efficiency than the power supply using the conventional damper circuit, and has practical value, and has industrial applicability. ,new Innovative and progressive elements, 提出 filed an invention patent application in accordance with the law.
The above is only the preferred embodiment of the present invention, and the equivalent design changes made by the scope of the present invention should be covered by the technical scope of the present invention.
1‧‧‧ chip package
11‧‧‧Optocrystalline grains
111, 131, 141‧‧‧ first pad
112, 132, 142‧‧‧second solder pads
113‧‧‧ Third pad
114‧‧‧fourth pad
12‧‧‧Package colloid
13‧‧‧Capacitor crystal
14‧‧‧Zina diode grain
151~153‧‧‧ wire
16‧‧‧Adhesive layer
17‧‧‧ Wafer holder
18‧‧‧ solder
181‧‧‧First solder
182‧‧‧second solder
183‧‧‧ Third solder
184‧‧‧fourth solder
2, 3‧‧ ‧ lead
Q‧‧‧Optocrystal structure
C‧‧‧ capacitor
D‧‧‧Zina diode
The following drawings are a part of the specification of the invention, and illustrate the embodiments of the invention
The first A is a schematic view of the structure of the transistor of the first embodiment of the present invention.
The first B diagram is a schematic view of the structure of the transistor of the second embodiment of the present invention.
The first C diagram is a schematic diagram of the structure of the transistor of the third embodiment of the present invention.
The second A diagram is a schematic diagram of the transistor crystal grains of the present invention being bipolar junction transistor crystal grains.
The second B diagram is a schematic diagram of the transistor crystal grains of the present invention being bipolar junction transistor crystal grains.
The second C diagram is a schematic diagram of the connection of the bipolar junction transistor die and the capacitor die of the present invention.
The second D diagram is a schematic diagram of the bipolar junction transistor crystal grain of the invention connected to the capacitor crystal grain and the Zener diode.
The third to seventh drawings are schematic cross-sectional views of the transistor packages of the embodiments in which the lead pins and the pads are electrically connected by wire bonding.
8 to 9 are schematic cross-sectional views showing the transistor packages of the embodiments in which the lead pins and the pads are electrically connected by a flip chip bonding method.
10A to 11D are perspective views of the transistor package of the embodiments of the present invention.
The twelfth figure is a damper circuit to which the transistor structure of the present invention is applied.
Figure 13 is a flow chart of the first embodiment of the transistor packaging method of the present invention.
Figure 14 is a flow chart showing a second embodiment of the transistor packaging method of the present invention.
The fifteenth embodiment is a flow chart of the third embodiment of the transistor packaging method of the present invention.
Figure 16 is a flow chart showing a fourth embodiment of the transistor packaging method of the present invention.
Figure 17 is a flow chart showing a fifth embodiment of the transistor packaging method of the present invention.
Figure 18 is a flow chart showing a sixth embodiment of the transistor packaging method of the present invention.
The nineteenth diagram is a schematic diagram of a conventional RCD damper circuit.
1‧‧‧ chip package
11‧‧‧Optocrystalline grains
111‧‧‧First pad
112‧‧‧Second pad
113‧‧‧ Third pad
12‧‧‧Package colloid
2, 3‧‧ ‧ lead

Claims (18)

  1. A transistor structure comprising: a chip package comprising an oxide crystal grain and a package colloid covering the transistor crystal grain; and a second lead leg, wherein a first lead leg is electrically connected to the electric The first pad and the second pad of the crystal grain are electrically connected to the third pad of the transistor die.
  2. The transistor structure of claim 1, wherein the chip package further comprises: a capacitor die, wherein the first pad of the capacitor die is electrically connected to the first die of the transistor die a pad or a third pad, wherein the second pad of the capacitor die is electrically connected to the first lead or the second lead, and the encapsulant system covers the capacitor die.
  3. The transistor structure of claim 2, wherein the chip package further comprises: a Zener Diode die, wherein the first pad of the Zener diode die is electrically The first pad of the capacitor die is connected to the first pad or the third pad of the transistor die, and the second pad of the Zener diode die is electrically connected to the capacitor die a second pad or a first pad or a third pad of the transistor die, and the encapsulant system encapsulates the Zener diode die.
  4. The transistor structure of claim 2, wherein the chip package further comprises: a resistor die, wherein the first pad of the resistor die is electrically connected to the first pad of the transistor die a pad or a third pad, wherein the second pad of the resistor die is electrically connected to the first pad of the capacitor die, and the encapsulant system covers the resistor die.
  5. The transistor structure of claim 1, wherein the first lead or the second lead of the transistor structure is connected to one end of a capacitor to form a snubber circuit to be connected in an active manner. Component or a load.
  6. The transistor structure of claim 5, wherein one end of the capacitor is further connected to one end of a Zener diode, and the other end of the capacitor is connected to the other end of the Zener diode to form a damping. The circuit is connected in parallel with an active component or a load.
  7. The transistor structure of claim 1, wherein the first lead or the second lead of the transistor structure is connected to one end of a resistor, and the other end of the resistor is connected to one end of a capacitor. A damper circuit is formed to connect an active component or a load.
  8. The transistor structure of claim 5, 6, or 7, wherein the active device is a metal oxide semiconductor field effect transistor (MOSFET), a diode, or a diode Bipolar junction transistor (BJT), one An insulated gate bipolar transistor (IGBT), a static induction transistor (SIT), a gate fluid or a circuit thereof, and the load is an inductor, a resistor, a capacitor or a circuit thereof.
  9. The transistor structure of claim 1, wherein the transistor grain is a bipolar junction transistor (BJT) die.
  10. The transistor structure of claim 9, wherein the first pad of the transistor die is an emitter pad, and the second pad is a base pad. The pad, and the third pad is a collector pad.
  11. The transistor structure of claim 1, wherein the first pad, the second pad, and the third pad are electrically connected to each of the leads by wire bonding.
  12. The transistor structure of claim 11, wherein the wire bonding is performed by connecting the lead wires through three wires.
  13. The transistor structure of claim 11, wherein the first pad and the second pad are electrically connected, and one of the leads is connected to the first pad or the second pad through a wire. And the third pad is connected to the other lead through a wire.
  14. The transistor structure of claim 13, wherein the first pad is electrically connected to the second pad through a wire or a solder.
  15. The transistor structure of claim 1, wherein the chip package further comprises a wafer holder, and the transistor crystal grain is disposed on the wafer holder through an adhesive layer.
  16. The transistor structure of claim 1, wherein the first pad, the second pad, and the third pad are electrically connected to each of the pins by means of flip chip bonding.
  17. A method for packaging a transistor, comprising: providing a transistor having a first pad, a second pad, and a third pad; forming a wire on the surface of the first pad and the second pad Electrically connecting a first lead; forming a wire electrically connected to a second lead on the surface of the third pad; and providing an encapsulant covering the transistor die, the wires and the guiding One part of the foot.
  18. A transistor packaging method includes: providing a transistor crystal having a first pad, a second pad, and a third pad; forming a solder on the surfaces of the first pad and the second pad respectively Electrically connecting a first lead; Forming a solder on the surface of the third pad to electrically connect a second lead; and providing an encapsulant to encapsulate the transistor die, the solder and a portion of the leads.
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US5397934A (en) * 1993-04-05 1995-03-14 National Semiconductor Corporation Apparatus and method for adjusting the threshold voltage of MOS transistors
US5828559A (en) * 1997-02-03 1998-10-27 Chen; Keming Soft switching active snubber
JP2004273570A (en) * 2003-03-05 2004-09-30 Kanto Sanyo Semiconductors Co Ltd Resin sealed semiconductor device and its manufacturing method
US20040202215A1 (en) * 2003-04-09 2004-10-14 Elantec Semiconductor, Inc. Programmable damping for laser drivers
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US7190564B2 (en) * 2004-09-30 2007-03-13 The Bergquist Torrington Company Snubber circuit
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TWM473610U (en) 2014-03-01

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