TWM471031U - 氧化物半導體薄膜電晶體基板 - Google Patents

氧化物半導體薄膜電晶體基板 Download PDF

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TWM471031U
TWM471031U TW102215196U TW102215196U TWM471031U TW M471031 U TWM471031 U TW M471031U TW 102215196 U TW102215196 U TW 102215196U TW 102215196 U TW102215196 U TW 102215196U TW M471031 U TWM471031 U TW M471031U
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oxide semiconductor
drain
thin film
source
film transistor
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His-Ming Chang
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Chunghwa Picture Tubes Ltd
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Priority to TW102215196U priority Critical patent/TWM471031U/zh
Priority to US14/078,494 priority patent/US8853698B1/en
Publication of TWM471031U publication Critical patent/TWM471031U/zh

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    • H—ELECTRICITY
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
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    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
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    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]

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Description

氧化物半導體薄膜電晶體基板
本創作是有關於一種氧化物半導體薄膜電晶體基板。
液晶顯示面板包含薄膜電晶體基板、彩色濾光片基板及位於薄膜電晶體基板與彩色濾光片基板之間的液晶分子層。薄膜電晶體基板上配置多個薄膜電晶體，每一薄膜電晶體包含閘極、閘介電層、半導體層、源極及汲極。半導體層的材料例如可包含非晶矽、多晶矽、微晶矽、單晶矽、有機半導體、氧化物半導體或其他合適的材料。
相較於非晶矽薄膜電晶體，氧化物半導體薄膜電晶體具有較高的載子遷移率(Mobility)，而擁有較佳的電性表現。然而在形成氧化物半導體層時，容易使與氧化物半導體層相互接觸的金屬層的表面發生氧化。舉例而言，在形成氧化物半導體層於源極和汲極上的情況下，與氧化物半導體層相互接觸的源極和汲極的表面容易發生氧化，導致氧化物半導體層與源極和汲極之間的接觸阻抗升高，進而 影響氧化物半導體薄膜電晶體的電性表現。有鑑於此，目前亟需一種改良的氧化物半導體薄膜電晶體基板，以解決上述問題。
本創作之一態樣提供一種氧化物半導體薄膜電晶體基板，其能夠於形成氧化物半導體層時，有效避免源極及汲極發生氧化現象。此氧化物半導體薄膜電晶體基板包含基板、源極及汲極、圖案化透明導電層、氧化物半導體層、閘極及閘介電層。源極及汲極位於基板上。圖案化透明導電層包含第一透明電極、第二透明電極及畫素電極，第一及第二透明電極分別覆蓋源極之上表面及汲極之上表面，畫素電極連接汲極。氧化物半導體層接觸第一及第二透明電極。閘介電層夾設於氧化物半導體層與閘極之間。
根據本創作之一實施方式，第一透明電極的內側邊緣與源極的內側邊緣實質上對齊。
根據本創作之一實施方式，第一透明電極之上視輪廓與源極之上視輪廓不同。
根據本創作之一實施方式，第一透明電極更覆蓋源極之內側邊緣，氧化物半導體層未與源極接觸。
根據本創作之一實施方式，第二透明電極的內側邊緣與汲極的內側邊緣實質上對齊。
根據本創作之一實施方式，第二透明電極之上視輪廓與汲極之上視輪廓不同。
根據本創作之一實施方式，第二透明電極更覆蓋汲極之內側邊緣，氧化物半導體層未與汲極接觸。
根據本創作之一實施方式，氧化物半導體層未與第一及第二透明電極之任何邊緣對齊。
根據本創作之一實施方式，第二透明電極連接畫素電極。
根據本創作之一實施方式，閘介電層位於源極及汲極之下方，畫素電極覆蓋並接觸閘介電層。
根據本創作之一實施方式，閘介電層位於源極及汲極之上方，畫素電極覆蓋並接觸基板。
110‧‧‧基板
120‧‧‧閘介電層
130‧‧‧保護層
400、500‧‧‧底閘型薄膜電晶體基板
600‧‧‧頂閘型薄膜電晶體基板
A-A'‧‧‧線段
D‧‧‧汲極
DL‧‧‧資料線
G‧‧‧閘極
I1‧‧‧第一透明電極的內側邊緣
I2‧‧‧源極的內側邊緣
I3‧‧‧第二透明電極的內側邊緣
I4‧‧‧汲極的內側邊緣
PE‧‧‧畫素電極
S‧‧‧源極
SE‧‧‧氧化物半導體層
SL‧‧‧掃描線
T‧‧‧圖案化透明導電層
T1‧‧‧第一透明電極
T2‧‧‧第二透明電極
Tp‧‧‧圖案化透明導電層之一部分
第1A-1B、2A-2B、3A-3B、4A-4B圖係顯示依照本創作一實施方式之氧化物半導體薄膜電晶體基板之各製程階段的上視與剖面示意圖。
第5A-5B圖係顯示依照本創作另一實施方式之氧化物半導體薄膜電晶體基板的上視與剖面示意圖。
第6圖係顯示依照本創作又一實施方式之氧化物半導體薄膜電晶體基板的剖面示意圖。
以下將以圖式揭露本創作之複數個實施方式，為明確說明起見，許多實務上的細節將在以下敘述中一併說 明。然而，應瞭解到，這些實務上的細節不應用以限制本創作。也就是說，在本創作部分實施方式中，這些實務上的細節是非必要的。此外，為簡化圖式起見，一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。
本創作之一態樣係提供一種氧化物半導體薄膜電晶體基板，其能夠於形成氧化物半導體層時，有效避免源極及汲極發生氧化現象。以下將例示氧化物半導體薄膜電晶體基板之數種實施方式。
第1A、2A、3A、4A圖係顯示依照本創作之一實施方式之底閘型氧化物半導體薄膜電晶體基板之各製程階段的上視示意圖。第1B、2B、3B、4B圖係分別根據第1A、2A、3A、4A圖的線A-A'繪示剖面示意圖。請參照第4A-4B圖，底閘型薄膜電晶體基板400包含基板110、源極S及汲極D、圖案化透明導電層T、氧化物半導體層SE、閘極G及閘介電層120。圖案化透明導電層T包含第一透明電極T1、第二透明電極T2及畫素電極PE。
如第1A-1B圖所示，閘極G位於基板110上。基板110需具有足夠的機械強度，其可例如為玻璃、石英或透明高分子材料。在本實施方式中，薄膜電晶體基板400更包含掃描線SL位於基板110上，且閘極G及掃描線SL屬於同一圖案化導電層。閘極G及掃描線SL可為單層或多層結構，其材料可為金屬或合金，例如鉬(Mo)、鉻(Cr)、鋁(Al)、釹(Nd)、鈦(Ti)、銅(Cu)、銀(Ag)、金(Au)、鋅(Zn)、銦(In)、鎵(Ga)、其他合適的金屬或上述的組合。舉例而言， 可利用濺鍍(sputtering)、蒸鍍(evaporation)製程或其他薄膜沉積技術先形成一層金屬層(未繪示)於基板110上，再利用微影蝕刻製程形成閘極G與掃描線SL。
閘介電層120覆蓋閘極G，如第2B圖所示。閘介電層120可更覆蓋掃描線SL。閘介電層120可為單層或多層結構，其材料可為有機介電材料或無機介電材料。有機介電材料可為聚亞醯胺(Polyimide,PI)；無機介電材料例如為氧化矽、氮化矽、氮氧化矽或上述之組合。例如可利用化學氣相沉積法(chemical vapor deposition,CVD)或其他合適的薄膜沉積技術形成閘介電層120。閘介電層120夾設於氧化物半導體層SE與閘極G之間，如第4B圖所示。
源極S及汲極D位於基板110上，如第2A-2B圖所示。詳細而言，源極S與汲極D設置於閘介電層120上。在本實施方式中，薄膜電晶體基板400更包含資料線DL位於基板110上，且源極S、汲極D及資料線DL屬於同一圖案化導電層。源極S、汲極D及資料線DL可為單層或多層結構，其材料請參考上述閘極G及掃描線SL所例示的材料。例如可利用濺鍍、蒸鍍製程或其他薄膜沉積技術先形成一層金屬層(未繪示)於閘介電層120上，再利用微影蝕刻製程形成源極S、汲極D與資料線DL。
圖案化透明導電層T設置於源極S、汲極D和閘介電層120上，如第3A-3B圖所示。第二透明電極T2連接畫素電極PE，畫素電極PE連接汲極D。第一透明電極T1及第二透明電極T2分別覆蓋源極S的上表面及汲極D的上表 面，因此在後續形成氧化物半導體層的步驟中，源極S及汲極D的上表面未露出，故源極S及汲極D不易發生氧化現象。在一實施例中，第一透明電極T1、第二透明電極T2及畫素電極PE可由同一道光罩之微影蝕刻製程所形成，故不會增加製程時間及製程成本。在本實施方式中，閘介電層120位於源極S及汲極D之下方，而畫素電極PE覆蓋並接觸閘介電層120。
詳細而言，第一透明電極T1覆蓋源極S，且第一透明電極T1的內側邊緣I1與源極S的內側邊緣I2實質上對齊。另一方面，第二透明電極T2的內側邊緣I3與汲極D的內側邊緣I4實質上對齊。第一透明電極T1、第二透明電極T2及畫素電極PE可為單層或多層結構，其材料可例如為氧化銦錫(ITO)、氧化鋁鋅(AZO)、氧化鋁錫(ATO)、氧化鎵鋅(GZO)、氧化銦鈦(ITiO)、氧化銦鉬(IMO)、其他透明導電材料或上述之組合。
以另一種定義方式而言，圖案化透明導電層T包含第一透明電極T1與一部分Tp，如第3A圖所示。該部分Tp包含第二透明電極T2及畫素電極PE。因此，第二透明電極T2可定義為在該部分Tp之中，位於汲極D上表面正上方的部分；畫素電極PE可定義為在該部分Tp之中，第二透明電極T2以外的另一部分，如第3A-3B圖所示。
氧化物半導體層SE接觸第一及第二透明電極T1、T2，如第4A-4B圖所示。詳細而言，氧化物半導體層SE設置於第一透明電極T1及第二透明電極T2上，以及源極 S與汲極D之間的閘介電層120上。氧化物半導體層SE未與第一及第二透明電極T1、T2之任何邊緣對齊。
另外，底閘型薄膜電晶體基板400可更包含保護層130全面覆蓋氧化物半導體層SE、第一透明電極T1、第二透明電極T2及畫素電極PE，如第4B圖所示。保護層130可為單層或多層結構，其材料請參考上述閘介電層120所例示的材料。
在另一實施方式中，請參照第5A-5B圖，底閘型薄膜電晶體基板500包含基板110、源極S及汲極D、圖案化透明導電層T、氧化物半導體層SE、閘極G及閘介電層120。圖案化透明導電層T包含第一透明電極T1、第二透明電極T2及畫素電極PE。特別的是，薄膜電晶體基板500的第一透明電極T1之上視輪廓與源極S之上視輪廓不同。詳細而言，第一透明電極T1更覆蓋源極S之內側邊緣I2，使氧化物半導體層SE不能與源極S接觸。另外，第二透明電極T2之上視輪廓與汲極D之上視輪廓不同。第二透明電極T2更覆蓋汲極D之內側邊緣I4，使氧化物半導體層SE不能與汲極D接觸。因此，源極S及汲極D完全被第一透明電極T1及第二透明電極T2所保護，故在形成氧化物半導體層SE時，源極S及汲極D不會氧化，也就不會發生接觸阻抗變大的情形。
在又一實施方式中，請參照第6圖，頂閘型薄膜電晶體基板600包含基板110、源極S及汲極D、圖案化透明導電層T、氧化物半導體層SE、閘極G及閘介電層120。 圖案化透明導電層T包含第一透明電極T1、第二透明電極T2及畫素電極PE。源極S及汲極D位於基板110上，並直接接觸基板110。第一及第二透明電極T1、T2分別覆蓋源極S之上表面及汲極D之上表面。畫素電極PE連接汲極D。氧化物半導體層SE接觸第一及第二透明電極T1、T2。閘介電層120夾設於氧化物半導體層SE與閘極G之間。在本實施方式中，閘介電層120位於源極S及汲極D之上方，而畫素電極PE覆蓋並接觸基板110。
類似於上述實施方式，第一及第二透明電極T1、T2除了分別覆蓋源極S的上表面及汲極D的上表面之外，更分別覆蓋源極S的內側邊緣I2及汲極D的內側邊緣I4。因此，源極S及汲極D完全被第一透明電極T1及第二透明電極T2所保護，故在形成氧化物半導體層SE時，源極S及汲極D不會氧化，也就不會發生接觸阻抗變大的情形。
綜合上述，由於第一及第二透明電極可分別保護源極及汲極，故在後續形成氧化物半導體層時，源極及汲極不易氧化進而影響接觸阻抗。另外，第一透明電極、第二透明電極及畫素電極可由同一道光罩之微影蝕刻製程所形成，故不會增加製程時間及製程成本。
雖然本創作已以實施方式揭露如上，然其並非用以限定本創作，任何熟習此技藝者，在不脫離本創作之精神和範圍內，當可作各種之更動與潤飾，因此本創作之保護範圍當視後附之申請專利範圍所界定者為準。
110‧‧‧基板
120‧‧‧閘介電層
130‧‧‧保護層
400‧‧‧底閘型薄膜電晶體基板
D‧‧‧汲極
G‧‧‧閘極
I2‧‧‧源極的內側邊緣
I4‧‧‧汲極的內側邊緣
PE‧‧‧畫素電極
S‧‧‧源極
SE‧‧‧氧化物半導體層
T‧‧‧圖案化透明導電層
T1‧‧‧第一透明電極
T2‧‧‧第二透明電極

Claims (11)

  1. 一種氧化物半導體薄膜電晶體基板，包含：一基板；一源極及一汲極，位於該基板上；一圖案化透明導電層，包含一第一透明電極、一第二透明電極及一畫素電極，該第一及該第二透明電極分別覆蓋該源極之上表面及該汲極之上表面，該畫素電極連接該汲極；一氧化物半導體層，接觸該第一及該第二透明電極；一閘極；以及一閘介電層，夾設於該氧化物半導體層與該閘極之間。
  2. 如請求項1之氧化物半導體薄膜電晶體基板，其中該第一透明電極的內側邊緣與該源極的內側邊緣實質上對齊。
  3. 如請求項1之氧化物半導體薄膜電晶體基板，其中該第一透明電極之上視輪廓與該源極之上視輪廓不同。
  4. 如請求項3之氧化物半導體薄膜電晶體基板，其中該第一透明電極更覆蓋該源極之內側邊緣，該氧化物半導體層未與該源極接觸。
  5. 如請求項1之氧化物半導體薄膜電晶體基板，其中該第二透明電極的內側邊緣與該汲極的內側邊緣實質上對齊。
  6. 如請求項1之氧化物半導體薄膜電晶體基板，其中該第二透明電極之上視輪廓與該汲極之上視輪廓不同。
  7. 如請求項6之氧化物半導體薄膜電晶體基板，其中該第二透明電極更覆蓋該汲極之內側邊緣，該氧化物半導體層未與該汲極接觸。
  8. 如請求項1之氧化物半導體薄膜電晶體基板，其中該氧化物半導體層未與該第一及該第二透明電極之任何邊緣對齊。
  9. 如請求項1之氧化物半導體薄膜電晶體基板，其中該第二透明電極連接該畫素電極。
  10. 如請求項1之氧化物半導體薄膜電晶體基板，其中該閘介電層位於該源極及該汲極之下方，該畫素電極覆蓋並接觸該閘介電層。
  11. 如請求項1之氧化物半導體薄膜電晶體基板，其中該閘介電層位於該源極及該汲極之上方，該畫素電極覆蓋並接觸該基板。
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