TWI863483B - 半導體模組及其製造方法 - Google Patents

半導體模組及其製造方法 Download PDF

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Publication number
TWI863483B
TWI863483B TW112129327A TW112129327A TWI863483B TW I863483 B TWI863483 B TW I863483B TW 112129327 A TW112129327 A TW 112129327A TW 112129327 A TW112129327 A TW 112129327A TW I863483 B TWI863483 B TW I863483B
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TW
Taiwan
Prior art keywords
inductor
memory
memory chip
chip
aforementioned
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TW112129327A
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English (en)
Chinese (zh)
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TW202412218A (zh
Inventor
黑田忠廣
川野連也
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先端系統技術研究組合
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Publication of TW202412218A publication Critical patent/TW202412218A/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/497—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/20—Inductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/501—Inductive arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/26—Configurations of stacked chips the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/288—Configurations of stacked chips characterised by arrangements for thermal management of the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
    • H10W90/792—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between multiple chips

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  • Semiconductor Integrated Circuits (AREA)
TW112129327A 2022-09-12 2023-08-04 半導體模組及其製造方法 TWI863483B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2022-144892 2022-09-12
JP2022144892 2022-09-12

Publications (2)

Publication Number Publication Date
TW202412218A TW202412218A (zh) 2024-03-16
TWI863483B true TWI863483B (zh) 2024-11-21

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Family Applications (1)

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TW112129327A TWI863483B (zh) 2022-09-12 2023-08-04 半導體模組及其製造方法

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US (1) US20250210514A1 (https=)
JP (1) JPWO2024057707A1 (https=)
TW (1) TWI863483B (https=)
WO (1) WO2024057707A1 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2024262221A1 (https=) * 2023-06-20 2024-12-26
WO2024262220A1 (ja) * 2023-06-20 2024-12-26 先端システム技術研究組合 半導体モジュール
WO2025258552A1 (ja) * 2024-06-10 2025-12-18 先端システム技術研究組合 半導体モジュール及び半導体モジュールの製造方法
JP2026001327A (ja) * 2024-06-19 2026-01-07 ヤマハロボティクス株式会社 チップ積層デバイス、半導体モジュール、及びそれらの製造方法
WO2026018508A1 (ja) * 2024-07-16 2026-01-22 先端システム技術研究組合 半導体モジュール

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020097132A1 (en) * 1999-07-09 2002-07-25 Micron Technology, Inc. Integrated circuit inductors
US20200020473A1 (en) * 2018-07-13 2020-01-16 Qualcomm Incorporated Inductors formed with through glass vias
US20200211985A1 (en) * 2018-12-29 2020-07-02 Intel Corporation Integrated magnetic inductors for embedded-multi-die interconnect bridge substrates
TW202044500A (zh) * 2019-05-29 2020-12-01 佐臻股份有限公司 模組堆疊封裝結構
US20210391251A1 (en) * 2020-06-12 2021-12-16 Taiwan Semiconductor Manufacturing Co., Ltd. Extended via semiconductor structure, device and method

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994026083A1 (en) * 1993-04-23 1994-11-10 Irvine Sensors Corporation Electronic module comprising a stack of ic chips
JP3610661B2 (ja) * 1996-02-21 2005-01-19 株式会社日立製作所 三次元積層モジュール
JP2011108779A (ja) * 2009-11-16 2011-06-02 Panasonic Corp 半導体装置
WO2017126014A1 (ja) * 2016-01-18 2017-07-27 ウルトラメモリ株式会社 積層型半導体装置及びその製造方法
US20210018952A1 (en) * 2017-06-02 2021-01-21 Ultramemory Inc. Semiconductor module
CN113056819B (zh) * 2019-11-11 2022-06-03 超极存储器股份有限公司 半导体模块、dimm模块以及它们的制造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020097132A1 (en) * 1999-07-09 2002-07-25 Micron Technology, Inc. Integrated circuit inductors
US20200020473A1 (en) * 2018-07-13 2020-01-16 Qualcomm Incorporated Inductors formed with through glass vias
US20200211985A1 (en) * 2018-12-29 2020-07-02 Intel Corporation Integrated magnetic inductors for embedded-multi-die interconnect bridge substrates
TW202044500A (zh) * 2019-05-29 2020-12-01 佐臻股份有限公司 模組堆疊封裝結構
US20210391251A1 (en) * 2020-06-12 2021-12-16 Taiwan Semiconductor Manufacturing Co., Ltd. Extended via semiconductor structure, device and method

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US20250210514A1 (en) 2025-06-26
WO2024057707A1 (ja) 2024-03-21
TW202412218A (zh) 2024-03-16
JPWO2024057707A1 (https=) 2024-03-21

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