TWI846810B - 半導體裝置及電子裝置 - Google Patents

半導體裝置及電子裝置 Download PDF

Info

Publication number
TWI846810B
TWI846810B TW109103086A TW109103086A TWI846810B TW I846810 B TWI846810 B TW I846810B TW 109103086 A TW109103086 A TW 109103086A TW 109103086 A TW109103086 A TW 109103086A TW I846810 B TWI846810 B TW I846810B
Authority
TW
Taiwan
Prior art keywords
wiring
circuit
transistor
input
terminal
Prior art date
Application number
TW109103086A
Other languages
English (en)
Chinese (zh)
Other versions
TW202032407A (zh
Inventor
木村肇
黒川義元
Original Assignee
日商半導體能源研究所股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商半導體能源研究所股份有限公司 filed Critical 日商半導體能源研究所股份有限公司
Publication of TW202032407A publication Critical patent/TW202032407A/zh
Application granted granted Critical
Publication of TWI846810B publication Critical patent/TWI846810B/zh

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/048—Activation functions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0499—Feedforward networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Biophysics (AREA)
  • General Health & Medical Sciences (AREA)
  • Molecular Biology (AREA)
  • General Engineering & Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Data Mining & Analysis (AREA)
  • Computational Linguistics (AREA)
  • Computing Systems (AREA)
  • Artificial Intelligence (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Neurology (AREA)
  • Power Engineering (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)
  • Dram (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Control Of El Displays (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Memory System (AREA)
TW109103086A 2019-02-15 2020-01-31 半導體裝置及電子裝置 TWI846810B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019025723 2019-02-15
JP2019-025723 2019-02-15

Publications (2)

Publication Number Publication Date
TW202032407A TW202032407A (zh) 2020-09-01
TWI846810B true TWI846810B (zh) 2024-07-01

Family

ID=72044717

Family Applications (2)

Application Number Title Priority Date Filing Date
TW109103086A TWI846810B (zh) 2019-02-15 2020-01-31 半導體裝置及電子裝置
TW113120471A TWI906891B (zh) 2019-02-15 2020-01-31 半導體裝置及電子裝置

Family Applications After (1)

Application Number Title Priority Date Filing Date
TW113120471A TWI906891B (zh) 2019-02-15 2020-01-31 半導體裝置及電子裝置

Country Status (7)

Country Link
US (3) US11776586B2 (https=)
JP (3) JP7443263B2 (https=)
KR (1) KR20210125004A (https=)
CN (1) CN113383342A (https=)
DE (1) DE112020000823T5 (https=)
TW (2) TWI846810B (https=)
WO (1) WO2020165685A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI906891B (zh) * 2019-02-15 2025-12-01 日商半導體能源研究所股份有限公司 半導體裝置及電子裝置

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11430846B2 (en) * 2019-03-19 2022-08-30 Innolux Corporation Display module with transistor
JP2020160887A (ja) * 2019-03-27 2020-10-01 ソニー株式会社 演算装置及び積和演算システム
WO2020234681A1 (ja) 2019-05-17 2020-11-26 株式会社半導体エネルギー研究所 半導体装置、及び電子機器
KR20230039668A (ko) 2020-07-17 2023-03-21 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 전자 기기
US12371791B2 (en) 2021-01-15 2025-07-29 Taiwan Semiconductor Manufacturing Co., Ltd. System and method for dynamically adjusting thin-film deposition parameters
US12293281B2 (en) * 2021-04-09 2025-05-06 International Business Machines Corporation Training DNN by updating an array using a chopper
US12481867B2 (en) * 2021-04-28 2025-11-25 Arm Limited Memory for artificial neural network accelerator
WO2025153927A1 (ja) * 2024-01-17 2025-07-24 株式会社半導体エネルギー研究所 記憶回路、記憶装置及び電子機器
WO2026033397A1 (ja) * 2024-08-08 2026-02-12 株式会社半導体エネルギー研究所 半導体装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019003464A (ja) * 2017-06-16 2019-01-10 株式会社半導体エネルギー研究所 半導体装置、演算回路及び電子機器

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3260357B2 (ja) 1990-01-24 2002-02-25 株式会社日立製作所 情報処理装置
JP3353786B2 (ja) 1990-01-24 2002-12-03 株式会社日立製作所 情報処理装置
JPH0467259A (ja) 1990-07-09 1992-03-03 Hitachi Ltd 情報処理装置
JP4393980B2 (ja) 2004-06-14 2010-01-06 シャープ株式会社 表示装置
US8127075B2 (en) 2007-07-20 2012-02-28 Seagate Technology Llc Non-linear stochastic processing storage device
KR20230098374A (ko) * 2011-10-18 2023-07-03 가부시키가이샤 한도오따이 에네루기 켄큐쇼 발광 장치
US9934826B2 (en) * 2016-04-14 2018-04-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US11556771B2 (en) 2017-04-10 2023-01-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor neural network device including a synapse circuit comprising memory cells and an activation function circuit
US11568223B2 (en) 2017-04-14 2023-01-31 Semiconductor Energy Laboratory Co., Ltd. Neural network circuit
WO2018211349A1 (ja) 2017-05-19 2018-11-22 株式会社半導体エネルギー研究所 半導体装置
JP2019168851A (ja) * 2018-03-22 2019-10-03 東芝メモリ株式会社 演算装置及び演算方法
US12118333B2 (en) * 2018-04-26 2024-10-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
WO2019239245A1 (ja) 2018-06-15 2019-12-19 株式会社半導体エネルギー研究所 半導体装置
KR20250173579A (ko) 2018-10-19 2025-12-10 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 전자 기기
WO2020095140A1 (ja) 2018-11-08 2020-05-14 株式会社半導体エネルギー研究所 半導体装置、及び電子機器
TWI846810B (zh) 2019-02-15 2024-07-01 日商半導體能源研究所股份有限公司 半導體裝置及電子裝置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019003464A (ja) * 2017-06-16 2019-01-10 株式会社半導体エネルギー研究所 半導体装置、演算回路及び電子機器

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI906891B (zh) * 2019-02-15 2025-12-01 日商半導體能源研究所股份有限公司 半導體裝置及電子裝置
US12518800B2 (en) 2019-02-15 2026-01-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device performing arithmetic operation

Also Published As

Publication number Publication date
JP2024061728A (ja) 2024-05-08
TW202032407A (zh) 2020-09-01
JP7671888B2 (ja) 2025-05-02
JP7443263B2 (ja) 2024-03-05
US12518800B2 (en) 2026-01-06
DE112020000823T5 (de) 2021-11-04
KR20210125004A (ko) 2021-10-15
US20240046967A1 (en) 2024-02-08
JPWO2020165685A1 (https=) 2020-08-20
WO2020165685A1 (ja) 2020-08-20
US20260088064A1 (en) 2026-03-26
JP2025119617A (ja) 2025-08-14
US11776586B2 (en) 2023-10-03
US20220165311A1 (en) 2022-05-26
CN113383342A (zh) 2021-09-10
TWI906891B (zh) 2025-12-01
TW202509920A (zh) 2025-03-01

Similar Documents

Publication Publication Date Title
TWI846810B (zh) 半導體裝置及電子裝置
JP7842280B2 (ja) 半導体装置及び電子機器
JP7441175B2 (ja) 半導体装置、及び電子機器
JP7661571B2 (ja) 半導体装置および電子機器
JP7562785B2 (ja) 半導体装置、電子機器
JP7614204B2 (ja) 半導体装置、及び電子機器
JP7851475B1 (ja) 半導体装置、電子機器
JP7854547B2 (ja) 半導体装置