TWI839915B - Detection method and detection system for micro-damage on wafer surface - Google Patents

Abstract

The present invention relates to a detection method and a detection system for micro-damage on the surface of a wafer. The detection method comprises: a selection step: selecting a wafer that has been polished; a single crystal layer growth step: growing a single crystal layer on the surface of the selected wafer; a heat treatment step: performing heat treatment on the wafer on which the single crystal layer has been grown; and a detection step: performing stacking layer error detection on the single crystal layer of the heat-treated wafer to determine whether the wafer has surface micro-damage.

Description

Detection method and detection system for micro-damage on wafer surface

The present invention belongs to the field of wafer processing and manufacturing technology, and specifically, relates to a detection method and system for micro-damage on the surface of a wafer.

During the wafer manufacturing process, mechanical processing such as rolling, slicing, and grinding will introduce mechanical damage to the surface of the wafer. Therefore, the damaged layer will be removed in subsequent processing through steps such as etching and polishing. As a result, the surface of the wafer after polishing usually no longer has obvious damage. However, during the polishing process such as double-sided polishing, sometimes there will still be micro-damage such as micro scratches and local shallow pits on the wafer surface due to particles such as silicon slag and impurities in the polishing liquid entering the polishing area. This micro-damage will become larger and deeper in the subsequent cleaning steps due to the faster corrosion rate of the chemical liquid contained in the cleaning solution on the damaged defect compared to the undamaged area. Micro-damage destroys the original single crystal layer and easily causes leakage in the steps of thin film or circuit deposition in device manufacturing, thereby causing device failure.

At present, commonly used methods for detecting wafer surface damage include microscope observation and angle polishing. However, for this kind of micro damage generated in the polishing stage, it is difficult to detect it through a microscope or other detection instruments due to its small size. As for the angle polishing method, first of all, it is used to detect the damage layer generated after wafer cutting and grinding, that is, a layer of damage layer that is prevalent on the entire surface of the wafer, and this kind of micro damage generated in the polishing process does not exist on the entire wafer surface, but is only scattered in the local area of the wafer. Therefore, if the angle polishing method is used to detect the micro damage on the wafer surface after the polishing process, The cracked chips selected for testing may not have micro damage; furthermore, even if there is micro damage in the cracked chips selected for testing, since the polishing effect of angle polishing is far inferior to the polishing effect of the polishing process in the wafer production process, it is impossible to detect the micro damage generated in the polishing stage by using the relevant detection means used when using the angle polishing method.

This section provides a general summary of the invention, but is not a comprehensive disclosure of the entire scope or all features of the invention.

One purpose of the present invention is to provide a detection method capable of detecting micro-damages of small size on the surface of a wafer.

Another object of the present invention is to provide a method for detecting micro damage on the surface of a wafer, which can detect micro damage scattered on the surface of the wafer.

In order to achieve one or more of the above purposes, according to one aspect of the present invention, a method for detecting micro-damage on the surface of a wafer is provided, which comprises: a selection step: selecting a wafer that has been polished; a single crystal layer growth step: growing a single crystal layer on the surface of the selected wafer; a heat treatment step: heat treating the wafer on which the single crystal layer has been grown; and a detection step: performing stacking layer error detection on the single crystal layer of the heat-treated wafer to determine whether the wafer has surface micro-damage.

In the above-mentioned detection method for micro-damage on the wafer surface, before the single crystal layer growth step is performed, a cleaning step may also be included: cleaning the selected wafer to remove the polishing liquid remaining on the surface of the wafer.

In the above-mentioned detection method for micro-damage on the wafer surface, the growth of a single crystal layer on the surface of the selected wafer can be achieved by chemical vapor deposition, physical vapor deposition, liquid phase epitaxy, atomic layer epitaxy or molecular beam epitaxy.

In the above-mentioned detection method for micro-damage on the wafer surface, the thickness of the single crystal layer can be 3~6um.

In the above-mentioned method for detecting micro-damage on the wafer surface, growing a single crystal layer on the surface of the selected wafer may include using chemical vapor deposition to react SiHCl ₃ with H ₂ at 1100-1200° C. for 3-5 minutes to generate a single crystal layer on the surface of the wafer.

In the above-mentioned detection method for micro-damage on the wafer surface, heat treatment of the wafer on which the single crystal layer has been grown may include heat treatment of the wafer at 1100~1200℃ for 8~16h.

In the above-mentioned detection method for micro-damage on the wafer surface, the heat treatment can be performed in a diffusion furnace, or in the case of using chemical vapor deposition to grow a single crystal layer on the surface of the selected wafer, the heat treatment can be performed in a chemical vapor deposition reaction chamber into which a protective gas is introduced.

In the above-mentioned detection method for micro-damage on the wafer surface, the protective gas can be argon.

In the above-mentioned detection method for micro-damage on the wafer surface, stacking layer error detection can be performed using X-ray diffraction topography or copper mist method.

According to another aspect of the present invention, a detection system for wafer surface micro-damage is provided, which includes: A selection unit for selecting a wafer that has been polished; a single crystal layer growth unit for growing a single crystal layer on the surface of the selected wafer; a heat treatment unit for heat-treating the wafer on which the single crystal layer has been grown; and a detection unit for performing stacking layer error detection on the single crystal layer of the heat-treated wafer to determine whether the wafer has surface micro-damage.

According to the present invention, a single crystal layer is grown on the surface of the wafer, so that a stacking layer error is formed on the micro damage and the micro damage is "magnified" to a degree that can be easily detected, so as to indirectly realize the detection of micro damage of small size. In addition, the single crystal layer is grown on the entire surface of the wafer, so all micro damage existing on the entire surface of the wafer can be "magnified" to a degree that can be easily detected, thereby enabling the micro damage scattered on the surface of the wafer to be detected.

The above-mentioned features and advantages as well as other features and advantages of the present invention will become more clear through the following detailed description of the exemplary embodiments of the present invention in conjunction with the accompanying drawings.

S101-S104: Steps

S201-S203: Steps

10: Base

11: Transmitter

12: Receiving end

100: Wafer

FIG1 is a schematic flow chart of a method for detecting micro-damage on a wafer surface according to an embodiment of the present invention; FIG2 is a schematic flow chart of using XRT to detect stacking errors in a single crystal layer grown on a wafer surface; FIG3 schematically shows the operation process of using XRT to detect stacking errors in a single crystal layer; FIG4 is a schematic flow chart of a single crystal layer grown on a wafer surface after a single crystal layer growth step and a heat treatment step. FIG5 is an XRT inspection spectrum of the single crystal layer of the wafer after the single crystal layer growth step and the heat treatment step, wherein there is no stacking layer fault in the entire area of the wafer; FIG5 is an XRT inspection spectrum of the single crystal layer of another comparison wafer after the single crystal layer growth step and the heat treatment step, wherein there is a stacking layer fault in the central area of the wafer; and FIG6 is an XRT inspection spectrum of FIG5 after grayscale processing in order to more clearly show micro damage.

In order to help the review committee understand the technical features, content and advantages of the present invention and the effects it can achieve, the present invention is described in detail as follows with accompanying drawings and appendices in the form of embodiments. The drawings used therein are only for illustration and auxiliary description purposes, and may not be the true proportions and precise configurations after the implementation of the present invention. Therefore, the proportions and configurations of the attached drawings should not be interpreted to limit the scope of application of the present invention in actual implementation.

In the description of the embodiments of the present invention, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the attached drawings, and are only for the convenience of describing the embodiments of the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention.

In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the embodiments of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

The present invention is described in detail below with reference to the accompanying drawings and by means of exemplary implementation methods. It should be noted that the following detailed description of the present invention is only for illustrative purposes and is by no means a limitation of the present invention.

During the polishing process, such as double-sided polishing, particles such as silicon slag and impurities in the polishing liquid enter the polishing area and scratch the wafer surface, resulting in micro scratches, local shallow pits and other micro damages. Due to their small size and scattered distribution on the wafer surface, it is difficult to detect them in time through some related detection equipment and detection methods.

In order to solve the above problems, the present invention indirectly detects micro damage by "magnifying" the micro damage to a level that can be easily detected and using appropriate detection means to detect the "magnified" micro damage.

Specifically, referring to FIG. 1 , the embodiment of the present invention provides a method for detecting micro-damage on the surface of a wafer, which includes: S101: a selection step: selecting a wafer that has been polished; S102: a single crystal layer growth step: growing a single crystal layer on the surface of the selected wafer; S103: a heat treatment step: performing heat treatment on the wafer on which the single crystal layer has been grown; and S104: a detection step: performing a stacking layer error detection on the single crystal layer of the heat-treated wafer to determine whether the wafer has surface micro-damage.

The selection step includes selecting test samples from the polished wafers, i.e., performing a random inspection. As mentioned above, during the polishing process, particles such as silicon slag and impurities in the polishing liquid may enter the polishing area and scratch the surface of the wafer, thereby causing micro scratches, local shallow pits and other micro damage. At this time, by performing a random inspection on the polished wafers, it can be determined whether there are particles in the polishing area, so that early intervention can be carried out.

According to the implementation of the present invention, a single crystal layer needs to be grown on the surface of the selected or sampled wafer, thereby growing a single crystal layer on the wafer surface. In the case of micro-damage on the wafer surface, when the single crystal layer is grown, single crystal atoms will accumulate upward at the micro-pits or depressions of the micro-damage, and the micro-pits or depressions will introduce stress into the accumulated and grown single crystal layer and thus cause dislocation. As the single crystal layer grows and the thickness of the single crystal layer increases, the dislocation will form a stacking error, which will also extend in the single crystal layer as the thickness of the single crystal layer continues to increase, thereby becoming obvious relative to the perfect lattice part of the single crystal layer, thereby "magnifying" the micro-damage.

After the growth of the single crystal layer is completed, the wafer with the single crystal layer needs to be heat treated again. The heat treatment can further amplify the stacking layer errors in the single crystal layer, making them more obvious relative to the perfect lattice part of the single crystal layer, so that they can be easily detected, thereby achieving the goal of "magnifying" the micro damage to a level that can be easily detected.

In this case, it is allowed to indirectly detect micro damage by detecting stacking layer errors in the single crystal layer grown on the wafer surface. Since stacking layer errors are generated in the grown single crystal layer due to micro damage, and stacking layer errors are easy to detect, for example, by some related detection equipment or methods, if the presence of stacking layer errors is detected, it can be indirectly determined that micro damage exists, thereby indirectly achieving the detection of micro damage.

In the method, a single crystal layer is grown on the surface of a wafer so that stacking errors that can be clearly distinguished relative to the perfect lattice portion of the single crystal layer are formed on the micro-damages that are small in size and difficult to detect, so as to "magnify" the micro-damages to a degree that can be easily detected, thereby indirectly realizing the detection of micro-damages of small size. Moreover, the single crystal layer is grown on the entire surface of the wafer, so all micro-damages existing on the entire surface of the wafer can be "magnified" to a degree that can be easily detected, thereby enabling the micro-damages scattered on the surface of the wafer to be detected.

In the implementation method of the present invention, before the single crystal layer growth step is performed, a cleaning step may also be included: cleaning the selected wafer to remove the polishing liquid remaining on the wafer.

There may still be some polishing liquid left on the surface of the polished wafer, which will have an adverse effect on the growth of a single crystal layer on the wafer surface. The wafer surface can be cleaned with water, for example, to remove the remaining polishing liquid, and the single crystal layer growth step can be continued after drying.

It can be understood that the single crystal layer is a material homogeneous with the wafer, that is, the single crystal layer is a silicon single crystal layer. In this case, the grown single crystal layer can be connected to the wafer in the same lattice structure. In contrast, lattice connection failure will occur at the micro-damage, resulting in lattice errors, which can be clearly different from the perfect lattice part of the single crystal layer, so that the micro-damage can be indirectly detected by detecting such lattice errors, i.e., stacking layer errors.

In the implementation of the present invention, the growth of a single crystal layer on the surface of a wafer can be achieved by chemical vapor deposition (CVD), physical vapor deposition (PVD), liquid phase epitaxy (LPE), atomic layer deposition (ALE) or molecular beam epitaxy (MBE).

It is conceivable that the growth of a single crystal layer on the surface of a wafer can also be achieved using other thin film deposition methods.

In the implementation method according to the present invention, the thickness of the single crystal layer can be 3~6um.

For example, when using chemical vapor deposition to grow a single crystal layer on the surface of a wafer, SiHCl ₃ and H ₂ can be introduced into a chemical vapor deposition reaction chamber as raw materials, and reacted at 1100~1200°C for 3~5 minutes to generate a single crystal layer on the surface of the wafer. In this way, the thickness of the generated silicon single crystal layer can be approximately 3~6um.

In an implementation of the present invention, heat treatment of a wafer having grown a single crystal layer may include heat treating the wafer at 1100-1200°C for 8-16 hours.

The heat treatment can be carried out at 1100~1200℃ for 8~16h in a diffusion furnace, or in the case of growing a single crystal layer on the surface of the wafer by chemical vapor deposition, it can be carried out at 1100~1200℃ for 8~16h in a chemical vapor deposition reaction chamber with a protective gas such as argon (Ar) gas.

After the above heat treatment, the single crystal layer is subjected to stacking layer error detection to detect micro damage. In the implementation mode of the present invention, the stacking layer error detection can be performed using X-ray Diffraction Topography (XRT) or copper mist method. It is understandable that the detection of stacking layer errors in the single crystal layer can also be achieved using other suitable methods.

Below, the process of detecting stacking errors using XRT is further described in conjunction with Figures 2 to 6.

As shown in Figures 2 and 3, after the wafer has been cleaned, grown and heat treated, XRT can be used to detect stacking errors in the single crystal layer, including the following steps: S201: placing the wafer 100 processed in the above steps on the base 10 to be tested; S202: selecting the test crystal plane and setting parameters; and S203: turning on the X-ray source to perform transmission scanning on the entire wafer, that is, by emitting X-rays from the emitting end 11 to the test crystal plane and receiving the diffracted X-rays from the receiving end 12, a projection pattern of the entire wafer is obtained.

In XRT, areas with defects such as stacking errors do not meet the angle requirements of Bragg diffraction, resulting in a difference in contrast between the XRT pattern in this area and the XRT pattern in a perfect area, which can show the defect.

Referring to Figures 4 to 6, the XRT spectrum when no stacking layer error is detected, the XRT spectrum when a stacking layer error is detected, and the XRT spectrum after grayscale processing when a stacking layer error is detected are respectively shown.

It can be clearly seen in Figure 5 and more obviously in Figure 6 that a very obvious arc-shaped mark appears in the central area of the test wafer shown, which is the stacking layer error. Therefore, it can be determined that there are micro-damages in the test wafers shown in Figures 5 and 6.

In addition, it should be noted that in the XRT spectra shown in Figures 4 to 6, there are also multiple traces on the edge of the wafer, but these are only edge layer errors caused by damage caused by the wafer contacting the furnace during heat treatment, and have nothing to do with the micro-damage generated in the polishing stage and can be ignored.

The copper mist method can also be used to detect stacking errors in single crystal layers.

After the wafer has been cleaned, grown and heat treated, the copper mist method can be used to detect stacking errors in the single crystal layer, including the following steps: immersing the wafer in a copper salt solution such as copper chloride solution or copper nitrate solution for 5 hours; drying the wafer and heat treating it at 1100°C for 1 hour, and then lowering the wafer temperature to room temperature; and observing the surface of the wafer under a microscope to determine the stacking error area.

In the copper mist method, the solid solubility of copper ions in silicon is very large at high temperatures, and ions can easily enter the wafer. At relatively low temperatures, the solid solubility of copper ions drops sharply, and copper ions precipitate outward. During the cooling process, copper ions in silicon tend to gather in the stacking layer error area instead of precipitating outward. Therefore, the area on the surface where there is no copper precipitation after cooling is the stacking layer error area.

Therefore, when observing the surface of the wafer under a microscope, if there is a part on the surface without copper precipitation, this part is the stacking layer error area, and thus it can be determined that there is micro damage in the test wafer.

According to another aspect of the present invention, a detection system for micro-damage on the surface of a wafer is also provided, which includes: a selection unit for selecting a wafer that has been polished; a single crystal layer growth unit: for growing a single crystal layer on the surface of the selected wafer; a heat treatment unit: for heat treating the wafer on which the single crystal layer has been grown; and a detection unit: for performing stacking layer error detection on the single crystal layer of the heat-treated wafer to determine whether the wafer has surface micro-damage.

According to an embodiment of the present invention, the detection system for micro-damage on the wafer surface may also include a cleaning unit, which is used to clean the selected wafer before the single crystal layer growth unit grows a single crystal layer on the surface of the selected wafer to remove the polishing liquid remaining on the surface of the wafer.

The above is only a preferred embodiment of the present invention and is not intended to limit the scope of implementation of the present invention. If the present invention is modified or replaced by something equivalent without departing from the spirit and scope of the present invention, it shall be covered by the protection scope of the patent application of the present invention.

S101-S104: Steps

Claims (9)

A method for detecting micro-damage on the surface of a wafer, comprising: a selection step: selecting a wafer that has been polished; a single crystal layer growth step: growing a single crystal layer on the surface of the selected wafer, the thickness of the single crystal layer being 3-6 um; a heat treatment step: performing heat treatment on the wafer on which the single crystal layer has been grown; and a detection step: performing stacking layer error detection on the single crystal layer of the wafer that has been heat treated to determine whether the wafer has surface micro-damage. The method for detecting micro-damage on the surface of a wafer as described in claim 1, wherein before the single crystal layer growth step is performed, a cleaning step is also included: the selected wafer is cleaned to remove the polishing liquid remaining on the surface of the wafer. A method for detecting micro-damage on a wafer surface as described in claim 1 or 2, wherein the growth of a single crystal layer on the surface of the selected wafer is achieved by chemical vapor deposition, physical vapor deposition, liquid phase epitaxy, atomic layer epitaxy or molecular beam epitaxy. A method for detecting micro-damage on a wafer surface as described in claim 1 or 2, wherein the growing of a single crystal layer on the surface of the selected wafer comprises utilizing chemical vapor deposition to react SiHCl ₃ and H ₂ at 1100-1200°C for 3-5 minutes to generate a single crystal layer on the surface of the wafer. The method for detecting micro-damage on the surface of a wafer as described in claim 1 or 2, wherein the heat treatment of the wafer having grown the single crystal layer includes heat treating the wafer at 1100-1200°C for 8-16 hours. A method for detecting micro-damage on a wafer surface as described in claim 1 or 2, wherein the heat treatment is performed in a diffusion furnace, or when chemical vapor deposition is used to grow a single crystal layer on the surface of the selected wafer, the heat treatment is performed in a chemical vapor deposition reaction chamber into which a protective gas is introduced. A method for detecting micro-damage on a wafer surface as described in claim 6, wherein the protective gas is argon. A method for detecting micro-damage on a wafer surface as described in claim 1 or 2, wherein the stacking layer error detection is performed using X-ray diffraction topography or copper mist method. A detection system for wafer surface micro-damage includes: a selection unit for selecting a wafer that has been polished; a single crystal layer growth unit for growing a single crystal layer on the surface of the selected wafer, the thickness of the single crystal layer being 3-6 um; a heat treatment unit for heat-treating the wafer on which the single crystal layer has been grown; and a detection unit for performing stacking layer error detection on the single crystal layer of the wafer that has been heat-treated to determine whether the wafer has surface micro-damage.