TWI826908B - 積體晶片及其形成方法 - Google Patents

積體晶片及其形成方法 Download PDF

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Publication number
TWI826908B
TWI826908B TW111103032A TW111103032A TWI826908B TW I826908 B TWI826908 B TW I826908B TW 111103032 A TW111103032 A TW 111103032A TW 111103032 A TW111103032 A TW 111103032A TW I826908 B TWI826908 B TW I826908B
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TW
Taiwan
Prior art keywords
electrode
top electrode
hard mask
bottom electrode
layer
Prior art date
Application number
TW111103032A
Other languages
English (en)
Chinese (zh)
Other versions
TW202318646A (zh
Inventor
張富宸
陳姿妤
石昇弘
涂國基
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US17/519,808 external-priority patent/US20220059550A1/en
Priority claimed from US17/528,611 external-priority patent/US11800720B2/en
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW202318646A publication Critical patent/TW202318646A/zh
Application granted granted Critical
Publication of TWI826908B publication Critical patent/TWI826908B/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H01L28/56—Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/40—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the peripheral circuit region

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW111103032A 2021-07-12 2022-01-25 積體晶片及其形成方法 TWI826908B (zh)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US202163220683P 2021-07-12 2021-07-12
US63/220,683 2021-07-12
US17/519,808 US20220059550A1 (en) 2019-07-31 2021-11-05 Memory cell with offset interconnect via
US17/519,808 2021-11-05
US17/528,611 2021-11-17
US17/528,611 US11800720B2 (en) 2019-07-31 2021-11-17 Memory cell having a top electrode interconnect arranged laterally from a recess

Publications (2)

Publication Number Publication Date
TW202318646A TW202318646A (zh) 2023-05-01
TWI826908B true TWI826908B (zh) 2023-12-21

Family

ID=84533932

Family Applications (1)

Application Number Title Priority Date Filing Date
TW111103032A TWI826908B (zh) 2021-07-12 2022-01-25 積體晶片及其形成方法

Country Status (4)

Country Link
KR (1) KR20230010574A (ko)
CN (1) CN115696931A (ko)
DE (1) DE102022100837A1 (ko)
TW (1) TWI826908B (ko)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010018237A1 (en) * 2000-01-13 2001-08-30 Walter Hartner Method for fabricating a nonvolatile dram memory cell
US20070114590A1 (en) * 2002-03-18 2007-05-24 Fujitsu Limited Semiconductor device and method of manufacturing the same
TW202013728A (zh) * 2018-09-27 2020-04-01 台灣積體電路製造股份有限公司 積體晶片及形成積體晶片的方法
TW202107678A (zh) * 2019-07-31 2021-02-16 台灣積體電路製造股份有限公司 積體晶片及其形成方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160064391A1 (en) 2014-08-26 2016-03-03 Qualcomm Incorporated Dynamic random access memory cell including a ferroelectric capacitor
US10790439B2 (en) 2018-07-24 2020-09-29 Taiwan Semiconductor Manufacturing Co., Ltd. Memory cell with top electrode via

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010018237A1 (en) * 2000-01-13 2001-08-30 Walter Hartner Method for fabricating a nonvolatile dram memory cell
US20070114590A1 (en) * 2002-03-18 2007-05-24 Fujitsu Limited Semiconductor device and method of manufacturing the same
TW202013728A (zh) * 2018-09-27 2020-04-01 台灣積體電路製造股份有限公司 積體晶片及形成積體晶片的方法
TW202107678A (zh) * 2019-07-31 2021-02-16 台灣積體電路製造股份有限公司 積體晶片及其形成方法

Also Published As

Publication number Publication date
KR20230010574A (ko) 2023-01-19
TW202318646A (zh) 2023-05-01
CN115696931A (zh) 2023-02-03
DE102022100837A1 (de) 2023-01-12

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