TWI792307B - 半導體結構與其裝置及半導體裝置的形成方法 - Google Patents

半導體結構與其裝置及半導體裝置的形成方法 Download PDF

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TWI792307B
TWI792307B TW110116907A TW110116907A TWI792307B TW I792307 B TWI792307 B TW I792307B TW 110116907 A TW110116907 A TW 110116907A TW 110116907 A TW110116907 A TW 110116907A TW I792307 B TWI792307 B TW I792307B
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layer
germanium
silicon
gate
fin structure
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TW110116907A
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TW202201564A (zh
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黃懋霖
朱龍琨
徐崇威
余佳霓
江國誠
程冠倫
王志豪
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台灣積體電路製造股份有限公司
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Abstract

本揭露之一種半導體裝置，包括在一基底上方的一鰭片結構、設置於鰭片結構上方的矽奈米結構的一垂直堆疊、設置在鰭片結構周圍的一隔離結構、包裹在前述垂直堆疊中各個矽奈米結構周圍的一含鍺之界面層、包裹在含鍺之界面層周圍的一閘極介電層、以及包裹在閘極介電層周圍的一閘極電極層。

Description

半導體結構與其裝置及半導體裝置的形成方法
本發明實施例內容是有關於一種半導體結構與其裝置及半導體裝置的形成方法，特別是有關於一種具有可引入偶極子或固定電荷的界面層的半導體結構與其裝置及半導體裝置的形成方法，以增進所製得的半導體裝置的性能。
半導體積體電路(IC)工業的發展已經歷經了快速的成長。積體電路材料和設計上的技術進步已經產生了許多世代的積體電路，其中每一世代都比前一世代具有更小、更複雜的電路。在積體電路發展的過程中，通常增加了功能密度(即，每個晶片區域的互連裝置的數量)，而幾何尺寸(即，使用製程可以產生的最小部件(或線) )則縮減了。此種按比例縮減尺寸的製程通常藉由提高生產效率和降低相關成本而提供好處。而尺寸縮減也增加了製作積體電路之製程步驟的複雜性。
例如，隨著積體電路(IC)技術朝著更小的技術節點發展，已經引入了多閘極裝置(multi-gate devices)，以藉由增加閘極-通道耦合(gate-channel coupling)、減小關閉狀態的電流和減少短通道效應(short-channel effects，SCE)來改善閘極控制。多閘極裝置通常是指具有設置在通道區一側以上的一閘極結構或其一部分的裝置。類鰭式場效電晶體(FinFET)和多橋通道(multi-bridge-channel，MBC)電晶體是多閘極裝置的示例，這些裝置已經成為高性能和低漏電流應用的受重視和有前景的候選裝置者。鰭式場效電晶體(FinFET)具有超過一側被閘極包裹(例如，閘極包裹了自基底延伸而來的半導體材料之「鰭片」的頂部和側壁)的一抬升通道(elevated channel)。多橋通道(MBC)電晶體具有可以部分或全部圍繞著一通道區域延伸的一閘極結構，以提供對兩側或更多側的通道區域的存取。由於多橋通道(MBC)電晶體的閘極結構圍繞通道區域，因此多橋通道(MBC)電晶體也可以稱為環繞式閘極電晶體(surrounding gate transistor，SGT)或環繞式閘極(gate-all-around，GAA)電晶體。多橋通道(MBC)電晶體的通道區可以由奈米線、奈米片或其他奈米結構而形成，並且由於這個原因，多橋通道(MBC)電晶體也可以被稱為奈米線電晶體或奈米片電晶體。
目前已經提出了幾種方法以獲得期望的p型場效電晶體(PFETs)的臨界電壓(threshold voltages)。在其中一種技術中，可以在矽通道上堆疊超過一層的p型功函數金屬層以獲得期望的臨界電壓。在另一種技術中，將p型裝置中的矽通道替換為矽鍺通道(silicon germanium channels)。但是，這些方法遇到了不同的挑戰。關於前者，確定出可實現令人滿意的能帶間隙的p型功函金屬是具有挑戰性的。關於後者，事實證明矽鍺通道的集成是具有挑戰性的。因此，儘管用於形成多橋通道(MBC)裝置的常規技術通常對於它們的預期目的是適當的，但是這些常規技術並不是在所有方面都是令人滿意。
本發明的一些實施例提供一種半導體結構。此半導體結構包括在一基底上方的一鰭片結構、設置於鰭片結構上方的矽奈米結構(silicon nanostructures)的一垂直堆疊、設置在鰭片結構周圍的一隔離結構(isolation structure)、包裹在前述垂直堆疊中各個矽奈米結構周圍的一含鍺之界面層(germanium-containing interfacial layer)、包裹在含鍺之界面層周圍的一閘極介電層(gate dielectric layer)、以及包裹在閘極介電層周圍的一閘極電極層(gate electrode layer)。
本發明的一些實施例又提供一種半導體裝置。此半導體裝置包括一p型電晶體和一n型電晶體。p型電晶體包括位於一基底之上的一第一鰭片結構(first fin structure)、設置在此第一鰭片結構上方的多個第一矽奈米結構、包裹該些第一矽奈米結構之周圍的第一界面層(first interfacial layer)、包裹第一界面層之周圍的一閘極介電層、以及包裹閘極介電層之周圍的一閘極電極層。此n型電晶體包括在基底上方的一第二鰭片結構(second fin structure)、設置在第二鰭片結構上方的多個第二矽奈米結構、包裹各個第二矽奈米結構之周圍並與之接觸的第二界面層(a second interfacial layer)、包裹第二界面層之周圍的閘極介電層以及包裹在閘極介電層周圍的閘極電極層。第一界面層的組成係不同於第二界面層的組成。
本發明的一些實施例提供一種半導體裝置的形成方法。此形成方法包括交替地堆疊多個第一磊晶層(first epitaxy layers)和多個第二磊晶層(second epitaxy layers)，以在一基底上方形成一半導體堆疊(semiconductor stack)，圖案化前述半導體堆疊以形成一鰭片，去除鰭片的前述第一磊晶層以從前述第二磊晶層形成多個奈米結構(nanostructures)，形成一含鍺之覆蓋層包覆前述奈米結構的周圍，進行一預清洗製程(pre-clean process)以將至少一部分的前述含鍺之覆蓋層轉換成一含鍺之界面層，沉積一閘極介電層以包覆前述含鍺之界面層的周圍，以及在前述閘極介電層之上形成一閘極電極層。
以下內容提供了很多不同的實施例或範例，用於實現本發明實施例的不同部件。組件和配置的具體範例描述如下，以簡化本發明實施例。當然，這些僅僅是範例，並非用以限定本發明實施例。舉例來說，敘述中若提及一第一特徵部件形成於一第二特徵部件之上方或位於其上，可能包含上述第一和第二特徵部件直接接觸的實施例，也可能包含額外的特徵部件形成於上述第一特徵和上述第二特徵部件之間，使得第一和第二特徵部件不直接接觸的實施例。另外，本發明實施例可能在許多範例中重複元件符號及/或字母。這些重複是為了簡化和清楚的目的，其本身並非代表所討論各種實施例及/或配置之間有特定的關係。
再者，當使用「約」、「大約」、或類似的用語來描述一個數值或一個數值範圍時，除非有另外指明，則此用語是用於涵蓋在一合理範圍的數值，且此範圍考量到本領域的普通技術人員所能理解的在製程期間所產生的固有的變化。例如，基於製造與此數值相關聯的部件的已知製造公差，此數值或數值範圍係涵蓋了包括所述數值的一合理範圍，例如在所述數值的+/- 10％以內。例如，厚度為「約5nm」的材料層可包含的尺寸範圍為4.25 nm至5.75 nm，其中本領域的普通技術人員已知與沈積此材料層相關的製造公差為+/- 15％。再者，本揭露可能在不同示例中重複元件符號及/或字母。此些重複是為了簡化和清楚的目的，其本身並非代表所討論各種實施例及/或配置之間具有特定關係。
本揭露係大致上關於多閘極電晶體(multi-gate transistor)及其製造方法，特別是關於用來引入偶極子(dipoles)或固定電荷的界面層(interfacial layers)。
多橋通道(multi-bridge-channel，MBC)電晶體可以是n型或p型。由於不同導電類型的多橋通道(MBC)電晶體需要不同的臨界電壓，因此已經提出了幾種臨界電壓調節的方法。例如，可以在用於n型和p型多橋通道(MBC)電晶體的閘極結構中形成不同的功函數金屬堆疊。另外，當通道構件由矽形成時，仍在尋找令人滿意的p型功函數金屬。對於另一個示例，在不同的裝置區域中實現了不同的通道材料。前一種方法需要在緊密間隔排列的通道構件周圍和之間堆疊幾層的功函數金屬層。後者涉及用於不同半導體組成的通道構件的製程的集成。在這兩種示例方法中，製程窗口(process window)可能很小，性能可能不理想，並且製造成本可能很高。
本揭露提供了用於形成一半導體裝置的實施例方法，此半導體裝置包括矽通道(silicon channel)和設置在矽通道上的鍺覆蓋層(germanium cladding layer)。在一例示性的實施例中，在釋放通道區域中的通道構件(channel members)之後，係在通道構件的表面上沉積一含鍺覆蓋層(germanium-containing cladding layer)。進行第一退火製程(first anneal process)以驅入含鍺覆蓋層中的鍺。結果，至少一部分含鍺覆蓋層轉變成一矽鍺層(silicon germanium layer)。然後對退火的覆蓋層進行一預清洗製程(pre-clean process)。預清洗製程去除了覆蓋層的富鍺部分(germanium-rich portion)，並氧化了覆蓋層的富矽部分(silicon-rich portion)，以形成一含鍺的界面層(germanium-containing interfacial layer)。然後，在含鍺的界面層上沉積一閘極介電層。可以在沉積閘極介電層之後進行一第二退火製程(second anneal process)。可以觀察到的是，當應用在p型裝置區域中時，含鍺的界面層可能會提供偶極子或是固定電荷，從而導致p型多橋通道(MBC)電晶體具有較低的臨界電壓。換句話說，可以對一p型裝置區域中的矽通道構件進行「回火」(tempered)，以提供期望的臨界電壓。
現在將參考附圖更詳細地描述本揭露的各個方面。第1圖示出了根據本揭露的一個或多個方面的由一工件(workpiece)形成一半導體裝置的方法100的流程圖。方法100僅是一示例，並且並非旨在將本揭露限制在方法100中所明確示出的內容。在方法100之前、之間和之後，可以提供一些附加的步驟，並且可以替換、消除或者移動所描述的某些步驟。 為了簡單起見，本文沒有詳細描述所有步驟。以下結合第2圖至第21圖描述方法100，其為根據方法100之實施例的處於不同製造階段的工件的局部透視圖或剖面示意圖。
參照第1圖和第2圖，方法100包括步驟102，其中係提供一工件200。注意的是，由於工件200將被製造成一半導體裝置，所以根據上下文需要，工件200也可以被稱為半導體裝置200。     工件200可以包括一基底202。儘管在圖式中未明確示出，但是基底202可以包括用於製造不同導電類型的電晶體的n型井區(n-type well region)和p型井區。在一實施例中，基底202可以是一矽基底。在一些其他實施例中，基底202可以包括其他半導體，例如鍺(Ge)、矽鍺(SiGe)、或III-V族半導體材料。III-V半導體材料的示例可以包括砷化鎵(gallium arsenide，GaAs)、磷化銦(indium phosphide，InP)、磷化鎵(gallium phosphide，GaP)、氮化鎵(gallium nitride，GaN)、磷化砷化鎵(gallium arsenide phosphide，GaAsP)、砷化鋁銦(aluminum indium arsenide，AlInAs)、砷化鋁鎵(aluminum gallium arsenide，AlGaAs)、磷化銦鎵鎵(gallium indium phosphide，GaInP)和砷化銦鎵(indium gallium arsenide，InGaAs)。基底202還可以包括一絕緣層，例如氧化矽層，而具有一絕緣體上覆矽(silicon-on-insulator，SOI)結構。當存在有絕緣層時，各個n型井和各個p型井中都形成在基底202中並且包括一摻雜分佈。n型井可以包括一n型摻質的摻雜分佈，n型摻質例如是磷(P)或砷(As)。p型井可以包括一p型摻質的摻雜分佈，p型摻質例如是硼(B)。可以使用離子注入或熱擴散來形成n型井和p型井中的摻雜分佈，並且可以將其視為基底202的一部分。為避免疑問，X方向、Y方向和Z方向係為彼此垂直。
如第2圖所示，工件200還包括設置在基底202上方的一堆疊件(stack)204。堆疊件204包括交錯設置的多個通道層(channel layers)208與多個犧牲層(sacrificial layers)206。通道層208和犧牲層206可具有不同的半導體組成。在一些實施方式中，通道層208由矽(Si)形成，而犧牲層206由矽鍺(SiGe)形成。在這些實施方案中，犧牲層206中的額外鍺含量可使得選擇性去除或下凹犧牲層206時不會對通道層208造成實質性的損壞。在一些實施例中，犧牲層206和通道層208是磊晶層(epitaxy layers)，並且可以使用磊晶製程(epitaxy process)沉積。合適的磊晶製程包括氣相磊晶(vapor-phase epitaxy，VPE)、超高真空化學氣相沉積(ultra-high vacuum chemical vapor deposition，UHV-CVD)、分子束磊晶(molecular beam epitaxy，MBE)、以及/或其他合適的製程。如第2圖所示，犧牲層206和通道層208一個接一個的交替沉積，以形成堆疊件204。注意的是，如第2圖所示之五層的犧牲層206和五層的通道層208交替和垂直的分佈設置，這僅出於說明的目的，並非意圖用於限制權利要求書中具體敘述的範圍。可以理解的是，可以在堆疊件204中形成任何數量的犧牲層206和通道層208。材料層的數量取決於裝置200的通道構件的期望數量。在一些實施例中，通道層的數量208在2到10之間。
參照第1圖和第3圖，方法100包括步驟104，其中由堆疊件204形成一鰭片結構(fin-shaped structure)214。在一些實施例中，將堆疊件204和基底202的一部分圖案化，以形成鰭片結構214。出於圖案形成的目的，可以在堆疊件204上沉積一硬遮罩層210。硬遮罩層210可以是單層或多層。在一示例中，硬遮罩層210包括一氧化矽層211和在氧化矽層211之上的一氮化矽層212。如第3圖所示，鰭片結構214自基底沿著Z方向垂直地延伸，並沿著Y方向縱向地延伸。鰭片結構214包括由基底202形成的一基底部分(base portion)214B和由堆疊件204形成的一堆疊部分(stack portion)214S。可以使用包括雙重圖案化(double-patterning)或多重圖案化(multi-patterning)製程在內的合適的製程來圖案化鰭片結構214。一般而言，雙重圖案化或多重圖案化製程是結合了光學微影及自對準製程，得以使形成的圖案的節距(pitch)小於使用單一、直接的光學微影製程所能得到的節距。例如，在一實施例中，在一基底的上方形成一材料層，並使用一光學微影製程將此材料層圖案化。使用自對準製程在上述已圖案化的材料層旁邊形成間隔物(spacers)。然後移除材料層，利用留下的間隔物或芯軸(mandrels)藉由蝕刻堆疊件204和基底202以圖案化上述鰭片結構214。在一些實施例中，遮罩(或是其他層)可留在鰭片上方。蝕刻製程可以包括乾式蝕刻、濕式蝕刻、反應性離子蝕刻(reactive ion etching，RIE)以及/或其他合適的製程。
參照第1圖、第4圖、第5圖和第6圖。方法100包括步驟106，其中在鰭片結構214上方形成一虛置閘極堆疊(dummy gate stack)224。在第4圖所示的一些實施例中，在進行步驟104之後，可以在鰭片結構214的基底部分214B的附近並圍繞鰭片結構214的基底部分214B形成一隔離部件(isolation feature)216。隔離部件216設置在鰭片結構214和另一鰭片結構214(未示出)之間。隔離部件216也可以稱為淺溝槽隔離(shallow trench isolation，STI)部件216。在一示例製程中，首先在工件200上方沉積一介電層，且介電層填充位於鰭片結構214和相鄰的另一鰭片結構214之間的溝槽。介電材料形成的第二形狀的結構214。在一些實施例中，介電層可以包括氧化矽、氮化矽、氮氧化矽、摻氟矽酸鹽玻璃(fluorine-doped silicate glass，FSG)、低介電常數介電質、前述之組合以及/或其他合適的材料。在各種示例中，可以通過化學氣相沉積(chemical vapor deposition，CVD)製程、次大氣壓化學氣相沉積(subatmospheric CVD，SACVD)製程、可流動式化學氣相沉積(flowable CVD)製程、原子層沉積(atomic layer deposition，ALD)製程、物理氣相沉積(physical vapor deposition，PVD)製程、旋轉塗佈(spin-on coatin)、以及/或其他合適的製程來沉積此介電層。然後，例如通過一化學機械研磨(chemical mechanical polishing，CMP)製程來使沉積的介電材料變薄並平坦化。可通過乾式蝕刻製程、濕式蝕刻製程以及/或前述之組合使平坦化的介電層進一步凹陷，以形成隔離部件216。如第4圖所示，鰭片結構214的堆疊部分214S抬升，而高於隔離部件216。如第4圖所示，也可以在形成隔離部件216的期間去除硬遮罩層210。
在一些實施例中，係採用一閘極替換製程(或一閘極後製製程)，其中虛置閘極堆疊224(如第5圖所示)做為一功能性閘極結構的佔位件。也可以使用其他製程和配置方式。為了形成虛置閘疊224，如第4圖所示，在工件200上方沉積一虛置介電層(dummy dielectric layer)218、一虛置閘極層(dummy gate electrode layer)220和一閘極頂部硬遮罩層(gate-top hard mask layer)222。可以使用包括低壓化學氣相沉積(LPCVD)、化學氣相沉積、電漿輔助化學氣相沉積(plasma-enhanced CVD，PECVD)製程、物理氣相沉積(physical vapor deposition，PVD)、原子層沉積(atomic layer deposition，ALD)、熱氧化、電子束蒸發、或其他合適的沉積技術、或前述之組合來沉積這些材料層。虛置介電層218可以包括氧化矽，虛置閘極層220可以包括多晶矽，並且閘極頂部硬遮罩層222可以是包括氧化矽和氮化矽的一多層結構。使用光學微影和蝕刻製程，以圖案化閘極頂部硬遮罩層222。光學微影製程可以包括光阻塗佈(例如，旋轉塗佈)、軟烘烤、遮罩對準、曝光、曝光後烘烤、光阻顯影、沖洗、乾燥(例如，旋轉乾燥以及/或硬烘烤)、其他合適的微影技術、以及/或前述方法之組合。光學。蝕刻製程可以包括乾式蝕刻(例如反應性離子蝕刻)、濕式蝕刻和/或其他蝕刻方法。之後，使用圖案化的閘極頂部硬遮罩層222作為蝕刻遮罩，然後蝕刻虛置介電層218和虛置閘極層220，以形成虛置閘極堆疊224。如第5圖所示，虛置閘極堆疊224形成在隔離部件216上方，並且至少部分地設置在鰭片結構214上。如第5圖所示，虛置閘極堆疊224係沿著X方向縱向延伸，以在鰭片結構214上包裹鰭片結構214。位於虛置閘極堆疊224下方的鰭片結構214的部分則是一通道區(channel region)214C。通道區214C和虛置閘極堆疊224還定義了未與虛置閘極堆疊224垂直重疊的源極/汲極區214(source/drain regions)SD。通道區214C設置在兩個源極/汲極區214SD之間。
參照第6圖，步驟106可包括在虛置閘極堆疊224的頂表面和側壁上方形成一閘極間隔層(gate spacer layer)226。在一些實施例中，閘極間隔層226的形成包括在工件200上順應性的沉積一或多個介電層。在一示例性的製程，使用化學氣相沉積(CVD)、次大氣壓化學氣相沉積(SACVD)或原子層沉積(ALD)沉積一個或多個介電層。前述一或多個介電層可包括氧化矽、氮化矽、碳化矽、氮氧化矽、碳氮化矽、碳氧化矽、碳氮氧化矽、以及/或前述之組合。
參照第1圖和第7圖，方法100包括步驟108，其中在鰭片結構214中形成源極/汲極溝槽(source/drain trenches)228。
在第7圖所示的實施例中，在沉積閘極間隔層226之後，係以一蝕刻製程對工件200進行蝕刻。如第7圖所示，蝕刻製程去除了閘極頂部硬遮罩層222的頂表面上的閘極間隔層226，並且下凹鰭片結構214的未被閘極頂部硬遮罩層222及閘極間隔層226遮住的源極/汲極區214SD。源極/汲極區214SD的凹陷形成了由閘極間隔層226定義的源極/汲極溝槽228。步驟108處的蝕刻製程可以是乾式蝕刻製程、或是其他合適的蝕刻製程。示例性的乾式蝕刻製程可以實施含氧氣體、氫氣、含氟氣體(例如CF4 ，SF6 ，CH2 F2 ，CHF3 和/或C2 F6 )、含氯氣體(例如Cl2 ，CHCl3 ，CCl4 和/或BCl3 )、含溴氣體(例如HBr和/或CHBR3 )、含碘氣體、其他合適的氣體以及/或電漿、以及/或前述之組合。如第7圖所示，通道區214C中的犧牲層206和通道層208的側壁係暴露在源極/汲極溝槽228中。
參照第1圖和第8圖，方法100包括步驟110，其中係形成內部間隔物部件(inner spacer features)230。在步驟110中，在源極/汲極溝槽228中暴露出的犧牲層206被選擇性地和部分地下凹以形成內部間隔物凹陷(inner spacer recesses)，同時暴露出的通道層208被適當地蝕刻。在通道層208主要由矽(Si)組成並且犧牲層206主要由矽鍺(SiGe)組成的一實施例中，選擇性和部分地下凹犧牲層206的步驟可以包括SiGe氧化製程，然後去除SiGe氧化物。在這樣的實施例中，SiGe氧化製程可以包括使用臭氧(O3 )。在一些其他實施例中，選擇性的下凹製程可以是選擇性的等向性蝕刻製程(例如，選擇性乾式蝕刻製程、或選擇性濕式蝕刻製程)，並且犧牲層206的凹陷程度係由蝕刻製程的持續時間控制。選擇性乾式蝕刻製程可以包括使用一種或多種基於氟的蝕刻劑(fluorine-based etchants)，例如含氟氣體或氫氟碳化合物。選擇性濕式蝕刻製程可以包括氟化氫(HF)或氫氧化銨(NH4OH)蝕刻劑。在形成內部間隔物凹陷之後，將一內部間隔物材料層(inner spacer material layer)沉積在工件200上，包括沉積在內部間隔物凹陷中。內部間隔物材料層可以包括氧化矽、氮化矽、碳氧化矽、碳氮氧化矽、碳氮化矽、金屬氮化物、或合適的介電材料。然後，回蝕沉積的內部間隔物材料層，以去除閘極間隔層226上和通道層208的側壁上多餘的內部間隔物材料層，從而形成如第8圖所示的內部間隔物部件230。在一些實施例中，步驟110處的蝕刻製程可以是乾式蝕刻製程，其包括使用含氧氣體、氫氣、氮氣、含氟氣體(例如，CF4 、SF6 、CH2 F2 、CHF3 以及/或C2 F6 )、含氯氣體(例如Cl2 、CHCl3 、CCl4 以及/或BCl3 )、含溴氣體(例如HBr以及/或CHBR3 )、含碘氣體(例如CF3 I)、其他合適的氣體、以及/或電漿、以及/或前述之組合。
參照第1圖和第9圖，方法100包括步驟112，其中在源極/汲極區214SD上方的源極/汲極溝槽228(第8圖所示)中形成源極/汲極部件(source/drain features)232。在一些實施例中，可以使用例如氣相磊晶(vapor-phase epitaxy，VPE)、超高真空化學氣相沉積(ultra-high vacuum chemical vapor deposition，UHV-CVD)、分子束磊晶(molecular beam epitaxy，MBE)、以及/或其他合適的製程來形成源極/汲極部件232。磊晶成長製程可以使用氣態及/或液態前驅物，其與基底202以及通道層208的成分相互作用。因此，源極/汲極部件232耦合到通道層208或者釋出的通道構件2080(channel members)(將在下面進行說明)。取決於待形成的多橋通道(MBC)電晶體的導電類型，源極/汲極部件232可以是n型源極/汲極部件或p型源極/汲極部件。示例性的n型源極/汲極部件可以包括Si、GaAs、GaAsP、SiP、或其他合適的材料，並且可以在磊晶製程中通過引入n型摻質例如磷(P)、砷(As)進行原位(in-situ)摻雜，或是使用一佈植製程(即，一接面佈植製程)進行異位(ex-situ)摻雜。示例性的p型源極/汲極部件可以包括Si、Ge、AlGaAs、SiGe、摻硼SiGe、或其他合適的材料，並且可以在磊晶製程期間通過引入p型摻質例如硼(B)進行原位摻雜，或是使用一佈植製程(即一接面佈植製程)進行異位摻雜。在所提出的實施例中，源極/汲極部件232是p型源極/汲極部件，並且包括摻雜硼的矽鍺(SiGe)。
參照第1、10和11圖，方法100包括步驟114，其中在工件200上方沉積一接觸蝕刻停止層(contact etch stop layer，CESL)234和一層間介電(interlayer dielectric，ILD)層236。第10圖示出了工件200的局部透視圖，圖中示出了接觸蝕刻停止層234相對於源極/汲極部件232、閘極間隔層226的相對位置。第11圖示出了工件200沿X方向的局部剖視圖，虛置閘極堆疊224沿X方向縱向延伸。接觸蝕刻停止層234可以包括氮化矽、氧化矽、氮氧化矽、以及/或本領域已知的其他材料，並且可以通過原子層沉積(ALD)、電漿輔助化學氣相沉積(PECVD)製程、以及/或其他合適的沉積製程或氧化製程來形成。如第10和11圖所示，接觸蝕刻停止層234可以沉積在源極/汲極部件232的頂表面上並且沿著閘極間隔層226的側壁。雖然接觸蝕刻停止層234也沉積在閘極間隔層226的頂表面上和閘極頂部硬遮罩層222上，第10和11圖僅示出在通過以平坦化製程(將在下文中敘述)去除閘極頂部硬遮罩層222之後的工件200的透視圖和剖面示意圖。步驟114還包括在接觸蝕刻停止層234上方沉積層間介電層236。在一些實施例中，層間介電層236包括例如四乙氧基矽烷(Tetra Ethyl Ortho Silicate，TEOS)氧化物、未摻雜矽酸鹽玻璃、或是例如矽酸硼磷矽酸鹽玻璃(BPSG)之類的摻雜矽氧化物的材料、熔融石英玻璃(FSG)、磷矽玻璃(Phospho-Silicate Glass，PSG)、硼矽玻璃(Boro-Silicate Glass，BSG)和/或其他合適的介電材料。可以通過電漿輔助化學氣相沉積(PECVD)製程或其他合適的沉積技術來沉積層間介電層236。在一些實施例中，在形成層間介電層236之後，可以對工件200進行退火，以改善層間介電層236的完整性。可以進行一平坦化製程，例如化學機械研磨(CMP)製程，以去除多餘的材料並暴露出虛置閘極堆疊224的頂表面，如第10圖和第11圖所示。還可以通過此平坦化製程去除了閘極頂部硬遮罩層222。
參照第1圖、第12圖和第13圖，方法100包括步驟116，其中係去除虛置閘極堆疊224。參照第12圖，去除虛置閘極堆疊224而形成在通道區214C上方的閘溝槽槽(gate trench)238。如將在下面描述的，將在閘極溝槽238中形成一閘極結構250(將在下文敘述)。虛置閘極堆疊224的去除可以包括對虛置閘極堆疊224中的材料具有選擇性的一種或多種蝕刻製程。例如，虛置閘極堆疊224的去除可使用選擇性的濕式刻蝕(selective wet etch)、選擇性的乾式刻蝕、或前述之組合來進行。第13圖示出了與第12圖中的I-I′剖面一致的剖面示意圖。因此，第13圖示出了沿著Y方向的剖面示意圖，此Y方向是鰭片結構214的長度方向。如第13圖所示，在去除虛置閘極堆疊224之後，通道區214C中的通道層208和犧牲層206的側壁在閘極溝槽238中暴露。
參照第1圖和第14圖，方法100包括步驟118，其中選擇性地去除在通道區214C中的犧牲層206，以釋出通道構件2080。在去除虛置閘極堆疊224之後，方法100的步驟118可以包括用於選擇性進行去除在通道區214C中的通道層208之間的犧牲層206的步驟。選擇性去除犧牲層206係釋出了通道層208，以形成通道構件2080。在此，由於通道構件2080的尺寸小於100nm，所以通道構件2080也可以被稱為奈米結構。犧牲層206的選擇性去除可以通過選擇性乾式蝕刻、選擇性濕式蝕刻、或其他選擇性蝕刻製程來實現。在一些實施例中，選擇性濕式蝕刻包括APM蝕刻(例如，氨水-過氧化氫-水的混合物)。在一些實施例中，選擇性去除包括SiGe的氧化，接著是矽鍺氧化物的去除。例如，可以通過臭氧清潔來提供氧化，然後可通過例如NH4 OH之類的蝕刻劑而去除氧化矽鍺。
參照第1圖和第15圖，方法100包括步驟120，其中係在通道構件2080上形成一覆蓋層(cladding layer)240。在一些實施例中，覆蓋層240可以包括鍺(Ge)，並且可以使用化學氣相沉積(CVD)、原子層沉積(ALD)或磊晶方式進行沉積。用於形成覆蓋層240的一示例性化學氣相沉積(CVD)製程可以包括例如鍺烷(GeH4 )或鍺烷(Ge2 H6 )的前驅物。用於形成覆蓋層240的示例性原子層沉積(ALD)製程可以包括例如二甲基二甲基鍺二氯化鍺(dimethyl germanium dichloride，GeH2 Cl2 )和氫(H2 )的前驅物。示例性磊晶製程可以包括氣相磊晶(vapor-phase epitaxy，VPE)、超高真空化學氣相沉積(ultra-high vacuum chemical vapor deposition，UHV-CVD)和分子束磊晶(molecular beam epitaxy，MBE)。在一些其他實施例中，覆蓋層240不僅可以包括鍺，還可以包括矽。類似地，可以使用化學氣相沉積(CVD)、原子層沉積(ALD)或磊晶方式來沉積此種矽鍺覆蓋層240。此種矽鍺覆蓋層240的沉積可以包括使用含鍺的前驅物和含矽的前驅物。含鍺前驅物的例子可包括鍺烷(GeH4 )、二鍺烷(Ge2 H6 )或二甲基二氯化鍺(GeH2 Cl2 )。含矽前驅物的例子可以包括矽烷(SiH4 )、乙矽烷(Si2 H6 )、氯矽烷(SiHCl3 )、或二甲基二氯化矽(SiH2 Cl2 )。如第15圖所示，由於晶格不匹配，覆蓋層240的形成對於基底202和通道構件2080可以是選擇性的。也就是說，隔離部件216的表面可以基本上不存在覆蓋層240。在一些實施方式中，覆蓋層240形成的厚度可以在大約0.5埃(Å)至大約5埃(Å)之間。
參照第1圖和第16圖，方法100包括步驟122，其中係進行第一退火製程(first anneal process)300。第一退火製程300可以是快速熱退火(rapid thermal anneal，RTA)製程、雷射尖峰退火製程(laser spike anneal process)或快閃退火製程(flash anneal process)。第一退火製程300的作用是使覆蓋層240中的鍺擴散到通道構件2080的矽(Si)晶格中，或是導致通道構件2080中的矽(Si)與覆蓋層240中的鍺(Ge)之間的相互擴散。矽和鍺的相互擴散可引起矽和鍺的合金化，從而形成矽鍺。因此，第一退火製程300也可以被稱為鍺驅入製程。注意的是，第一退火製程300可以在形成覆蓋層240時原位進行，或者可以在形成覆蓋層240後異位進行。在前者中，是使覆蓋層240的形成和第一退火製程300在相同的製程腔室中進行，而無需破壞真空。在一些實施方式中，第一退火製程300甚至可以與覆蓋層240的形成交替進行，並且這樣的交替循環係將鍺逐漸引入通道構件2080中。在後者中，第一退火製程300和覆蓋層240的形成可以在相同的處理腔室中或在兩個不同的處理腔室中進行。
在一些實施方式中，第一退火製程300可以包括介於約600°C和約950°C之間的第一退火溫度。當第一次退火溫度低於600°C時，鍺的擴散可能不明顯。在此，第一退火溫度可以指的是第一退火製程300的峰值溫度。第一退火製程300可以導致從覆蓋層240的表面到通道構件2080中的一鍺濃度梯度。換句話說，在覆蓋層240的表面上的鍺濃度最高，並且隨著覆蓋層240的深度而逐漸降低。由於鍺濃度通常與蝕刻劑或清洗溶液中的蝕刻速率成反比，所以具有較高鍺濃度的覆蓋層240的表面部分更易於蝕刻和清潔。在覆蓋層240由鍺形成的一些情況下，覆蓋層240的最外層在第一退火製程300之後可以保持基本上無矽。鍺濃度梯度可以隨著第一退火製程300的持續時間的長度和退火溫度而變化。當退火溫度低或是退火持續時間短時，鍺濃度梯度可能是陡峭的，並且較少的鍺擴散到通道構件2080中。當退火溫度高或是退火持續時間長時，鍺濃度梯度可能是更為平坦的，並且更多的鍺可以更深地擴散到通道構件2080中。沒有第一退火製程300將鍺驅入通道構件2080，覆蓋層240沒有形成矽鍺層可以在隨後的清洗製程中被去除。
參照第1、17、18、19和20圖，方法100包括步驟124，其中在通道構件2080上方和周圍形成一閘極結構250。在所敘述的實施例中，閘極結構250沉積在閘極溝槽238中(如第12圖所示)並包括界面層242、閘極介電層244和閘極電極層246。在一些實施例中，通道構件2080以及沉積在其上的覆蓋層240可進行一預清洗製程，此預清洗製程可能包括使用RCA SC-1(氨、過氧化氫和水)以及/或RCA SC-2(鹽酸、過氧化氫和水)。如第17圖所示，預清洗製程在覆蓋層240外面形成一界面層(interfacial layer)242。如上所述，第一退火製程300已經將覆蓋層240轉換為單層的矽鍺(SiGe)層、或者一內部的矽鍺層和一外部的鍺(Ge)層。在預清洗製程中可以去除純鍺層或富鍺之矽鍺層(germanium-rich silicon germanium layers)。在預清洗製程中的氧化劑可以使富矽之鍺層氧化，以形成界面層242，此界面層因此可以包括氧化鍺、氧化矽鍺、或摻雜鍺的氧化矽。由於去除了覆蓋層240中的富鍺層，界面層242中的矽含量可以大於界面層242中的鍺含量。
參照第18圖，可以使用原子層沉積(atomic layer deposition，ALD)、物理氣相沉積(PVD)、化學氣相沉積(CVD)、氧化、以及/或其他合適的方法在界面層242上沉積閘極介電層244。閘極介電層244可以由高介電常數之介電材料形成。如本文所使用和描述的，高介電常數之介電材料包括例如介電常數大於熱氧化矽的介電常數(大約3.9)的介電材料。閘極介電層244可以包括氧化鉿。在其他示例中，閘極介電層244可以包括其他高介電常數之介電質，例如二氧化鈦(TiO2 )、氧化鋯鉿(HfZrO)、氧化鉭(Ta2 O5 )、氧化矽鉿(HfSiO4 )、二氧化鋯(ZrO2 )、氧化矽鋯(ZrSiO2 )、氧化鑭(La2 O3 )、氧化鋁(Al2 O3 )、氧化鋯(ZrO)、氧化釔(Y2 O3 )、鈦酸鍶 (SrTiO3 ；STO)、鈦酸鋇 (BaTiO3 ；BTO)、BaZrO、鉿鑭鉿氧化物(HfLaO)、鑭矽氧化物(LaSiO)、鋁矽氧化物(AlSiO)、鉿鉭氧化物(HfTaO)、鉿鈦氧化物(HfTiO)、鈦酸鍶鋇((Ba，Sr)TiO3；BST)、氮化矽(SiN)、氮氧化矽(SiON)、前述之組合、或其他合適的材料。如第19圖所示，步驟124可以包括一第二退火製程400。第二退火製程400可以是一快速熱退火(RTA)製程、一雷射尖峰退火製程(laser spike anneal process)或一快閃退火製程(flash anneal process)，並且可以包括在約700℃至約1000℃之間的一退火溫度。第二退火製程400具有消除閘極介電層244和界面層242之間的一界面處的缺陷和去除陷在此界面處的電荷的作用。在一些情況下，第二退火製程400可以在閘極介電層244和界面層242之間的界面處形成矽酸鉿(hafnium silicate)。
參照第20圖，然後使用原子層沉積(ALD)、物理氣相沉積(PVD)、化學氣相沉積(CVD)、電子束蒸發、或其他合適的方法，將閘極電極層246沉積在閘極介電層244上。閘極電極層246可包括單層或是多層結構，例如具有選定之功函數的金屬層以增強裝置性能 (功函數金屬層)、一襯裡層(liner layer)、一潤濕層(wetting layer)、一附著層、一金屬合金、或一金屬矽化物的各種組合。舉例來說，閘極電極層246可以包括氮化鈦(TiN)、鈦鋁(TiAl)、氮化鋁鈦(TiAlN)、氮化鉭(TaN)、鉭鋁(TaAl)、氮化鉭鋁(TaAlN)、碳化鉭鋁(TaAlC)、碳氮化鉭(TaCN)、鋁(Al)、鎢(W)、鎳(Ni)、鈦(Ti)、釕(Ru)、鈷(Co)、鉑(Pt)、碳化鉭(TaC)、氮化鉭矽(TaSiN)、銅(Cu) 、其他耐火金屬(refractory metals)、或其他合適的金屬材料、或前述材料之組合。此外，在半導體裝置200包括n型電晶體和p型電晶體的情況下，可以為n型電晶體和p型電晶體分別形成不同的閘極電極層，n型電晶體和p型電晶體可以包括不同的金屬層(例如，用於提供不同的n型功函數金屬層和p型功函數金屬層)。
在步驟124中，在工件200上方的閘極溝槽238(圖12所示)內形成閘極結構250(包括界面層242、閘極介電層244和閘極電極層246)。沉積在工件200上的閘極結構250係包裹每個通道構件2080。據此，閘極結構250在XZ平面上包裹每個通道構件2080。
參照第1圖和第21圖，方法100包括步驟126，在步驟126係進行後續的製程。後續進一步的製程可以包括工件200的平坦化(planarization)、形成源極/汲極接觸件(source/drain contacts)、形成閘極接觸件(gate contacts)、形成背面源極/汲極接觸件(backside source/drain contact)、以及形成互連結構(interconnect structures)。第21圖示出了在進行一平坦化製程例如一化學機械研磨(CMP)製程之後的工件200。可以進行平坦化製程，以去除閘極介電層244和閘極電極層246的多餘材料，從而提供閘極結構250的一實質上平坦的頂表面。
為了說明在方法100的操作之後的閘極結構250之構造，第21圖中其中一個通道構件2080周圍的一虛線區域係被放大，並在第22A圖或第22B圖的局部剖面示意圖中示出。在第22A圖和第22B圖的局部剖面示意圖並不是沿著X方向的局部剖面示意圖，而是沿著Y方向的局部剖面示意圖。如上所述，在第一退火製程300之後，可以將覆蓋層240轉換或合金化(converted or alloyed)而成為矽鍺層、或是成為襯有一鍺層的一矽鍺層。同時，可以形成沿著覆蓋層240之深度的一鍺濃度梯度。在步驟124處的預清洗(pre-clean)可以去除轉化的覆蓋層240的富含鍺的外部(germanium-rich outer portion)，並氧化覆蓋層240的富含矽的內部(silicon rich inner portion)。根據鍺在通道構件2080中擴散的深度，可以保留一部份的覆蓋層240。
首先參照第22A圖，當不是所有轉化的覆蓋層240都被氧化以形成界面層242時，覆蓋層240的一部分可以留下而設置在通道構件2080上。在這樣的實施例中，轉化的覆蓋層240包裹在通道構件2080的周圍，界面層242設置在留下的覆蓋層240上，閘極介電層244設置在界面層242上，並且閘極電極層246設置在閘極介電層244上。在一些情況下，在覆蓋層240和界面層242中的鍺濃度可以在約1％至約10％之間，例如在約3％至約4％之間。注意的是，可能會去除覆蓋層240的鍺濃度大於約10％的部分。在這些實施例中，覆蓋層240可以包括矽鍺，並且界面層242可以包括氧化鍺、矽鍺氧化物或摻雜鍺的氧化矽。因為界面層242包括鍺，所以界面層242也可以被稱為一含鍺的氧化層(germanium-containing oxide layer)。
先參照第22B圖，當所有轉化的覆蓋層240被氧化而形成界面層242時，基本上所有的覆蓋層240可以從通道構件2080去除。 在這些實施例中242，界面層242包裹在通道構件2080的周圍，閘極介電層244包裹在界面層242的周圍，閘極電極層246包裹在閘極介電層244的周圍。在一些情況下，界面層242中的鍺濃度可以在約1％至約10％之間，例如在約3％至約4％之間。注意的是，覆蓋層240的鍺濃度大於約10％的部分可能在預清洗製程中被去除。在這些實施例中，界面層242可以包括氧化矽、氧化鍺、氧化矽鍺、或摻雜鍺的氧化矽。由於界面層242包括鍺，因此界面層242可以被稱為含鍺的氧化層。
在第23圖所示的一些實施例中，覆蓋層240係選擇性地應用於p型多橋通道(MBC)電晶體，而沒有應用於n型多橋通道(MBC)電晶體。首先參照第23圖。第23圖示出了一工件200，其包括一p型裝置區域1000和一n型裝置區域2000。儘管未明確的示出，但是在p型裝置區域1000中的基底202可以包括一n型井，在n 型裝置區域2000中的基底202可以包括一p型井。為了使用方法100而選擇性的應用覆蓋層240，可以在n型裝置區域2000中形成一遮罩層241，以在n型裝置區域2000中遮蔽通道構件2080。遮罩層241可以是一光阻層或一底部抗反射塗層(bottom antireflective coating layer；BARC layer)。在一些情況下，BARC層可以包括氮氧化矽、氧化矽、聚合物、或前述之組合，並且可以使用化學氣相沉積(CVD)或原子層沉積(ALD)。在n型裝置區域2000被遮罩層241覆蓋的情況下，可以在p型裝置區域1000中的基底202和通道構件2080上選擇性地沉積覆蓋層240。
使用方法100和變化第23圖之製程，可以在p型裝置區域1000中形成一p型電晶體260，並且在n型裝置區域2000中形成一n型電晶體270，如圖24所示。p型電晶體260和n型電晶體270都是多橋通道(MBC)電晶體，每個多橋通道(MBC)電晶體在通道區中包括多個通道部件2080的堆疊。p型電晶體260包括p型源極/汲極部件232和圍繞每個通道構件2080的閘極結構250。n型電晶體270包括n型源極/汲極部件2320和圍繞每個通道構件2080的不含鍺的閘極結構(germanium-free gate structure)252。如上所述，p型源極/汲極部件232可以包括摻雜有p型摻質的矽鍺(SiGe)，p型摻質例如是硼(B)，並且n型源極/汲極部件2320可以包括摻雜有n型摻質的矽(Si)，n型摻質例如是磷(P)或砷(As)。為了簡潔起見，省略了p型源極/汲極部件232和n型源極/汲極部件2320的形成。如第22A圖和第22B圖所示，閘極結構250可以包括含鍺的界面層242，並且甚至可以包括覆蓋層240的剩餘部分。由於在其形成過程中缺少覆蓋層240，因此不含鍺的閘極結構252中不存在鍺，並且不含鍺的閘極結構252包括基本上由氧化矽組成的一不含鍺之界面層(germanium-free interfacial layer)243。實驗已經證明，在p型裝置區域1000中實施覆蓋層240或形成含鍺之界面層242可在約100mV至約250mV之間產生功函數的偏移，這將導致p型電晶體260的臨界電壓下降。從理論上講，功函數的偏移係源自於含鍺之界面層242處或周圍的偶極子(dipole)或固定電荷(fixed charges)的形成。
雖然不意圖是限制性的，但是本揭露的一個或多個實施例為一半導體裝置或其形成方法提供了許多益處。例如，本揭露提供了一種實施例，其包括在一p型裝置區域中的一p型多橋通道(MBC)電晶體和在一n型裝置區域中的一n型多橋通道(MBC)電晶體。p型多橋通道(MBC)電晶體和n型多橋通道(MBC)電晶體均包括了矽通道構件(silicon channel members)。為了給p型多橋通道(MBC)電晶體和n型多橋通道(MBC)電晶體提供期望的臨界電壓，在遮蔽n型裝置區域的同時，在p型裝置區域中的矽通道構件上方選擇性地沉積一含鍺的覆蓋層。覆蓋層中的鍺通過退火製程被驅入，並且覆蓋層至少部分地轉化成含鍺的界面層。在沒有覆蓋層的情況下，不含鍺的界面層沉積在n型裝置區域中。含鍺的界面層會產生偶極子或是固定電荷，以降低p型多橋通道(MBC)電晶體的臨界電壓。
在一個示例性方面，本揭露針對一種半導體結構。此半導體結構包括在一基底上方的一鰭片結構、設置於鰭片結構上方的矽奈米結構(silicon nanostructures)的一垂直堆疊、設置在鰭片結構周圍的一隔離結構(isolation structure)、包裹在前述垂直堆疊中各個矽奈米結構周圍的一含鍺之界面層(germanium-containing interfacial layer)、包裹在含鍺之界面層周圍的一閘極介電層(gate dielectric layer)、以及包裹在閘極介電層周圍的一閘極電極層(gate electrode layer)。
在一些實施例中，前述半導體結構可以進一步包括一矽鍺層(silicon germanium layer)，位於前述含鍺之界面層和前述垂直堆疊的每個矽奈米結構之間。在一些實施例中，前述含鍺之界面層包括氧化矽鍺、氧化鍺、或摻雜鍺的氧化矽。在一些實施方式中，前述含鍺之界面層設置在前述鰭片結構上。在一些情況下，前述半導體結構可以進一步包括一矽鍺層，位於前述含鍺之界面層和前述鰭片結構之間。在一些情況下，前述半導體結構可以進一步包括多個內部間隔物部件(inner spacer features)，前述內部間隔物部件係與前述垂直堆疊的矽奈米結構交錯設置。前述含鍺之界面層係接觸前述內部間隔物隔離物部件。
在另一個示例性方面，本揭露係關於一種半導體裝置。此半導體裝置包括一p型電晶體和一n型電晶體。p型電晶體包括位於一基底之上的一第一鰭片結構(first fin structure)、設置在此第一鰭片結構上方的多個第一矽奈米結構、包裹該些第一矽奈米結構之周圍的第一界面層(first interfacial layer)、包裹第一界面層之周圍的一閘極介電層、以及包裹閘極介電層之周圍的一閘極電極層。此n型電晶體包括在基底上方的一第二鰭片結構(second fin structure)、設置在第二鰭片結構上方的多個第二矽奈米結構、包裹各個第二矽奈米結構之周圍並與之接觸的第二界面層(a second interfacial layer)、包裹第二界面層之周圍的閘極介電層以及包裹在閘極介電層周圍的閘極電極層。第一界面層的組成係不同於第二界面層的組成。
在一些實施例中，前述第一界面層包括鍺，而前述第二界面層不含鍺。在一些實施例中，前述半導體裝置可以進一步包括在前述第一界面層和前述第一矽奈米結構之間的一矽鍺層。在一些實施方式中，前述第一界面層設置在前述第一鰭片結構上。在一些情況下，前述第一矽奈米結構基本上是由矽組成。在一些實施例中，前述第一界面層包括氧化矽鍺、氧化鍺、或摻雜鍺的氧化矽，並且前述第二界面層包括氧化矽。在一些實施例中，前述半導體裝置可以進一步包括複數個內部間隔物部件(inner spacer features)，前述內部間隔物部件與前述第一矽奈米結構交錯設置。前述第一界面層與前述內部間隔件部件接觸。在一些情況下，前述p型電晶體還包括耦合到前述第一矽奈米結構的一p型源極/汲極部件。 前述p型源極/汲極部件係包括矽鍺和一p型摻質。前述n型電晶體還包括耦合到前述第二矽奈米結構的一n型源極/汲極部件，並且此n型源極/汲極部件係包括矽和一n型摻質。
在又一個示例性方面，本揭露係關於一種半導體裝置的形成方法。此形成方法包括交替地堆疊多個第一磊晶層(first epitaxy layers)和多個第二磊晶層(second epitaxy layers)，以在一基底上方形成一半導體堆疊(semiconductor stack)，圖案化前述半導體堆疊以形成一鰭片，去除鰭片的前述第一磊晶層以從前述第二磊晶層形成多個奈米結構(nanostructures)，形成一含鍺之覆蓋層包覆前述奈米結構的周圍，進行一預清洗製程(pre-clean process)以將至少一部分的前述含鍺之覆蓋層轉換成一含鍺之界面層，沉積一閘極介電層以包覆前述含鍺之界面層的周圍，以及在前述閘極介電層之上形成一閘極電極層。
在一些實施例中，前述第一磊晶層基本上由矽鍺組成，而前述第二磊晶層基本上由矽組成。在一些實施例中，前述含鍺之覆蓋層的形成包括通過化學氣相沉積(CVD)、原子層沉積(ALD)、或磊晶方式，而在前述基底和前述奈米結構上沉積前述含鍺之覆蓋層。在一些實施方式中，此方法可以進一步包括在形成前述含鍺之覆蓋層之後並且在進行前述預清洗製程之前，進行一第一退火製程。在某些情況下，前述預清洗製程包括使用氫氧化氨、過氧化氫、水、或鹽酸。在一些實施例中，半導體裝置的形成方法可以進一步包括在沉積前述閘極介電層之後並且在形成前述閘極電極層之前，進行一第二退火製程。
以上概述數個實施例之部件，以便在本發明所屬技術領域中具有通常知識者可以更加理解本發明實施例的觀點。在本發明所屬技術領域中具有通常知識者應理解，他們能輕易地以本發明實施例為基礎，設計或修改其他製程和結構，以達到與在此介紹的實施例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應理解，此類等效的結構並無悖離本發明的精神與範圍，且他們能在不違背本發明之精神和範圍下，做各式各樣的改變、取代和替換。因此，本發明之保護範圍當視後附之申請專利範圍所界定為準。
100:方法 102,104,106,108,110,112,114,116,118,120,122,124, 126:步驟 200:工件(/半導體裝置) 202:基底 204:堆疊件 206:犧牲層 208:通道層 2080:通道構件 210:硬遮罩層 211:氧化矽層 212:氮化矽層 214:鰭片結構 214B:基底部分 214S:堆疊部分 214C:通道區 214SD:源極/汲極區 216:隔離部件 218:虛置介電層 220:虛置閘極層 222:閘極頂部硬遮罩層 224:虛置閘極堆疊 226:閘極間隔層 228:源極/汲極溝槽 230:內部間隔物部件 232:源極/汲極部件(/p型源極/汲極部件) 2320:n型源極/汲極部件 234:接觸蝕刻停止層 236:層間介電層 238:閘極溝槽 240:覆蓋層 241:遮罩層 242:界面層(/含鍺之界面層) 243:不含鍺之界面層 244:閘極介電層 246:閘極電極層 250:閘極結構 252:不含鍺的閘極結構 260:p型電晶體 270:n型電晶體 300:第一退火製程 400:第二退火製程 1000:p型裝置區域 2000:n型裝置區域 I-I′:剖面 X,Y,Z:方向
藉由以下的詳細描述配合所附圖式，可以更加理解本發明實施例的內容。需強調的是，根據產業上的標準慣例，許多部件(feature)並未按照比例繪製。事實上，為了能清楚地討論，各種部件的尺寸可能被任意地增加或減少。 第1圖示出了根據本揭露的一個或多個方面的由一工件(workpiece)形成一半導體裝置的方法100的流程圖。 第2圖至第21圖示出了根據本揭露的一個或多個方面，根據第1圖之方法100的一製程期間一工件的局部透視圖或剖面示意圖。 第22A、22B圖示出了根據本揭露的一個或多個方面，被一閘極結構包圍的一奈米結構(nanostructure)的放大剖面示意圖。 第23圖和第24圖示出了根據本揭露的一個或多個方面的示例性之實施例，在裝置區域中選擇性的實施一鍺覆蓋層(germanium cladding layer)之示意圖。
200:工件(/半導體裝置)
202:基底
2080:通道構件
214B:基底部分
214C:通道區
216:隔離部件
240:覆蓋層
242:界面層(/含鍺之界面層)
244:閘極介電層
246:閘極電極層
250:閘極結構
X,Y,Z:方向

Claims (13)

  1. 一種半導體結構，包括：在一基底上方的一鰭片結構(fin structure)；設置於該鰭片結構上方的一垂直堆疊，該垂直堆疊具有複數個矽奈米結構(silicon nanostructures)；設置在該鰭片結構周圍的一隔離結構(isolation structure)；包裹在該垂直堆疊的各該矽奈米結構的周圍的一含鍺之界面層(germanium-containing interfacial layer)，其中該含鍺之界面層包括氧化矽鍺、氧化鍺、或摻雜鍺的氧化矽；包裹在該含鍺之界面層周圍的一閘極介電層(gate dielectric layer)；以及包裹在該閘極介電層周圍的一閘極電極層(gate electrode layer)。
  2. 如請求項1所述之半導體結構，更包括：一矽鍺層(silicon germanium layer)，位於在該含鍺之界面層和該垂直堆疊的每該矽奈米結構之間。
  3. 如請求項1或請求項2所述之半導體結構，其中該含鍺之界面層設置在該鰭片結構上，且該半導體結構更包括：一矽鍺層，位於該含鍺之界面層和該鰭片結構之間。
  4. 如請求項1或請求項2所述之半導體結構，更包括：複數個內部間隔物部件(inner spacer features)與該垂直堆疊的該些矽奈米結構交錯設置，其中該含鍺之界面層係與該些內部間隔物隔離物部件接觸。
  5. 一種半導體裝置，包括： 一p型電晶體，包括：位於一基底之上的一第一鰭片結構(first fin structure)；設置在該第一鰭片結構之上的複數個第一矽奈米結構；包裹各該些第一矽奈米結構之周圍的一第一界面層(first interfacial layer)；包裹該第一界面層之周圍的一閘極介電層(gate dielectric layer)；及包裹該閘極介電層之周圍的一閘極電極層；以及一n型電晶體，包括：在該基底之上的一第二鰭片結構(second fin structure)；設置在該第二鰭片結構之上的複數個第二矽奈米結構；包裹各該些第二矽奈米結構之周圍並與該些第二矽奈米結構接觸的一第二界面層(second interfacial layer)；包裹該第二界面層之周圍的該閘極介電層；以及包裹該閘極介電層之周圍的該閘極電極層，其中，該第一界面層的組成係不同於該第二界面層的組成，並且其中該第一界面層包括鍺，而該第二界面層不含鍺。
  6. 如請求項5所述之半導體裝置，更包括：在該第一界面層和該些第一矽奈米結構之間的一矽鍺層。
  7. 如請求項5所述之半導體裝置，其中該第一界面層係設置在該第一鰭片結構上。
  8. 一種半導體裝置的形成方法，包括：交替地堆疊複數個第一磊晶層(first epitaxy layers)和複數個第二磊晶層(second epitaxy layers)，以在一基底上方形成一半導體堆疊(semiconductor stack)； 圖案化該半導體堆疊，以形成一鰭片；去除該鰭片的該些第一磊晶層，以自該些第二磊晶層形成複數個奈米結構(nanostructures)；形成一含鍺之覆蓋層(germanium-containing cladding layer)包覆該些奈米結構的周圍；進行一預清洗製程(pre-clean process)，以將至少一部分的該含鍺之覆蓋層轉換成一含鍺之界面層(germanium-containing interfacial layer)；沉積一閘極介電層以包覆該含鍺之界面層的周圍；以及在該閘極介電層之上形成一閘極電極層。
  9. 如請求項8所述之半導體裝置的形成方法，其中該些第一磊晶層基本上由矽鍺組成，而該些第二磊晶層基本上由矽組成。
  10. 如請求項8所述之半導體裝置的形成方法，其中前述形成該含鍺之覆蓋層包括通過化學氣相沉積(CVD)、原子層沉積(ALD)、或磊晶製程，以在該基底和該些奈米結構上沉積該含鍺之覆蓋層。
  11. 如請求項8-10任一項所述之半導體裝置的形成方法，更包括：在形成該含鍺之覆蓋層之後並且在該預清洗製程之前，進行一第一退火製程(first anneal process)。
  12. 如請求項8-10任一項所述之半導體裝置的形成方法，其中該預清洗製程係包括使用氫氧化氨、過氧化氫、水、或鹽酸。
  13. 如請求項8-10任一項所述之半導體裝置的形成方法，更包括：在沉積該閘極介電層之後並且在形成該閘極電極層之前，係進行一第二退火製程(second anneal process)。
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