CN113299733A - 半导体器件、半导体结构及其形成方法 - Google Patents

半导体器件、半导体结构及其形成方法 Download PDF

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CN113299733A
CN113299733A CN202110197939.1A CN202110197939A CN113299733A CN 113299733 A CN113299733 A CN 113299733A CN 202110197939 A CN202110197939 A CN 202110197939A CN 113299733 A CN113299733 A CN 113299733A
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layer
germanium
silicon
gate
fin structure
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CN113299733B (zh
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黄懋霖
朱龙琨
徐崇威
余佳霓
江国诚
程冠伦
王志豪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

根据本公开的半导体器件包括：鳍结构，位于衬底上方；竖直堆叠的硅纳米结构，设置在鳍结构上方；隔离结构，设置在鳍结构周围；含锗界面层，包围在每一个竖直堆叠的硅纳米结构周围；栅极介电层，包围在含锗界面层周围；以及栅电极层，包围在栅极介电层周围。本申请的实施例提供了半导体器件、半导体结构及其形成方法。

Description

半导体器件、半导体结构及其形成方法
技术领域
本申请的实施例涉及半导体器件、半导体结构及其形成方法。
背景技术
半导体集成电路(IC)工业经历了快速增长。IC材料和设计的技术进步产生了多代IC，其中，每一代都具有比先前一代更小且更复杂的电路。在IC发展过程中，功能密度(即每芯片面积上互连器件的数量)通常增大了而几何尺寸(即，使用制造工艺可以做出的最小的元件(或线))减小了。这种规模缩小工艺通常通过增加产量效率和降低相关成本来提供很多益处。这种按比例缩小工艺也增大了加工和制造IC的复杂度。
例如，随着集成电路(IC)技术朝着更小的技术节点发展，已经引入了多栅极器件，以通过增加栅极-沟道耦合、减小截止状态电流和减小短沟道效应(SCE)来改善栅极控制。多栅极器件通常是指具有栅极结构或其部分设置在沟道区域的多于一侧上方的器件。鳍式场效应晶体管(FinFET)和多桥沟道(MBC)晶体管是多栅极器件的示例，这些器件已成为高性能和低泄漏应用的流行和有希望的候选者。FinFET的升高的沟道在多于一侧上被栅极围绕(例如，栅极围绕从衬底延伸的半导体材料“鳍”的顶部和侧壁)。MBC晶体管的栅极结构可以部分或全部围绕沟道区域延伸，以提供对两侧或更多侧沟道区域的访问。由于MBC晶体管的栅极结构围绕沟道区域，所以MBC晶体管也可以称为环绕栅极晶体管(SGT)或全环栅(GAA)晶体管。MBC晶体管的沟道区域可以由纳米线、纳米片或其他纳米结构形成，并且由于这个原因，MBC晶体管也可以被称为纳米线晶体管或纳米片晶体管。
已经提出了几种方法来实现p型场效应晶体管(PFET)的理想阈值电压。在一种技术中，可以在硅沟道上堆叠一个以上p型功函数金属层以获得期望的阈值电压。在另一种技术中，将p型器件中的硅沟道替换为硅锗沟道。然而，这些方法遇到了不同的挑战。对于前者，确定p型功函数金属以实现令人满意的带隙具有挑战性。对于后者，已经证明硅锗沟道的集成具有挑战性。因此，尽管用于形成p型MBC器件的常规技术通常对于它们的预期目的是足够的，但是它们并不是在所有方面都令人满意。
发明内容
在一些实施例中，一种半导体结构，包括：鳍结构，位于衬底上方；竖直堆叠的硅纳米结构，设置在所述鳍结构上方；隔离结构，设置在所述鳍结构周围；含锗界面层，包围在每一个竖直堆叠的硅纳米结构周围；栅极介电层，包围在所述含锗界面层周围；以及栅电极层，包围在所述栅极介电层周围。
在一些实施例中，一种半导体器件，包括：p型晶体管，包括：第一鳍结构，位于衬底上方，第一多个硅纳米结构，设置在所述第一鳍结构上方，第一界面层，包围在每一个第一多个硅纳米结构周围，栅极介电层，包围在所述第一界面层周围，和栅电极层，包围在所述栅极介电层周围；以及n型晶体管，包括：第二鳍结构，位于所述衬底上方，第二多个硅纳米结构，设置在所述第二鳍结构上方，第二界面层，包围在每一个第二多个硅纳米结构周围并与之接触，栅极介电层，包围在所述第二界面层周围，和栅电极层，包围在所述栅极介电层周围，其中，所述第一界面层的组成不同于所述第二界面层的组成。
在一些实施例中，一种方法，包括：在衬底上方交替堆叠第一外延层和第二外延层以形成半导体堆叠件；图案化所述半导体堆叠件以形成鳍；从所述第二外延层去除所述鳍的第一外延层以形成纳米结构；形成包围在所述纳米结构周围的含锗覆层；执行预清洁工艺以将至少部分含锗覆层转化为含锗界面层；沉积包围在所述含锗界面层周围的栅极介电层；以及在所述栅极介电层上方形成栅电极层。
本申请的实施例提供了硅沟道回火。
附图说明
当结合附图进行阅读时，从以下详细描述可更好地理解本发明。应该强调，根据工业中的标准实践，各个部件未按比例绘制并且仅仅用于说明的目的。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1示出根据本公开的一个或多个方面的用于形成半导体器件的方法的流程图。
图2至图21示出根据本公开的一个或多个方面的在根据图1的方法的制造工艺期间的工件的局部立体图或截面图。
图22A和图22B示出根据本公开的一个或多个方面的由栅极结构围绕的纳米结构的放大截面图。
图23和图24示出根据本公开的一个或多个方面的其中在器件区域之一中选择性地实施锗覆层的示例性实施例。
具体实施方式
以下公开内容提供了许多不同实施例或实例，用于实现所提供主题的不同特征。以下将描述组件和布置的具体实例以简化本发明。当然，这些仅是实例并且不意欲限制本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例，也可以包括形成在第一部件和第二部件之间的附加部件使得第一部件和第二部件不直接接触的实施例。而且，本发明在各个实例中可以重复参考数字和/或字母。这种重复仅是为了简明和清楚，其自身并不表示所论述的各个实施例和/或配置之间的关系。
此外，当用“约”、“近似”等描述数值或数值的范围时，该词语旨在涵盖在合理范围内的数字，考虑到如本领域普通技术人员所理解的在制造期间固有地产生的变化。例如，基于与制造具有与数值相关联的特征的部件相关联的已知制造公差，数值或数值的范围涵盖包括所述数值的合理范围，诸如在所述数值的+/-10％以内。例如，厚度为“约5nm”的材料层可以涵盖4.25nm至5.75nm的尺寸范围，其中本领域普通技术人员已知与沉积材料层相关的制造公差为+/-15％。另外，本发明可以在各个实例中重复附图标号和/或字母。这种重复仅是为了简明和清楚，其自身并不表示所论述的各个实施例和/或配置之间的关系。
本公开总体上涉及多栅极晶体管和制造方法，并且更具体地涉及引入偶极子或固定电荷的界面层。
MBC晶体管可以是n型或p型。由于不同类型的MBC晶体管需要不同的阈值电压，所以已经提出了几种阈值电压调制的方法。例如，可以在用于n型和p型MBC晶体管的栅极结构中实施不同的功函数金属堆叠件。附加地，当沟道构件由硅形成时，仍在寻找令人满意的p型功函数金属。对于另一示例，在不同的器件区域中实施不同的沟道材料。前一种方法需要在紧密间隔的沟道构件周围和之间堆叠若干功函数金属层。后者涉及用于不同半导体组成的沟道构件的制造工艺的集成。在这两种示例性方法中，工艺窗口可能很小，性能可能不理想，并且制造成本可能很高。
本公开提供用于形成半导体器件的实施例方法，该半导体器件包括硅沟道和设置在硅沟道上的锗覆层。在示例性实施例中，在释放沟道区域中的沟道构件之后，在沟道构件的表面上沉积含锗覆层。执行第一退火工艺以在含锗覆层中引入锗。结果，至少部分含锗覆层转化为硅锗层。然后对退火的覆层进行预清洁工艺。预清洁工艺去除覆层的富锗部分，并氧化覆层的富硅部分，以形成含锗界面层。然后将栅极介电层沉积在含锗界面层上方。可以在沉积栅极介电层之后执行第二退火工艺。观察到，当在p型器件区域中实施时，含锗界面层可以提供偶极子或固定电荷，从而导致p型MBC晶体管的阈值电压较低。换句话说，可以对p型器件区域中的硅沟道构件进行“回火”以提供期望的阈值电压。
现在将参考附图更详细地描述本公开的各个方面。图1示出根据本公开的一个或多个方面的用于从工件形成半导体器件的方法100的流程图。方法100仅是示例，并且不旨在将本公开限制为在方法100中明确示出的内容。可在方法100之前、期间和之后提供附加步骤，并且对于方法的附加实施例，可将描述的一些步骤替换、消除或转移。为了简单起见，本文没有详细描述所有步骤。下面结合图2至图21描述方法100，其是根据方法100的实施例的处于不同制造阶段的工件的局部立体图或截面图。
参考图1和图2，方法100包括框102，其中提供工件200。应当注意，因为将工件200制造成半导体器件，所以根据上下文需要，也可以将工件200称为半导体器件200。工件200可以包括衬底202。尽管在附图中未明确示出，但是衬底202可以包括用于制造不同导电类型的晶体管的n型阱区域和p型阱区域。在一个实施例中，衬底202可以是硅(Si)衬底。在一些其他实施例中，衬底202可以包括其他半导体，诸如锗(Ge)、硅锗(SiGe)或III-V族半导体材料。示例性III-V族半导体材料可以包括砷化镓(GaAs)、磷化铟(InP)、磷化镓(GaP)、氮化镓(GaN)、磷砷化镓(GaAsP)、砷化铝铟(AlInAs)、砷化铝镓(AlGaAs)、磷化铟镓镓(GaInP)和砷化铟镓(InGaAs)。衬底202还可以包括绝缘层，诸如氧化硅层，以具有绝缘体上硅(SOI)结构。当存在时，n型阱和p型阱中的每一个形成在衬底202中并且包括掺杂分布。n型阱可以包括诸如磷(P)或砷(As)的n型掺杂剂的掺杂分布。p型阱可以包括诸如硼(B)的p型掺杂剂的掺杂分布。可以使用离子注入或热扩散来形成n型阱和p型阱中的掺杂，并且可以将其视为衬底202的部分。为避免疑问，X方向、Y方向和Z方向彼此垂直。
如图2所示，工件200还包括设置在衬底202上的堆叠件204。堆叠件204包括由多个牺牲层206交错的多个沟道层208。沟道层208和牺牲层206可以具有不同的半导体组成。在一些实施方式中，沟道层208由硅(Si)形成，而牺牲层206由硅锗(SiGe)形成。在这些实施方式中，牺牲层206中的附加锗含量允许牺牲层206的选择性去除或开槽而不会对沟道层208造成实质性损害。牺牲层206和沟道层208是外延层，并且可以使用外延工艺沉积。合适的外延工艺包括气相外延(VPE)、超高真空化学气相沉积(UHV-CVD)、分子束外延(MBE)和/或其他合适的工艺。如图2所示，牺牲层206和沟道层208一个接一个地交替沉积，以形成堆叠件204。应当注意，如图2所示，五(5)层牺牲层206和五(5)层沟道层208交替地竖直布置，这仅是出于说明的目的，并不旨在限制权利要求中具体记载的内容。可以理解，可以在堆叠件204中形成任何数量的牺牲层206和沟道层208。层的数量取决于器件200的沟道构件的期望数量。在一些实施例中，沟道层208的数量在2和10之间。
参考图1和图3，方法100包括框104，其中由堆叠件204形成鳍状结构214。在一些实施例中，将堆叠件204和衬底202的部分图案化以形成鳍状结构214。为了图案化的目的，可以在堆叠件204上方沉积硬掩模层210。硬掩模层210可以是单层或多层。在一个示例中，硬掩模层210包括氧化硅层211和氧化硅层211上方的氮化硅层212。如图3所示，鳍状结构214从衬底202沿Z方向竖直延伸，并沿Y方向纵向延伸。鳍状结构214可以包括由衬底202形成的基部214B和由堆叠件204形成的堆叠部214S。可以使用包括双图案化或多图案化工艺的合适的工艺来图案化鳍状结构214。通常，双图案化或多图案化工艺将光刻和自对准工艺组合，从而允许创建具有例如间距小于使用单一、直接光刻工艺可获得的间距的图案。例如，在一个实施例中，在衬底上方形成材料层，并使用光刻工艺对其进行图案化。使用自对准工艺在图案化的材料层旁边形成间隔件。然后去除材料层，然后可以通过蚀刻堆叠件204和衬底202来使用剩余的间隔件或心轴来图案化鳍状结构214。蚀刻工艺可以包括干蚀刻、湿蚀刻、反应离子蚀刻(RIE)和/或其他适合的工艺。
参考图1、图4、图5和图6，方法100包括框106，其中在鳍状结构214上方形成伪栅极堆叠件224。在图4所示的一些实施例中，在框104中的操作之后，可以在鳍状结构214的基部214B附近和周围形成隔离部件216。隔离部件216设置在鳍状结构214和另一鳍状结构214(未示出)之间。隔离部件216也可以称为浅沟槽隔离(STI)部件216。在示例性工艺中，首先在工件200上方沉积介电层，用介电材料填充鳍状结构214与相邻鳍状结构214之间的沟槽。在一些实施例中，介电层可以包括氧化硅、氮化硅、氮氧化硅、掺杂氟的硅酸盐玻璃(FSG)、低k电介质、它们的组合和/或其他合适的材料。在各个示例中，可以通过CVD工艺、次大气压CVD(SACVD)工艺、可流动CVD工艺、原子层沉积(ALD)工艺、物理气相沉积(PVD)工艺、旋涂和/或其他合适的工艺来沉积介电层。然后，例如通过化学机械抛光(CMP)工艺来减薄和平坦化沉积的介电材料。通过干蚀刻工艺、湿蚀刻工艺和/或它们的组合对平坦化的介电层进一步开槽以形成隔离部件216。如图4所示，鳍状结构214的堆叠部214S突出在隔离部件216之上。如图4所示，也可以在形成隔离部件216期间去除硬掩模层210。
在一些实施例中，采用栅极替换工艺(或后栅极工艺)，其中伪栅极堆叠件224(如图5所示)用作功能栅极结构的占位件。其他工艺和配置也是可能的。为了形成伪栅极堆叠件224，在工件200上方沉积伪介电层218、伪栅电极层220和栅极顶部硬掩模层222，如图4所示。这些层的沉积可以包括使用低压CVD(LPCVD)、CVD、等离子体增强CVD(PECVD)、PVD、ALD、热氧化、电子束蒸发或其他合适的沉积技术或其组合。伪介电层218可以包括氧化硅，伪栅电极层220可以包括多晶硅，并且栅极顶部硬掩模层222可以是包括氧化硅和氮化硅的多层。使用光刻和蚀刻工艺，可以对栅极顶部硬掩模层222进行图案化。光刻工艺可以包括光刻胶涂覆(例如，旋涂)、软烘烤、掩模对准、曝光、曝光后烘烤、光刻胶显影、冲洗、干燥(例如，旋干和/或硬烘烤)、其他合适的光刻技术和/或其组合。蚀刻工艺可以包括干蚀刻(例如，RIE蚀刻)、湿蚀刻和/或其他的蚀刻方法。之后，使用图案化的栅极顶部硬掩模222作为蚀刻掩模，然后蚀刻伪介电层218和伪栅电极层220，以形成伪栅极堆叠件224。如图5所示，伪栅极堆叠件224形成在隔离部件216上方，并且至少部分地设置在鳍状结构214上方。如图5所示，伪栅极堆叠件224沿X方向纵向延伸以包围在鳍状结构214上方。伪栅极堆叠件224下面的鳍状结构214的部分是沟道区域214C。沟道区域214C和伪栅极堆叠件224还限定未与伪栅极堆叠件224竖直地重叠的源极/漏极区域214SD。沟道区域214C设置在两个源极/漏极区域214SD之间。
参考图6，框106中的操作可以包括在伪栅极堆叠件224的顶面和侧壁上方形成栅极间隔件层226。在一些实施例中，栅极间隔件层226的形成包括在工件200上方共形沉积一个或多个介电层。在示例性工艺中，使用CVD、SACVD或ALD沉积一个或多个介电层。一个或多个介电层可以包括氧化硅、氮化硅、碳化硅、氮氧化硅、碳氮化硅、碳氧化硅、碳氮氧化硅和/或它们的组合。
参考图1和图7，方法100包括框108，其中在鳍状结构214中形成源极/漏极沟槽228。在图7所示的实施例中，在沉积栅极间隔件层226之后，在蚀刻工艺中蚀刻工件200。如图7所示，蚀刻工艺去除栅极顶部硬掩模层222的顶面上的栅极间隔件层226，并且对鳍状结构214的未被栅极顶部硬掩模层222和栅极间隔件层226掩蔽的源极/漏极区域214SD进行开槽。源极/漏极区域214SD的开槽获得由栅极间隔件层226限定的源极/漏极沟槽228。框108中的蚀刻工艺可以是干蚀刻工艺或合适的蚀刻工艺。示例性干蚀刻工艺可以实施含氧气体、氢气、含氟气体(例如，CF4、SF6、CH2F2、CHF3和/或C2F6)、含氯气体(例如，Cl2、CHCl3、CCl4和/或BCl3)、含溴气体(例如，HBr和/或CHBR3)、含碘气体、其他合适的气体和/或等离子体和/或它们的组合。如图7所示，沟道区域214C中的牺牲层206和沟道层208的侧壁暴露在源极/漏极沟槽228中。
参考图1和图8，方法100包括框110，其中形成内部间隔件部件230。在框110中，在源极/漏极沟槽228中暴露的牺牲层206被选择性地和部分地开槽以形成内部间隔件凹槽，同时暴露的沟道层208被适当地蚀刻。在沟道层208主要由硅(Si)组成并且牺牲层206主要由硅锗(SiGe)组成的实施例中，牺牲层206的选择性和部分的开槽可以包括SiGe氧化工艺以及之后的SiGe氧化物去除。在该实施例中，SiGe氧化工艺可以包括使用臭氧(O3)。在一些其他实施例中，选择性开槽可以是选择性各向同性蚀刻工艺(例如，选择性干蚀刻工艺或选择性湿蚀刻工艺)，并且牺牲层206被开槽的程度由蚀刻工艺的持续时间控制。选择性干蚀刻工艺可以包括使用一种或多种基于氟的蚀刻剂，诸如氟气或氢氟烃。选择性湿蚀刻工艺可以包括氟化氢(HF)或NH4OH蚀刻剂。在形成内部间隔件凹槽之后，将内部间隔件材料层沉积在工件200上方，包括在内部间隔件凹槽中。内部间隔件材料层可以包括氧化硅、氮化硅、碳氧化硅、碳氮氧化硅、碳氮化硅、金属氮化物或合适的介电材料。然后回蚀刻沉积的内部间隔件材料层，以去除栅极间隔件层226和沟道层208的侧壁上方的多余的内部间隔件材料层，从而形成如图8所示的内部间隔件部件230。在一些实施例中，框110处的回蚀刻工艺可以是干蚀刻工艺，其包括使用含氧气体、氢气、氮气、含氟气体(例如，CF4、SF6、CH2F2、CHF3和/或C2F6)、含氯气体(例如，Cl2、CHCl3、CCl4和/或BCl3)、含溴气体(例如，HBr和/或CHBr3)、含碘气体(例如，CF3I)、其他合适的气体和/或等离子体和/或它们的组合。
参考图1和图9，方法100包括框112，其中在源极/漏极区域214SD上方，在源极/漏极沟槽228(图8所示)中形成源极/漏极部件232。在一些实施例中，可以使用诸如VPE、UHV-CVD、MBE和/或其他合适的工艺的外延工艺来形成源极/漏极部件232。外延生长工艺可以使用气体和/或液体前体，其与衬底202以及沟道层208的成分相互作用。因此，源极/漏极部件232耦合至沟道层208或释放的沟道构件2080(将在下面描述)。取决于要形成的MBC晶体管的导电类型，源极/漏极部件232可以是n型源极/漏极部件或p型源极/漏极部件。示例性n型源极/漏极部件可以包括Si、GaAs、GaAsP、SiP或其他合适的材料，并且可以在外延工艺期间通过引入n型掺杂剂(诸如，磷(P)、砷(As))进行原位掺杂或使用注入工艺(即，结注入工艺)进行异位掺杂。示例性p型源极/漏极部件可以包括Si、Ge、AlGaAs、SiGe、硼掺杂的SiGe或其他合适的材料，并且可以在外延工艺期间通过引入p型掺杂剂(诸如，硼(B))进行原位掺杂或使用注入工艺(即，结注入工艺)进行异位掺杂。在所描绘的实施例中，源极/漏极部件232是p型源极/漏极部件并且包括硼掺杂的硅锗(SiGe)。
参考图1、图10和图11，方法100包括框114，其中接触蚀刻停止层(CESL)234和层间介电(ILD)层236沉积在工件200上方。图10示出工件200的局部立体图，示出CESL 234相对于源极/漏极部件232、栅极间隔件层226的相对位置。图11示出工件200沿X方向的局部截面图，伪栅极堆叠件224沿其纵向延伸。CESL 234可以包括氮化硅、氧化硅、氮氧化硅和/或本领域中已知的其他材料，并且可以通过ALD、等离子体增强化学气相沉积(PECVD)工艺和/或其他合适的沉积或氧化工艺来形成。如图10和图11所示，CESL 234可以沉积在源极/漏极部件232的顶面上并且沿着栅极间隔件层226的侧壁。尽管CESL 234也沉积在栅极顶部硬掩模层222和栅极间隔件层226的顶面上方，但是图10和图11仅示出在通过平坦化工艺(将在下面描述)去除栅极顶部硬掩模层222之后的工件200的立体图和截面图。框114还包括在CESL234上方沉积ILD层236。在一些实施例中，ILD层236包括诸如正硅酸乙酯(TEOS)氧化物、未掺杂的硅酸盐玻璃或掺杂的氧化硅(诸如硼磷硅酸盐玻璃(BPSG)、熔融石英玻璃(FSG)、磷硅酸盐玻璃(PSG)、掺杂硼的硅玻璃(BSG))的材料和/或其他合适的介电材料。可以通过PECVD工艺或其他合适的沉积技术来沉积ILD层236。在一些实施例中，在形成ILD层236之后，可以对工件200进行退火以改善ILD层236的完整性。为了去除多余的材料并暴露伪栅极堆叠件224的顶面，可以执行平坦化工艺，诸如化学机械抛光(CMP)工艺，如图10和图11所示。还通过平坦化工艺去除栅极顶部硬掩模层222。
参考图1、图12和图13，方法100包括框116，其中去除伪栅极堆叠件224。参考图12，去除伪栅极堆叠件224获得沟道区域214C上方的栅极沟槽238。如将在下面描述的，将在栅极沟槽238中形成栅极结构250(将在下面描述)。伪栅极堆叠件224的去除可以包括一个或多个蚀刻工艺，其对伪栅极堆叠件224中的材料具有选择性。例如，可以使用选择性湿蚀刻、选择性干蚀刻或其组合来执行伪栅极堆叠件224的去除。图13示出与图12中的I-I'截面一致的局部截面图。因此，图13示出沿Y方向的截面图，其为鳍状结构214的纵向方向。如图13所示，在去除伪栅极堆叠件224之后，沟道区域214C中的沟道层208和牺牲层206的侧壁暴露在栅极沟槽238中。
参考图1和图14，方法100包括框118，其中沟道区域202C中的牺牲层206被选择性地去除以释放沟道构件2080。在去除伪栅极堆叠件224之后，方法100的框118可以包括用于选择性地去除沟道区域214C中的沟道层208之间的牺牲层206的操作。牺牲层206的选择性去除释放沟道层208以形成沟道构件2080。这里，因为沟道构件2080的尺寸小于100nm，所以沟道构件2080也可以被称为纳米结构。牺牲层206的选择性去除可以通过选择性干蚀刻、选择性湿蚀刻或其他选择性蚀刻工艺来实现。在一些实施例中，选择性湿蚀刻包括APM蚀刻(例如，氢氧化铵-过氧化氢-水的混合物)。在一些实施例中，选择性去除包括SiGe氧化以及之后的硅锗氧化物去除。例如，可以通过臭氧清洁来提供氧化，然后通过诸如NH4OH的蚀刻剂去除氧化硅锗。
参考图1和图15，方法100包括框120，其中在沟道构件2080上形成覆层240。在一些实施例中，覆层240可以包括锗(Ge)并且可以使用CVD、ALD或外延沉积。用于形成覆层240的示例性CVD工艺可以包括诸如锗烷(GeH4)或乙锗烷(Ge2H6)的前体。用于形成覆层240的示例性ALD工艺可以包括诸如二甲基二氯化锗(GeH2Cl2)和氢(H2)的前体。示例性外延工艺可以包括VPE、UHV-CVD和MBE。在一些其他实施例中，覆层240不仅可以包括锗，而且可以包括硅。类似地，可以使用CVD、ALD或外延来沉积这种硅锗覆层240。这种硅锗覆层240的沉积可以包括使用含锗前体和含硅前体。示例性含锗前体可以包括锗烷(GeH4)、乙锗烷(Ge2H6)或二甲基二氯化锗(GeH2Cl2)。示例性含硅前体可以包括硅烷(SiH4)、乙硅烷(Si2H6)或氯硅烷(SiHCl3)或二甲基二氯化硅(SiH2Cl2)。如图15所示，由于晶格失配，所以覆层240的形成可以对衬底202和沟道构件2080是选择性的。也就是说，隔离部件216的表面可以基本上不存在覆层240。在一些实施方式中，可以将覆层240形成为在约0.5埃
Figure BDA0002946575210000111
与约
Figure BDA0002946575210000112
之间的厚度。
参考图1和图16，方法100包括框122，其中执行第一退火工艺300。第一退火工艺300可以是快速热退火(RTA)工艺、激光尖峰退火工艺或快速退火工艺。第一退火工艺300用于使覆层240中的锗扩散到沟道构件2080的硅(Si)晶格中或使沟道构件2080中的硅(Si)与覆层240中的锗(Ge)相互扩散。硅和锗的相互扩散可以引起硅和锗的合金化，从而形成硅锗。因此，第一退火工艺300也可以被称为锗引入工艺。应当注意，第一退火工艺300可以在形成覆层240的过程中原位进行，或者可以在形成覆层240的过程后异位进行。在前者中，覆层240的形成和第一退火工艺300在同一工艺室中进行而无需破坏真空。在一些实施方式中，第一退火工艺300甚至可以与覆层240的形成交替，并且这样的交替循环将锗逐渐泵入沟道构件2080。在后者中，第一退火工艺300和覆层240的形成可以在同一工艺室中或在两个不同的工艺室中进行。
在一些实施方式中，第一退火工艺300可以包括介于约600和约950之间的第一退火温度。当第一退火温度低于600时，锗的扩散可能不明显。在此，第一退火温度可以是指第一退火工艺300的峰值温度。第一退火工艺300可以获得从覆层240的表面到沟道构件2080中的锗浓度梯度。换句话说，锗浓度在覆层240的表面上最高，并且随着深度而逐渐减小。因为锗浓度通常与蚀刻剂或清洁溶液中的蚀刻速率成反比，所以具有较高锗浓度的覆层240的表面部分更易于蚀刻和清洁。在覆层240由锗形成的一些实例中，在第一退火工艺300之后，覆层240的最外部分可以保持基本无硅。锗浓度梯度可以随着第一退火工艺300的持续时间的长度和退火温度的变化而变化。当退火温度较低或退火持续时间较短时，锗浓度梯度可以较陡，并且允许较少的锗扩散到沟道构件2080中。当退火温度较高或退火持续时间较长时，锗浓度梯度可以较平缓，并且允许较多的锗更深地扩散到沟道构件2080中。如果没有第一退火工艺300引入锗，则覆层240可以基本上(如果不是完全)存在于随后的清洁工艺中。
参考图1、图17、图18、图19和图20，方法100包括框124，其中在沟道构件2080上方和周围形成栅极结构250。在所示的实施例中，栅极结构250沉积在栅极沟槽238中(图12中示出)，并且包括界面层242、栅极介电层244和栅电极层246。在一些实施例中，沟道构件2080以及沉积在其上的覆层240可以经受预清洁工艺，其可以包括使用RCA SC-1(氨、过氧化氢和水)和/或RCA SC-2(盐酸、过氧化氢和水)。如图17所示，预清洁工艺在覆层240外形成界面层242。如上所述，第一退火工艺300可能已将覆层240转化为单硅锗(SiGe)层或内部硅锗(SiGe)层和外部锗(Ge)层。观察到在预清洁工艺期间可以去除纯锗层或富锗硅锗层。预清洁工艺中的氧化剂可以氧化富硅锗锗层以形成界面层242，其因此可以包括氧化锗、氧化硅锗或掺杂锗的氧化硅。由于去除了覆层240中的富锗层，所以界面层242中的硅含量可以大于界面层242中的锗含量。
参考图18，可以使用ALD、物理气相沉积(PVD)、CVD、氧化和/或其他合适的方法在界面层242上方沉积栅极介电层244。栅极介电层244可以由高K介电材料形成。如本文所使用和描述的，高k介电材料包括具有高介电常数的介电材料，例如，其大于热氧化硅的介电常数(
Figure BDA0002946575210000131
)。栅极介电层244可以包括氧化铪。替代地，栅极介电层244可以包括其他高k电介质，诸如氧化钛(TiO2)、氧化锆铪(HfZrO)、氧化钽(Ta2O5)、氧化硅铪(HfSiO4)、氧化锆(ZrO2)、氧化锆硅(ZrSiO2)、氧化镧(La2O3)、氧化铝(Al2O3)、氧化锆(ZrO)、氧化钇(Y2O3)、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、氧化镧铪(HfLaO)、氧化镧硅(LaSiO)、氧化铝硅(AlSiO)、氧化钽铪(HfTaO)、氧化钛铪(HfTiO)、(Ba，Sr)TiO3(BST)、氮化硅(SiN)、氮氧化硅(SiON)、它们的组合或其他合适的材料。如图19所示，框124中的操作可以包括第二退火工艺400。第二退火工艺400可以是快速热退火(RTA)工艺、激光尖峰退火工艺或快速退火工艺，并且可以包括在约700和约1000之间的退火温度。第二退火工艺400用于去除栅极介电层244和界面层242的界面处的缺陷和电荷载流子陷阱。在一些情况下，第二退火工艺400可以在栅极介电层244和界面层242之间的界面处形成硅酸铪。
参考图20，然后使用ALD、PVD、CVD、电子束蒸发或其他合适的方法在栅极介电层244上方沉积栅电极层246。栅电极层246可以包括单层或替代的多层结构，诸如具有增强器件性能的所选功函数的金属层(功函数金属层)、衬层、湿润层、粘合层、金属合金或金属硅化物的各种组合。举例来说，栅电极层246可以包括氮化钛(TiN)、钛铝(TiAl)、氮化钛铝(TiAlN)、氮化钽(TaN)、钽铝(TaAl)、氮化钽铝(TaAlN)、碳化钽铝(TaAlC)、碳氮化钽(TaCN)、铝(Al)、钨(W)、镍(Ni)、钛(Ti)、钌(Ru)、钴(Co)、铂(Pt)、碳化钽(TaC)、氮化钽硅(TaSiN)、铜(Cu)、其他难熔金属或其他合适的金属材料或其组合。此外，在半导体器件200包括n型晶体管和p型晶体管的情况下，可以分别为n型晶体管和p型晶体管形成不同的栅电极层，其可以包括不同的金属层(例如，用于提供不同的n型和p型功函数金属层)。
在框124中，在工件200上方的栅极沟槽248(图14所示)内形成栅极结构250(包括界面层242、栅极介电层244和栅电极层246)，并且沉积为包围每一个沟道构件2080。在这方面，栅极结构250在X-Z平面上包围在每一个沟道构件2080周围。
参考图1和图21，方法100包括框126，其中执行进一步处理。这样的进一步处理可以包括工件200的平坦化、源极/漏极接触件的形成、栅极接触件的形成、背侧源极/漏极接触件的形成以及互连结构的形成。图12示出在诸如CMP工艺的平坦化工艺之后的工件200。可以执行平坦化工艺以去除用于栅极介电层244和栅电极层246两者的多余材料，从而提供栅极结构250的基本平坦的顶面。
为了说明在方法100的操作之后的栅极结构250的构造，图21中的沟道构件2080之一周围的虚线区域被放大并在图22A和图22B的局部截面图中示出。图22A和图22B中的局部截面图不是沿X方向的截面图，而是沿Y方向的截面图。如上所述，在第一退火工艺300之后，可以将覆层240转化或合金化为硅锗层或衬有锗层的硅锗层。同时，可以创建沿着覆层240的深度的锗浓度梯度。框124中的预清洁可以去除转化的覆层240的富锗外部部分并且氧化转化的覆层240的富硅内部部分。取决于锗向沟道构件2080中行进的深度，覆层240的部分可以保留。
首先参考图22A，当不是所有转化的覆层240都被氧化以形成界面层242时，覆层240的部分可以保留在沟道构件2080上。在这些实施例中，转化的覆层240包围在沟道构件2080周围，界面层242设置在剩余的覆层240上，栅极介电层244设置在界面层242上，并且栅电极层246设置在栅极介电层244上。在一些情况下，覆层240和界面层242中的锗浓度可以在约1％和约10％之间，诸如在约3％和约4％之间。应当注意，当覆层240的所述部分的锗浓度大于约10％时，可能被去除。在这些实施例中，覆层240可以包括硅锗，并且界面层242可以包括氧化锗、氧化硅锗或掺杂锗的氧化硅。因为界面层242包括锗，所以界面层242可以被称为含锗氧化物层。
首先参考图22B，当所有转化的覆层240都被氧化以形成界面层242时，基本上覆层240的全部都可以从沟道构件2080去除。在这些实施例中，界面层242包围在沟道构件2080周围，栅极介电层244包围在界面层242周围，并且栅电极层246包围在栅极介电层244周围。在一些情况下，界面层242中的锗浓度可以在约1％和约10％之间，诸如在约3％和约4％之间。应当注意，当覆层240的所述部分的锗浓度大于约10％时，可能在预清洁工艺期间被去除。在这些实施例中，界面层242可以包括氧化硅、氧化锗、氧化硅锗或掺杂锗的氧化硅。因为界面层242包括锗，所以界面层242可以被称为含锗氧化物层。
在图23所示的一些实施例中，覆层240被选择性地实施为p型MBC晶体管，而不被实施为n型MBC晶体管。首先参考图23。图23示出工件200，其包括p型器件区域1000和n型器件区域2000。尽管未明确示出，但是p型器件区域1000中的衬底202可以包括n型阱，并且n型器件区域2000中的衬底202可以包括p型阱。为了使用方法100来执行覆层240的选择性实施，可以在n型器件区域2000中形成掩模层241以在n型器件区域2000中掩蔽沟道构件2080。在一些实施例中，掩模层241可以是光刻胶层或底部抗反射涂层(BARC)。在一些情况下，BARC层可以包括氮氧化硅、氧化硅、聚合物或其组合，并且可以使用CVD或ALD沉积。在n型器件区域2000被掩模层241覆盖的情况下，可以在p型器件区域1000中的衬底202和沟道构件2080上选择性地沉积覆层240。
利用方法100和图23所示的工艺变更，可以在p型器件区域1000中形成p型晶体管260，并且在n型器件区域2000中形成n型晶体管270，如图24所示。p型晶体管260和n型晶体管270都是MBC晶体管，每个都在沟道区域中包括堆叠的沟道构件2080。p型晶体管260包括围绕在每一个沟道构件2080周围的栅极结构250和p型源极/漏极部件232。n型晶体管270包括围绕在每一个沟道构件2080周围的无锗栅极结构252和n型源极/漏极部件2320。如上所述，p型源极/漏极部件232可以包括掺杂有诸如硼(B)的p型掺杂剂的硅锗(SiGe)，并且n型源极/漏极部件2320可以包括掺杂有诸如磷(P)或砷(As)的n型掺杂剂的硅(Si)。为了简洁，省略了p型源极/漏极部件232和n型源极/漏极部件2320的形成。如图22A和图22B所示，栅极结构250可以包括含锗界面层242，甚至可以包括覆层240的剩余部分。由于在其形成工艺中缺少覆层240，所以无锗栅极结构252中不存在锗，并且无锗栅极结构252包括基本上由氧化硅构成的无锗界面层243。实验已经证明，在p型器件区域1000中实施覆层240或形成含锗界面层242可以在约100mV和约250mV之间创建功函数的偏移，这使得p型晶体管260的阈值电压降低。从理论上讲，功函数的偏移源自于含锗界面层242处或周围的偶极子或固定电荷的形成。
尽管不旨在限制，但本发明的一个或多个实施例提供了半导体器件及其形成的许多益处。例如，本公开提供了一种实施例，其包括p型器件区域中的p型MBC晶体管和n型器件区域中的n型MBC晶体管。p型MBC晶体管和n型MBC晶体管两者包括硅沟道构件。为了向p型MBC晶体管和n型MBC晶体管提供期望的阈值电压，在掩蔽n型器件区域的同时，在p型器件区域中的硅沟道构件上方选择性地沉积含锗覆层。覆层中的锗通过退火工艺被引入，并且覆层至少部分地转化为含锗界面层。在没有覆层的情况下，无锗界面层沉积在n型器件区域中。含锗界面层创建偶极子或固定电荷，以降低p型MBC晶体管的阈值电压。
在一个示例性方面中，本公开针对一种半导体结构。半导体结构包括：鳍结构，位于衬底上方；竖直堆叠的硅纳米结构，设置在鳍结构上方；隔离结构，设置在鳍结构周围；含锗界面层，包围在每一个竖直堆叠的硅纳米结构周围；栅极介电层，包围在含锗界面层周围；以及栅电极层，包围在栅极介电层周围。
在一些实施例中，半导体结构可以进一步包括位于含锗界面层和每一个竖直堆叠的硅纳米结构之间的硅锗层。在一些实施例中，含锗界面层包括氧化硅锗、氧化锗或掺杂锗的氧化硅。在一些实施方式中，含锗界面层设置在鳍结构上。在一些情况下，半导体结构可以进一步包括位于含锗界面层和鳍结构之间的硅锗层。在一些情况下，半导体结构可以进一步包括与竖直堆叠的硅纳米结构交错的内部间隔件部件。含锗界面层与内部间隔件部件接触。
在另一示例性方面中，本公开针对一种半导体器件。半导体器件包括p型晶体管和n型晶体管。p型晶体管包括：第一鳍结构，位于衬底上方；第一多个硅纳米结构，设置在第一鳍结构上方；第一界面层，包围在每一个第一多个硅纳米结构周围；栅极介电层，包围在第一界面层周围；以及栅电极层，包围在栅极介电层周围。n型晶体管包括：第二鳍结构，位于衬底上方；第二多个硅纳米结构，设置在第二鳍结构上方；第二界面层，包围在每一个第二多个硅纳米结构周围并与之接触；栅极介电层，包围在第二界面层周围；以及栅电极层，包围在栅极介电层周围。第一界面层的组成不同于第二界面层的组成。
在一些实施例中，第一界面层包括锗，并且第二界面层不含锗。在一些实施例中，半导体器件可以进一步包括位于第一界面层和第一多个硅纳米结构之间的硅锗层。在一些实施方式中，第一界面层设置在第一鳍结构上。在一些情况下，第一多个硅纳米结构基本上由硅构成。在一些实施例中，第一界面层包括氧化硅锗、氧化锗或掺杂锗的氧化硅，并且第二界面层包括氧化硅。在一些实施例中，半导体器件可以进一步包括与第一多个硅纳米结构交错的内部间隔件部件。第一界面层与内部间隔件部件接触。在一些情况下，p型晶体管进一步包括耦合至第一多个硅纳米结构的p型源极/漏极部件。p型源极/漏极部件包括硅锗和p型掺杂剂。n型晶体管进一步包括耦合至第二多个硅纳米结构的n型源极/漏极部件，并且n型源极/漏极部件包括硅和n型掺杂剂。
在又一示例性方面中，本公开针对一种方法。该方法包括：在衬底上方交替堆叠第一外延层和第二外延层以形成半导体堆叠件；图案化半导体堆叠件以形成鳍；从第二外延层去除鳍的第一外延层以形成纳米结构；形成包围在纳米结构周围的含锗覆层；执行预清洁工艺以将至少部分含锗覆层转化为含锗界面层；沉积包围在含锗界面层周围的栅极介电层；以及在栅极介电层上方形成栅电极层。
在一些实施例中，第一外延层基本上由硅锗构成，并且第二外延层基本上由硅构成。在一些实施例中，含锗覆层的形成包括通过化学气相沉积(CVD)、原子层沉积(ALD)或外延在衬底和纳米结构上沉积含锗覆层。在一些实施方式中，该方法可以进一步包括在形成含锗覆层之后并且在预清洁工艺之前，执行第一退火工艺。在一些情况下，预清洁工艺包括使用氢氧化氨、过氧化氢、水或盐酸。在一些实施例中，该方法可以进一步包括在沉积栅极介电层之后并且在形成栅电极层之前，执行第二退火工艺。
在一些实施例中，一种半导体结构，包括：鳍结构，位于衬底上方；竖直堆叠的硅纳米结构，设置在所述鳍结构上方；隔离结构，设置在所述鳍结构周围；含锗界面层，包围在每一个竖直堆叠的硅纳米结构周围；栅极介电层，包围在所述含锗界面层周围；以及栅电极层，包围在所述栅极介电层周围。在一些实施例中，还包括：位于所述含锗界面层和每一个竖直堆叠的硅纳米结构之间的硅锗层。在一些实施例中，含锗界面层包括氧化硅锗、氧化锗或掺杂锗的氧化硅。在一些实施例中，含锗界面层设置在所述鳍结构上。在一些实施例中，还包括：位于所述含锗界面层和所述鳍结构之间的硅锗层。在一些实施例中，还包括：与所述竖直堆叠的硅纳米结构交错的内部间隔件部件，其中，所述含锗界面层与所述内部间隔件部件接触。
在一些实施例中，一种半导体器件，包括：p型晶体管，包括：第一鳍结构，位于衬底上方，第一多个硅纳米结构，设置在所述第一鳍结构上方，第一界面层，包围在每一个第一多个硅纳米结构周围，栅极介电层，包围在所述第一界面层周围，和栅电极层，包围在所述栅极介电层周围；以及n型晶体管，包括：第二鳍结构，位于所述衬底上方，第二多个硅纳米结构，设置在所述第二鳍结构上方，第二界面层，包围在每一个第二多个硅纳米结构周围并与之接触，栅极介电层，包围在所述第二界面层周围，和栅电极层，包围在所述栅极介电层周围，其中，所述第一界面层的组成不同于所述第二界面层的组成。在一些实施例中，第一界面层包括锗，并且所述第二界面层不含锗。在一些实施例中，还包括：位于所述第一界面层和所述第一多个硅纳米结构之间的硅锗层。在一些实施例中，第一界面层设置在所述第一鳍结构上。在一些实施例中，第一多个硅纳米结构基本上由硅构成。在一些实施例中，第一界面层包括氧化硅锗、氧化锗或掺杂锗的氧化硅，其中，所述第二界面层包括氧化硅。在一些实施例中，还包括：与所述第一多个硅纳米结构交错的内部间隔件部件，其中，所述第一界面层与所述内部间隔件部件接触。在一些实施例中，p型晶体管还包括耦合至所述第一多个硅纳米结构的p型源极/漏极部件，其中，所述p型源极/漏极部件包括硅锗和p型掺杂剂，其中，所述n型晶体管还包括耦合至所述第二多个硅纳米结构的n型源极/漏极部件，其中，所述n型源极/漏极部件包括硅和n型掺杂剂。
在一些实施例中，一种方法，包括：在衬底上方交替堆叠第一外延层和第二外延层以形成半导体堆叠件；图案化所述半导体堆叠件以形成鳍；从所述第二外延层去除所述鳍的第一外延层以形成纳米结构；形成包围在所述纳米结构周围的含锗覆层；执行预清洁工艺以将至少部分含锗覆层转化为含锗界面层；沉积包围在所述含锗界面层周围的栅极介电层；以及在所述栅极介电层上方形成栅电极层。在一些实施例中，第一外延层基本上由硅锗构成，并且所述第二外延层基本上由硅构成。在一些实施例中，含锗覆层的形成包括通过化学气相沉积(CVD)、原子层沉积(ALD)或外延在所述衬底和所述纳米结构上沉积所述含锗覆层。在一些实施例中，还包括：在形成所述含锗覆层之后并且在所述预清洁工艺之前，执行第一退火工艺。在一些实施例中，预清洁工艺包括使用氢氧化氨、过氧化氢、水或盐酸。在一些实施例中，还包括：在沉积所述栅极介电层之后并且在形成所述栅电极层之前，执行第二退火工艺。
上面论述了若干实施例的部件，使得本领域技术人员可以更好地理解本发明的各个实施例。本领域普通技术人员应该理解，可以很容易地使用本发明作为基础来设计或更改其他用于达到与本文所介绍实施例相同的目的和/或实现相同优点的处理和结构。本领域普通技术人员也应该意识到，这种等效构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (10)

1.一种半导体结构，包括：
鳍结构，位于衬底上方；
竖直堆叠的硅纳米结构，设置在所述鳍结构上方；
隔离结构，设置在所述鳍结构周围；
含锗界面层，包围在每一个竖直堆叠的硅纳米结构周围；
栅极介电层，包围在所述含锗界面层周围；以及
栅电极层，包围在所述栅极介电层周围。
2.根据权利要求1所述的半导体结构，还包括：
位于所述含锗界面层和每一个竖直堆叠的硅纳米结构之间的硅锗层。
3.根据权利要求1所述的半导体结构，其中，所述含锗界面层包括氧化硅锗、氧化锗或掺杂锗的氧化硅。
4.根据权利要求1所述的半导体结构，其中，所述含锗界面层设置在所述鳍结构上。
5.根据权利要求4所述的半导体结构，还包括：
位于所述含锗界面层和所述鳍结构之间的硅锗层。
6.根据权利要求1所述的半导体结构，还包括：
与所述竖直堆叠的硅纳米结构交错的内部间隔件部件，
其中，所述含锗界面层与所述内部间隔件部件接触。
7.一种半导体器件，包括：
p型晶体管，包括：
第一鳍结构，位于衬底上方，
第一多个硅纳米结构，设置在所述第一鳍结构上方，
第一界面层，包围在每一个第一多个硅纳米结构周围，
栅极介电层，包围在所述第一界面层周围，和
栅电极层，包围在所述栅极介电层周围；以及
n型晶体管，包括：
第二鳍结构，位于所述衬底上方，
第二多个硅纳米结构，设置在所述第二鳍结构上方，
第二界面层，包围在每一个第二多个硅纳米结构周围并与之接触，
栅极介电层，包围在所述第二界面层周围，和
栅电极层，包围在所述栅极介电层周围，
其中，所述第一界面层的组成不同于所述第二界面层的组成。
8.根据权利要求7所述的半导体器件，其中，所述第一界面层包括锗，并且所述第二界面层不含锗。
9.根据权利要求7所述的半导体器件，还包括：
位于所述第一界面层和所述第一多个硅纳米结构之间的硅锗层。
10.一种形成半导体结构的方法，包括：
在衬底上方交替堆叠第一外延层和第二外延层以形成半导体堆叠件；
图案化所述半导体堆叠件以形成鳍；
从所述第二外延层去除所述鳍的第一外延层以形成纳米结构；
形成包围在所述纳米结构周围的含锗覆层；
执行预清洁工艺以将至少部分含锗覆层转化为含锗界面层；
沉积包围在所述含锗界面层周围的栅极介电层；以及
在所述栅极介电层上方形成栅电极层。
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