TWI791912B - 於基材上形成鉬薄膜之方法 - Google Patents

於基材上形成鉬薄膜之方法 Download PDF

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TWI791912B
TWI791912B TW108138017A TW108138017A TWI791912B TW I791912 B TWI791912 B TW I791912B TW 108138017 A TW108138017 A TW 108138017A TW 108138017 A TW108138017 A TW 108138017A TW I791912 B TWI791912 B TW I791912B
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molybdenum
substrate
vapor deposition
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湯瑪士 Ｈ 邦姆
布萊恩 C 漢迪克斯
世輝 陳
羅柏茲 二世 懷特
詹姆斯 沃勘納
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美商恩特葛瑞斯股份有限公司
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Abstract

本發明描述一種於基材上形成含鉬材料之製程，其中在氣相沈積條件下該基材與二氯二氧化鉬(MoO2 Cl2 )蒸氣接觸以將該含鉬材料沈積於該基材上。有利地，穩固製程並不需要利用成核劑預處理該基材。在某些實施例中，該製程例如藉由諸如脈衝CVD或ALD之化學氣相沈積(CVD)技術引起鉬之塊狀沈積。

Description

於基材上形成鉬薄膜之方法
本發明係關於含鉬材料之氣相沈積。特定言之，本發明係關於使用二氯二氧化鉬(molybdenum dioxydichloride，MoO2 Cl2 )作為此類沈積之前驅體。
鉬由於其極高熔點、較低熱膨脹係數、較低電阻率及較高熱導率之特徵而逐漸用於製造半導體裝置中，包括用於擴散阻擋層、電極、光罩、大功率電子基材、低電阻閘極及互連件中。
此類效用激勵實現用於此類應用之鉬薄膜之沈積，其表徵為經沈積薄膜之高保形性及高沈積速率以適應高效大批量製造操作。此轉而明智地有助於研發適用於氣相沈積操作之改良鉬源試劑以及利用此類試劑之經改良製程參數。
五氯化鉬最常用作含鉬材料之化學氣相沈積之鉬源。然而，仍需要實現以更高沈積速率來沈積含鉬材料以適應高效大批量製造操作。
本發明係關於氣相沈積含鉬材料，且更具體言之，關於使用二氯二氧化鉬(MoO2 Cl2 )作為用於此類氣相沈積之源試劑，以及關於採用二氯二氧化鉬(MoO2 Cl2 )作為源試劑之製程及裝置。
在一個態樣中，本發明提供一種於基材上形成含鉬材料之製程，其包含在氣相沈積條件下使基材與二氯二氧化鉬(MoO2 Cl2 )蒸氣接觸以將含鉬材料沈積於基材上。
在各種實施例中，本發明係關於一種於基材上形成含鉬材料之方法，其包含藉由氣相沈積製程利用二氯二氧化鉬(MoO2 Cl2 )前驅體以及諸如氫之還原化合物來沈積鉬和/或氧化鉬，以於基材上產生含鉬材料。
有利地，在本發明之製程中，可在小於約400℃之溫度下沈積鉬，其使得該製程能夠用於製造邏輯裝置。在鉬沈積之前，此類邏輯裝置由於與現有裝置結構之相容性而形成挑戰。
此外，較高鉬沈積速率降低工具時間及處理花費。吾人亦發現該製程依靠曝露於鉬前驅體(MoO2 Cl2 )而產生減少的氮化鈦蝕刻。由於額外TiN呈現較不必需用於補償鉬沈積步驟期間蝕刻的任何錫，因此隨著可減小裝置中之導電所需的橫截面積而需要減少的TiN蝕刻。最後，需要避免TiN蝕刻，此係由於其可能產生非均一裝置效能。在一個實施例中，TiN蝕刻之範圍小於約10Å每分鐘。
因此形成的薄膜具有小於1%氧，或小於0.1%氧，由大於99%鉬組成，且擁有大於95、大於99或接近100%之保形性，如例如藉由截面穿透電子顯微術成像技術所測定，以及在35Å之薄膜厚度下小於或等於20 µΩ·cm之電阻率。
本發明之其他態樣、特徵及實施例將自隨後之說明書及所附權利要求書更加充分明顯。
本發明係關於氣相沈積鉬，且特定言之係關於使用二氯二氧化鉬(MoO2 Cl2 )用於此類沈積，例如在製造需要優異保形性及電氣效能特性之鉬薄膜之半導體裝置中。根據本發明，已在諸如化學氣相沈積(CVD)之氣相沈積製程中發現二氯二氧化鉬(MoO2 Cl2 )提供高度保形特徵之較低電阻率、較高沈積速率薄膜。在一個態樣中，本發明係關於一種於基材上形成含鉬材料之製程，其包含在氣相沈積條件下使基材與二氯二氧化鉬(MoO2 Cl2 )蒸氣接觸以將含鉬材料沈積於基材上。
在本發明之各種實施例中，使用二氯二氧化鉬(MoO2 Cl2 )作為前驅體以於基材上氣相沈積含鉬材料可提供較高程度之保形性(如圖1中所展示之t2 /t1 )，接近100%保形性，如藉由截面穿透電子顯微術成像技術所測定(參見圖1)。有利地，可以比沈積五氯化鉬(MoCl5 )更高之速率繼續沈積二氯二氧化鉬(MoO2 Cl2 )。在3D NAND結構之情況下，MoO2 Cl2 相較於MoOCl4 而需要更高壓力、更大氫氣流動及更低安瓿溫度。另外，儘管氧存在於二氯二氧化鉬(MoO2 Cl2 )之結構中，但因此沈積之含鉬材料可具有較低電阻率及氧含量。
圖2描繪展示三種不同Mo前驅體之薄膜電阻率對比薄膜厚度之比較的曲線。在曲線中，將安瓿加熱至溫度70℃且將薄膜沈積至具有TiN層之矽基材塗層上。
在本發明之某些實施例中，可使用脈衝氣相沈積條件來沈積前驅體。已發現，此可改良沈積之步階式覆蓋率。取決於基材結構及反應器設計，脈衝沈積之適當「脈衝」及「淨化」時間可各自獨立地在1至120秒、1至60秒或1至20秒範圍內。
在各種實施例中，蒸氣條件經選擇以使得經沈積的含鉬材料之電阻率小於100 µΩ· cm、小於50 µΩ· cm、至多20 µΩ· cm、視情況至多15-20 µΩ· cm，且在其他實施例中，低至8 µΩ· cm。
可在350℃至750℃範圍內，或在300℃至600℃範圍內，或在300℃至575℃範圍內之(基材)溫度下沈積含鉬材料。
在各種實施例中，除視情況存在之諸如氫之還原劑以外，氣相沈積條件包含惰性氣氛。在某些實施例中，可在實質上不存在其他金屬蒸氣下沈積二氯二氧化鉬(MoO2 Cl2 )。
本發明之製程可包含使二氯二氧化鉬(MoO2 Cl2 )揮發，以形成二氯二氧化鉬(MoO2 Cl2 )蒸氣用於氣相沈積操作。氣相沈積條件可具有任何適合之類型，且可例如包含諸如氫氣之還原環境(蒸氣)使得含鉬材料在沈積薄膜中包含元素鉬材料。因此沈積之含鉬材料可包含以下、或替代地由以下組成、或基本上由以下組成：元素鉬、或氧化鉬、或其他含鉬材料。取決於還原劑含量，例如氫濃度，可較佳地沈積更大比例之元素鉬對比氧化鉬。
本發明之額外優點為較高鉬沈積速率降低工具時間及處理成本。因而，該製程依靠曝露於鉬前驅體(MoO2 Cl2 )而產生減少的氮化鈦蝕刻。發現在整個所測試的所有基材溫度範圍中，TiN基材之蝕刻小於5Å。
在本發明之一個態樣中，圖3展示隨基材溫度而變化沈積之MoOCl4 及MoO2 Cl2 前驅體之TiN蝕刻速率的比較。如藉由圖3所展示，當相較於MoOCl4 時，MoO2 Cl2 展示TiN之較低蝕刻速率。用於圖3之曲線的沈積條件為T安瓿 = 60℃(安瓿之溫度)，200A TiN基材，氬氣(Ar)流動速率= 50 sccm，用於MoO2 Cl2 之H2 流動速率= 4000 sccm且用於MoOCl4 之H2 流動速率= 2000 sccm。
在本發明之其他實施例中，用於所描述製程中之基材可具有任何適合之類型，且可例如包含半導體裝置基材，例如矽基材、二氧化矽基材或其他矽類基材。在各種實施例中，基材可包含一或多種金屬或介電基材，例如TiN、Mo、MoC、SiO2 、W、SiN、WCN、Al2 O3 、AlN、ZrO2 、HfO2 、SiO2 、氧化鑭(La2 O3 )、氮化鉭(TaN)、氧化釕(RuO2 )、氧化銥(IrO2 )、氧化鈮(Nb2 O3 )及氧化釔(Y2 O3 )。
在某些實施例中，例如在諸如二氧化矽之氧化物基材或替代地矽或多晶矽基材之情況下，基材可經處理或製造以於其上包括勢壘層，例如氮化鈦用於後續沈積材料。
在一個實施例中，沈積於基材表面上之含鉬層可例如藉由脈衝化學氣相沈積(CVD)或原子層沈積(ALD)或其他氣相沈積技術，無需預先形成晶核層且因此直接利用二氯二氧化鉬(MoO2 Cl2 )蒸氣來形成。相應二氯二氧化鉬(MoO2 Cl2 )蒸氣接觸步驟可交替且重複地進行所需的多次循環以形成鉬薄膜之需要厚度。在各種實施例中，使基材(例如，氮化鈦)層與二氯二氧化鉬(MoO2 Cl2 )蒸氣接觸係在低至350℃之溫度下進行，且在其他實施例中，在300℃至750℃範圍內的溫度下進行，如本文對於(MoO2 Cl2 )氣相沈積所定義。
圖4展示隨用於自MoO2 Cl2 中脈衝CVD沈積Mo之基材溫度而變化量測的沈積Mo薄膜厚度及薄膜電阻率之曲線。圖4中使用的沈積條件為在80T下，Ar流動速率=50 sccm及H2 流動速率=4000 sccm的100次脈衝循環(1s啟用/59s斷開)。
另外，圖6描繪展示用於比較自MoO2 Cl2 中CVD及脈衝沈積Mo兩者之Mo薄膜電阻率對比基材溫度之曲線。如藉由薄膜電阻率證明，在用於CVD之低於Tsub = 570℃下，Mo薄膜質量降低，而在Tsub =約380℃下，脈衝CVD製程獲得良好薄膜。參看圖6，所使用沈積條件為T安瓿 = 60℃，200A TiN厚度，壓力= 80T，Ar流動速率= 50 sccm，H2 流動速率= 4000 sccm，前驅體之脈衝沈積序列啟用1s，斷開59秒。應注意，在低溫下，Mo薄膜厚度降低。
另外，圖7提供展示前驅體引入脈衝、H2 流及壓力之用於自MoO2 Cl2 中Mo沈積的脈衝CVD方法及定時序列的示意圖。當前驅體脈衝至反應器腔室中時，注意到壓力尖峰＞60T基礎壓力。
利用二氯二氧化鉬(MoO2 Cl2 )蒸氣，可將含鉬材料直接沈積至基材上，以形成元素鉬、或氧化鉬、或其他含鉬化合物或組合物之塊狀沈積物。H2 之濃度為形成鉬金屬或氧化物之關鍵，如需要大於四莫耳當量或過量H2 用於金屬形成。小於四(4)莫耳當量之H2 將導致形成不同鉬氧化物量，且因此將需要進一步曝露於H2 以減小因此形成的氧化鉬。
圖5描繪表示隨用於兩個反應器壓力(60及80T)之H2 流動速率而變化的自MoO2 Cl2 中沈積的薄膜的量測的薄膜電阻率及薄膜組合物之曲線，如藉由x射線繞射驗證。如藉由圖5所展示，形成MoOx及Mo(金屬)很大程度上依賴於H2 流動速率。用於圖5之沈積條件為T安瓿 = 60℃，40A TiN厚度，Ar流動速率= 50 sccm，Tsub = 656℃保持10分鐘。
在各種實施例中，在300℃至750℃範圍內或如上文對於(MoO2 Cl2 )氣相沈積所定義之另一範圍內的溫度下，將含鉬材料沈積於表面上。可進行製程使得氣相沈積條件於基材上產生元素鉬，如含鉬材料之沈積。氣相沈積條件可具有任何適合之特徵，且可例如包含存在氫或其他還原氣體，以於基材上形成元素鉬之塊狀層。
更大體而言，根據本發明之於基材上形成含鉬材料之廣義方法可包含氣相沈積條件，該等氣相沈積條件包含存在氫或其他還原氣體。在存在或不存在氫之情況下，可將含鉬材料沈積於勢壘層或表面上。舉例而言，勢壘層可由氮化鈦構成，且在存在氫的情況下，氮化鈦層可與二氯二氧化鉬(MoO2 Cl2 )蒸氣接觸。
將瞭解，可以諸多替代方式且在多種製程條件下進行本發明之方法。本發明之製程可例如以於基材上製得半導體裝置之製程形式進行。半導體裝置可具有任何適合之類型，且可例如包含DRAM裝置、3-D NAND裝置、或其他裝置或裝置積體結構。在各種實施例中，基材可包含其中沈積含鉬材料之通孔。舉例而言，裝置可具有在2:1至40:1範圍內之深度比橫向尺寸之縱橫比(L/W) (參見圖1)。
根據本發明之用於沈積含鉬材料之製程化學反應可包括藉由反應2MoO2 Cl2 +6H2 →2Mo+4HCl+4H2 O來沈積元素鉬、Mo(0)。中間物反應可存在且為此項技術中所熟知。
根據本發明方法沈積之含鉬材料可由以下表徵：任何適合的評估度量值及參數，諸如含鉬材料之沈積速率、經沈積含鉬材料之薄膜電阻率、經沈積含鉬材料之薄膜形態、經沈積含鉬材料之薄膜應力、材料之步階式覆蓋率以及適合的製程條件之製程窗或製程包封。可應用任何適合的評估度量值及參數來表徵經沈積材料且使經沈積材料與特定製程條件相關，以使得能夠大批量生產對應半導體產品。有利地，本發明之製程能夠將高純度鉬之薄膜沈積至半導體裝置上。因此，在另一態樣中，本發明提供一種具有鉬薄膜沈積於其上之半導體裝置，其中該薄膜包含大於99%之鉬。
在某些實施例中，本發明係關於一種於基材上形成含鉬材料之方法，其包含藉由化學氣相沈積(CVD)製程利用二氯二氧化鉬(MoO2 Cl2 )前驅體將鉬沈積在基材表面上，以於該基材上產生含鉬材料。
可如本文中不同地描述以任何適合方式進行此類製程。在特定實施例中，此類方法可藉由包含化學氣相沈積，例如脈衝化學氣相沈積之氣相沈積製程來進行。可進行該方法使得所得含鉬材料實質上由元素鉬構成，且在各種實施例中，鉬可在存在氫或其他適合之還原氣體的情況下沈積於基材表面上。在本發明之其他實施例中，MoO2 Cl2 及還原氣體可經依序脈衝以在脈衝時沈積鉬薄膜，其中脈衝序列針對薄膜保形性及薄膜電阻率進行優化。可在製造半導體裝置產物，諸如DRAM裝置或3-D NAND及邏輯裝置中進行該方法。
大體而言，用於於基材上形成含鉬材料之本發明之方法可進行以實現以高水準步階式覆蓋率，例如75%至100%之步階式覆蓋率沈積含鉬材料。
形成於基材上之含鉬薄膜展現良好黏附特性。在一個實施例中，進行沈積而無需預處理二氧化矽基材且所得鉬薄膜展現＞95%之黏附性，藉由用於利用帶測試量測黏附性之ASTM D 3359-02-標準測試方法。
本發明可進一步藉由其較佳實施例之以下實例說明，但應理解，除非另外具體指示，否則僅出於說明之目的包括此等實例且不意欲限制本發明之範疇。
實驗部分
通用程序： 可藉由以下製程步驟序列於在二氧化矽基底層上包含氮化鈦勢壘層之基材上製造半導體裝置。
步驟1：沖洗沈積腔室；
步驟2：在存在氫(H2 )或氬氣(Ar)或惰性氣體的情況下，例如在約500℃之溫度下，使基材之勢壘層(TiN層)與二氯二氧化鉬(MoO2 Cl2 )蒸氣之脈衝接觸；
步驟3；系統在H2 或惰性氣體(例如，Ar)下經淨化以允許MoO2 Cl2 前驅體與H2 共反應物及基材之完全反應。
步驟4：重複步驟1至3 (視情況)以形成所需特徵之鉬薄膜層。
實例1 以下範圍中之製程參數； 1)     在1標準立方公分/分鐘(sccm)至1000 sccm範圍內之前驅體流動。 2)     在1至10000 sccm範圍內之惰性前驅體載氣流動 3)     在25 sccm至25000 sccm範圍內之H2 共反應物流動 4)     在0.1T至250T範圍內之壓力 5)     300至1000℃範圍內之基材溫度 6)     脈衝CVD循環時間包括a)前驅體脈衝「啟用」時間0.1秒至120秒，b)前驅體脈衝「斷開」時間1秒至120秒 7)     沈積循環1至10000次循環
用於Al2 O3 基材之實例1 在400℃至700℃之基材溫度下，20至200次沈積循環之1秒「啟用」及39秒「斷開」，以4000 sccm (4 lpm) H2 流動速率，80T之腔室壓力之脈衝CVD Mo沈積；Mo金屬沈積速率為0.1至5埃/循環以及電阻率為10至33 µΩ-cm。主要量測2-3埃之Al2 O3 蝕刻，此係部分地由於在Mo頂部層中失去XRF訊號且最不可能由於Al2 O3 之實際蝕刻。
用於SiO2 基材之實例2 在450℃至700℃之基材溫度下，20至200次沈積循環之1秒「啟用」及39秒「斷開」，以4 lpm H2 流動速率，80T之腔室壓力之脈衝CVD Mo沈積；Mo金屬沈積速率為0.4至6埃/循環以及電阻率為10至70 µΩ-cm。未量測SiO2 蝕刻速率。
用於TiN基材之實例3 在360℃至700℃之基材溫度下，25至200次沈積循環之1秒「啟用」及39秒「斷開」，以4 lpm H2 流動速率，80T之腔室壓力之脈衝CVD Mo沈積；Mo金屬沈積速率為0.2至2.8埃/循環以及電阻率為12至1200 µΩ-cm。量測到TiN蝕刻為0至2.3埃。
圖1為展示藉由所揭示之方法之微電子裝置上之鉬(Mo)薄膜形成之縱橫比及保形性的薄膜圖示。
圖2為各種鉬前驅體之薄膜電阻率對比薄膜厚度之比較。
圖3為於200Å D-TiN試片上之鉬化學氣相沈積的氮化鈦(TiN)蝕刻速率對比基材溫度之曲線。
圖4描繪隨用於脈衝CVD Mo沈積之基材溫度而變化的Mo厚度及電阻率。
圖5為MoOx 及Mo金屬對比氫(H2 )流動速率及腔室壓力之曲線。此圖式說明H2 流動速率對於薄膜之屬性之重要性及影響：元素鉬金屬對比氧化鉬。
圖6為以µΩ· cm為單位之Mo電阻率對比基材溫度之曲線。
圖7為脈衝化學氣相沈積製程之圖示。壓力由自動節流閥控制。安瓿為對於腔室脈衝「啟用」持續1秒，隨後在該循環之剩餘59秒期間加壓。當安瓿對該腔室為脈衝開啟時，腔室中之壓力劇增至高於壓力設定點之更高壓力值。
圖8為說明使用H2 共反應物流動速率為3000 sccm之經30Å TiN塗佈基材上之利用MoO2 Cl2 的Mo沈積薄膜之截面薄膜之掃描電子顯微照片(SEM)。

Claims (9)

  1. 一種於基材表面上形成含鉬材料之製程，其包含在氣相沈積條件下使該基材之該表面與二氯二氧化鉬(MoO2Cl2)蒸氣接觸以將該含鉬材料沈積於該基材上，其中該基材選自氮化鈦(TiN)、氮化鉭(TaN)、氮化鋁(AlN)、氧化鋁(Al2O3)、氧化鋯(ZrO2)、氧化鉿(HfO2)、二氧化矽(SiO2)、氮化矽(SiN)、氧化鑭(La2O3)、氧化釕(RuO2)、氧化銥(IrO2)、氧化鈮(Nb2O5)及氧化釔(Y2O3)，其中該等氣相沈積條件經選擇以使得該沈積含鉬材料具有小於約50μΩ．cm之電阻率，及其中該基材之該表面與二氯二氧化鉬(MoO2Cl2)蒸氣之該接觸係在約350℃到約750℃之溫度下進行。
  2. 如請求項1之製程，其中該基材為氮化鈦。
  3. 如請求項1之製程，其中該基材為氧化鋁。
  4. 如請求項1之製程，其中該基材為二氧化矽。
  5. 如請求項1之製程，其中該等氣相沈積條件經選擇以使得該沈積含鉬材料具有小於約20μΩ．cm之電阻率。
  6. 如請求項1之製程，其中該等氣相沈積條件進一步包含H2。
  7. 如請求項1之製程，其中該等氣相沈積條件為脈衝化學氣相沈積條件。
  8. 如請求項1之製程，其中該含鉬材料以75%至100%之步階式覆蓋率沈積於該基材之該表面上。
  9. 一種半導體裝置，其具有沈積於其上之鉬薄膜，其中當在厚度為35Å之薄膜上量測時，該薄膜包含大於99%鉬、小於1%氧、大於99%之保形性及小於20μΩ．cm之電阻率。
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