CN112889132A - 用于在衬底上形成钼薄膜的方法 - Google Patents

用于在衬底上形成钼薄膜的方法 Download PDF

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CN112889132A
CN112889132A CN201980069107.2A CN201980069107A CN112889132A CN 112889132 A CN112889132 A CN 112889132A CN 201980069107 A CN201980069107 A CN 201980069107A CN 112889132 A CN112889132 A CN 112889132A
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molybdenum
substrate
vapor deposition
containing material
oxide
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T·H·鲍姆
B·C·亨德里克斯
P·S·H·陈
R·小赖特
J·韦肯纳
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Entegris Inc
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Abstract

一种在衬底上形成含钼材料的工艺，其中在气相沉积条件下使所述衬底与二氯二氧化钼(MoO2Cl2)蒸气接触以将所述含钼材料沉积于所述衬底上。有利地，稳健工艺并不需要利用成核剂预处理所述衬底。在某些实施例中，所述工艺例如通过例如脉冲化学气相沉积CVD或ALD等的CVD技术引起钼的本体沉积。

Description

用于在衬底上形成钼薄膜的方法
技术领域
本发明涉及含钼材料的气相沉积。确切来说，本发明涉及二氯二氧化钼(MoO2Cl2)作为前体用于此类沉积的用途。
背景技术
钼由于其极高熔点、较低热膨胀系数、较低电阻率和较高热导率的特征而逐渐用于制造半导体装置中，包括用于扩散阻挡层、电极、光罩、大功率电子衬底、低电阻栅极和互连件中。
此类效用已激励人们努力实现用于此类应用的钼薄膜的沉积，其表征为沉积薄膜的高保形性和高沉积速率以适应有效的大批量制造操作。此转而为研发适用于气相沉积操作的改进的钼源试剂以及利用此类试剂的改进非工艺参数做出努力。
五氯化钼最常用作含钼材料的化学气相沉积的钼源。然而，仍需要实现以更高沉积速率来沉积含钼材料以适应有效的大批量制造操作。
发明内容
本发明涉及含钼材料的气相沉积，且更确切来说，涉及二氯二氧化钼(MoO2Cl2)作为源试剂用于此类气相沉积的用途，以及涉及采用二氯二氧化钼(MoO2Cl2)作为源试剂的工艺和装置。
在一个方面中，本发明提供一种在衬底上形成含钼材料的工艺，其包含在气相沉积条件下使衬底与二氯二氧化钼(MoO2Cl2)蒸气接触以将含钼材料沉积于衬底上。
在各种实施例中，本发明涉及一种在衬底上形成含钼材料的方法，其包含通过气相沉积工艺利用二氯二氧化钼(MoO2Cl2)前体以及例如氢的还原化合物来沉积钼和/或氧化钼，以在衬底上产生含钼材料。
有利地，在本发明的工艺中，可在小于约400℃的温度下沉积钼，其使得所述工艺能够用于制造逻辑装置。此类逻辑装置由于在钼沉积之前与现有装置结构的兼容性而具有挑战。
此外，较高钼沉积速率降低工具时间和加工成本。我们还发现，由于暴露于钼前体(MoO2Cl2)，所述工艺引起氮化钛蚀刻减少。减少的TiN蚀刻是所需的，因为装置中导电所需的横截面积可由于额外TiN呈现不太需要补偿在钼沉积步骤期间蚀刻的任何锡而减少。最后，需要避免TiN蚀刻，这是由于其可能产生非均一装置性能。在一个实施例中，TiN蚀刻的程度小于约
Figure BDA0003028181280000021
因此形成的薄膜具有小于1％氧，或小于0.1％氧，由大于99％钼组成，且拥有大于95％、大于99％或接近100％的保形性，如例如通过截面透射电子显微术成像技术所测定，以及在
Figure BDA0003028181280000022
的薄膜厚度下小于或等于20μΩ·cm的电阻率。
本发明的其它方面、特征和实施例将从随后的说明书和所附权利要求书更加充分明显。
附图说明
图1为展示通过所公开的方法形成于微电子装置上的钼(Mo)薄膜的纵横比和保形性的薄膜图示。
图2为各种钼前体的薄膜电阻率相比于薄膜厚度的比较。
图3为在
Figure BDA0003028181280000024
D-TiN试片上进行钼化学气相沉积的氮化钛(TiN)蚀刻速率相比于衬底温度的曲线图。
图4描绘随用于脉冲CVD Mo沉积的衬底温度而变化的Mo厚度和电阻率。
图5为MoOx和Mo金属相比于氢(H2)流动速率和腔室压力的曲线图。此图式说明H2流动速率对于薄膜的属性(元素钼金属相比于氧化钼)的重要性和影响。
图6为以μΩ·cm为单位的Mo电阻率相比于衬底温度的曲线图。
图7为脉冲化学气相沉积工艺的图示。压力由自动节流阀控制。安瓿向腔室脉冲“启用(on)”1秒，随后在循环的剩余59秒期间加压。当安瓿向所述腔室脉冲开启时，腔室中的压力剧增到比压力设定点的更高的压力值。
图8为说明使用H2共反应物流动速率为3000sccm的经
Figure BDA0003028181280000023
TiN涂布的衬底上的利用MoO2Cl2的Mo沉积薄膜的截面薄膜的扫描电子显微图(SEM)。
具体实施方式
本发明涉及气相沉积钼，且确切来说涉及二氯二氧化钼(MoO2Cl2)用于此类沉积，例如在制造需要优异保形性和电气性能特性的钼薄膜的半导体装置中的用途。根据本发明，已在例如化学气相沉积(CVD)的气相沉积工艺中发现二氯二氧化钼(MoO2Cl2)提供具有高度保形特征的较低电阻率、较高沉积速率薄膜。在一个方面中，本发明涉及一种在衬底上形成含钼材料的工艺，其包含在气相沉积条件下使衬底与二氯二氧化钼(MoO2Cl2)蒸气接触以将含钼材料沉积于衬底上。
在本发明的各种实施例中，使用二氯二氧化钼(MoO2Cl2)作为前体以在衬底上气相沉积含钼材料可提供较高程度的保形性(如图1中所展示的t2/t1)，接近100％保形性，如通过截面透射电子显微术成像技术所测定(参见图1)。有利地，可以比沉积五氯化钼(MoCl5)更高的速率继续沉积二氯二氧化钼(MoO2Cl2)。在3D NAND结构的情况下，MoO2Cl2相较于MoOCl4需要更高的压力、更大的氢气流动和更低的安瓿温度。另外，尽管氧存在于二氯二氧化钼(MoO2Cl2)的结构中，但因此沉积的含钼材料可具有较低电阻率和氧含量。
图2描绘展示三种不同Mo前体的薄膜电阻率相比于薄膜厚度的比较的曲线图。在曲线图中，将安瓿加热到70℃的温度且将薄膜沉积到具有TiN层的硅衬底涂层上。
在本发明的某些实施例中，可使用脉冲气相沉积条件来沉积前体。已发现，此可改进沉积的步阶式覆盖率。取决于衬底结构和反应器设计，脉冲沉积的适当“脉冲”和“净化”时间可各自独立地在1到120秒、1到60秒或1到20秒范围内。
在各种实施例中，选择蒸气条件以使得沉积的含钼材料的电阻率小于100μΩ·cm、小于50μΩ·cm、至多20μΩ·cm、任选地至多15-20μΩ·cm，且在其它实施例中，低至8μΩ·cm。
可在350℃到750℃的范围内，或在300℃到600℃的范围内，或在300℃到575℃的范围内的(衬底)温度下沉积含钼材料。
在各种实施例中，除任选的存在例如氢的还原剂以外，气相沉积条件包含惰性气氛。在某些实施例中，可在大体上不存在其它金属蒸气的情况下沉积二氯二氧化钼(MoO2Cl2)。
本发明的工艺可包含使二氯二氧化钼(MoO2Cl2)挥发，以形成二氯二氧化钼(MoO2Cl2)蒸气以用于气相沉积操作。气相沉积条件可具有任何合适的类型，且可例如包含例如氢气等的还原环境(蒸气)以使得含钼材料在沉积薄膜中包含元素钼材料。因此沉积的含钼材料可包含以下、或替代地由以下组成、或基本上由以下组成：元素钼、或氧化钼、或其它含钼材料。取决于还原剂含量(例如，氢浓度)，相比于氧化钼，有可能优选地沉积更大比例的元素钼。
本发明的额外优点为较高钼沉积速率降低工具时间和加工成本。因而，所述工艺由于暴露于钼前体(MoO2Cl2)而引起氮化钛蚀刻减少。发现在整个所测试的所有衬底温度范围中，TiN衬底的蚀刻小于
Figure BDA0003028181280000041
在本发明的一个方面中，图3展示随衬底温度而变化的沉积的MoOCl4和MoO2Cl2前体的TiN蚀刻速率的比较。如通过图3所展示，当相较于MoOCl4时，MoO2Cl2展示较低的TiN蚀刻速率。用于图3的曲线图中的沉积条件为T安瓿＝60℃(安瓿的温度)，200A TiN衬底，氩气(Ar)流动速率＝50sccm，用于MoO2Cl2的H2流动速率＝4000sccm且用于MoOCl4的H2流动速率＝2000sccm。
在本发明的其它实施例中，用于所描述工艺中的衬底可具有任何合适的类型，且可例如包含半导体装置衬底，例如硅衬底、二氧化硅衬底或其它硅类衬底。在各种实施例中，衬底可包含一或多种金属或电介质衬底，例如TiN、Mo、MoC、SiO2、W、SiN、WCN、Al2O3、AlN、ZrO2、HfO2、SiO2、氧化镧(La2O3)、氮化钽(TaN)、氧化钌(RuO2)、氧化铱(IrO2)、氧化铌(Nb2O3)和氧化钇(Y2O3)。
在某些实施例中，例如在例如二氧化硅的氧化物衬底或替代地硅或多晶硅衬底的情况下，衬底可经加工或制造以于其上包括势垒层(例如氮化钛)以用于后续沉积材料。
在一个实施例中，沉积于衬底表面上的含钼层可例如通过脉冲化学气相沉积(CVD)或原子层沉积(ALD)或其它气相沉积技术，无需预先形成晶核层且因此直接利用二氯二氧化钼(MoO2Cl2)蒸气来形成。相应二氯二氧化钼(MoO2Cl2)蒸气接触步骤可交替且重复地进行所需的多次循环以形成所需厚度的钼薄膜。在各种实施例中，使衬底(例如，氮化钛)层与二氯二氧化钼(MoO2Cl2)蒸气接触在低至350℃的温度下进行，且在其它实施例中，在300℃到750℃范围内的温度下进行，如本文针对(MoO2Cl2)气相沉积所定义。
图4展示随用于从MoO2Cl2中脉冲CVD沉积Mo的衬底温度而变化所测量的沉积Mo薄膜厚度和薄膜电阻率的曲线图。图4中使用的沉积条件为在80T下，在流动速率＝50sccm和H2流动速率＝4000sccm下的100次脉冲循环(1s启用/59s断开)。
另外，图6描绘展示用于比较从MoO2Cl2中CVD和脉冲沉积Mo的Mo薄膜电阻率相比于衬底温度的曲线图。如通过薄膜电阻率所证明，在用于CVD的低于Tsub＝570℃下，Mo薄膜质量降低，而在Tsub＝约380℃下，脉冲CVD工艺获得良好薄膜。参看图6，所使用沉积条件为T安瓿＝60℃，200A TiN厚度，压力＝80T，Ar流动速率＝50sccm，H2流动速率＝4000sccm，前体的脉冲沉积序列启用1s，断开59秒。应注意，在低温下，Mo薄膜厚度降低。
另外，图7提供展示前体引入脉冲、H2流和压力的用于从MoO2Cl2中Mo沉积的脉冲CVD方法和定时序列的示意图。当前体脉冲到反应器腔室中时，注意到压力尖峰>60T基础压力。
利用二氯二氧化钼(MoO2Cl2)蒸气，可将含钼材料直接沉积到衬底上，以形成元素钼、或氧化钼、或其它含钼化合物或组合物的本体沉积物。H2的浓度为形成钼金属或氧化物的关键，如需要大于四摩尔当量或过量H2以用于金属形成。小于四(4)摩尔当量的H2将使得形成不同量的钼氧化物，且因此将需要进一步暴露于H2以便减少因此形成的氧化钼。
图5描绘表示随用于两个反应器压力(60和80T)的H2流动速率而变化的从MoO2Cl2中沉积的薄膜的测量的薄膜电阻率和薄膜组合物的曲线图，如通过x射线绕射所验证。如通过图5所展示，形成MoOx和Mo(金属)很大程度上取决于H2流动速率。用于图5的沉积条件为T安瓿＝60℃，40A TiN厚度，Ar流动速率＝50sccm，Tsub＝656℃，持续10分钟。
在各种实施例中，在300℃到750℃范围内或如上文对于(MoO2Cl2)气相沉积所定义的另一范围内的温度下，将含钼材料沉积于表面上。可进行工艺以使得气相沉积条件在衬底上产生元素钼作为含钼材料的沉积。气相沉积条件可具有任何合适的特征，且可例如包含存在氢或其它还原气体，以在衬底上形成元素钼的本体层。
更一般来说，根据本发明的在衬底上形成含钼材料的广义方法可包含气相沉积条件，所述气相沉积条件包含存在氢或其它还原气体。在存在或不存在氢的情况下，可将含钼材料沉积于势垒层或表面上。举例来说，势垒层可由氮化钛构成，且在存在氢的情况下，氮化钛层可与二氯二氧化钼(MoO2Cl2)蒸气接触。
将了解，可以诸多替代方式且在多种工艺条件下进行本发明的方法。本发明的工艺可例如以在衬底上制得半导体装置的工艺形式进行。半导体装置可具有任何合适的类型，且可例如包含DRAM装置、3-D NAND装置、或其它装置或装置集成结构。在各种实施例中，衬底可包含其中沉积含钼材料的通孔。举例来说，装置可具有在2:1到40:1范围内的深度比横向尺寸的纵横比(L/W)(参见图1)。
根据本发明的用于沉积含钼材料的工艺化学反应可包括通过反应2MoO2Cl2+6H2→2Mo+4HCl+4H2O来沉积元素钼、Mo(0)。中间物反应可存在且为所属领域中所熟知。根据本发明方法沉积的含钼材料可由以下表征：任何合适的评估度量值和参数，例如含钼材料的沉积速率、沉积的含钼材料的薄膜电阻率、沉积的含钼材料的薄膜形态、沉积的含钼材料的薄膜应力、材料的步阶式覆盖率以及适合的工艺条件的工艺窗或工艺包封。可应用任何合适的评估度量值和参数来表征沉积材料且使沉积材料与特定工艺条件相关，以使得能够大批量生产对应半导体产品。有利地，本发明的工艺能够将高纯度钼的薄膜沉积到半导体装置上。因此，在另一方面中，本发明提供一种上面沉积有钼薄膜的半导体装置，其中所述薄膜包含大于99％的钼。
在某些实施例中，本发明涉及一种在衬底上形成含钼材料的方法，其包含通过化学气相沉积(CVD)工艺利用二氯二氧化钼(MoO2Cl2)前体将钼沉积在衬底表面上，以在所述衬底上产生含钼材料。
可如本文中不同地描述以任何合适方式进行此类工艺。在特定实施例中，此类方法可通过包含化学气相沉积，例如脉冲化学气相沉积的气相沉积工艺来进行。可进行所述方法以使得所得含钼材料大体上由元素钼构成，且在各种实施例中，钼可在存在氢或其它适合的还原气体的情况下沉积在衬底表面上。在本发明的其它实施例中，MoO2Cl2和还原气体可经依序脉冲以在脉冲时沉积钼薄膜，其中脉冲序列针对薄膜保形性和薄膜电阻率进行优化。可在制造半导体装置产物(例如DRAM装置或3-D NAND和逻辑装置)时进行所述方法。
一般来说，可进行用于在衬底上形成含钼材料的本发明的方法以实现以高水平的步阶式覆盖率，例如75％到100％的步阶式覆盖率沉积含钼材料。
形成于衬底上的含钼薄膜展现良好粘附特性。在一个实施例中，进行沉积而无需预处理二氧化硅衬底且通过ASTM D 3359-02-用于利用带测试测量粘附性的标准测试方法，所得钼薄膜展现>95％的粘附性。
本发明可进一步通过其优选实施例的以下实例说明，但应理解，除非另外具体指示，否则仅出于说明的目的包括这些实例且不打算限制本发明的范围。
实验部分
通用程序：
可通过以下工艺步骤序列于在二氧化硅基底层上包含氮化钛势垒层的衬底上制造半导体装置。
步骤1：净化沉积腔室；
步骤2：在存在氢(H2)或氩气(Ar)或惰性气体的情况下，例如在约500℃的温度下，使衬底的势垒层(TiN层)与二氯二氧化钼(MoO2Cl2)蒸气的脉冲接触；
步骤3；在H2或惰性气体(例如，Ar)下净化系统以允许MoO2Cl2前体与H2共反应物和衬底的完全反应。
步骤4：重复步骤1到3(任选的)以形成具有所需特征的钼薄膜层。
实例1
以下范围中的工艺参数；
1)在1标准立方厘米/分钟(sccm)到1000sccm范围内的前体流动。
2)在1到10000sccm范围内的惰性前体载气流动
3)在25sccm到25000sccm范围内的H2共反应物流动
4)在0.1T到250T范围内的压力
5)300到1000℃范围内的衬底温度
6)脉冲CVD循环时间包括a)0.1秒到120秒的前体脉冲“启用”时间，b)1秒到120秒的前体脉冲“断开”时间
7)1到10000次循环的沉积循环
用于Al2O3衬底的实例1
在400℃到700℃的衬底温度下，持续1秒“启用”和39秒“断开”的20到200次沉积循环，在4000sccm(4lpm)H2流动速率，80T的腔室压力下的脉冲CVD Mo沉积；Mo金属沉积速率为0.1到5埃/循环，电阻率为10到33μΩ-cm。主要测量到2-3埃的Al2O3蚀刻，这部分归因于在Mo顶部层中XRF信号的损失且最可能不归因于Al2O3的实际蚀刻。
用于SiO2衬底的实例2
在450℃到700℃的衬底温度下，持续1秒“启用”和39秒“断开”的20到200次沉积循环，在4lpm H2流动速率，80T的腔室压力下的脉冲CVD Mo沉积；Mo金属沉积速率为0.4到6埃/循环，电阻率为10到70μΩ-cm。未测量到SiO2蚀刻速率。
用于TiN衬底的实例3
在360℃到700℃的衬底温度下1秒“启用”和39秒“断开”的25到200次沉积循环，在4lpm H2流动速率，80T下的腔室压力的脉冲CVD Mo沉积；Mo金属沉积速率为0.2到2.8埃/循环，电阻率为12到1200μΩ-cm。测量到0到2.3埃的TiN蚀刻。

Claims (20)

1.一种在衬底上形成含钼材料的工艺，其包含在气相沉积条件下使所述衬底与二氯二氧化钼(MoO2Cl2)蒸气接触以将所述含钼材料沉积于所述衬底上。
2.根据权利要求1所述的工艺，其中所述衬底选自氮化钛(TiN)、氮化钽(TaN)、氮化铝(AlN)、氧化铝(Al2O3)、氧化锆(ZrO2)、氧化铪(HfO2)、二氧化硅(SiO2)、氮化硅(SiN)、氧化镧(La2O3)、氧化钌(RuO2)、氧化铱(IrO2)、氧化铌(Nb2O5)和氧化钇(Y2O3)。
3.根据权利要求2所述的工艺，其中所述衬底是氮化钛。
4.根据权利要求2所述的工艺，其中所述衬底是氧化铝。
5.根据权利要求2所述的工艺，其中所述衬底是二氧化硅。
6.根据权利要求2所述的工艺，其中所述衬底是氮化硅。
7.根据权利要求3所述的工艺，其中所述氮化钛衬底与二氯二氧化钼蒸气的所述接触在约350℃到约750℃的温度下进行。
8.根据权利要求4所述的工艺，其中所述氧化铝衬底与二氯二氧化钼蒸气的所述接触在约350℃到约750℃的温度下进行。
9.根据权利要求5所述的工艺，其中所述二氧化硅衬底与二氯二氧化钼蒸气的所述接触在约350℃到约750℃的温度下进行。
10.根据权利要求1所述的工艺，其中选择所述气相沉积条件以使得所述沉积的含钼材料具有小于约50μΩ·cm的电阻率。
11.根据权利要求1所述的工艺，其中选择所述气相沉积条件以使得所述沉积的含钼材料具有小于约20μΩ·cm的电阻率。
12.根据权利要求1所述的工艺，其中所述气相沉积条件进一步包含H2。
13.根据权利要求12所述的工艺，其中所述气相沉积条件进一步包含浓度大于或等于4摩尔当量的H2。
14.根据权利要求1所述的工艺，其中所述气相沉积条件为脉冲化学气相沉积条件。
15.根据权利要求1所述的工艺，其中所述含钼材料以75％到100％的步阶式覆盖率沉积于所述衬底上。
16.根据权利要求3所述的工艺，其中氮化钛蚀刻为小于约10埃/分钟。
17.根据权利要求4所述的工艺，其中所述沉积在无需预处理所述氧化铝衬底的情况下进行。
18.根据权利要求5所述的工艺，其中所述沉积在无需预处理所述二氧化硅衬底的情况下进行且通过ASTM D 3359-02-用于利用带测试测量粘附性的标准测试方法，所得钼薄膜展现>95％的粘附性。
19.根据权利要求1所述的工艺，其中所述工艺在无需预成核步骤的情况下进行。
20.一种半导体装置，其具有沉积于其上的钼薄膜，其中当在厚度为
Figure FDA0003028181270000021
的薄膜上测量时，所述薄膜包含大于99％钼、小于1％氧、大于99％的保形性和小于20μΩ·cm的电阻率。
CN201980069107.2A 2018-10-24 2019-10-16 用于在衬底上形成钼薄膜的方法 Pending CN112889132A (zh)

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