TWI787503B - Method of manufacturing a 3d semiconductor wafer - Google Patents

Abstract

A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

Description

Method for manufacturing 3D semiconductor wafers Cross references to patents

This patented invention enjoys priority over concurrently filed U.S. patents 12/577,532, 12/706,520, 12/792,673, 12/797,493, 12/847,911, 12/849,272, 12/859,665, the contents of which are incorporated herein by reference .

The invention relates to the general field of integrated circuit (IC) components and manufacturing processes, in particular to the general field of multilayer and/or three-dimensional integrated circuit (3D IC) components and manufacturing processes.

Semiconductor manufacturing has increased component density exponentially over time, but this improvement has come at a price. That is, the cost of mask sets for each new process technology will also increase exponentially. Twenty years ago, a mask set cost less than $20,000; today's state-of-the-art mask sets typically cost $1 million.

These changes have mainly brought greater challenges to customized products. The smaller production capacity and more unitary market targeted by the components will bear the ever-increasing cost of product development, and even struggle.

Custom ICs can be divided into 2 market segments: The first is components where all layers of the product are custom. The second is that the partial layer of the product is a general layer, which can be applied to different customized products. In the second type of product, there is the famous gate array, that is, all layers use the common layer to the contact layer, and the contact layer completes the connection between silicon components and metal conductors, and there is a programmable gate array (FPGA), all layers are for the general layer. The common layers of the above-mentioned components are almost all arranged in a repeating structure, called the main chip, which is in the form of an array.

Logic array technology is based on a common structure that can be customized for a specific design during the customization phase. Customization of an FPGA is usually done using electrical programming. For gate arrays, modern structures are often referred to as structured application-specific integrated circuits (or, structured ASICs), and customization requires at least one custom layer, which can be done by direct writing with electron beams or a custom mask. Because the number of logic and memory and I/O module types in the design may vary greatly, suppliers of logic arrays usually produce product families, each product has a different number of main chips, which include a series of logic chips, Different sizes of storage chips and I/O chip configurations are available for customers to choose. However, determining the minimum master set has always been a challenge. A suitable master set can well adapt to large-scale design solutions, and if each product requires a dedicated mask set, the cost will skyrocket.

US Patent 4733288, authorized to Sato in March 1977, discloses a method for manufacturing gate array LSI chips, which can be cut into pairs of chips, and each chip has gate circuits of the required size and quantity according to the circuit design. Sato is cited in the references of this patent, and this idea can provide several ways to utilize the common layer for custom components of different sizes.

The array structure meets the requirements of different sizes. The difficulty in providing array structures of different sizes lies in the need to provide I/O chips and corresponding pads to connect components and package chips. To overcome this limitation, Sato suggested a method in which I/O chips could be built using transistors for general-purpose logic gates. Anderson also suggested a similar method. In U.S. Patent 5,217,916, this patent was authorized to Anderson et al. on July 8, 1993, disclosing a method of using transistor gate wafers to break through the preset limit and freely set the gate array. Type chips are used as logic chips, providing input and output functions. Correspondingly, the input and output functions can also be arranged around the logic array, and the size of the logic array is determined according to the application. The serious limitation of this method is that the I/O chip must use the same transistor as the logic chip, so the operating voltage of the I/O chip cannot be increased.

US Patent 7,105,871 issued September 12, 2006 to Or-Bach et al. discloses a semiconductor device including an unbounded logic array and local I/O chips. The logic array may contain a duplicated core, and at least one local I/O, which may serve as a configurable I/O.

In the past, it was common to design a configurable I/O chip to meet different customer needs. The growing demand for higher data rate I/O has driven the development of dedicated serial I/O circuits known as SerDes (Serializer/Serial to Parallel Converter) transceiver chips. These circuits are very complex and require larger silicon chips than conventional I/O chips. Thus, different configurations are implemented with different numbers of logic circuits, different numbers and types of memory chips, and different numbers and types of I/O chips. This means that even with current state-of-the-art unbounded logic arrays, multiple expensive mask sets still need to be used.

Today, the most common FPGA chips commercially available are based on static random access memory (SRAM) as the programming component. Floating-gate flash memory programmable devices also have some applications. There are also a small number of FPGAs that use antifuse memory as a programmable component. The first generation of antifuse FPGAs used antifuse directly embedded on the silicon substrate. The second generation moves the antifuse storage to the metal layer, which is called metal-metal antifuse storage. Antifuse functions like programmable vias. However, unlike vias that are made of the same metal and used to connect layers, antifuse typically uses amorphous silicon and some interfacial layers. Although, theoretically, antifuse memory can support a higher density than SRAM, SRAM FPGA has become the mainstream of the market today. In fact, antifuse storage FPGA components seem to have no one to continue to develop. One of the serious problems of antifuse memory is the lack of reprogrammable function. Another drawback is the specialized silicon production process required for antifuse storage, which requires additional R&D costs and can cause a time lag relative to benchmark IC technology scaling.

The drawback of common FPGA technology is their relatively inefficient use of silicon area. Although end users only care about whether their components can achieve the functions they want, the functional programming characteristics of FPGAs require that most of the silicon area be occupied for programming and program verification functions.

Some examples of this invention will seek to break through the limitations of current technology by using special types of transistors above or below the antifuse programmable interconnect circuit to achieve additional functions, making the use of silicon area more efficient efficient.

One type of transistor is the thin film transistor, also known as TFT, which is common in the art today. Thin film transistors have been proposed and used for more than 30 years. One of the more well-known applications is in screens, where TFTs are arranged on glass surfaces as screen screens. Another kind of transistor can also be processed on the antifuse memory programmable interconnection circuit, which is called vacuum field effect transistor (FET), which was proposed by US Patent 4721885 30 years ago.

Other available technologies include silicon-on-insulator (SOI) technology. In US patents 6,355,501 and 6,832,826, both granted to IBM, a multilayer 3-dimensional complementary metal oxide semiconductor (CMOS) integrated circuit is proposed. The patent proposes bonding a thin SOI wafer on top of the SOI wafer, forming another IC on one IC, and then connecting the two circuits through silicon vias or through-layer vias (TLV). Substrate manufacturer Soitec SA, Bernin, France, is now able to offer the technology, which stacks a processed thin-layer wafer on a bottom wafer.

Integrating a surface transistor on an insulating layer of an IC is uncommon because existing processes result in lower quality and density of the surface transistor than the bottom (substrate) layer. Monocrystalline silicon can be used as the substrate, which is an ideal and preferred solution for manufacturing high-density and high-quality transistors. There are also patent inventions that suggest the use of transistors to build storage chips, such as US patents 6815781 and 7446563; and some FPGAs based on SRAM, such as US patents 6515511 and 7265421.

The case of this patent aims to obtain higher density antifuse programmable logic chips by utilizing the advantages of surface transistors. An additional advantage of this is that by using a custom mask to replace the antifuse function, a method can be obtained to further reduce the cost of high-volume production, thereby ultimately eliminating the need for surface antifuse logic chips.

In addition, some cases in the present invention also provide new alternatives for multi-layer 3D IC technology. As on-chip interconnect circuits become the limiting factor for component scalability and power enhancement, 3D ICs may be an important technology for future IC chips. Currently, the only packaging technology that can be used for 3D ICs is through silicon vias (TSV). The problem with TSVs is that the vias are relatively large (a few microns in area each) and can result in significantly limited vertical connectivity. The patent of this invention may be able to provide several different alternatives for 3D IC and improve the vertical connection to a certain extent.

Building the 3D ICs of the future will require new structures and new ways of thinking. In particular, to solve the production capacity and stability problems of extremely complex 3D systems, the biggest challenge facing the current deep sub-micron generation process is the production capacity and stability problems of building complex ASICs.

Fortunately, current testing techniques are likely to prove suitable for 3D IC manufacturing, although the method of implementation may be very different. Figure-116 shows the existing group scan architecture used in 2D IC ASIC 11600. ASIC functions appear in logic clouds 11620, 11622, 11624, and 11626, separated by contiguous chips, in the form of dual flip-flops as in 11612, 11614, and 11616. ASIC 11600 also has input pads 11630 and output pads 11640 . Flip-flops are usually equipped with circuitry that enables them to function as shift registers in test mode. In FIG. 116, flip-flops form a scan register chain such that pairs of flip-flops 11612, 11614, and 11616 combine with scan test controller 11610 to form a sequence. Figure 116 shows a scan chain, but the actual design contains millions of flip-flops and many sub-chains.

In the test structure of FIG. 116, the test partitions are shifted into scan chains in test mode. The part is then placed in run mode for one or more clock cycles, after which the contents of the flip-flops are shifted out and compared with the expected result. Although the number of test partitions can be quite large in real designs, and it is possible to use an external tester, this may provide an excellent way to isolate errors and diagnose problems.

Figure-117 shows the Boundary Scan architecture of the prior art shown with ASIC 11700 as an example. The function of this part is shown in logic function block 11710. Also in this section are various I/O dies 11720, each die containing a bond pad 11722, an in-out buffer 11724, a 3-state output buffer 11726. Boundary scan register chains 11732 and 11734 are connected to scan test control block 11730 in a chain. Such an architecture has a similar working mode to the group scan architecture in FIG. 116 . The test partition is moved in, the part is started to be timed, and the results are compared with the expected results after they are moved out. Usually, group scan and boundary scan are used together in the same ASIC, thus forming a complete test range.

Figure 118 shows the existing built-in self-test (BIST) architecture for testing logic block 11800, which includes a core block function 11810 (i.e. the chalk to be tested), input 11812, output 11814, a BIST controller 11820, an input linear feedback shift register (LFSR) 11822, an output cyclic redundancy check (CRC) circuit 11824. Under the control of BIST controller 11820, LFSR11822 and CRC11824 are initialized (i.e., given a known initial value), block 11800 starts timing with a preset number of times, and LFSR11822 sends a pseudo-random test partition to the input of function block 11810, and is determined by CRC 11824 checks the output of function block 11810. After a preset clock cycle, the content of CRC 11824 is compared with the expected value (or signature). If the signatures match, the function block 11800 passes the test and will be considered to be working properly. This type of testing is useful for quick "go" or "fail" testing because the test is independent of the functional block being tested and does not require sorting through a large number of test partitions or using an external tester. BIST, group-scan and boundary-scan technologies are often combined in a complementary manner and used on the same ASIC. For a detailed theoretical discussion on LSFR and CRC, please refer to pages 432-447 of "Digital System Testing and Design for Testability". The author of the book is Abramovici, Breuer & Friedman, Computer Science Press (Computer Science Press), 1990.

Another technology suitable for solving 3D IC productivity and reliability issues is triple module redundancy (triple-mode redundancy). This technique is to implement circuit design using three layers of redundancy and compare the results. Since the output of 2 or 3 circuits is always the same (such as a binary signal), the voting circuit (or majority of 3/MAJ3) will take this same output as the result. Although this technology is mainly used in systems with high reliability requirements or high radiation resistance requirements, such as military, aerospace and space applications, it can also be used to cover up faulty circuit errors, because only two of the three The circuit is normal, and all functions of the system will work normally. A discussion of radiation tolerance of TMR systems, Single Event Effects (SEE), Single Event Upset (SEU), Single Event Transient (SET) can be found in US Patent Application Publication 2009/0204933, assigned to Rezgui.

According to some cases of this invention, 3D technology can also form a very novel IC alternative, which can reduce research and development costs, increase production capacity, and bring other advantages.

The case of this invention is to find a most efficient new process for the manufacture of semiconductor components for custom products. The example of this invention proposes the use of reprogrammable antifuse and "Through-Silicon Via (TSV)" to build a new programmable logic device, ie FPGA device. Examples of this invention may provide solutions to the challenges of high mask set cost and low flexibility faced in existing common processes for semiconductor manufacturing. Another advantage of some cases of this invention is that it can reduce the high cost of manufacturing different mask sets that can provide commercial logic device series and product lines, so that each product has a different main die set. The case of this invention should be able to achieve improvements in many aspects of the existing technology, including the construction method of semiconductor components and the manufacturing process of related semiconductor components.

The example of this invention reflects an effort to save mask costs over existing investments that would otherwise require the production of a set of commercial masters. Examples of this invention also seek the ability to include different types of memory blocks on a configurable component. Examples of the present invention provide a process for constructing programmable devices that can include as many logic, memory, I/O, and analog functions as desired on the device.

In addition, examples of the present invention can also use duplicate logic boards (LT), which can provide sequentially distributed logic. The example of this invention demonstrates that, with the help of through-silicon vias (TSVs), a modular approach can be used to build different configurable systems. Once the standard size and location of TSVs are defined, one can manufacture different configurable logic chips, configurable memory chips, configurable I/O chips, configurable analog circuit chips, and then connect them to build different configurable chips. Set up the system. In fact, it is possible to create a mix and match of different programmable chips, mixed function chips, and chips made using different processes.

Some examples of this invention will bring other advantages, such as more efficient use of silicon area by using special types of transistors above and below the antifuse programmable interconnect circuit. Typically, FPGA devices use antifuse memory to set the function of the device, and may also include electronic circuits that can program the antifuse memory. Programming circuits can be used to configure components first, and become a system expense most of the time once system setup is complete. The voltage used to program the antifuse is usually much higher than the operating voltage of the component circuit. The design of the anti-melt storage structure can realize that the unused anti-melt storage will not melt easily. Therefore, incorporating antifuse programming on the silicon substrate may require extra care to program the high voltages, which in turn may require allocating an additional silicon die.

In order to meet the performance requirements of high-speed components, the maximum requirement of the working transistor is speed, and the programming circuit can work relatively at a lower speed. Therefore, the programming circuit can use thin film transistors, which can well meet the functional requirements and reduce the need for silicon chip area.

Programming circuits can be built with thin film transistors, which can be fabricated on a programmable interconnect layer that contains and uses antifuse memory after the working circuit has been fabricated. Another advantage of the present invention is that it can reduce the cost of mass production. One may only need to use mask-defined connections, rather than antifuse and programming circuits. It is also possible to use a custom via mask, which reduces the number of steps involved in fabricating the antifuse memory layer, thin film transistor, and/or programming circuit interconnect layer.

In accordance with the examples of the present invention, an integrated circuit module is shown comprising a pair of antifuse programmable interconnection circuits and a pair of transistors for programming one of the above-mentioned antifuse memories, the transistors being fabricated in the antifuse memory Afterwards.

Further in accordance with the examples of the present invention, an integrated circuit module is presented comprising a pair of antifuse programmable interconnection circuits and a pair of transistors for programming one of the aforementioned antifuse memories, the transistors being fabricated in the antifuse Storage is at least processed.

Further according to the example of the present invention, the provided integrated circuit assembly includes a second pair of antifuse programmable logic chips and a pair of second transistors for setting one of the above-mentioned second antifuse memory, Fabrication of the second transistor is processed after antifuse storage.

Similarly, according to the case of the present invention, the given integrated circuit assembly includes a second pair of antifuse memory programmable logic chips and a pair of second transistors for setting one of the above-mentioned second antifuse memory , the second transistor is disposed under the second antifuse storage.

According to an example of the present invention, an integrated circuit assembly includes: a first antifuse layer having at least two metal layers thereon, and a second antifuse layer on top of the two metal layers.

According to the case of the present invention, a settable logic component includes: an antifuse settable look-up table logic, which is connected through an antifuse settable interconnection circuit.

According to the case of the present invention, a settable logic component includes: paired antifuse programmable look-up logic devices, paired programmable logic array (PLA) logic devices, and paired antifuse interconnected circuits.

According to the case of the present invention, a settable logic component includes: paired antifuse memory settable look-up table logic, paired settable drive chips, and the chips are set through paired antifuse memory.

According to the example of the present invention, a settable logic component includes: a settable logic chip connected by a pair of antifuse settable interconnection circuits, and at least one antifuse settling interconnection circuit in the circuit is set through a permanent memory.

Still according to the example of the present invention, a configurable logic element includes at least one antifuse interconnection circuit, and can be set through the PLA function.

In accordance with an alternate embodiment of the invention, an integrated circuit system includes: a programmable logic die and an I/O die, the programmable I/O die is connected to the I/O die using straight-through-silicon vias (TSVs) .

Still in accordance with an alternative embodiment of the invention, an integrated circuit system includes a programmable logic chip and a memory chip, the chips being connected using through-silicon vias (TSVs).

Still in accordance with an alternative example of the present invention, an integrated circuit system includes: a first configurable logic chip and a second configurable logic chip, the first configurable logic chip and the second configurable logic chip use silicon die through Via (TSV) connected.

Also, in accordance with the example of the present invention, the integrated circuit system includes an I/O chip fabricated using a different process than the configurable logic chip.

Still according to an alternative example of the present invention, an integrated circuit system includes at least two logic chips connected through through-silicon vias (TSVs), some of which are used to transmit system bus signals.

According to an example of the present invention, an integrated circuit system includes at least one programmable logic device.

Still in accordance with an alternative embodiment of the invention, an integrated circuit system includes: an antifuse programmable logic chip and a programming chip, said chips being connected using through-silicon vias (TSVs).

In addition, there is an increasing need to reduce the impact of interconnecting circuits between chips. In fact, interconnect circuitry is now a major factor in IC performance and power. 3D IC can be regarded as a way to shorten the interconnection circuit. At present, for general-purpose logic 3D ICs, a known and available method is to use through-silicon vias (TSVs) to stack processed components. The problem with TSVs is that the vias are relatively large, each measuring a few microns in area, which can severely limit the number of TSVs that can be used. Some examples of this invention present alternatives for building 3D ICs, many connections (TSVs) can be made smaller than 1 micron in size, making 3D IC technology usable for most devices.

In addition, using the 3D IC technology proposed in this invention can also provide an alternative for the production of new components.

860-1~860-4‧‧‧Programmable Transistor

820-1,1~820-2,2‧‧‧antifuse

830-1‧‧‧Metals

850-1,1,850-1,2‧‧‧antifuse

310-1~310-4‧‧‧Metal strip

308-1~308-4‧‧‧Metal strip

312-1~312-4‧‧‧Antifuse

300,320‧‧‧tiles

302‧‧‧Y selection logic

304‧‧‧Y programmable transistor

306‧‧‧Programmable Voltage

314‧‧‧Grounding

316‧‧‧X selection logic

318‧‧‧X programmable transistor

300B‧‧‧programmable interconnect structure

308-4B1, 308-4B2‧‧‧shorter

312-3B,312-4B‧‧‧Antifuse

318B, 318B1‧‧‧X programmable transistor

402,404,408,412‧‧‧Metal strips

406,410‧‧‧Antifuse

502‧‧‧Input

504‧‧‧phase inverter

506‧‧‧Output

510‧‧‧phase inverter

512‧‧‧Input

514‧‧‧Buffer

516‧‧‧output

520‧‧‧Antifuse Configurable Driver Unit

522‧‧‧Input

524‧‧‧Configurable strength buffer

524-1,524-3‧‧‧Buffer

526‧‧‧output

528-1~528-3‧‧‧Antifuse

530‧‧‧Delay trigger unit

532-2‧‧‧Input

532-1, 532-3~532-5‧‧‧Control input

534‧‧‧Delay trigger

536‧‧‧output

600‧‧‧logic elements

602-1~602-4‧‧‧input

602-6, 602-7‧‧‧Additional input

604‧‧‧Information Form 4

604-5‧‧‧2:1 Multiplexer

606‧‧‧Output

608-1‧‧‧Antifuse

6A00‧‧‧Programmable logic array logic unit

6A01‧‧‧Antifuse

6A02‧‧‧Input value

6A06‧‧‧Output

6A14‧‧‧Multi-input and

6A15‧‧‧Multi-input or

700‧‧‧programmable design unit

701‧‧‧Antifuse

701HV‧‧‧Antifuse

701VV‧‧‧Antifuse

701HH‧‧‧Antifuse

702‧‧‧Input value

706‧‧‧output value

708‧‧‧Input and output strips

710‧‧‧Logic unit

720‧‧‧configurable interconnect structure

722V‧‧‧separator

722H‧‧‧level bar

724‧‧‧Long

724LH‧‧‧Antifuse

802‧‧‧base

804‧‧‧The first layer of antifuse

806‧‧‧floor

807‧‧‧Second layer antifuse

808‧‧‧Pretreatment wafer or layer

808A, 808B, 808C‧‧‧Pretreatment wafer or layer

809,809A,809B‧‧‧transfer layer

810‧‧‧configurable interconnect structure

812‧‧‧Connect to external

814‧‧‧priority line

816‧‧‧contact connection

402‧‧‧base

404‧‧‧Through Silicon Via (TSV)

102‧‧‧Ceramic Bubbles

102-1‧‧‧Porcelain

102-2‧‧‧Porcelain

104‧‧‧Line

104-1‧‧‧Possible scribe lines

104-2‧‧‧Possible scribing lines

106‧‧‧Serializer Four-core wire

108‧‧‧blocks

1100A‧‧‧Programmable logic fragments

1101‧‧‧Porcelain

1102‧‧‧possible scribing line

110B‧‧‧Structured ASIC

1102‧‧‧possible scribing line

1100C‧‧‧RAM tile

1100D‧‧‧DRAM tile

1100E‧‧‧microprocessor or microcontroller core

1100F‧‧‧Input/Output Fragmentation

1202A‧‧‧base

1204A‧‧‧Chip

1206A‧‧‧Chip

1208A‧‧‧Chip

1202B‧‧‧base

1204B‧‧‧chip

1206B‧‧‧chip

1202C‧‧‧base

1202D‧‧‧base

1202E‧‧‧bottom chip

1204E‧‧‧Chip

1206E‧‧‧Chip

1208E‧‧‧Chip

1402‧‧‧Wafer

1404‧‧‧floor

1406‧‧‧donor wafer

1408‧‧‧Intelligent cutting line

1410‧‧‧3D Wafer

1412‧‧‧Oxide layer

1414‧‧‧top part

1501,1502‧‧‧Programmable Transistor

1504‧‧‧Antifuse

1506,1508‧‧‧programmable connection

1601,1602‧‧‧Isolation transistor

1603‧‧‧Control circuit

1604‧‧‧Antifuse

1606,1608‧‧‧logic transistor

1610‧‧‧Antifuse

1710‧‧‧Division

1711‧‧‧Feedback bias circuit

1720‧‧‧Feedback bias stage control circuit

1721‧‧‧Voltage generator

1723,1724‧‧‧Connection

1725‧‧‧Negative voltage generator

1726‧‧‧Positive voltage generator

1727,1729‧‧‧Oscillators

1732‧‧‧N-type channel metal-oxide-semiconductor transistor

1734‧‧‧P-type channel metal-oxide-semiconductor transistor

17C02‧‧‧power control circuit unit

17C04‧‧‧Control circuit

17C08, 17C10‧‧‧ District

17C12‧‧‧power cord

17C16‧‧‧Main equipment

17D02‧‧‧Sequential active circuit components

17D06‧‧‧Interconnection wire

17D08‧‧‧High Impedance Probe Circuit

17D12‧‧‧selection circuit

17D14‧‧‧probe output signal

17D16‧‧‧Buffer

1802‧‧‧SRAM cell

1806,1808‧‧‧Logic Circuits

1812‧‧‧Connection

1912‧‧‧Output driver

1914‧‧‧Input/Output Connection

1916‧‧‧Input protection circuit

1920‧‧‧Input logic

1922‧‧‧Buffer

1924‧‧‧Connection

19B06‧‧‧PMOS and NMOS output transistor

19B08‧‧‧Back chip or chip bump

19B10‧‧‧through silicon via

19C10‧‧‧Chip

19C12‧‧‧through silicon via

19C14‧‧‧primary silicon

19C20‧‧‧Chip

19C22‧‧‧through silicon via

19C24‧‧‧primary silicon

19C30‧‧‧Chip

19C32‧‧‧through silicon via

19C34‧‧‧primary silicon

19C40‧‧‧Bump

19D02‧‧‧radiator

19D04‧‧‧Substrate of heat spreader

19D06‧‧‧Intermediary layer

19D08‧‧‧through hole

19D12‧‧‧Heat spreader

19D14‧‧‧effective area of microprocessor

19D16‧‧‧Fundamentals

19D18‧‧‧Multi-compression DRAM

19D20‧‧‧through-silicon via

19D22‧‧‧through silicon via

19D24‧‧‧DRAM Stacking

19E24‧‧‧Wire welding

19E26‧‧‧Redistribution layer

19F00‧‧‧Nu perforation

19F01‧‧‧Buried oxide

19F02‧‧‧Substrate wafer

19F03‧‧‧Nu contact

19F04‧‧‧Dnu contact

19F05‧‧‧Thin silicon

19G00‧‧‧Bulk silicon wafer

19G02‧‧‧DTSV_Prior Technology

19H04‧‧‧Donor silicon wafer

19H05‧‧‧Surface

19H06‧‧‧Depth

19H07‧‧‧Nu piercing

19H08‧‧‧Acceptor Wafer

19H10‧‧‧Donor silicon wafer part

19I09‧‧‧Processor

19I10‧‧‧DRAM

19I11‧‧‧radiator

19I12‧‧‧base

19I13, 19I14‧‧‧Through silicon connection

19J01‧‧‧base

19J02‧‧‧top silicon layer

2002‧‧‧Preliminary wafer processing

2004‧‧‧Additional layer

2006‧‧‧donor wafer

2008‧‧‧Intelligent cutting line

2010‧‧‧3D Wafer

2011‧‧‧BEOL layer

2012‧‧‧Oxide layer

2014‧‧‧top part

2019‧‧‧semiconductor layer

2102‧‧‧P type wafer

2104‧‧‧N-Type Wafer

2106‧‧‧P-Epitaxial growth

2108‧‧‧P+ layer

2110‧‧‧Cleavage surface

2112‧‧‧Oxide

22B02‧‧‧gate designation area

22B04‧‧‧Top Transistor Source

22B06‧‧‧Top Transistor Drain

22B08‧‧‧Isolation Area

22C02‧‧‧Low temperature oxide

22D02‧‧‧Gate formation self-aligned etching process preparation

22D04‧‧‧source and drain extension regions

22E02‧‧‧Low temperature gate dielectric

22F02‧‧‧Metal grid

22G02‧‧‧thick oxide

22G20‧‧‧transistor

22F02‧‧‧Gate

22F02-1‧‧‧Back gate

2302‧‧‧N-Wafer

2304‧‧‧N+ floors

2306‧‧‧Cleavage surface

2308‧‧‧Oxide

24A04‧‧‧N+ layer

24B02‧‧‧gate designation area

24B04‧‧‧Top Transistor Source

24B06‧‧‧Top Transistor Drain

24B08‧‧‧Isolation area between transistors

24B09‧‧‧Etching space

24C02‧‧‧Removing N-layer between transistors

24D02‧‧‧shallow P+ area

24D04‧‧‧Reflective layer

24D06‧‧‧light

24D08‧‧‧opening area

24D10‧‧‧reflective layer

24E02‧‧‧thick oxide

24E04‧‧‧Photon energy absorbing layer

24F02‧‧‧Gate contact

24F04‧‧‧thick oxide

24F06‧‧‧N+ contact

2502‧‧‧N-Wafer

2504‧‧‧N+

2506‧‧‧Intelligent cutting cleavage surface

2508‧‧‧N-Epitaxial growth layer

2510‧‧‧P+ layer

2512‧‧‧Oxide

26B02‧‧‧Gate designated area

26B04‧‧‧Top Transistor Source

26B06‧‧‧Top Transistor Drain

26B08‧‧‧Isolation area between transistors

26C09‧‧‧Remove P+ layer between transistors

26C12‧‧‧Removing N-layer between transistors

26D02‧‧‧Shallow P+ area

26E02‧‧‧Gate contact

26E04‧‧‧thick oxide

26E06‧‧‧N+ contact

26E12‧‧‧contact

2702‧‧‧N+ wafer

2704‧‧‧P-layer

2706‧‧‧Intelligent cutting cleavage surface

2708‧‧‧N-layer

2710‧‧‧N+ floors

28A02‧‧‧N+ doped layer

2802‧‧‧base

2804‧‧‧Low temperature oxide

2806‧‧‧emitter

2808‧‧‧Aggregator

2809‧‧‧Isolation

29B02‧‧‧Transistor isolation

29B04‧‧‧Substrate P+ source contact opening

29C02‧‧‧Isolation Area

29C04‧‧‧Low temperature oxide

29C06‧‧‧Grinding inhibition layer

29D02‧‧‧source

29D04‧‧‧Drain

29D06‧‧‧Gate

29D08‧‧‧source and drain extension regions

29E02‧‧‧Gate dielectric

29E04‧‧‧Gate material

29G02‧‧‧thick oxide

29G04‧‧‧Perforation

29G06‧‧‧Low-level interconnection wiring

3000‧‧‧donor wafers

3000L‧‧‧transfer layer

3002‧‧‧Inflatable projection

3004‧‧‧N-type transistor rows

3006‧‧‧p-type transistor rows

3008‧‧‧West

3020‧‧‧Alignment mark

3040‧‧‧Four basic orientation indicators

3100‧‧‧Master Wafer

3120‧‧‧Alignment mark

3122‧‧‧North-south DY misalignment

3124‧‧‧DX misalignment

3202‧‧‧residue

33A02‧‧‧Perforation

33A04‧‧‧North-South Landing Strip

33B02‧‧‧Perforation

33B04‧‧‧North-South Landing Strip

3400‧‧‧Number of repeated lines

3402‧‧‧P-type wafer

3404‧‧‧N+ floors

3406‧‧‧P+ layer

3408‧‧‧P-Epitaxy

3410‧‧‧N-District

3412‧‧‧Shallow P+

3414‧‧‧shallow N+

3416‧‧‧Intelligent cutting cleavage surface

3418‧‧‧Oxide

3500‧‧‧Basic

3502‧‧‧cleavage surface

35B02‧‧‧Transistor isolation

35B04‧‧‧Metal layer

35B06‧‧‧base P+

35B08‧‧‧Substrate N+

35C02‧‧‧Isolation area

35C04‧‧‧Oxide

35C06‧‧‧Grinding inhibition layer

35D02‧‧‧n-type channel source

35D04‧‧‧n-type channel drain

35D06‧‧‧n-type channel self-aligned gate

35D08‧‧‧p-type channel source

35D10‧‧‧p-type channel drain

35D12‧‧‧p-channel self-aligned gate

35D14‧‧‧P+ corner source and drain extension regions

35E02‧‧‧Gate dielectric

35E04‧‧‧Metal grid

35G02‧‧‧Oxide

35G04‧‧‧Perforation

3600‧‧‧wafer

3601‧‧‧Porcelain

3602‧‧‧possible scribing line

3611‧‧‧terminal equipment

3612‧‧‧actual scribing line

3700‧‧‧wafer

3701‧‧‧Porcelain

3702‧‧‧Micro Control Unit-MCU

3702-00‧‧‧MCU

3702-01‧‧‧MCU

3702-11‧‧‧MCU

3702-12‧‧‧MCU

3704‧‧‧MCU to MCU connection

3711‧‧‧Porcelain

3714‧‧‧MCU to MCU connection

3800‧‧‧Porcelain in the southwest corner

3802‧‧‧Control input value

3814‧‧‧Time Delay Integration (TDI)

3816‧‧‧Time Delay Integration (TDI)

3820‧‧‧Northeast corner fragment

3822‧‧‧TDO output

3902‧‧‧P-type wafer

3904‧‧‧N+ floors

3906‧‧‧P-layer

3908‧‧‧N+ floors

3910‧‧‧Conductive barrier layer

3912‧‧‧Intelligent cutting cleavage surface

3914‧‧‧Al-Ge layer

3916‧‧‧Conductive barrier layer

3920‧‧‧Indoor metal layer

4002‧‧‧Etching inhibition layer

4004‧‧‧conductive layer

4006‧‧‧transistor tower

4010‧‧‧Oxide

4014‧‧‧Sidewall gate oxide

4018‧‧‧gate layer

4020‧‧‧Gate mask photoresist

4022‧‧‧Space gate electrode

4024‧‧‧Gate electrode

4030‧‧‧Oxide

4034‧‧‧Pierce Contact to Tower N+

4036‧‧‧Through hole contact to gate electrode

4040‧‧‧Metal wire

4100‧‧‧The first layer of programmable design layer

4102‧‧‧3*3 tiles

4104‧‧‧Programmable connection

4105‧‧‧Branch Programmable Connection

4106‧‧‧Programmable design components

4107‧‧‧Programmable design components

4108‧‧‧Programmable design components

4110‧‧‧The second layer of programmable design layer

4112‧‧‧3*3 tiles

4116‧‧‧Programmable design components

4117‧‧‧Programmable design components

4118‧‧‧Programmable design components

4120‧‧‧The third layer of programmable design layer

4122‧‧‧3*3 tiles

4140‧‧‧Vertical connection between layers

4202‧‧‧NMOS Transistor

4204‧‧‧PMOS transistor

4206‧‧‧NMOS source

4207‧‧‧PMOS source

4208‧‧‧NMOS and PMOS drain

4210‧‧‧NMOS&PMOS Gate

4300‧‧‧Highly doped N-type monocrystalline silicon wafer

4301‧‧‧P-layer

4302‧‧‧resistive layer

4304‧‧‧Oxide

4310‧‧‧P-type wafer

4312‧‧‧Oxide

4314‧‧‧Intelligent cutting cleavage surface

4316‧‧‧cleavage surface

4400‧‧‧Oxide layer

4402‧‧‧Protected oxides

4404‧‧‧Grinding inhibition layer

4406‧‧‧NMOS source to ground connection

4410‧‧‧Shallow trench (STI) isolation region

4411‧‧‧Gate oxide

4412‧‧‧NMOS gate

4414‧‧‧Polysilicon on STI trench interconnect

4416‧‧‧Implant offset interval

4418‧‧‧NMOS transistor source and drain

4420‧‧‧Oxide

4422‧‧‧Wafer surface

4500‧‧‧Oxide layer

4502‧‧‧N-Wafer

4504‧‧‧Oxide

4506‧‧‧Intelligent cutting cleavage surface

4508‧‧‧cleavage surface

4510‧‧‧Oxide layer

4512‧‧‧Shallow trench (STI) isolation region

4514‧‧‧Gate oxide

4516‧‧‧PMOS gate

4518‧‧‧Polysilicon on STI Trench Interconnect

4520‧‧‧Implant offset interval

4522‧‧‧PMOS transistor source and drain regions

4524‧‧‧Oxide

4530‧‧‧Etching inhibition and grinding inhibition layer

4532‧‧‧The deepest contact

4540‧‧‧NMOS drain only contact

4542‧‧‧NMOS&PMOS gates on STI interconnect contacts

4544‧‧‧NMOS and PMOS drain contacts

4546‧‧‧NMOS only gate on STI contact

4550‧‧‧PMOS gate interconnect on STI contacts

4552‧‧‧PMOS only gate contact

4554‧‧‧PMOS only drain contact

4600‧‧‧STI (Shallow Trench Isolation)

4602‧‧‧NMOS and PMOS gate

4604‧‧‧NMOS gate on STI to PMOS gate on STI contact

4606‧‧‧N+ source contact to ground plane

4608‧‧‧PMOS source contact

4610‧‧‧NMOS and PMOS Drain Common Contact

4702‧‧‧NMOS Transistor

4704‧‧‧PMOS Transistor

4706‧‧‧NMOS source

4707‧‧‧PMOS source connected to +V

4708‧‧‧PMOS drain

4710‧‧‧NMOS&PMOS gate

4800‧‧‧STI (Shallow Trench Isolation)

4802‧‧‧NMOS and PMOS gate

4804‧‧‧NMOS gate on STI to PMOS gate on STI contact

4806‧‧‧N+ source contact to ground plane

4808‧‧‧PMOS source contact

4810‧‧‧NMOS and PMOS Drain Common Contact

4812‧‧‧NMOS source contact

4900‧‧‧STI (Shallow Trench Isolation)

4902‧‧‧PMOS-B gate

4904‧‧‧Virtual gate

4906‧‧‧PMOS-A gate

4908‧‧‧Only PMOS gate on STI contact

4910‧‧‧NMOS-A gate

4912‧‧‧NMOS-B gate

4914‧‧‧NMOS gate on STI to PMOS gate on STI contact

4916‧‧‧NMOS unique gate on STI contact

4918‧‧‧N+ source contact to ground plane

4920‧‧‧PMOS-B source contact

4922‧‧‧NMOS-A, NMOS-B and PMOS-B drain common contacts

5000‧‧‧STI (Shallow Trench Isolation)

5002‧‧‧NMOS transistor

5004‧‧‧PMOS transistor

5006‧‧‧NMOS gate input

5008‧‧‧PMOS gate input

5010‧‧‧NMOS and PMOS source

5012‧‧‧NMOS and PMOS drain

5014‧‧‧PMOS gate

5016‧‧‧NMOS gate

5018‧‧‧Only PMOS gate on STI contact

5020‧‧‧Only NMOS gate on STI contact

5022‧‧‧NMOS and PMOS source common contacts

5024‧‧‧NMOS and PMOS drain common contacts

5100‧‧‧Transistor isolation oxide

5102‧‧‧Memory transistor M2

5104‧‧‧Memory transistor M4

5106‧‧‧Word line transistor M6

5108‧‧‧Vdd

5110‧‧‧Grounding

5112‧‧‧PMOS polysilicon on STI to NMOS polysilicon on STI contacts

5114‧‧‧PMOS P+ to NMOS N+ contact

5122‧‧‧bit line

5124‧‧‧Bit line Bar line

5202‧‧‧Curve D=1E18/1E17

5204‧‧‧Curve D=1E17/1E18

5206‧‧‧Curve D=1E18/1E17

5208‧‧‧Curve D=1E17/1E18

5300‧‧‧Transistor isolation oxide

5302‧‧‧SRAM state reading transistor M7, M9

5304‧‧‧Transistor M1, M2

5306‧‧‧Transistor M3, M4

5308‧‧‧Metal to Gate on STI Contacts

5310‧‧‧PMOS metal-1

5312‧‧‧PMOS Metal-1

5314‧‧‧PMOS polysilicon on STI to bottom NMOS polysilicon on STI contacts

5316‧‧‧Detection line

5318‧‧‧Detection pole

5320‧‧‧NMOS N+ contact

5322‧‧‧Grounding

5324‧‧‧Contact

5326‧‧‧Pull-down transistor M8, M10

5330‧‧‧Grounding

5332‧‧‧Word line transistor M6

5334‧‧‧Vdd

5336‧‧‧Matching line

5340‧‧‧Bitline Barline

5342‧‧‧bit line

5402‧‧‧N-Wafer

5404‧‧‧N+ floors

5410‧‧‧Conductive barrier layer

5412‧‧‧Intelligent cutting cleavage surface

5414‧‧‧Eutectic bonding

5416‧‧‧Conductive barrier layer

5420‧‧‧Indoor Roof Metal Wire

5500‧‧‧Metal bonding layer

5502‧‧‧Etching inhibition layer

5504‧‧‧N+ floors

5506‧‧‧transistor tower

5510‧‧‧Oxide

5514‧‧‧Sidewall gate oxide

5518‧‧‧P+ doped amorphous silicon

5520‧‧‧Gate mask photoresist

5530‧‧‧Oxide

5534‧‧‧Contact

5536‧‧‧contact to gate electrode

5540‧‧‧Metal wire

5600A‧‧‧N-Wafer

5602A‧‧‧Gate oxide

5604A‧‧‧N+ layer

5600‧‧‧N-Wafer

5602‧‧‧Gate oxide

5604‧‧‧N+ floors

5606‧‧‧implantation

5608‧‧‧Cleavage surface

5610‧‧‧N+ floors

5612‧‧‧Gate oxide

5614‧‧‧parallel lines

5616‧‧‧Gate oxide

5618‧‧‧polysilicon

5620‧‧‧Both oxygen

5608G‧‧‧cleavage surface

5622‧‧‧Metal interconnection strip

5624‧‧‧Oxide

5626‧‧‧Grinding inhibition layer

5628‧‧‧Isolation opening

5629‧‧‧opening

5630‧‧‧Top grid

5632‧‧‧Gate contact

5634‧‧‧Contact

5636‧‧‧Through hole

5640‧‧‧Metal wire

5700‧‧‧N-Wafer

5702‧‧‧Oxide

5704‧‧‧N+

5706‧‧‧Interconnection

5707‧‧‧Implantation

5708‧‧‧Cleavage surface

5710‧‧‧Gate oxide

5712‧‧‧Gate material

5714‧‧‧Top and side grid

5716‧‧‧Oxide

5720‧‧‧Gate contact

5722‧‧‧Transistor terminal contacts

5724‧‧‧Through hole

5800‧‧‧N-Wafer

5802‧‧‧Masking Oxide

5804‧‧‧N+ floors

5805‧‧‧CMP and Plasma Etch Suppressor

5806‧‧‧Metal interconnect layer

5808‧‧‧Transistor channel element

5810‧‧‧Gate oxide

5812‧‧‧Gate material

5814‧‧‧Top and side grid

5816‧‧‧Low temperature oxide

5820‧‧‧Gate contact

5822‧‧‧Trench terminal contact

5824‧‧‧Through hole

5902‧‧‧Transistor silicon layer

5904‧‧‧Contact

5905‧‧‧Bottom perforation

5906‧‧‧upper perforation

5907‧‧‧Perforation

5908‧‧‧Perforation

5909‧‧‧Perforation

5910‧‧‧The first metal layer

5912‧‧‧Metal wire

5914‧‧‧Metal wire

5916‧‧‧Metal wire

5918‧‧‧Metal wire

5920‧‧‧Metal wire

5922‧‧‧Bond

6000‧‧‧through silicon vias

6001‧‧‧Perforation

6002‧‧‧Perforation

6003‧‧‧Perforation

6004‧‧‧Perforation

6005‧‧‧Perforation

6006‧‧‧Perforation

6007‧‧‧Perforation

6008‧‧‧Perforation

6009‧‧‧Perforation

6010‧‧‧Contact

6011‧‧‧Metal wire

6012‧‧‧Metal wire

6013‧‧‧Metal wire

6014‧‧‧Metal wire

6015‧‧‧Metal

6016‧‧‧Metal layer

6017‧‧‧Metal

6018‧‧‧Metal wire

6019‧‧‧Metal layer

6020‧‧‧Metal layer

6022‧‧‧PMOS layer transfer silicon

6024‧‧‧First monocrystalline or polycrystalline silicon equipment layer

6100‧‧‧N-Wafer

6102‧‧‧Oxide

6103‧‧‧N+bottom

6104‧‧‧N+top floor

6105‧‧‧etching hard mask layer

6106‧‧‧Interconnecting metal chips or strips

6107‧‧‧implantation

6108‧‧‧junctionless transistor channel

6109‧‧‧Cleavage surface

6110‧‧‧Gate oxide

6112‧‧‧Gate material

6114‧‧‧Top and side grid

6116‧‧‧Oxide

6120‧‧‧Gate contact

6122‧‧‧Transistor source/drain terminal contacts

6124‧‧‧Through hole

6150‧‧‧Photoresist

6151‧‧‧source

6152‧‧‧Drain

6153‧‧‧ditch

6200‧‧‧Transistor isolation oxide

6201‧‧‧PMOS transistor

6202‧‧‧NMOS transistor

6203‧‧‧Input A

6204‧‧‧Input B

6211‧‧‧PMOS source

6212‧‧‧PMOS B drain

6213‧‧‧NMOS drain

6214‧‧‧PMOS metal 2

6215‧‧‧PMOS metal 1

6216‧‧‧V+ supply metal

6217‧‧‧Output Y metal

6218‧‧‧Earth wire

6220‧‧‧NMOS A drain

6300‧‧‧Transistor isolation oxide

6301‧‧‧PMOS transistor

6302‧‧‧NMOS Transistor

6303‧‧‧Input A to PMOS and NMOS gate A junction

6311‧‧‧PMOS transistor source

6312‧‧‧NMOS H source

6313‧‧‧PMOS drain

6314‧‧‧PMOS metal 2

6315‧‧‧Output Y supply metal

6316‧‧‧V+ supply metal

6317‧‧‧P+ to N+ contact

6318‧‧‧Earth wire

6320‧‧‧NMOS A source and NMOS B drain junctions

6400‧‧‧Transistor isolation oxide

6401‧‧‧PMOS transistor

6402‧‧‧NMOS Transistor

6403‧‧‧Input A fragment to PMOS A gate and NMOS A gate

6411‧‧‧PMOS H transistor source

6412‧‧‧NMOS source fragments to the ground

6413‧‧‧NMOS source node

6414‧‧‧Gate on STI to gate on contact on ST

6415‧‧‧NMOS metal-2

6416‧‧‧V+ supply metal

6417‧‧‧P+ to N+ to PMOS metal-2 contacts

6418‧‧‧NMOS metal-1 line

6420‧‧‧PMOS H-drain junction

6421‧‧‧PMOS metal 2

6501‧‧‧Donor wafer oxide layer

6503‧‧‧N+ floors

6504‧‧‧Gate dielectric

6505‧‧‧Gate metal

6506‧‧‧Oxide Isolation

6508‧‧‧Oxide

6510‧‧‧Contact opening

6700‧‧‧p-Silicon Wafer

6701‧‧‧Oxide layer

6702‧‧‧N+ floors

6703‧‧‧P-layer

6704‧‧‧Implanted hydrogen layer

6705‧‧‧Oxide isolation area

6706‧‧‧Concave channel

6707‧‧‧Gate dielectric

6708‧‧‧Gate

6709‧‧‧Low temperature oxide

6710‧‧‧Contact

6800‧‧‧p-Silicon Wafer

6801‧‧‧Oxide

6802‧‧‧N+ floors

6803‧‧‧P-layer

6804‧‧‧Hydrogen Implantation

6805‧‧‧Oxide isolation area

6806‧‧‧Interval precipitation

6807‧‧‧Spherical recess

6808‧‧‧Gate dielectric

6809‧‧‧Metal grid

6810‧‧‧Oxide

6811‧‧‧Contact

6920‧‧‧Replication of donor wafer alignment marks

6920C‧‧‧Closest Donor Wafer Alignment Mark

6922‧‧‧North-south misalignment

7000‧‧‧donor wafers

7001‧‧‧silicon layer

7002‧‧‧Isolation

7003‧‧‧Sensitive gate area

7004‧‧‧polysilicon

7005‧‧‧Gate oxide

7006‧‧‧NMOS source and drain

7007‧‧‧PMOS source and drain

7008‧‧‧interlayer dielectric

7010‧‧‧implantation

7012‧‧‧Cleavage surface

7014‧‧‧Carrier substrate

7016‧‧‧Interface

7018‧‧‧Donor wafer surface

7020‧‧‧Oxide

7022‧‧‧Oxide surface

7001‧‧‧Pretreatment of HKMG silicon layer

7024‧‧‧Metal strip

7026‧‧‧High-k gate dielectric

7028‧‧‧PMOS specific function metal gate

7030‧‧‧NMOS work-specific engineering metal gate

7032‧‧‧Aluminum filling

7034‧‧‧Gate contact

7036‧‧‧Source/Drain Contacts

7040‧‧‧Through hole

7050‧‧‧Isolation Implantation Inhibition Layer of Dense Materials

7052‧‧‧Photoresist

7104‧‧‧p-type transistor row width repetition width

7106‧‧‧p-type transistor row width repetition width Wp

7108‧‧‧Total Repeat W

7110‧‧‧Transistor isolation

7112‧‧‧Transistor source

7113‧‧‧PMOS gate

7114‧‧‧Transistor Drain

7116‧‧‧Transistor source

7117‧‧‧NMOS gate

7118‧‧‧Transistor Drain

7202‧‧‧Quarantine area

7215‧‧‧Replacement grid

7218‧‧‧Gate Contact Landing Area

7220‧‧‧Gate connection

7222‧‧‧source connection

7224‧‧‧Drain connection

7240‧‧‧Interlayer through-hole connection

7302‧‧‧Inflatable projection

7304‧‧‧Wy

7306‧‧‧Wx

7308‧‧‧Rdx

7502‧‧‧Through hole

7504‧‧‧Rectangular landing area

7602‧‧‧Wv

7604‧‧‧Wn

7606‧‧‧Wp

7610‧‧‧Transistor isolation

7612,7614‧‧‧effective area

7616‧‧‧Common isolation area

7618‧‧‧layer-to-layer perforated channel

7622,7622B‧‧‧Gate

77A02‧‧‧Through hole

77A04,77A06‧‧‧landing strip

7802‧‧‧Wv

7804‧‧‧Wy

7806‧‧‧Wx

7810‧‧‧Transistor isolation

7900‧‧‧Landing bar width increase

8000‧‧‧indoor wafer chip

8002‧‧‧General connectivity structure

8004‧‧‧non-repeating structure

8006‧‧‧Maximum donor wafer to acceptor wafer misalignment in the east-west direction (Mx)

8008‧‧‧Maximum donor wafer to acceptor wafer misalignment in the north-south direction (Mx)

8010‧‧‧Acceptor Wafer North-South Landing Strip

8011‧‧‧Donor Wafer East-West Landing Strip

8012‧‧‧through layer perforation

8100‧‧‧donor wafers

8102‧‧‧Donor wafer surface

8104‧‧‧Oxide

8106‧‧‧Oxide surface

8124‧‧‧Metal strip

8128‧‧‧Through hole

8130‧‧‧STI (shallow trench isolation) isolation

8136‧‧‧Oxide

8140‧‧‧Contact

8150‧‧‧Metal wire

8160‧‧‧Gate Oxide

8162‧‧‧Gate material

8170‧‧‧Completely depleted SOI transistor junction

8171‧‧‧Completely depleted SOI transistor junction

8202‧‧‧Dummy Gate Transistor

8206‧‧‧The first donor wafer

8208‧‧‧cleavage line

8216‧‧‧implantation

8218‧‧‧The second cleavage line

8226‧‧‧The second donor wafer

8232‧‧‧surface

8246‧‧‧implantation

8300‧‧‧donor wafers

8301‧‧‧Buried oxide (BOX)

8302‧‧‧thin silicon layer

8303‧‧‧Isolation between transistors

8304‧‧‧polysilicon

8305‧‧‧Gate oxide

8306‧‧‧NMOS source and drain

8307‧‧‧NMOS transistor channel

8308‧‧‧NMOS interlayer dielectric (ILD)

8310‧‧‧Atom class implantation

8312‧‧‧Cleavage surface

8314‧‧‧Donor wafer surface

8316‧‧‧Oxide layer

8320‧‧‧Carrier Wafer

8321‧‧‧Cleavage surface

8322‧‧‧surface

8333‧‧‧Isolation between transistors

8334‧‧‧polysilicon

8335‧‧‧Gate oxide

8336‧‧‧PMOS source and drain

8337‧‧‧PMOS transistor channel

8338‧‧‧PMOS interlayer dielectric (ILD)

8339‧‧‧dielectric layer

8340‧‧‧Atom class implantation

8341‧‧‧PMOS specific function metal gate

8342‧‧‧Aluminum filling

8343‧‧‧Gate contacts and metallization

8344‧‧‧Source and drain contacts and metallization

8347‧‧‧PMOS layer to NMOS layer through hole

8348‧‧‧Oxide layer

8350‧‧‧Metal landing strip

8360‧‧‧NMOS high-k gate dielectric

8361‧‧‧NMOS work-specific engineering metal gate

8362‧‧‧Aluminum filling

8363‧‧‧Gate contacts and metallization

8364‧‧‧Source and Drain Contacts and Metallization

8367‧‧‧NMOS layer to PMOS layer through hole

8369‧‧‧dielectric layer

8370‧‧‧dielectric layer

8372‧‧‧Through hole through layer to layer

83L00‧‧‧Repeated common unit

83L04‧‧‧NMOS Transistor

83L05‧‧‧Common Diffusion

83L02‧‧‧PMOS Transistor

83L10‧‧‧Transistor gate

83L12,83L20‧‧‧Perforation

83L06‧‧‧Vdd power cord

83L08‧‧‧diffusion connection

83L17‧‧‧General purpose metal structure facing down

83L14, 83L16, 83L18‧‧‧through hole

83L22,83L24‧‧‧NMOS transistor contacts

83L26‧‧‧Customer metal

83L25‧‧‧Vss power cord

8402‧‧‧Repeat logic pattern

8404‧‧‧block

8420‧‧‧SRAM unit

8422,8438,8452‧‧‧word line

8424,8426,8436,8462‧‧‧bit line

8430‧‧‧Consecutive array

8432‧‧‧storage module

8434‧‧‧etching unit

8450,8460‧‧‧logical structure

8468‧‧‧Read sensing circuit

8502‧‧‧Gate Oxide

8504‧‧‧Gate material

8506‧‧‧Gate stack

8508‧‧‧dielectric

8510‧‧‧local contacts

8512‧‧‧layer-to-layer contacts

8516‧‧‧Metallization

8520‧‧‧Oxide layer

8522‧‧‧Contact

8536‧‧‧Metal wire

8550‧‧‧Top Transistor

8552‧‧‧Top Transistor

8602‧‧‧logic layer

8612‧‧‧logic layer

8622‧‧‧logic layer

8632‧‧‧Repair logic layer

86C02‧‧‧Base Antenna

86C04‧‧‧RF to DC conversion circuit

86C06‧‧‧power supply unit

86C08‧‧‧Three-dimensional integrated circuits

86C10‧‧‧Solar Cell

86C12‧‧‧micro control unit

86C14‧‧‧radio module

8702‧‧‧Flip-Flop

8704‧‧‧normal output

8706‧‧‧branch

8708‧‧‧Repair input

8710‧‧‧Control

8712‧‧‧normal input

8714‧‧‧Multiplexer

8801‧‧‧P-type wafer

8802‧‧‧N+ floors

8803‧‧‧Hydrogen surface

8804‧‧‧Temporary carrier

8805‧‧‧Oxide

8806‧‧‧peripheral circuit

8807‧‧‧surface

8808‧‧‧Gate electrode

8809‧‧‧Gate dielectric

8810‧‧‧Oxide layer

8811‧‧‧First RCAT layer

8812‧‧‧Second RCAT layer

8813‧‧‧Highly doped polysilicon

8814‧‧‧Source line

8815‧‧‧bit line

8816‧‧‧Gate

8817‧‧‧P-layer

8818‧‧‧P-layer

8902‧‧‧Bit Line (BL)

8903‧‧‧Source Line (SL)

8904‧‧‧word line (WL)

8905‧‧‧Oxide isolation area

8906‧‧‧p-layer

8907‧‧‧WL

8908‧‧‧WL Wiring

8909‧‧‧SL Wiring 8909

8910‧‧‧BL Wiring

9001‧‧‧P-type wafer

9002‧‧‧n+ epitaxial layer

9003‧‧‧p-Epitaxial layer

9004‧‧‧Oxide layer

9005‧‧‧Hydrogen surface

9006‧‧‧peripheral circuit

9007‧‧‧Oxide

9008‧‧‧Gate electrode

9009‧‧‧Gate dielectric

9010‧‧‧Oxide layer

9011‧‧‧First RCAT layer

9012‧‧‧Second RCAT layer

9013‧‧‧Highly doped polysilicon

9014‧‧‧Source line

9015‧‧‧bit line

9016‧‧‧Gate electrode

9101‧‧‧SOI p-wafer

9102‧‧‧shallow trench isolation

9103‧‧‧Gate trench

9104‧‧‧Gate electrode

9105‧‧‧Gate dielectric layer

9106‧‧‧source and drain n+ regions

9107‧‧‧interlayer dielectric

9108‧‧‧P-type wafer

9109‧‧‧Oxide

9110‧‧‧Hydrogen surface

9113‧‧‧RCAT layer

9114‧‧‧RCAT layer

9115‧‧‧through hole

9116‧‧‧bit line BLs

9117‧‧‧source line SLs

9118‧‧‧peripheral circuit

9119‧‧‧Buried oxide layer

9201‧‧‧P-type wafer

9202‧‧‧Oxide layer

9203‧‧‧Hydrogen surface

9204‧‧‧peripheral circuit

9205‧‧‧Gate electrode

9206‧‧‧Oxide layer

9207‧‧‧Gate dielectric

9208‧‧‧source/drain region

9209‧‧‧Second PD-SOI transistor layer

9210‧‧‧Perforation

9211‧‧‧bit line

9212‧‧‧Source line

9213‧‧‧Transistor gate

9302‧‧‧The first wafer

9303‧‧‧circuit

9304‧‧‧Second Wafer

9305‧‧‧circuit

9306‧‧‧Thin Wafer

9310‧‧‧cleavage surface

9312‧‧‧thin layer

9322‧‧‧Bond structure

9402‧‧‧Metal landing strip

9403‧‧‧Unused possible rooms with additional metal bars

9406‧‧‧Length

9412‧‧‧landing strip

9413‧‧‧landing strip

9432‧‧‧A line perforation

9433‧‧‧B line perforation

9436‧‧‧through hole

9438‧‧‧Metal strip

9500‧‧‧P-substrate

9501‧‧‧Oxide

9502‧‧‧Oxide

9503‧‧‧N+ doped wafer size layer

9503'‧‧‧N+ floors

9504‧‧‧P-doped wafer size layer

9506‧‧‧P+ doped wafer size layer

9507‧‧‧Hydrogen Implantation

9508‧‧‧N-doped wafer size layer

9510‧‧‧Acceptor Wafer

9511‧‧‧Gate oxide

9512‧‧‧Gate oxide

9513‧‧‧N+ doped region

9514‧‧‧P-doped region

9516‧‧‧P+ doped region

9518‧‧‧N-doped region

9520‧‧‧Transistor isolation area

9526‧‧‧P+ source and drain regions

9528‧‧‧N-transistor channel region

9533‧‧‧N+ source and drain regions

9534‧‧‧P-transistor channel region

9542‧‧‧p-RCAT recessed channel

9544‧‧‧n-RCAT recessed channel

9550‧‧‧Oxide

9552‧‧‧Oxide

9554'‧‧‧p-RCAT gate electrode

9556'‧‧‧n-RCAT gate electrode

9562‧‧‧n-RCAT source contact

9564‧‧‧n-RCAT gate contact

9566‧‧‧n-RCAT drain contact

9572‧‧‧p-RCAT source contact

9574‧‧‧p-RCAT gate contact

9576‧‧‧p-RCAT drain contact

9599‧‧‧layer transfer division plane

9600‧‧‧donor wafers

9602‧‧‧N+ doped silicon layer

9604‧‧‧n+SiGe layer

9606‧‧‧N+ doped silicon layer

9608‧‧‧n+SiGe layer

9610‧‧‧Acceptor Wafer

9611‧‧‧Gate dielectric

9612‧‧‧Gate material

9613‧‧‧Oxide

9614‧‧‧Oxide

9616‧‧‧n+SiGe area

9618‧‧‧N+ Silicon District

9620‧‧‧Oxide

9622‧‧‧Oxide

9630‧‧‧Common gate area

9636‧‧‧Transistor gate channel

9699‧‧‧layer transfer division plane

9702‧‧‧Extra hole

9704‧‧‧Source

9706‧‧‧Gate

9708‧‧‧Drain

9710‧‧‧source

9712‧‧‧Gate

9714‧‧‧Drain

9716‧‧‧Buried oxide

9718‧‧‧Buried oxide

9720‧‧‧floating body area

9730‧‧‧Current differential

9734‧‧‧Drain current

9736‧‧‧Gate voltage

9800‧‧‧P-substrate

9801‧‧‧Oxide

9802‧‧‧Oxide

9804‧‧‧P-layer

9804'‧‧‧Remaining P-doped layer

9807‧‧‧Hydrogen Implantation

9810‧‧‧Acceptor Wafer

9820‧‧‧Transistor source and drain

9824‧‧‧Gate stack

9828‧‧‧NMOS transistor channel

9830‧‧‧Second Floor

9834‧‧‧Gate stack

9840‧‧‧Bit Line (BL) Contacts

9842‧‧‧Source Line (SL) Contact

9846‧‧‧Source Line (SL) Wiring

9848‧‧‧Bit line (BL) wiring

9850‧‧‧Oxide

9852‧‧‧N+ region on the source side of the transistor

9854‧‧‧N+ region on the drain side of the transistor

9864‧‧‧WL Wiring

9865‧‧‧SL wiring

9866‧‧‧BL Wiring

9899‧‧‧layer transfer division plane

9902‧‧‧Peripheral circuit substrate

9904‧‧‧Oxide

9906‧‧‧P-substrate

9906'‧‧‧remaining P-layer

9908‧‧‧Oxide

9910‧‧‧layer transfer division plane

9912‧‧‧donor wafer

9914‧‧‧Acceptor wafer

9916‧‧‧N+ Silicon District

9916'‧‧‧N+Silicon Area

9918‧‧‧p-Silicon District

9918'‧‧‧p-Silicon District

9920‧‧‧Oxide layer

9922‧‧‧First Si/SiO2 layer

9924‧‧‧Second silicon/silicon dioxide layer

9926‧‧‧Third Si/SiO2 layer

9928‧‧‧Gate dielectric region

9929‧‧‧Oxide layer

9930‧‧‧Gate electrode

9932‧‧‧Oxide

9934‧‧‧Bit Line (BL) Contacts

9936‧‧‧BL metal wire

9950‧‧‧word line area (WL)

9952‧‧‧Source line area (SL)

10002‧‧‧peripheral circuit substrate

10004‧‧‧Oxide

10006‧‧‧P-substrate

10006'‧‧‧remaining P-layer

10008‧‧‧Oxide

10010‧‧‧layer transfer division plane

10012‧‧‧donor wafer

10014‧‧‧Acceptor wafer

10016‧‧‧p-Silicon District

10017‧‧‧p-Silicon District

10020‧‧‧Oxide layer

10022‧‧‧Oxide

10023‧‧‧First Si/SiO2 layer

10025‧‧‧Second silicon/silicon dioxide layer

10026‧‧‧N+ Silicon District

10027‧‧‧Third Si/SiO2 layer

10028‧‧‧Gate Dielectric Region

10029‧‧‧Oxide layer

10030‧‧‧gate electrode

10032‧‧‧Oxide

10034‧‧‧Bit line (BL) contact

10036‧‧‧BL metal wire

10050‧‧‧word line area (WL)

10052‧‧‧Source line area (SL)

10102‧‧‧Peripheral circuit substrate

10104,10122,10132‧‧‧Oxide

10114‧‧‧Acceptor wafer

10112‧‧‧donor wafer

10106‧‧‧N+substrate

10110‧‧‧layer transfer division plane

10106'‧‧‧remaining N+ layers

10108,10120,10129‧‧‧Oxide layer

10123‧‧‧First Si/SiO2 layer

10125‧‧‧Second silicon/silicon dioxide layer

10127‧‧‧Third Si/SiO2 layer

10126‧‧‧N+Silicon District

10128‧‧‧Gate Dielectric Region

10130‧‧‧gate electrode

10150‧‧‧word line area (WL)

10152‧‧‧source line area (SL)

10134‧‧‧Bit line (BL) contact

10138‧‧‧Resistance change memory material

10136‧‧‧BL metal wire

10202‧‧‧Peripheral circuit substrate

10204‧‧‧Oxide

10206‧‧‧P-substrate

10206'‧‧‧P-layer

10208‧‧‧Oxide

10210‧‧‧layer transfer division plane

10212‧‧‧donor wafer

10214‧‧‧Acceptor wafer

10216‧‧‧p-Silicon District

10217‧‧‧p-Silicon District

10220‧‧‧Oxide layer

10222‧‧‧Oxidation zone

10223‧‧‧First Si/SiO2 layer

10225‧‧‧Second silicon/silicon dioxide layer

10226‧‧‧N+ Silicon District

10227‧‧‧Third Si/SiO2 layer

10228‧‧‧Gate Dielectric Region

10229‧‧‧Oxide layer

10230‧‧‧Gate electrode

10232‧‧‧Oxide

10234‧‧‧Bit line (BL) contact

10236‧‧‧BL metal wire

10238‧‧‧Resistance changing material

10250‧‧‧word line area (WL)

10252‧‧‧Source line area (SL)

10302‧‧‧Peripheral circuit substrate

10304‧‧‧Oxide

10306‧‧‧P-substrate

10306'‧‧‧P-layer

10308‧‧‧Oxide

10310‧‧‧layer transfer division plane

10312‧‧‧donor wafer

10314‧‧‧Acceptor wafer

10316‧‧‧N+ Silicon District

10316'‧‧‧N+Silicon Area

10318‧‧‧p-Silicon District

10318'‧‧‧p-Silicon District

10320‧‧‧Oxide layer

10322‧‧‧Oxidation zone

10323‧‧‧The first Si/SiO2 layer

10325‧‧‧Second silicon/silicon dioxide layer

10326‧‧‧N+ Silicon District

10327‧‧‧Third Si/SiO2 layer

10328‧‧‧Gate Dielectric Region

10329‧‧‧Oxide layer

10330‧‧‧Gate electrode

10332‧‧‧Oxide

10334‧‧‧Bit line (BL) contact

10336‧‧‧BL metal wire

10338‧‧‧Resistance changing material

10350‧‧‧word line area (WL)

10352‧‧‧Source line area (SL)

10400‧‧‧donor wafer

10401‧‧‧Oxide

10402‧‧‧Oxide

10404‧‧‧P-layer

10404'‧‧‧P-doped layer

10407‧‧‧Hydrogen Implantation

10410‧‧‧Acceptor wafer

10420‧‧‧Transistor source and drain

10424‧‧‧Gate stack

10428‧‧‧P-Silicon NMOS transistor channel

10430‧‧‧Storage transistor second layer

10434‧‧‧Source Line (SL) Contact

10440‧‧‧Bit line (BL) contact

10442‧‧‧Resistance change memory material

10446‧‧‧Source line (SL) wiring

10448‧‧‧Bit line (BL) wiring

10450‧‧‧Oxide

10452‧‧‧N+ region on the source side of the transistor

10454‧‧‧N+ region on the drain side of the transistor

10499‧‧‧layer transfer division plane

10500‧‧‧donor wafers

10501‧‧‧Oxide

10502‧‧‧Oxide

10504‧‧‧P-doped layer

10504'‧‧‧P-doped layer

10507‧‧‧Hydrogen Implantation

10510‧‧‧Acceptor Wafer

10520‧‧‧P-doped region

10522‧‧‧Charge Trapping Gate Dielectric

10524‧‧‧Gate metal material

10528‧‧‧Gate stack

10530‧‧‧NAND String Source and Drain Terminations

10534‧‧‧Intertransistor source and drain

10542‧‧‧The first layer of storage transistor

10544‧‧‧Storage transistor second layer

10548‧‧‧Source Line (SL) Ground Contact

10549‧‧‧Bit line contact

10550‧‧‧Oxide

10599‧‧‧layer transfer division plane

10602‧‧‧Peripheral circuit substrate

10604‧‧‧Oxide

10606‧‧‧N+substrate

10606'‧‧‧N+ floors

10608‧‧‧Oxide

10610‧‧‧layer transfer division plane

10612‧‧‧donor wafer

10614‧‧‧Acceptor Wafer

10620‧‧‧Oxide layer

10622‧‧‧Oxidation zone

10623‧‧‧First Si/SiO2 layer

10625‧‧‧Second silicon/silicon dioxide layer

10626‧‧‧N+Silicon District

10627‧‧‧Third Si/SiO2 layer

10628‧‧‧Gate Dielectric Region

10629‧‧‧Oxide

10630‧‧‧Gate metal electrode area

10632‧‧‧Oxide

10634‧‧‧Select gate contact

10636‧‧‧NAND serial area

10638‧‧‧select gate area

10644‧‧‧source region

10646‧‧‧Select metal wire

10652‧‧‧Bit line area (BL)

10700‧‧‧donor wafer

10701‧‧‧Oxide

10702‧‧‧Oxide

10704‧‧‧P-doped layer

10704'‧‧‧P-doped layer

10707‧‧‧Hydrogen Implantation

10710‧‧‧Acceptor wafer

10720‧‧‧P-doped region

10722‧‧‧Tunnel oxide

10722'‧‧‧Tunnel oxide area

10724‧‧‧FG gate metal material

10724'‧‧‧FG gate metal area

10725‧‧‧Oxide layer between polysilicon

10725'‧‧‧Inter-polysilicon oxide region

10726‧‧‧Control grid (CG) gate metal material

10726'‧‧‧CG gate metal area

10728‧‧‧Gate stack

10730‧‧‧NAND string source and drain termination

10734‧‧‧Intertransistor source and drain

10742‧‧‧The first layer of storage transistor

10744‧‧‧Second layer of storage transistor

10748‧‧‧Ground contact for source line (SL)

10749‧‧‧Bit line contact

10750‧‧‧Oxide

10799‧‧‧layer transfer division plane

10802‧‧‧peripheral circuit substrate

10804‧‧‧Oxide

10806‧‧‧N+substrate

10806'‧‧‧N+ floors

10808‧‧‧Oxide

10810‧‧‧layer transfer division plane

10812‧‧‧donor wafer

10814‧‧‧Acceptor Wafer

10816‧‧‧N+ area

10818‧‧‧Tunnel dielectric

10823‧‧‧First storage layer

10825‧‧‧Second storage layer

10828‧‧‧FG District

10829‧‧‧Oxide layer

10829'‧‧‧thin oxide layer

10838‧‧‧FG District

10850‧‧‧Oxide layer between polysilicon

10852‧‧‧Control grid (CG) gate material

10902‧‧‧Peripheral circuit substrate

10904‧‧‧Oxide

10906‧‧‧N+ doped polysilicon or amorphous layer

10908‧‧‧Oxide layer

10916‧‧‧Crystalline N+ silicon layer

10920‧‧‧Silicon oxide layer

10922‧‧‧Oxidation zone

10923‧‧‧The first Si/SiO2 layer

10925‧‧‧Second silicon/silicon dioxide layer

10926‧‧‧Crystalline N+ silicon region

10927‧‧‧Third Si/SiO2 layer

10928‧‧‧Gate Dielectric Region

10929‧‧‧Oxide

10930‧‧‧Gate electrode

10932‧‧‧Oxide

10934‧‧‧Bit line (BL) contact

10936‧‧‧BL metal wire

10938‧‧‧Resistance change memory material

10950‧‧‧word line area (WL)

10952‧‧‧Source line area (SL)

11002‧‧‧Silicon substrate

11004‧‧‧Oxide layer

11006‧‧‧N+ doped amorphous silicon or polysilicon layer

11016‧‧‧Crystalline N+ silicon layer

11020‧‧‧Oxide layer

11022‧‧‧Oxidation zone

11023‧‧‧First Si/SiO2 layer

11025‧‧‧Second silicon/silicon dioxide layer

11026‧‧‧Crystalline N+ silicon region

11027‧‧‧The third Si/SiO2 layer

11028‧‧‧Gate Dielectric Region

11029‧‧‧Oxide layer

11030‧‧‧gate electrode

11032‧‧‧Oxide

11034‧‧‧Bit line (BL) contact

11036‧‧‧BL metal wire

11038‧‧‧Resistance change memory material

11050‧‧‧word line area (WL)

11052‧‧‧source line area (SL)

11078‧‧‧peripheral circuit

11100‧‧‧donor wafer

11100'‧‧‧donor wafer portion

11101‧‧‧Bond surface

11102‧‧‧floor

11110‧‧‧Acceptor wafer

11111‧‧‧Bond surface

11130‧‧‧Alignment window

11130'‧‧‧alignment window

11131‧‧‧Align the window area

11150‧‧‧Donor Wafer Equipment Structure

11160‧‧‧Through Layer Via (TLVS)

11180‧‧‧Metal connection chips or strips

11190‧‧‧Acceptor wafer alignment mark

11199‧‧‧layer transfer division plane

11201‧‧‧Interconnect metallization layer

11202‧‧‧base

11203‧‧‧thin silicon dioxide layer

11204‧‧‧Oxide layer

11205‧‧‧Hot layer

11206‧‧‧Donor wafer substrate

11206'‧‧‧remaining transfer layer

11207‧‧‧Masking Oxide

11212‧‧‧donor wafer

11214‧‧‧Acceptor wafer

11299‧‧‧layer transfer division plane

11300‧‧‧Printed wiring board

11302‧‧‧Transistor bottom layer

11304‧‧‧Through layer power and ground vias

11305‧‧‧Non-conductive heat spreader

11306‧‧‧Transistor top layer power supply and ground grid

11307‧‧‧Transistor bottom power supply and grounding grid

11310‧‧‧bonded oxides

11312‧‧‧Transistor top layer

11325‧‧‧Packaging heat spreader

11330‧‧‧radiator

11360‧‧‧Side wall heat conductor

11401‧‧‧logic layer

11402‧‧‧logic layer

11405‧‧‧Vertical connection

11406‧‧‧Vertical connection

11411‧‧‧Logic cone

11412‧‧‧Logic cone

11421‧‧‧Flip-Flop

11422‧‧‧Flip-Flop

11431‧‧‧Multiplexer

11432‧‧‧Multiplexer

11441‧‧‧Control point

11442‧‧‧Control Point

11451‧‧‧BIST Controller/Detector

11452‧‧‧BIST Controller/Detector

11501‧‧‧floor

11502‧‧‧floor

11503‧‧‧floor

11511-1‧‧‧Logic Cone

11511-2‧‧‧Logic Cone

11511-3‧‧‧Logic Cone

11521-1‧‧‧Flip-Flop

11521-2‧‧‧Flip-Flop

11521-3‧‧‧Flip-Flop

11531‧‧‧majority voting circuit

11541-1‧‧‧Final fault-tolerant FF output

11541-2‧‧‧Final fault-tolerant FF output

11541-3‧‧‧Final fault-tolerant FF output

11551‧‧‧local FF output

11552‧‧‧FF output value

11553‧‧‧FF output value

11600‧‧‧Two-dimensional integrated circuit ASIC

11610‧‧‧Scan Test Controller

11612‧‧‧Multiple triggers

11614‧‧‧Multiple triggers

11616‧‧‧Multiple triggers

11620‧‧‧Logic cloud

11622‧‧‧Logic cloud

11624‧‧‧Logic cloud

11626‧‧‧Logic cloud

11630‧‧‧Input chip

11640‧‧‧Output chip

11700‧‧‧ASIC

11710‧‧‧In the logic function module

11720‧‧‧Input/Output Unit

11722‧‧‧Bond wafer

11724‧‧‧Input buffer

11726‧‧‧Three-state output buffer

11730‧‧‧Scanning test control module

11732‧‧‧Boundary scan register chain

11734‧‧‧Boundary scan register chain

11800‧‧‧logic module

11810‧‧‧chip function

11812‧‧‧Input value

11814‧‧‧output value

11820‧‧‧BIST controller

11822‧‧‧Linear Feedback Shift Register (LFSR)

11824‧‧‧Cyclic redundancy check circuit

11900‧‧‧Three-dimensional integrated circuits

11910‧‧‧Control logic

11911‧‧‧Scan trigger

11912‧‧‧Scan trigger

11913‧‧‧Scan trigger

11914‧‧‧combinational logic cloud

11915‧‧‧combinational logic cloud

11920‧‧‧Control logic

11921‧‧‧Scan trigger

11922‧‧‧Scan trigger

11923‧‧‧Scan trigger

11924‧‧‧Logic cloud

11925‧‧‧Logic cloud

12000‧‧‧Sweep Flip-Flops

12002‧‧‧D type flip-flop

12004‧‧‧Multiplexer

12006‧‧‧Multiplexer

12100‧‧‧Three-dimensional integrated circuits

12110‧‧‧Level 1 Logic Cone

12112‧‧‧Scan trigger

12114‧‧‧XOR gate

12120‧‧‧Level 2 Logic Cone

12122‧‧‧Scan trigger

12124‧‧‧XOR gate

12170‧‧‧LAYER_SEL door latch

12172‧‧‧ERROR2 line

12174‧‧‧COL_ADDR line

12176‧‧‧ROW_ADDR line

12178‧‧‧COL_BIT line

12182‧‧‧N-type channel transistor

12184‧‧‧N-type channel transistor

12186‧‧‧N-type channel transistor

12188‧‧‧Line

12190‧‧‧P-type channel transistor

12192‧‧‧P-type channel transistor

12200‧‧‧Logic function block (LFB)

12202‧‧‧Input

12204‧‧‧Output

12210‧‧‧Small logic function module

12212‧‧‧Linear feedback shift register circuit

12214‧‧‧cyclic redundancy check circuit

12216‧‧‧Logic function

12220‧‧‧Small logic function module

12230‧‧‧Linear Feedback Shift Register (LFSR) Circuit

12232‧‧‧cyclic redundancy check circuit

12300‧‧‧Three-dimensional integrated circuits

12310‧‧‧Control logic module

12311‧‧‧Scan trigger

12312‧‧‧Scan trigger

12313‧‧‧Multiplexer

12314‧‧‧Multiplexer

12315‧‧‧Logic cone

12320‧‧‧Control logic module

12321‧‧‧Scan trigger

12322‧‧‧Scan trigger

12323‧‧‧Multiplexer

12324‧‧‧Multiplexer

12325‧‧‧Logic Cone

12400‧‧‧Three-dimensional integrated circuits

12410‧‧‧Level 1 Logic Cone

12412‧‧‧Scan trigger

12414‧‧‧Multiplexer

12416‧‧‧XOR gate

12420‧‧‧Level 2 Logic Cone

12422‧‧‧Scan trigger

12424‧‧‧Multiplexer

12426‧‧‧XOR gate

12500‧‧‧Three-dimensional integrated circuits

12510,12520‧‧‧Logic function block (LFB)

12522,12524‧‧‧Multiplexer

12530‧‧‧Power Selection Multiplexer

12600‧‧‧Three-dimensional integrated circuits

12610‧‧‧Interconnection wire

12612‧‧‧Interconnection wire

12620‧‧‧Level 2 Logic Cone

12622‧‧‧Scan trigger

12624‧‧‧Multiplexer

12626‧‧‧XOR gate

12628‧‧‧RS flip-flop

12630‧‧‧Reset Line 2

12632‧‧‧or grid

12634‧‧‧2nd layer OR-chain input line

12636‧‧‧2nd layer OR-chain output line

12638‧‧‧N-type channel transistor

12640‧‧‧N-type channel transistor

12642‧‧‧N-type channel transistor

12644‧‧‧Induction

12646‧‧‧and grid

12648‧‧‧TEST_EN line

12700‧‧‧Three-dimensional integrated circuits

12710‧‧‧Level 1 Logic Cone

12714‧‧‧Flip-Flop

12716‧‧‧Majority of Three (MAJ3) Gate

12720‧‧‧Level 2 Logic Cone

12724‧‧‧Flip-Flop

12726‧‧‧Majority of Three (MAJ3) Gate

12730‧‧‧Level 3 Logic Cone

12734‧‧‧Flip-Flop

12736‧‧‧Majority of Three (MAJ3) Gate

12800‧‧‧Three-dimensional integrated circuits

12810‧‧‧Level 1 Logic Cone

12812‧‧‧Majority of Three (MAJ3) Gate

12814‧‧‧Flip-Flop

12820‧‧‧Level 2 Logic Cone

12822‧‧‧Majority of Three (MAJ3) Gate

12824‧‧‧Flip-Flop

12830‧‧‧Level 3 Logic Cone

12832‧‧‧Majority of Three (MAJ3) Gate

12834‧‧‧Flip-Flop

12900‧‧‧Three-dimensional integrated circuits

12910‧‧‧Level 1 Logic Cone

12912‧‧‧Majority of three (MAJ3) grid

12914‧‧‧Flip-Flop

12916‧‧‧Majority of three (MAJ3) grid

12920‧‧‧Level 2 Logic Cone

12922‧‧‧Majority of Three (MAJ3) Gate

12924‧‧‧Flip-Flop

12926‧‧‧Majority of Three (MAJ3) Gate

12930‧‧‧Level 3 Logic Cone

12932‧‧‧Majority of Three (MAJ3) Gate

12934‧‧‧Trigger

12936‧‧‧Majority of Three (MAJ3) Gate

13000‧‧‧perforation patterns

13002‧‧‧Perforated Metal Laminated Chip

13004‧‧‧Perforated Metal Laminated Chip

13006‧‧‧Perforated Metal Laminated Chip

13008‧‧‧Perforated Metal Laminated Chip

13010‧‧‧Perforated pattern

13012‧‧‧Perforated Metal Laminated Chip

13014‧‧‧Perforated Metal Laminated Chip

13016‧‧‧Perforated Metal Laminated Chip

13018‧‧‧Perforated Metal Laminated Chip

13020‧‧‧Three-dimensional integrated circuits

13030‧‧‧floor

13031‧‧‧Transistor

13032‧‧‧Contact

13033‧‧‧Metal 1

13034‧‧‧Perforation 1

13035‧‧‧Metal 2

13036‧‧‧Perforation 2

13037‧‧‧Metal 3

13040‧‧‧through-silicon via

13100‧‧‧Perforated pattern

13102‧‧‧Perforated Metal Laminated Chip

13104‧‧‧Perforated Metal Laminated Chip

13106‧‧‧Perforated Metal Laminated Chip

13110‧‧‧Perforated pattern

13112‧‧‧Perforated Metal Laminated Chip

13114‧‧‧Perforated Metal Laminated Chip

13116‧‧‧Perforated Metal Laminated Chip

13200‧‧‧Perforated pattern

13202‧‧‧Perforated Metal Laminated Chip

13204‧‧‧Perforated Metal Laminated Chip

13206‧‧‧Perforated Metal Laminated Chip

13208‧‧‧Perforated Metal Laminated Chip

13210‧‧‧Perforated Metal Laminated Chip

13212‧‧‧Perforated Metal Laminated Chip

13214‧‧‧Perforated Metal Laminated Chip

13216‧‧‧Perforated Metal Laminated Chip

13218‧‧‧Perforated Metal Laminated Chip

13220‧‧‧Three-dimensional integrated circuits

13230‧‧‧Interconnect layer

13232‧‧‧Interconnect layer

13240‧‧‧Interconnect layer

13242‧‧‧Interconnect layer

13250‧‧‧Interconnect layer

13252‧‧‧Interconnect layer

13301‧‧‧P-doped layer

13302‧‧‧P-substrate donor wafer

13304‧‧‧N+ doped layer

13306‧‧‧Metal silicide layer

13308‧‧‧Oxide layer

13310‧‧‧Acceptor substrate or wafer

13312‧‧‧Carrier or carrier substrate

13314‧‧‧Adhesive layer

13316‧‧‧P-layer

13318‧‧‧Oxide layer

13322‧‧‧Transistor isolation area

13323‧‧‧Concave channel

13324‧‧‧Oxidation zone

13326‧‧‧Metal silicide source and drain regions

13328‧‧‧N+ source and drain regions

13330‧‧‧P-type channel region

13332‧‧‧Gate dielectric

13334‧‧‧Gate electrode

13336‧‧‧Source and drain contacts

13338‧‧‧thick oxide

13342‧‧‧Gate contact

13399‧‧‧layer transfer division plane

13400‧‧‧Acceptor Wafer

13400A‧‧‧Acceptor substrate with channel transistor

13400B‧‧‧Acceptor substrate with channel transistor and memory element

13402‧‧‧donor wafer

13402'‧‧‧channel transistor layer

13404‧‧‧memory element donor wafer

13404'‧‧‧memory element layer

13410‧‧‧Through Layer Via (TLVS)

13410A‧‧‧through layer perforation

13410B‧‧‧through layer perforation

13420‧‧‧Storage to switch through layer through hole

13430‧‧‧Storage to acceptor pass-through layer perforation

13440‧‧‧memory element

13442‧‧‧Channel Transistor Gate

13444‧‧‧Channel transistor source

13445‧‧‧Channel transistor drain

13446‧‧‧FPGA configuration network metal wire

13447‧‧‧FPGA configuration network metal wire

13500‧‧‧Acceptor Wafer

13500A‧‧‧Acceptor substrate with channel transistor and memory element

13502‧‧‧donor wafer

13502'‧‧‧Channel transistor and storage layer

13510‧‧‧Through Layer Via (TLVs)

13510A‧‧‧through layer perforation

13510B‧‧‧through layer perforation

13525‧‧‧Channel transistor and storage layer interconnection metallization

13540‧‧‧memory element

13542‧‧‧Channel Transistor Gate

13544‧‧‧Channel transistor source

13545‧‧‧Channel transistor drain

13546‧‧‧FPGA configuration network metal wire

13547‧‧‧FPGA configuration network metal wire

13602‧‧‧Control grid

13604‧‧‧Floating gate

13610‧‧‧Switching transistor channel

13612‧‧‧Switching transistor source

13614‧‧‧Switching transistor drain

13620‧‧‧Sense Transistor Channel

13622‧‧‧Sensing Transistor Source

13624‧‧‧Sense Transistor Drain

13700‧‧‧donor wafers

13701‧‧‧Masking Oxide

13702‧‧‧Oxide

13704‧‧‧N+ doped layer

13704'‧‧‧residual highly doped layer

13706‧‧‧P-doped layer

13707‧‧‧Hydrogen Implantation

13710‧‧‧Acceptor wafer

13711‧‧‧Tunnel dielectric

13714‧‧‧Tunnel dielectric

13715‧‧‧High N+ doping in the southeast transistor area in the future

13716‧‧‧Southwest transistor channel area

13717‧‧‧Southeast transistor channel area

13720‧‧‧Transistor isolation area

13721‧‧‧Southwest to Southeast Isolation Area

13724‧‧‧Southwest source and drain regions

13725‧‧‧Southeast source and drain regions

13741‧‧‧polysilicon interlayer dielectric body

13742‧‧‧Southwest Sag Channel

13743‧‧‧Southeast Sag Channel

13752‧‧‧Floating gate

13754‧‧‧Control grid

13799‧‧‧layer transfer division plane

Combining the pictures and the detailed description below, readers can have a more in-depth understanding of different cases in this invention.

FIG. 1 is a schematic circuit diagram of the prior art.

FIG. 2 is a partial cross-sectional view of the prior art circuit diagram in FIG. 1 .

FIG. 3A is a schematic diagram of a programmable interconnection circuit structure.

Figure 3B is a schematic diagram of a programmable interconnection circuit structure; Figure 4A is a schematic diagram of a programmable interconnection circuit board; Figure 4B is a schematic diagram of a 2x2 programmable interconnection circuit board; Figure 5A is a schematic diagram of an inverter logic chip; Figure 5B is a buffer A schematic diagram of a logic chip; Figure 5C is a schematic diagram of a buffer logic chip with adjustable strength; Figure 5D is a schematic diagram of a D-trigger logic chip; Figure 6 is a schematic diagram of a LUT4 logic chip; Figure 6A is a schematic diagram of a PLA logic chip; Figure 7 It is a schematic diagram of a programmable chip; FIG. 8 is a schematic diagram of a programmable component layer structure; FIG. 8A is a schematic diagram of a multilayer structure of a programmable component; An IC system using existing through-silicon via (TSV) technology.

FIG. 10A is a schematic diagram of a continuous array wafer manufactured in the prior art.

FIG. 10B is a partial schematic diagram of a continuous array wafer manufactured in the prior art.

FIG. 10C is a partial schematic diagram of a continuous array wafer fabricated in the prior art.

11A-11F are schematic diagrams of actual masks on a wafer.

12A-12E are schematic diagrams of a configurable system; FIG. 13 is a schematic diagram of a 3D logical partition process; FIG. 14 is a schematic diagram of a layer removal process; FIG. 15 is a schematic diagram of a bottom programming circuit; FIG. 16 is a schematic diagram of a bottom isolation transistor circuit; Figure 17A is a topological schematic diagram of the bottom reverse bias circuit; Figure 17B is a schematic diagram of the bottom reverse bias circuit; Figure 17C is a schematic diagram of the power control circuit; Figure 17D is a schematic diagram of the probe circuit; Figure 18 is a schematic diagram of the bottom SRAM ; Figure 19A is a schematic diagram of bottom I/O; Figure 19B is a schematic diagram of edge "cutting"; Figure 19C is a schematic diagram of a 3D IC system; Figure 19D is a schematic diagram of a 3D IC processor and DRAM system; Figure 19E is a 3D IC processor and a schematic diagram of a DRAM system; FIG. 19F is a schematic diagram of using a custom SOI wafer to construct a through-silicon connection.

FIG. 19G is a schematic diagram of manufacturing straight through-silicon vias (TSVs) using the prior art.

Figure 19H is a schematic diagram of the process of manufacturing a custom SOI wafer; Figure 19I is a schematic diagram of a processor-DRAM stack; Figure 19J is a schematic diagram of the process of fabricating a custom SOI wafer; Figure 20 is a schematic diagram of the layer removal process; Figure 21B is a schematic diagram of a pre-processed wafer capable of layer removal; Figures 22A-22H are schematic diagrams of surface planar transistor formation; Figures 23A and 23B are schematic diagrams of layer removal using a pre-processed wafer ; Figure 24A-24F is a schematic diagram of surface plane transistor formation; Figure 25A, 25B is a schematic diagram of layer excision using a pretreated wafer; Figure 26A-26E is a schematic diagram of surface plane transistor formation; Figure 28A-28E is a schematic diagram of surface transistor formation; Figure 29A-29G is a schematic diagram of surface plane transistor formation; Figure 30 is a schematic diagram of an electron supply wafer; Figure 31 is the cut layer on the main wafer Schematic diagram; Fig. 32 is a schematic diagram of measuring alignment deviation; Fig. 33A, 33B are schematic diagrams of connection strips; Fig. 34A-34E are schematic diagrams of layer removal of multiple pre-processed wafers; Fig. 35A-35G are schematic diagrams of forming surface plane transistors; Figure 36 is a schematic diagram of a panel array wafer; Figure 37 is a schematic diagram of a programmable terminal component; Figure 38 is a schematic diagram of the adjusted JTAG connection; Figures 39A-39C are schematic diagrams of a pre-processed wafer used to manufacture vertical transistors; Figure 40A -40I is a schematic diagram of a vertical n-MOSFET surface transistor; Figure 41 is a schematic diagram of a 3D IC system with redundancy; Figure 42 is a schematic diagram of an inverter chip; Figure 43A-C is a schematic diagram of the preparation steps for 3D chip molding; 44A-F is a schematic diagram of 3D chip molding steps; Figure 45A-G is a schematic diagram of 3D chip molding steps; Figure 46A-C is a schematic cross-sectional view of a layer of 3D inverter chips; Figure 47 is a schematic diagram of 2 input NOR chips; 48A-C is a schematic cross-sectional diagram of a 3D 2-input NOR chip; Figure 49A-C is a schematic diagram of a 2-input NOR 3D chip; Figure 50A-D is a schematic diagram of a 3D CMOS transmission chip; Figure 51A-D is a schematic diagram of a 3D CMOS SRAM chip ; Figures 52A and 52B are simulation diagrams of the components of the jointless transistor; Figure 53A-E is a schematic diagram of a 3D CAM chip; Figure 54A-C is a schematic diagram of the forming of the jointless transistor; Schematic diagram; Figure 56A-M is a schematic diagram of forming a jointless transistor; Figure 57A-G is a schematic diagram of forming a jointless transistor; Figure 58A-G is a schematic diagram of forming a jointless transistor; Figure 59 is a metal interconnection stack of the prior art Schematic diagram; Figure 60 is a schematic diagram of a metal interconnect stack; Figure 61A-I is a schematic diagram of a junctionless transistor; Figure 62A-D is a schematic diagram of a 3D NAND2 chip; Figure 63A-G is a schematic diagram of a 3D NAND8 chip; Figure 64A -G is a schematic diagram of a 3D NOR8 chip; Figure 65A-C is a schematic diagram of forming a junctionless transistor; Figure 66 is a schematic diagram of a groove channel array transistor; Figure 67A-F is a schematic diagram of forming a groove channel array transistor; 68A-F is a schematic diagram of forming a spherical groove channel array transistor; FIG. 69 is a schematic diagram of an electron supply wafer; FIG. 70A, B, B-1 and C-H are schematic diagrams of the formation of a surface plane transistor; FIG. A schematic diagram of a circle; Figure 72A-F is a schematic diagram of surface plane transistor formation; Figure 73 is a schematic diagram of an electron supply wafer; Figure 74 is a schematic diagram of measuring alignment deviation; Figure 75 is a schematic diagram of a connection strip; Figure 76 is a schematic diagram of an electron supply wafer Fig. 77 is a schematic diagram of connecting strips; Fig. 78A, 78B, and 78C are schematic diagrams of a layer of electron supply wafer; Fig. 79 is a schematic diagram of connecting strips; Fig. 80 is a schematic diagram of connecting strip array structure; Fig. 81A-81F-2 Figure 82A-G is a schematic diagram of forming a surface plane transistor; Figure 83A-L is a schematic diagram of forming a surface plane transistor; Figure 83L1-L4 is a schematic diagram of forming a surface plane transistor; Figure 84A-G is a continuous Schematic diagram of transistor array; Figure 85A-E is a schematic diagram of surface plane transistor formation; Figure 86A is a schematic diagram of a 3D logic IC structure for maintenance; Figure 86B is a schematic diagram of a single-layer scan chain 3D IC; Figure 86C is a schematic diagram of non-contact testing; Figure 87 is a schematic diagram of a flip-flop of a repairable 3D IC logic device; Figure 88A-F is a schematic diagram of the formation of a 3D DRAM; Figure 89A-D is a schematic diagram of the formation of a 3D DRAM; Figure 90A-F is a schematic diagram of the formation of a 3D DRAM; L is a schematic diagram of the formation of 3D DRAM; Figure 92A-F is a schematic diagram of the formation of 3D DRAM; Figure 93A-D is a schematic diagram of the advanced TSV process; Figure 94A-C is a schematic diagram of the advanced multi-connection TSV process; Figure 95A-J is a schematic diagram of CMOS concave Schematic diagram of forming a slot channel array transistor; Figure 96A-J is a schematic diagram of forming a junctionless transistor; Figure 97 is a schematic diagram of a basic floating body DRAM; Figure 98A-H is a schematic diagram of forming a floating body DRAM transistor; Figure 99A-M It is a schematic diagram of forming a floating body DRAM transistor; Figure 100A-L is a schematic diagram of forming a floating body DRAM transistor; Figure 101A-K is a schematic diagram of forming a resistive storage transistor; Figure 102A-L is a forming schematic diagram of a resistive storage transistor Schematic diagram; Figure 103A-M is a schematic diagram of forming a resistive storage transistor; Figure 104A-F is a schematic diagram of forming a resistive storage transistor; Figure 105A-G is a schematic diagram of forming a charge-trapping transistor; Figure 106A-G is a schematic diagram of a charge Figure 107A-G is a schematic diagram of forming a floating gate storage transistor; Figure 108A-H is a schematic diagram of forming a floating gate storage transistor; Figure 109A-K is a schematic diagram of forming a resistive storage transistor; Figure 110A- J is a schematic diagram of forming a resistive storage transistor with an upper edge; Figure 111A-D is a schematic diagram of a general layer removal process and a case of its window; Figure 112 is a schematic diagram of a 3D IC system with a heat sink; Figure 113A-B It is a schematic diagram of a 3D-IC integrated heat removal device; Figure 114 is a schematic diagram of a field-repairable 3D IC system; Figure 115 is a schematic diagram of a 3-mode redundant 3D IC system; Figure 116 is a schematic diagram of a group scanning architecture in the prior art; Figure 117 FIG. 118 is a schematic diagram of a prior art BIST architecture; FIG. 119 is a schematic diagram of another field-repairable 3D IC system; FIG. 120 is a schematic diagram of a scan flip-flop that can be used for the 3D IC shown in FIG. 119 ; Figure 121A is a schematic diagram of the third field repairable 3D IC system; Figure 121B is the other side of the field repairable 3D IC system in Figure 121A; Figure 122 is a schematic diagram of the fourth field repairable 3D IC system; Figure 123 is Figure 124 is a schematic diagram of the sixth field repairable 3D IC system; Figure 125A is a schematic diagram of the seventh field repairable 3D IC system; Figure 125B is a schematic diagram of the field repairable 3D IC system in Figure 125A The other side of the repairable 3D IC system; Figure 126 is a schematic diagram of the eighth field repairable 3D IC system; Figure 127 is a schematic diagram of the second 3-mode redundant 3D IC system; Figure 128 is the third 3-mode redundant A schematic diagram of the remaining 3D IC system; Figure 129 is a schematic diagram of the fourth 3-mode redundant 3D IC system; Figure 130A is a schematic diagram of the first via technology overlapping method; Figure 130B is a schematic diagram of the second via technology overlapping method Schematic diagram; FIG. 130C is a schematic diagram of the alignment of via technology overlapping methods of field repairable 3D ICs in FIGS. 130A and 130B; FIG. 130D is a side view of the structure in FIG. 130C; FIG. 131A is a schematic diagram of the third via technology overlapping method; Figure 131B is a schematic diagram of the fourth via technology overlapping method; Figure 131C is a schematic diagram of the alignment of the via technology overlapping methods in Figures 131A, 131B and 131C; Figure 132A is a schematic diagram of the fifth via technology overlapping method; Figure 132B is Figure 132A is a schematic diagram of the alignment of the 3D IC via metal overlapping method; Figure 133A-I is a schematic diagram of the formation of a trench channel array transistor with source and drain silicide; Figure 134A-F is a 3D IC FPGA processor Schematic diagram of the process; Figure 135A-D is a schematic diagram of the process flow of an alternative 3D IC FPGA processor; Figure 136 is a schematic diagram of the NVM FPGA setting chip; Figure 137A-G is a schematic diagram of the processing flow of the 3D IC NVM FPGA setting chip.

Hereinafter, examples of the present invention will be described with reference to the drawings. Usually a person with only basic knowledge in the field would like the description and drawings to explain the invention rather than limit the understanding of the invention, and the drawings need not be enlarged for greater clarity. At the same time, people will also realize that by applying the principles of this invention, more cases can be created, and these cases will all belong to the scope of protection of this invention patent, unless otherwise stated in the attached patent statement.

FIG. 1 is a schematic circuit diagram of the prior art. For example, 860-1 to 860-4 are programmable transistors for programming 850-1, 1.

FIG. 2 is a partial cross-sectional view of the prior art circuit diagram in FIG. 1. The programming transistor 860-1 is embedded as part of the silicon substrate.

FIG. 3A is a schematic diagram of a programmable connection board. 310-1 is one of 4 horizontal metal strips that make up the parallel strips. Today, typical ICs have multiple metal layers. In a typical programmable component, the first two or three metal layers can be used to build the logic component. On top of them, metal layers 4-7 are used to build the routing circuits for logic components. In an FPGA device, the logic elements are programmable, as are the wiring circuits between the logic elements. The configurable wiring circuit of the present invention is constructed from the 4th metal layer or above. For example, metal layers 4 and 5 can be used as long splice strips, and metal layers 6 and 7 can be used as short splice strips. Usually, the plug strips constitute a programmable wiring circuit, have the same long height and extension direction, just like 310-1, 310-2, 310-3, 310-4, constitute parallel plug strips. Usually a band contains 10-40 splice strips. Usually, the plug bars of the subsequent layers extend vertically, as shown in FIG. 3A , the plug bars 310 of the metal layer 6 and the plug bars 308 of the metal layer 7 (that is, vertical relationship). In this example, the insulator between the metal layer 6 and the metal layer 7 constitutes the location of the antifuse storage at the intersection of the straps between the metal layers 6 and 7 . Board 300 includes 16 such antifuse stores. 312-1 is the antifuse storage located at the crossing position of the plug strips 310-4 and 308-4. When turned on, it can be plugged into strip 310-4 and plugged into strip 308-4. FIG. 3A is a simplified diagram. Usually, each layer of the board contains 10-40 plug strips, and there are multiple such boards, including antifuse memory programmable wiring circuit structure.

304 is a Y programmable transistor connected to the plug strip 310-1. 318 is an X programmable transistor connected to strip 308-4. 302 is a Y selection logic which allows selection of a Y programming transistor during the programming phase. 316 is an X selection logic which allows selection of an X programming transistor during the programming phase. Once 304 and 318 are selected, programming voltage 306 is generated on strip 310-1 while strip 308-4 is grounded, causing antifuse 312-4 to be turned on.

FIG. 3B is a schematic diagram of a programmable connection structure 300B; 300B is a variation of 300A, and some plug strips of the energy band have different lengths. In this variation, there is no splicing strip 308-4, only two shorter splicing strips 308-4B1 and 308-4B2. This may be beneficial for the signal input and output of the programmable wiring circuit structure 300B. In order to reduce the number of plug strips in a board, these short plug strips can be used for the input and output of signals in the wiring circuit structure, instead of using the previous plug-in strips. to select the path. In this variation, the programming circuit needs to be amplified to support the programming of antifuse storage 312-4B and 312-4B.

Different from the prior art, various cases in this invention suggest not constructing the programmable transistor in the diffusion layer of the silicon substrate, but setting the working voltage in the antifuse wiring. This is also part of the antifuse structure setting, so that the antifuse will not be easily opened. Also, be aware that it may be necessary to set and add a silicon source to ensure that the programming process does not damage the working circuit. Therefore, additional silicon area and great care are required when including antifuse programmable transistors on a silicon substrate.

In order to meet the performance requirements of high-speed components, the maximum requirement of the working transistor is speed, and the programming circuit can work relatively at a lower speed. Therefore, the programming circuit can use thin film transistors, which can satisfy the function well and reduce the requirement on the silicon chip area.

There are other types of transistors, such as vacuum FETs, bipolar transistors, etc., which can also be used in programmable circuits, and can also be arranged not on the silicon base, but on the upper or lower layer of the antifuse memory programmable wiring circuit.

However, in another alternative, programmable transistors and programmable circuits can be fabricated on SOI wafers, and the wafers can be bonded to programmable logic wafers using through-silicon vias (TSVs) Or connected through layer vias (TLV). The advantage of using SOI wafers for antifuse programming is that the

High voltage transistors are very efficient and can be used to program circuits and support functions such as programming controller functions. In addition, there is a variant in which programmable circuits can be fabricated on the previous SOI wafer process, further reducing costs. It can also be used in other process technologies and/or manufacturing locations around the world.

There are also other processing technologies that can integrate silicon chips or other semiconductor layers on the antifuse programmable wiring circuit to realize the construction of the antifuse programmable circuit. As an example, there is a recent technique that proposes the use of plasma guns to spray semiconductor-grade silicon to form semiconductor structures, including, for example, p-n junctions. The corresponding semiconductor type formed by spraying silicon is predictable. In addition, there are more and more technologies using graphene and carbon nanotubes (CNTs) to realize semiconductor functions. Based on this invention, we will use the phrase "thin film transistor" as a general term for the above technologies, including all known or unknown similar technologies.

In summary, a common goal is to reduce the cost of mass production with minimal mask setup cost without resetting. Using thin film transistors, as programmable transistors, enables relatively simple and straightforward volume cost savings. Instead of embedding the antifuse in the isolation layer, a custom mask can be used to define the vias in all the final locations, although previously these vias each had a separate open antifuse. In addition, those that need to be programmed before, the same connections between them can be connected through fixed vias. This may save costs associated with fabricating the antifuse programming layer and programming circuitry. Note that there may be a distinction between antifuse resistors and mask-defined via resistors. The conventional approach is to make analog models of the two alternatives, and the setter will verify whether the settings in both cases are feasible.

Another purpose of building programming circuits on top of the antifuse layer is to achieve higher circuit densities. Many connections may be required to connect the programming transistors to their respective metal straps. If these connections go up, it is possible not to block the wiring circuit path for the connections on the lower layers, thereby reducing the circuitry above.

FIG. 3A shows a wiring circuit structure of a 4x4 plug strip, and a common wiring circuit structure may include multiple 20x30 plug strips. For a 20x30 board, about 20+30=50 programming transistors are needed. A 20x30 board area is about 30hpx30vp, "hp" indicates the horizontal spacing, and "vp" indicates the vertical spacing. In this way, the area of the programmable transistor may be relatively large, about 12hp x vp (20hpx30vp/50=12hpxvp). In addition, you need to deal with: between programmable layers, the available area for each connection, and the programmable wiring circuit structure. Also, 1-2 of the redistribution layers may need to redistribute the connections within the available area, and then build these connections down, preferably aligned, so that before connecting to the lower layer patch strip 310 of the programmable routing circuit structure The process causes minimal hindrance.

FIG. 4A is a schematic diagram of a programmable connection board 300 and another programmable connection board 320 . Due to the higher silicon density, configurable routing circuits can be built on this board in the most compact way. Figure 4B is a schematic of a 2x2 programmable wiring circuit board; including a tessellated board 300 and a board 320, which is a variation of board 300 rotated 90 degrees. When a signal is transmitted from south to north, it is necessary to use antifuse memory, such as 406, to connect the south-north splice strip. Both 406 and 410 are antifuse, located at the end of a strip that is connected to other strips in the same orientation. Signals travel from metal layer 6 to metal layer 7 from south to north. If a change of direction is required, use an antifuse like 312-1.

The configurable routing circuit structure may include: connecting the output logic chip to the input logic chip, and constructing the required part of the custom logic. The logic chip itself is built with the first few metal layers and transistors on the silicon substrate. Usually metal layer 1 and metal layer 2 are used to build logic chips. Sometimes it is also effective to use metal layer 3 or part of layer 3.

FIG. 5A is a schematic diagram of an inverter 504 and its input 502 and output 506 . An inverter is the simplest logic chip. The input 502 and the output 506 can be connected through a plug strip on a configurable wiring structure.

FIG. 5B is a schematic diagram of buffer 514 and its input 512 and output 516 . The input 512 and the output 516 can be connected through a plug strip on a configurable wiring structure.

FIG. 5C is a schematic diagram of a settable strength buffer 524 and its input 522 and output 526 . The input 522 and the output 526 can be connected through a plug strip on a configurable wiring structure. 524 is programmable through antifuse 528-1, 528-2 and 528-3 which constitute an antifuse programmable drive chip.

5D is a schematic diagram of D-flip-flop 534 and its input 532-2 and output 536, including control inputs 532-1, 532-3, 532-4, and 532-5. Control signals can be connected to configurable wiring circuits or local or global control signals.

FIG. 6 is a schematic diagram of LUT4. LUT4 604 is a common logic element in FPGA technology called a 16-bit look-up table or LUT4. The component has four inputs 602-1, 602-2, 602-3, and 602-4. One outputs 606. Usually a LUT4 can be programmed to implement any logic function requiring less than or equal to 4 inputs. The LUT function in FIG. 6 can be realized through 32 antifuse memory such as 608 . 604-5 is a 2-1 multiplexer. In FPGA, the most common way to implement LUT4 is to use 16-bit SRAM chips or 15-way multiplexers. Figure 6 shows a LUT4 antifuse configurable look-up table implementation via 32-bit antifuse and 7-way multiplexers. The programmable chip in FIG. 6 includes additional inputs 602-6, 602-7, each with 8-bit antifuse attached, allowing functions other than LUT4 to be implemented.

FIG. 6A is a schematic diagram of a PLA logic chip 6A00. This die was used in most commonly used programmable logic devices before LUT logic became mainstream. Other acronyms for such logic devices include PLD and PAL. 6A01 is a kind of antifuse memory, which allows to select the input signal of multi-channel input AND6A14. In this diagram, an antifuse is included at all intersections of vertical and horizontal lines, enabling connections according to the desired end function. The large AND chip 6A14 constitutes the product term and realizes the input selection AND function of 6A02 or the inverse copy. A multi-input OR 6A15 implements an OR function based on the selection of the product term to form an output 6A06. Figure 6A shows an antifuse programmable PLA logic.

The logic chips in Figures 5, 6 and 6A are representative only. There are many different ways of building programmable logic logic structures, including attached logic chips, such as AND, MUX and other chips, and variations of the above chips. In addition, in the construction of the logic chip, there may also be different forms due to the configurable wiring circuit structure used for the input and output connections or the use of direct non-configurable connections.

FIG. 7 is a schematic diagram of a programmable chip 700 . Programmable structures can be built by tiling the above chips. Tiling of the same wafer can be repeated to form a homogeneous structure. Additionally, mixing of different wafers can form non-uniform structures. The logic chip 700 may be any one of FIGS. 5 and 6 , a mix and match of the above, and their predecessors. Logic chip 710 , input 702 and output 706 are all connected to configurable wiring structure 720 through input and output strip 708 and connected antifuse memory 701 . The shorter wiring circuit 722 includes metal plug strips, the same length as the board, including horizontal plug strips 722H on one metal layer, vertical plug strips 722V on the other metal layer, and antifuse memory 701HV at their intersections , allowing selection of horizontal and vertical strips and connections. The connection between the horizontal plug strip and another horizontal plug strip is realized through the antifuse memory 701HH, which has the same function as the antifuse memory 410 in FIG. 4 . The connection between the vertical plug strip and another vertical plug strip is realized through the antifuse memory 701VV, which has the same function as the antifuse memory 406 in FIG. 4 . Long horizontal strips 724 are used to connect long distance signals, usually 8 boards or more in length. Usually a long-distance strip has an optional connection to shorten the travel through antifuse 724LH, and a vertical long-distance strip with 724. FIG. 7 is a two-dimensional schematic diagram of a programmable chip 700 . In actual use, 700 is a three-dimensional structure, and the logic chip 710 uses a silicon base and metal layers 1, 2, and 3. The programmable wiring structure includes connected antifuse on its surface.

FIG. 8 is a schematic diagram of a programmable component layer structure, which is an alternative solution of the present invention. In this scheme, the antifuse memory consists of two layers. The first level is used to set the logic region and in some cases the logic clock distribution. The first antifuse layer can also be used to manage some power distribution, saving power by disconnecting power from unused circuits. This layer can also be used to connect certain long-distance transmission paths and/or to connect the inputs and outputs of logic chips.

Fabrication of the Components As shown in Figure 8, starting with a semiconductor substrate 802 containing logic chip transistors, the substrate also includes first antifuse layer programmable transistors. Next comes 804 layers, including metal 1, insulator, metal 2, and sometimes metal 3. These layers are used to build logic chips, I/O and other analog chips. In this alternative, the first antifuse memory is contained in the isolation layer, between metal layer 1 and metal layer 2, or in the isolation layer between metal layer 2 and metal layer 3, and the programming transistor can be embedded in the It is located in the silicon substrate 802 under the first antifuse memory. The first antifuse memory can be used to program logic chips, such as 520, 600, 700, and can also be used to connect each chip to achieve greater logic functions. The first antifuse can also be used to program the logic clock distribution. The first antifuse layer can also be used to manage some power distribution, saving power by disconnecting power from unused circuits. This layer can also be used to connect certain long-distance transmission paths and/or to connect the inputs and outputs of these chips.

The following layers 806 can form long-distance wiring channels for all or part of the power distribution and clock networks, forming a supplement to the structures in the previous layers 804 .

The underlying base layer 807 may include an antifuse programmable wiring structure. It can also be called a short-distance wiring structure. If metal layers 6 and 7 are used for the plug strips of the configurable wiring structure, the second antifuse can be embedded in the insulating layer between layers 6 and 7 .

The programming transistors and other portions of the programming circuitry are available for subsequent fabrication, above the programmable wiring structure 810 . The programming element can be a thin film transistor or other peroxide transistors mentioned above. At this time, the antifuse memory programming transistor is disposed above the antifuse layer, which makes it possible to implement the configurable wiring circuit 808 or 804 . It should be noted that in some cases it may be beneficial to build the control logic of the second antifuse programming circuit on the base layers 802 and 804 .

The final step is the connection to the external 812. Solder joints can be used for wire bonding, and solder balls can be used for flip-chip, optoelectronic or other connection structures such as TSV connections.

In another alternative of the present invention, the antifuse programmable wiring structure can be used for multiple purposes. The same structure can be used as part of the wiring structure, or as a part of the PLA logic chip, or as a part of the read-only memory (ROM) function. In FPGA products, it may be necessary for a component to be able to serve multiple purposes. Equipping system resources with multiple functions can increase the utility of FPGA components.

FIG. 8A is a schematic diagram of a programmable component layer structure, which is another alternative solution of the present invention. In this alternative, there is an attached circuit 814 contacting 816 to the first antifuse layer 804 . The programming transistors of the first antifuse layer 804 are provided by the underlying components. In this way, the diffusion layer 816 of the programmable device does not need to bear the cost of the programming transistor of the first antifuse layer 804 . Correspondingly, the programming connection of the first antifuse layer 804 can be directly connected downward to the lower programming component 804 , while the programming connection to the second antifuse layer 807 can be directly connected upward to the programming circuit 810 . This reduces congestion on the wiring paths inside the circuit.

Reference number 808 in subsequent figures may be various pre-processed wafers or combinations of layers, wafers or layers comprising multiple transport layers (combinations) as described in this invention. The phrase "preprocessed wafer or layer" is generic; when reference number 808 is used in the drawings to illustrate examples of the invention, reference number 808 may represent a number of different preprocessed wafer or layer types, including but not limited to Lower prefab layer, lower wiring filaments, base layer, substrate layer, housing wafer, target wafer, pre-processing circuit, pre-processing circuit receiver wafer, substrate wafer layer, bottom layer, bottom master wafer, base layer , top layer, or fab wafer.

Figure 8B is a generic preprocessed wafer or layer 808. The wafer or 808 layer may contain pre-processing circuits, such as logic circuits, microprocessors, circuits including various transistors, other types of digital or analog circuits, including but not limited to various cases in the present invention. The preprocessed wafer or 808 layer may contain preprocessed metal wiring circuits, possibly made of copper or aluminum. Preprocessed metal wiring circuits may be used for layer transport setup or fabrication, including electrical connections from the preprocessed wafer or layer 808 to that layer or transport layer.

FIG. 8C is a schematic diagram of the universal transport layer 809 before being processed into the preprocessed wafer or layer 808 . The transfer layer 809 may be processed onto a carrier wafer or a substrate wafer during a layer dicing process. The preprocessed wafer or layer 808 can become the target wafer, receptor substrate or receptor wafer. The susceptor wafer may contain susceptor wafer metal connection pads or straps configured to make electrical connections to the transport layer 809 . The transfer layer 809 may be processed onto a carrier wafer or a substrate wafer during a layer dicing process. The transfer layer 809 may contain metal wiring circuits configured to be fabricated for layer transfer or electrical connection to the pre-processed wafer or to the 808 layer. The electrical connections from the transport layer 809 to the preprocessed wafer or between layers 808 may use through-layer via (TLV) connections. Transport layer 809 may comprise monocrystalline silicon, crystalline silicon, or predictable crystalline silicon single or multiple layers, other semiconductor, metal and insulator materials, layers, etc.; or multiple regions of monocrystalline silicon, predictable monocrystalline silicon, or other semiconductor , metal, or insulator materials.

FIG. 8D is a schematic diagram of a preprocessed wafer or layer 808 formed by layer dicing from an upper transport layer 809 . Above the pre-processed wafer or layer 808, pre-processed metal wiring circuits may be further processed for the setting and manufacture of layer transfer, including electrical connections from the pre-processed wafer or layer 808 to this layer or transfer layer.

FIG. 8E is a schematic diagram of the universal transport layer 809A prior to processing into a preprocessed wafer or layer 808A. The transfer layer 809A may be processed onto a carrier wafer or a substrate wafer during a layer dicing process. The transfer layer 809A may contain metal wiring circuits designed to be fabricated for layer transfer or electrical connection to the preprocessed wafer or to the layer 808A.

FIG. 8F shows a pre-processed wafer or layer 808B formed from the upper transfer layer 809A by layer dicing of the pre-processed wafer or layer 808A. Above the pre-processed wafer or 808B layer, pre-processed metal wiring circuits may be further processed for the setting and manufacture of layer transfer, including electrical connections from the pre-processed wafer or 808B layer to this layer or transfer layer.

FIG. 8G is a schematic diagram of the generic transport layer 809B prior to processing into a preprocessed wafer or layer 808B. The transfer layer 809B may be processed onto a carrier wafer or a substrate wafer during a layer dicing process. The transport layer 809B may contain metal wiring circuits designed to be fabricated for layer transport or electrical connection between the pre-processed wafer or the 808B layer.

Figure 8H shows a pre-processed wafer or layer 808C formed from the upper transfer layer 809B through layer dicing of the pre-processed wafer or layer 808B. Above the pre-processed wafer or 808C layer, pre-processed metal wiring circuits may be further processed for the setting and manufacture of layer transfer, including electrical connections from the pre-processed wafer or 808C layer to this layer or transfer layer.

FIG. 8I shows a pre-processed wafer or layer 808C, a 3D IC stack, which may include ablated layers 809A and 809B, on top of the pre-processed wafer or layer 808. One or more layers of cut-out layers 809A and 809B and the initial pre-processed wafer or layer 808 may include one or more types of transistors, metallization, such as one or more layers including copper or aluminum, upper and lower wiring circuits between layers, and In-layer wiring circuits. The transistors within a layer can be of different types between layers. Transistors can also be arranged in various ways. The arrangement of transistors can be a repeat arrangement or a strip arrangement. Transistors can be arranged in multiple layers within the transport layer. The arrangement of transistors can be electrodeless transistors or trench via transistors. Cut out layers 809A and 809B, and preprocessed wafer or layer 808 may also contain semiconductor components such as resistors, capacitors, inductors, one or more programmable wiring circuits, storage structures and components, sensors, microwave components, and The photoelectric wiring circuit term "carrier wafer" or "carrier substrate" connected to the microwave transceiver can also be called "support wafer" or "support substrate".

The layer-slicing process can be reused multiple times to produce pre-processed wafers containing multiple cut-out layers that can be combined as pre-processed wafers or layers for further layer-slicing. The layer dicing process is flexible enough that the preprocessed wafer and the transfer layer can be turned over and cut on any side under appropriate manufacturing and insertion conditions, and continue to cut in any direction according to the set selection.

Those with only basic knowledge will easily understand the illustrations in Figures 8-8I (not enlarged). At the same time, there will be further realization that more of deformation. After reading this description, people will realize that the scope of the present invention will include many modifications and variations. Therefore, this invention is not limited to the patent statement in the appendix.

The alternative technology for this underlying circuit is the "SmartCut" intelligent cutting process. The "SmartCut" intelligent cutting process is widely used in the manufacture of SOI wafers. The smart dicing process, coupled with wafer bonding technology, enables "layer dicing" to produce a thin layer of monocrystalline silicon wafers from one wafer after another. "Layer cutting" can be completed below 400 degrees Celsius, and the cut layer produced can be less than 100nm thick. Two companies, Soitec (Crolles, France) and SiGen-Silicon Genesis (San Jose, CA), have commercialized the process with several variants and names. The silicon wafer bonding process at room temperature, which uses a particle beam to treat the silicon surface under vacuum, has recently been monopolized by Mitsubishi Heavy Industries (Tokyo, Japan). The process is able to cut silicon wafer layers at room temperature.

Additionally, there are other techniques in use. For example, other techniques can also be used for layer dicing, such as the IBM layer dicing process, as described in IEDM2005, A.W. Topol et al. IMB's layer dicing process uses an SOI technology and a glass substrate wafer. The power supply circuit can be processed at high temperature on the SOI wafer, temporarily bonded to the borosilicate glass substrate wafer, chemical mechanical polishing is used to thin the backside, and the buried oxide (BOX) is etched away. At this point, the thinned power supply wafer is aligned and the low temperature oxide is bonded to the receiving wafer surface. The thinned power supply wafer is then separated from the glass substrate wafer, and through-layer via connections are processed. In addition, the ELO technique, as described by P. Demeester et al., published by IMEC in Semiconductor Science and Technology 1993, can also be used for layer dicing. ELO selectively removes the very thin sacrificial layer between the substrate and the layer to be cut. The GaAs or Si to-be-cut layer can be "rolled" with an adhesive cylinder, or removed from the substrate using a flexible carrier, such as black wax, to lift the to-be-cut layer structure. This process occurs at the same time as selective etching, which can be dilute Hydrofluoric (HF) acid to remove the layer that needs to be released from the surface. The release layer can be silicon oxide of SOI or AlAs. After stack transfer, the cutout layer is aligned and bonded to the desired receiving substrate or wafer. The productivity of the ELO process in multilayer slicing was improved by J. Yoon et al., J. Yoon from the University of Illinois at Urbana-Champaign. The article was published in Nature on May 20, 2010. Canon has developed a layer cutting technology called ELTRAN-porous silicon film layer cutting. ELTRAN can also be used. According to the Electrochemical Society Conference Abstract No.438, 2000, and JSAP International Papers in July 2001, the seed wafer oxidized by HF/ethanol solution can generate pores on the surface of silicon, and the pores can be treated by low temperature oxidation. The pores are then sealed using hydrogen reduction at high temperature. Then silicon crystal film can be placed on the porous silicon and oxidized to form SOI BOX. The seed wafer can be bonded to the substrate wafer, and the seed wafer can be split by aligning the porous silicon layer with high pressure water. The porous silicon can then be selectively etched to form a dense silicon layer.

Fig. 14 is a schematic diagram of the layer cutting process. In another alternative of the invention, "layer dicing" is used to construct the underlying circuitry 814. 1402 is a wafer that is processed to construct the underlying circuitry. Wafer 1402 can be used in most advanced processes, or recent generations of processes. It can contain programming circuitry 814, among other useful structures, and can serve as a pre-processed CMOS silicon wafer, or partially processed CMOS, or other silicon or semiconductor substrate for fabrication. Wafer 1402 may also be referred to as a receiver substrate or target wafer. Subsequently, an oxide layer 1412 will be placed on the wafer 1402 and polished to achieve a better planarity and surface grade. Power supply die 1406 is then bonded to 1402 . The surfaces of power supply wafer 1406 and wafer 1402 are pre-treated with various surface treatments for low temperature bonding, including RCA pre-cleaning, which may include diluted ammonium hydroxide or hydrochloric acid, and may include electrical Slurry surface treatment to reduce bonding energy and improve wafer-to-wafer bonding strength. The power supply wafer 1406 is preprocessed by smart dicing of particle implantation. The atomic type may include H+ ions, and the required depth depends on the scribe line of the smart dicing 1408 . The smart cutting line 1408 can become a layer cutting dividing plane, as shown by the dotted line. The smart dicing scribe lines 1408 or layer cut dividing planes can be formed before or after the power supply wafer 1406 is processed. The power wafer 1406 can be bonded to the wafer 1402 by contacting the surface of the power wafer 1406 with the surface of the wafer 1402, followed by mechanical force and/or annealing to strengthen the oxide-oxide bond. Alignment of power wafer 1406 to wafer 1402 may be performed immediately after wafer bonding. Including the annealing bonding cycle, the acceptable bond strength should not exceed approximately 4000C. After bonding the two wafers, smart dicing is performed to cut and remove the top 1414 of the power supply wafer 1406 along the dicing layer 1408 . Cutting can use various energy methods to cut to the intelligent cutting line 1408 or layer cutting plane, including mechanical cutting with a knife, water impact, air cutting, or on-site laser annealing or other suitable methods. A 3D wafer 1410 is obtained, including a wafer 1402 and a monocrystalline silicon (or multi-layer material) additional layer 1404 . The layer 1404 can be polished by chemical or mechanical methods to achieve a suitable surface quality for subsequent processing. Layer 1404 can be very thin, on the order of 50-200 nm. The process required above is called "layer cutting". Layer dicing is commonly used in the SOI manufacturing process, SIO stands for silicon-on-insulator wafer. For SOI wafers, the top surface has been oxidized such that after "layer dicing" a buried oxide-BOX is obtained, isolating the top thin monocrystalline silicon layer from the body of the wafer. The use of implanted atoms, such as hydrogen or helium or a mixture of hydrogen and helium, can produce the above-mentioned cutting planes, also referred to as "ion-cutting" in this document, which is the preferred version of the layer cutting method.

People with only basic knowledge will also easily understand Figure 14 - the illustration in the diagram (not enlarged). In general, one can further realize that, for example, deeply doped (greater than 1e20 atoms/cm3) layers of boron or silicon germanium (SiGe) can be used as etch stops for ion-dicing process flow, layer dicing division The plane can be placed on the etch stop layer or below the substrate material, or the etch stop layer can be used in a non-implant dicing process, or the donor wafer can be preferentially etched until the etch stop layer is reached. It is further recognized that oxides in SOI or GeOI donor wafers can be used as etch stop layers. After reading this description, people will realize that the scope of the present invention will include many modifications and changes. Therefore, this invention is not limited to the patent statement in the appendix.

Thus, a "layer cut" process can be used to bond a thin single crystal silicon layer 1404 on a preprocessed wafer 1402. A standard flow is sufficient to ensure that the remainder of the required circuitry is constructed as shown in FIG. 8A, from the cut layer 1404. The upper layer 802 starts. The printing step uses the alignment marks on the wafer 1402 so that the circuits 802 , 816 , etc. can be connected to the underlying circuit 814 . One factor to be aware of is high temperature, which may be required during processing of circuit 802 . The preprocessing circuits on wafer 1402 need to withstand the high temperatures used to turn on semiconductor transistors 802 built on layer 1404 . The circuits on wafer 1402 will include transistors and polysilicon local wiring circuits (polysilicon or poly) and some other type of circuits that can withstand high temperatures, such as tungsten (circuits). The processed wafer can support the transistors processed later at high temperature, and the wafer can be called "base" or substrate, base layer, base circuit. The advantage of using layer cutting to build the underlying circuit is that the layer cutting 1404 can be made very thin, so that the through-silicon via connection 816, or the through-layer via (TLV) has a low aspect ratio and can be closer to the normal contact. , so it can be made very small to minimize the area of expenditure. The thinner cut-out layer can also use the conventional direct through-layer alignment technique, which can increase the density of the via connection 816 .

Figure 15 is a schematic diagram of the underlying programming circuit. Both the transistors 1501 and 1502 are prefabricated on the substrate 1402 , and then the programmable logic circuit and the antifuse memory 1504 are processed on the cut-out layer 1404 . Programming connections 1506, 1508 are connected to programming transistors using contact holes through layer 1404, as shown at 816 in FIG. 8A. The transistor is set to withstand a higher programming voltage when the antifuse 1504 is programmed.

FIG. 16 is a schematic diagram of the bottom isolation transistor circuit. Bringing the antifuse 1604 to a high voltage may damage the logic transistors 1606,1608. In order to protect these logic circuits, the transistors 1601, 1602 are isolated so that the set transistors can withstand higher voltages. The higher programming voltage is only used during the programming phase, while the isolation transistor is turned off by the control circuit 1603. The lower wafer 1402 can be used to build isolation transistors. Since the programming transistors and isolation transistors on the substrate 1402 are larger, better utilization of the primary silicon 802 (1404) is possible. Usually primary silicon is manufactured in the front-end process to obtain high density and performance. The substrate can be fabricated in a later process step, reducing cost and supporting high voltage transistors. It can also be processed without CMOS transistors, such as double-diffused metal oxide semiconductor (DMOS) or bipolar transistors, which is beneficial to switching and isolation functions. In most cases, the gate input requires a protective diode, called an antenna. Such a protective deposition can effectively integrate the input of the isolation transistor into the substrate. In addition, the isolation transistors 1601, 1602 can also provide antenna effect protection without additional diodes.

Another alternative example of the present invention is to preprocess the base layer 1402 to produce a pair of reverse bias voltage generators. One of the major challenges of advanced semiconductor logic devices is die-to-die and intra-die parametric variation. Parts of the wafer may have different conductive properties due to dopants and the like. The most influential of these parameters on bias is the threshold voltage of the transistor. The difference in gate voltage within the wafer is mainly caused by differences in channel dopants, gate insulators, and critical dimensions. The impact of these differences on sub-45nm process node components is enormous. The usual solution is to consider the worst case when setting, resulting in a large performance cost. In addition, a new setting idea is currently being proposed to solve the huge uncertainty of production capacity and cost caused by the deviation problem. Potential solutions include using local reverse bias to improve performance in the worst-case region, improving overall performance while consuming minimal additional power. Base-local reverse bias can also be used to reduce leakage due to process variations.

FIG. 17A is a topological schematic diagram of a reverse bias circuit. The substrate 1402 carries a reverse bias circuit 1711, which can improve the performance of some regions 1710 of the primary crystal device, which would otherwise maintain a lower level of performance.

17B is a schematic diagram of a reverse bias circuit; a reverse bias control circuit 1720 controls oscillators 1727 and 1729 to drive a reverse bias generator 1721 . Negative reverse bias voltage generator 1725 will generate the required negative bias voltage, connect to the main circuit through connection 1723, and provide reverse bias voltage to N-channel metal oxide semiconductor (NMOS) transistor 1732 on primary silicon 1404 . The forward and reverse bias voltage generator 1726 will generate the required negative bias voltage, connect with the main circuit through the connection 1724, and provide reverse bias voltage to the P-channel metal oxide semiconductor (PMOS) transistor 1724 on the primary crystal silicon 1404 . The size of the corresponding reverse bias voltage is set in the initialization phase according to the region. It can be programmed using an external tester and controller, or it can be done using the on-chip self-test circuit. Usually, non-volatile storage is used to save the reverse bias voltage of each region, so that the device can be initialized normally when it is turned on. In addition, dynamic planning can be used to set the required reverse bias voltage for devices in different operating modes. Setting the reverse bias circuit in the substrate can make better use of the silicon chip resources of the primary device, making the logic operation of the main chip device less distorted.

Figure 17C is an alternative circuit function that can also be used for "basics". In many IC configurations, it is necessary to integrate power control to reduce the power supply to some magnetic regions of the component, or to cut off the corresponding power supply when these magnetic regions are completely in the "sleep" state. Typically, these supply controls are best accomplished using high voltage transistors. Therefore, it may be necessary to build a power control circuit on the substrate chip 17C02. The power control 17C02 can use its own high voltage power supply and control or adjust the power supply voltage of the 17C10 and 17C08 magnetic areas on the main chip assembly. Control can be initiated through the main chip component 17C16 and managed by 17C04 on the base board.

Figure 17D is an alternative circuit function that can also be used for "basics". In many IC setups, it is necessary to integrate probing assistance systems to enable easy probing of components during the debug phase and to support production testing. Probe circuits are also used in the prior art, using the same transistors as the main circuit. Figure 17D shows the probe circuit built under the primary layer active circuit on the substrate. Figure 17D shows the connections to the continuous active circuit component 17D02. The connection is connected to the substrate through the interconnection circuit 17D06, and the high-impedance probe circuit 17D08 is used to detect the output of subsequent components. Selection circuit 17D12 allows one or more outputs to be routed through one or more buffers 17D16 that can be controlled by signals on the primary circuit to drive sequential output signals to probe signal output 17D14 for debugging or testing. People can generally understand that, for example, multiple probe circuits 17D08 groups, multiple probe output signals 17D14, and a control buffer 17D16 whose signals are not output from the main circuit are all possible configurations.

In another solution, the substrate 1402 may carry an SRAM chip, as shown in FIG. 18 . The SRAM chip 1802 is pre-fabricated on the bottom substrate 1402 and can be connected to the main logic circuits 1806, 1808 on 1812-1404. As described above, the layers built on 1404 can be aligned with the pre-fabricated structures on the underlying substrate 1402 to enable logic chips to be connected to corresponding underlying RAM chips.

Figure 19A is a schematic diagram of bottom I/O. The substrate 1402 can be pre-processed to carry I/O circuits, or part of the I/O, such as the output drive 1912 relatively large transistor. Alternatively TSVs on the substrate can also be used to route I/O connections 1914 all the way back to the back of the substrate. Figure 19B is a side "cut" of an integrated component according to an example of the present invention. The output drive is shown as PMOS and NMOS output transistor 19B06, and the two transistors are aligned through TSV 19B10, and connected to the back solder joint or ball solder joint 19B08. The material connected in the substrate 1402 can be selected to withstand the high temperature in the subsequent manufacturing process of the components on the entire 1404, as shown in Fig. 8A-802, 804, 806, 807, 810, 812, it can be tungsten. The substrate can also be equipped with an input protection circuit 1916 to connect the pad 19B08 to the input logic 1920 of the main circuit.

Another example of this invention is to use TSV on the substrate, such as TSV19B10, to connect chips to form a 3D integrated system. Typically, each TSV requires a relatively large area, typically several square microns. When many TSVs need to be used, the area occupied by high-density transistors will be excluded, making the area of all TSVs very expensive. On the donor wafer, pre-processing these TSVs using the previous flow can significantly reduce the effective cost of 3D TSV connection. Connections 1924 to pristine silicon circuits 1920 can be made using the smallest contact area, on the order of a fraction of a square nanometer, which is two orders of magnitude smaller than the several square micrometers required for TSVs. The illustration in Figure 19B (not enlarged) will be readily understood by persons with only basic knowledge. It is generally well understood that many other strengths and component arrangements can be constructed using the inventive principles described in Figure 19B, which is provided for reference only.

Figure 19C is a 3D system comprising 3 connected chips (19C10, 19C20, 19C30) and TSVs (19C12, 19C22, 19C32), illustrated in a similar manner to TSV 19B10 and Figure 19A. The stack of 3 chips uses TSV (19C12, 19C22, 19C32) on the substrate to build a 3D interconnection circuit, so that the primary silicon 19C14, 19C24, 19C34 are connected to their respective substrates through via holes of the smallest size, and the impact and loss of silicon chip area are minimal . The stack of three chips can be connected to the PC motherboard using ball bond 19C40, which is connected to the back side of chip TSV19C32. The illustration in Figure 19C (not enlarged) will be readily understood by persons with only basic knowledge. It is generally well understood that many other strengths and component arrangements can be constructed using the inventive principles described in Figure 19C, which is provided for reference only. For example, a die stack can be placed in a package using flip-chip bonding, or ball bonds 19C40 can be used instead of bond pads, and the part can be flipped and bonded in a conventional package with wire bonds.

Figure 19D is a schematic diagram of a 3D IC processor and DRAM system; a well-known problem facing the computer industry is the "memory wall" related to the speed with which the processor can access the DRAM. The solution given by the prior art is to use TSVs directly arranged above the processor to connect to the DRAM stack, and bump the heat sink to the back of the processor to dissipate heat for the processor. However, doing so requires a special via through the DRAM to allow processor I/O and current to pass through. Too many processor "vias through DRAM" can lead to some serious drawbacks. First, it will reduce the available silicon area of DRAM by as much as several percent. Then, the current passing through the top will be increased by several percentage points. In addition, it will require the setting of the DRAM to coordinate with the setting of the processor, which is a commercial challenge. The example of Figure 19D presents a solution that can reduce the above-mentioned problems: use a substrate with TSVs as shown in Figures 19B and 19C. Using a substrate and pristine silicon structure allows the connection to the processor without going through the DRAM.

In Fig. 19D, the processor I/O and voltage can be connected through the down-facing microprocessor active area 19D14 - the primary silicon layer, through the heat sink substrate 19D04 and the base material 19D06 through vias 19D08. The heat sink 19D12, the bottom plate of the heat sink 19D04, and the cooling groove 19D02 are all used to take away the heat generated by the active area 19D14 of the processor. The TSVs (19D22) passing through the backplane 19D16 are used to connect to the DRAM stack 19D24. A DRAM pair includes a plurality of thin DRAMs 19D18 interconnected by TSVs 19D20. Therefore, the DRAM stack does not need to pass through processor I/O and voltage planes, and can be fabricated independently of processor settings and placement. The DRAM chip 19D18 is closest to the substrate 19D16 and can be set to connect to the substrate TSV 19D22, or a separate redistribution layer (or RDL, not shown) can be added between, or the substrate 19D16 can be used as a pre-processing high-temperature wiring layer , such as the aforementioned tungsten. Another processor active area does not contain TSVs, unlike substrate 19D16.

In addition, substrate vias 19D22 can be used to pass through the processor I/O and power, connecting the substrate 19D04 and substrate material 19D06, while the DRAM stack can be directly connected to the processor active area 19D14. It can be easily understood that many different combinations can be used within the scope of the present invention.

FIG. 19E is another example of the present invention. The DRAM stack 19D24 can be connected to an RDL (redistribution layer) 19E26 through bonding wires 19E24. The RDL connects the DRAM to the substrate via 19D22, and then connects them to the processor facing down. 19D14 is connected.

In another case, custom SOI wafers can be processed in the NuVias 19F00 in the fab. NuVias 19F00 can use traditional TSVs with a diameter of about 1 micron or more, which are also processed by SOI wafer suppliers. As shown in FIG. 19F, wafer 19F02 and buy-in oxide BOX 19F01 are processed. Process wafer 19F02 is typically hundreds of microns thick, and BOX 19F01 is typically hundreds of nanometers thick. The Integrated Component Manufacturer (IDM) or foundry then processes the NuContacts 19F03 to interface with the NuVias 19F00. NuContact can be a contact of a conventional size, which is obtained by etching on the thin SOI silicon wafer 19F05 and BOX 19F01 and then filling it with metal. The size of NuContact DnuContact 19F04, as shown in Figure 19F, can be processed to the nanoscale. Prior Art As shown in Figure 19G, construction is done on bulk silicon wafers 19G00, typically with one TSV diameter, DTSV_prior_art 19G02, in the micron range. NuContact DnuContact 19F04, shown in Figure 19F, the reduced size may be of great significance to semiconductor planners. For through-silicon connections, the use of NuContact can provide reduced die size spending, smaller ultra-thin silicon wafer processing, and less setup complexity. On traditional SOI wafers, TSV placement is based on the requirements of high-volume integrated device manufacturers (IDMs) or foundries, or in accordance with recognized industry standards.

The flowchart shown in FIG. 19H can be used to fabricate conventional SOI wafers. Wafer suppliers may use a similar process. With silicon donor wafer 19H04, the surface 19H05 can be oxidized. An atom, such as helium, is then implanted (doped) to a certain depth in 19H06. Oxide-oxide bonding as described in other cases can be used to bond this wafer to a receiver wafer 19H08 with pre-processed NuVias 19H07 vias. NuVias 19H07 can be constructed using conductive materials, such as tungsten or doped silicon, so that it can withstand high temperatures in subsequent processing. An insulating barrier, such as silicon oxide, can also be used to separate the NuVia 19H07 from the silicon on the receiver wafer 19H08. Alternatively, wafer suppliers can build NuVias 19H07 using silicon oxide. An integrated component manufacturer or foundry can etch the oxide after high temperature (greater than 400 degrees) transistor fabrication and can use metal, copper or aluminum, instead of the oxide. This process allows for lower melting points, but uses highly conductive metals such as copper or aluminum. After bonding, a portion 19H10 of the donor wafer 19H04 can be diced at 19H06 and can then be treated with chemical/mechanical polishing as described in other cases.

Figure 19J shows another technique for fabricating conventional SOI wafers. A standard SOI wafer can be used, and the substrate 19J01, BOX 19F01, and surface silicon 19J02, NuVias 19F00 can be processed in order from the backside to the oxide layer. This technology may produce thicker buried oxide 19F01 than standard SOI process.

Figure 19I illustrates how a 3D stack of a processor 19I09 and a DRAM 19I10 is processed using a custom SOI wafer. In the above configuration, the power distribution and I/O connections of a processor are all from the backplane 19I12, through the DRAM 19I10, and then connected to the processor 19I09. The above technique in FIG. 19F can make the contact area of the DRAM active silicon chip smaller, which is very convenient for the application of the preprocessor-DRAM stack. On the DRAM chip, the transistor area lost due to processing through-chip connections 19I13 and 19I14 will become very small due to the diameter of NuContact 19I13 on the active DRAM chip (a few nanometers). When the large through-silicon connection is located in the middle of the DRAM, the larger area occupied will increase the difficulty of setting. Smaller size through-silicon connections can cope with this problem. One can easily imagine using this technology to build processor-SRAM stacks, processor-flash memory stacks, processor-graphics storage stacks, combinations of the above, or any other type of integrated circuit Combinations, such as SRAM programmable logic components, and related setting ROM/PROM/EPROM/EEPROM components, ASIC and power regulators, microcontrollers and analog function circuits, etc. In addition, silicon-on-insulator (SOI) can be polysilicon-on-insulator, GaAs, GaN, etc. It is easy to imagine that the NuVia and NuContact technologies are widely applicable, and the scope of this invention is not limited to the rights statement in the appendix.

Another example of the present invention is that the substrate 1402 can additionally carry a re-drive chip (commonly called a buffer). Redriver chips are commonly used in the industry for signal transmission with relatively long paths. Inserting a re-driver circuit along the transmission path helps avoid severe degradation of signal timing and shape due to the high resistance and capacity loss of the path. An advantage of having the redriver on the substrate 1402 is that the redriver can be built using transistors and thus can withstand larger programming voltages. In addition, isolation transistors, such as 1601 and 1602, or other isolation schemes can also be used for the input and output of the logic chip.

FIG. 8A is a schematic structural diagram of a multilayer structure of a programmable device, which has two antifuse storage layers. The programmable transistors used for the first layer 804 can be prefabricated on 814, and then, using smart dicing, the monocrystalline silicon layer 1404 is processed, after which the main programming logic 802 and advanced logic transistors and other circuits are added. Subsequently, a lower layer antifuse memory 804 , a wiring layer 806 , a second antifuse memory layer and a configurable interconnection circuit 807 are also included during multi-metal layer processing. For the second antifuse, the programming transistor 810 can also be processed using the second cut-only layer.

Fig. 20 is a schematic diagram of the layer cutting process of the second layer. Raw wafer 2002 contains all previous layers 814 , 802 , 804 , 806 and 807 . Subsequently, an oxide layer 2012 will be placed on the wafer 2002 and polished to achieve a better planarity and surface grade. A power supply wafer 2006 (or a cutable wafer, as marked) is then bonded to 2002 . Prefabrication of the donor wafer 2006 to include the semiconductor layer 2019 can then be used to build the top layer of the programming transistor 810 as an alternative to TFT transistors. The power supply wafer 2006 can also be pretreated by smart dicing of particle implantation. The atomic type may include H+ ions, and the required depth depends on the scribe line of smart dicing 2008. After bonding the two wafers, smart dicing is performed to remove the top layer 2008 of the power supply wafer 2006 along the dicing layer 2014 . In this way, the donor wafer can now also be used to process and reprocess further layers. The result is a 3D wafer 2010 comprising a wafer 2002 and an additional layer 2004 of monocrystalline silicon (or multilayer material). The cut out layer 2004 can be very thin, approximately between 10-200nm. The use of smart dicing enables the fabrication of monocrystalline semiconductor layers on preprocessed wafers without annealing the preprocessed wafers to temperatures above 4000°C.

Using smart dicing layer cutting does not exceed the upper temperature limit of the underlying pre-processing structure, there are many alternative methods to build the surface layer transistors and accurately align with the underlying pre-processing layer, such as the pre-processing wafer or layer 808. Since the thickness of the cut out layer is less than 200nm, the above-defined transistor can be accurately aligned with the surface metal layer of the preprocessed wafer or layer 808 as required, and the alignment error of these transistors is less than 40nm.

An alternative approach is to use a thinner cutout of monocrystalline silicon for the growth of the outer Ge crystals, using the cutout as a germanium seed. Another method is to use a thinner monocrystalline silicon cut-out layer for the growth of the outer edge GexSi1-x. The Ge/Si percentages in these layers are specified by circuit transistor specifications. The method provided by the prior art is to use a silicon substrate to crystallize germanium through oxide holes on the oxide surface, and grow crystals or lattice seeds from the underlying silicon crystal. However, this is very difficult to do on the surface of multiple wiring layers. Through layer cutting, we can obtain a single crystal layer of silicon on the surface, and make the seeding and crystallization relatively simple, and obtain a superimposed germanium layer. Using CVD at 300 degrees Celsius, the amorphous germanium can be regularly distributed and aligned with the pattern of the underlying layer, which can be a pre-processed wafer or layer 808, and then packaged using low temperature oxide. A short heat pulse on the order of seconds melts the germanium layer while keeping the temperature of the underlying structure below 400 degrees Celsius. The Ge/Si junction will start to crystallize or lattice accumulative growth, crystallizing into germanium, or forming a GeXSi1-x layer. Then, Ge transistors are formed by doping, which can be turned on by laser pulses without damaging the underlying structure, while taking advantage of the low activation temperature of impurities in germanium.

Another method is to use pre-processed wafers for layer dicing, as shown in Figure 21. Figure 21A is a schematic diagram of layer dicing using a preprocessed wafer; a lightly doped P-type wafer (P-wafer) 2101 can be processed into a highly doped N-type silicon (N+) "buried" layer, through Doping and turn-on can also be achieved through shallow N+ doping and diffusion after P- accumulation crystal growth 2106 . Alternatively, a shallow P+ layer 2108 can be additionally doped and turned on if the performance of the transistor requires the use of a substrate contact. Figure 21B is a pre-processed wafer, which can be used for layer cutting after doping atoms. The doping atoms can be H+, and the "cut-out plane" 2110 for smart cutting can be prepared in the lower N+ region, and the oxide After deposition or growth 2112, an oxide layer for oxide bonding may be generated. The layer dicing process can now be performed to process the pre-processed single crystal P-silicon and N+ layers on top of the pre-processed wafer or layer 808 . Pre-processed wafers or 808 layers can be bonded using oxide deposition and/or surface treatment. It is generally foreseeable that the above methods are used for reference only, and other cases and application scopes can be deduced based on the principles of this invention, and the scope of the invention is not limited by the rights statement in the appendix.

22A-22H are schematic diagrams of forming the upper planar source extension transistor. FIG. 22A is a preprocessed wafer or cut out layer on top of layer 808, after smart dicing, N+2 104 is on the surface. The surface transistor source 22B04 and the drain 22B06 are formed by etching away the N+ in the designated area of the gate 22B02, leaving a thinner and clearer doped N+ layer as the extension of the subsequent source and drain, and the transistor The isolation layer of 22B08. Using an additional masking layer, isolation regions 22B) 8 are obtained by etching into the surface of the preprocessed wafer or layer 808 to form isolation between transistors or groups of transistors. Etching away the N+ layer between the transistors helps to conduct the N+ layer. This step is aligned with the surface of the pre-processed wafer or layer 808, so that the formed transistors can form a good connection with the metal layer of the pre-processed wafer or layer 808. Then, a highly equivalent low temperature oxide 22C02 (or oxide/nitride stack) is obtained by deposition and etching to form the structure shown in Figure 22C. Figure 22D shows the structure after the preparatory step of the self-aligned etch for gate 22D02 followed by source and drain extensions 22D04. Figure 22E is the structure obtained after low-temperature microwave oxidation technology, which can be TEL SPA (Toyota Electronics Co., Ltd. slot planar antenna) oxygen radical plasma, so as to grow or deposit a low-temperature gate insulator 22E02 for MOSFET gate oxide, or atomic layer deposition (ALD) techniques can be used. In addition, the gate structure can also be obtained using the following high-K-metal gate process. After an industry standard HF/SC1/SC2 clean to form an atomically smooth surface, a high-k insulating layer 22E02 is deposited. The semiconductor industry has chosen Hafnium-based insulating layers as the material of choice to replace SiO2 and silicon oxynitride. Hafnium-based group insulators include hafnium oxide and hafnium silicate/hafnium silicon oxynitride. Hafnium oxide, HfO2, has a dielectric constant about twice that of hafnium silicate/hafnium silicon oxynitride. (HfSiO/HfSiON k~15) The choice of metal is the key to the normal operation of the device. The metal that replaces the N+ polymer is used as the electrode of the gate, and a working threshold of about 4.2eV is required to ensure the normal operation of the device under the normal threshold voltage. In addition, the metal that replaces the P+ polymer is used as the electrode of the gate, and the work function of about 5.2eV is required to ensure normal operation. TiAl and TiAlN-based metal groups can be used to increase the work function of metals from 4.2eV to 5.2eV.

Figure 22F is the metal gate 22F02 after deposition, grinding and etching. Additionally, to improve transistor performance, a target stress layer can be used to induce higher channel stress. A tensile nitride layer can be deposited at low temperature to increase the channel stress of the NMOS device in FIG. 22 . PMOS transistors can be constructed through the above process, only need to change the initial P-wafer or 2104N+ layer on the outer edge of the P-, N-wafer or N-wafer on the P+ outer layer; and the N+ Layer 2104 was changed to a P+ layer. Then, after forming the metal gate, a compressive nitride film can be deposited to improve the performance of the PMOS transistor.

Finally a thick oxide layer 22G02 is deposited and the contact openings are masked and etched ready for connection to the transistors as shown in Figure 22G. The thicker oxides or low temperature oxides in this document can be processed by chemical vapor deposition (CVD), indoor vapor deposition (PVD) or plasma enhanced chemical vapor deposition (PECVD) techniques. This process can form a single-crystal surface MOS transistor, which can be connected to the underlying multi-metal layer semiconductor components without exposing the underlying components and interconnection circuit metals to high temperatures. These transistors can be used as antifuse programming transistors of layer 807, connected with pre-processed wafer or layer 808 to form a monolithic 3D circuit stack, or used for other functions of 3D integrated circuits. These transistors can be regarded as "planar MOSFET transistors", that is, the current in the transistor channel is always in the horizontal direction. The above-mentioned transistors, including other transistors in this file, can be horizontal transistors, horizontal direction, or lateral transistors. Another advantage of this process is that the intelligent cutting H+, or other atomic doping steps are completed before the gate of the MOS transistor is formed, which can avoid damaging the gate function. If desired, the surface layer of the preprocessed wafer or layer 808 may include a "back gate" 22F02-1, and the gate 22F02 may be directly aligned with the back gate 22F02-1 from above, as shown in FIG. 22H. The back gate 22F02-1 can be processed from the pre-processed wafer or the surface metal layer of the 808 layer, or an oxide layer can be deposited on the surface of the metal layer to bond the wafers (wafer not shown) as the back gate pole gate oxide.

During the normal manufacturing process of the component layers according to some examples of the present invention, each new layer must be aligned with the next layer using previously machined alignment marks as shown in FIG. 8 . Sometimes, the alignment of one layer can be used to align multiple layers above, and sometimes a new layer must also have alignment marks, which are used to align with other layers above in subsequent manufacturing steps. So layer 804 must be aligned with layer 802, layer 806 must be aligned with layer 804, and so on. Another advantage of the above process is that the cut-out layer can be made thin enough. In the subsequent drawing step (the drawing step is described in FIG. 22B ), the cut-out layer can be aligned with the alignment mark of the pre-processed wafer or layer 808, It can also be aligned with any of the following layers, such as 806, 804, 802, or other layers to make a 3D IC. Therefore, the "back gate" 22F02-1, which is part of the surface metal layer of the pre-processed wafer or layer 808, can be accurately aligned with 22F02 from below because the marks of all layers are aligned layer by layer. In this paper, the alignment accuracy is largely dependent on the marking equipment. For 45nm and below processes, the accuracy of overlay alignment is usually smaller than that of 5nm. Alignment requirements will become higher and higher with the use of scaling, and modern stepper motors can be more accurate than 2nm. Order of magnitude smaller alignment requirements can be achieved in TSV based 3D IC systems, as shown in Figure 12 and below, it is very difficult to achieve 0.5 micron overlay alignment accuracy. The connection between the surface gate and the back gate can be realized through surface vias or TLVs. In this way, the leakage current of the gate 22F02 and the back gate 22F02-1 can be further reduced, and the two gates can be connected to better cut off the transistor 22G20. At the same time, by dynamically changing the threshold voltage of the surface gate transistor - realized by independently changing the bias voltage of the back gate 22F02-1 - it is also possible to set a sleep mode, a normal sleep mode, and a fast sleep mode. In addition, to build an accumulation mode (full depletion) MOSFET transistor through the above process, it is only necessary to change the initial P-wafer 2102, or to form P-2106 on the outer edge of the 2104N+ layer into an N-wafer or N+ outer N-wafer on edge layer.

Another factor in producing surface transistors using this technology is the size of the vias or TLVs used to connect the surface transistors 22G20 to the metal layer and the underlying 808 layer of the pre-processed wafer. A generally reliable rule of thumb is that the size of the via hole is greater than 1/10 of the thickness of the layer it passes through. Since the layer thickness of the structure, as shown in Figure 12, is typically greater than 50 microns, the TSVs on the structure are typically greater than 10 microns. The thickness of the cut-out layer in FIG. 22A is less than 100nm, so the size of the via hole connecting the surface layer transistor 22G20 to the lower preprocessed wafer and the metal layer in the 808 layer should be less than 50nm. Due to the shrinking of the manufacturing process, the thickness of the cut-out layer and the size of the corresponding via hole connecting the underlying structure can also be reduced. For some advanced processes, the end thickness of the cut layer can be less than 10nm.

Another scheme for forming planar surface transistors with source and drain extensions is to process the processed wafer in FIG. 21B , as shown in FIGS. 29A-29G . FIG. 29A is the sliced layer on top of the preprocessed wafer or layer 808. After smart dicing, N+ 2104, P- 2106 and P+ 2108 are on the surface. The oxide layer of the auxiliary bonding wafer is not shown. The contact openings of the substrate P+ source 29B04 and the transistor isolation 29B02 are masked and etched as shown in Figure 29B. Using an additional mask layer, isolation regions 29B02, obtained by etching into the surface of the preprocessed wafer or layer 808, form isolation between transistors or groups of transistors, as shown in Figure 29C. Etching away the P+ layer between the transistors helps to conduct the P+ layer. A low temperature oxide 29C04 is then deposited and polished using chemical mechanical methods. Then, a thin grinding stop layer 29C06, which may be low temperature silicon nitride, is deposited to form the structure shown in FIG. 29C. The source 29D02, the drain 29D04, and the self-aligned gate 29D06 can be obtained by masking and etching on the thin grinding stop layer 29C06, followed by N+ bevel etching, as shown in FIG. 29D. Bevel (30-90 degrees, 45 degrees shown) or dual bevel etch can be achieved using wet chemical or plasma etch techniques. This process can form angled source and drain extensions 29D08. As shown in FIG. 29E, the deposition and densification of the subsequent low-temperature gate insulator 29E02, or the deposition and densification of the low-temperature microwave plasma silicon surface oxide, or the deposition and densification of the gate insulator by atomic layer deposition (ALD) can be performed using Make MOSFET gate oxide, then proceed with deposition of gate material 29E04, such as aluminum or tungsten.

In addition, the high-K metal gate structure can also be obtained using the following process. After an industry standard HF/SC1/SC2 clean to form an atomically smooth surface, a high-k insulating layer 29E02 is deposited. The semiconductor industry has chosen Hafnium-based insulating layers as the material of choice to replace SiO2 and silicon oxynitride. Hafnium-based group insulators include hafnium oxide and hafnium silicate/hafnium silicon oxynitride. Hafnium oxide, HfO2, has a dielectric constant about twice that of hafnium silicate/hafnium silicon oxynitride. (HfSiO/HfSiON k~15) The choice of metal is the key to the normal operation of the device. The metal instead of N+ polymer is used as the electrode of the gate, and the working threshold of about 4.2eV is required to ensure the normal operation of the device under the normal threshold voltage. In addition, the metal used as the gate electrode instead of the P+ polymer requires a working threshold of about 5.2eV to ensure normal operation. TiAl and TiAlN-based metal groups can be used to increase the work function of metals from 4.2eV to 5.2eV.

As shown in FIG. 29F , after the metal gate 29E04 is chemically mechanically polished, the stop layer 29C06 is polished with nitride to obtain the structure. PMOS transistors can be constructed through the above process, only need to change the initial P-wafer or 2104N+ layer on the outer edge of the P-, N-wafer or N-wafer on the P+ outer layer; and the N+ Layer 2104 was changed to a P+ layer. Similarly, if P+ is changed to N+, layer 2108 will also change in the event that substrate contacts are used.

Finally a thick oxide layer 29G02 is deposited and the contact openings are masked and etched ready for connection to the transistors as shown in Figure 29G. The figure also shows that the layer-cut silicon via hole 29G04, after masking and etching process, provides connection for the surface transistor circuit to the bottom layer 808 interconnection circuit 29G06. This process can form a single-crystal surface MOS transistor, which can be connected to the underlying multi-metal layer semiconductor components without exposing the underlying components and interconnection circuit metals to high temperatures. These transistors can be used as antifuse programming transistors of layer 807, connected with pre-processed wafer or layer 808 to form a monolithic 3D IC, or used for other functions of 3D integrated circuits. These transistors can be regarded as planar OSFET transistors, that is, the current in the transistor channel is horizontal. The above transistors, including other transistors in this document, can be horizontal transistors, horizontal orientation, or lateral transistors. Another advantage of this process is that the intelligent cutting H+, or other atomic doping steps are completed before the gate of the MOS transistor is formed, which can avoid damaging the gate function. In addition, to build an accumulation mode (full depletion) MOSFET transistor through the above process, it only needs to change the initial P-wafer, or form P- on the outer edge of the 2104N+ layer to become an N-wafer or N+ outer edge N-wafer on layer. Alternatively, a back gate similar to that of FIG. 22H can be used.

Another method is to use pre-processed wafers for layer dicing, as shown in Figure 23. Figure 23A is a schematic diagram of layer dicing using pre-processed crystals; N-wafer 2302 can process a buried layer N+ 2304, which can be realized through doping and opening, and can also be achieved through shallow N+ doping after N-cumulative crystal growth. Complexity and diffusion are realized. FIG. 23B is a pre-processed wafer, which can be used for layer cutting after deposition or growth of oxide 2308. After doping atoms, such as H+, a cutting plane 2306 for smart cutting can be prepared under the N+ region. The layer dicing process can now be performed to process the preprocessed single crystal N- silicon and N+ layers, which are located on the preprocessed wafer or layer 808 .

24A-24F are schematic diagrams of forming the top junction field effect (JFET) planar transistor. Figure 24A shows the structure formed after layer dicing on the pre-processed wafer or layer 808. So after the Wisdom Cut, N+ 2304 appeared on the surface, now labeled 24A04. The surface transistor source 24B04 and the drain 24B06 pass through the isolation layer connecting the gate 24B02 and the transistor 22B08. The N+ in the specified area is etched away to form. This step is aligned with the surface of the pre-processed wafer or layer 808 so that the formed transistors can form good connections with the pre-processed wafer or layers below the 808 layer. Additional masking and etching steps are then performed to remove the N-layer between the transistors, as shown in Figure 24C02, resulting in a better transistor isolation layer as shown in Figure 24C. Figure 24D is an alternative shaping method for P+ region 24D02 for processing JFET gates. In this approach, it may be necessary to turn on P+ using laser or other optical slow cooling methods. FIG. 24E shows how to perform laser annealing on the preprocessed wafer or the upper part of the 808 layer to reduce heat transfer. After the thicker oxide deposition 24E02, a layer of aluminum 24D04 or other reflective material will be added to the reflective layer. Laser 24D06 anneals the P+ 24D02 doped regions after masking and etching the openings 24D08 of the reflective layer and reflects most of the laser energy 24D06 away from the preprocessed wafer or above the 808 layer. Typically, the area of the open region 24D08 is less than 10% of the entire wafer area. In addition, a layer of copper 24D10, or a layer of reflectivity, or other reflective material, can be processed onto the pre-processed wafer or 808 layer, so that the unwanted laser energy can be reflected away from the 24D06 without heat transfer to the pre-processed wafer. processing on wafer or 808 layer. Layer 24D10 can also be used as a ground plane or a conductive back gate when molding components and circuits. Of course, the layer 24D10 can also be processed with openings, which can be used to build subsequent vias connecting the second surface cut-out layer and the pre-processed wafer or the 808 layer. The same reflective laser annealing or other optical annealing techniques can be used to anneal any of the above structures so that the gate of the transistor can be doped and turned on during the second layer cutting process. Additionally, oil absorbing materials, and/or other luminescent materials, may be used in the laser or other optical annealing methods described above. As shown in FIG. 24E-1, the light energy absorbing layer 24E04 can be amorphous carbon, which can be deposited or sprayed at low temperature to the area requiring laser annealing, and then masked and etched accordingly. In this way, minimal laser or other optical energy can be used to effectively anneal the area, turn on doped materials, and minimize thermal stress on the reflective layers 24D04 & 24D10, pre-wafer or 808 layers. Laser annealing can be used on the entire wafer surface, or on the area where the gate circuit is located, in order to further reduce the total heat and ensure that it will not cause damage to the underlying layer.

The structure shown in FIG. 24F is obtained after the following processing formula, laser reflective layer 24D04 etching, deposition, masking, etching thick oxide layer 24F04 to obtain opening contacts 24F06 and 24F02, deposition and partial etching (or chemical mechanical polishing) (CMP)) Aluminum (or other metal to get a Schottky or Ohmic contact at 24F02) forms the 24F06 contact and gate 24F02. If necessary, the N+ contact 24F06 and the gate contact 24F02 can be masked and etched separately, so that different metals can be deposited on it to obtain a Schottky or Ohmic contact on the gate 24F02, and the N+ contact 24F06 to get an ohmic connection. The thick oxide layer 24F04 is a non-conductive insulating material that also fills the etched gaps 24B08 and 24B09 between the surface transistors, and other isolation materials such as silicon nitride may be used. Surface transistors are finally surrounded by isolating insulating materials. Unlike traditional bulk integrated circuit transistors, traditional transistors are processed on a single-crystal silicon wafer and surrounded only by non-conductive insulating materials. This process can form a single crystal surface JFET transistor, which can be connected to the underlying multi-metal layer semiconductor component without exposing the underlying component to high temperature.

In another version of the above flow, transistor technology - pseudo-MOSFET, can be used, using a molecular layer that is covalently grafted to the channel region between the drain and source. This process can be carried out at relatively low temperatures (less than 400 degrees Celsius).

Another method is to use pre-processed wafers for layer dicing, as shown in Figure 25. Figure 25A is a schematic diagram of layer dicing using pre-processed crystals; N-wafer 2502 can process a buried layer N+ 2304, which can be realized through doping and opening, and can also be achieved through the shallow N+ layer after N-cumulative crystal growth 2508 Doping and diffusion are achieved. A P+ layer 2510 is additionally processed on the surface. The P+ layer 2510 can again be processed using doping and turning on, or P+ cumulative growth. 25B is a pre-processed wafer, which can be used for layer cutting after deposition or growth of oxide 2512. After doping atoms, such as H+, a cutting plane 2506 for intelligent cutting can be prepared under the N+ region 2504. . The layer slicing process can now be performed to process the preprocessed monocrystalline silicon, doped with N- and N+ layers, on top of the preprocessed wafer or layer 808 .

26A-24E are schematic diagrams of the formation of the upper junction field effect (JFET) planar transistor (with reverse bias gate or double gate). Figure 26A is a pre-processed wafer or cut out layer on top of layer 808, after smart dicing, N+ 2504 is on the surface. The surface transistor source 26B04 and the drain 26B06 pass through the isolation layer connecting the gate 26B02 and the transistor 26B08. The N+ in the specified area is etched away to form. This step is aligned with the surface of the pre-processed wafer or layer 808 so that the formed transistors can form good connections with the pre-processed wafer or layers below the 808 layer. Afterwards, through masking and etching, the N- between the transistors 26C12 is removed to make it contact with the buried P+ layer 2510 now. Another masking and etching step is then performed to remove the P+ layer 2510 between the transistors, thereby obtaining complete isolation as shown in Figure 26C. Figure 26D is an alternative shaping method of the shallow P+ region 26D02 for constructing the gate. In this approach, laser annealing may be required to turn on P+. The structure shown in Figure 26E is obtained by the following steps, deposition and etch/CMP of a thick oxide layer 26E04, deposition and etch back of aluminum (or other metal, at 26E02 to obtain the best Schottky or ohmic contact), to obtain a contact Points 26E06, 26E12 and gate 26E02. If necessary, the N+ contact 26E06 and the gate contact 26E02 can be masked and etched separately, so that different metals can be deposited thereon to obtain a Schottky or Ohmic contact on the gate 26E02, and the N+ contact 26E06 & ohmic connection on 26E12. The thick oxide layer 26E04 is a non-conductive insulating material that also fills the etched gaps 26B08 and 26B09 between the surface transistors, and other isolation materials such as silicon nitride may be used. Contact 26E12 allows the addition of a transistor back gate, or can be connected to gate 26E02 to form a dual gate JFET. Alternatively, back gate connections may be included in the preprocessed wafer or layer 808, connecting layer 2510 from below. This process can form a single crystal surface ultra-thin body JFET transistor with back gate or double gate function, which can be connected to the underlying multi-metal layer semiconductor components without exposing the underlying components to high temperature.

Another method is to use pre-processed wafers for layer dicing, as shown in Figure 27. FIG. 27A is a schematic diagram of layer dicing using preprocessed crystals; an N+ wafer 2702 is processed with a buried layer, which is realized by ion implantation and open annealing, and can also be constructed by diffusion to build a vertical structure, and NPN blocks (or PNP block) bipolar transistor. Cumulatively grown layers can be used to build doped multilayer structures. Starting with the P layer 2704, then the N- layer 2708, and finally the N+ layer 2710, which are finally turned on by annealing to a higher turn-on temperature. FIG. 27B is a pre-processed wafer, which can be used for layer cutting after deposition or growth of oxide 2712. After doping atoms, such as H+, it can be cut out in the N+ region ready for smart dicing 2706. The layer dicing process can now be performed to process the preprocessed layer, which is on top of the preprocessed wafer or layer 808 .

28A-E are schematic diagrams showing the formation of surface bipolar transistors. FIG. 28A is the sliced layer on top of the preprocessed wafer or layer 808. After smart dicing, N+28A02 (part of 2702) is on the surface. Usually at this point, there is one giant transistor covering the entire wafer. The following are multiple etching steps, as shown in FIGS. 28B-28D , after the giant transistor is cut and divided as required, it is aligned with the underlying pre-processed wafer or layer 808. The etch step also exposes the different layers comprising the bipolar transistor, making contact with the emitter 2806, base 2802, and collector 2808, and then etch down to the surface oxide layer of the pre-processed wafer or layer 808, Figure 28D Transistor isolation. The surface N+ doped layer 28A02 can be masked and etched as shown in FIG. 28B to form an emitter 2806 . Then, the P 2704 and N-2706 doped layers can be masked and etched as shown in FIG. 28C to form the base 2802 . Subsequently, the collector layer 2710 is masked and etched until the surface oxide layer of the pre-processed wafer or layer 808 to achieve transistor isolation 2809 in FIG. 28D. The entire structure can be covered with a low temperature oxide 2804, the oxide is leveled using CMP, then masked and etched to achieve the contacts of the emitter 2806, base 2802 and collector 2808 shown in Figure 28E. The thick oxide layer 2804 is a non-conductive insulating material that fills the etched gaps 2809 between the surface transistors, and other isolation materials such as silicon nitride can be used. The process enables the formation of single-crystal surface bipolar transistors that can be connected to underlying multi-metal semiconductor components without exposing the underlying components to high temperatures.

The obtained bipolar transistor shown in Fig. 27 and Fig. 28 can be used to form analog or digital BiCMOS circuit, and CMOS transistor is positioned at substrate primary crystal layer 802 and preprocessed wafer or layer 808, and bipolar transistor can be arranged in cutting out the surface layer.

Another type of device can be constructed at high temperature before layer dicing to the substrate with metal interconnect circuits, and then finished at low temperature after layer dicing to junction-less transistor (JLT). For example, in the deep sub-micron process, copper plating is used, so high temperatures above about 400 degrees Celsius can be achieved, and low temperatures are at and below 400 degrees Celsius. The structure of the junctionless transistor avoids the sharp layered junctions required in the scaling of silicon technology, and can build a thicker gate oxide layer, which has performance comparable to that of traditional MOSFET transistors. Junctionless transistors are also known as junctionless nanowire transistors, or gate selection resistors, or nanowire transistors, see Nature Nanotechnology, 21 February 2010, published by Jean-Pierre Colinge et al. When building a junctionless transistor, the transistor channel can be a thin solid sheet of uniformly heavily doped single crystal silicon. The channel can be doped at the same concentration as the source and drain. The considerations are that the nanowire channel must be thin enough and narrow enough to fully utilize the carriers when the device is off, and the channel must be doped high enough to generate the required current when the device is on. These considerations can lead to little room for process variation, limiting channel thickness, width, dopant concentration required for gate work function, and gate oxide thickness.

One of the challenges of junctionless transistor devices is to minimize the leakage of the closed channel when the gate bias is zero. In order to improve the control of the gate to the transistor channel, the channel can be non-uniformly doped, the doping with the highest concentration is closest to the gate, and the doping of the channel is lighter and farther than the gate electrode. For example, junctionless transistor channels with 2, 3, or 4 gates are doped more lightly in the middle than at the edges. In this way, the leakage current of the work function of the grid is low and controlled. As shown in Figures 52A and 52B, under logarithmic and linear scaling, respectively, the simulated drain to simulated source current I, as a function of the gate voltage V, to represent the doping of different junctionless transistor channels, where The total thickness of the n-channel is 20 nm. Of the 4 bar curves in each graph, 2 correspond to uniformly doped 20nm channels to concentrations of 1E17 and 1E18 atoms/cm3. The analog results shown by the remaining 2 plug-in curves are that the 20nm channel consists of two 10nm-thick doped layers respectively. In the legend for the remaining 2 bar curves, the first number corresponds to the portion of the 10nm layer closest to the gate electrode. For example, the curve D=1I18/1I17 indicates that the part of the 10nm channel doped with a concentration of 1E18 is the closest to the gate electrode, while the part doped with a concentration of 1E17 in the 10nm channel is farther away from the gate electrode. In FIG. 52A, curves 5202 and 5204 correspond to D=1I18/1E17 of the doping pattern, respectively. According to FIG. 52A, when V=0v, the leakage current of the doped region D=1E18/1E17 is 50 times lower than that of the opposite doped region D=1E17/1E18. Similarly, in FIG. 52B, curves 5206 and 5208 correspond to D=1I18/1E17 of the doping pattern, respectively. In Fig. 52B, when V=1v, the I of the two doped regions differ only by a few percentage points.

The doping of the junctionless transistor channel can be done uniformly, in layers, or in separate layers. Transistor channels may also be constructed without doped monocrystalline silicon, such as polysilicon, other semiconducting, insulating, or conducting materials, such as graphite or other graphitic materials, or using combinations of similar or different materials from other layers. For example, the center of the channel can consist of a layer of oxide, or lightly doped silicon, and the edges can be heavily doped single crystal silicon. This can improve the control effect of the resistor's gate in the off state, and may also increase the pass current due to the strain effect of other layers in the channel. Straining techniques can also be used for capping and upper and lower insulating materials, as well as surrounding transistor channels and gates. Lattice modification can also be used to stretch silicon, such as embedded SiGe doping and annealing. The interface of the transistor channel can be rectangular, circular, or elliptical in order to improve gate-to-channel control. In addition, in order to achieve the best mobility of P-channel non-junction transistors during 3D layer cutting, before bonding, the donor wafer can be rotated 90 degrees relative to the acceptor wafer, which is beneficial to <110> Formation of P-channels in the silicon plane direction.

In order to build an n-type 4-sided gate-controlled junctionless transistor, the silicon wafer needs to be pretreated, and then layered as shown in FIGS. 56A-56G . These processes may need to be performed at temperatures above 400°C for mating because the layers have not yet been cut to the substrate with the metal interconnect circuitry. As shown in Figure 56A, an N- wafer can be processed with a layer N+ 5604A, which can be achieved by doping and turning on, or by N+ cumulative growth, or by forming a deposited layer on heavily N+ doped polysilicon. Gate oxide 5602A can be grown before or after doping to a thickness approximately half of the desired final surface gate oxide thickness. Figure 56B is a pre-processed wafer, which can be used for layer cutting. After doping atoms 5606, such as H+, a plane 5608 can be prepared in the N-region 5600A of the substrate, and then undergo plasma or other surface treatment to form The oxide surface of the wafer oxide layer is used for bonding of oxides. Another wafer is processed as above, but not doped with H+, and then as shown in Figure 56C, the two wafers are bonded for layer cutting out of pre-processed single crystal silicon N- and N+ layers and half gates Oxide layer, in a similar pre-treatment, but cut out layers undoped N- wafer 5600 and N+ layer 5604 and oxide layer 5602. The surface wafer is sliced and separated from the underlying wafer. In this way, the surface wafer can also be used to process and rework more layers to build the resistive layer. The remaining surface wafer N- and N+ layers are chemically mechanically polished until a very thin N+ silicon layer 5610 is obtained, as shown in FIG. 56D . This thin N+ doped silicon layer 5610 has a thickness between 5-40nm and finally forms a resistor with gate control in 4 directions. The two "half" gate oxides 5602, 5602A can now be bonded together to form the gate oxide 5612, which is ultimately processed into the surface gate oxide of the junctionless transistor, as shown in Figure 56E. A high temperature anneal can be used to remove residual oxide or surface charge.

Alternatively, to construct the bottom wafer in Figure 56C, the N+ layer 5604 can be used to build heavily doped polysilicon, and the half gate oxide 5602 deposited or grown prior to layer dicing. The bottom wafer N+ silicon or poly layer 5604 will eventually become the upper gate of the junctionless transistor.

As shown in FIGS. 56E-56G , the wafer is conventionally processed, and the temperature needs to be higher than 400 degrees Celsius to prepare a processed "shell" wafer 808 that can be sliced into a junctionless transistor structure. A thin layer of oxide can be grown to protect the surface of the thin resistive silicon layer 5610, and then the parallel conductive lines 5614 with repeated spacing on the thin resistive layer can be mask-etched, as shown in FIG. 56E, and then the photolithography is cleaned. glue. This thin oxide layer, if any, can be removed in a diluted hydrofluoric acid (HF) solution, and then a conventional oxide layer 5616 and a polysilicon layer 5618, which can be doped or undoped, can be deposited, as shown in the figure 56F. Perform chemical and mechanical polishing (CMP) to planarize the polysilicon, and grow or deposit a thin oxide layer 5620 for low temperature oxide-oxide wafer bonding in the next step. Polysilicon 5618 can be additionally doped, either before or after CMP. Polysilicon is finally processed into the bottom and side gates of junctionless transistors. Figure 56G is a pre-processed wafer, which can be used for layer cutting. After doping atoms 5606, such as H+, a "cut out plane" 5608G can be prepared in the N- region 5600 of the substrate, and then undergo plasma or other surface treatment, Form the oxide surface of the wafer oxide layer for bonding of oxides. The acceptor wafer 808 has logic transistors and metal interconnection circuits. After pretreatment, it can be used for low-temperature oxide-oxide wafer bonding and surface oxide surface treatment. The bonding is shown in FIG. 56H. After the surface donor wafer is sliced, it is separated from the lower acceptor wafer 808, and the surface N-substrate is removed by CMP. Metal wiring straps 5622 in housing 808 are shown in Figure 56H.

Figure 56I is a top view of the wafer, which is the same as step 56H, and has two cross-sectional views I and II. N+ layer 5604, which ultimately forms the top gate of the resistor, and top gate oxide 5612 will control one side of resistor line 5614, bottom and side gate oxide 5616 and poly bottom and side gate 5618 control the other three sides of resistor 5614 side. The logic housing wafer 808 has an upper oxide layer 5624 that wraps the top metal routing strips 5622, as indicated by the outer dashed lines in the top view.

In FIG. 56J, the grinding stop layer 5626 can be deposited on the surface layer of the wafer using materials such as oxide or silicon nitride, and the isolation opening 5628 is masked and etched to the depth of the oxide layer 5624 of the shell 808, so that it can be completely isolated transistor. The isolation opening 5628 is completely filled with low temperature oxide, and then polished flat by chemical and mechanical polishing (CMP). The masking and etching of the top gate 5630 are shown in Figure 56K, and then the etching opening 5629 is filled with low-temperature filling oxide deposition, polished and leveled by chemical and mechanical (CMP), and then another layer of oxide is deposited to realize the wiring metal layer isolation.

Contacts are masked and etched as shown in Figure 56L. The gate contact 5632 is masked and etched such that the contact is etched all the way through the top gate layer 5630. During the metal layer opening masking and etching, the gate oxide is also etched such that the top gate 5630 and bottom 5618 The gate is connected. Contacts 5634 connecting the two electrodes of the resistive layer 5614 are also masked and etched. Then, the through-layer vias 5636 to the housing wafer 808 and the metal wiring strips 5622 are masked and etched.

As shown in Figure 56M, the metal line 5640 is defined by a mask and etched, filled with barrier metal and copper interconnection circuit, processed by CMP and conventional metal interconnection circuit scheme, and completes contact via hole 5632 and surface layer 5630 and bottom layer 5618 gate Simultaneous connection, the connection of the two electrodes 5634 of the resistor 5614, and the connection with the metal interconnection circuit inserting strip 5622 of the shell wafer 808. This process can form a single crystal 4-sided gate junctionless transistor, which can be connected to the underlying multi-metal layer semiconductor component without exposing the underlying component to high temperature.

Alternatively, as shown in FIGS. 96A-96J , an N-channel 4-sided gated junction-less transistor (JLT) can be constructed during the corresponding 3D IC fabrication process. The 4-sided gated JL can also become a fully gated JLT, or a silicon nanowire JLT.

As shown in FIG. 96A, a P- or N-substrate donor wafer 9600 can be processed to include wafer-sized N+ doped silicon layers 9602 and 9606, and wafer-sized N+ SiGe layers 9604 and 9608. Layers 9602, 9604, 9608 can be cumulatively grown and then carefully processed in terms of thickness and stoichiometry to maintain defect density due to lattice mismatch between Si and underlying SiGe. The stoichiometry of SiGe may vary from layer to layer, resulting in different etch rates, as detailed below. Some techniques for achieving different etch rates include: Keeping the thickness of the SiGe layer below the critical thickness for defect formation. An oxide layer 9613 can be deposited on the surface of the donor wafer 9600, so that oxide wafer bonding can be performed. These processes may need to be performed at temperatures above 400°C for mating because the layers have not yet been cut to the substrate with the metal interconnect circuitry. A wafer-sized layer can provide a continuous layer of material or combination of materials across the entire wafer to the edge of the wafer, possibly with approximately uniform thickness. If a wafer-sized layer contains dopants, the dopant concentration will generally be consistent in the x and y directions, but may vary in the z direction (perpendicular to the wafer surface).

As shown in FIG. 96B , the layer-slicing dividing plane 9699 (shown as a dotted line) may be implemented on the donor wafer 9600 by helium doping or other aforementioned methods.

As shown in FIG. 96C , both the surface layers of the donor wafer 9600 and the acceptor wafer 9610 can be processed for wafer bonding, and then the donor wafer 9600 is reversed to align with the alignment marks on the acceptor wafer 9610 (not shown). ) for alignment and bonding at low temperatures (approximately below 400 degrees Celsius). The oxide layer 9613 on the surface of the donor wafer and the acceptor wafer 9610 are then atomically bonded, as shown in diagram 9614 .

As shown in FIG. 96D, the portion of the P-donor wafer substrate 9600 that lies above the layer-slicing demarcation plane 9699 can be removed by dicing and grinding, etching, or other low temperature methods as previously described. The CMP process can be used to remove the remaining P- layer until the N+ silicon layer 9602 is reached. Then use the process of ion implantation of atoms, such as helium, to form a layer cutting division plane, and then cut or thin, or it can be called "ion cutting". Acceptor wafer 9610 can also be processed using methods similar to wafer 808, see FIG. 8 for the processing of wafer 808.

As shown in Figure 96E, the N+ silicon stack and the N+ SiGe layer can be processed into transistors or channels, and then the gate part can be printed and scribed and the plasma/RIE of the N+ silicon layers 9602 & 9606 and the N+ SiGe layers 9604 & 9608 obtained by etching. As a result, N+SiGe9616 stacks and N+SiGe9618 layers can be obtained. The isolation between the stacks can be completely filled with low temperature fill oxide 9620, and then smoothed by chemical physical polishing (CMP). This completely separates the individual transistors. The ends of the pile are drawn in the figure for ease of understanding.

As shown in Figure 96F, the final grouped or common gate portion 9630 can be obtained using printed scribe and oxide etch. This exposes the sides of the transistor channel and gate region stack, consisting of alternating layers of N+Si 9618 and N+SiGe 9616, ultimately forming grouped or common gate regions 9630. The ends of the pile are drawn in the figure for ease of understanding.

As shown in FIG. 96G, the exposed N+SiGe layer 9616 can be removed by a selective etch recipe without damaging the N+Si layer 9618. This forms a voided N+ silicon region 9618 in the final grouped or common gate region 9630 . The above etching recipe is in "High Temperature 5nm Radius Twin Silicon Nanowire MOSFET (TSNWFET): Fabrication, Characteristics and Dependencies on a Si Wafer Stack", Proc.IEDM Tech by S.D.Suk et al., pp. 717-720, 2005 published in the year. The N+SiGe layer farthest from the top edge can be structured stoichiometrically such that this layer (region) (e.g., N+SiGe layer 9608) achieves a slightly faster etch rate relative to other layers closer to the top (e.g., N+SiGe layer 9604), and can make the gate lengths of the final two stack transistors the same. The ends of the pile are drawn in the figure for ease of understanding.

As shown in Figure 96H, there is an optional step to reduce the surface weeding, round the edges, and thin the diameter of the N+ silicon region 9618, which is exposed in the cluster or common gate area, and use low temperature oxidation , and then etched with HF to remove the oxide layer. This step can be repeated multiple times. For bare N+ silicon surfaces, helium can also be added during oxidation, or bonded using plasma treatment. In this way, a round silicon-like nanowire structure can be obtained to form the final gate-controlled channel 9636 of the transistor. The ends of the pile are drawn in the figure for ease of understanding.

As shown in Figure 96I, a low temperature based gate insulator can be deposited and densified for use as the gate oxide for junctionless transistors. In addition, the silicon surface of the gate control channel 9636 of the final transistor can be oxidized by low-temperature microwave ion beam as JLT gate oxide or HKMG gate oxide can be formed by atomic layer deposition (ALD) technology. Low temperature gate material 9612 deposition, such as P+ doped amorphous silicon, can also be performed. In addition, the high-K metal gate structure can also be obtained using the following process. A CMP process is performed on the gate material deposition. The ends of the pile are drawn in the figure for ease of understanding.

Figure 96J shows the complete JLT transistor stack formed in Figure 96I, without the oxide layer for clarity, and also includes the cross-sectional cut I in Figure 96I. The gate 9612 surrounds the transistor gated channel 9636, and each group of transistor silicon is isolated from the other stacks by an oxide 9622. The source and drain connections of the transistor stack can be moved to the N+ Si 9618 and N+ SiGe 9616 regions, which are not covered by the gate 9612.

The contacts with the source, drain and gate of the four-sided gate-controlled JLT can be processed using traditional back-end process (BEOL), and the connection between the formed JLT and the receiver wafer can be connected to the receiver through the through-layer via (TLV). On the main wafer metal interconnection circuit pad. This process can form a single-crystal silicon channel 4-sided gate junctionless transistor, which can be connected to the underlying multi-metal layer semiconductor component without exposing the underlying component to high temperature.

The P-channel 4-sided gate-controlled JLT can be constructed using the above-mentioned N+ silicon layers 9602 and 9608 as P+ doped materials, and the work function of the gate metal 9612 can correspondingly close the P-channel when the gate voltage is 0.

The process flow is shown in Figure 96A-J. The key steps include the molding of 4-sided gate-controlled JLT and 3D stack components. It is not difficult for senior personnel in this industry to imagine that the process can be improved on this basis. For example, steps and additional material/areas can be added to increase the stress on the JLT. Alternatively N+SiGe layers 9604 and 9608 may comprise P+SiGe or undoped SiGe, and a selective abrasive solution formulation. Additionally, more than 2 layers of chips or circuits can be added on the 3D stack. At the same time, silicon nanowire transistors can also be constructed using a variety of methods. The above content is explained on pages 1-4 and pages 7-9 of "High Performance and High Consistency Fully Gate-Controlled Silicon Nanowire MOSFET and Scaling Down", the book is "Electronic Components Conference (IEDM)" 2009 2009, IEEE, by Bangsaruntip.S, GM; Majundar.A, et al., December 2009. (Book original title: High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling) (“Bangsaruntip”) and the above-mentioned high-performance_5nm radius double silicon nanowire MOSFET (TSNWFET): on Si wafer stack Manufacture, Characteristics and Dependencies, in Proc. IEDM Tech by D. Suk, S.-Y. Lee, S.-M. Kim, ("Suk") et al., pp. 717-720, published 2005. The contents of the above disclosures are quoted in this document as a reference. The techniques in the above publications can be used to fabricate four-sided gated JLTs.

Alternatively, as shown in Figures 57A-57G, an N-channel 3-side gated junction-less transistor (JLT) can be constructed during the corresponding 3D IC fabrication process. As shown in Figures 57A and 57B, the preprocessed silicon wafer can be sliced. These processes may need to be performed at temperatures above 400°C for mating because the layers have not yet been cut to the substrate with the metal interconnect circuitry. As shown in FIG. 57A, an N- wafer 5700 can be processed with a layer N+ 5704 by doping and turning on, or by N+ cumulative growth, or by forming a deposited layer on heavily N+ doped polysilicon. Barrier oxide 502 can be grown before doping to protect the silicon wafer during doping and provide an oxide layer for subsequent wafer-to-wafer bonding. Figure 57B is a pre-processed wafer that can be used for layer cutting. After doping 5707 atoms, such as H+, it can be prepared to cut out a plane 5708 in the N- region 5700A of the substrate, and then undergo plasma or other surface treatment to form The oxide surface of the wafer oxide layer is used for bonding of oxides. The acceptor wafer or shell wafer 808 has logic transistors and metal interconnection circuits. After pretreatment, it can be used for low temperature oxide-oxide wafer bonding and surface oxide surface treatment. The bonding is shown in Figure 57C. After the surface donor wafer is diced, it is separated from the lower acceptor wafer 808, and the surface N- substrate is processed through CMP to the N+ layer 5704 to form a junction-free transistor surface gate layer. The metal wiring strips 5706 in the acceptor wafer or housing 808 are shown in Figure 57C. For the sake of simplicity and clarity, the donor wafer oxide layer 5702 and the acceptor wafer or shell 808 oxide layer are not drawn separately in the figure, as shown in FIGS. 57D-57G .

A thin layer of oxide can be grown to protect the surface of the thinner transistor silicon layer 5704, then the thin transistor channel element 5708 can be mask etched, as shown in Figure 57D, and the photoresist can then be cleaned. After the thin oxide layer is washed away with dilute HF solution, a gate insulator based on low temperature can be deposited and densified to be used as the gate oxide layer 5710 of the junctionless transistor. In addition, low-temperature microwave ion beam oxidation can be used to oxidize the surface of the silicon crystal to form the gate oxide layer 5710 of the junctionless transistor, or the HKMG gate oxide can be formed using atomic layer deposition (ALD) technology.

Low temperature gate material 5712 deposition, such as P+ doped amorphous silicon, can also be performed, as shown in FIG. 57E. In addition, the high-K metal gate structure can also be obtained using the above-mentioned process. Afterwards, the gate material 5712 is cross-processed on the surface of the transistor channel component 5708 and the side gate 5714 through masking and etching, and the crossing is usually vertical, as shown in FIG. 57F .

Afterwards, the entire structure is covered with a low temperature oxide layer 5716, the oxide layer is chemically and mechanically polished, and contacts and metal interconnection circuits are masked and etched, as shown in FIG. 57G. A gate contact 5720 is used to connect to the gate 5714 . The electrode contacts 5722 of the two transistor channels are respectively connected to the transistor element 5708 and the gate 5714 on both sides. Through-layer vias 5724 connect the transistor metal layer to the acceptor wafer or housing wafer 808 at the interconnect circuit 5706 . This process can form single-crystal silicon 4-sided gate-controlled junctionless transistors, which can be connected to the underlying multi-metal layer semiconductor components without exposing the underlying components to high temperatures.

Alternatively, as shown in Figures 58A-58G, an N-channel 3-side gated thin-side-up junctionless transistor (JLT) can be constructed in a corresponding 3D IC fabrication process. The junctionless transistor with the thin side up has the thinnest dimension when the channel cross-section is up (horizontally placed), and the cross-section is parallel to the surface of the silicon substrate. The thin-side-up junctionless transistor described above and below may also have the thinnest dimension when the channel cross-section is facing up (vertically placed), the cross-section being perpendicular to the surface of the silicon substrate. As shown in Figures 58A and 58B, the preprocessed silicon wafer can be sliced. These processes may need to be performed at temperatures above 400°C for mating because the layers have not yet been cut to the substrate with the metal interconnect circuitry. As shown in FIG. 58A, an N- wafer 5800 can be processed with a layer N+ 5804 by doping and turning on, or by N+ cumulative growth, or by forming a deposited layer on heavily N+ doped polysilicon. Barrier oxide 5802 can be grown prior to doping to protect the silicon wafer during doping and provide an oxide layer for subsequent wafer-to-wafer bonding. FIG. 58B is a pre-processed wafer, which can be used for layer cutting. After doping 5802 atoms, such as H+, it can be prepared to cut out a plane 5806 in the N- region 5800 of the substrate, and then undergo plasma or other surface treatment to form a wafer. The oxide surface of the circular oxide layer is used for bonding of oxides. The acceptor wafer 808 has logic transistors and metal interconnection circuits. After pretreatment, it can be used for low-temperature oxide-oxide wafer bonding and surface oxide surface treatment. The bonding is shown in FIG. 58C. After the surface donor wafer is sliced, it is separated from the lower acceptor wafer 808, and the surface N- substrate is processed to the N+ layer 5804 by CMP to form a junctionless transistor channel layer. Figure 58C shows the deposition of a CMP and plasma etch stop layer 5805, such as low temperature SiN on the oxide surface, on the surface of the N+ layer 5804. The metal wiring layer 5806 in the acceptor wafer or housing 808 is shown in Figure 58C. For the sake of simplicity and clarity, the donor wafer oxide layer 5802 and the acceptor wafer or shell 808 oxide layer are not drawn separately in the illustration, as shown in FIGS. 58D-58G .

After the transistor channel element 5808 has been masked and etched as shown in Figure 58D, the photoresist is removed. As shown in FIG. 48E, a low temperature based gate insulator is deposited and densified as the gate oxide layer 5810 of the junctionless transistor. In addition, low-temperature microwave ion beam oxidation can be used to oxidize the surface of the silicon crystal to form the gate oxide layer 5810 of the junctionless transistor, or the HKMG gate oxide can be formed using atomic layer deposition (ALD) technology. Low temperature gate material 5812 deposition, such as P+ doped amorphous silicon, may also be performed. In addition, the high-K metal gate structure can also be obtained using the above-mentioned process. Gate material 5812 is then masked and etched onto the surface of transistor channel element 5808 and side gate 5814. As shown in Figure 58G, the entire structure is covered with a low temperature oxide layer 5816, which is chemically and mechanically polished to level, and contacts and metal interconnects are masked and etched. A gate contact 5820 connects to the resistive gate 5814 (eg, front-to-back plane connection from other components, as in FIG. 58G ). The electrode contacts 5822 of the two transistor channels are respectively connected to the transistor channel element 5808 and the gate 5814 on both sides. Through-layer vias 5824 connect the transistor metal layer to the acceptor wafer or housing wafer 808 at the interconnect circuit 5806 . This process can form gate-controlled junction-free transistors with three thin sides of single-crystal silicon facing up, which can be connected to the underlying multi-metal layer semiconductor components without exposing the underlying components to high temperatures. Persons with only basic knowledge will easily understand the illustrations in Figures 57A-57G, and Figures 58A-58G (not enlarged). It is also easy for people to further imagine that various deformations can be produced. For example, the above-mentioned process of the combination 57A-57G can be used to manufacture a junctionless transistor, the height of the transistor channel is greater than the width, or the combination of 58A-58G The described process can be used to manufacture a junctionless transistor that is wider than it is tall. After reading this description, those skilled in the art will realize that the scope of the invention encompasses many modifications and variations. Therefore, this invention is not limited to the patent statement in the appendix.

Alternatively, as shown in Figures 61A-61I, a double-layer N-channel 3-side gated junction-less transistor (JLT) can be constructed in the corresponding 3D IC fabrication process. This structure increases the source and drain resistance by doping the contact surface at a higher concentration than the channel. Moreover, this structure can be used to build a 2-layer channel, and the channel closer to the gate has a higher doping concentration. As shown in Figures 61A and 61B, the preprocessed silicon wafer can be sliced. These pre-processing processes may need to be carried out at higher than 400 degrees Celsius for insertion, because the layer cutting has not yet been completed to the substrate with metal interconnection circuits. As shown in Figure 61A, N-wafer 6100 can be processed with double-layer N+. The doping concentration of the surface layer 6104 is lower than that of the bottom N+ layer 6103. This can be achieved through doping and opening, or through N+ cumulative growth, or a combination of methods. . Vertically doped layers or gradients can also be built using one or more depositions of in-situ doped amorphous silicon. Barrier oxide 6102 can be grown prior to doping to protect the wafer during doping and provide an oxide layer for subsequent wafer-to-wafer bonding. Figure 61B is a pre-processed wafer, which can be used for layer cutting. After doping 6107 atoms, such as H+, a "cut-out plane" 6109 can be prepared in the N- region 6100A of the substrate, and then undergo plasma or other surface treatment , forming the oxide surface of the wafer oxide layer for bonding of oxides.

The acceptor wafer or shell wafer 808 has logic transistors and metal interconnection circuits. After pretreatment, it can be used for low temperature oxide-oxide wafer bonding and surface oxide surface treatment. The bonding is shown in Figure 61C. After the surface donor wafer is sliced, it is separated from the lower acceptor wafer 808, and the surface N- substrate is processed to the N+ layer 6103 by CMP to form an N+ layer 6103 with a higher doping concentration. An etched hard film can be deposited on the surface of 6103 using low temperature silicon nitride 6105, including a thin oxide stress buffer layer. Metal interconnect circuit pads or straps 5706 in the acceptor wafer or housing 808 are shown in Figure 61C. For the sake of simplicity and clarity, the donor wafer oxide layer 6102 and the acceptor wafer or shell 808 oxide layer are not drawn separately, as shown in FIGS. 61D-61I .

The connection area of the source and the drain can be masked, the silicon nitride 6105 is etched away, and then the photoresist is removed. Partial or full silicon plasma etching can be performed, or the oxide can be etched with HF acid after low temperature oxidation, down to the thin layer 6103. As shown in Figure 61D, the double-layer channel was described and simulated in conjunction with 52A and 52B above. The thin layer 6103 formed by the above etching process is almost completely removed, and the resulting part 6103 is on the surface of 6104, and then on the surface of 6105. The complete layer 6103 is preserved below. The 6103 layer of the surface trench can be completely removed. This etch process will be used to adjust the wafer-to-wafer CMP deformation of the remaining donor wafer layers, eg 6100 and 6103, after layer removal of trenches with smaller thickness variations.

In FIG. 61E, photoresist 6150 defines the source 6151 (6103 region of one full thickness), drain 6152 (6104 of another full thickness) region of the junctionless transistor, channel 5153 (6130 and 6130 of partial thickness) 6104 of the full thickness).

The exposed silicon on layer 6104, as shown in FIG. 61F, can be plasma etched and the photoresist 6159 removed. This process will form the isolation between the devices and define the channel width of the junctionless transistor channel 6108.

As shown in FIG. 61G, a low temperature based gate insulator is deposited and densified as the gate oxide layer 6110 of the junctionless transistor. In addition, low-temperature microwave ion beam oxidation can be used to oxidize the surface of the silicon crystal to form the gate oxide layer 6110 of the junction-free transistor, or the HKMG gate oxide can be formed using atomic layer deposition (ALD) technology. Low temperature gate material 6112 deposition, such as doped amorphous silicon, can also be performed, as shown in FIG. 61G. In addition, the high-K metal gate structure can also be obtained using the above-mentioned process.

Afterwards, the gate material 6112 is cross-processed on the surface of the transistor channel component 6108 and the side gate 6114 through masking and etching, and the crossing is usually vertical, as shown in FIG. 61H . After completion, the entire structure can be covered with low-temperature oxide 6116, which can be flattened by CMP.

Thereafter, masking and etching of contacts and metal interconnection circuits are performed as shown in FIG. 61I. A gate contact 6120 is used to connect to the gate 6114 . The source/drain electrode contacts 6122 of the two transistors are respectively connected to the heavily doped layers 6103 on both sides, and then connected to the transistor channel element 6108 and the gate 6114 . Through layer vias 6124 connect the junctionless transistor metal layer and the acceptor wafer or housing wafer 808 at the interconnect circuit 6106 . The vias 6124 can be masked and etched separately to provide machining allowances for the other contacts 6122 and 6120 . This process can form single-crystal silicon double-layer 3-side gate-controlled junctionless transistors, which can be connected to multiple metal layer semiconductor components in the lower layer without exposing the lower layer components to high temperature.

Alternatively, as shown in Figures 65A-C, a 1-side gated junction-less transistor (JLT) can be built in the corresponding 3D IC fabrication process. A thin layer of heavily doped silicon layer 6503 can be obtained by layer-slicing the surface of the acceptor wafer or shell wafer 808. Using the aforementioned layer-slicing technique, the oxide layer 6501 of the donor wafer can be used to bond with the recipient wafer. The master or housing wafer 808 is oxide bonded. The doped layer 6503 cut out can be doped with N+, used as an N-structure junctionless transistor, or P+ doped, used as a P-structure junctionless transistor. As shown in FIG. 65B , the oxide layer isolation 6506 can be obtained by masking and etching on the N+ layer 6503 , and the subsequent low-temperature oxide deposition can be chemical-mechanical polished to the thickness of the channel silicon 6503 . Channel thickness 6504 can be adjusted at this step. The low temperature gate insulating layer 6504 and the gate metal layer 6505 can be deposited or grown by signing, followed by photolithographic printing and etching. As shown in FIG. 65C, a low temperature oxide layer 6508 can be deposited subsequently, which can also provide the mechanical stress required by the channel to increase the activity of carriers. Contact openings 6510 can then be machined for use as enabling electrodes for junctionless transistors. Those of ordinary skill can foresee that the use of the above methods is for reference only, and other cases and application scopes can be deduced based on the principles of this invention, and the scope of the invention is not limited by the rights statement in the appendix.

Since the surface transistors have been previously aligned with the underlying fabrication acceptor or housing wafer 808, processing of the vertical family of devices can now proceed. Vertical components can be processed by doping and annealing the monocrystalline silicon layer of the transistor, using the "smart dicing" layer cutting process, in which the upper temperature limit must not exceed the limit of the underlying prefabricated structure. For example, vertical MOSFET transistors, floating gate flash memory transistors, attached DRAMs, thyristors, bipolar and Schottky gate JFET transistors, and memory components. Junctionless transistors can also be constructed using a similar approach. The gates of vertical transistors or resistors can be controlled by memory or logic components, such as MOSFET, DRAM, SRAM, floating village, antifuse memory, floating body components, etc. The above components are located on the upper and lower layers or on the same layer of the vertical insert. For example, a vertical fully gate-controlled N-MOSFET transistor can be constructed as follows.

The donor wafer is pre-processed through the general layer dicing process shown in FIG. 39 . Obtaining a P-wafer 3902 can process a "buried" layer N+ 3904 by doping and turning on, or by shallow N+ doping and diffusion. After this process, a P-accumulated crystal growth layer 3906 is deposited, and finally another N+ layer 3908 is processed on the surface. The N+ layer 2510 can again be processed using doping and turning on, or N+ cumulative growth.

Figure 39B is a pre-processed wafer that can be cut into a conductive adhesive layer. After depositing a conductive barrier layer 3910 on the surface of the N+ layer 3908, such as TiN or TaN, and then doping atoms, such as H+, after that, it can be formed in the N+ region The lower part of 3904 is ready for cutting out plane 3912 of wisdom cutting.

As shown in Figure 39C, the acceptor wafer may be processed with an oxide pre-clean and deposited with a conductive barrier layer 3916 and Al-Ge layer 3914. The Al-Ge eutectic layer 3914 can form an Al-Ge eutectic bond together with the conductive barrier layer 3910, which is realized in the wafer bonding process of annealing and pressure, which is part of the layer dicing process. After that, the single crystal silicon is pretreated. The N+ and P- layers are sliced. Thus, a conductive path can be obtained on the surface metal layer 3920 of the housing 808 to connect to the bottom N+ layer 3908 of the diced donor wafer. Alternatively, the Al-Ge eutectic layer 3914 can be processed using copper to obtain a copper-copper or copper-barrier annealed pressure bond. Similarly, the conductive path to the donor wafer can be obtained by directly annealing and pressure-bonding the shell wafer metal line 3920 (made of copper and barrier metal) to the copper layer 3910, where most of the bonding surface is the copper of the donor wafer and the shell The oxide layer of the wafer, and the rest of the surface is an adhesion layer between the copper of the donor wafer and the copper and barrier metal of the housing wafer 808 .

40A-40I are schematic diagrams of forming the surface layer transistors of the vertical fully gate-controlled n-MOSFET. Figure 40A is the first step. After the above-mentioned conductive path layer cutting is completed, a CMP and plasma etching stop layer 4002 is deposited, such as low-temperature SiN, by depositing on the surface of the N+ layer 3904 . For simplicity, the conductively isolated overlying Al-Ge eutectic layers 3910, 3914, and 3916 are represented by conductive layer 4004, as shown in Figure 40A.

Figures 40B-H are vertical projections (eg, top views of horizontal and vertical interfaces) showing partial flow and vertical relationships. Transistors are square when viewed from above, but can be configured as rectangles for different widths and gate control effects. In addition, when viewed from above, the square transistor can be intentionally rounded to form a vertical cylinder, or the shape can be obtained in the subsequent processing process, and finally become a vertical tower. See FIG. 40B, the vertical transistor tower 4006 is mask drawn, and plasma/reactive ion etching (RIE) etched to the chemical mechanical polishing (CMP) stop layer 4004, N+ layers 3904 and 3908, and P- layer 3906, conductive The metal bonding layer 4004, up to the oxide layer of the housing wafer 808, and then the photoresist is removed, as shown in FIG. 40B. This definition and etching can then build up the N-P-N stack such that the bottom N+ layer 3908 is connected to the shell wafer metal layer 3920 through the conductive layer 4004 .

The area between the towers is partially made of oxide 4010 through a spin-on-glass hair (SPG) that is spun, solidified, and etched back, as shown in Figure 40C. Alternatively, a low temperature CVD void-fill oxide can be deposited, then CMP-polished and then selectively etched back to form the same oxide shape 4010 as shown in Figure 40C. The height of the oxide layer 4010 can be determined as follows: a small portion of the bottom N+ tower layer 3908 is not covered by the oxide layer. In addition, this step can also be obtained through an equivalent low temperature oxide CVD deposition and etch back process to form the isolation profile coverage of the bottom N+ tower layer 3908 .

In addition, the side gate oxide 4014 is constructed by low-temperature microwave oxidation technology, such as TEL SPA (Tokyo Electron Limited Slot Plane Antenna) oxygen free plasma, using aqueous compounds, such as diluted HF, to remove, and then as shown in Figure 40D Re-grow 4014.

A gate is then deposited, such as an equivalent doped amorphous silicon layer 4018, as shown in FIG. 40E. After that, a gate mask photoresist 4020 is drawn.

The etching of the gate layer 4018 should ensure that the isolation contour gate 4022 remains in the area not covered by the photoresist 4020 as shown in FIG. 40F. The full thickness of the gate layer 4018 should remain where it is covered by the resistor 4020, and the gate layer 4020 should be completely removed from between the towers. Finally, the photoresist 4020 is removed. This approach minimizes drain coverage of the gate and ultimately results in a clean contact connection to the gate.

As shown in Figure 40G, the gaps between the towers are filled and the towers are covered with an oxide layer 4030 by low temperature gap fill deposition and CMP.

In FIG. 40H , via contact 4034 to tower N+ layer 3904 is masked and etched, followed by masking and etching via contact 4036 to gate polysilicon 4024 .

The metal line 4040 is obtained by masking and etching, filled with isolation metal and copper interconnection circuit, and CMP polished using the normal interconnection circuit scheme, so as to complete the contact via connection with the tower N+ 3904 and the gate 4024, as shown in the figure 40I shown.

This process can form a MOS transistor on the surface of single crystal silicon, which can be connected to the underlying multi-metal layer semiconductor components, without exposing the underlying components and interconnection circuit metal to high temperature. These transistors can be used as the antifuse programming transistors of layer 807, connected with the wafer metal layer or layer 808 to form a monolithic 3D IC, as the transfer transistors on the wafer or layer 808, or the user FPGA, or with for other 3D semiconductor components.

In addition, the vertical fully gate-controlled junctionless transistor can also be constructed according to Figures 54 and 55. FIG. 54A is a schematic diagram of layer ablation using pre-processed crystals; an N- wafer 5402 can be processed into an N+ layer 5404 through ion implantation and turn-on, and can also be realized through N+ accumulated crystal growth. Figure 54B is a pre-processed wafer that can be cut into a conductive adhesive layer. After depositing a conductive barrier layer 5410 on the surface of the N+ layer 5410, such as TiN or TaN, and then doping atoms, such as H+, after that, it can be in the N+ region The lower part of 5404 is ready for cutting out plane 5412 of wisdom cutting.

The acceptor or housing wafer 808 can also be processed by oxide pre-cleaning and depositing a conductive spacer layer 5416 and layers of Al and Ge to form a Ge-Al eutectic bonding layer 5414. It is completed in bonding, which is part of the layer dicing process. Then, on the surface of the acceptor wafer or the shell wafer 808, the preprocessed single crystal silicon layer and an N+ layer 5404 shown in FIG. 54B are layered, as shown in FIG. 54C Show. The N+ layer 5405 can be polished to remove scratches left by the layer cutting process. Thus, a conductive path can be obtained on the metal layer 5420 on the surface of the acceptor wafer or housing 808 to connect to the N+ layer 5404 of the diced donor wafer. Alternatively, the Al-Ge eutectic layer 5414 can be processed using copper to obtain a copper-copper or copper-barrier annealed pressure bond. Similarly, conductive pathways to the donor wafer can be obtained by direct annealing and pressure bonding of the donor wafer or housing wafer metal lines 5420 (made of copper and barrier metal) to the copper layer 5410, where the majority of the bonding surface is the donor wafer The oxide layer of the copper and the shell wafer, and the remaining surface is the bonding layer between the copper of the donor wafer and the copper of the donor wafer or the shell wafer 808 and the barrier metal.

55A-55I are schematic diagrams of the formation of vertical fully-gated junction-free transistors above the preprocessed acceptor wafer or housing 808 in FIG. 54C. 55A shows the deposition of a CMP and plasma etch stop layer 5502, such as low temperature SiN, on the surface of the N+ layer 5504. For simplicity, the blocked overlying Al-Ge eutectic layers 5410, 5414, and 5416 are represented by conductive layer 5500 in FIG. 54C.

Similarly, Figures 55B-H are vertical projections showing partial flow and vertical relationships. When viewed from above, the junctionless transistor is square, but it can be configured as a rectangle to obtain different channel thicknesses, widths and gate control effects. In addition, when viewed from above, the square transistor can be intentionally rounded to form a vertical cylinder, or the shape can be obtained in the subsequent processing process, and finally become a vertical tower. Vertical transistor towers 5506 are mask drawn, and plasma/reactive ion etch (RIE) etched to chemical mechanical polish (CMP) stop layer 5502, N+ layers 5504 and 3908, conductive metal bonding layer 5500, all the way to the housing wafer 808 of the oxide layer, followed by removal of the photoresist, as shown in Figure 55B. This definition and etch creates N+ transistor channel stacks that are isolated from each other but conduct at the bottom of the N+ layer 5404 to the housing wafer metal layer 5420 .

The area between the towers is partially made of oxide 5510 through a spin-on glass (SPG) that is spun, cryogenically solidified, and etched back, as shown in Figure 55C. Alternatively, a low temperature CVD void filling oxide layer can be deposited, then CMP polished, followed by selective etch back to form the same shape 5510 as shown in Figure 55C. In addition, this step can also be obtained through an equivalent low-temperature oxide CVD deposition and etch-back process to form the isolation contour coverage of the N+ resistor tower layer 5504 .

In addition, the side gate oxide 5514 is constructed by low-temperature microwave oxidation technology, such as TEL SPA (Tokyo Electron Limited Slot Plane Antenna) oxygen free plasma, using hydrated compounds, such as diluted HF, to remove, and then reapply as shown in Figure 55D Grow 5514.

Then deposit the gate, such as the P+ doped amorphous silicon layer 5518, then chemical mechanical polishing, polishing, and then selectively etch back to obtain the shape 5518 shown in FIG. 55E, and then perform gate masking. The line drawing of the resist 5520 is shown in FIG. 55E.

The gate layer 5518 is etched through such that the gate layer is completely clear from between the towers, and then the photoresist is removed as shown in FIG. 55F.

As shown in Figure 55G, the gaps between the towers are filled, the towers are covered with oxide layer 5530 deposited by low temperature gap fill, followed by CMP processing, and another oxide deposition, as shown in Figure 55G.

In FIG. 55H, contacts 5534 to the N+ layer 5504 of the transistor tower are masked and etched, followed by masking and etching of contacts 5518 to the gate polysilicon 5518. Metal line 5540 is masked and etched, filled with isolation metal and copper interconnection, and CMP polished using normal dual damascene interconnection scheme to complete contacts to transistor channel tower N+ 5504 and gate 5518 Via connection, as shown in Figure 55I.

This process can form a vertical junction-free transistor on the surface of monocrystalline silicon, which can be connected to the underlying multi-metal layer semiconductor components without exposing the underlying components and interconnection circuit metals to high temperatures. These junctionless transistors can be used as programmable transistors on the acceptor wafer or housing wafer 808, or transfer transistors for logic devices, or for FPGs, or for other 3D semiconductor devices.

Recessed Array Transistor (RCAT) can be used as another family of transistors to enable the construction of low temperature monolithic 3D ICs using layer cut and etch definitions. Two types of RCAT component structures are shown in Figure 66. It was explained by J.Kim et al. in the 2003-2005 VLSI Technology Forum. Note that the background technologies described by Kim et al. belong to single-layer transistors and do not use any layer cutting technology. They also use high-temperature processes in their work, such as source-drain open annealing, at temperatures above 400 degrees Celsius. The difference is that in the case of the present invention a family of transistors in a two-dimensional plane is used. All transistors (junctionless, grooved or depleted, etc.) have sources and drains on the same two-dimensional plane, and can be considered as planar transistors.

As shown in Figure 67A-F, the layer stacking method is used to build 3D ICs and standard RCAT. For an N-groove MOSFET, a P-silicon wafer 6700 can be used as the starting point for processing. The N+Si buried layer 6702 can be doped, as shown in Figure 67A, resulting in a P- layer 6703 on the surface of the donor wafer. Another method is to perform shallow N+Si doping, and then deposit a P-Si layer 6703 on the outer edge. To turn on the dopant material of the N+ layer 6702, the wafer can be annealed using standard annealing procedures such as gas annealing, tip annealing or laser annealing.

An oxide layer 6701 may then be grown or deposited as shown in FIG. 67B. Nitrogen can be doped into the wafer 6704, and then the smart dicing process is performed, as shown in FIG. 67B.

Layer dicing can then be performed to bond the wafer shown in Figure 67B onto a pre-processing circuit acceptor wafer 808, as shown in Figure 67C. The helium doped layer 6704 may be used to dice the remainder of the wafer 6700.

After dicing, chemical mechanical polishing (CMP) may be performed. An oxide layer isolation region 6705 can be processed and etched to form a groove 6706 as shown in FIG. 67D. This etching process can be further tuned so that sharp corners are smoothed and high spots are avoided.

A gate insulating layer 6707 may then be deposited, either through the aforementioned atomic layer deposition or through a low temperature oxide forming process. Metal gates 6708 can then be deposited to fill the grooves, followed by CMP and gate drawing, as shown in Figure 67E.

A low temperature oxide layer 6709 may then be deposited and planarized using CMP. Contacts 6710 are then machined to connect all electrodes of the transistor, as shown in Figure 67F. This process can form a complete low-temperature RCAT on the surface of the pre-processing circuit 808 . The P-groove MOSFETs can then be fabricated using the analog process. P and N slot RCATs can be used to form a library of monolithic 3D CMOS circuit components.

As shown in Figure 68A-F, the layer stacking method is used to build 3D ICs and standard RCAT. For an N-groove MOSFET, a P-silicon wafer 6800 can be used as the starting point for processing. The N+Si buried layer 6802 can be doped, as shown in Figure 68A, resulting in a P- layer 6803 on the surface of the donor wafer. Another method is to perform shallow N+Si doping, and then deposit a P-Si layer 6803 on the outer edge. With the doped material of the N+ layer 6802 turned on, the wafer can be annealed using standard annealing procedures such as gas annealing, tip annealing or laser annealing.

An oxide layer 6801 may then be grown or deposited as shown in FIG. 68B. Hydrogen can be doped into the wafer 6804, and then the smart dicing process is performed, as shown in FIG. 68B.

Layer dicing can then be performed to bond the wafer shown in Figure 68B onto a pre-processing circuit acceptor wafer 808, as shown in Figure 68C. The helium doped layer 6804 may be used to dice the remainder of the wafer 6800. After dicing, chemical mechanical polishing (CMP) may be performed.

Oxide isolation regions 6805 may be processed as shown in Figure 68D. The final gate recess can be obtained through masking and partial etching, and then spacer deposition 6806 can be performed using an equivalent low temperature deposition, such as silicon oxide or silicon nitride or a combination of the above.

An anisotropic etch can be used for the spacers such that spacer material remains only on the vertical sides of the recessed gate opening. Uniform silicon etching can then be performed to form spherical grooves 6807, as shown in FIG. 68E. The spacers between the sides can be removed using a selective etch.

A gate insulating layer 6808 may then be deposited, either through the aforementioned atomic layer deposition or through a low temperature oxide formation process. Metal gates 6809 can then be deposited to fill the grooves, followed by CMP and gate drawing, as shown in Figure 68F. The gate material can also be doped, using amorphous silicon or a low temperature conductor with a suitable work function. A low temperature oxide layer 6810 may then be deposited and planarized using CMP. Contacts 6811 are then machined to connect all electrodes of the transistor, as shown in Figure 68F.

This process can form a complete low-temperature S-RCAT on the surface of the preprocessing circuit 808 . The P-groove MOSFETs can then be fabricated using the analog process. P and N slot S-RCAT can be used to form a library of monolithic 3D CMOS circuit components. In addition, SRAM circuits built using RCAT may have different trench depths than logic circuits. RCAT and S-RCAT components can be used to build BiCMOS inverters and other hybrid circuits, only need to have conventional bipolar junction transistors in the 808 layers of the casing, and layer cutting can be used to build the whole RCAT component.

The 3D component structure can be built in a single crystal silicon layer, and by taking advantage of the pre-processed donor wafer, through the construction of different material layers of the wafer size, without being limited by temperature, and then layer-cut the pre-processed donor wafer to the acceptor wafer Round, after which different processing steps can be selected for processing, and then the above process can be repeated many times, and processed with low temperature (below 400 degrees Celsius) or high temperature (higher than 400 degrees Celsius), after the final layer cutting, in one or more Memory device structures, such as transistors, are built on the cut-out layers that are aligned with each other, and each layer can be connected to the acceptor wafer.

A new type of monolithic 3D dynamic access memory (DRAM) can be constructed using the method described above. Some examples of this invention are the floating body DRAM type.

Floating body DRAM is a new generation of DRAM, and many companies are currently developing DRAM, such as Innovative Silicon, Synix, and Toshiba. Floating-body DRAM stores data as charge in an SOI MOSFET, or charge in a multi-gate MOSFET. Details and types of operation of floating body DRAMs can be found in the following US Patents and others: 7541616, 7514748, 7499358, 7499352, 7492632, 7486563, 7477540, 7476939. A monolithic 3D integrated DRAM can be built using floating body transistors. Existing technologies for building monolithic 3D DRAMs use planar transistors, and the crystalline silicon layer is formed using selective epi or laser recrystallization. Selective epi technology and laser recrystallization technology cannot produce perfect single crystal silicon, and usually have high thermal energy expenditure. A description of this process can be found in the book "Integrated Interconnect Technologies for 3D Nanoelectronic System" by Bakir and Meindl.

As shown in FIG. 97, the basic elements of the floating body DRAM in operation will be described below. In order to store a "1" byte, it may be necessary to have redundant holes 9702 in the floating body region 9720, and to change the threshold voltage of the storage chip transistor, which includes a source 9704, a gate 9706, a floating body 9720, a buried Oxide layer (BOX) 9718. As shown in Figure 97a. In order to store 0 bytes, it may be necessary to have redundant holes 9710 in the floating body region 9720, and to change the threshold voltage of the memory chip transistor, which includes a source 9712, a gate 9714, a floating body 9720, and a buried oxide layer (BOX) 9716. As shown in Figure 97b. The difference in the threshold voltage of the storage chip transistor in Figure 97a and 97b causes the transistor to be in different working states in the drain current 9734, and the gate voltage 9736 of the transistor is a specified value at this time. As shown in Figure 97c. The current difference 9730 can be discriminated and processed by the sense amplifier circuit as the states of "0" and "1", respectively, and stored in the chip.

As shown in Figures 98A-H, horizontally arranged monolithic 3D DRAMs using two masking steps per memory layer can be constructed using a suitable 3D IC fabrication flow.

As shown in FIG. 98A, a p-substrate donor wafer 9800 can be processed to include a wafer-sized p-doped silicon layer 9804. The P-layer 9804 can have the same or different doping concentration as the P-substrate 9800 . P-doped layer 9804 can be fabricated by ion implantation or annealing. The barrier oxide layer 9801 can be grown before doping to protect the silicon from doping and provide an oxide layer for subsequent oxide wafer bonding.

As shown in FIG. 98B , the surface of the donor wafer 9800 can be re-oxidized by depositing an oxide layer 9802 or annealing a P- layer 9804 for oxide wafer bonding, or using a doped barrier oxide layer 9801 . Layer-slicing dividing planes 9899 (shown in dashed lines), possibly on the donor wafer 9800 or P-layer 9804 (shown), are achieved by doping helium 9807 or other methods as previously described. Both the donor wafer 9800 and the acceptor wafer 9810 can be processed for wafer bonding. As mentioned above, it is best to use low temperature (less than 400 degrees Celsius) to reduce stress during bonding. A portion of the P-donor wafer substrate 9804, as well as a portion of the P-donor wafer substrate 9800, located above the layer-cut dividing plane 9899, can be removed by dicing and grinding, or other aforementioned methods, such as ion dicing.

The remaining P-doped layer 9804', and oxide layer 9802 are layer diced to the acceptor wafer 9810 as shown in FIG. 98C. The acceptor wafer 9810 may contain peripheral circuits that can withstand additional rapid thermal annealing (RTA) temperatures and maintain operational capability and better performance. Therefore, it is better to construct peripheral circuits without RTA turn-on dopant, or use weak RTA. Moreover, the peripheral circuit can use a high-temperature-resistant metal, such as tungsten, so that it can withstand a high temperature greater than 400 degrees Celsius. The surface of the P-doped layer 9804' can be smoothed by chemical and mechanical polishing. Now, the transistors can be constructed and aligned with the alignment marks (not shown) of the acceptor wafer 9810 .

As shown in Figure 98D, shallow trench isolation (STI) oxide regions (not shown) can be etched using scribe and plasma/RIE, down to at least the surface layer of oxide layer 9802, to remove regions of p-single crystal silicon layer 9804'. Gapfill oxide can be deposited and planarized by CMP to form STI oxide regions and use P-doped monocrystalline silicon regions (not shown) to build transistors. At this point, you can choose whether to perform threshold adjustment doping. The gate stack 9824 can be constructed using a gate insulator, such as annealed oxide, and a gate metal material, such as polysilicon. In addition, the gate oxide can be an atomic layer doped (ALD) gate insulating layer, whose work function corresponds to a specified gate metal, which is a high-K metal gate treatment scheme according to industry standards. Alternatively, the gate oxide can be formed using Rapid Anneal Oxidation (RTO), low-temperature oxide deposition, or low-temperature microwave plasma oxidation of the silicon surface, and then tap the gate material, such as tungsten or aluminum. The gate stack is aligned with the LDD (lightly doped drain), and then the annular heavy penetration doping can be performed to adjust the junction and transistor breakdown characteristics. Oxide and/or nitride gap deposition can also be used, followed by etch back to create a doped offset gap (not shown) on the gate stack 9824 . Self-aligning N+ source and drain can be doped to build transistor source and drain 9820 and the remaining P- silicon NMOS transistor channel 9828. At this time, you can choose whether to perform a high-temperature annealing step to turn on the dopant and set the initial junction depth. Finally, the entire gap-fill oxide 9850 can be covered with low temperature oxide 9850 and flattened by CMP. The oxide surface can be processed as a silicon bond oxide, as described previously.

As shown in Figure 98E, the formation of the transistor layer, bonding to the oxide layer 9850 of the acceptor wafer 9810, and the subsequent formation of the transistors of Figures 98A-D can be repeated to build the second layer 9830 of storage transistors. After the construction of all the storage layers is completed, rapid annealing (RTA) can be used to open the doping materials of all the storage layers and the peripheral circuits in the acceptor substrate 9810 . In addition, optical annealing, such as laser annealing, can also be used.

As shown in Figure 98F, contacts and metal interconnection circuits can be processed by printing and plasma/RIE etching. A bit line (BL) contact 9840 is connected to the storage layer transistor N+ region, which is located in the transistor drain layer 9854, and a source line contact 9842 is connected to the storage layer transistor N+ region, which is located in the transistor drain layer 9854. Source side 9852. Bit line (BL) connection 9848 and source line (SL) connection 9846 are connected to bit line contact 9840 and source line contact 9842, respectively. Gate stacks, such as 9834, can be connected to contacts and metal layers (not shown) to form word lines (WL). Through-layer vias 9860 (not shown) can communicate with the metal layers of BL, SL, and WL, and connect with peripheral circuits of the acceptor substrate 9810 through acceptor wafer metal connection pads 1980 (not shown).

As shown in FIG. 98G , which is a cross-sectional top view of the surface of the memory array, the WL line 9864 and the SL line 9865 can be arranged perpendicular to the BL line 9866 .

As shown in FIG. 98H , in the scheme of a single-layer DRAM array, WL, BL and SL are connected at each array layer. The multi-layer structure of the array shares BL and SL contacts, but each layer has its own WL connection group, and can realize the independent visit of each byte.

This process can form a horizontally arranged monolithic 3D DRAM array. By performing two mask processing on each memory array, the 3D DRAM array can be combined with the wafer-sized doped single crystal silicon layer. The underlying multi-metal layer semiconductor components are connected, and the underlying components may or may not contain peripheral circuits, which are used to control the read and write functions of the DRAM.

The illustrations in Figures 98A-98H (not enlarged) will be readily understood by persons with only basic knowledge. Those skilled in the art can easily think further, and many deformations can be derived on this basis. For example, the transistor can be of other types such as RCAT or junctionless. Alternatively, the contacts can also use doped polysilicon, or other conductive materials. Alternatively, stacked memory layers may be connected to peripheral circuits above. After reading this description, those skilled in the art will realize that the scope of the present invention encompasses many modifications and variations. Therefore, this invention is not limited to the patent statement in the appendix.

As shown in Figures 99A-99M, horizontally arranged monolithic 3D DRAMs using two masking steps per memory layer can be constructed using a suitable 3D IC fabrication flow.

As shown in FIG. 99A , the silicon substrate with the peripheral circuit 9902 can use high temperature resistant (higher than 400 degrees Celsius) wiring, such as tungsten. The peripheral circuit substrate 9902 may contain memory control circuits, as well as other functions and types of circuits, such as analog, digital, microwave (RF), or memory functions. The peripheral circuit substrate 9902 may include peripheral circuits that can withstand the additional rapid annealing (RTA) temperature and maintain workability and better performance. Therefore, it is better to construct peripheral circuits without RTA turn-on dopant, or use weak RTA to turn on. An oxide layer 9904 can be deposited on the surface of the donor wafer 9902, so that oxide wafers can be bonded to form an acceptor wafer 2414.

As shown in FIG. 99B, a P-substrate donor wafer 9912 can be processed to include a wafer-sized p-doped silicon layer 9906 (not shown) that can be doped at a concentration comparable to that of the P-substrate 9906. different. P-doped layers can be fabricated by ion implantation or annealing. The barrier oxide layer 9908 can be grown or deposited before doping to protect the silicon crystal from doping and provide oxidation for subsequent wafer bonding of the oxide layer. Layer-cut dividing planes 9910 (shown by dotted lines) can be implemented on the donor wafer 9912 of the P-substrate 9906 or on the P-doped layer by doping or other aforementioned methods. Both the donor wafer 9912 and the acceptor wafer 9914 can be processed for wafer bonding. As mentioned above, the oxide layer 9904 and the oxide layer 9908 are bonded on the surface. It is best to use low temperature (less than 400 degrees Celsius) to reduce the Light stress, or use moderate temperatures (less than 900°C).

As shown in FIG. 99C, a part of the P-donor wafer substrate 9906, and the P-wafer substrate 9906 above the dicing plane 9910 can be removed by dicing and grinding, or other aforementioned methods, such as ion cutting, etc. , thereby constructing the monocrystalline silicon P-layer 9906. The remaining p-layer 9906' and oxide layer 9908 can be layer diced to the acceptor wafer 9914. The surface of the P-layer 9906' can be smoothed by chemical and mechanical polishing. Transistors or portions of transistors may then be constructed and aligned with alignment marks (not shown) of the acceptor wafer 9914 .

As shown in FIG. 99D, the N+ silicon region 9916 can be defined by printed lines, and the N-type, such as arsenic, can be ion-implanted into the P- silicon layer 9906'. This also enables the construction of the remaining P-silicon region 9918.

As shown in Figure 99E, an oxide layer 9920 may be deposited to prepare the surface necessary for later oxide-to-oxide bonding, thus forming a first Si/SiO2 layer 9922. The Si/SiO2 layer includes a silicon dioxide layer 9920 , N+ silicon regions 9916 and P− silicon regions 9918 .

As shown in FIG. 99F, the Si/SiO2 layers shown in FIGS. 99A to 99E may be additionally formed, such as a second Si/SiO2 layer 9924 and a third Si/SiO2 layer 9926. An oxide layer 9929 may be deposited. After all desired memory layers are built, a rapid thermal anneal (RTA) can be performed to essentially turn on dopants in all memory layers 9922, 9924 and 9926 and peripheral circuitry 9902. Alternatively, optical annealing, such as laser annealing, can be performed.

As shown in FIG. 99G, the oxide layer 9929, the third Si/SiO2 layer 9926, the second Si/SiO2 layer 9924 and the first Si/SiO2 layer 9922 can be subjected to photolithography and plasma/reactive ion etching, Forms part of a memory wafer structure. Etching may form P- silicon regions 9918 (which form the floating body transistor trenches) and N+ silicon regions 9916 (which form source, drain and local source lines).

As shown in Figure 99H, gate dielectric and gate electrode material may be deposited, planarized by chemical-mechanical polishing (CMP), and then photolithography and plasma/reactive ion etching may be performed to form the gate electrode. pole dielectric 9928. The gate dielectric 9928 may be self-aligned with and covered by the gate electrode 9930 (as shown), or may substantially cover the entire silicon/oxide multilayer structure. The size and alignment of the gate electrode 9930 and gate dielectric 9928 gate stack layer should ensure sufficient and complete coverage of the P-silicon region 9918'. The gate stack layer (comprising gate electrode 9930 and gate dielectric 9928) consists of a gate dielectric (eg, high thermal oxide) and a gate electrode material (eg, polysilicon). Alternatively, the gate dielectric can be selected from an atomic layer deposition (ALD) material that matches the work function of the specific gate metal, in line with the industry standard for high-k metal gate process solutions described above. In addition, the gate dielectric can be formed by rapid thermal oxidation (RTO). Rapid high thermal oxidation is a process of low-temperature oxidation deposition or low-temperature microwave plasma oxidation on the surface of silicon, which can eventually be deposited as a gate electrode, such as a tungsten electrode or an aluminum electrode.

As shown in FIG. 99I, the gap-fill oxide layer 9932 can completely cover the entire structure, which can be planarized by chemical-mechanical polishing (CMP). For clarity, the oxide layer 9932 is shown as a transparent layer in the figure. In addition, there are word line regions (WL) 9950, gate electrodes 9930, source line regions (SL) 9952 and N+ silicon regions 9916' as shown.

As shown in FIG. 99J, the bit line (BL) contact 9934 can be photolithographically and plasma/reactive ion etched and processed by photoresist stripping. Subsequently, a metal such as copper, aluminum or tungsten may be deposited to fill the contacts and then etched or polished to the top of the oxide layer 9932. Each BL contact 9934 can be fully shared with all memory layers, such as the three memory layers shown in Figure 99J. Through-layer vias 9960 (not shown) may be formed to electrically couple the metallized areas of BL, SL, and WL to peripheral circuitry of the acceptor substrate 9914 through acceptor wafer metal connection pads 9980 (not shown).

As shown in FIG. 99K , BL metal lines 9936 may be formed and connected together with associated BL contacts 9934 . Contacts for WL and SL and associated metal wiring (not shown) may be formed at the edge of the memory array. "Three-dimensional Wafer Lamination Technology with Punching and Filling Process for Ultra-High-Density Flash Memory" ("2007 IEEE Symposium on Very Large-Scale Integration Technology"; Volume: None; Pages: 14-15, 12-14; June 2007; Authors: Tanaka, H., Kido, M., Yahashi, K., and Oomura, M. et al.) to make SL contacts into a stepped structure.

As shown in Figures 99L, 99L1 and 99L2, the second cross-sectional view of Figure 99L is shown in Figure 99L1, and the third cross-sectional view of Figure 99L is shown in Figure 99L2. BL metal line 9936, oxide layer 9932, BL contact 9934, WL region 9950, gate dielectric 9928, P-silicon region 9918' and peripheral circuit substrate 9902 are shown in FIG. 99L1. The BL contact 9934 connects one of the three horizontal planes of the floating body transistor. The floating body transistor includes two N+ silicon regions 9916' for each horizontal plane and corresponding P- silicon regions 9918'. BL metal line 9936, oxide layer 9932, gate electrode 9930, gate dielectric 9928, P-silicon region 9918', interlayer oxide region (OX) and peripheral circuit substrate 9902 are shown in FIG. 99L2. Gate electrodes 9930 are common to the six P-silicon regions 9918', which form six double-sided gated floating body transistors.

As shown in FIG. 99M, a typical floating body transistor with double gates on the first Si/SiO2 layer 9922 may include a P-silicon region 9918' (acting as a floating body transistor trench), an N+ silicon region 9916 ' (acting as source and drain) and two gate electrodes 9930 (with corresponding gate dielectric 9928). The transistors are insulated from below by the oxide layer 9908 .

This process can form a monolithic 3D DRAM in the horizontal direction. The DRAM uses a masking process in memory formed by transferring wafer-sized single-crystal doped silicon layers one by one. At the same time, the 3D DRAM is connected to the underlying multi-metal layer semiconductor device.

Those of ordinary skill may consider the examples mentioned in FIGS. 99A-99M to be representative examples only and not scaled down. A skilled person can take into account more changes. For example, other types of transistors, such as RCAT, etc., can be used, or fewer contacts can be used. Alternatively, doped polysilicon or other conductive materials can be used for the contacts. Alternatively, the stacked memory layer can be connected to peripheral circuits above the memory stack layer. Alternatively, the Si/SiO2 layers 9922, 9924 and 9926 can be annealed layer by layer as long as the relevant implantation procedures are completed by using a laser annealing system. A reading of this specification will allow the skilled person to recall how to make modifications elsewhere within the scope of the invention. Accordingly, the invention is limited only by the appended claims.

As shown in FIGS. 100A to 100L, a horizontally oriented 3D DRAM can be constructed. After all layers have been completely transferred, this method of memory passes through a common masking process for each memory layer without using an additional masking process. 3D DRAM is suitable for producing 3D ICs.

As shown in FIG. 100A , the silicon substrate with the peripheral circuit 10002 can use high temperature (over 400° C.) wiring, such as tungsten wire. The peripheral circuit substrate 10002 may include memory control circuits and various circuits for other purposes, such as analog, digital, radio frequency or storage. The peripheral circuit substrate 10002 may include peripheral circuits. This peripheral circuit can continue to operate even after additional rapid thermal annealing (RTA), maintaining good performance. For this reason, when constructing peripheral circuits, it should be considered to select those peripheral circuits that can turn on the dopant only with a slight RTA or without RTA. The uppermost layer of the peripheral circuit substrate 10002 can be used to bond the oxide wafer and the deposited layer of silicon dioxide 10004 to form the acceptor wafer 10014 .

As shown in FIG. 100B , single crystal silicon donor wafer 10012 may include a wafer-sized P-doped layer (not shown), which may have a different dopant concentration than P-substrate 1006 . The P-doped layer can be formed by ion implantation and high temperature annealing. A mask oxide layer 10008 may be grown or deposited prior to implantation to ensure that silicon is free from contamination during implantation and to provide an oxide layer for later wafer-to-wafer bonding. A layer transfer boundary plane 10010 (dotted line in the figure) can be formed in the donor wafer 10012 in the P-substrate 10006 or in the P-doped layer (not shown) by hydrogen ion implantation or other methods described above. As previously mentioned, both the donor wafer 10012 and the acceptor wafer 10014 are used for wafer bonding, and are bonded together on the surfaces of the oxide layer 10004 and the oxide layer 10008 . Because the stress is lowest at low temperature, the bonding operation is best carried out at low temperature (below 400°C) or medium temperature (not exceeding 900°C).

As shown in FIG. 100C, the portion of the P-layer (not shown) above the layer-transfer interface plane 10010 and the P-wafer substrate 10006 can be removed by dicing or grinding or the processes described above (such as ion cutting or other methods). removal, thereby forming the remaining single crystal silicon P-layer 10006'. The remaining P-layer 10006' and oxide layer 10008 are layer diced onto the acceptor wafer 10014. The topmost layer of the P-layer 10006' can be polished smooth and flat by chemical or mechanical means. The transistors are now fully or partially formed and aligned with the alignment marks (not shown) of the acceptor wafer 10014 . An oxide layer 10020 may be deposited to provide a surface for later bonding between oxides. At this point, the first Si/SiO2 layer 10023 has been formed, including the silicon dioxide layer 10020, the P-silicon layer 10006' and the oxide layer 10008.

As shown in Fig. 100D, Si/SiO2 layers shown in Figs. 100A to 100C may be additionally formed, such as a second Si/SiO2 layer 10025 and a third Si/SiO2 layer 10027. An oxide layer 10029 may be deposited to provide isolation from the top silicon layer.

As shown in Figure 100E, the oxide layer 10029, the third Si/SiO2 layer 10027, the second Si/SiO2 layer 10025 and the first Si/SiO2 layer 10023 can be photolithographically and plasma/reactive ion etched, Forms part of a memory wafer structure. The memory chip structure now includes P-silicon region 10016 and oxide layer region 10022 .

As shown in Figure 100F, gate dielectric and gate electrode material may be deposited, planarized by chemical-mechanical polishing (CMP), and then photolithography and plasma/reactive ion etching may be performed to form the gate electrode. pole dielectric 10028. The gate dielectric 10028 may be self-aligned with and covered by the gate electrode 10030 (as shown), or may substantially cover the entire silicon/oxide multilayer structure. The gate stack layer (comprising gate electrode 10030 and gate dielectric 10028) consists of a gate dielectric (eg, high thermal oxide) and a gate electrode material (eg, polysilicon). Alternatively, the gate dielectric can be selected from an atomic layer deposition (ALD) material that matches the work function of the specific gate metal, in line with the industry standard for high-k metal gate process solutions described above. In addition, the gate dielectric can be formed by rapid thermal oxidation (RTO). Rapid high thermal oxidation is a process of low-temperature oxidation deposition or low-temperature microwave plasma oxidation on the surface of silicon, which can eventually be deposited as a gate electrode, such as a tungsten electrode or an aluminum electrode.

As shown in FIG. 100G , the N+ silicon region 10026 and the gate electrode 10030 can be self-aligned by implanting N-type ions (such as arsenic) into the P- silicon region 10016 . The P-silicon region 10016 is not blocked by the gate electrode 10030 . This forms the rest of the P-silicon region 10017 (not shown) in the region blocked by the gate electrode 10030. When implanting N-type ions into each layer of P-silicon region 10016, different implantation energies or angles or implantation multiples can be used. Gate sidewalls (not shown) may be used in a multi-step implantation process, and different gate sidewall widths may be used for silicon layers present in different stacks to account for the different lateral diffusion of N-type ion implantation. The bottom layer (eg, 10023) may have wider gate sidewalls than the top layer (eg, 10027) requires. Likewise, angular ion implantation with substrate rotation can be used to compensate for different implant spreads. The top layer implant may have a certain tilt angle, which is not perpendicular to the wafer surface, and it places the ions slightly below the edge of the gate electrode 10030, which is closely coordinated with the ion implantation of the lower layer with better perpendicularity. Ion implantation of the lower layers can place ions slightly below the gate electrode 10030 due to the higher implant energy required to reach the bottom layer, resulting in a diffusion effect. A rapid thermal anneal (RTA) may be performed to essentially turn on dopants in all memory layers 10023, 10025 and 10027 and peripheral circuitry 10002. Alternatively, optical annealing, such as laser annealing, can be performed.

As shown in Figure 100H, a gap-fill oxide layer 10032 may cover the entire structure, which may be planarized by chemical-mechanical polishing (CMP). For clarity, the oxide layer 10032 is shown as a transparent layer in the figure. In addition, there are word line region (WL) 10050, gate electrode 10030, source line region (SL) 10052 and N+ silicon region 10026 as shown.

As shown in Figure 100I, bit line (BL) contacts 10034 can be photolithographically and plasma/reactive ion etched and processed by photoresist stripping. Subsequently, a metal such as copper, aluminum or tungsten may be deposited to fill the contacts and then etched or polished to the top of the oxide layer 10032. Each BL contact 10034 can be fully shared with all storage layers, such as the three storage layers shown in Figure 100I. Through-layer vias 10060 (not shown) may be formed to electrically couple the metallized areas of BL, SL and WL to peripheral circuitry of the acceptor substrate 10080 through acceptor wafer metal connection pads 10014 (not shown).

As shown in Figure 100J, BL metal lines 10036 may be formed and connected together with associated BL contacts 10034. Contacts for WL and SL and associated metal wiring (not shown) may be formed at the edge of the memory array.

The second cross-sectional view of FIG. 100K is shown in FIG. 100K1, and the third cross-sectional view of FIG. 100K is shown in FIG. 100K2. BL metal line 10036, oxide layer 10032, BL contact 10034, WL region 10050, gate dielectric 10028, N+ silicon region 10026, P- silicon region 10017 and peripheral circuit substrate 10002 are shown in FIG. 100K1. The BL contact 10034 connects one of the three horizontal planes of the floating body transistor. The floating body transistor comprises two N+ silicon regions 10026 and corresponding P- silicon regions 10017 per horizontal plane. BL metal line 10036, oxide layer 10032, gate electrode 10030, gate dielectric 10028, P-silicon region 10017, interlayer oxide region (OX) and peripheral circuit substrate 10002 are shown in FIG. 100K2. Gate electrodes 10030 are common in the six P-silicon regions 10017, which form six double-sided gated floating body transistors.

As shown in FIG. 100M, a typical floating body transistor with double gates on the first Si/SiO2 layer 10023 may include a P-silicon region 10017 (acting as a floating body transistor trench), an N+ silicon region 10026 ( function as source and drain) and two gate electrodes 10030 (with corresponding gate dielectrics 10028). The transistor is insulated from below by the oxide layer 10008.

This process can form a monolithic 3D DRAM in the horizontal direction. The 3D DRAM does not use a masking process in a memory formed by transferring wafer-sized single-crystal doped silicon layers one by one. At the same time, the DRAM is connected to the underlying MLS device.

One of ordinary skill would consider the examples mentioned in FIGS. 100A-100L to be representative examples only and not to scale. A skilled person can take into account more changes. For example, other types of transistors can be used, such as RCAT, etc., or fewer contacts can be used. Alternatively, doped polysilicon or other conductive materials can be used for the contacts. Alternatively, the stacked memory layer can be connected to peripheral circuits above the memory stack layer. In addition, each gate of dual-gate 3D DRAM can be independently controlled to better control the memory chip. A reading of this specification will allow the skilled person to recall how to make modifications elsewhere within the scope of the invention. Accordingly, the invention is limited only by the appended claims.

New monolithic 3D memory technologies that take advantage of the material's resistance-changing characteristics could be used in a similar fashion. There are many types of resistive memory, including phase change memory, metal oxide memory, resistive random access memory (RRAM), memristor, solid dielectric memory, ferroelectric random access memory and magnetic random access memory, etc. . For background information on these resistive memory types, see "Storage Class Memory Candidate Technology Overview" (IBM Corporate Research and Development Journal; Vol. 52; No. 4.5; Pages: 449-464; July 2008; Author: G.W. et al). The relevant content of this document is included in this manual for reference.

As shown in Figures 101A to 101K, 3D memory can be built using a resistive no additional masking process at each memory layer. 3D memory is suitable for producing 3D IC. The 3D memory uses junctionless transistors with resistive memory components connected in series with select transistors or access transistors.

As shown in FIG. 101A , the silicon substrate with the peripheral circuit 10102 can use high temperature (over 400° C.) wiring, such as tungsten wire. The peripheral circuit substrate 10102 may include memory control circuits and various circuits for other purposes, such as analog, digital, radio frequency or storage. The peripheral circuit substrate 10102 may include peripheral circuits. This peripheral circuit can continue to operate even after additional rapid thermal annealing (RTA), maintaining good performance. For this reason, when constructing peripheral circuits, it should be considered to select those peripheral circuits that can turn on the dopant only with a slight RTA or without RTA. The uppermost layer of the peripheral circuit substrate 10102 can be used to bond the oxide wafer and the deposited layer of silicon dioxide 10104 to form the acceptor wafer 10114 .

As shown in FIG. 101B , single crystal silicon donor wafer 10112 may optionally include a wafer-sized N+ doped layer (not shown), which may have a different dopant concentration than N+ substrate 10106 . The N+ doped layer can be formed by ion implantation and high thermal annealing. A mask oxide layer 10108 may be grown or deposited prior to implantation to ensure that the silicon is free from contamination during implantation and to provide an oxide layer for later wafer-to-wafer bonding. A layer transfer boundary plane 10110 (dotted line in the figure) can be formed in the N+ substrate 10106 or the donor wafer 10112 in the N+ doped layer (not shown) by hydrogen ion implantation or other methods described above. Both the donor wafer 10112 and the acceptor wafer 10114 are used for wafer bonding and are bonded together on the surfaces of the oxide layer 10104 and the oxide layer 10108 as previously described. Because the stress is lowest at low temperature, the bonding operation is best carried out at low temperature (below 400°C) or medium temperature (not exceeding 900°C).

As shown in FIG. 101C, the N+ layer portion (not shown) above the layer transfer interface plane 10110 and the N+ wafer substrate 10106 can be removed by dicing or grinding or the processes described above (such as ion cutting or other methods), Thus, the remaining monocrystalline silicon N+ layer 10106 is formed. The remaining N+ layer 10106' and oxide layer 10108 are layer diced onto the acceptor wafer 10114. The uppermost layer of the N+ layer 10106' can be polished smooth and flat by chemical or mechanical means. The transistors are now fully or partially formed and aligned with the alignment marks (not shown) of the acceptor wafer 10114. An oxide layer 10120 may be deposited to provide a surface for later bonding between oxides. At this point, the first Si/SiO2 layer 10023 has been formed, including the silicon dioxide layer 10120, the N+ silicon layer 10106' and the oxide layer 10108.

As shown in FIG. 101D, Si/SiO2 layers shown in FIGS. 101A to 101C may be additionally formed, such as a second Si/SiO2 layer 10125 and a third Si/SiO2 layer 10127. An oxide layer 10129 may be deposited to provide isolation from the top N+ silicon layer.

As shown in Figure 101E, the oxide layer 10129, the third Si/SiO2 layer 10127, the second Si/SiO2 layer 10125 and the first Si/SiO2 layer 10123 can be photolithographically and plasma/reactive ion etched, Forms part of a memory wafer structure. The memory wafer structure now includes N+ silicon region 10126 and oxide layer region 10122 .

As shown in Figure 101F, the gate dielectric and gate electrode material may be deposited, planarized by chemical-mechanical polishing (CMP), and then photolithography and plasma/reactive ion etching may be performed to form the gate electrode. pole dielectric 10128. The gate dielectric 10128 may be self-aligned with and covered by the gate electrode 10130 (as shown), or may substantially cover the entire N+ silicon region 10126 and oxide region 10122 multilayer structure. The gate stack layer (comprising gate electrode 10130 and gate dielectric 10128) consists of a gate dielectric (eg, high thermal oxide) and a gate electrode material (eg, polysilicon). Alternatively, the gate dielectric can be selected from an atomic layer deposition (ALD) material that matches the work function of the specific gate metal, in line with the industry standard for high-k metal gate process solutions described above. In addition, the gate dielectric can be formed by rapid thermal oxidation (RTO). Rapid thermal oxidation is a process of low-temperature oxidation deposition or low-temperature microwave plasma oxidation on the surface of silicon, which can eventually be deposited as a gate electrode, such as a tungsten electrode or an aluminum electrode.

As shown in FIG. 101G, a gap-fill oxide layer 10132 may cover the entire structure, which may be planarized by chemical-mechanical polishing (CMP). For clarity, the oxide layer 10132 is shown as a transparent layer in the figure. In addition, there are word line region (WL) 10150, gate electrode 10130, source line region (SL) 10152 and N+ silicon region 10126 as shown.

As shown in Figure 101H, the bit line (BL) contact 10134 can be photolithographically and plasma/reactive ion etched through the oxide layer 10132, the three N+ silicon regions 10126 and the associated oxide layer vertical isolation regions, so as to communicate with all The storage layer is connected vertically. BL contact 10134 is processed by photoresist stripping. The resistive memory material 10138, such as hafnium dioxide, may then be deposited, preferably by atomic layer deposition (ALD). The electrodes of the RRAM device may then be deposited by ALD to form electrode/BL contacts 10134 . Excess deposited material should be polished so that it is on the same surface as or below the top of the oxide layer 10132. Each BL contact 10034 with resistive material 10138 can be fully shared with all storage layers, such as the three storage layers shown in FIG. 101H.

As shown in FIG. 101I , a BL metal line 10136 can be formed and connected to a related BL contact 10134 with a resistive material 10138 . Contacts for WL and SL and associated metal wiring (not shown) may be formed at the edge of the memory array. Through-layer vias 10160 (not shown) may be formed to electrically couple the metallized areas of BL, SL and WL to peripheral circuitry of the acceptor substrate 10180 through acceptor wafer metal connection pads 10114 (not shown).

The second cross-sectional view of Fig. 101J is shown in Fig. 101J1, and the third cross-sectional view of Fig. 101J is shown in Fig. 101J2. Figure 101J1 shows BL metal line 10136, oxide layer 10132, BL contact/electrode 10134, resistive switch material 10138, WL region 10150, gate dielectric 10128, N+ silicon region 10126 and peripheral circuit substrate 10102. The BL contact/electrode 10134 is connected to one of the three horizontal planes of the resistive material 10138 . The other side of the resistive material 10138 is connected to the N+ region 10126 . BL metal line 10136, oxide layer 10132, gate electrode 10130, gate dielectric 10128, N+ silicon region 10126, interlayer oxide region (OX) and peripheral circuit substrate 10102 are shown in FIG. 101J2. The gate electrodes 10130 are common in the six N+ silicon regions 10126, and they form six double-sided gate-controlled junctionless transistors as memory selection transistors.

As shown in FIG. 101K, a typical double-gate junctionless transistor on the first Si/SiO2 layer 10123 may include an N+ silicon region 10126 (functioning as source, drain and transistor trench) and two A gate electrode 10130 (with a corresponding gate dielectric 10128). The transistors are insulated from below by the oxide layer 10108 .

The process can form resistive multilayer or 3D memory arrays without additional masking steps for each memory layer. The storage layer uses a junctionless transistor, and its resistive memory component is connected in series with the selection transistor. The memory array is constructed by layering and dicing doped monocrystalline silicon layers of wafer size. At the same time, the 3D memory array is connected to the underlying multi-metal layer semiconductor device.

Those of ordinary skill may regard the examples mentioned in FIGS. 101A-101K as typical examples only and not to scale. A skilled person can take into account more changes. For example, other types of transistors, such as RCAT, can be used. In addition, the dopant of the N+ layer may vary slightly when compensating for interconnect resistance. Alternatively, the stacked memory layer can be connected to peripheral circuits above the memory stack layer. In addition, each gate of dual-gate 3D resistive memory can be independently controlled to better control the memory chip. A reading of this specification will allow the skilled person to recall how to make modifications elsewhere within the scope of the invention. Accordingly, the invention is limited only by the appended claims.

As shown in Figures 102A to 102L, 3D memory can be built in each memory layer using a resistive no additional masking process. 3D memory is suitable for producing 3D IC. The 3D memory uses dual-gated metal-oxide-semiconductor field-effect transistors (MOSFETs) with resistive memory elements in series with select transistors.

As shown in FIG. 102A, the silicon substrate with the peripheral circuit 10202 can use high temperature resistant (over 400° C.) wiring, such as tungsten wire. The peripheral circuit substrate 10202 may include memory control circuits and various circuits for other purposes, such as analog, digital, radio frequency or storage. The peripheral circuit substrate 10202 may include peripheral circuits. This peripheral circuit can continue to operate even after additional rapid thermal annealing (RTA), maintaining good performance. For this reason, when constructing peripheral circuits, it should be considered to select those peripheral circuits that can turn on the dopant only with a slight RTA or without RTA. The uppermost layer of the peripheral circuit substrate 10202 can be used to bond the oxide wafer and the deposited layer of silicon dioxide 10204 to form the acceptor wafer 10214 .

As shown in FIG. 102B , a single crystal silicon donor wafer 10212 may include a wafer-sized P-doped layer (not shown), which may have a different dopant concentration than the P-substrate 10206 . The P-doped layer can be formed by ion implantation and high temperature annealing. A mask oxide layer 10208 may be grown or deposited prior to implantation to ensure silicon contamination during implantation and to provide an oxide layer for later wafer-to-wafer bonding. A layer transfer boundary plane 10210 (dotted line in the figure) can be formed in the donor wafer 10212 in the P-substrate 10206 or in the P-doped layer (not shown) by hydrogen ion implantation or other methods described above. As mentioned above, both the donor wafer 10212 and the acceptor wafer 10214 are used for wafer bonding. 10204 and the surfaces of the oxide layer 10208 are bonded together.

As shown in FIG. 102C, the portion of the P-layer (not shown) above the dicing interface plane 10210 and the P-wafer substrate 10206 can be removed by dicing or grinding or the processes described above (such as ion cutting or other methods). , thereby forming the remaining monocrystalline silicon P-layer 10206. The remaining p-layer 10206' and oxide layer 10208 are layer diced onto the acceptor wafer 10214. The topmost layer of the P-layer 10206' can be polished smooth and flat by chemical or mechanical means. The transistors are now fully or partially formed and aligned with the alignment marks (not shown) of the acceptor wafer 10214. An oxide layer 10220 may be deposited to provide a surface for later bonding between oxides. At this point, the first Si/SiO2 layer 10223 has been formed, including the silicon dioxide layer 10220, the P-silicon layer 10206' and the oxide layer 10208.

As shown in FIG. 102D, Si/SiO2 layers shown in FIGS. 102A to 102C may be additionally formed, such as a second Si/SiO2 layer 10225 and a third Si/SiO2 layer 10227. An oxide layer 10229 may be deposited to provide isolation from the top silicon layer.

As shown in FIG. 102E, the oxide layer 10229, the third Si/SiO2 layer 10227, the second Si/SiO2 layer 10225 and the first Si/SiO2 layer 10223 can be subjected to photolithography and plasma/reactive ion etching, Forms part of a memory wafer structure. The memory chip structure now includes P-silicon region 10216 and oxide layer region 10222 .

As shown in Figure 102F, the gate dielectric and gate electrode material may be deposited, planarized by chemical-mechanical polishing (CMP), and then photolithography and plasma/reactive ion etching may be performed to form the gate electrode. pole dielectric 10228. The gate dielectric 10228 may be self-aligned with and covered by the gate electrode 10230 (as shown), or may substantially cover the entire silicon/oxide multilayer structure. The gate stack layer (comprising gate electrode 10230 and gate dielectric 10228) consists of a gate dielectric (eg, high thermal oxide) and a gate electrode material (eg, polysilicon). Alternatively, the gate dielectric can be selected from an atomic layer deposition (ALD) material that matches the work function of the specific gate metal, in line with the industry standard for high-k metal gate process schemes described above. In addition, the gate dielectric can be formed by rapid thermal oxidation (RTO). Rapid thermal oxidation is a process of low-temperature oxidation deposition or low-temperature microwave plasma oxidation on the surface of silicon, which can eventually be deposited as a gate electrode, such as a tungsten electrode or an aluminum electrode.

As shown in FIG. 102G , the N+ silicon region 10226 and the gate electrode 10230 can be self-aligned by implanting N-type ions (such as arsenic) into the P- silicon region 10216 . The P-silicon region 10216 is not blocked by the gate electrode 10230 . This forms the rest of the P-silicon region 10217 (not shown) in the region blocked by the gate electrode 10230. When implanting N-type ions into each layer of P-silicon region 10216, different implantation energies or angles or implantation multiples can be used. Gate sidewalls (not shown) may be used in a multi-step implantation process, and different gate sidewall widths may be used for silicon layers present in different stacks to account for the different lateral diffusion of N-type ion implantation. The bottom layer (eg, 10223) may have wider gate sidewalls than the top layer (eg, 10027) requires. Likewise, angular ion implantation with substrate rotation can be used to compensate for different implant spreads. The top layer implant may have a certain tilt angle, which is not perpendicular to the wafer surface, and it places the ions slightly below the edge of the gate electrode 10230, which is closely coordinated with the ion implantation of the lower layer with better perpendicularity. Ion implantation of the lower layers can place ions just below the gate electrode 10230 due to the higher implant energy required to reach the lower layers, resulting in a diffusion effect. A rapid thermal anneal (RTA) may be performed to essentially turn on dopants in all memory layers 10223, 10225, and 10227 and peripheral circuitry 10202. Alternatively, optical annealing, such as laser annealing, can be performed.

As shown in FIG. 102H, a gap-fill oxide layer 10232 may cover the entire structure, which may be planarized by chemical-mechanical polishing (CMP). For clarity, the oxide layer 10232 is shown as a transparent layer in the figure. In addition, there are word line region (WL) 10250, gate electrode 10230, source line region (SL) 10252 and N+ silicon region 10226 as shown.

As shown in FIG. 102I, the bit line (BL) contact 10234 can be photolithographically and plasma/reactive ion etched through the oxide layer 10232, the three N+ silicon regions 10226 and the associated oxide layer vertical isolation regions in order to fully communicate with the All memory layers are connected vertically, followed by photoresist removal. The resistive memory material 10238, such as hafnium dioxide, may then be deposited, preferably by atomic layer deposition (ALD). The electrodes of the RRAM device may then be deposited by ALD to form the electrode/BL contact 10234 . Excess deposited material should be polished so that it is on the same surface as or below the top of the oxide layer 10232 . Each BL contact 10234 with resistive material 10238 can be fully shared with all storage layers, such as the three storage layers shown in FIG. 102I.

As shown in FIG. 102J , a BL metal line 10236 can be formed and connected to a related BL contact 10234 with a resistive material 10238 . Contacts for WL and SL and associated metal wiring (not shown) may be formed at the edge of the memory array. Through-layer vias 10260 (not shown) may be formed to electrically couple the metallized areas of BL, SL and WL to peripheral circuitry of the acceptor substrate 10280 through acceptor wafer metal connection pads 10214 (not shown).

The second cross-sectional view of Figure 102K is shown in Figure 102K1, and the third cross-sectional view of Figure 102K is shown in Figure 102K2. Figure 102K1 shows BL metal line 10236, oxide layer 10232, BL contact/electrode 10234, resistive switch material 10238, WL region 10250, gate dielectric 10228, P- silicon region 10217, N+ silicon region 10226 and peripheral circuit substrate 10202. The BL contact/electrode 10234 is connected to one of the three horizontal planes of the resistive material 10238 . The other side of the resistive material 10238 is connected to the N+ silicon region 10226 . As shown in Figure 102K2, the P- region 10217 and the corresponding N+ region 10226 on each side form the source, drain and trench of the select transistor. BL metal line 10236, oxide layer 10232, gate electrode 10230, gate dielectric 10228, P-silicon region 10217, interlayer oxide region (OX) and peripheral circuit substrate 10202 are shown in FIG. 102K2. Gate electrodes 10230 are common to the six P-silicon regions 10217, and they control the six dual-gated MOSFET select transistors.

As shown in FIG. 102L, a typical dual-gated MOSFET selection transistor on the first Si/SiO2 layer 10223 may include a P-silicon region 10217 (acting as a transistor trench), an N+ silicon region 10226 (acting as source and drain) and two gate electrodes 10230 (with corresponding gate dielectrics 10228). The transistors are insulated from below by the oxide layer 10208 .

The process forms resistive 3D memory without additional masking steps for each memory layer. 3D memory is constructed by layering wafer-sized doped monocrystalline silicon layers. At the same time, the 3D memory is connected to the underlying multi-metal layer semiconductor device.

One of ordinary skill would consider the examples mentioned in FIGS. 102A-102L to be representative examples only and not to scale. A skilled person can consider more variations. For example, other types of transistors, such as RCAT, can be used. MOSFET option devices can utilize lightly doped drain and halo implants in trench engineering. Alternatively, doped polysilicon or other conductive materials can be used for the contacts. Alternatively, the stacked memory layer can be connected to peripheral circuits above the memory stack layer. In addition, each gate of dual-gate 3D DRAM can be independently controlled to better control the memory chip. A reading of this specification will allow the skilled person to recall how to make modifications elsewhere within the scope of the invention. Accordingly, the invention is limited only by the appended claims.

As shown in FIGS. 103A to 103M , resistivity can be used to build 3D memory with an additional masking process at each memory layer. 3D memory is suitable for producing 3D IC. The 3D memory uses a dual-gate MOSFET selection transistor with a resistive memory element connected in series with the selection transistor.

As shown in FIG. 103A , the silicon substrate with the peripheral circuit 10302 can use high temperature resistant (over 400° C.) wiring, such as tungsten wire. The peripheral circuit substrate 10302 may include memory control circuits and various circuits for other purposes, such as for analog, digital, radio frequency or storage. The peripheral circuit substrate 10302 may contain circuits. This circuit can continue to operate and maintain good performance even after additional rapid thermal annealing (RTA). For this reason, when constructing peripheral circuits, it should be considered to select those peripheral circuits that can turn on the dopant only with a slight RTA or without RTA. The uppermost layer of the peripheral circuit substrate 10302 can be used to bond the oxide wafer and the deposited layer of silicon dioxide 10304 to form the acceptor wafer 2414 .

As shown in FIG. 103B , a single crystal silicon donor wafer 10312 may include a wafer-sized P-doped layer (not shown), which may have a different dopant concentration than the P-substrate 10306 . The P-doped layer can be formed by ion implantation and high temperature annealing. A mask oxide layer 10308 may be grown or deposited prior to implantation to ensure that the silicon is free from contamination during the implantation process and to provide an oxide layer for later wafer-to-wafer bonding. A layer transfer boundary plane 10306 (dotted line in the figure) can be formed in the donor wafer 10312 in the P-substrate 10310 or P-doped layer (not shown) by hydrogen ion implantation or other methods described above. As mentioned above, both the donor wafer 10312 and the acceptor wafer 10314 are used for wafer bonding. 10304 and the surfaces of the oxide layer 10308 are bonded together.

As shown in FIG. 103C, the portion of the P-layer (not shown) above the dicing interface plane 10310 and the P-wafer substrate 10306 can be removed by dicing or grinding or the processes described above (such as ion cutting or other methods). removal, thereby forming the remaining single crystal silicon P-layer 10306. The remaining P-layer 10306' and oxide layer 10308 are layer diced onto the acceptor wafer 10314. The topmost layer of the P-layer 10306' can be polished smooth and flat by chemical or mechanical means. The transistors are now fully or partially formed and aligned with the alignment marks (not shown) of the acceptor wafer 10314.

As shown in FIG. 103D, the N+ silicon region 10316 can be photolithographically implanted and the rest of the P- silicon region 10318 can be formed.

As shown in Figure 103E, an oxide layer 10320 may be deposited to prepare the necessary surface for later oxide-to-oxide bonding, thus forming a first Si/SiO2 layer 10323. The Si/SiO2 layer includes a silicon dioxide layer 10320 , an N+ silicon region 10316 and a P− silicon region 10318 .

As shown in FIG. 103F, Si/SiO2 layers shown in FIGS. 103A to 103E may be additionally formed, such as a second Si/SiO2 layer 10325 and a third Si/SiO2 layer 10327. An oxide layer 10329 may be deposited. After all desired memory layers are built, a rapid thermal anneal (RTA) can be performed to essentially turn on dopants in all memory layers 10323, 10325, and 10327 and peripheral circuitry 10302. Alternatively, optical annealing, such as laser annealing, can be performed.

As shown in Figure 103G, the oxide layer 10329, the third Si/SiO2 layer 10327, the second Si/SiO2 layer 10325 and the first Si/SiO2 layer 10323 can be photolithographically and plasma/reactive ion etched, Forms part of a memory wafer structure. Etching may form P- silicon regions 10318' (which form the transistor trenches) and N+ silicon regions 10316' (which form source, drain and local source lines).

As shown in Figure 103H, the gate dielectric and gate electrode material may be deposited, planarized by chemical-mechanical polishing (CMP), and then photolithography and plasma/reactive ion etching may be performed to form the gate electrode. pole dielectric 10328. The gate dielectric 10328 may be self-aligned with and covered by the gate electrode 10330 (as shown), or may substantially cover the entire silicon/oxide multilayer structure. The size and alignment of the gate electrode 10330 and the gate dielectric 10328 gate stack layer should ensure sufficient and complete coverage of the P-silicon region 10318'. The gate stack layer (comprising gate electrode 10330 and gate dielectric 10328) consists of a gate dielectric (eg, high thermal oxide) and a gate electrode material (eg, polysilicon). Alternatively, the gate dielectric can be selected from an atomic layer deposition (ALD) material that matches the work function of the specific gate metal, in line with the industry standard for high-k metal gate process solutions described above. In addition, the gate dielectric can be formed by rapid thermal oxidation (RTO). Rapid high thermal oxidation is a process of low-temperature oxidation deposition or low-temperature microwave plasma oxidation on the surface of silicon, which can eventually be deposited as a gate electrode, such as a tungsten electrode or an aluminum electrode.

As shown in Figure 103I, a gap-fill oxide layer 10332 may cover the entire structure, which may be planarized by chemical-mechanical polishing (CMP). For clarity, the oxide layer 10332 is shown as a transparent layer in the figure. In addition, there are word line region (WL) 10350, gate electrode 10330, source line region (SL) 10352 and N+ silicon region 10316 as shown.

As shown in FIG. 103J, the bit line (BL) contact 10334 can be photolithographically and plasma/reactive ion etched through the oxide layer 10332, the three N+ silicon regions 10316' and the associated oxide layer vertical isolation regions in order to communicate with All storage layers are connected vertically. BL contact 10334 is processed by photoresist stripping. The resistive memory material 10338, such as hafnium dioxide, may then be deposited, preferably by atomic layer deposition (ALD). The electrodes of the RRAM device may then be deposited by ALD to form electrode/BL contacts 10334 . Excess deposited material should be polished so that it is on the same surface as or below the top of the oxide layer 10332. Each BL contact/electrode 10334 with resistive material 10338 can be fully shared with all storage layers, such as the three storage layers shown in FIG. 103J.

As shown in FIG. 103K, a BL metal line 10336 can be formed and connected to the associated BL contact 10334 with a resistive material 10338. Contacts for WL and SL and associated metal wiring (not shown) may be formed at the edge of the memory array. Through-layer vias 10360 (not shown) may be formed to electrically couple the metallized areas of BL, SL and WL to the acceptor substrate 10314 peripheral circuitry through acceptor wafer metal connection pads 10380 (not shown).

The second cross-sectional view of Figure 103L is shown in Figure 103L1, and the third cross-sectional view of Figure 103L is shown in Figure 103L2. Figure 103L2 shows BL metal line 10336, oxide layer 10332, BL contact/electrode 10334, resistive switch material 10338, WL region 10350, gate dielectric 10328, P- silicon region 10318', N+ silicon region 10316' and surrounding circuit substrate 10302. The BL contact/electrode 10334 is connected to one of the three horizontal planes of the resistive material 10338 . The other side of the resistive material 10338 is connected to the N+ silicon region 10316'. As shown in Figure 103L2, the P- region 10318' and the corresponding N+ region 10316' on each side form the source, drain and trench of the select transistor. BL metal line 10336, oxide layer 10332, gate electrode 10330, gate dielectric 10328, P-silicon region 10318', interlayer oxide region (OX) and peripheral circuit substrate 10302 are shown in Figure 103L2. Gate electrodes 10330 are common to the six P-silicon regions 10318', which control the six dual-gated MOSFET select transistors.

As shown in FIG. 103L, a typical dual-gated MOSFET select transistor on the first Si/SiO2 layer 10323 may include a P-silicon region 10318 (acting as a transistor trench), an N+ silicon region 10316 (acting as source and drain) and two gate electrodes 10330 (with corresponding gate dielectrics 10328). The transistors are insulated from below by the oxide layer 10308 .

The process forms resistive 3D memory, using an additional masking process for each memory layer. Resistive 3D memory is built by layering wafer-sized doped single-crystal silicon layers. At the same time, the 3D memory is connected to the underlying multi-metal layer semiconductor device.

Those of ordinary skill would consider the examples mentioned in Figures 103A-103M to be representative examples only and not to scale. A skilled person can consider more variations. For example, other types of transistors, such as RCAT, can be used. Alternatively, doped polysilicon or other conductive materials can be used for the contacts. Alternatively, the stacked memory layer can be connected to peripheral circuits above the memory stack layer. Alternatively, the Si/SiO2 layers 10322, 10324 and 10326 can be annealed layer by layer as long as the relevant implantation procedures are completed by using a laser annealing system. A reading of this specification will allow the skilled person to recall how to make modifications elsewhere within the scope of the invention. Accordingly, the invention is limited only by the appended claims.

As shown in Figures 104A to 104F, resistive 3D memories can be built with two additional masking steps per memory layer. 3D memory is suitable for producing 3D IC. The 3D memory uses a single-gate MOSFET select transistor with a resistive memory element in series with the select transistor.

As shown in Figure 104A, a P-substrate donor wafer 10400 is processed to include a wafer-sized P-doped layer 10404. The dopant concentration of the P-doped layer 10404 may be the same as that of the P-substrate 10400, or it may be different. The P-doped layer 10404 can be formed by ion implantation and high thermal annealing. A mask oxide layer 10401 can be grown prior to implantation to ensure that the silicon is free from contamination during implantation and to provide an oxide layer for later wafer-to-wafer bonding.

As shown in Figure 104B, the top layer of the donor wafer 10400 can be used to bond the oxide wafer to the deposited layer of the oxide layer 10402, either through high thermal oxidation of the P- layer 10404, or secondary oxidation of the implanted mask oxide layer 10401 An oxide layer 10402 is formed. A layer transfer boundary plane 10499 (dotted line in the figure) can be formed in the donor wafer 10400 or the P-layer 10404 (as shown) by hydrogen ion implantation 10407 or other methods described above. As previously described, both the donor wafer 10400 and the acceptor wafer 10410 can be used as a bond between the wafers, and then the two are bonded together. The above-mentioned bonding is best carried out at low temperature (not exceeding 400°C) to keep the stress at the lowest level. Portions of the P-layer above the layer-transfer interface plane 10499 and the P-donor wafer substrate 10400 may be removed by dicing or grinding or the processes described above, such as ion dicing or other methods.

The remaining P-doping 10404&apos; and oxide layer 10402 have been layered onto the acceptor wafer 10410 as shown in Figure 104C. The acceptor wafer 10410 may contain circuitry. This circuit can continue to operate and maintain good performance even after additional rapid thermal annealing (RTA). For this reason, when constructing peripheral circuits, it should be considered to select those peripheral circuits that can turn on the dopant only with a slight RTA or without RTA. In addition, the peripheral circuits can use refractory metals, such as tungsten with high temperature resistance over 400°C. The uppermost layer of the P-doped layer 10404' can be polished smooth and flat by chemical or mechanical means. The transistors are now formed and aligned with the alignment marks (not shown) of the acceptor wafer 10410 .

As shown in Figure 104D, the shallow trench insulator (STI) oxide region (not shown) can be subjected to photolithography and plasma/reactive ion etching up to the top layer of the oxide layer 10402 to remove the P-monocrystalline silicon layer region 10404. A gap-fill oxide may be deposited and planarized by chemical-mechanical polishing (CMP) to form conventional STI oxide regions and P-doped monocrystalline silicon regions (not shown) to form transistors. Simultaneous injection with or without threshold adjustment can also be performed. The gate stack consists of a gate dielectric (such as a high thermal oxide layer) and a gate electrode material (such as polysilicon). Alternatively, the gate oxide layer can be an atomic layer deposition (ALD) gate dielectric that matches the work function of the specific gate metal, which is in line with the industry standard for high-k metal gate process solutions described above. In addition, gate oxide can be formed by rapid thermal oxidation (RTO). Rapid thermal oxidation is a low-temperature oxidation deposition or low-temperature microwave plasma oxidation process on the silicon surface, and finally gate materials such as tungsten or aluminum can be deposited. At this time, gate stack self-alignment LDD (Lightly Doped Drain) and halo breakdown implantation can be performed to adjust the breakdown characteristics of contacts and transistors. Conventional gate sidewall deposition of oxide and nitride followed by etch back can be performed to form implanted inexpensive gate sidewalls (not shown) on the gate stack layer 10424 . Self-aligned N+ source and drain implants can then be performed to create transistor source and drain 10420 and remaining P-silicon NMOS (N-channel metal-oxide-semiconductor) transistor trenches 10428 . At this time, it is necessary to start implanting ions, set the initial joint depth, and whether to perform high-temperature annealing. Finally, a gap-fill oxide layer 10450 may cover the entire structure, which may be planarized by chemical-mechanical polishing (CMP). As mentioned above, the oxide surface can be used for bonding between the oxide and the oxide wafer.

As shown in FIG. 104E , repeating the transistor layer formation described in FIGS. 104A to 104D , the bonding of the acceptor wafer 10410 and the oxide layer 10450 , and the subsequent transistor formation process, can form the memory transistor second layer 10430 . After all desired memory layers are built, a rapid thermal anneal (RTA) can be performed to essentially turn on all memory layers and dopants in peripheral circuits of the acceptor substrate 10410. Alternatively, optical annealing, such as laser annealing, can be performed.

Contacts and metal wiring can be formed by photolithography and plasma/reactive ion etching as shown in FIG. 104F. The bit line (BL) contact 10440 is electrically connected to the N+ region of the storage layer transistor on the drain side 10454 of the transistor, and the source line contact 10442 is connected to the storage layer transistor on the source side 10452 of the transistor The N+ region is electrically coupled. Bit line (BL) wiring 10448 and source line (SL) wiring 10446 are electrically coupled to bit line 10440 and source line contact 10442 , respectively. A gate stack layer, such as 10434, may be connected with contacts and metallization regions (not shown) to form word line regions (WL). Through-layer vias 10460 (not shown) may be formed to electrically couple the metallized areas of BL, SL and WL to peripheral circuitry of the acceptor substrate 10410 through acceptor wafer metal connection pads 1980 (not shown).

As shown in Figure 104F, source line (SL) contact 10434 can be photolithographically and plasma/reactive ion etched through the oxide layer 10450, N+ silicon region 10420 and associated oxide vertical isolation regions of each memory layer , so as to be vertically connected to all storage layers. SL contacts can be processed by photoresist removal. The resistive memory material 10442, such as hafnium dioxide, may then be deposited, preferably by atomic layer deposition (ALD). The electrodes of the RRAM device may then be deposited by ALD to form SL electrodes/contacts 10434 . Excess deposited material should be polished so that it is on the same surface as or below the top of the oxide layer 10450. Each SL contact/electrode 10434 with resistive switching material 10442 can be fully shared with all memory layers, such as the three memory layers shown in FIG. 104F. The SL contact 10434 is electrically coupled to the storage layer transistor N+ region on the source side 10452 of the transistor. SL metal lines 10446 can be formed and connected to associated SL contacts 10434 using resistive switch material 10442. An oxide layer 10452 may be deposited and planarized. Bit line (BL) contacts 10440 are photolithographically and plasma/reactive ion etched through oxide 10450, N+ silicon regions 10420 and associated oxide vertical isolation regions of each memory layer to fully communicate with all The storage layer is connected vertically. BL contact 10440 is processed by photoresist stripping. The BL contact 10440 is electrically coupled to the N+ region of the storage layer transistor on the drain side 10454 of the transistor. BL metal lines 10448 can be formed and connected to associated BL contacts 10440 . A gate stack layer, such as 10424, may be connected with contacts and metallization regions (not shown) to form word line regions (WL). Through-layer vias 10460 (not shown) may be formed to electrically couple the metallized areas of BL, SL and WL to peripheral circuitry of the acceptor substrate 10410 through acceptor wafer metal connection pads 10480 (not shown).

The process forms resistive 3D memory using two additional masking steps per memory layer. 3D memory is constructed by layering wafer-sized doped monocrystalline silicon layers. At the same time, the 3D memory is connected to the underlying multi-metal layer semiconductor device.

One of ordinary skill would consider the examples mentioned in FIGS. 104A-104F to be representative examples only and not to scale. A skilled person can consider many more variations. For example, other types of transistors, such as PMOS (P-channel Metal Oxide Semiconductor) or RCAT, can be used. Alternatively, the stacked memory layer can be connected to peripheral circuits above the memory stack layer. In addition, each storage layer can be configured with a slightly different doping profile for the P-layer of the donor wafer. In addition, the memory can adopt different layout methods, such as BL and SL are interchanged, or where the wiring is buried, the wiring of the memory array can be placed below the storage layer and above the peripheral circuit. A reading of this specification will allow the skilled person to recall how to make modifications elsewhere within the scope of the invention. Accordingly, the invention is limited only by the appended claims.

Charge-trapping NAND (NAND) memory devices are another common commercially available non-volatile memory. A charge-trapping device stores its charge in a charge-trapping layer. The charge trapping layer in turn affects the transistor trench. For background information on charge-trapping memory, please refer to "Integrated Interconnection Technology for 3D Nanoelectronic Systems" (Altec Press; 2009; Authors: Bakir and Meindl - hereinafter referred to as Bakir), "A Method Using Junctionless Buried Ditch Highly Scalable 8-Layer 3D Vertical Gate (VG) TFT NAND Flash Memory for BE-SONOS Devices" (Symposium on VLSI Technology; 2010; Authors: Hang-Ting Lue et al.) and "Flash Memory Overview" (Proc. IEEE91; pp. 489-502 (2003); Author: Bez et al.). The device described by Bakir uses selective crystal growth, laser recrystallization, or polysilicon to form transistor trenches, resulting in suboptimal transistor performance. Any kind of charge trap memory can be used with the structures shown in Figs. 105 and 106 .

As shown in Figures 105A to 104G, a charge-trapping 3D memory can be constructed with two additional masking steps per memory layer. 3D memory is suitable for producing 3D IC. The 3D memory uses NAND strings of charge-trapping transistors built in single-crystal silicon.

As shown in Figure 105A, a P-substrate donor wafer 10500 is processed to include a wafer-sized P-doped layer 10504. The dopant concentration of the P-doped layer 10504 may be the same as that of the P-substrate 10500, or it may be different. P-doped layer 10504 may have a vertical doping gradient. The P-doped layer 10504 can be formed by ion implantation and high thermal annealing. A mask oxide layer 10501 may be grown prior to implantation to ensure that the silicon is free from contamination during the implantation process and to provide an oxide layer for later wafer-to-wafer bonding.

As shown in FIG. 105B, the top layer of the donor wafer 10500 can be used to bond the oxide wafer to the deposited layer of the oxide layer 10502, or through high thermal oxidation of the P-doped layer 10504, or implant the second layer of the mask oxide layer 10501. The secondary oxidation forms an oxide layer 10502. A layer transfer interface plane 10599 (dotted line in the figure) can be formed in the donor wafer 10500 or the P-layer 10504 (as shown) by hydrogen ion implantation 10507 or other methods described above. As previously described, both the donor wafer 10500 and the acceptor wafer 10510 can be used as a bond between the wafers, and then the two are bonded together. The above-mentioned bonding is best carried out at low temperature (not exceeding 400°C) to keep the stress at the lowest level. The P-layer portion 10504 above the layer transfer interface plane 10599 and the P-donor wafer substrate 10500 may be removed by dicing or grinding or a process as previously described (eg, ion dicing or other methods).

The remaining P-doping 10504' and oxide layer 10502 have been layer diced onto the acceptor wafer 10510 as shown in Figure 105C. The acceptor wafer 10510 may contain circuitry. This circuit can continue to operate and maintain good performance even after additional rapid thermal annealing (RTA). For this reason, when constructing peripheral circuits, it should be considered to select those peripheral circuits that can turn on the dopant only with a slight RTA or without RTA. In addition, the peripheral circuits can use refractory metals, such as tungsten with high temperature resistance over 400°C. The uppermost layer of the P-doped layer 10504' can be polished smooth and flat by chemical or mechanical means. The transistors are now formed and aligned with the alignment marks (not shown) of the acceptor wafer 10510.

As shown in Figure 105D, the shallow trench insulator (STI) oxide region (not shown) can be subjected to photolithography and plasma/reactive ion etching up to the top layer of the oxide layer 10502 to remove the P-monocrystalline silicon layer region 10504', and form a P-doped region 10520. A gap-fill oxide may be deposited and planarized by chemical-mechanical polishing (CMP) to form conventional STI oxide regions and P-doped monocrystalline silicon regions (not shown) to form transistors. Simultaneous injection with or without threshold adjustment can also be performed. By growth or charge-trapping gate dielectric 10522 (e.g. high thermal oxide layer and silicon nitride layer - ONO: Oxide-Nitride-Oxide) and gate metal material 10524 (e.g. doped or undoped polysilicon) deposition A gate stack layer may be formed. Likewise, the charge-trapping gate dielectric may comprise silicon or III-V nanocrystals encapsulated in oxide.

As shown in FIG. 105E , the gate stack layer 10528 can be subjected to photolithography and plasma/reactive ion etching to remove the gate metal material region 10524 and the charge trapping gate dielectric 10522 . Self-aligned N+ source and drain implants can be performed to form the inter-transistor source and drain 10534 and the ends 10530 of the NAND string source and drain. Finally, a gap-fill oxide layer 10550 and an oxide layer can cover the entire structure, which can be planarized by chemical-mechanical polishing (CMP). As mentioned above, the oxide surface can be used for bonding between the oxide and the oxide wafer. The first layer of storage transistors 10542 is now formed, comprising silicon dioxide layer 10550, gate stack layer 10528, inter-transistor source and drain 10534, NAND string source and gate terminations 10530, P-silicon region 10520 and Oxide layer 10502.

As shown in FIG. 105F, repeating the formation of the transistor layer described in FIGS. 105A to 105D, the bonding of the acceptor wafer 10510 and the oxide layer 10550, and the subsequent formation of the transistor can form a memory on top of the first layer of the storage transistor 10542. Bulk transistor second layer 10544. After all desired memory layers are built, a rapid thermal anneal (RTA) can be performed to essentially turn on dopants in all memory layers and peripheral circuitry of the acceptor substrate 10510. Alternatively, optical annealing, such as laser annealing, can be performed.

As shown in Figure 105G, source line (SL) contacts 10548 and bit line contacts 10549 are permeable through the oxide layer 10550 of each storage layer, NAND string source and drain terminals 10530, P-region 10520 and associated oxide Layer vertical isolation regions are subjected to photolithography and plasma/reactive ion etching to connect vertically to all memory layers. Then, the SL ground contacts and bit line contacts can be processed by photoresist removal. Contacts and metallization areas can be filled with metal or heavily doped polysilicon to form BL and SL wiring regions (not shown). A gate stack layer, such as 10528, can be connected with contacts and metallization areas to form word line regions (WL) and WL wiring regions (not shown). Through-layer vias 10560 (not shown) may be formed to electrically couple the metallized areas of BL, SL and WL to peripheral circuitry of the acceptor substrate 10510 through acceptor wafer metal connection pads 10580 (not shown).

The process creates charge-trapping 3D memory using two additional masking steps per memory layer. 3D memory is constructed by layering wafer-sized doped monocrystalline silicon layers. At the same time, the 3D memory is connected to the underlying multi-metal layer semiconductor device.

Those of ordinary skill may regard the examples mentioned in FIGS. 105A-105G as typical examples only and not to scale. Skilled people can consider more changes, for example, BL or SL selection transistors can be built through this process. Alternatively, the stacked memory layer can be connected to peripheral circuits above the memory stack layer. In addition, each storage layer can be configured with a slightly different doping profile for the P-layer of the donor wafer. In addition, the memory can adopt different layout methods, such as BL and SL interchange, or modify these structures into NOR flash memory storage format, or in the place where wiring is buried, the wiring of the storage array can be placed under the storage layer, around the above the circuit. In addition, charge-trapping insulating layers and gate layers may be deposited and temporarily bonded to carriers or wafer holders or substrates before layer dicing, and then transferred to the acceptor substrate using peripheral circuits. A reading of this specification will allow the skilled person to recall how to make modifications elsewhere within the scope of the invention. Accordingly, the invention is limited only by the appended claims.

As shown in FIGS. 106A to 106G, a charge-trapping 3D memory can be constructed without an additional masking process in each memory layer. 3D memory is suitable for producing 3D IC. The 3D memory uses NAND strings of charge-trapping junctionless transistors with junctionless select transistors built in single crystal silicon.

As shown in FIG. 106A , the silicon substrate with the peripheral circuit 10602 can use high temperature resistant (over 400° C.) wiring, such as tungsten wire. The peripheral circuit substrate 10602 may include memory control circuits and various circuits for other purposes, such as for analog, digital, radio frequency or storage. The peripheral circuit substrate 10602 may include peripheral circuits. This peripheral circuit can continue to operate even after additional rapid thermal annealing (RTA), maintaining good performance. For this reason, when constructing peripheral circuits, it should be considered to select those peripheral circuits that can turn on the dopant only with a slight RTA or without RTA. The uppermost layer of the peripheral circuit substrate 10602 can be used to bond the oxide wafer and the deposited layer of silicon dioxide 10604 to form the acceptor wafer 10614 .

As shown in FIG. 106B , a single crystal silicon donor wafer 10612 may include a wafer-sized N+ doped layer (not shown), which may have a different dopant concentration than the N+ substrate 10606 . The N+ doped layer can be formed by ion implantation and high thermal annealing. A mask oxide layer 10608 can be grown or deposited prior to implantation to ensure that the silicon is free from contamination during implantation and to provide an oxide layer for later wafer-to-wafer bonding. A layer transfer boundary plane 10610 (dotted line in the figure) can be formed in the N+ substrate 10606 or the donor wafer 10612 in the N+ doped layer (not shown) by hydrogen ion implantation or other methods described above. Both the donor wafer 10612 and the acceptor wafer 10614 are used for wafer bonding and are bonded together on the surfaces of the oxide layer 10604 and the oxide layer 10608 as previously described. Because the stress is lowest at low temperature, the bonding operation is best carried out at low temperature (below 400°C) or medium temperature (not exceeding 900°C).

As shown in FIG. 106C , the portion of the N+ layer (not shown) above the layer transfer interface plane 10610 and the N+ wafer substrate 10606 can be removed by dicing or grinding or the processes described above (such as ion cutting or other methods), thereby The remaining monocrystalline silicon N+ layer 10606 is formed. The remaining N+ layer 10606' and oxide layer 10608 are layer diced onto the acceptor wafer 10614. The uppermost layer of the N+ layer 10606' can be polished smooth and flat by chemical or mechanical means. An oxide layer 10620 may be deposited to provide a surface for later bonding between oxides. At this point, the first Si/SiO2 layer 10623 has been formed, including the silicon dioxide layer 10620, the N+ silicon layer 10606' and the oxide layer 10608.

As shown in FIG. 106D, Si/SiO2 layers shown in FIGS. 106A to 106C may be additionally formed, such as a second Si/SiO2 layer 10625 and a third Si/SiO2 layer 10627. An oxide layer 10629 may be deposited to provide isolation from the top N+ silicon layer.

As shown in Figure 106E, the oxide layer 10629, the third Si/SiO2 layer 10627, the second Si/SiO2 layer 10625 and the first Si/SiO2 layer 10623 can be photolithographically and plasma/reactive ion etched, Forms part of a memory wafer structure. The memory wafer structure now includes N+ silicon region 10626 and oxide layer region 10622 .

As shown in Figure 106F, by growing or depositing a charge-trapping gate dielectric (such as high thermal oxide layer and silicon nitride layer-ONO: Oxide-Nitride-Oxide) and a gate metal electrode layer (such as doped or Doped polysilicon) can form the gate stack layer. Then, the gate metal electrode layer can be planarized by chemical-mechanical polishing (CMP). Likewise, the charge-trapping gate dielectric may comprise silicon or III-V nanocrystals encapsulated in oxide. Select gate region 10638 may include a non-charge-trapping insulating layer. The gate metal electrode region 10630 and gate dielectric region 10628 of the NAND string region 10636 and select transistor region 10638 can be photolithographically and plasma/reactive ion etched.

As shown in FIG. 106G, a gap-fill oxide layer 10632 may cover the entire structure, which may be planarized by chemical-mechanical polishing (CMP). For clarity, the oxide layer 10632 is shown as a transparent layer in the figure. Select metal lines 10646 can be formed and connected together with associated select gate contacts 10634 . Contacts for WL and SL and associated metal routing (not shown) may be formed at the edge of the memory array. Word line region (WL) 10636, gate electrode 10630 and bit line region (BL) 10652, including N+ silicon region 10626 as shown. Source region 10644 is formed by contact etch and fill to bond to the N+ silicon region at the source end of NAND string 10636 . Through-layer vias 10660 (not shown) may be formed to electrically couple the metallized areas of BL, SL, and WL to peripheral circuitry of the acceptor substrate 10614 through acceptor wafer metal connection pads 10680 (not shown).

The process can form charge-trapping 3D memory without additional masking steps for each memory layer. 3D memory is constructed by layering wafer-sized doped monocrystalline silicon layers. At the same time, the 3D memory is connected to the underlying multi-metal layer semiconductor device.

Those of ordinary skill may consider the examples mentioned in FIGS. 106A-106G to be representative examples only and not to scale. People with high skills can consider more changes. For example, the ladder method described above can be used to build BL or SL contacts. Alternatively, the stacked memory layer can be connected to peripheral circuits above the memory stack layer. In addition, each storage layer can be configured with a slightly different doping profile for the N+ layer of the donor wafer. In addition, the memory can adopt different layout methods, such as BL and SL are interchanged, or where the wiring is buried, the wiring of the memory array can be placed below the storage layer and above the peripheral circuit. Other types of 3D charge-trapping memories can also be constructed through the method of monocrystalline silicon layer dicing, for example, in "A highly scalable 8-layer 3D vertical gate (VG) using a junctionless buried channel BE-SONOS device TFTNAND Flash Memory" (Symposium on VLSI Technology; 2010; Author: Hang-Ting Lue et al.) and "A Multilayer Vertical Gate NAND Flash Memory Overcomes the Stacking Limit of Terabit Density Memory" (Symposium on VLSI Technology; 2009; Authors: W.Kim, S.Choi, etc.). A reading of this specification will allow the skilled person to recall how to make modifications elsewhere within the scope of the invention. Accordingly, the invention is limited only by the appended claims.

Floating gate (FG) memory devices are another common type of commercial non-volatile memory. A floating-gate device stores its charge in a conductive gate (FG), which is nominally insulated from unintentional electric fields. In these electric fields, the charge on FG will in turn affect the trench of the transistor. Background information on floating gate flash memory can be found in "Overview of Flash Memory" (Proc. IEEE91; pages 489 to 502 (2003); author: R. Bez et al.). Any kind of floating gate memory can use the structure shown in Figs. 107 and 108.

As shown in Figures 107A to 104G, a floating gate 3D memory can be built with two additional masking steps per memory layer. 3D memory is suitable for producing 3D IC. The 3D memory uses NAND strings of floating-gate transistors built in single-crystal silicon.

As shown in Figure 107A, a P-substrate donor wafer 10700 is processed to include a wafer-sized P-doped layer 10704. The dopant concentration of the P-doped layer 10704 may be the same as that of the P-substrate 10700, or it may be different. P-doped layer 10704 may have a vertical doping gradient. The P-doped layer 10704 can be formed by ion implantation and high thermal annealing. A mask oxide layer 10701 can be grown prior to implantation to ensure silicon contamination during implantation and to provide an oxide layer for later wafer-to-wafer bonding.

As shown in FIG. 107B, the top layer of the donor wafer 10700 can be used to bond the oxide wafer to the deposited layer of the oxide layer 10702, or through high thermal oxidation of the P-doped layer 10704, or implant the second layer of the mask oxide layer 10701. The secondary oxidation forms an oxide layer 10702 . A layer transfer interface plane 10799 (dotted line in the figure) can be formed in the donor wafer 10700 or the P-layer 10704 (as shown) by hydrogen ion implantation 10707 or other methods described above. As previously described, both the donor wafer 10700 and the acceptor wafer 10710 can be used as a bond between the wafers, and then the two are bonded together. The above-mentioned bonding is best carried out at low temperature (not exceeding 400°C) to keep the stress at the lowest level. The P-layer portion 10704 and the P-donor wafer substrate 10700 above the dicing interface plane 10799 may be removed by dicing or grinding or the processes described above, such as ion dicing or other methods.

The remaining P-doping 10704&apos; and oxide layer 10702 have been layered onto the acceptor wafer 10710 as shown in Figure 107C. The acceptor wafer 10710 may contain circuitry. This circuit can continue to operate and maintain good performance even after additional rapid thermal annealing (RTA). For this reason, when constructing peripheral circuits, it should be considered to select those peripheral circuits that can turn on the dopant only with a slight RTA or without RTA. In addition, the peripheral circuits can use refractory metals, such as tungsten with high temperature resistance over 400°C. The uppermost layer of the P-doped layer 10704' can be polished smooth and flat by chemical or mechanical means. The transistors are now formed and aligned with the alignment marks (not shown) of the acceptor wafer 10710 .

As shown in FIG. 107D , a portion of the gate stack can be formed by growing or depositing a tunnel oxide layer 10722 (eg, a high thermal oxide layer) and an FG gate metal material 10724 (eg, doped or undoped polysilicon). Likewise, the charge-trapping gate dielectric may comprise silicon or III-V nanocrystals encapsulated in oxide. The shallow trench insulator (STI) oxide region (not shown) can be photolithographically and plasma/reactive ion etched down to the top layer of the oxide layer 10702 to remove the P- monocrystalline silicon layer region 10704 and form the P- Doped region 10720. A gap-fill oxide may be deposited and planarized by chemical-mechanical polishing (CMP), forming a conventional STI oxide (not shown).

As shown in FIG. 107E, a polysilicon oxide layer 10725 (such as a silicon dioxide layer and a silicon nitride layer—ONO: Oxide-Nitride-Oxide) and a control gate (CG) gate metal material 10726 (such as a doped or undoped polysilicon) may be deposited. The gate stack layer 10728 can be subjected to photolithography and plasma/reactive ion etching to remove the CG gate metal material region 10726 , the polysilicon oxide layer 10725 , the FG gate metal material 10724 and the tunnel oxide layer 10722 . The removal operation may form gate stack layer 10728 including CG gate metal region 10726 , polysilicon oxide region 10725 , FG gate metal region 10724 and tunnel oxide region 10722 . For clarity, only one gate stack layer 10728 is labeled in the area layer line. Self-aligned N+ source and drain implants can be performed to form inter-transistor source and drain 10734 and ends 10730 of NAND string source and drain. Finally, a gap-fill oxide layer 10750 may cover the entire structure, which may be planarized by chemical-mechanical polishing (CMP). As mentioned above, the oxide surface can be used for bonding between the oxide and the oxide wafer. The first layer of storage transistors 10742 is now formed, comprising silicon dioxide layer 10750, gate stack layer 10728, inter-transistor source and drain 10734, NAND string source and gate terminations 10730, P-silicon region 10720 and Oxide layer 10702.

As shown in FIG. 107F, repeating the formation of the transistor layer described in FIGS. 107A to 107D, the bonding of the acceptor wafer 10710 and the oxide layer 10750, and the subsequent formation of the transistor can form a memory on top of the first layer of the storage transistor 10742. Bulk transistor second layer 10744. After all desired memory layers are built, a rapid thermal anneal (RTA) can be performed to essentially turn on all memory layers and dopants in the surrounding circuitry of the acceptor substrate 10710. Alternatively, optical annealing, such as laser annealing, can be performed.

As shown in FIG. 107G, source line (SL) ground contact 10748 and bit line contact 10749 are permeable through oxide layer 10750 of each storage layer, NAND string source and drain terminals 10730, P-region 10720 and associated Oxide vertical isolation regions are photolithographically and plasma/reactive ion etched for vertical connection to all memory layers. The SL ground contact 10748 and the bit line contact 10749 can then be processed by photoresist removal. Contacts and metallization areas can be filled with metal or heavily doped polysilicon to form BL and SL wiring regions (not shown). A gate stack layer, such as 10728, can be connected with contacts and metallization areas to form word line regions (WL) and WL wiring regions (not shown). Through-layer vias 10760 (not shown) may be formed to electrically couple the metallized areas of BL, SL and WL to peripheral circuitry of the acceptor substrate 10780 through acceptor wafer metal connection pads 10710 (not shown).

The process creates floating-gate 3D memory using two additional masking steps per memory layer. 3D memory is constructed by layering wafer-sized doped monocrystalline silicon layers. At the same time, the 3D memory is connected to the underlying multi-metal layer semiconductor device.

Those of ordinary skill would consider the examples mentioned in Figures 107A-107G to be representative examples only and not to scale. Skilled people can consider more changes, for example, BL or SL selection transistors can be constructed through this process. Alternatively, the stacked memory layer can be connected to peripheral circuits above the memory stack layer. In addition, each storage layer can be configured with a slightly different doping profile for the P-layer of the donor wafer. In addition, the memory can adopt different layout methods, such as BL and SL are interchanged, or where the wiring is buried, the wiring of the memory array can be placed below the storage layer and above the peripheral circuit. A reading of this specification will allow the skilled person to recall how to make modifications elsewhere within the scope of the invention. Accordingly, the invention is limited only by the appended claims.

As shown in Figures 108A to 108H, a floating gate 3D memory can be constructed with an additional masking process at each memory layer. 3D memory is suitable for producing 3D IC. The 3D memory uses 3D floating gate junctionless transistors built in single crystal silicon.

As shown in FIG. 108A , the silicon substrate with the peripheral circuit 10802 can use high temperature resistant (over 400° C.) wiring, such as tungsten wire. The peripheral circuit substrate 10802 may include memory control circuits and various circuits for other purposes, such as analog, digital, radio frequency or storage. The peripheral circuit substrate 10802 may include peripheral circuits. This peripheral circuit can continue to operate even after additional rapid thermal annealing (RTA), maintaining good performance. For this reason, when constructing peripheral circuits, it should be considered to select those peripheral circuits that can turn on the dopant only with a slight RTA or without RTA. The uppermost layer of the peripheral circuit substrate 10802 can be used to bond the oxide wafer and the deposited layer of silicon dioxide 10804 to form the acceptor wafer 10814 .

As shown in FIG. 108B , a single crystal silicon N+ donor wafer 10812 may include a wafer-sized N+ doped layer (not shown), which may have a different dopant concentration than the N+ substrate 10806 . The N+ doped layer can be formed by ion implantation and high thermal annealing. A mask oxide layer 10808 may be grown or deposited prior to implantation to ensure that the silicon is free from contamination during implantation and to provide an oxide layer for later wafer-to-wafer bonding. A layer transfer boundary plane 10810 (dotted line in the figure) can be formed in the N+ substrate 10806 or the donor wafer 10812 in the N+ doped layer (not shown) by hydrogen ion implantation or other methods described above. Both the donor wafer 10812 and the acceptor wafer 10814 are used for wafer bonding and are bonded together on the surfaces of the oxide layer 10804 and the oxide layer 10808 as described above. Because the stress is lowest at low temperature, the bonding operation is best carried out at low temperature (below 400°C) or medium temperature (not exceeding 900°C).

As shown in FIG. 108C , the portion of the N+ layer (not shown) above the layer transfer boundary plane 10810 and the N+ wafer substrate 10806 can be removed by dicing or grinding or the processes described above (such as ion cutting or other methods), thereby The remaining monocrystalline silicon N+ layer 10806 is formed. The remaining N+ layer 10806' and oxide layer 10808 are layer diced onto the acceptor wafer 10814. The uppermost layer of the N+ layer 10806 can be polished smooth and flat by chemical or mechanical means. The transistors are now fully or partially formed and aligned with the alignment marks (not shown) of the acceptor wafer 10814 .

As shown in FIG. 108D , the N+ region 10816 can be subjected to photolithography and plasma/reactive ion etching to remove the N+ layer region 10806 and reside on or partially in the oxide layer 10808 .

As shown in Figure 108E, tunnel dielectric 10818 (such as high-temperature silicon dioxide) may be grown or deposited, and floating gate (FG) material 10828 (such as doped or undoped polysilicon) may be deposited. This structure may be substantially coplanar with the N+ region 10816 by chemical-mechanical polishing (CMP). As mentioned above, this surface can be used for bonding between oxide and oxide wafer, such as deposition between thin layers of oxide. The first storage layer 10823 has now been formed, including the future FG region 10828 , tunnel dielectric 10818 , N+ region 10816 and oxide layer 10808 .

As shown in FIG. 108F , the second layer 10825 of memory can be formed on top of the first layer of the memory layer 10823 by repeating the N+ layer formation, acceptor wafer bonding, and subsequent formation of the memory layer described in FIGS. 108A to 108E . An oxide layer 10829 may then be deposited.

As shown in Figure 108G, the FG region 10838 can be chemically mechanically polished (CMP) to remove the oxide layer portion 10829 on the second storage layer 10825, the future FG region 10828 and oxide layer 10808, and the first storage layer The future FG region 10828 on 10823 stays on the oxide layer 10808 of the first storage layer 10823 or partially stays in the oxide layer 10808 .

As shown in FIG. 108H, a polysilicon oxide layer 10850 (such as a silicon dioxide layer and a silicon nitride layer—ONO: Oxide-Nitride-Oxide) and a control gate (CG) gate material 10852 (such as doped or doped polysilicon) may be deposited. The surface is planarized by chemical-mechanical polishing (CMP), resulting in a thin oxide layer 10829'. This results in information about four horizontally oriented floating gate memory chips with N+ junctionless transistors, as shown. Contacts and metal wiring forming the well-known memory egress/decoding circuitry can be processed to form through-layer vias (TLVs). The metal connection pad of the acceptor wafer is electrically coupled with the outlet of the memory, and the peripheral circuit of the acceptor substrate is decoded.

The process creates floating-gate 3D memory, using an additional masking process for each memory layer. 3D memory is constructed by layering wafer-sized doped monocrystalline silicon layers. At the same time, the 3D memory is connected to the underlying multi-metal layer semiconductor device.

One of ordinary skill would consider the examples mentioned in FIGS. 108A-108H to be representative examples only and not to scale. Skilled people can consider more variations, for example, memory chip control lines can be built on different layers (rather than the same layer). Alternatively, the stacked memory layer can be connected to peripheral circuits above the memory stack layer. In addition, each storage layer can be configured with a slightly different doping profile for the N+ layer of the donor wafer. In addition, the memory can adopt different layout methods, such as BL and SL interchange, or modify these structures into NOR flash memory storage format, or in the place where wiring is buried, the wiring of the storage array can be placed under the storage layer, around the above the circuit. A reading of this specification will allow the skilled person to recall how to make modifications elsewhere within the scope of the invention.

The monolithic 3D integration concept mentioned in this patent application can lead to novel examples of polysilicon-based memory structures. When using the resistive memory structure as an example to explain the concepts in Figures 109 and 110 below, those familiar with the field can clearly see that similar concepts can be used in NAND flash memory, charge trapping memory, DRAM memory structure and the processing flow described above in this patent application.

As shown in Figures 109A to 109K, a resistive 3D memory can be constructed without additional masking process in each memory layer, and the method is suitable for the production of 3D ICs. The 3D memory uses polysilicon junctionless transistors. This transistor uses a positive or secondary threshold voltage and a resistive memory component in series with a select or access transistor.

As shown in FIG. 109A , the silicon substrate with the peripheral circuit 10902 can use high temperature (over 400° C.) wiring, such as tungsten wire. The peripheral circuit substrate 10902 may include memory control circuits and various circuits for other purposes, such as for analog, digital, radio frequency or storage. The peripheral circuit substrate 10902 may include peripheral circuits. This peripheral circuit can continue to operate even after additional rapid thermal annealing (RTA), maintaining good performance. For this reason, when constructing peripheral circuits, it should be considered to select those peripheral circuits that only require partial or slight RTA or can turn on the dopant without RTA. A silicon dioxide layer 10904 is deposited on top of the peripheral circuit substrate.

As shown in Figure 109B, an N+ doped polysilicon layer or amorphous silicon layer 10906 may be deposited. The amorphous silicon layer or polysilicon layer 10906 can be deposited by chemical vapor deposition (such as low pressure chemical vapor deposition - LPCVD or plasma enhanced chemical vapor deposition - PECVD or other process methods). N+ dopant, such as arsenic or phosphorus, can be doped during deposition; it can also be undoped during deposition, and then doped after deposition, for example, using ion implantation or PLAD (plasma doping) technology. A silicon dioxide layer 10920 may then be deposited or grown. The first Si/SiO2 layer 10923 is now formed, comprising an N+ doped polysilicon layer or amorphous silicon layer 10906 and a silicon dioxide layer 10920 .

As shown in FIG. 109C, Si/SiO2 layers shown in FIG. 109B may be additionally formed, such as a second Si/SiO2 layer 10925 and a third Si/SiO2 layer 10927. An oxide layer 10929 may be deposited to provide insulation from the top N+ doped polysilicon or amorphous silicon layer.

As shown in Figure 109D, rapid high thermal annealing (RTA) can be performed to make the N+ doped polysilicon layer of the first Si/SiO2 layer 10923, the second Si/SiO2 layer 10925 and the third Si/SiO2 layer 10927 or non- The crystalline silicon layer 10906 is crystallized to form a crystallized N+ silicon layer 10916 . The temperature can be as high as 800°C during RTA. Alternatively, optical annealing (such as laser annealing) can be used alone, or optical annealing and RTA can be used at the same time, or other annealing processes can be used.

As shown in Figure 109E, the oxide layer 10929, the third Si/SiO2 layer 10927, the second Si/SiO2 layer 10925 and the first Si/SiO2 layer 10923 can be subjected to photolithography and plasma/reactive ion etching, Forms part of a memory wafer structure. The memory chip structure now includes multilayer crystallized N+ silicon region 10926 (previously crystallized N+ silicon layer 10916 ) and oxide layer region 10922 .

As shown in Figure 109F, gate dielectric and gate electrode material may be deposited, planarized by chemical-mechanical polishing (CMP), and then photolithography and plasma/reactive ion etching may be performed to form the gate electrode. Pole dielectric region 10928. Gate dielectric region 10928 may be self-aligned with and covered by gate electrode 10930 (as shown), or may substantially cover the entire N+ silicon region 10126 and oxide region 10922 multilayer structure. The gate stack layer (comprising gate electrode 10930 and gate dielectric region 10928) consists of a gate dielectric region (eg, high thermal oxide) and a gate electrode material (eg, polysilicon). Alternatively, the gate dielectric can be selected from an atomic layer deposition (ALD) material that matches the work function of the specific gate metal, in line with the industry standard for high-k metal gate process solutions described above. In addition, the gate dielectric can be formed by rapid thermal oxidation (RTO). Rapid thermal oxidation is a process of low-temperature oxidation deposition or low-temperature microwave plasma oxidation on the surface of silicon, which can eventually be deposited as a gate electrode, such as a tungsten electrode or an aluminum electrode.

As shown in Figure 109G, a gap-fill oxide layer 10932 may cover the entire structure, which may be planarized by chemical-mechanical polishing. For clarity, the oxide layer 10932 is shown as a transparent layer in the figure. In addition, there are word line regions (WL) 10950, gate electrodes 10930, source line regions (SL) 10952 and crystallized N+ silicon regions 10926 as shown.

As shown in Figure 109H, the bit line (BL) contact 10934 can be photolithographically and plasma/reactive ion etched through the oxide layer 10932, the three crystallized N+ silicon regions 10926 and the associated oxide layer vertical isolation regions, In order to fully connect vertically to all memory layers, followed by photoresist removal. The resistive memory material 10938, such as hafnium dioxide or titanium oxide, may then be deposited, preferably by atomic layer deposition (ALD). The electrodes of the RRAM device may then be deposited by ALD to form electrode/BL contacts 10934 . Excess deposited material should be polished so that it is on the same surface as or below the top of the oxide layer 10932. Each BL contact 10934 with resistive material 10938 can be fully shared with all storage layers, such as the three storage layers shown in FIG. 109H.

As shown in FIG. 109I , BL metal lines 10936 can be formed and connected to the associated BL contacts 10934 with resistive material 10938 . Contacts for WL and SL and associated metal wiring (not shown) may be formed at the edge of the memory array. Through layer vias 10960 (not shown) may be formed to electrically couple the metallized areas of BL, SL and WL to the acceptor substrate peripheral circuitry through acceptor wafer metal connection pads 10980 (not shown).

The second cross-sectional view of Figure 109J is shown in Figure 109J1, and the third cross-sectional view of Figure 109J is shown in Figure 109J2. Figure 101J1 shows BL metal line 10936, oxide layer 10932, BL contact/electrode 10934, resistive switch material 10938, WL region 10950, gate dielectric 10928, crystallized N+ silicon region 10926 and peripheral circuit substrate 10902. The BL contact/electrode 10934 is connected to one of the three horizontal planes of the resistive material 10938 . The other side of the resistive material 10938 is connected to the crystallized N+ region 10196 . BL metal line 10936, oxide layer 10932, gate electrode 10930, gate dielectric 10928, crystallized N+ silicon region 10926, interlayer oxide region (OX) and peripheral circuit substrate 10902 are shown in FIG. 109J2. Gate electrodes 10930 are common in the six crystallized N+ silicon regions 10926, which form six double-sided gate-controlled junctionless transistors as memory select transistors.

As shown in FIG. 109K, a typical double-sided gate-controlled junctionless transistor on the first Si/SiO2 layer 10923 may include crystallized N+ silicon regions 10926 (serving as source, drain and transistor trench) and double gate electrode 10930 (with corresponding gate insulating layer 10928). The transistors are insulated from below by the oxide layer 10908 .

The process can form resistive multilayer or 3D memory arrays without additional masking steps for each memory layer. The storage layer uses a junctionless polysilicon transistor, and its resistive memory component is connected in series with the selection transistor. The memory array is constructed by layering wafer-sized doped polysilicon layers. At the same time, the 3D memory array is connected to the underlying multi-metal layer semiconductor device.

One of ordinary skill would consider the examples mentioned in FIGS. 109A-109K to be representative examples only, and not scaled down. A skilled person can consider more variations. For example, RTA and/or optical annealing can be performed on the N+ doped polysilicon layer or amorphous silicon layer 10906 in FIG. 109D after the formation of the Si/SiO2 layers in FIG. 109C. In addition, the N+ doped polysilicon layer or amorphous silicon layer 10906 can be doped with P+, or dopants and other polysilicon network modifiers can be added at the same time to enhance the RTA or optical annealing effect and subsequent crystallization effect, and reduce the N+ Resistivity of silicon layer 10916. In addition, the dopant of the crystallized N+ layer may vary slightly when compensating for interconnect resistance. In addition, each gate of dual-gated 3D resistive memory can be independently controlled to better control the memory chip. A reading of this specification will allow the skilled person to recall how to make modifications elsewhere within the scope of the invention. Accordingly, the invention is limited only by the appended claims.

As shown in Figures 110A to 110J, another example of a resistive 3D memory that can be built in each memory layer without additional masking process, the method is suitable for the production of 3D IC. The 3D memory uses polysilicon junctionless transistors. This transistor uses a positive or secondary threshold voltage and a resistive memory component in series with a select or access transistor. It facilitates the formation of peripheral circuit layers or layer cutting of circuit layers on top of 3D memory arrays.

A silicon dioxide layer 11004 may be deposited or grown on top of the silicon substrate 11002 as shown in FIG. 110A .

As shown in FIG. 110B, an N+ doped polysilicon layer or an amorphous silicon layer 11006 may be deposited. The amorphous silicon layer or polysilicon layer 11006 can be deposited by chemical vapor deposition (such as low pressure chemical vapor deposition - LPCVD or plasma enhanced chemical vapor deposition - PECVD or other process methods). N+ dopant, such as arsenic or phosphorus, can be doped during deposition; it can also be undoped during deposition, and then doped after deposition, for example, using ion implantation or PLAD (plasma doping) technology. A silicon dioxide layer 11020 may then be deposited or grown. Now the first Si/SiO2 layer 11023 is formed, including N+ doped polysilicon layer or amorphous silicon layer 11006 and silicon dioxide layer 11020 .

As shown in FIG. 110C, Si/SiO2 layers shown in FIG. 110B may be additionally formed, such as a second Si/SiO2 layer 11025 and a third Si/SiO2 layer 11027. An oxide layer 11029 may be deposited to provide insulation from the top N+ doped polysilicon or amorphous silicon layer.

As shown in Figure 110D, rapid high thermal annealing (RTA) can be performed to make the N+ doped polysilicon layer of the first Si/SiO2 layer 11023, the second Si/SiO2 layer 11025 and the third Si/SiO2 layer 11027 or non- The crystalline silicon layer 11006 is crystallized to form a crystallized N+ silicon layer 11016 . Alternatively, optical annealing (such as laser annealing) can be used alone, or optical annealing and RTA can be used at the same time, or other annealing processes can be used. During the RTA process the temperature can be as high as 700°C and can even reach 1400°C. Since there is no circuit or metallization layer under these crystallized N+ silicon layers, very high temperature (such as 1400°C) can be used in the annealing process, so that the quality of polysilicon is very good, there are few grain boundaries, and the carriers are close to each other. Monocrystalline silicon is more flexible.

As shown in Figure 110E, the oxide layer 11029, the third Si/SiO2 layer 11027, the second Si/SiO2 layer 11025 and the first Si/SiO2 layer 11023 can be subjected to photolithography and plasma/reactive ion etching, Forms part of a memory wafer structure. The memory chip structure now includes multilayer crystallized N+ silicon region 11026 (previously crystallized N+ silicon layer 11016) and oxide layer region 11022.

As shown in Figure 110F, the gate dielectric and gate electrode material may be deposited, planarized by chemical-mechanical polishing (CMP), and then photolithography and plasma/reactive ion etching may be performed to form the gate electrode. Pole dielectric region 11028. The gate dielectric region 11028 may be self-aligned with and covered by the gate electrode 11030 (as shown), or may cover the entire crystallized N+ silicon region 11026 and oxide region 11022 multilayer structure. The gate stack layer (comprising gate electrode 11030 and gate dielectric 11028) consists of a gate dielectric (eg, high thermal oxide) and a gate electrode material (eg, polysilicon). Alternatively, the gate dielectric can be selected from an atomic layer deposition (ALD) material that matches the work function of the specific gate metal, in line with the industry standard for high-k metal gate process solutions described above. In addition, the gate dielectric can be formed by rapid thermal oxidation (RTO). Rapid thermal oxidation is a process of low-temperature oxidation deposition or low-temperature microwave plasma oxidation on the surface of silicon, which can eventually be deposited as a gate electrode, such as a tungsten electrode or an aluminum electrode.

As shown in FIG. 110G, a gap-fill oxide layer 11032 may cover the entire structure, which may be planarized by chemical-mechanical polishing. For clarity, the oxide layer 11032 is shown as a transparent layer in the figure. In addition, there are word line regions (WL) 11050, gate electrodes 11030, source line regions (SL) 11052 and crystallized N+ silicon regions 11026 as shown.

As shown in Figure 110H, the bit line (BL) contact 11034 can be photolithographically and plasma/reactive ion etched through the oxide layer 11032, the three crystallized N+ silicon regions 11026 and the associated oxide layer vertical isolation regions, In order to be vertically connected to all storage layers. BL contact 11034 is processed by photoresist stripping. A resistive memory material 11038, such as hafnium dioxide or titanium oxide, may then be deposited, preferably by atomic layer deposition (ALD). The electrodes of the RRAM device may then be deposited by ALD to form electrode/BL contacts 11034 . Excess deposited material should be polished so that it is on the same surface as or below the top of the oxide layer 11032. Each BL contact 11034 with resistive material 11038 can be fully shared with all storage layers, such as the three storage layers shown in FIG. 110H.

As shown in FIG. 110I , a BL metal line 11036 can be formed and connected to a related BL contact 11034 with a resistive material 11038 . Contacts for WL and SL and associated metal wiring (not shown) may be formed at the edge of the memory array.

As shown in FIG. 110J, the peripheral circuit 11078 can be constructed using the methods described above (such as ion dicing and replacing the gate), and then layer cut to the memory array, and then form through-layer vias (not shown), so that the The peripheral circuits are electrically coupled to the memory arrays BL, WL, SL and other connection lines, such as power lines and ground lines. Alternatively, peripheral circuits can be built using layer-cut wafer-sized doped layers and subsequent processing (such as junctionless, trench-arranged transistors, V-groove, or bipolar transistor molding processes as described above), and Align directly with memory array and silicon substrate 11002.

The process can form resistive multilayer or 3D memory arrays without additional masking steps for each memory layer. The storage layer uses a junctionless polysilicon transistor, and its resistive memory component is connected in series with the selection transistor. The memory array is constructed by layering wafer-sized doped polysilicon layers. At the same time, the 3D storage array is connected with the upper multi-metal layer semiconductor device or peripheral circuits.

One of ordinary skill would consider the examples mentioned in FIGS. 110A-110J to be representative examples only and not to scale. A skilled person can consider more variations. For example, RTA and/or optical annealing can be performed on the N+ doped polysilicon layer or amorphous silicon layer 11006 in FIG. 110D after the formation of the Si/SiO2 layers in FIG. 110C. In addition, the N+ doped polysilicon layer or amorphous silicon layer 11006 can be doped with P+, or dopants and other polysilicon network modifiers can be added at the same time to enhance the RTA or optical annealing effect and subsequent crystallization effect, and reduce the N+ Resistivity of silicon layer 11016. In addition, the dopant of the crystallized N+ layer may vary slightly when compensating for interconnect resistance. In addition, each gate of dual-gated 3D resistive memory can be independently controlled to better control the memory chip. Moreover, standard CMOS transistors can be processed at high temperatures (over 700°C) by selecting the correct storage layer transistors and storage layer wire materials (such as using tungsten wire and other materials that can withstand high temperatures during wiring processing), A peripheral circuit 11078 is formed. A reading of this specification will allow the skilled person to recall how to make modifications elsewhere within the scope of the invention. Accordingly, the invention is limited only by the appended claims.

Monolithic 3D DRAM is another example of the present invention, which we call NuDRAM. It may use the layering and cutting methods mentioned in this document. This method can provide high-quality monocrystalline silicon with less change in effective heat, which is a qualitative leap in the existing technology.

An example of the present invention can be constructed by taking the flow shown in Fig. 88(A) to (F). Figure 88(A) depicts the first step of the process. N-type dopants can be implanted into the p- wafer 8801 to form the n+ layer 8802, followed by RTA. The n+ layer 8802 can also be formed by the method of crystal-like growth.

Figure 88(B) shows the next step in the process. Hydrogen can be implanted into the wafer at a certain depth in the p-region 8801 . The final position of the hydrogen is shown by dashed line 8803.

Figure 88(C) depicts the next step in the process. The wafer is attached to the wafer temporary carrier 8804 using an adhesive. For this purpose, for example, we can bond the wafer to the wafer temporary carrier 8804 made of glass using a polyimide adhesive from DuPont. The wafer can then be diced on the hydrogen plane 8803 using the dicing method described in this document. After dicing, chemical-mechanical polishing is used to polish the cut surface so that an oxide layer 8805 is deposited on the surface. The wafer structure after all steps are fully completed is shown in FIG. 88(C).

Figure 88(D) shows the next step in the process. A wafer with DRAM peripheral circuits 8806 (eg sense amplifiers, row decoders, etc.) can now be used as the base. The wafer in Figure 88(C) can be attached on top of the base using oxide-oxide bonding on surface 8807. The temporary carrier 8804 can now be removed. Masking, etching and oxidation operations can then be performed to define diffusion rows, insulated by an oxide layer similar to 8905 in Figure 89(B). The diffusion and isolation rows may be aligned with the underlying peripheral circuitry 8806 . After the insulating region is formed, RCAT (Recessed Array Transistor) can be constructed by etching and then depositing gate dielectric 8809 and gate electrode 8808 . This procedure is further explained in the description of Figure 67. The gate electrode mask can be aligned with the underlying peripheral circuitry 8806 . An oxide layer 8810 may be deposited and polished by chemical-mechanical polishing.

Figure 88(E) shows the next step in the process. A second RCAT layer 8812 can be formed on top of the first RCAT layer 8811 using steps similar to those in FIGS. 88(A)-(D). By repeating the above steps several times, an ideal multi-layer 3D DRAM can be obtained.

Figure 88(F) depicts the next step in the process. Vias may be etched completely through all stack layers to source 8814 and drain 8815. Since this step is repeated during alignment with the peripheral circuit 8806, an etch stop layer is required, otherwise fragile components should not be placed under the designated etch position. This is similar to a traditional DRAM array. In a conventional DRAM array, gates 8816 of multiple RCAT transistors are connected by polysilicon wires or metal lines perpendicular to the plane in FIG. 88 . Connecting the gate electrodes can form word lines similar to those illustrated in Figures 89A-D. The layout will expand the word lines of the multi-layer DRAM structure, so that there is a vertical contact hole connection on each layer, so that the peripheral circuit 8806 can individually control the word lines of each layer. Then it can be filled with heavily doped polysilicon 8813. The heavily doped polysilicon 8813 can be constructed by a low temperature (less than 400°C) process (such as PECVD). The heavily doped polysilicon 8813 can not only improve the contacts of multiple sources, drains and word lines of 3D DRAM, but also can separate adjacent p-layers 8817 and 8818. Alternatively, an oxide layer can also be used for isolation. Then, multi-layer interconnection layers and through holes can be built to form bit lines 8815 and source lines 8814 to complete the entire DRAM array. The RCAT transistor is shown in Figure 88. Other types of low temperature stacked transistors can also be constructed using a process flow similar to that shown in Figures 88A-F. For example, V-groove transistors and other transistors described in other examples in this invention can be constructed.

Figures 89(A)-(D) show a side view, layout and schematic diagram, respectively, of a portion of the NuDRAM array depicted in Figures 88(A)-(F). Figure 89(A) shows a specific cross-sectional view of a NuDRAM array. Bit lines (BL) 8902 may run in a direction perpendicular to word lines (WL) 8904 and source lines (SL) 8903 .

Fig. 89(B) shows a cross-sectional view seen from a plane indicated by a dotted line. The oxide insulating region 8905 can separate the p-layer 8906 of adjacent transistors. Essentially, the WL8907 can consist of the gate electrodes of individual transistors connected together.

Figure 89(C) shows the layout of this array. WL wiring 8908 and SL wiring 8909 may be perpendicular to BL wiring 8910. The schematic diagram of the NuDRAM array (Fig. 89(D)) reveals the connection of WL, BL and SL at the array level.

Figure 90(A)-(F) depicts another example of the present invention. Figure 90(A) depicts the first step of the process. The p-wafer 9001 comprises an n+ quasi-like growth layer 9002 and a p- quasi-like growth layer 9003 grown over the n+ quasi-like growth layer. In addition, these layers are also formed by implantation. An oxide layer 9004 may also be grown or deposited over the wafer.

Figure 90(B) shows the next step in the process. Hydrogen H+ or other atomic species can be implanted into the wafer at a certain depth in the n+ region 9002 . The final position of the hydrogen is shown by dashed line 9005.

Figure 90(C) describes the next step in the process. The wafer is turned over and pasted on the wafer with DRAM peripheral circuit 9006 by way of bonding between oxides. The wafer can then be diced on the hydrogen plane 9005 using the low temperature (below 400°C) dicing method described in this document. After cutting, chemical-mechanical polishing can be used to polish the cut surface.

As shown in Fig. 90(D), masking, etching and low temperature oxide deposition operations can be performed to define the diffusion rows insulated by the above oxide layer. The aforementioned diffusion row and isolation row may be aligned with the peripheral circuit 9006 below. After the insulating region is formed, a RCAT (recessed array transistor) can be constructed through masking, etching, and depositing gate dielectric 9009 and gate electrode 9008 . This procedure is further explained in the description of Figure 67. The above-mentioned gates can be aligned with the peripheral circuit 9006 below. An oxide layer 9010 may be deposited and polished by chemical-mechanical polishing.

Figure 90(E) shows the next step in the process. A second RCAT layer 9012 can be formed on top of the first RCAT layer 9011 using steps similar to those in FIGS. 90(A)-(D). By repeating the above steps several times, an ideal multi-layer 3D DRAM can be obtained.

Figure 90(F) depicts the next step in the process. Vias can be etched completely through all stacked layers to source and drain connection lines. This is similar to a traditional DRAM array. In a conventional DRAM array, gate electrodes 9016 of multiple RCAT transistors are connected by polysilicon wires perpendicular to the plane in FIG. 90 . Connecting the gate electrodes can be formed similar to word lines. The layout will expand the word lines of the multi-layer DRAM structure so that there is a vertical hole on each layer, so that the peripheral circuit 9006 can individually control the word lines of each layer. Then it can be filled with heavily doped polysilicon 9013 . The heavily doped silicon 9013 can be constructed by a low temperature (less than 400°C) process (such as PECVD). Then, multi-layer interconnection layers and through holes can be constructed to form bit lines 9015 and source lines 9014 to complete the entire DRAM array. The array structure of the NuDRAM depicted in FIG. 90 is similar to the array in FIG. 89 . The RCAT transistor is shown in Figure 90. Other types of low-temperature stacked transistors can also be constructed using a process flow similar to that shown in FIG. 90 . For example, V-groove transistors and other transistors in other instances of the invention described above can be constructed.

Other process flows for building NuDRAM are shown in Figures 91A-L. The process described beginning with FIG. 91A shows a shaped trench insulation layer 9102 in an SOI p-wafer 9101 . The buried oxide layer is marked as 9119.

Subsequently, gate trench etching 9103 is performed as shown in FIG. 91B. FIG. 91A shows a cross-sectional view of NuDRAM on the XZ plane, and FIG. 91B is a cross-sectional view on the YZ plane (so the shallow trench insulating layer 9102 is not marked in FIG. 91B ).

Figure 91C illustrates the next step in the process. A gate dielectric layer 9105 and RCAT gate electrode 9104 can be formed using a procedure similar to that of Figure 67E. Next, ion implantation can be performed to form the source and drain of the n+ region 9106 .

FIG. 91D shows the forming and grinding process of the interlayer dielectric layer 9107.

91E shows the next step in the process. Another p-wafer 9108 may be taken. An oxide layer 9109 is grown on the p-wafer 9108 . For the purpose of dicing, hydrogen H+ or other atomic species can be implanted into the wafer 9108 at a certain depth at 9110 .

This "upper layer" 9108 can then be flipped over and attached to the lower wafer 9101 by way of oxide-to-oxide bonding. Dicing can then be performed on the hydrogen plane 9110 followed by chemical-mechanical polishing to obtain the structure shown in Figure 91F.

Figure 91G shows the next step in the process. Another layer of RCAT 9113 can be built using a procedure similar to that shown in Figures 91B-D. This layer of RCAT can be aligned with features of the bottom wafer 9101.

As shown in Figure 91H, one or more layers of RCAT 9114 can be constructed using a procedure similar to that shown in Figures 91B-D.

Figure 91I shows vias 9115 formed to different n+ regions and WL layers. These vias 9115 may be constructed using heavily doped polysilicon.

Figure 91J illustrates the next step in the process. This step allows rapid thermal annealing (RTA) to turn on the implanted dopants and fully crystallize the polysilicon regions in all layers.

Figure 91K shows bit line BL 9116 and source line SL 9117 formed.

After BL 9116 and SL 9117 are formed, Figure 91L shows the method of forming a new layer of transistors and vias for DRAM peripheral circuit 9118 using the procedure described above (for example, using the method of Figure 29A-G to form a V-groove MOSFET) . These peripheral circuits 9118 may be aligned with the underlying DRAM transistor layer. The DRAM transistor in this case can be of any type (transistors processed at high temperature (that is, over 400°C) or low temperature (that is, below 400°C) can be used); since the peripheral circuit will be in the aluminum or copper wiring layer 9116 and For construction after 9117, the peripheral circuit can use transistors processed at low temperature. The array structure for the case in FIG. 91 may be similar to the array structure shown in FIG. 89 .

The evolution flow shown in Figures 91A-L can be used as an alternative flow for making NuDRAM. The peripheral circuit layer can be built before RTA after all steps of the transistor are completed. One or more layers of tungsten metal may be used in the local wiring of these peripheral circuits. Afterwards, as shown in Figure 91, the layer cutting method can be used to construct multi-layer RCAT, followed by RTA. Next, layers of highly conductive copper or aluminum lines can be added to complete the DRAM process. By sharing the high-temperature step RTA and thoroughly processing all the crystallization layers at one time, this process reduces the production cost, and can also be used in the peripheral circuits of 3D NuDRAM similar to the settings used in traditional 2D DRAM. In this process flow, any type of DRAM transistor can be used, not limited to low-temperature lithography transistors, such as RCAT or V-groove transistors.

Figures 92A-F show a NuDRAM constructed using partially depleted SOI transistors. Figure 99A depicts the first step of the process. An oxide layer 9202 may be grown on the p-wafer 9201. 92B shows the next step in the process. Hydrogen can be implanted into the wafer at a certain depth in p-region 9201 . The final position of the hydrogen is shown by dashed line 9203. Figure 92C illustrates the next step in the process. A wafer with DRAM peripheral circuits 9204 can be prepared. This wafer has transistors that have not been RTA processed. In addition, peripheral circuits can also perform slight or partial RTA. Fabricate the multilayer tungsten interconnects that connect the transistors in the 9204 together. The wafer in FIG. 92B is flipped over and pasted onto the wafer with DRAM peripheral circuits 9204 by means of oxide-to-oxide bonding. The wafer can then be diced on the hydrogen plane 9203 using the dicing method described in this document. After cutting, the cut surface is polished by chemical-mechanical polishing. Figure 92D illustrates the next step in the process. As shown in Figure 92D, masking, etching, and low temperature oxide deposition operations can be performed to define the diffusion rows insulated by the oxide. The aforementioned diffusion row and isolation row may be aligned with the peripheral circuit 9204 below. After the insulating region is formed, a partially depleted SOI (PD-SOI) transistor is constructed to form the gate dielectric 9207 and the gate electrode 9205, and then the 9207 and 9205 are patterned and etched, and then the ion implantation source/drain is formed. Polar Region 9208. Note that there is no need for RTA to turn on the implant source/drain regions 9208 in this step. The mask shown in Figure 92D can be aligned with the underlying peripheral circuitry 9204. An oxide layer 9206 may be deposited and polished by chemical-mechanical polishing. 92E shows the next step in the process. A second layer of PD-SOI transistors 9209 can be formed on top of the first layer of PD-SOI transistors by following steps similar to those in Figures 92A-D. By repeating the above steps several times, an ideal multi-layer 3D DRAM can be obtained. Next, RTA can be performed to turn on the dopant and completely crystallize the polysilicon regions of all transistor layers. Figure 92F depicts the next step in the process. Vias 9210 may be masked and etched completely through all stack layers to word lines, source and drain connection lines. Please note that the gates of transistors 9213 are connected in a manner similar to that shown in Figure 89 to form word lines. The vias may then be filled with a metal such as tungsten. Alternatively, heavily doped polysilicon can be used. Then, multi-layer interconnection layers and through holes can be constructed to form bit lines 9211 and source lines 9212 to complete the entire DRAM array. The array structure of the NuDRAM described in FIG. 92 is similar to the array in FIG. 89 .

For programming transistors, it is sufficient to use one type of upper layer transistor. For logic type circuits, two complementary transistors may be more beneficial for CMOS type logic devices. Therefore, the various monolithic transistor processes described above can be performed twice. All steps are performed thoroughly first to build the "n" type transistor, followed by one more layer cut to build the "p" type transistor on top of the "n" type transistor.

Another approach is to build "n" type transistors and "p" type transistors on the same layer. The difficulty is how to align these transistors with the layer 808 below. The innovative solution will be described below with reference to FIGS. 30 to 33 . This process is applicable to any transistor built in a way suitable for wafer transfer, including but not limited to horizontal or vertical MOSFETs, JFETs, horizontal and vertical junctionless transistors, RCAT and spherical RCAT, etc. As shown in Figure 30, the main difference is that the donor wafer 3000 has now been pre-processed to build not just one type of transistor, but two types of transistors, including the "n" type transistor 3004 on the donor wafer 3000 Alternate between the trips and the trips to build "p"-type transistors. FIG. 30 also shows indicators 3040 of the four cardinal directions, which are explained in FIG. 33 . The width of the n-type row 3004 is Wn, the width of the p-type row 3006 is Wp, and the sum of the two, W 3008, is equal to the width of the repeated pattern. Rows repeat from east to west, and alternating rows repeat from north to south. Donor wafer rows 3004 and 3006 extend lengthwise from east to west for a distance equal to the width of the acceptor die plus the maximum distance between the donor wafer and the acceptor wafer misalignment. Alternatively, it can extend the entire length of the donor wafer from east to west. In fact, the wafer can be regarded as a scribe line projection area. In most cases, these projection areas will contain multiple dies of images or fields. In most cases, the width of the scribe line for further cutting the wafer into individual dies may exceed 20 microns. The wafer-to-wafer misalignment distance is approximately 1 micron. Therefore, extending the pattern to the scribing groove can make full use of the pattern within the range of the bare wafer without affecting the cutting of the scribing groove as much as possible. Wn and Wp can be set to the minimum width of the corresponding transistor plus its isolation width in the selected process node. Wafer 3000 also has a strip of alignment marks 3020 on the same layer as the donor wafer as rows n 3004 and p 3006. Therefore, wafer 3000 may be reused later in order to align other image rendering and processing with rows n 3004 and n 3006 described above.

As mentioned above, the acceptor wafer 3000 will be placed on top of the master wafer 3100 for layer dicing. The current technological development can achieve perfect corner alignment of the bonding step, but it is very difficult to achieve a perfect position alignment of more than 1 tooth m.

People with ordinary skills will think that the four directions of east, west, north and south are only for illustrative purposes, and have nothing to do with the real geographical direction; and will think that the north-south direction can be changed to east-west direction (and vice versa) just by rotating the wafer 90°; The "n" type transistor row 3004 and the "p" type transistor row 3006 can also run in the north-south direction, depending on the settings selected and the rest of the fabrication process adjusted accordingly. The skilled person may consider choosing different configurations for the "n" transistor row 3004 and the "p" transistor row in different setting options. For example, the "n" type transistor row 3004 and the "p" type transistor row 3006 may each include a single row of parallel transistors, multiple rows of parallel transistors, and multiple sets of transistors of different specifications, directions, and types (single Only transistors or combined transistors are acceptable), and different transistor sizes or numbers can be selected for the "n" type transistor row 3004 and the "p" type transistor row 3006. Accordingly, the scope of the present invention is limited by the appended claims.

FIG. 31 shows a cut-out layer 3000L of a master wafer 3100 (with alignment marks 3120 ) and a donor wafer 3000 (with alignment marks 3020 ). The east-west misalignment is DX 3124, and the north-south misalignment is DY 3122. In order to simplify the description below, it can be assumed that the alignment marks 3120 and 3020 have been set. In this way, no matter whether the alignment marks 3020 are perfectly aligned (within the tolerance range), or the alignment marks are aligned in an approximate manner South of the alignment mark 3120, the alignment mark of the cut-out layer 3020 will always be located north of the alignment line of the substrate 3120. In addition, these alignment marks can only be set at certain positions on each wafer, and can be set in each step field, in each bare wafer, in each repeated pattern W, or in other positions according to different settings.

In building the monolithic 3D ICs described herein, the goal is to connect structures on layer 3000L to structures on the master wafer 3100 below and on layers 808 with the same density and precision as the interconnects at each layer in 808. The alignment accuracy required in this process is on the order of tens of nanometers or more.

The method used in the east-west direction can be the same as that described in FIGS. 21 to 29 . Whether or not the misalignment line DX 3124 is the same, the prefabricated structures on the donor wafer 3000 are the same. Therefore, as in the previous steps, the alignment mark 3120 below can be used to align the prefabricated structure, and the "n" type transistor row 3004 and the "p" type transistor row 3006 can be formed through etching and separate processing, without considering DX. As the figure changes, the situation in the north-south direction is different. However, the fact that the pattern repeats every distance W 3008 shows an advantage to the intended structure of repeating the pattern in the north-south direction of alternating rows shown in FIG. 30 . Therefore, since the pattern in the north-south direction can keep repeating every segment W, the uncertainty in the effective alignment can be reduced to W 3008.

Therefore, the method shown in Figure 32 can be used to calculate the uncertainty of the effective alignment to determine the number of W needed for DY 3122 - the complete pattern of "n" row 3004 and "p" row 3006 combinations, and calculate the residual Rdy 3202 (The remainder of DY modulus W, 0<=Rdy<W). Therefore, to accurately align with the nearest n 3004 and p 3006 in the north-south direction, it must be aligned with the offset alignment mark 3120 of the Rdy 3202 below. Therefore, alignment should be performed according to the misalignment line between the acceptor wafer alignment mark 3120 and the donor wafer alignment mark 3020 , and considering the repeat distance W 3008 , the resultant vector required for the offset Rdy 3202 is calculated. Alignment marks 3120 covered by wafer 3000L during the alignment process can be seen using infrared lamps and optical components and can be used for segmenter or lithography tool alignment systems.

Alternatively, multiple alignment marks on the donor wafer may be used as shown in FIG. 69 . Donor wafer alignment marks 3020 can be accurately replicated on each segment W 6920 in the north-south direction at a distance sufficient to completely cover any north-south misalignment M 6922 that may occur between the donor wafer and the acceptor wafer It is appropriate. Therefore, residual Rdy 3202 may be a north-south misalignment between the nearest donor wafer alignment mark 6920C and acceptor wafer alignment mark 3120 . Thus, align with the alignment mark 9620C closest to the donor wafer layer, and not align with the alignment mark 3120 that is offset from the Rdy 3202 below. Therefore, the method of selecting the closest alignment mark 6920C on the donor wafer can be used to align according to the misalignment line between the acceptor wafer alignment mark 3120 and the donor wafer alignment mark 6920 .

The illustration is simplified by the inset in FIG. 69 , the alignment marks may exceed the size of WxW in practice. In this case, in order to prevent the alignment marks 6920 from overlapping each other, an offset technique can be used to adopt appropriate marks to achieve an ideal alignment effect.

Each wafer to be processed through this process has a specific Rdy 3202, which is based on the actual misalignment line DY 3122. However, the masks used to draw various patterns need to be set and fabricated in advance; all wafers (wafers used for the same terminal equipment) must use the same mask, without considering the actual misalignment situation. As shown in FIG. 33A , in order to improve the connection between the structure on the cut-out layer 3000L and the lower main wafer 3100, the lower wafer 3100 is provided with north-south insertion pads 33A04 along the length direction of W 3008 And the necessary extensions for the via setting rules. Lengthwise or widthwise bond pad extensions that meet via-setting rules can include compensation for angular misalignment due to wafer-to-wafer bonding, as well as uncompensated donor wafer bow and warpage. The stepper motor overlap algorithm does not compensate for angular misalignment. The plug strips 33A04 can be part of the substrate 3100 and thus aligned with the alignment marks 3120 . The top-down via 33A02 (becoming part of the top layer 3000L pattern, aligned with the underlying alignment mark 3120 with Rdy offset) will connect together with the bond pad 33A04.

Alternatively, splicing strips 33B04 with a length of at least W in the north-south direction can be made on the top layer 3000L, as well as extensions that meet the through-hole setting rules and other compensation parts mentioned above, and pairs with Rdy offsets below the corresponding regions Alignment marks 3120 are aligned so as to be connected to via holes 33B02 and become part of the lower pattern (aligned with lower alignment marks 3120 without offset).

An example of a process flow for creating complementary transistors on a separate cut-out layer for CMOS logic is given below. First, the donor wafer can be pre-processed first in preparation for layer dicing. As shown in Figure 34A, the complementary donor wafer can be specially processed to produce repeating rows 3400 of p and n wells with a combined width of W3008. The length of the repeating row 3400 may be equal to the width of the acceptor die plus the maximum distance between the donor wafer and the receiver wafer misalignment; alternatively, the length of the repeating row may be equal to the total length of the donor wafer. Rotate Fig. 34A by 90° relative to Fig. 30 as indicated by the indicators of the four cardinal directions, so that Fig. 34A is oriented in the same way as in subsequent Figs. 34B to 35G.

Figure 34B is a cross-sectional view of a wafer preprocessed for layer dicing. The P- wafer 3402 processed by successive masking, ion implantation and opening in the width W 3008 has a "buried" N+ layer 3404 and a P+ layer 3406

Next to be performed are masking, ion implantation and annealing of P-like crystal growth 3408 and N-region 3410 in FIG. 34C.

Next, as shown in FIG. 34D , shallow trenches P+ 3412 and N+ 3414 are formed through a mask, shallow trench ion implantation and RTA opening.

Figure 34E shows a wafer drawing preprocessed by implantation of atomic species (eg, H+) for layer dicing, forming a SmartCut "cut plane" 3416 in the bottom region of the deeper N+ and P+ regions. A thin oxide layer 3418 may be deposited or grown to promote adhesion of the oxide to layer 808 . Oxide layer 3418 can be deposited or grown before H+ implantation, including P+ 3412 and N+ 3414 regions with different thicknesses, making the termination of H+ implantation range more uniform, promoting the improvement of implantation level and producing continuous SmartCut cutting plane 3416. The depth of the H+ implant can be adjusted if necessary in other ways, including setting different implant depths for the P+ 3412 and N+ 3414 regions.

As shown in FIG. 20, the layer dicing process can now be performed to transfer the prefabricated strap multi-well monocrystalline silicon wafer on top of 808 shown in FIG. 35A. Cutting surfaces can now be smoothed by both CMP and chemical grinding, or not.

The above p & n well ribbon donor wafer pretreatment process can also be changed to pre-well isolation by means of shallow trench etching, dielectric filling and CMP before layer dicing.

35A to 35G are step-by-step side views of low temperature formed planar CMOS transistors on a complementary donor wafer (shown in FIG. 34). Figure 35A shows the layers transferred to the top of the wafer or layer 808 after smart dicing 3502; where N+ 3404 and P+ 3406 are uppermost, as indicated by cardinal direction 3500, running east-west (i.e., perpendicular to plane), and the repeat width is north-south.

Next, as shown in FIG. 35B , the substrate P+ 35B06 and N+ 35B08 sources and 808 metal layer 35B04 inspection openings and the transistor isolation region 35B02 can be masked and etched. This layer and all subsequent masking layers will be aligned with the layers shown in FIGS. 30-32 and FIG. 35B , where layer alignment mark 3020 is aligned with alignment mark 3120 of substrate layer 808 by offset Rdy.

By using an additional masking layer, isolation region 35C02 is etched sufficiently all the way to the top of prefabricated wafer or layer 808 to completely isolate the transistor or groups of transistors shown in FIG. 35C. Next, a low temperature oxide layer 35C04 is deposited and polished by chemical-mechanical polishing. Then, a thin grind stop layer 35C06, such as low temperature silicon nitride, is deposited, resulting in the structure shown in Figure 35C.

As shown in FIG. 35D, n-trench source 35D02, drain 35D04 and self-aligned gate 35D06 are formed by masking and etching a thin grind stop layer 35C06 and sloped N+ etch layer. Repeating the above steps on the P+ layer can form p-trench source 35D08, drain 35D10 and self-aligned gate 35D12, creating complementary components and forming a complementary metal oxide semiconductor (CMOS) tilt (35° to 90°, shown in the figure For 45°) etching can be followed by wet chemical or plasma etching techniques. This etching operation forms N+ source and drain angle extensions 35D12 and P+ source and drain angle extensions 35D14.

Figure 35E shows the structure of the low temperature gate dielectric 35E02 after deposition and densification, or the structure of the silicon surface (serving as gate oxide for n & p MOSFETs) after low temperature microwave plasma oxidation, followed by the gate material Deposition of 35E04 (such as aluminum or tungsten). In addition, the following methods can also be used to form the high-k metal gate structure. High-k dielectric 35E02 will be deposited after an atomically smooth surface using industry standard HF/SC1/SC2 cleans. The semiconductor industry has chosen hafnium dielectric as the main material to replace SiO2 and silicon oxynitride. The hafnium dielectric family includes hafnium dioxide and hafnium silicate/hafnium silicon oxynitride. The dielectric constant of hafnium dioxide (HfO2) is twice that of hafnium silicate/hafnium oxynitride silicon (HfSiO/HfSiON k~15). The choice of metal material plays a critical role in the proper functioning of the component. The work function of the metal that replaces N+ polysilicon as the gate electrode should reach about 4.2eV so that the device can operate normally at the correct threshold voltage. Alternatively, the metal that replaces the P+ polysilicon as the gate electrode should have a work function of about 5.2eV for the device to function properly. For example, the TiAl and TiAlN metal series can be used to tune the work function of the metal from 4.2eV to 5.2eV. The gate oxide and gate metal can be different in n- and p-trench devices, and one type of gate oxide and gate metal can be selectively removed and replaced by the other.

FIG. 35F shows the structure of metal gate 35E04 after chemical-mechanical polishing using nitride polishing stop layer 35C06. Finally, as shown in Figure 35G, a thick oxide layer 35G02 is deposited and the contact openings are masked and etched, ready for the transistors to be connected together. FIG. 35F also shows layer cut silicon via 35G04. The TSVs will be masked and etched to interconnect the upper transistor wiring and the bottom 808 interconnection wiring 35B04. This process forms the single-crystal top-layer CMOS transistors and interconnects metal and high-temperature components. These transistors are connected to the underlying multi-metal semiconductor components without exposing the underlying components. These transistors can be used as antifuse programming transistors on layer 807 or can be used for other functions such as logic or logic in 3D integrated circuits electrically coupled to the metal layer or layer 808 of the prefabricated wafer. Memory. Another advantage of this process is that the implantation of SmartCut H+ or other atomic species is completed before the gate of the MOS transistor is formed, avoiding potential damage to the gate function.

Those of ordinary skill will recognize that, for clarity, in explaining the method of simultaneously fabricating P-groove and N-groove transistors, the conduction trenches of transistors fabricated in accordance with FIGS. 34A to 35G are oriented north-south, And their grid electrodes are in the east-west direction. In fact other orientations and configurations are also possible. Those skilled in the art can further consider that the transistor can be rotated 90° about the gate electrode in the north-south direction. For example, those skilled in the art can easily understand that transistors aligned in the east-west direction can be insulated from each other by using the low-temperature oxide layer 35C04, or choose to share source and drain regions and contacts according to different settings. Those skilled in the art will also appreciate that row 3004 of "n" type transistors may include multiple N-channel transistors aligned in a north-south direction and row 3006 of "p" type transistors may include multiple P-channel transistors aligned in a north-south direction. The trench transistors, one by one, form sub-rows of back-to-back P-trough and N-trough transistors with the same effective logic layout. In a logical layout, sub-rows of the same type share power and connection lines. Many other setting options can also be taken within the scope of the present invention, which is instructive to those skilled in the art. Accordingly, the invention is limited only by the appended claims.

Alternatively, complete CMOS devices can be built using simple layer-cutting of wafer-sized doped layers. The following will take n-RCAT and p-RCAT as examples to describe the process flow, but this process is not applicable to the above-mentioned components using the transfer doping layer construction of the wafer size.

As shown in Figures 95A to 95I, n-RCAT and p-RCAT can be constructed using simple layer-cutting of wafer-sized doped layers. Its process flow is also suitable for the production of 3D ICs.

As shown in Figure 95A, a P-substrate donor wafer 9500 may contain four wafer-sized layers, which are N+ doped layer 9503, P-doped layer 9504, P+ doped layer 9506, and N-doped layer 9508. The dopant concentration of the P-doped layer 9504 may be the same as that of the P-substrate 9500, or it may be different. Four doped layers 9503, 9504, 9506 and 9508 can be formed by ion implantation and thermal annealing. In addition, doped silicon layers can be deposited by sequential morphological growth or stacked layers can be formed using morphological growth, ion implantation, and high thermal annealing simultaneously. P-layer 9504 and N-layer 9508 can also be graded doped to solve performance problems of transistors, such as short pass effect. A mask oxide layer 9501 can be grown or deposited prior to implantation to ensure that the silicon is free from contamination during the implantation process and to provide an oxide layer for later wafer-to-wafer bonding. These steps can be performed at temperatures in excess of 400°C since metal wiring has not yet been moved to the processed substrate.

As shown in Figure 95B, the top layer of the donor wafer 9500 can be used to bond the oxide wafer to the deposited layer of the oxide layer 9502, either through high thermal oxidation of the N- layer 9508, or secondary oxidation of the implanted mask oxide layer 9501 An oxide layer 9502 is formed. Slicing boundary planes 9599 (dotted lines in the figure) can be formed in the donor wafer 9500 or the N+ layer 9503 (as shown) by hydrogen ion implantation 9507 or other methods described above. As mentioned above, both the donor wafer 9500 and the acceptor wafer 9510 can be used as bonding between the wafers, and then the two are bonded together at a low temperature (not exceeding 400° C.). The portion of the N+ layer 9503 above the layer cut interface plane 9599 and the P- donor wafer substrate 9500 can be removed by dicing or grinding or the processes described above. The method of forming a layer cutting boundary plane by ion implantation of atomic species, such as hydrogen implantation, followed by cutting or grinding can be called "ion cutting". The meaning of the acceptor wafer is similar to the wafer 808 mentioned above, please refer to FIG. 8 for details.

As shown in FIG. 95C , the remaining N+ layer 9503 , P-doped layer 9504 , P+ doped layer 9506 , N-doped layer 9508 and oxide layer 9502 have been layered onto the acceptor wafer 9510 . The uppermost layer of the N+ doped layer 9503' can be polished smooth and flat by chemical or mechanical means. Multiple transistors have now been formed using a low temperature (below 400°C) process and aligned with the acceptor wafer 9510 alignment marks (not shown). For ease of illustration, subsequent drawings will not show the oxide layer (eg, 9502) used to promote wafer-to-wafer bonding.

As shown in Figure 95D, the transistor isolation region can be formed by photolithography first, and then through plasma/reactive ion etching, at least reaching the top oxide layer of the acceptor substrate 9510 to remove the N+ doped layer part 9503, P-doped layer 9504, P+ doped layer 9506 and N-doped layer 9508. Next, a low temperature gap-fill oxide layer may be deposited and chemical-mechanical polished to remain in the transistor isolation region 9520 . In this way, the N+ doped region 9513, the P-doped region 9514, the P+ doped region 9516 and the N-doped region 9518 of the RCAT transistor have been further formed.

As shown in FIG. 95E, the p-RCAT portion of the wafer with N+ doped regions 9513 and P- doped regions 9514 can be photolithographically removed by plasma/reactive ion etching or selective wet etching. . Next, the p-RCAT hidden trench 9542 can be masked and etched. Wet chemical or plasma/reactive ion etching techniques can be used to smooth the surface and edges of hidden trenches to reduce the effect of strong electric fields. These process steps form the P+ source and drain regions 9526 and the N- transistor trench region 9528 .

As shown in Figure 95F, a gate oxide layer 9511 may be formed and a gate metal material 9554 may be deposited. The gate oxide layer 9511 can choose an atomic layer deposition (ALD) gate dielectric that matches the work function of the specific gate metal 9554, which conforms to the industry standard of the high-k metal gate process mentioned above, and is positioned as p-groove RCAT use. In addition, the gate oxide region 9511 can be formed by low temperature oxide deposition or low temperature microwave plasma oxidation on the silicon surface. Next gate material such as platinum or aluminum may be deposited. Then, the gate material 9554 can be polished by a chemical-mechanical method, and the p-RCAT gate electrode 9554' can be processed by masking and etching.

As shown in Figure 95G, a low temperature oxide layer 9550 can be deposited and planarized, covering the formed p-RCAT. This allows processing to begin and form n-RCAT.

As shown in Figure 95H, the n-RCAT hidden trench 9544 can be masked and etched. Wet chemical or plasma/reactive ion etching techniques can be used to smooth the surface and edges of hidden trenches to reduce the effect of strong electric fields. These process steps form the N+ source and drain regions 9533 and the P- transistor trench region 9534 .

As shown in FIG. 95I, a gate oxide layer 9512 may be formed and a gate metal material 9556 may be deposited. The gate oxide layer 9512 can choose an atomic layer deposition (ALD) gate dielectric that matches the work function of the specific gate metal 9556, which conforms to the industry standard of the high-k metal gate process scheme mentioned above, and is positioned as n-groove RCAT. In addition, the gate oxide region 9512 can be formed by low temperature oxide deposition or low temperature microwave plasma oxidation on the silicon surface. Next gate material such as tungsten or aluminum may be deposited. Next, the gate material 9556 can be polished by a chemical-mechanical method, and the gate electrode 9556' can be processed by masking and etching.

As shown in Figure 95J, a low temperature oxide layer 9552 can cover the entire structure, which can be planarized by chemical-mechanical polishing. Contacts and metal wiring can be formed by photolithography and plasma/reactive ion etching. n-RCAT N+ source and drain regions 9533, P- transistor trench region 9534, gate dielectric 9512 and gate electrode 9556' are shown. The p-RCAT P+ source and drain regions 9526, N- transistor trench region 9528, gate dielectric 9511 and gate electrode 9554' are shown. Transistor isolation region 9520, oxide layer 9552, n-RCAT source contact 9562, gate contact 9564, and drain contact 9566 are shown. The p-RCAT source contact 9572, gate contact 9574 and drain contact 9576 are shown. The n-RCAT source contact 9562 and drain contact 9566 are electrically coupled to the respective N+ region 9533 . n-RCAT gate contact 9564 is electrically coupled to gate electrode 9556&apos;. The p-RCAT source contact 9572 and drain contact 9576 are electrically coupled to respective N+ regions 9526 . n-RCAT gate contact 9574 is electrically coupled to gate electrode 9554&apos;. Junctions (not shown) of P+ doped regions 9516 and N- doped regions 9518 may be used to allow noise suppression biasing and back gate/substrate biasing.

Next, wiring metallization can be formed using conventional methods. Through-layer vias 9560 (not shown) may be formed to electrically couple the metallized regions of the complementary RCAT to the acceptor substrate 9510 at acceptor wafer metal connection pads 9580 (not shown). This process enables single crystal silicon n-RCAT and p-RCAT to be formed by simple layer dicing of prefabricated wafer-sized doped layers. They can be connected with the underlying multi-metal layer semiconductor components to avoid exposing the underlying components to high temperature.

Those of ordinary skill may consider the examples mentioned in FIGS. 95A-95J to be representative examples only and not scaled down. A skilled person can consider more variations. For example, n-RCAT can be processed before p-RCAT or various etched hard films can be applied. A skilled person might further consider making a slight change to the process flow to generate components other than complementary RCATs, e.g. bipolar junction complementary transistors, or complementary transistors with raised source and drain extensions, or junctionless Type complementary transistor, or V-groove complementary transistor. A reading of this specification will allow the skilled person to recall how to make modifications elsewhere within the scope of the invention. Accordingly, the invention is limited only by the appended claims.

Another way to build "n" and "p" transistors on the same layer is to partially implement the first steps of transistor formation (with conventional CMOS processing) on the donor wafer, including the "dummy gate ", this process is suitable for gate-last transistors. In this case of the present invention, the layer cutting operation of the single crystal silicon can be performed after the completion of the dummy gate and before the formation of the replacement gate. There is no temperature limit for the operation before layer cutting, and the operation during and after layer cutting should be carried out at low temperature, usually lower than 400°C. Dummy gates and replacement gates can be made of various materials such as silicon and silicon dioxide, or metals and low-k materials such as TiAlN and HfO2. Another example is the high-k metal gate (HKMG) CMOS transistor, which has 45nm, 32nm, 22nm and other alternative CMOS Intel and Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC) have confirmed " Advantages of gate-last" approach to building high-performance HKMG CMOS transistors (C, Auth et al; VLSI2008; Pages: 128-129 and C.H.Jan et al; 2009 IEDM; Page: 647).

As shown in FIG. 70A , the bulk silicon donor wafer 7000 is advanced processed by HKMG "gate last" until CMP exposure of the polysilicon dummy gate. Figure 70A shows a cross-section of a bulk silicon donor wafer 7000, gate sidewalls 7002 between transistors, polysilicon 7004 and gate oxide 7005 for n-type and p-type CMOS dummy gates, their corresponding source and Drains 7006 (NMOS) and 7007 (PMOS) and interlayer dielectric (ILD) 7008 . These structures in Figure 70A illustrate the completion of the first step in the transistor forming process. As shown in FIG. 70B , at this stage, either layer 7008 has just been CMPed to expose the polysilicon dummy gate, or the oxide layer 7008 is planarized without exposing the dummy gate, and implanted atomic species 7010 (eg, H+) can be A dicing plane 7012 is prepared for the bulk silicon of the donor substrate suitable for layer dicing.

As shown in Figure 70C, the donor wafer 7000 and the carrier substrate 7014 can now be temporarily bonded using a low temperature process (which facilitates low temperature release). The carrier substrate 7014 can be a glass substrate, so that the optical alignment of the acceptor wafer can reach the most advanced level. The temporary bonding between the carrier substrate 7014 and the donor wafer 7000 at the interface 7016 can use a polymeric material, such as polyimide DuPont HD3007. This material can be released in a subsequent step by means of laser ablation, UV irradiation or thermal decomposition. Alternatively, temporary bonding can be performed using unipolar electrostatic or bipolar electrostatic techniques, such as the Apache tool from Beam Services Inc.

As shown in FIG. 70D , the donor wafer 7000 can then be diced on a dicing plane and thinned by chemical-mechanical polishing (CMP). As such, the transistor gate sidewalls 7002 may be exposed on the donor wafer surface 7018 . Alternatively, the CMP operation can be continued down to the bottom of the joint, resulting in a completely depleted SOI layer.

As shown in FIG. 70E , the thin single crystal donor wafer surface 7018 can be used for layer dicing by low temperature oxidation or precipitation of an oxide layer 7020, as well as plasma or other surface treatments to clean the wafer from oxide to oxide. The bond between them is ready to oxidize the surface 7022. Similar surface treatments can also be used on 808 acceptor wafers when preparing the surface for oxide-to-oxide bonding.

As shown in FIG. 70E , low temperature (eg, below 400° C.) layer dicing can be performed to transfer the thinned HKMG silicon layer 7001 (with carrier substrate 7014 ) pre-processed in the first step of transistor formation to On the acceptor wafer 808 (top metallization), metal straps 7024 are included, which become bond pads for the connection lines between the circuit formed on the cut-out layer and the circuit-layer 808 below.

As shown in FIG. 70F , the carrier substrate 7014 may be released by a low-temperature process (such as laser ablation) next.

The bonded acceptor wafer 808 and HKMG transistor silicon layer 7001 are now ready for advanced "gate last" transistor formation. As shown in FIG. 70G, the interlayer dielectric 7008 may be chemical-mechanical polished to expose the top layer of the polysilicon dummy gate. Next, the polysilicon dummy gate can be removed by etching, and the high-k gate dielectric 7026 and the PMOS specific work function metal gate 7028 can be deposited. The PMOS work function metal gate can be removed from the NMOS transistor and the NMOS specific work function metal gate 7030 can be deposited. Aluminum 7032 is filled on the NMOS and PMOS gates, and the metal is chemical-mechanical polished.

As shown in Figure 70H, a dielectric layer 7032 may be deposited, and conventional gate 7034 and source/drain 7036 contact formation and metallization operations can now be performed to connect the transistors on the single crystal layer and Connect to the top metallization strap 7024 of the acceptor wafer 808 through vias 7040 . In this way, the donor wafer and the acceptor wafer can be connected through the cut-out layer. A top metal layer can be formed to become the acceptor wafer bonding strip. The above-mentioned process flow is repeated in order to position another pre-processed single crystal two-step formed transistor thin layer. Other types of gates such as doped polysilicon on thermal oxide, doped polysilicon on oxynitride, or other metal gate configurations can also be constructed using the above process. These gates can be used as "dummy gates" to perform layer dicing of thin single crystal layers, replacing gate electrodes and gate maintenance, and then perform low-temperature wiring processing.

Alternatively, a silicon wafer can be used as the carrier substrate 7014, aligned using infrared and optical components. 82A to 82G can be used to illustrate the use of a carrier wafer. FIG. 82A illustrates the first steps in preparing transistors with dummy gates 8202 on a first donor wafer 8206. The first step completes the first stage of transistor shaping.

FIG. 82B illustrates a method of forming dicing lines 8208 by implanting atomic particles 8216 (eg, H+).

Figure 82C illustrates a method of permanently bonding a first donor wafer 8206 to a second donor wafer 8226. As mentioned earlier, the permanent bond may be an oxide-to-oxide wafer bond.

Figure 82D shows a second donor wafer 8226 (which becomes the carrier wafer after the first wafer is diced), leaving a thin layer 8206 with embedded dummy gate transistors 8202.

FIG. 82E illustrates the formation of a second dicing line 8218 by implanting an atomic type 8246 (eg, H+) into a second donor wafer 8226 .

Figure 82F illustrates the second step of layer cutting. Through this step, the prepared dummy gate transistor 8202 to be permanently bonded is brought into the housing 808 . For the convenience of explanation, the steps related to the preparation of the surface layer for each bonding link are omitted here.

Figure 82G shows housing 808 with dummy gate transistor 8202 on top. At this point the second donor wafer has been diced and the layer on top of the dummy gate transistors has been removed. The process can now begin to replace the dummy gates with the final gates, form the metal interconnect layer, and continue the 3D fabrication process.

There is another interesting approach that can be used when taking the carrier wafer flow. In this process, we can use both sides of the cut-out layer to build NMOS on one side and PMOS on the other side. Properly timing the replacement gate during this process will ensure good performance of the transistors aligned with each other. This process can also build compressed 3D module library chip.

As shown in Figure 83A, an SOI (silicon on insulator) donor wafer 8300 can be processed using advanced techniques such as the HKMG "gate-last" process, using adjusted thermal cycling to compensate for later thermal processing until polysilicon dummy gates appear CMP until bare. Alternatively, the donor wafer 8300 can be initially used as a bulk silicon wafer, and a buried oxide layer is formed by oxygen ion implantation and high temperature annealing, such as the SIMOX process (ie isolation by oxygen ion implantation). FIG. 83A shows a cross-section of an SOI donor wafer substrate 8300, a buried oxide layer (i.e., BOX) 8301, a thin oxide layer 8302 of the SOI wafer, gate sidewalls 8303 between transistors, and n-type CMOS dummy gates. Pole polysilicon 8304 and gate oxide layer 8305, and NMOS related source and drain 8306, NMOS transistor trench 8307 and NMOS interlayer dielectric (ILD) 8308. Alternatively, PMOS components or complete CMOS components can also be built at this stage. This step completes the first stage of transistor shaping.

As shown in FIG. 83B, at this stage, either layer 8308 has just been CMPed to expose polysilicon dummy gates, or oxide layer 8308 is planarized without exposing dummy gates, and implanted atomic species 8310 (eg, H+) can be A dicing plane 8312 is prepared for the bulk silicon of the donor substrate suitable for layer dicing.

The SOI donor wafer 8300 can now be permanently bonded to the carrier wafer 8320 as shown in FIG. 83C . The carrier wafer 8320 has an oxide layer 8316 that can be used for oxide-oxide bonding to the donor wafer surface 8314 .

As shown in FIG. 83D , the donor wafer 8300 can then be diced on the dicing plane 8312 and thinned by chemical-mechanical polishing (CMP). The surface 8322 can be used for transistor molding.

The donor wafer layer 8300 on the surface 8322 can be processed using advanced "gate last" processing methods to form PMOS transistors with dummy gates. Figure 83A shows the cross-section of the buried oxide layer (BOX) 8301 after the PMOS component is formed, the thin silicon layer 8300 of the SOI substrate, the gate sidewall 8333 between the transistors, the polysilicon 8334 of the p-type CMOS dummy gate and Gate oxide 8335, and PMOS related source and drain 8336, PMOS transistor, body trench 8337 and PMOS interlayer dielectric (ILD) 8338. Since the common substrate 8300 has the same alignment mark, the PMOS transistor and the NMOS transistor can be precisely aligned using advanced technology. In this step, or just CMP layer 8338, this process can expose the PMOS polysilicon dummy gate or planarize the oxide layer 8338 without exposing the dummy gate. The wafer can now be placed in a high temperature annealing furnace to turn on the NMOS and PMOS transistors.

As shown in FIG. 83F , an atomic species 8340 (eg, H+) can then be implanted to prepare the dicing plane 8321 for the bulk silicon of the carrier wafer substrate 8320 suitable for layer dicing.

The PMOS transistors are now ready for the "gate last" transistor forming step using state-of-the-art processes. As shown in Figure 83G, the interlayer dielectric 8338 may be chemical-mechanical polished to expose the top layer of the polysilicon dummy gate. Next, the polysilicon dummy gate can be removed by etching, and the PMOS high-k gate dielectric 8340 and the PMOS specific work function metal gate 8341 can be deposited. Aluminum 8342 is filled on the PMOS gate, and the metal is chemical-mechanical polished. A dielectric layer 8339 can be deposited and conventional gate 8343 and source/drain 8344 contacts can be formed and metallized. As shown in FIG. 83G, the PMOS layer to NMOS layer via hole 8347 can be partially formed and metallized, and an oxide layer 8348 can be deposited to prepare for bonding.

As shown in FIG. 83H , the carrier wafer and the double-sided n/p layer can then be aligned and permanently bonded to the case acceptor wafer 808 with the associated bonding strap metal 8350 .

As shown in FIG. 83I , next, the carrier wafer 8320 can be diced on the dicing plane 8321 , and then the oxide layer 8316 can be thinned by chemical-mechanical polishing (CMP).

The NMOS transistors are now ready for the "gate last" transistor forming step using state-of-the-art processes. As shown in Figure 83J, the NMOS interlayer dielectric 8308 can be chemical-mechanical polished to expose the top layer of the NMOS polysilicon dummy gate. Next, the polysilicon dummy gate can be removed by etching, and the NMOS high-k gate dielectric 8360 and the NMOS specific work function metal gate 8361 can be deposited. Aluminum 8362 is filled on the NMOS gate, and the metal is chemical-mechanical polished. A dielectric layer 8369 can be deposited and conventional gate 8363 and source/drain 8364 contacts can be formed and metallized. Vias 8367 connecting 8347 between the NMOS layer and the PMOS layer can be formed and metallized.

As shown in Figure 83K, a dielectric layer 8370 may be deposited. Layer-to-layer vias 8372 may then be aligned, masked, etched, and metalized to electrically connect them to the acceptor wafer 808 and metal bond bars 8350 . As shown in FIG. 83K, the topmost metal layer may be formed to become the acceptor wafer bonding strip. The above process flow is repeated to position another pre-processed single crystal transistor thin layer. Those of ordinary skill may consider the examples mentioned in FIGS. 83A-83K to be representative examples only and not to scale. A skilled person can consider more variations. For example, the transistors on each side of BOX8301 can completely use CMOS; or use CMOS on one side and other n-type MOSFET transistors on the other side; or use other combinations and other types of semiconductor components. A reading of this specification will allow the skilled person to recall how to make modifications elsewhere within the scope of the invention. Accordingly, the invention is limited only by the appended claims.

Figure 83L is a repeating wafer 83L00 (which is the base wafer forming the gate array) and two NMOS transistors 83L04 (with a common diffusion layer 83L05, "face down") and two PMOS transistors 83L02 (with a common diffusion layer) In the plan view, the NMOS transistor gate covers the PMOS transistor gate 83L10, and the covered gates are connected to each other through the through hole 83L12. The VDD supply line 83L06 becomes part of the front-down common structure during operation, and is connected to the layer above through the via 83L20. Diffusion connection 83L08 will use face down generic structure 83L17 and bring it up through vias 83L14, 83L16 and 83L18.

Figure 83L1 shows a general-purpose chip 83L00 customized according to custom NMOS contacts 83L22, 83L24 and custom metal 83L26, which can form a double inverter. The Vss power line 83L25 can be run on top of an NMOS transistor.

FIG. 83L2 is a drawing of a general-purpose chip 83L00 for customizing NOR functions; FIG. 83L3 is a drawing of a general-purpose chip 83L00 for customizing NAND functions; FIG. 83L3 is a drawing of a general-purpose chip 83L00 for customizing multiplexer functions. Therefore, 83L00 can be widely used to customize various desired logic functions. Thus, any logic function can be customized using custom contact vias and metal layers using the generic gate array of chip 83L00.

For another method, please refer to Figure 70 and its description. Figure 70B-1 illustrates this method in detail. First, through the mask and etch the protective implant stop layer 7050 of dense material (such as tantalum of 5000 angstroms), the implanted atomic species 7010 (such as H+) can be masked from the sensitive gate region 7003, and bonded with the photoresist of 5000 angstroms stand up. This creates segmented cut planes 7012 in the bulk silicon of the donor wafer and the silicon wafer. In addition, grinding can be used to provide a smooth bonding surface suitable for layer cutting.

Another approach that can be used is to use an SOI donor wafer to isolate the transistors in the vertical direction. For example, pn junctions can be formed between vertically stacked transistors, and these junctions can be biased. In addition, oxygen ions can be implanted between vertically stacked transistors and annealed to form a buried oxide layer. Likewise, SRI technology can be used on first-time dummy transistors, where the SiGe layer is selectively etched and refilled with oxide, creating islands of silicon-on-insulator.

Please refer to FIG. 70 for another example of the above-mentioned process flow. FIGS. 81A to 81F describe the case of attraction, which can provide a face-down CMOS planar transistor layer on the top of the pre-processed housing substrate. As can be seen below and in Figures 70A and 70B, dummy gates can be used to fabricate CMOS planar transistors and create cut planes 7012 in the donor wafer. According to the foregoing description and the related content of FIG. 81A, the dummy gate can be removed at this time.

The contact and metallization steps can be performed as in Figure 81B to connect the transistors to each other when they are face down.

As shown in Figure 81C, the front side 8102 of the donor wafer 8100 can be bonded using oxide deposition 8104, plasma or other surface treatment to prepare for wafer-to-wafer direct and oxide-to-oxide bonding Good oxidation surface 8106.

Similar surface treatments can also be used on 808 acceptor wafers when preparing the surface for oxide-to-oxide bonding. As shown in FIG. 81D , the low temperature (not exceeding 400° C.) layer dicing process can now be performed to transfer the prepared donor wafer 8100 (with top surface 8106 ) onto the acceptor wafer 808 . The acceptor wafer 808 may be pre-processed with transistor lines and metal wiring. The acceptor wafer 808 may be metallized on the top, including metal straps 8124 , which become bond pads for connections between circuits formed on the cut-out layer and circuit layers in the housing 808 below. For ease of illustration, an additional STI (Shallow Trench Insulation) isolation region 8130 (without via 7040 ) is added in FIGS. 81D to 81F .

As shown in FIG. 81E , the donor wafer 8100 can then be diced on the dicing plane 7012 and thinned by chemical-mechanical polishing (CMP). In this way, the transistor gate sidewalls 7002 and 8130 are exposed. Alternatively, the CMP operation can be continued down to the bottom of the joint, resulting in a completely depleted SOI layer.

A low temperature oxide or low-k dielectric 8136 may be deposited and planarized as shown in FIG. 81F. Vias 8128 to housing 808, acceptor wafer bonding strips 8124 and contacts 8140 and vias 7040 are etched, metallized and connected with wires 8150 to implement donor wafer transistor and acceptor die Electrical connections between circles. As shown in Figures 32 and 33A, the length of the splice strip 8124 should be at least as long as the repeat width W plus the width of the edge that satisfies the proper via placement rules. Bond pad strip extensions that meet via set rules can include compensation for angular misalignment due to wafer-to-wafer bonding, as well as uncompensated donor wafer bow and warpage. The stepper motor overlap algorithm does not compensate for angular misalignment.

The face down process has some advantages. For example, double gate transistors can be turned on, reverse biased transistors or floating bodies into memory applications. For another example, the back gate of the double gate transistor can be constructed as shown in FIG. 81E-1. A low temperature gate oxide 8160 with gate material 8162 may be grown or deposited and processed using photolithography and timing processes as previously described.

Build the metal wiring diagram as shown in Figure 81F-1.

As shown in Figure 81F-2, a fully depleted SOI transistor with connectors 8170 and 8171 can also be constructed according to the requirements of this process and thinned by CMP as shown in Figure 81E.

Figures 85A to 85E show another example of the above double gate process flow, which can provide a back gate in a front-side-up process, please refer to Figure 70 for details. As can be seen below and in Figures 70A and 70B, dummy gates can be used to fabricate CMOS planar transistors and create cut planes 7012 in the donor wafer (bulk or SOI). As can be seen below and in Figure 70C, the donor wafer can be permanently or temporarily attached to the carrier substrate and then diced and thinned to STI 7002 as shown in Figure 70D. Alternatively, the CMP operation can be continued down to the bottom of the joint, resulting in a completely depleted SOI layer.

As shown in FIG. 85A, a second gate oxide layer 8502 may be grown or deposited, and gate material 8504 may be deposited. The gate oxide layer 8502 and the gate material 8504 can be formed using low temperature (not exceeding 400°C) materials and processes, such as the TEL SPA gate oxide and amorphous silicon mentioned above, ALD technology or high-k metal gate stack (HKMG); Higher temperature gate oxide or oxynitride and doped polysilicon can also be used if the carrier substrate is permanently bonded and the dopant movement of existing planar transistors has been described.

As shown in Figure 85B, the gate stack layer 8506 can be outlined, a dielectric 8508 can be deposited and planarized, and then local contacts 8510 and layer-to-layer contacts 8512 and metallization can be formed. Layer 8516.

As shown in FIG. 85C , a thin stack of single crystal donor and carrier substrates, including oxide layer 8520 , can be prepared for layer dicing by the methods described above. A similar surface treatment can also be used on the housing 808 acceptor wafer in preparing the surface for oxide-to-oxide bonding. As shown in FIG. 85C, low temperature (eg, below 400°C) layer dicing can be performed to separate the thinned HKMG silicon layer 7001 and back gate 8506 (with carrier The substrate 7014) is transferred onto the acceptor wafer 808 (top metallization), including metal straps 8124, which become bond pads for the connection lines between the circuits formed on the cut-out layer and the circuit layer 808 below.

As shown in FIG. 85D , the carrier substrate 7014 may then be released on the surface 7016 as previously described.

As shown in Figure 85E, the bonded acceptor wafer 808 and HKMG transistor silicon layer 7001 are now ready for advanced techniques to form the "gate-last" transistors and place the acceptor wafer The shell 808 is connected to the via 7040 through the layer. The top gate is connected to the bottom gate, metal line 8536 and contact 8522 through gate contact 7034 and to the donor wafer layer through layer contact 8512 so that the upper transistor 8550 has a back gate. The upper transistor 8552 is reverse biased by connecting the metal line 8516 to the back bias circuit. Back bias circuitry may be present at the upper transistor level or within housing 808 .

The present invention overcomes the difficulties encountered in forming planar transistors aligned with the underlying layer 808, see FIGS. 71-79 and 30-33 for details. As mentioned above, with reference to FIGS. 70A to 70H , it can be known that a general process can be adopted in the transistor forming process. In one case, the donor wafer 3000 can be pre-processed so that not just one transistor type is built, but two types, by including alternating rows in parallel. The alternating rows are equal to the width of the die plus the maximum length between the misalignment of the donor and acceptor wafers. In addition, as shown in Figure 30, in the first stage of "n" type 3004 and "p" type 3006 transistor formation, alternating rows can also be made as long as the wafer, and Figure 30 also shows the four basic directions The indicator 3040 of Figure 71 to Figure 78 is explained by these indicators. As shown in the enlarged projection diagram 3002, the width of the n-type row 3004 is Wn, the width of the p-type row 3006 is Wp, and the sum of the two, W3008, is equal to the width of the repeated pattern. Rows repeat from east to west, while alternating patterns repeat from north to south across the wafer. Wn and Wp can be set to the minimum width of the corresponding transistor plus its isolation width in the selected process node. Wafer 3000 also has a strip of alignment marks 3020 on the same layer as the donor wafer as rows n 3004 and p 3006 . Therefore, wafer 3000 may be reused later in order to align other image rendering and processing with rows n 3004 and n 3006 described above.

As shown in Figure 71, the width repetition Wp 7106 of the p-type transistor row may include two transistor isolation regions 7110, each with a width of 2F; plus a transistor source 7112, with a width of 2.5F; and a PMOS gate 7113 , width F and a transistor drain 7114, width 2.5F. The total width Wp may be equal to 10F, where F is 2 x λ, the minimum setting rule. The n-type transistor row width repeat Wn 7104 may comprise two transistor isolation regions 7110, each 2F wide; plus a transistor source 7116, 2.5F wide; an NMOS gate 7117, wide F and a transistor Crystal drain 7118, width 2.5F. The total width Wn may be equal to 10F, and the total repeat width W 7108 is equal to 20F.

As previously described and with reference to FIG. 70E , the now thinned donor wafer layer 3000L and first stage transistor forming pre-processed HKMG silicon layer 7001 (with accompanying carrier substrate 7014 ) can be placed as shown in FIG. 31 The top of the acceptor wafer 3100. The current technological development can achieve perfect corner alignment of bonding steps, but it is very difficult to achieve perfect position alignment of more than 1 mm. FIG. 31 shows a cut-out layer 3000L of a recipient wafer 3100 (with corresponding alignment marks 3120 ) and a donor wafer (with alignment marks 3020 ). The east-west misalignment is DX 3124 and the north-south misalignment is DY 3122. These alignment marks 3120 and 3020 can only be set at certain positions on each wafer, and can be set in each step field, each bare wafer or each repeated pattern W. As previously described and with reference to Figures 32, 33A, and 33B, the alignment method, including residual Rdy 3202 and bond pad strips 33A04 and 33B04, can be used to increase the density and dependence of the electrical connection between the transferred donor wafer layer and the acceptor wafer. sex.

Figures 72A to 72F illustrate the low temperature layer dicing flow for a donor wafer layout with gates in parallel to the source and drain shown in Figure 71 .

Figure 72A shows the thin single crystal prefabricated donor layer sliced and bonded to the acceptor wafer after the first stage of transistor formation after layer dicing and the bonded structure described in the section preceding and including Figure 70F Top and cross-sectional views of the wafer after removal from the carrier substrate.

Perform chemical-mechanical polishing on the interlayer dielectric (ILD) 7008 to expose the top of the dummy polysilicon; and etch, metal fill, and smooth the layer-to-layer via 7040 as shown in FIG. 72B .

Longer rows of preformed transistors can be etched to desired lengths or segments by forming isolation regions 7202, as shown in FIG. 72C. Low temperature oxidation can be performed to repair the damaged portion of the transistor edge; the region 7202 can be filled with dielectric and smoothed by chemical-mechanical polishing to isolate the transistor segments.

Alternatively, the regions 7202 of PMOS and NMOS can be selectively opened or filled to improve the overall transistor trench or increase its tensile stress, which is beneficial to improve carrier mobility.

The polysilicon 7004 and oxide 7005 dummy gates can now be etched to provide some gates at the boundaries of the isolation region 7202 and the normal replacement gate deposition of the high-k dielectric 7026, PMOS metal gate 7028 and NMOS metal gate 7030 overlay. In addition, aluminum overfill 7032 is available. As shown in Figure 72D, aluminum 7032 can be chemical-mechanical polished to planarize the surface for gate profiling.

As shown in FIG. 72E, the replacement gate 7215 can be patterned and etched, and a gate contact bonding pad 7218 can be provided.

An interlayer dielectric may be deposited and planarized by chemical-mechanical polishing. As shown in FIG. 72F, common contact forming and metallization steps may be performed to create gate 7220, source 7222, drain 7224, and interlayer via 7240 connection lines.

In another example, the donor wafer 7000 can be pre-processed in the first stage of transistor formation to create n- and p-type dummy wafers, including repeating patterns in both directions. Figures 73, 74 and 75 also show indicators 3040 of the four cardinal directions by which interpretation can be made. As shown in the enlarged projection view 7302 in FIG. 73, the width Wy 7304 coincides with the repeating pattern row. The repeating pattern row is equal to the width of the acceptor die from east to west plus the maximum length between the misalignment line of the donor wafer and the acceptor wafer; or equal to the length of the donor wafer from east to west; repeat pattern across the die The circles are repeated from north to south. Similarly, Wx 7306 is shown consistent with repeating graphic lines. Repeat pattern row equals width of acceptor die from north to south plus maximum length between donor wafer and acceptor wafer misalignment; or equal to length of donor wafer from north to south; repeat pattern across die The circles are repeated from east to west. Wafer 7000 also has a strip of alignment marks 3020 on the same layer as the donor wafer as the Wx 7306 and Wy 7304 conflicting pattern rows. Therefore, alignment marks 3020 may be used later in order to align other image rendering and processing with the above-mentioned rows.

As previously described and with reference to FIG. 70E , the now thinned donor wafer layer 3000L and first stage transistor forming pre-processed HKMG silicon layer 7001 (with accompanying carrier substrate 7014 ) can be placed as shown in FIG. 31 The top of the acceptor wafer 3100. The current technological development can achieve perfect corner alignment of the bonding step, but it is very difficult to achieve a perfect position alignment of more than 1 tooth m. FIG. 31 shows a cut-out layer 3000L of a recipient wafer 3100 (with corresponding alignment marks 3120 ) and a donor wafer (with alignment marks 3020 ). The east-west misalignment is DX 3124, and the north-south misalignment is DY 3122. These alignment marks can only be set at certain positions on each wafer, and can be set in each step field, each bare wafer, or each repeated pattern W.

As shown in Figure 74, the proposed structure consists of a repeating pattern of alternating rows of energy bands in parallel transistors in north-south and east-west directions. The advantage of the proposed structure is that the processing technology of the transistor is similar to the processing technology of the acceptor wafer, thereby greatly reducing the development cost of 3D integrated components. Therefore, the uncertainty in the effective alignment can be reduced to Wy 7304 (north-south direction) and Wx 7306 (east-east direction). Correspondingly, the alignment residual Rdy 3202 (the remainder of the DY modulus Wy, 0<=Rdy<Wy) in the north-south direction can be calculated. For accurate alignment with the nearest Wy, be sure to align north-south with the alignment mark 3120 offset from the Rdy 3202 below. Likewise, the uncertainty in effective alignment in the east-west direction can be reduced to Wx 7306. The alignment residual Rdx 3708 (the remainder of the DX modulus Wx, 0<=Rdx<Wx) in the east-west direction can be calculated using a method similar to Rdy3202. Likewise, for accurate alignment with the nearest Wx, it must be aligned with the alignment mark 3120 offset from the lower Rdx 7308 in the east-west direction.

Each wafer to be processed according to this flow should have at least one specific Rdx 7308 and Rdy 3202, both of which depend on the actual misalignment lines DX 3124 and DY 3122 and Wx and Wy. However, the masks used to draw various graphics need to be set and fabricated in advance; all wafers (wafers used for the same terminal equipment) must use the same mask, regardless of the actual wafer-to-wafer Misalignment condition. As shown in FIG. 75 , in order to ensure that the structures on the donor wafer 7001 are better connected to the donor wafer 808 below, the lower wafer 808 should be provided with rectangular bonding pads 7504 extending along the length Wy 7304 in the north-south direction, plus The extension that satisfies the via design rules; in addition, the bond pad should also extend along the length Wx 7306 in the east-west direction, plus the extension that satisfies the via design rules. Rectangular extensions of bond pads that satisfy via-setting rules can include compensation for angular misalignment due to wafer-to-wafer bonding, as well as uncompensated donor wafer bow and warpage. The stepper motor overlap algorithm does not compensate for angular misalignment. The bond pads 7504 may become part of the acceptor wafer 808 and thus align with its alignment marks 3120 . Vias 7502 are in the descending direction and are part of the donor wafer 7001 pattern. It connects to the bond pad 7504 by offsetting Rdx 7308 and Rdy 3202 respectively from the alignment mark 3120 below.

As shown in FIG. 77, in another example, the rectangular bonding pads 7504 in the acceptor substrate 808 can be replaced with bonding strips 77A04 in the acceptor wafer and vertical bonding strips 77A06 in the acceptor layer. The via hole 77A02 is in the descending direction and is part of the pattern of the donor wafer 7001 . It connects to bond pad 77A06 by offsetting Rdx 7308 and Rdy 3202 respectively from alignment mark 3120 below.

Figure 76 shows repeating patterns from north-south and east-west directions, respectively. This repeating pattern may be a repeating pattern of transistors each having a gate 7622 forming the transistor energy bands along the east-west axis. The repeating pattern in the north-south direction can include transistor energy bands connected in parallel, where each transistor has an active region 7612 or 7614 . A transistor may have its gate 7622 fully defined. Thus, repeating Wx 7306 allows the structure to repeat in the east-west direction. The structure repeats each Wy 7304 in a north-south direction. The width Wv 7602 of the via trench 7618 between layers is 5F, and the width Wn 7604 of the n-type transistor row can include two transistor isolation regions 7610 (width 3F), a common isolation region 7616 (width 1F) and Transistor active area 7614 (width 2.5F). P-type transistor row width Wp 7606 may include two transistor isolation regions 7610 (width 3F), common isolation region 7616 (width 1F), and transistor active region 7612 (width 2.5F). The total width Wy may be equal to 18F, which is the sum of Wv+Wn+Wp, where F is 2×λ, the minimum setting rule. The width of the grid 7622 is F, and the distance between each grid in the east-west direction is 4F. The east-west repeat width Wx 7306 is 5F. Neighboring transistors in the east-west direction can be isolated from each other by biasing the middle gate to an appropriate off state, such as a ground gate for NMOS and a Vdd gate for PMOS.

As previously described and with reference to FIG. 70E , the now thinned donor wafer layer 3000L and first stage transistor forming pre-processed HKMG silicon layer 7001 (with accompanying carrier substrate 7014 ) can be placed as shown in FIG. 31 The top of the acceptor wafer 3100. DX 3124 and DY 3122 misalignment and associated Rdx 7308 and Rdy 3202 can be calculated as previously described. As shown in FIG. 77A , in order to ensure that the structure on the donor wafer 7001 is better connected to the wafer 808 below, the wafer 808 below should be set with bonding pads 77A04 extending along the length Wy 7304 in the north-south direction, and additionally meet the requirements of the pass An extension of the hole setting rule. Bond pad extensions that meet via-setting rules can include compensation for angular misalignment due to wafer-to-wafer bonding, as well as uncompensated donor wafer bow and warpage. The stepper motor overlap algorithm does not compensate for angular misalignment. The strap 77A04 may become part of the wafer 808 and thus be aligned with its alignment mark 3120 . Bonding strips 77A06 can be part of the donor wafer layer and are oriented parallel to the transistor energy bands and thus also in an east-west direction. Bonding strip 77A06 can be aligned with master wafer alignment mark 3120 with Rdx and Rdy offsets (ie, equivalently aligned with donor wafer alignment mark 3020 ). The via 77A02 connecting the two bonded strips 77A04 and 77A06 can be part of the top layer 7001 pattern. The vias 77A02 can be aligned with the main wafer alignment marks 3120 (with Rdy offset) in the north-south direction.

Alternatively, as shown in FIG. 78A, the repeating pattern of continuous diffusion regions of the gate depicted in FIG. 76 may have enlarged Wv 7802 to enlarge the row of bonded bars 77A06. The width Wv 7802 of the via trench 7618 between layers is equal to 10F, and the total width Wy 7804 of the north-south pattern repeat is equal to 23F.

As shown in FIG. 77B , in another example, gate 7622B may repeat in an east-west direction, mating with additional gate sidewall repeat 7810 . This repeating pattern of transistors forms the energy bands of the transistors along the east-west axis, where each transistor has a gate 7622B. The repeating pattern in the north-south direction can include transistor energy bands connected in parallel, where each transistor has an active region 7612 or 7614 . The pattern repeat width Wx 7806 in the east-west direction is 14F, and the length of the donor wafer bonding strip 77A06 can be set as the length Wx 7806 plus the length of the extension necessary to meet the setting rules mentioned above. The orientation of the donor wafer bonding strips 77A06 may be parallel to the transistor energy bands, and thus is also east-west.

Figure 78C shows a cross-section of a portion of a gate array with a repeating transistor wafer structure. The die is similar to the one in Fig. 78B, where the gates of the N transistors are connected to the corresponding gates of the P transistors. Figure 78C shows the implantation of basic logic chips: Inv, NAND, NOR and MUX.

Or, as shown in FIG. 79, to increase the density of the through-hole connection lines in the through-holes between the layers of the donor wafer, set the length of the donor wafer bonding strip 77A06 to be lower than Wx 7306 by increasing Engage 7900 of the width of the strip in housing 77A04 and offset via hole 77A02. Align splice strips 77A04 and 77A06 as previously described. Vias 77A02 are aligned with master wafer alignment marks 3120 (with Rdy offset) in the north-south direction, and aligned with the alignment marks 3120 of acceptor wafer 808 in the east-west direction, slightly offset to the east, as previously described. The offset dimension is equal to the reduction of the donor wafer bonding strap 77A06.

In another example, functional blocks of non-repeating patterned device structures can be prepared on the donor wafer and the diced layer using the techniques described above. The donor wafer of this non-repeating pattern device structure may be a memory block of a DRAM, or a functional block of an input-output circuit, or other functional blocks. The donor wafer non-repeating pattern device structure 8004 can be connected to the acceptor wafer-housing wafer bare die 8000 using conventional bonding structures 8002 .

The shell 808 wafer bare chip 8000 is shown in FIG. 80 . The connection structure 8002 can be placed inside or outside the non-repeating structure 8004 . As mentioned above, during the layer cutting process, Mx 8006 is equal to the maximum distance in the east-west direction between the donor wafer and the acceptor wafer 8000 misalignment plus the extension necessary to meet the set rules; My 8008 is equal to The maximum distance in the north-south direction between the donor wafer and the acceptor wafer misalignment plus the extension necessary to satisfy the set rules. Mx 8006 and My 8008 may include increased angular misalignment due to wafer-to-wafer bonding, as well as uncompensated donor wafer bow and warp. The stepper motor overlap algorithm does not compensate for angular misalignment. The length of the bonding strip 8010 in the north-south direction of the acceptor wafer is equal to My 8008, aligned with the acceptor wafer alignment marks 3120. The length of the bonding strip 8011 in the east-west direction of the donor wafer is equal to Mx 8006 , aligned with the donor wafer alignment marks 3020 . The vias 8012 connecting them are aligned with the acceptor wafer alignment marks 3120 in the east-west direction and with the donor wafer alignment marks 3020 in the north-south direction. For ease of explanation, the lower metal bonding bars of the donor wafer are oriented east-west, and the higher metal bonding bars of the donor wafer are oriented north-south. The direction of engaging the strips is interchangeable.

The donor wafer may contain components of repeating device structures (as shown in FIGS. 76 and 78B ) as well as non-repeating device structures. As mentioned above, one of these two components is a repeating component, and the other is a non-repeating component, which can draw graphics independently. The reason is that the pattern of non-repeating components can be aligned with the donor wafer alignment marks 3020, while the pattern of repeating components can be aligned with the acceptor wafer alignment marks 3120 (with Rdx and Rdy offsets). Therefore, the general connection structure shown in Fig. 80 can be used for the connection between these two components. East-west bonded strips 8011 can be aligned with donor wafer alignment marks 3020 and non-repeating components, while north-south bonded bars 8010 can be aligned with acceptor wafer alignment marks 3120 (with offset) and repeated components Graphical alignment. The vias 8012 connecting these straps need to be aligned with the donor wafer alignment marks 3020 in the north-south direction and the acceptor wafer alignment marks 3120 (with offset) in the east-west direction.

The above process, whether it is a single type transistor donor wafer or a complementary type transistor donor wafer, can be repeated many times when building a multi-layer 3D monolithic integrated system. These processes can also provide multiple component technologies in a single 3D manner. For example, component I/O or analog circuits (such as phase-locked loop-PLL), clock distribution or radio frequency circuits can be integrated into CMOS logic circuits through the method of layer cutting; or bipolar circuits can be integrated into CMOS logic circuits; Or integrate analog components into logic circuits, etc. Prior art also provides other techniques for building 3D components. The most commonly used techniques are to use thin film transistors (TFT) to build a single 3D device; or to stack prefabricated wafers and then use through-silicon vias (TSVs) to connect the prefabricated wafers. Since the relatively wide side of the 3D layer is about 60 microns, the density of TSVs connecting them is also relatively low. The TFT approach depends on the performance of thin film transistors, while the stacking method depends on the relatively large size of TSV vias. The size of one side (approximately equal to a few microns). It can be seen from many cases of building 3D ICs by layer cutting in the present invention that the cut layer is usually a thin layer with a thickness less than 0.4 microns. From some cases of the present invention, it can be seen that the 3D IC with cut-out layer is in sharp contrast with the previous 3D IC constructed using TSV technology. When using TSV technology, the thickness of the layer connected by TSV exceeds 5 microns, and in many cases exceeds 50 microns.

The other process flows shown in FIGS. 20-35 , 40 , 54-61 , and 65-94 provide true monolithic 3D integrated circuits. The process can use single-crystal silicon transistor layers, layers aligned with each other, and layers limited only by the performance of stepper motors. The monocrystalline silicon transistor layer should be able to align the upper transistors with the underlying circuitry. Likewise, the contact spacing between the upper transistor and the underlying circuitry should match the contact spacing of the underlying layer. With the latest stacking methods, the stacked wafers are only a few microns thick. When using the alternative processes mentioned in Figures 20-35, 40, 40-61, and 65-94, the layers are very thin, typically only 100 nanometers; and recent workpieces have demonstrated layer thicknesses of only about 20 Nano.

Therefore, the alternative process shown can be used for true monolithic 3D component production. This monolithic 3D technology allows for full density integration with tighter feature measurements that can keep pace with the semiconductor industry.

In addition, a true monolithic 3D device can generate various subcircuit structures in an effective three-dimensional space, and its performance is better than that of the equivalent 2D structure. The following will illustrate how to use the true monolithic 3D method to build a 3D chip library.

Figure 42 shows a typical layout and schematic diagram of a 2D CMOS inverter, where NMOS transistors 4202 and PMOS transistors 4204 are placed side by side in wells with different doping levels. The NMOS source 4206 is grounded normally, the NMOS and PMOS drains 4208 are electrically connected together, the NMOS and PMOS gates 4210 are electrically connected together, and the PMOS 4207 source is connected to +Vdd. The 3D structures described below will make use of these third-dimensional connecting lines.

The preprocessing method of the acceptor wafer is shown in Fig. 43A. A large dose of N+ type ions can be implanted into the heavily doped N single crystal silicon wafer 4300 and annealed to form a layer 4302 with lower resistivity. Alternatively, high temperature resistant metals such as tungsten can be added as low resistance interconnect layers, or thin slab layers or treated geometry metallization layers. Oxide 4304 is grown or deposited, ready to bond the wafer. As shown in Figure 43B, the donor wafer is preprocessed in preparation for layer dicing. Figure 43B is a drawing of a pre-processed donor wafer for layer dicing. The P-wafer 4310 can be prepared for layer dicing by deposition or growth of oxide 4312, surface plasma treatment, atomic type implantation (such as H+ implantation in preparation of SmartCut cutting plane 4314). As shown in Figure 43C, the layer dicing process can now begin by layer dicing the pre-processed monocrystalline silicon donor wafer on top of the acceptor wafer. Now the cutting surface 4316 can be polished smooth by CMP, chemical polishing and epitaxial growth (EPI) polishing simultaneously, or not.

44A to 44G show the process flow of generating components and wiring and building a 3D module library. As shown in FIG. 44A , a grind stop layer 4404 (eg, silicon nitride or amorphous carbon) may be deposited after the protective oxide layer 4402 . The NMOS source-ground 4406 is masked and etched to contact the heavily doped N+ layer 4302 as a ground plane. This operation can be performed with typical contact dimensions and accuracies. For clarity, the two oxide layers (acceptor wafer oxide layer 4304 and donor wafer oxide layer 4312 ) are merged together and referred to as 4400 . Fill the NMOS source-ground 4406 with heavily doped polysilicon or amorphous silicon, or a high melting point metal (such as tungsten); then perform chemical-mechanical polishing as shown in FIG.

The standard NMOS transistor formation process can now begin, with two exceptions. Case 1: In the implantation step for distinguishing NMOS and PMOS devices, the photolithographic masking process is omitted, and only NMOS devices are formed. The second case: the high-temperature annealing step is adopted or not taken during the NMOS forming process, and some or all of the necessary annealing procedures described later can only be completed after the PMOS forming. As shown in FIG. 44C, through the mask, the unmasked P-layer 4301 is plasma etched to the oxide layer 4400, the mask layer is stripped, a gap-fill oxide layer is deposited, and the gap is removed by chemical-mechanical polishing. The fill oxide is smoothed to form a typical shallow trench insulator (STI) region 4410 between the final NMOS transistors. Simultaneous injection with or without threshold adjustment can also be performed. The remaining oxide is removed by HF (hydrofluoric acid) etching, and the silicon surface is cleaned.

Gate oxide 4411 is thermally grown and doped polysilicon is deposited to form the gate stack. Photolithography and etching are performed on the gate stack layer to form NMOS gate 4412 and polymer on STI wiring 4414 as shown in FIG. 44D . Alternatively, a high-k metal gate process step can be utilized at this stage to form the gate stack layer 4412 and form wiring over the STI 4414 . At this time, gate stack self-alignment LDD (Lightly Doped Drain) and halo breakdown implantation can be performed to adjust the breakdown characteristics of contacts and transistors.

Figure 44E shows a typical spacer deposition of oxide and nitride followed by an etch back process to form implant bias spacers 4416 on the gate stack layer. Then perform self-aligned N+ source and drain implantation to generate NMOS transistor source and drain 4418 . At this time, it is necessary to start implanting ions, set the initial joint depth, and whether to perform high-temperature annealing. A self-aligned silicide may then be formed. Additionally, one or more interconnect layers with corresponding contacts and vias (not shown) can be constructed using standard semiconductor fabrication processes. Use metals such as copper or aluminum to build metal layers at low temperatures, or use refractory metals such as tungsten for normal use at high temperatures exceeding 400°C. As shown in Figure 44F, a thick oxide film 4420 is deposited and planarized by chemical-mechanical polishing (CMP). The wafer surface 4422 is treated by plasma activation during processing of the wafer to become a recipient wafer for the next layer dicing operation.

As shown in Figure 45A, the donor wafer for PMOS generation is pre-processed in preparation for layer dicing. The N- wafer 4502 can be prepared for layer dicing by deposition or growth of oxide 4504, surface plasma treatment, atomic type implantation (eg H+ implantation in preparation of SmartCut cutting plane 4506).

As shown in Figure 45B, the layer dicing process can now begin by layer dicing the pre-processed monocrystalline silicon donor wafer on top of the acceptor wafer and layer dicing the acceptor wafer oxide 4420 onto the donor wafer oxide Object 4504 on. To optimize the flexibility of the PMOS, the donor wafer can be rotated 90° so that the acceptor wafer becomes part of the bonding process, facilitating the generation of PMOS trenches in the <110> silicon plane orientation. Now the cutting surface 4508 can be polished smooth by CMP, chemical polishing and epitaxial growth (EPI) polishing at the same time, or not.

For clarity, the two oxide layers (acceptor wafer oxide layer 4420 and donor wafer oxide layer 4504 ) are merged together and referred to as 4500 . The standard PMOS transistor formation process can now begin, with one exception. The photolithographic masking process is omitted in the implantation step for distinguishing NMOS and PMOS devices, and only PMOS devices are formed. One advantage of this 3D wafer structure is that PMOS transistors and NMOS transistors can be formed independently. Therefore, the forming process of each transistor can be optimized individually. This process is accomplished through individual selection of crystal orientation and various stress materials and techniques (eg doping profiles, material thickness and composition, temperature cycling, etc.).

A grind stop layer 4404 (eg, silicon nitride or amorphous carbon) may be deposited after the protective oxide layer 4510 . As shown in FIG. 45C, through photolithography, plasma etching to the oxide layer 4500, deposition of a gap-fill oxide layer, and smoothing of the gap-fill oxide layer through chemical-mechanical polishing, a typical PMOS transistor is formed between the final PMOS transistors. The shallow trench insulator (STI) region 4512. Simultaneous injection with or without threshold adjustment can also be performed.

The remaining oxide is removed by HF (hydrofluoric acid) etching, and the silicon surface is cleaned. Gate oxide 4514 is thermally grown and doped polysilicon is deposited to form the gate stack. As shown in FIG. 45D , the gate stack layer is photolithographically and etched to form a PMOS gate 4516 and a polymer on the STI wiring 4518 . Alternatively, a high-k metal gate process step may be utilized at this stage to form the gate stack layer 4516 and form wiring over the STI 4418 . At this time, gate stack self-alignment LDD (Lightly Doped Drain) and halo breakdown implantation can be performed to adjust the breakdown characteristics of contacts and transistors.

Figure 45E shows a typical spacer deposition of oxide and nitride followed by an etch back process to form implant bias spacers 4520 on the gate stack layer. Then perform self-aligned P+ source and drain implantation to generate PMOS transistor source and drain 4422 . Hyperthermic annealing in PMOS and NMOS components using RTA (rapid hyperthermic annealing) or furnace thermal exposure to open the graft and set the junction. Alternatively, laser annealing can be performed after the NMOS and PMOS source and drain implants to open the grafts and set the contacts. As previously indicated, the graft can be returned with an optically absorbing and reflective layer, and the joint opened.

As shown in Figure 45F, a thick oxide film 4524 is deposited and planarized by chemical-mechanical polishing (CMP).

Figure 45G illustrates the programming method for three sets of eight layers of interlayer nodes. Etch stop and grind stop layers or layers 4530 may be deposited, such as nitride or amorphous carbon. First, the deepest contact 4532 of the N+ ground plane layer 4302, and the NMOS only gate on the NMOS drain only contact 4540 and the STI contact 4546 are masked and etched in the first contact step. Next, the NMOS & PMOS gates and NMOS and PMOS drain contacts 4544 on the STI interconnect 4542 are masked and etched in a second contact step. Next, mask and etch the PMOS flat contacts: the PMOS gate wiring on the STI contact 4550 in the third contact step, the only PMOS source contact 4552 and the only PMOS drain contact 4554 . Alternatively, the shallowest contacts are masked and etched first, the middle contacts are processed next, and the deepest contacts last. The metal lines are masked, etched, and filled with barrier metal, and CMP is performed by a common dual-embedded interconnection method to complete eight kinds of contact connections.

As shown in FIGS. 46A to 46C , with regard to the layout and schematic diagram of the 2D CMOS inverter chip shown in FIG. 42 , an example of a compressed 3D CMOS inverter chip can be constructed using the above process flow. The top view of the 3D chip is shown in FIG. 46A , where the STI 4600 of the NMOS and the PMOS are consistent, and the PMOS is on top of the NMOS.

See Figure 46B for a cross-sectional view in the X direction, and Figure 46C for a cross-sectional view in the Y direction. The NMOS and PMOS gates 4602 are aligned and stacked, connected by an NMOS gate on the STI to a PMOS gate on the STI contact 4604 . Figure 42A shows how the inverter input signal A is connected. As shown in Figure 42, the N+ source contact (similar to contact 4406 of Figure 44B) of the ground plane 4606 in Figures 46A & 46C grounds the NMOS source. As shown in FIG. 42, PMOS source contact 4608 (similar to contact 4552 in FIG. 45G) connects the PMOS source to +V 4207. As shown in FIG. 42, NMOS and PMOS drain common junction 4610 (similar to junction 4544 in FIG. 45G) has common junction 4208 as output Y. The ground-to-ground plane contact (similar to contact 4532 in Figure 45G) is not shown. This contact is not required in every die and can be shared.

Other 3D logic or memory chips can be constructed in a similar manner. FIG. 47 shows a typical layout and schematic diagram of a 2D dual-input NOR chip, in which NMOS transistors 4702 and PMOS transistors 4704 are arranged side by side in wells with different doping levels. The NMOS source 4706 is generally grounded, and the two NMOS sources and one of the PMOS drains 4708 are electrically connected to form an input Y. NMOS & PMOs gates 4710 are electrically connected together to form input A or output B. The 3D structures described below will make use of these connecting lines in the third dimension.

As shown in FIGS. 44A-48C , the process flow described above can be used to construct a compressed 3D dual-input NOR chip example. The top view of the 3D chip is shown in FIG. 48A , where the shallow trench insulator (STI) 4800 of NMOS and PMOS is consistent at the bottom and side, not on the top silicon layer, and only the NMOS drain is connected. The cross-sectional view of the wafer in the X direction is shown in FIG. 48B, and the cross-sectional view in the Y direction is shown in FIG. 48C.

The NMOS and PMOS gates 4802 are aligned and stacked, each gate being connected by an NMOS gate on the STI to a PMOS gate on the STI contact 4804 (similar to contact 4542 shown in Figure 45G). Figure 47 shows the connection of input signal A & B.

As shown in Figure 47, the N+ source contact of ground plane 4806 in Figures 48A and 48C connects the NMOS source to ground. As shown in FIG. 47, PMOS source contact 4808 (similar to contact 4552 in FIG. 45G) connects the PMOS source to +V 4707. As shown in FIG. 47, NMOS and PMOS drain common junction 4810 (similar to junction 4544 in FIG. 45G) has common junction 4708 as output Y. NMOS source contact 4812 (similar to contact 4540 in FIG. 45) connects the NMOS to output Y. Output Y is connected to NMOS and PMOS drain common junction 4810 using metal to form output Y in FIG. 47 . The ground-to-ground plane contact (similar to contact 4532 in Figure 45G) is not shown. This contact is not required in every die and can be shared.

As shown in FIGS. 49A-49C , an alternate compressed 3D dual-input NOR wafer paradigm can be constructed using the above-described process flow. The top view of the 3D wafer is shown in FIG. 49A , where the shallow trench insulation (STI) 4900 of NMOS and PMOS is consistent on the top and sides, and is not on the top silicon layer. This creates isolation between the NMOS-A and NMOS-B transistors and connects the separate gates. As shown in Figure 47, an NMOS or PMOS transistor with the letters -A or -B designates the NMOS or PMOS transistor to which the gate is connected, either the A input or the B input. The cross-sectional view of the wafer in the X direction is shown in FIG. 49B, and the cross-sectional view in the Y direction is shown in FIG. 49C.

PMOS-B gate 4902 is aligned with dummy gate 4904 and stacked on top of it; PMOS-B gate 4902 is only connected to input B through the PMOS gate on STI contact 4908. Both the NMOS-A gate 4910 and the NMOS-B gate 4912 are under the PMOS-A gate 4906 . The NMOS-A gate 4910 and the PMOS-A gate 4912 are connected together and connected by the NMOS gate on the STI to input A, which in turn is connected to the PMOS gate on the STI contact 4914 (similar to FIG. 45G The contact shown in 4542). NMOS-B gate 4912 is connected to input B by the NMOS only gate on STI contact 4916, similar to contact 4546 shown in FIG. Figure 47 shows how input signals A & B 4710 are connected.

As shown in Figure 47B, the N+ source contact of ground plane 4918 in Figures 49A and 49C grounds the NMOS source, similar to ground 4406 in Figure 44B. As shown in FIG. 47 , a PMOS-B source contact 4920 for Vdd (similar to contact 4552 in FIG. 45G ) connects the PMOS source to +V 4707 . As shown in FIG. 47, the NMOS-A, NMOS-B, and PMOS drains share a joint 4922 (similar to joint 4544 in FIG. 45G) with common joint 4708 as output Y. The ground-to-ground plane contact (similar to contact 4532 in Figure 45G) is not shown. This contact is not required in every die and can be shared.

CMOS transfer gates can be constructed using the process flow described above. Figure 50A shows an example schematic and layout of a typical 2D CMOS transfer gate. The NMOS transistor 5002 and the PMOS transistor 5004 are arranged side by side in wells with different doping levels. Control signal A (as NMOS gate input 5006) and its complement  (as PMOS gate input 5008) allows the input signal to be fully passed to the output signal when both NMOS and PMOS transistors are on (A=1, Â=0), When both NMOS and PMOS transistors are turned off (A=0, Â=1), no input signal is passed through. The sources 5010 of the NMOS and PMOS are electrically connected together and connected to an output; the drains 5012 of the NMOS and PMOS are connected together electrically to generate an output. The 3D structures described below will make use of these connecting lines in the third dimension.

As shown in FIGS. 50B-50D , a compressed 3D CMOS transfer chip example can be built using the above process flow. The top view of the 3D wafer is shown in FIG. 50B , where the shallow trench insulation (STI) 5000 of NMOS and PMOS is consistent on the top and sides. The cross-sectional view of the wafer in the X direction is shown in FIG. 50C, and the cross-sectional view in the Y direction is shown in FIG. 50D. The PMOS gate 5014 is aligned with the NMOS gate 5016 and stacked. The PMOS gate on STI contact 5018 connects the PMOS gate 5014 to the control signal 5008. The NMOS gate on STI contact 5020 connects NMOS gate 5016 to control signal A 5006 . NMOS and PMOS source common contact 5022 connects common connection layer 5010 to the input in Figure 50A. NMOS and PMOS drain common contact 5024 connects common connection layer 5012 to the output in FIG. 50A.

This 3D process flow and method can be used to build other logic chips and memory chips, such as dual-input NAND gates, transfer gates, NMOS drivers, flip-flops, 6T SRAM, floating body DRAM, CAM (addressable memory) array etc.

It is also possible to build more types of compressed 3D module libraries, so that there is one or more layers of metal wiring between NMOS and PMOS components. This method can build more compact wafers, especially complex wafers; however, as mentioned earlier, low-temperature layer-slicing and transistor formation processes should now be used to build the top PMOS components, unless the metal between the NMOS and PMOS layers is used. Refractory metals such as tungsten.

Therefore, in FIG. 43 and FIG. 44, the above-mentioned process flow of the module library can be adopted. As shown in Figure 21, Figure 22, Figure 29, Figure 39 and Figure 40, next, one or more conventional metal wiring layers are built on top of the NMOS components, and then that wafer is regarded as the acceptor wafer or "enclosure". "Wafer 808, the PMOS components are layer sliced and built using one of the low temperature processes.

As shown in Figures 51A-51D, the process flow described above can be used to build compressed 3D CMOS 6-transistor SRAM (Static Random Access Memory) chips. A schematic diagram of a SRAM chip is shown in FIG. 51A. Reading the chip is controlled by word line transistors M5 and M6, where M6 is labeled 5106. The read transistor controls the connection of bitline 5122 and bitline barline 5124. The two cross-coupled inverters M1-M4 are pulled up to Vdd 5108 by M1 or M2 5102, and then pulled to ground 5110 by transistor M3 or M4 5104.

The top view of the NMOS (metal not shown) of the 3D SRAM chip is shown in Figure 51B; the cross-sectional view of the SRAM chip in the X direction is shown in Figure 51C; the cross-sectional view in the Y direction is shown in Figure 51D. NMOS word line access transistor M6 5106 is connected to bit line bar type line 5124 (contact with NMOS metal 1). The NMOS pull-down transistor 5104 is connected to the ground line 5110 by the contact of NMOS metal 1, and is connected to the N+ ground layer of the backplane. Bit line 5122 and TIO 5100 in NMOS metal 1 are shown. The Vdd supply 5108 is brought into the die on PMOS Metal 1 and connected to M2 5102 through the P+ contact. The PMOS polysilicon on the STI to the NMOS polysilicon on the STI contact 5112 connects the gate of M2 5102 and the gate of M4 5104, illustrating the method of 3D cross-coupling. The common drains of M2 and M4 are connected to bit line sense transistor M6 through PMOS P+ to NMOS N+ contact 5114 .

As shown in FIGS. 62A-62D , the above-described process flow can be used to construct an example of a compressed 3D CMOS dual-input NAND chip. A schematic diagram and a 2D layout of a NAND-2 chip are shown in FIG. 62A. The sources 6211 of the two PMOS transistors 6201 are connected together and connected to the V+ power supply. Two PMOS drains are connected together, one of which is connected to the NMOS drain 6213 and the other is connected to the output Y. Input A 6203 is connected to one PMOS gate and one NMOS gate. Input B 6204 is connected to the other PMOS and NMOS gates. The NMOS A drain connects 6220 to the NMOS B source, and the PMOS B drain 6212 is grounded. The 3D structures described below will make use of these connecting lines in the third dimension.

A top view of a 3D NAND-2 chip (metal not shown) is shown in FIG. 62B; a cross-sectional view of a NAND-2 chip in the X direction is shown in FIG. 62C; a cross-sectional view in the Y direction is shown in FIG. 62D. The two PMOS sources 6211 are connected together in the PMOS silicon layer and connected to the V+ power metal 6216 through a contact in the PMOS metal 1 layer. The NMOS A drain and the PMOS A drain use the P+ to connect the 6213 to the N+ contact, and connect to the output Y metal 6217 in the PMOS metal 2, and then connect to the PMOS B drain contact through the PMOS metal 1 6215 superior. Input A on PMOS metal 2 6214 connects 6203 to PMOS A gate and NMOS A gate, NMOS A gate connects it to NMOS gate on STI contact through PMOS gate on STI. Input B connects the 6204 to the PMOS B gate, and NMOS B uses the P+ gate on the STI to connect it to the NMOS gate on the STI contact. The NMOS A source and the NMOS B drain are connected together 6220 on the NMOS silicon layer. The NMOS B source 6212 is connected to the ground line 6218 by the NMOS metal 1 contact, and is connected to the backplane N+ ground plane. Transistor insulating oxide 6200 is shown in the figure.

Other types of compressed 3D libraries can also be built such that there is one or more layers of metal wiring between the NMOS and PMOS component layers. This method can build more compact wafer structures, especially complex wafers; however, as mentioned earlier, low-temperature layer-slicing and transistor formation processes should now be used to build devices above the first NMOS layer.

Therefore, in FIG. 43 and FIG. 44, the above-mentioned process flow of the module library can be adopted. As shown in Figure 21, Figure 22, Figure 29, Figure 39 and Figure 40, next, one or more conventional metal wiring layers are built on top of the NMOS components, and then that wafer is regarded as the acceptor wafer or "enclosure". "Wafer 808, the PMOS components are layer sliced and built using one of the low temperature processes. This low-temperature process can then be repeated to form another layer of PMOS or NMOS components, and so on.

As shown in Figures 53A-53E, the process flow described above can be used to build a compressed 3D CMOS Addressable Memory (CAM) array. A schematic diagram of a CAM chip is shown in Figure 53A. The read SRAM chip is controlled by word row transistors M5 and M6, where M6 is marked as 5332. The read transistor controls the connection of bitline 5342 and bitline barline 5340. The two cross-coupled inverters M1-M4 are pulled up to Vdd 5334 by M1 or M2 5304, and then pulled to ground 5330 by transistor M3 or M4 5306. The match line 5336 transmits the matching or non-matching status of the comparing circuit to the matching address decoder. The sense line 5316 and the sense bar line 5318 select the comparison chip used for address retrieval and ground 5322 the gates of the pull-down transistors M8 and M10 5326 . The gates of the SRAM state read transistors M7 and M9 5302 are connected to the nodes n1 and n2 of the SRAM chip to read the state of the SRAM chip into the comparison circuit chip. The 3D structures described below will make use of these connecting lines in the third dimension.

The top view of the NMOS on the 3D CAM chip (not shown metal) is shown in Figure 53B; the top view of the NMOS on the 3D CAM chip (metal shown) is shown in Figure 53C; the cross-sectional view of the 3D CAM chip in the X direction is shown in Figure 53D; the cross-sectional view in the Y direction See Figure 53E. NMOS word line access transistor M6 5332 is connected to bit line bar 5342 (N+ contact with NMOS metal 1). The NMOS pull-down transistor 5306 is connected to the ground line 5330 by the N+ contact of the NMOS metal 1, and is connected to the N+ ground layer of the backplane. Bit line 5340 and TIO 5300 in NMOS metal 1 are shown. The ground plane 5322 is brought into the die on the upper NMOS metal-2. Vdd supply 5334 is brought into the die on PMOS metal-1 and connected to M2 5304 through the P+ contact. PMOS polysilicon on STI to bottom NMOS polysilicon on STI contact 5314 connects the gate of M2 5304 to the gate of M4 5306, illustrates the method of SRAM 3D cross-coupling, and connects to the comparison chip node through PMOS metal-1 5312 n1. Connect common drains of M2 and M4 to bit line read transistor M6 through PMOS P+ to NMOS N+ contact 5320, node n2 to M9 gate 5302 through PMOS metal-1 5310 and metal to Gate on STI contact 5308. The gate 5326 of the upper NMOS comparison chip ground pull-down transistor M10 is connected to the detection line 5316, and is connected to the gate polysilicon on the STI contact through NMOS metal-2. A sense line 5318 in the upper NMOS metal-2 connects the thru contact 5324 to the gate of M8 in the upper NMOS layer. Match line 5336 in upper NMOS Metal-2 is connected to the drain side of M9 and M7.

Other types of compressed 3D modules can also be built such that there is one or more layers of metal wiring between the NMOS and PMOS component layers and one or more components are built vertically.

Compressed 3D CMOS eight-input NAND chips were constructed as shown in Figures 63A to 63G. A schematic diagram and 2D layout of a NAND-8 chip is shown in FIG. 63A. The sources 6311 of the eight PMOS transistors 6301 are connected together and connected to the V+ supply. Two PMOS drains are connected together 6313, one of which is connected to the NMOS A drain and the other is connected to the output Y. Inputs A to H are connected to one PMOS gate and one NMOS gate. Input A is connected to PMOS A gate and NMOS A gate, and input B is connected to PMOS B gate and NMOS B gate. By analogy, input H is connected to PMOS H gate and NMOS H gate. The eight NMOS transistors between the output Y, the PMOS drain and the ground plane are connected in series. The 3D structures described below will make use of these third-dimensional connecting lines.

A top view of a 3D NAND-8 wafer (metal not shown, with horizontal NMOS and PMOS components) is shown in Figure 63B; a cross-sectional view of the wafer in the X direction is shown in Figure 63C; a cross-sectional view in the Y direction is shown in Figure 63D. A top view of NAND-8 with vertical PMOS and horizontal NMOS components is shown in Figure 63E; a cross-sectional view in the X direction is shown in Figure 63F; a cross-sectional view in the Y direction is shown in Figure 63H. The equivalent structures in the cases shown in Figures 63B to 63D and Figures 63E to 63G may also use the same reference numbers. The eight PMOS sources 6311 are connected together in the PMOS silicon layer and connected to the V+ power metal 6316 through the P+ of the metal contact in the PMOS metal 1 layer. The NMOS A drain and the PMOS A drain 6313 are connected to the N+ contact using the through P+, and connected to the output Y power metal 6315 in the PMOS metal 2, and then connected to the PMOS drain through the PMOS metal 1 6215 Point. Input A on PMOS metal 2 6314 connects 6303 to PMOS A gate and NMOS A gate, NMOS A gate connects it to NMOS gate on STI contact 6314 through PMOS gate on STI. All other inputs are similarly connected to the P and N gates. The NMOS A source and the NMOS B drain are connected together 6320 on the NMOS silicon layer. The NMOS H source 6232 is connected to the ground line 6318 by the NMOS metal 1 contact, and is connected to the backplane N+ ground plane. Transistor insulating oxide 6300 is shown.

A compressed 3D CMOS eight-input NOR chip was constructed as shown in Figures 64A to 64G. A schematic and 2D layout of a NOR-8 chip is shown in Figure 64A. The PMOS H transistor source 6411 is connected to the V+ supply. The NMOS drains are connected together 6413 and to the PMOS A drain and output Y. Inputs A to H are connected to a PMOS gate and an NMOS gate. Input A 6403 is connected to PMOS A gate and NMOS A gate. All NMOS sources are grounded 6412. In the gate stack layer, PMOS G, the PMOS H drain connects 6420 to the next PMOS source, and so on. The 3D structures described below will make use of these connecting lines in the third dimension.

See Figure 64B for a top view of a 3D NOR-8 wafer (metal not shown, with horizontal NMOS and PMOS components); see Figure 64C for a cross-sectional view of the wafer in the X direction; and 64D for a cross-sectional view in the Y direction. A top view of NAND-8 with vertical PMOS and horizontal NMOS components is shown in Figure 64E; a cross-sectional view in the X direction is shown in Figure 64F; a cross-sectional view in the Y direction is shown in Figure 64G. The PMOS H source 6411 is connected to the V+ power metal 6416 in the PMOS metal 1 layer through the P+ of the metal contact. The PMOS H drain connects 6420 to the PMOS G source in the PMOS silicon layer. The NMOS source 6412 is fully grounded through the N+ of the NMOS metal-1 contact, and is connected to the N- substrate metal line 6418 and the backplane N+ ground plane. The input A on PMOS metal-2 is connected to the PMOS and NMOS gate 6403 with the gate on the STI, which is then connected to the gate on the STI contact 6414. Use NMOS Metal-2 6415 to connect all NMOS Drains to NMOS A Drain and PMOS A Drain 6413, P+ to N+, PMOS Metal-2 contact 6417 (connected to output Y). Figure 64G illustrates the use of vertical PMOS transistors to closely connect stacked sources and drains and form the compressed region wafer shown in Figure 64E. Transistor insulating oxide 6400 is shown.

This allows the construction of CMOS circuits, in which various circuit chips are constructed on two silicon layers, resulting in smaller circuit areas and shorter distances within and between transistor wiring. Since wiring becomes the dominant factor in power consumption and speed, smaller area compression circuits can lead to lower power consumption and faster speed of end components.

Those of ordinary skill will think that this document introduces several different process flows using typical logic gates and memory chips as representative circuits. A skilled person will further consider which process to use in each setting. It is possible to generate a library of modules with all the necessary logic functions required in the setup so that the chips can be easily reused, either in a single setup or in other setups following the same process. A highly skilled person will also use many different setting styles in a given setting. For example, chips of the same height (standard chips often referred to in this industry) can be used to build a library of logic chip modules. Alternatively, a library of modules can be generated for use in longer continuous strips of transistors, known in the art as gated arrays. In another case, a chip module library can be built for use in manual or custom settings, which is also common in this technology. For example, in another alternate case, a library of logic chip modules tailored to the method of implementation may be used in a particular configuration, and this is a matter of configuration choice. If the module library is used on the same layer of the 3D IC, the selected module library can use the same process flow. Different process flows can be used at different levels of 3D IC, and one or more chip module libraries can be selected for each level in a separate setting.

Computer program products are also commonly used in the art. These products are stored on computer-readable media and used in data processing systems to automate the setting process. In layman's terms, they are computer-aided setting (CAD) software. Skills Ordinary people will consider the advantages of setting the chip module library in a way compatible with CAD software.

Those of ordinary skill will recognize that one or more process flows or libraries of modules that generate I/O chips, analog function chips, complete memory blocks of various types, and other circuits used in the setup process should be used in conjunction with Compatible with CAD software. After reading this manual, many other uses and examples will inspire the skilled person. Accordingly, the invention is limited only by the appended claims.

In addition, as mentioned above, if the circuit chip is built on one or more thin silicon layers, and has a dense, vertical through-silicon interconnection layer, the metallization layer configuration using this dense 3D technology can be carried out. perfect, as follows. Figure 59 shows a prior art silicon IC metallization setup scheme. The conventional transistor silicon layer 5902 is connected to the first metal layer 5910 through contacts 5904 . The dimensions of such interconnecting contact pairs and metal lines are typically at the minimum line resolution of the lithography and etch capabilities of the technology process node. It is often referred to as the "1X" set rule metal layer. In general, the next metal layer also follows the "1X" set rule, vias below metal lines 5912, 5905, and vias above 5906 (connecting metal 5912 to 5910 or 5914 is fine). Next, the next few metal layers are usually made twice the minimum lithography and etch capability, referred to as "2X" metal layers. The metal is thicker and has a higher current carrying capacity. This can be illustrated using the metal line 5914 matching the via 5907 and the metal line 5916 matching the via 5908 in FIG. 59 . Thus, the metal vias of 5918 (with bond pad opening 5922) and 5920 (with bond pad opening 5922) represent "4X" metallization layers where the planar and thickness dimensions are larger and thicker than the 2X and 1X layers. The exact number of 1X or 2X or 4X layers often changes, mainly depending on the needs of the interconnection layer and other requirements; however, the general process is that the larger the size of the metal line and metal space, the via holes as the metal layer are separated from the silicon The farther away the transistor is, the closer it is to the bond pad.

As shown in FIG. 60 , the scheme for setting the metallization layer of the 3D circuit can be improved. The first single crystal silicon or polycrystalline silicon component layer 6024 can be understood as the NMOS silicon transistor layer of the above-mentioned 3D module library chip, and can also be understood as a traditional logic transistor silicon substrate or layer. The "1X" metal layers 6020 and 6019 are connected to the silicon transistor using contacts 6010 and connected to each other or to metal line 6018 using vias 6008 and 6009 . The 2X layer is connected to the metal 6018 through the via 6007 , and the 2X layer is connected to the metal 6017 through the via 6006 . Vias 6005 connect 4X metal layer 6016 to metal 6015 also on 4X layer. Now, however, via 6004 is built according to the 2X set rule, so that metal line 6014 is also at 2X layer. The metal line 6013 and the via hole 6003 also comply with the 2X setting rule and meet their thickness requirements. The via holes 6002 and 6001 are connected to the metal wires 6012 and 6011, which meet the size and thickness requirements of the 1X minimum setting rule. Next, construct the TSVs 6000 of the PMOS layer cut silicon 6022 according to the 1X minimum setting rule, and provide the highest density of the top layer. The exact number of 1X or 2X or 4X layers will often vary, depending primarily on circuit area and current-carrying metallization set rules and set tradeoffs. The layer-cut upper transistor layer 6022 can adopt any low-temperature device described herein.

If the cut-out layer is not transparent to shorter wavelength light, it is therefore impossible to detect alignment marks and images with a resolution of one nanometer or tens of nanometers, due to the thickness of the cut-out layer or its carrier or substrate holder. Alignment can be performed using infrared (IR) optics and imaging techniques. However, its resolution and alignment capabilities may not be satisfactory. In this case, an alignment window is created during the slice process, allowing alignment using shorter wavelength light.

As shown in FIG. 111A , a donor wafer 11100 is used at the beginning of the normal process flow (using a conductive wafer 11100 formed by deposition, ion implantation and annealing, oxidation, crystal-like growth, simultaneously using the above methods, or other semiconductor processing steps and methods. layer 11102, semiconducting material or insulating material for preprocessing). The donor wafer 11100 can also be pre-processed with a layer cut boundary plane (eg, a hydrogen implant cut plane) before or after the formation of the layer 11102 , or thinned by the methods described above. The alignment window 11130 is first subjected to photolithography and plasma/reactive ion etching, then filled with a shorter wavelength transparent material (such as silicon dioxide) and planarized by chemical-mechanical polishing (CMP). Alternatively, chemical-mechanical polishing (CMP) can be used to further thin the donor wafer. The size and layout of the donor wafer that aligns the window 11130 depends on the maximum misalignment tolerance of the alignment plan used when bonding the donor wafer 11100 to the recipient wafer 11110, and the misalignment of the recipient wafer. The layout position of quasi-mark 11190. The alignment window 11130 can be machined before or after layer 11102 is formed. The acceptor wafer 11110 can be a pre-processed wafer with fully functional circuits, or a wafer with pre-cut layers, or a blank carrier or holding wafer or other types of substrates, also known as target wafer. For example, the acceptor wafer 11110 and the donor wafer 11100 may be single crystal silicon wafers or silicon-on-insulator (SOI) wafers or germanium-on-insulator (GeOI) wafers. The acceptor wafer 11110 metal connection pads or straps 11180 and acceptor wafer alignment marks are shown.

The bonding surfaces 11101 and 11111 of the donor wafer 11100 and the acceptor wafer 11110 can be used for wafer bonding through deposition, grinding, plasma or wet chemical treatment to promote successful bonding between wafers.

As shown in FIG. 111B , the donor wafer 11100 with layers 11102 , alignment windows 11130 and layer cut interface planes 11199 can then be flipped over, with higher resolution, and aligned to the acceptor wafer alignment marks 11190 And bonded to the acceptor wafer 11110.

As shown in FIG. 1111C , the donor wafer 11100 is diced at or thinned to the layer-cut interface plane so that portions of the donor wafer 11100 , alignment window 11130 and pre-process layer 11102 are aligned and bonded to Acceptor Wafer 11110.

As shown in FIG. 111D , the remaining portion 11100 of the donor wafer can be removed by grinding or etching; the cut-out layer 11102 can be further processed to generate the donor wafer assembly structure 11150 . The donor wafer assembly structure 11150 is precisely aligned with the recipient wafer alignment marks 11190 . The alignment window 11130' can be further processed into the alignment window area 11131. These donor wafer assembly structures 11150 may use through layer vias (TLVs) 11160 to connect the donor wafer assembly structures 11150 to the acceptor wafer metal connection pads or straps 11180 in a bonded manner. Since the cut-out layer 11102 is very thin, about 200nm or less in thickness, the TLV can be easily processed into common metal-to-metal vias. The diameter of the above-mentioned TLV reaches the highest technical level, such as several nanometers or tens of nanometers.

Another use of the high-density TLV 11160 in Figure 111D or in this document is to transfer the heat generated by the active circuit from one layer to another layer connected to the TLV through heat transfer, such as from the donor layer and device structure to the acceptor crystal. round or on a substrate. The TLV 11160 can also be used to transfer heat to a thermoelectric cooler, heat sink, or other heat sink on the wafer. The TLV part on the 3D IC can be mainly used for electrical coupling, or it can be mainly used for heat transfer. In many cases, TLVs are used for both electrical coupling and heat transfer.

Since the layers are stacked on the 3D IC, the power density per unit area will increase. The heat transfer function of monocrystalline silicon is the weakest at 150W/m-K. Silicon dioxide (the most common electrical insulator in modern silicon integrated circuits) has the weakest heat transfer function at 1.4W/m-K. If no heat sink is placed on the layer of the 3D IC stack, the bottom die or layer (furthest from the heat sink) has the worst heat transfer function to that heat sink, because the heat emitted from the bottom layer must pass through the die or layer above it. Layers of silicon dioxide and silicon.

As shown in FIG. 112A , a heat sink layer 11205 is deposited on top of a thin silicon dioxide layer 11203 which is deposited on the top surface of the interconnect metallization layer 11201 of the substrate 11202 . The heat dissipation layer 11205 may comprise plasma-enhanced chemical vapor deposition diamond-like carbon (PECVD DLC), whose thermal conductivity is 1000W/m-K, or other heat transfer materials, such as chemical vapor deposition (CVD) graphene (5000W/m-K) m-K) or copper (400W/m-K). The thickness of the heat dissipation layer 5015 is approximately between 20 nanometers and 1 micron. The ideal thickness range is 50nm to 100nm. The insulator is the most ideal accessory for the conductivity of the heat dissipation layer 11205, which can ensure that the through-layer through hole meets the minimum diameter specified by the set rules. If the heat sink is conductive, the opening of the TLV needs to be enlarged appropriately so that the non-conductive capping layer is deposited on the TLV walls before the conductive core of the TLV is deposited. Alternatively, if the heat sink layer 11205 is conductive, it can be masked and etched to provide a bond pad for the TLV and provide a larger grid around the pad for heat transfer. The heat sink can also be used as a ground plane or as a power trunk and ground bus for circuits above or below it. An oxide layer 11204 may be deposited (and also planarized to fill gaps in the thermal transfer layer) in preparation for wafer-to-wafer oxide bonding. The acceptor substrate 11214 may include a substrate 11202 , an interconnect metallization layer 11201 , a thin silicon dioxide layer 11203 , a heat dissipation layer 11205 and an oxide layer 11204 . As previously mentioned, after layer dicing, the donor wafer substrate can be processed with wafer-sized doped layers in preparation for molding of transistors and circuits (e.g., junctionless, RCAT, V-groove, and bipolar) 11206. If implantation is used, a mask oxide layer 11207 can be grown or deposited prior to implantation to ensure that the silicon is free from contamination during the implantation process and to provide an oxide layer for later wafer-to-wafer bonding. Slicing boundary planes 11299 (dashed lines in the figure) can be formed in the donor wafer substrate 11206 by hydrogen ion implantation, "ion dicing" or other methods described above. As previously discussed, in preparation for transistor formation, donor wafer 11212 may include donor substrate 11206, layer cut interface plane 11299, mask oxide layer 11207, and other layers (not shown). As mentioned above, both the donor wafer 11212 and the acceptor wafer 11214 are used for wafer bonding, and are bonded together on the surfaces of the oxide layer 11204 and the oxide layer 11207 at low temperature (less than 400° C.). The remaining cut-out layer 11206' may be formed by removing the portion of the donor wafer 11206 above the layer-cut interface plane 11299 by dicing or grinding or a process described above such as ion dicing or other methods. Alternatively, the host wafer 11212 can be first constructed using the method described above, for example, using a replacement gate (not shown) for ion dicing, and then layer-cut out onto the acceptor substrate 11214. The transistors are now fully or partially formed and aligned with the previously formed acceptor wafer alignment marks (not shown) and through-layer vias. In this way, a 3D IC with an integrated heat dissipation layer is constructed.

As shown in Figure 113, a set of power and ground gates (e.g. bottom transistor power and ground gate 11307 and top transistor power and ground gate 11306) can pass through layer power vias and ground The vias 11304 are connected together and connected to the non-conductive heat dissipation layer 11305 through thermal coupling. If the heat sink is a conductor, either it can only be used as a ground plane, or it can be patterned between the bonding pads of the TLV using the power plane and the ground pad. The density of power and ground gates and the through-layer vias of power and ground gates are set to increase some of the total thermal resistance of heat transfer for all circuits in the layers of the 3D IC stack. Bond oxide 11310, printed circuit board 11300, package heat sink layer 11325, bottom transistor layer 11302, top transistor layer 11321 and heat sink are shown. In this way, a 3D IC with an integrated heat sink, heat dissipation layer, and through-layer vias for power and ground gates is constructed.

As shown in FIG. 113B , a thermally conductive material (such as PECVD DLC) can be formed on the sidewall of the 3D IC structure in FIG. 113A , thereby forming a sidewall thermal conductor 11360 for heat removal from the sidewall. Bottom Transistor Layer Power and Ground Gates 11307, Top Transistor Layer Power and Ground Gates 11306, Thru Layer Power and Ground Vias 11304, Thermal Spreader 11305, Bond Oxide 11310, Printed Circuit 11300 , package heat sink layer 11325, bottom transistor layer 11302, top transistor layer 11312 and heat sink 11330 as shown.

The individual shape of each transistor also encourages the use of materials other than silicon to construct transistors. For example, one or more of the above-mentioned 3D layers can be applied with a thin III-V composite quantum well trenches (eg InGaAs and InSb). In this way, a high-mobility transistor is formed, and the p- and n-groove transistors can be optimized separately, which solves the integration problem of adding n and p III-V transistors on the same substrate at the same time, and also solves the problem of adding n and p III-V transistors on the same substrate. The challenge of integrating II-V transistors with traditional silicon transistors on one substrate. For example, the first layer of silicon transistors and metallization layers usually cannot be exposed to high temperatures above 400°C. The processing temperatures required for III-V composites, buffer layers, and dopants typically exceed the 400°C limit. By using the pre-deposition, doping, annealing layer donor wafer shaping and subsequent donor-to-acceptor wafer layer dicing techniques described above and illustrated in Figures 14, 20-29, and 43-45, Build III-V transistors and circuits on top of silicon transistors and circuits without damaging the silicon transistors and circuits below. Furthermore, even if there is a stress mismatch in the heterogeneous materials to be integrated (such as silicon and III-V composites), it can be mitigated by an oxide layer or a special buffer layer vertically between the heterogeneous material layers. In addition, this method can also integrate optoelectronic components, communication components, and data paths through traditional silicon logic transistors, memory transistors, and silicon circuit processing. In addition to silicon, germanium can also be used to build individual transistor layers individually.

It should be noted that this 3D IC technology can be used in many applications. By using the techniques described in Figures 21-35, the various structures shown in Figures 15-19 are built on a "foundation", possibly under the main or first or shell layer. These structures can also be fabricated on a "top layer", possibly above the main or first or outer skin layer.

It should also be noted that for a 3D programmable system, the size of its logic structure is determined by dicing the chip of the tiled array, as shown in Figure 36, and the "monolithic integrated circuit" 3D technology related to the "basic" in Figure 14 can be used. Or through the applicable 'cutting edge' 35 technology shown in Figure 21, add IO chips or memory chips, as shown in Figure 11. So in many cases it is preferable to use TSVs to construct 3D programmable systems, and sometimes it is better to use 'basic' or 'cutting-edge' technologies.

Here, if the substrate wafer, transfer wafer, or donor wafer is thinned through cleavage and chemical mechanical polishing, there are other methods that can be used to thin the wafer. For example, boron implantation and annealing can be used to create a surface on a silicon substrate that is thinned to produce a wet chemical etch stop plane. Dry etching, such as a cluster beam of halogen gas, can be used to thin the silicon substrate, followed by smoothing the silicon substrate with oxygen clusters. These thinning technologies can be used alone or comprehensively to meet the needs of the process flow to meet the appropriate thickness and surface smoothness.

9A through 9C exemplify a 3D-3D composite mold integrated construction method for IC systems and utilizing through-silicon vias. FIG. 9A illustrates the construction of an overall cross-die connection through all dies so that TSVs remain vertical.

Figure 9B illustrates a similarly sized mold building 3D system. FIG. 9B shows that TSVs 404 are in the same relative position in all die configuration standard interfaces.

Fig. 9C illustrates a 3D system of molds of different sizes. FIG. 9C also illustrates the use of wire bonding to connect all IC system 3 dies (three dies) with external links? .

FIG. 10A is a schematic diagram of the current technology in the United States, that is, the continuous array chip of patent 7,337,425. Bubbles 102 represent a continuous array of recurring blocks, and lines 104 represent potential horizontal and vertical cutting lines. Block 102 may be constructed according to Figure 10B102-1 with potential cut line 104-1 or Figure 10C with parallel converter fillet 106 that is block 102-2 and potential cut line 104-2 the components.

Usually logic components include a large number of various logic components, memory and I/O chips. The continuous array of current technology allows the die size to be determined outside the same die, so that the logic components will also change accordingly, but the three-way ratio between logic components, I/O chips and memory is difficult to change. In addition, there are various types of memory, such as static random access memory (SARM), dynamic random access memory (DRAM), flash memory, etc., and I/O chips are also in various forms, such as parallel converters. Some applications may still require other functions, such as processing programs, digital signal processing, analog functions, etc.

In the case of this invention, it can take a different approach. Instead of trying to combine these functions on one programmable die, which would require a large number of expensive mask sets, configurable systems are built using through-silicon vias. This "Integrated Circuit and Vertical Integration Packaging" technology has become US Patent 6,322,903, issued on November 27, 2001 to Oleg Siniaguine and Sergey Savastiouk.

According to the case of this invention, it can be suggested to use the continuous arrangement of blocks to concentrate one or several functions. Then, build the end system by integrating the desired value of each block in 3D IC.

FIG. 11A is a schematic diagram of the actual mask on a wafer containing FPGA blocks indicated by programmable logic 1100A. A chip is a contiguous array of programmable logic. 1102 is a potential dicing line to support building different molds and logic on one mask set. Such a mold can be used as the basis for 1202A, 1202B, 1202C or 1202D in the 3D system shown in FIG. 12 . As an alternative to the present invention, these dies can be used to carry most of the logic, and the desired memory and I/O chips can also be obtained through other dies connected by through-silicon vias. It should be noted that steel wire is not present in many cases, or even never used in cutting wire 108 . In this case, at least for logic dies, individual blocks can be connected by connecting unused potential dicing lines with a dedicated mask, depending on the desired die size. The actual cutting line can also be called the trunk line.

It should be noted that etching on a wafer is typically done by repeated projections in a "high-quality electronic step-and-repeat" manner known as a mask on the wafer. In many cases, it is preferable to consider separately the separation between the cyclic blocks 102, which are under the mask image-to-block comparison, related to the 2 projections. A simple description is to use a wafer, but in many cases a wafer only uses one mask on a block.

The loop block 102 takes various forms. For field programmable gate array applications, it is better to set the block 1101 between 0.5mm and 1mm, so that due to the unused potential cutting line 1102, there is a good balance between the terminal component size and the acceptable relative area loss. Keep a good balance.

The uniform cycle block of FIG. 11A has many advantages. Programmable devices can be constructed by dicing the wafer to the required device size. It also facilitates terminal components as complete composite components rather than just collections of individual blocks 1101 . Figure 36 shows a wafer with potential dicing lines 3602 carrying 3601 arrays of blocks, diced along actual dicing lines 3612 to construct a terminal assembly 3611 of 3x3 blocks. Termination assembly 3611 is constrained by actual cutting line 3612 .

FIG. 37 is a schematic diagram of a terminal component 3611, and 3611 includes nine blocks 3701, such as 3601. Each block 3701 contains a very small microcontroller chip - MCU3702. This control chip has a common architecture, such as 8051, with its own program memory and data memory. The microcontroller chip on each block will register the FPGA block 3701 with its programmed functions and initial settings required for the correct operation of the components. They are connected to each other in order to be controlled by the west or south of their blocks in order of preference. For example, MCU3702-11 will be controlled by MCU 3702-01. There is no MCU to the west of MCU 3702-01, so it is controlled by the MCU to the south of 3702-00. Correspondingly, the MCU 3702-00 located in the southwest corner has no block MCU to control it, it is the main control chip of the terminal components.

Figure 38 illustrates a simple control connection that supports this block approach with a slightly modified joint test action set - based on the MCU architecture. Each MCU has two Time Delay Integrated Inputs (TDIs), the TDI3816 on the component is on the west side and the TDIb 3814 on the MCU is on the south side. As long as the input of TDI3816 on the west side is open, it is the control chip, otherwise the TDIb 3814 on the south side is the control chip. In this schematic diagram, the block 3800 located in the southwest corner will be the master controller, and the input 3802 controlled by it will be used to control the terminal components and be transmitted to other blocks through the MCU3800. In the structural schematic diagram of FIG. 38 , the output port of the terminal component 3611 is connected with the MCU located in block 3820 in the northeast corner, and 3820 is located at the test data output of block 3822 . These MCUs and their connections will be used to register terminal component functions, perform initialization and testing, debugging, setting time, and other desired functions. Once the end unit has completed its setup and other control or initialization functions such as testing or debugging, these MCUs can be used as user functions as part of the end unit operation.

Another advantage of building a tiled field programmable gate array (FPGA) with MCUS is that it enables building a system-on-chip with embedded programmable gate array functionality. A single block 3601 can be connected to a system-on-chip using through-silicon vias - TSVs, thus creating a standalone embedded programmable gate array function.

Obviously, the same scheme can be modified to use east/north (or other combination of orthogonal directions) directions to effectively program the same priority scheme.

FIG. 11B is an alternate schematic diagram of mask locations on a wafer consisting of structured application specific integrated circuit blocks (ASICs) 1100B. Such a chip may be a contiguous array of configurable logic chips. 1102 is a potential dicing line to support the construction of various dies and logic chips. Such molds can be used as the basis for 3D systems 1202A, 1202B, 1202C or 1202D in FIG. 12 .

FIG. 11C is a schematic diagram of another mask location on a wafer consisting of random access memory (RAM) 1100C blocks. A chip may be a memory in a contiguous array. Mold blocks other than wafers may be storage mold components for 3D compositing systems. It may contain an antifuse memory layer or other form of configuration technology to act as a configurable memory die. It is possible to build through multiple memory connections, that is, through multiple connections through silicon vias to a configurable die, which can be used to configure the original memory of the storage die in a configurable system to achieve its intended function.

FIG. 11D is a schematic diagram of another mask position on a wafer composed of DRAM 1100D blocks. The chip may be a continuous array of DRAM.

FIG. 11E is a schematic diagram of another mask location on a wafer consisting of microprocessor blocks or microcontroller cores 1100E. A chip may be a contiguous array of processors.

FIG. 11F is a schematic diagram of another mask location on a wafer consisting of I/O wafer blocks 1100F, including groups of parallel switches (SerDes). A chip may be a continuous block of I/O chips. The mold block other than the wafer may be the I/O wafer mold assembly of the 3D compositing system. It may contain an antifuse layer or other forms of configuration technology such as SRAM to configure the I/O chips of the configurable I/O dies so that they function in a configurable system. It is possible to build through multiple I/O connections, that is, through multiple connections through silicon vias to a configurable die, which in a configurable system can be used to configure the original I/O die of the I/O die to achieve its intended function.

The I/O circuit is a good example, it is beneficial to use the old version to open the program. Usually program drivers are SRAM and logic circuits. It often takes a long time to perform analog functions related to I/O circuits, parallel converter circuits, phase-locked loop circuits (PLL), and other linear functions. In addition, there are benefits to using smaller transistors for logic functions. I/O chips may require stronger drivers and relatively larger transistors. Therefore, it may be more cost-effective to adopt the old code, because the chip of the old code costs less without reducing the functional effectiveness.

Another feature is that it may be beneficial to take out the programmable logic die and enter other dies in the 3D system. It is connected through silicon vias, which may be the clock circuit and its associated phase-locked loop (PLL). Dynamic connection ( DLL) circuit and control circuit, etc. PLL and distribution. These circuits are frequently used in areas and may also be demanding due to noise generation. In many cases they can be effectively implemented using legacy procedures. Clock trees and power distribution lines may be included on the I/O die. And through silicon vias (TSVs) or optical fiber means, the clock signal can be transferred to the programmable die. The technology of transferring data between molds through optical fiber has been issued to Intel Corporation as US Patent 6052498.

As an option, fiber optic clock distributors can also be utilized. There are a number of new technologies available for fabricating fiber guides on silicon or other substrates. Fiber optic clock distributors can be used to minimize the energy used for clock signal distribution and reduce distortion and noise in digital systems. On the same mold, compared with the integrated optical fiber clock distributor with logic chips in the prior art, the optical fiber clock can be built on different molds, and can be connected to digital molds through silicon vias or optical fiber, making it very practical.

Alternatively, fiber optic clock distribution auxiliary lines and potentially some supporting electronics, such as optical to electronic switching, can be achieved by utilizing a combination of storage layer migration and smart slicing as described in Figures 14 and 20. Fiber optic clock distribution auxiliary lines and some potential supporting electronics can first be built on the "base" of chip 1402, then the thin chip 1404 can be transformed using "smart dicing", so the construction of all the following primary circuits will follow. The fiber optic clock distribution auxiliary lines and supporting electronics can withstand high temperatures during the processing of the storage layer 1404 transistors.

In relation to FIG. 20 , light guides and suitable semiconductor structures (supporting electronics will be dealt with later on) are pre-established on storage layer 2019 . Using the "smart dicing" flow, it can be transferred to wafer 808 for full processing. For "smart cutting" needs, the light guide should be able to withstand ion 2008 implantation, while the supporting electronics will end up in the cycle, this situation is similar to Figs. 21 to 35, and Figs. 39 to 94. This means that the landing target of the clock signal needs to accommodate a shift of about 1 micron towards the memory layer 2004 for preprocessing - primary circuit and upper layer 808 . This displacement is acceptable in many settings. As an option, the base of the supporting electronics will be prefabricated on the storage layer 2019, and the storage layer and the final loop of the supporting electronics will be transferred before the light guide can be constructed. to 94 similar. Another option is to assemble the supporting electronics after the wafer has been processed by using a similar cycle of Figures 21 to 35, Figures 39 to 94. The optical waveguide can then be constructed at low temperature using the transfer of the memory layer on the supporting electronics.

It is precisely because of these functions of the chip that it can support the production of large-capacity non-patented products. Similar to Lego bricks, many different configurable systems can be built with a variety of logic memory and I/O chips. In addition to the alternatives shown in Fig. 11A, Fig. 11F also has many functions that can be created and incorporated into a 3D configurable system. Such as image sensor, analog, data acquisition function, optoelectronic components, non-volatile memory, etc.

Another function of the 3D system after adopting TSV is power regulation. In many cases, it can shut down part of the power of the integrated circuit when it is not in operation. When the power supply voltage of the external die may be high, it is beneficial to use the power control distributor of the external die with through-silicon vias (TSVs), because it uses the old formula. High power supply voltage can make the power distribution of the controlled mold easier and better controlled.

Components of a configurable system may be built by one or more suppliers, and the suppliers shall agree on standard specific interfaces that allow mixing and matching of molds.

3D programmable systems can be customized for general market needs or special needs of customers.

Another advantage of this patent case is that it can be mixed and matched with different programs. There are advantages to using memory for leading-edge technology programs, but I/O chips and analog function dies can be used by older programs of mature technology (as discussed above).

Figures 12A-12E illustrate an integrated circuit system, which is a schematic view of an integrated circuit system in a 3D system and in die graphics or a configurable system with multiple die options. Figure 12E shows the 3D structure sideways. A small number of molds such as 1204E, 1206E, 1208E are placed on the same base 1202E, which allows relatively smaller molds to be placed on the same master mold. For example, die 1204E may be a parallel converter die, while die 1206E may be an analog data acquisition die. Combining these dies with different programs on different wafers is better than synthesizing them on one system. When the molds are relatively small, they should be placed side by side (Fig. 12E) rather than stacked on top of each other (Fig. 12A-D).

Through silicon via technology is constantly improving. In the early days, the diameter of the via hole was 10 microns, but now it has been developed to less than 1 micron in diameter. However, the density of horizontal connections in the die using this technique is still much higher than the density of vertical connections.

Another application of the present invention is that the logical memory part is decomposed into multiple dies, the dies are equal in size, and can be integrated into a 3D configurable system. Likewise, memory can be divided into multiple dies, as can other functions.

Recent advances in 3D synthesis have demonstrated efficient ways of bonding wafers and dicing these bonded wafers. This combination will form a mold structure as shown in Figure 12A or Figure 12D. For 3D assembly technology, it may be better to have molds of different sizes. Also, decomposing logic functions into vertically synthesized dies can be used to reduce the average length of heavy-duty wires, such as clock signals, and data busses, which in turn will improve performance.

Another variation of the present invention is that the serial array is adapted (FIGS. 10 and 11) for use in general logic components or even 3D ICs. For this advanced device setup, the limitations of etching need to be considered. Therefore, a regular structure is a suitable choice, and each storage layer can be constructed in the most suitable pattern, in most cases, one orientation at a time. Among other things, highly vertically connected 3D ICs can be efficiently built by separating logic memory and I/O chips into dedicated memory layers. For only logical storage layers, the structure shown in Figure 76 and Figure 78 can be fully utilized, as illustrated in Figure 84. Thus, the circular logic pattern 8402 may be combined into a complete mask. Figure 84A illustrates a cycle pattern for the logic die of Figure 78B, which cycled 8x12 times. Figure 84B illustrates that the unified logic loops more times to fill a mask. A variety of surface molds for building logic areas can be used for multiple logic storage layers and multiple integrated circuits of 3D integrated circuits. This loop structure can include logic memory P and N transistors, their corresponding contact layers, and even landing strips connecting the base layer. The interconnection layer next to these logical areas can be customized or partially customized according to the setting, depending on the setting method. Custom metal interconnects can keep the logic area unused in the cutting line area. A scribe line mask can also be used to etch the unused transistors in the scribe line 8404, as shown in Figure 84C.

Continuous logic ranges can use any style of transistor, including those shown previously. Another advantage of some of the 3D storage layer conversion technologies mentioned above is that in order to reduce the manufacturing cost of 3D custom integrated circuits, high-capacity transistors can be constructed in advance.

Likewise, a memory range can be constructed as a fully masked continuous loop memory structure. The acyclic components of most memories can be address decoders and sometimes current sense circuits. These acyclic devices can be built using logic transistors on the underlying memory layer or on the overlying memory layer.

84D-G are schematic diagrams of static random access memory (SRAM) ranges. It illustrates six conventional transistor static random access memory (SRAM) chips (cells) 8420 controlled by word lines (WL) 8422 and bit lines (BL.BLB) 8424 and 8426, usually SRAM bit line settings Very compact.

A generic contiguous array 8430 can be a range of mask fields for a static random access memory (SRAM) bit die 8420, where transistor memory layers and even metal 1 memory layers can be used in substantially all settings. Figure 84E illustrates a contiguous array 8430 where 4x4 memory blocks are defined by etching 8434 the surrounding die. The memory can be customized through custom metal face molds such as Metal 2 and Metal 3. To control memory blocks, wordlines 8438 and bitlines 8436 can be connected by vias below or above the logic range.

FIG. 84F illustrates that a logic structure 8450 can be built on a logic scale to drive a word line 8452. FIG. 84G illustrates that a logic structure 8460 can be built on a logic range to drive a word line 8462. FIG. 84G also illustrates that the read current sense circuit 8468 can read the contents of the memory from the bit line 8462. Similarly, other memory structures can be built on and from unlicensed memory ranges close to the intended memory structure. In a similar comparison, other memories such as flash memory or dynamic random access memory (DRAM) may include memory ranges. Also, memory areas can be etched at the edge of the projected mold to define cut lines, similar to the logic areas shown in Figure 84C.

If multi-layer storage layers with different functions are used to build 3D integrated circuits, the 3D storage layers can be combined by using the storage layer transfer technology according to this invention case, and the prefabricated components can be connected by the industry standard through-silicon via technology.

Another feature of the present invention is that off-the-shelf fixes can be provided for arbitrary logic. The 3D integrated circuit technology here can use multiple logic storage layers to construct very complex logical 3D integrated circuits. In such integrated circuits, it may be desirable to repair any common defect in the manufacture of integrated circuits. Patching repeated structures is well known and commonly used in memory, see Figure 41 for this. Another point is patching arbitrary logic to provide support for current 3D IC technology and direct-write e-beam technology features, such as those provided by Advantech, Fujitsu Microelectronics, and Vistec.

Figure 86A illustrates a 3D logic IC to be repaired. It contains 3 logical storage layers 8602, 8612, 8622 and the upper storage layer 8632 to be patched. Each logic storage layer has a primary output, and the trigger circuit can be passed to the 8632. The 8632 originally contained a loop structure of unauthorized logic transistors, similar to that shown in Figures 76 and 78.

Figure 87 illustrates the flip-flop circuit set for the repairable 3D IC logic. The trigger circuit 8702 includes, in addition to the normal output 8704, a branch 8706 leading to the upper storage layer, repairing the logic storage layer 8632. For each trigger circuit, there are two wires originating from the 8632, namely patch input 8708 and control 8710. The normal input to the flip-flop circuit 8712 can be selected through a specially programmed multiplexer 8714 as long as the top level control 8710 is floating. However, the multiplexer 8714 may choose to patch the input 8708 once the top level control 8710 becomes less active. Faulty inputs may have a greater impact than major inputs. Patching restores all required logic to replace faulty inputs in similar situations.

There are also multiple options for inserting new inputs, including utilizing programmability, such as without top control line 8710, a one-time programmable component switching multiplexer 8714 from original input 8712 to desired input 8708.

In terms of fabrication, 3D IC chips can be inspected through full scan. If a defect is detected, a patch can be applied. Patching logic can be established in the upper storage layer 8632 using the configuration database. Patching logic can go to all base outputs as long as it is valid at the top storage layer. Thus, those outputs that need to be repaired can be used for reconstruction of flawed precise logic. Reconfiguration logic can enhance certain functions, such as larger drivers or stronger metal lines, to compensate for the ups and downs of long lines. Repair logic, the actual replacement for the 'cone' of faulty logic, can be built using the enabling transistors on the top memory. Top-level memory is customized by using direct write electron beams with a custom metal layer that is defined for each die on the wafer. The replacement signal 8708 can be connected to a suitable trigger circuit and made active by deactivating the top level control signal 8710 .

The patching process can also be used to enhance performance. If wafer testing includes timing, then a slow performing logical 'cone' may be replaced in a similar manner by a faulty logical 'cone' as described in the previous paragraph.

FIG. 86B is a schematic diagram of a 3D integrated circuit in which the scan chain is set so that it is limited to only one memory layer. This limitation makes each storage layer testable as it is being built, which is also useful in many ways. If the test performance is poor after the circuit layer is completed, the chip can be removed and no longer continue to build the 3D circuit layer on the poor foundation. In addition, a modular setup can be built so that the underlying transfer circuit layer contains replacement modules for the underlying fault layer, similar to the suggestion in FIG. 41 .

The inventive elements involved in Figures 86A and 86B require inspection of wafers at the manufacturing stage, and if a wafer is detected during inspection, it is relevant for fragments that are in physical contact with the inspection wafer. Accompanying drawing 86C is the case of a no-contact automatic self-test, schematic diagram. With loop antenna 86C02, RF to DC conversion circuit 86C04 and power supply unit 86C06, the non-contact power collection component can collect the electromagnetic energy on the relevant circuit, thereby generating the necessary power supply voltage to run the self-test circuit and various 3D devices to be tested IC circuit 86C08. Alternatively, use a small photovoltaic cell 86C10 to convert the beam energy into current, and then convert it to the required voltage through the power supply unit 86C06. Once the circuit is powered on, the microcontroller 86C12 can perform a full scan of all existing circuits 86C08. There are two options for self-test: full scan or BIST (built-in self-test). The test results can be transmitted to the base device outside the 3D IC wafer through the radio module 86C14. This contactless wafer inspection can be used for testing referenced in Figures 86A and 86B or for other applications such as wafer-to-wafer or die-to-wafer TSV bonding. Alternative uses of contactless detection can be applied in different combinations of the present invention. For example, the carrier wafer method can be used to produce wafer transport layers, while the transistors and the metal layers connecting them form the functional electronic circuits. These functional circuits validate proper yield through contactless detection; if possible, perform repair actions or enable internal redundancy. Then through layer transfer, the tested functional circuit layer will be transferred to another processed wafer 808, and then connected by one of the methods introduced earlier.

According to the yield recovery setup methodology, almost all of the main output signal 8706 will grow, and almost all of the main input signal 8712 will be replaced by the 8708 signal from the top.

An additional advantage of the yield recovery setup methodology is the ability to reuse logic layers between one setup and another. For example, one layer of the 3D IC system contains a WiFi transceiver, and this circuit is required by a completely different 3D IC. Therefore, it is very beneficial to reuse the same WiFi transceiver in the new configuration, only by using the receiver as one of the new 3D IC configuration layers to achieve the purpose of not having to reset and save NRE (one-time cost) such as masks . The principle of re-use can also be applied in many other functions, making 3D ICs trend towards the old-fashioned bonding function, ie PC (printed circuit) boards. In order to ensure the smooth implementation of this concept, the ideal way is to develop a connectivity standard suitable for connecting up and down lines.

Other applications of these concepts include using upper layers to adjust the clock of the actual device and its various manufacturing components for the purpose of modifying the timing of the clock. The scan circuit can be used to measure the clock skew and report it to an external setting tool. The external setting tool can perform timing modification under the application of the clock modification circuit, and then use the direct-reading electron beam to form the transistor and the upper circuit, so that through the clock modification, the better yield and performance level of 3D IC terminal products can be achieved.

Another way to increase the yield of complex systems with 3D structures is to duplicate the same setup on two superimposed layers and use the same BIST setup technique as described above for identifying and replacing abnormal logic cones. This should demonstrate that the use of one-time or irreversible repair structures such as antifuse or direct-reading dedicated electron beams at the production stage can be very effective in repairing large numbers of ICs, even at low yields. With the memory-based repair structure described below in Figure 114, the same repair method is also available, per power-up sequence (power-up sequence)? Helping systems that need self-healing capabilities.

Figure 114 is a schematic illustration of a possible example of this concept. The two logical layers 11401 and 11402 superimposed on top of each other basically adopt the same setting. This setup (the same for all layers) is based on scans, and each layer 11451 and 11452 that communicates directly or through an external tester contains a BIST controller/checker. 11421 is a representative flip-flop (FF) on the first layer, and there is a corresponding FF 11422 on the second layer, which are respectively fed by the same logic cones (logic cones) 11411 and 11412. The output of flip-flop 11421 is coupled to the A input of multiplexer 11431 and the B input of multiplexer 11432 via vertical connection 11406, while the output of flip-flop 11422 is coupled to the A input of multiplexer 11432 and multiplexed via vertical connection 11405. The B input of device 11431. Each output multiplexer is individually controlled from control points 11441 and 11442, and the multiplexer output drives the respective next logic stage below each layer. Therefore, whether it is the logic cone 11411 and the flip-flop 11421 or the logic cone 11412 and the flip-flop 11422, it is programmatically or selectively coupled to the next logic stage under each layer.

Multiplexer control points 11441 and 11442 are implemented using memory chips, antifuses or any other custom parts such as wires for Direct-Write e-Beam machines. If a memory chip is used, its contents can be stored in ROM, flash memory or other non-volatile storage media, or stored in 3D IC or distributed when the system is turned on, reset or system maintenance request, and loaded into the in the content system.

Once turned on, the BCC initializes all multiplexer control programs to select input A and run diagnostic tests on each layer setting. Identify fault triggers (FFs) on each logical layer through scanning and BIST techniques. As long as a pair of corresponding FFs do not fail at the same time, the BCCs can communicate with each other (directly or through an external tester) to determine which is running Good FF use, and set the multiplexer control program 11441 and 11442.

If the multiplexer control programs 11441 and 11442 are reprogrammable by the memory chip, then the test and repair process can occur every turn-on or request, thereby realizing the self-healing of the 3D IC in the circuit. If the multiplexer control program can only be programmed once, then the diagnosis and repair process needs to be realized through external equipment. Note that the no-contact test and repair technique described above in Figure 86C can be applied in this case.

Another example of this concept: Multiplexing 8714 is employed at the FF input depicted in FIG. 87 . In that case, both the Q of the FF and the reverse Q can be used, if present.

Those skilled in the art know that this method of repairing one of two almost identical parts superimposed on top of each other can be applied to other parts except the above-mentioned FF. Examples include, but are not limited to, analog blocks, I/O, memory, and other components. In this case, the selection of the job output requires a special multiplexing technique (multiplexing technique), but the essence of the technique remains the same.

Those skilled in the art will also appreciate that once the BIST diagnostics for both layers are complete, the same mechanism used to determine the multiplexer control program can also be used to selectively power down unused portions of the logic layer, thereby saving power consumption.

But another difference of the present invention is that vertical stacking is used in fly (rapid) repair by means of redundancy concepts such as triple-mode (or higher) redundancy ("TMR"). TMR is a well-known concept in the high-dependency industry, where three copies of each circuit are produced, and their outputs pass through the majority-voting circuit. As long as no more than one single fault occurs in the TMR module, the TMR system continues to operate without faults. One of the main problems when setting up a TMR IC is that when the circuit is tripled, the interconnection becomes much longer which slows down the system operation, and the routing becomes more complicated, which slows down the progress of the system set-up. Another major problem with TMR is that the setting process is expensive due to the larger setting size, and the market is limited.

Vertical stacking provides a natural solution for duplicating the mapping of each top system. Figure 115 illustrates a system with three layers 11501 11502 11503 where combinational logic is replicated in logic cones 11511-1, 11511-2 and 11511-3 and FF is replicated in 11521-1, 11521-2 and 11521- 3. One of the tiers 11501 in this section contains majority voting circuitry 11531 which decides between the local FF output 11661 and the vertically stacked FF outputs 11552 and 11553, resulting in an -3 etc. Final fault tolerant FF output for all logical layers.

Those skilled in the art will appreciate that configuration changes are possible, such as assigning an independent layer to the voting circuit so that the layers 11501, 11502, and 11503 are logically consistent; relocating the voting circuit to the input of the FF instead of on output; or extend redundant replication to at least 3 more times (and overlays).

The above-mentioned methods for setting triple-mode redundancy (TMR) all mention the above-mentioned disadvantages at the same time. First, because of the existence of TMR, there is basically no additional routing congestion in each layer, and the settings of each layer can be optimally implemented in a single mapping instead of a triple mapping. Second, by vertically stacking the three original maps and adding a majority voting circuit on any, all three, or a separate layer in Figure 115, any setup implemented in a non-highly dependent market can be implemented with minimal Efforts to realize the setting conversion of TMR. TMR circuits can be shipped from the factory with known existing errors (TMR redundancy masking) or with the addition of a repair layer to repair any known errors, thus ensuring higher dependencies.

The cases discussed so far have mainly involved yield improvement and factory repair issues before shipping 3D ICs to customers. Another aspect of the present invention is to provide redundancy and self-healing when distributing 3D ICs in production rates. This is a desirable product feature because even if it works flawlessly in the factory, defects can still appear in inspected products. For example, the defect cause may be a delayed failure mechanism, such as a faulty gate dielectric of a transistor that evolves into a short circuit problem between the gate and the source, drain or base of the underlying transistor. After assembly, the transistors are tested to operate without error at the factory, but with time and applied voltage and temperature, defects can evolve into failures, which can be found in subsequent field tests. Many other delay failure mechanisms are known. Leaving aside the defective nature of the delay, if it introduces a logic error in the 3D IC, it can be detected and repaired using subsequent testing in accordance with the present invention.

According to the example of the present invention, accompanying drawing 119 illustrates the 3D IC indicated by 11900. The 3D IC 11900 includes two layers, respectively denoted as layer 1 and layer 2, which are distinguished by dotted lines in the drawings. Layer 1 and Layer 2 can be bonded into a 3D IC by methods known in the art. Signals between layer 1 and layer 2 can be electrically coupled through through silicon via technology (TSV) or other interlayer technologies. Layers 1 and 2 each contain a semiconductor device layer, called a transistor layer, and its associated interconnections (implemented in one or more physical metal layers) are called interconnect layers. A transistor layer and one or more interconnect layers are called circuit layers. Layer 1 and Layer 2 may each include one or more circuit layers of devices and interconnects, depending on the setup.

Although there are differences in the structural details, Layer 1 and Layer 2 in the 3D IC 11900 generally employ the same logic functions. In some cases, layer 1 and layer 2 are individually encapsulated using the same mask as all layers to reduce production costs. In other cases, however, one or more of the mask layers still has a slight deviation. For example, there is still a choice for one logic layer to generate different logic signals on each layer, which tells the control logic blocks on layers 1 and 2 of the fact that they are layers 1 and 2 in their respective importance. 2 layer controller. Other differences between layers exist depending on the setting.

Tier 1 contains control logic 11910, representative scan flops 11911, 11912, and 11913, and representative combinatorial logic clouds 11914 and 11915, while tier 2 contains control logic 11920, representative scan flops 11921, 11922, and 11923, and representative Logic Cloud 11924 and 11925. Control logic 11910 and scan flip-flops 11911, 11912 and 11913 are coupled together to form a scan chain to group scan test combinatorial logic clouds 11914 and 11915 in the manner described above. The control logic 11920 and the scan flip-flops 11921 , 11922 and 11923 are also coupled together to form a scan chain to group scan test combinatorial logic clouds 11924 and 11925 . Control logic blocks 11910 and 11920 are coupled together to coordinate testing performed on the two layers. In some cases, control logic blocks 11910 and 11920 may test themselves or each other. If one fails, the other can also control the tests performed on layers 1 and 2.

Those of ordinary skill in the art will be pleased to see that the representative features of the scan chains in Figure 119 are based on the premise that millions of flip-flops form multiple scan chains in actual settings, and that the principles of the invention disclosed herein apply, Unaffected by the size and range set.

As in the previous case, the layer 1 and layer 2 scan chains can be used for different test purposes in the factory. For example, Layer 1 and Layer 2 may each have an associated repair layer (not shown in FIG. 119 ) for correcting defective logic cones or logic blocks. Alternatively, layers 1 and 2 share a restoration layer.

Figure 120 illustrates a typical scan flip-flop 12000 (in the dashed box in the figure) suitable for some cases of the present invention. Scan flip-flop 12000 is used for scan flip-flops 11911, 11912, 11913, 11921, 11922, and 11923 in FIG. 119 . In Figure 120 is D flip-flop 12002 which has a Q output coupled to the Q output of scan flip-flop 12000 and a D input coupled to the output of multiplexer 12004, and a clock input coupled to the CLK signal. Multiplexer 12004 also has a first data entry coupled to the output of multiplexer 12006, a SI (scan in) input coupled to scan flip-flop 12000, and a select input coupled to the SE (scan on) signal. Multiplexer 12006 also has first and second data entries coupled to the D0 and D1 inputs of scan flip-flop 12000, and a select input coupled to the LAYER_SEL signal.

The SE, LAYER_SEL and CLK signals are not shown coupled to the inputs of the scan flip-flop 12000 to avoid over-complicating the disclosure - especially a drawing like Figure 119 where multiple instances of the scan flip-flop 12000 show and clearly the wiring would To divert attention from the idea being expressed. In a practical setup, all three signals are typically coupled into each respective circuit of scan flip-flop 12000.

When asserted, the SE signal puts the scan flip-flop 12000 in scan mode causing the gate of the multiplexer 12004 to control the SI input to the D input of the D-type flip-flop 12002 . Since this signal is diverted to all scan flip-flops 12000 in the scan chain, they are connected together to form a shift register, so that vectors are shifted in and test results are shifted out. The multiplexer 12004 selects the output of the multiplexer 12006 to the D input of the D flip-flop 12002 when SE is indeterminate.

The CLK signal appears as an "internal" signal because its starting point will vary from case to case due to a matter of setting choice. In a practical setup, a clock signal (or variants thereof) is specially routed to each flip-flop in its functional domain. In some scan test general structures, the third multiplexer (not shown in FIG. 120 ) will select CLK from the domain clock during function operation; during scan test, it will select from the scan clock. In these cases, the SCAN_EN signal will be specifically coupled to the select input of the third multiplexer so that the D-type flip-flop 12002 can be clocked correctly in both scan and function modes. In other scan overall structures, the scan clock is in test mode using the functional domain clock without additional multiplexers. Those of ordinary skill in the art appreciate that many different scan profiles are known, and recognize that the particular scan profile in any given case will be a matter of setting choice and not limiting of the present disclosure.

The LAYER_SEL signal determines the data source of the scan flip-flop 12000 in normal operation mode. As shown in FIG. 119, the input D1 is coupled to the output of the logic cone of a certain level (level 1 or level 2) where the scan flip-flop 12000 is located, and the input D0 is coupled to the output of the corresponding logic cone of the other level. The default value of LAYER_SEL is logical value -1, which selects the output of the same layer. Each scan flip-flop 12000 has its unique ALYER_SEL signal. This enables a defective logic cone on one layer to undergo programmable or selective replacement of its corresponding cone on another layer. In this case, the signal coupled to D1 that is replaced is called the fault signal, and the signal coupled to D0 that replaces it is called the repair signal.

FIG. 121A illustrates a typical 3D IC, indicated generally at 12100. Like the case in Figure 119, the 3D IC 12000 includes two layers, respectively denoted as layer 1 and layer 2, which are distinguished by dotted lines in the drawing. Layer 1 contains 1st logic cone 12110 , scan flip-flop 12112 and XOR gate 12114 , while layer 2 contains layer 2 logic cone 12120 , scan flip-flop 12122 and XOR gate 12124 . Scan flip-flop 12000 in FIG. 120 can be used for scan flip-flops 12112 and 12122, although SI and other internal connections are not shown in FIG. 121A. The output of the logic cone 12110 of the first layer (indicated by DATA1 in the figure) is respectively coupled to the D1 input of the first layer scan flip-flop 12112 and the D0 input of the second layer scan flip-flop 12122 . Similarly, the output of the logic cone 12120 of the layer 2 (indicated by DATA2 in the figure) is coupled to the D1 input of the layer 2 scan flip-flop 12122 and the D0 input of the layer 1 scan flip-flop 12112, respectively. Scan flip flops 12112 and 12122 each have their own LAYER_SEL signal (not shown in FIG. 121A ) that selects between the D0 and D1 inputs in the same manner as illustrated in FIG. 120 .

XOR gate 12114 has a first input coupled to DATA1, a second input coupled to DATA2 and an output coupled to signal ERROR1. Likewise, XOR gate 12124 has one input coupled to DATA2, a second input coupled to DATA1 and an output coupled to signal ERROR2. If the logic values of the signals on DATA1 and DATA2 are different, ERROR1 and ERROR2 will take logic value -1, indicating that there is a logic error. If the logic values of the signals on DATA1 and DATA2 are the same, ERROR1 and ERROR2 will take a logic value of -0, indicating that there is no logic error. Those skilled in the art know that the assumption implied here is that only one of the logic cones 12110 and 12120 will be broken at the same time. Now that tier 1 and tier 2 have been factory tested, validated and in some cases repaired, the statistical similarity of two logic cones that failed in the field, even without any factor repair, is impossible, thus confirming this hypothesis.

In 3D IC 12100, visual setting selection needs to be tested in many different ways. For example, the clock is stopped suddenly, and the status of the ERROR1 and ERROR2 signals is monitored in a spot check during the system maintenance phase. Alternatively, abort the run and run through the vectors according to the alignments made for each vector. In some cases, a linear feedback shift register commonly used in BIST test schemes is used to generate pseudo-random vectors for cyclic redundancy checks. These methods all involve stopping the system and entering test mode. Other methods of real-time monitoring of possible error conditions are discussed below.

In order to achieve the repair of 3D IC 12100, two determinations were made: (1) the position of the faulty logic cone, and (2) which of the two corresponding logic cones worked correctly at that position. Therefore, although there are other methods, the monitoring method of the ERROR1 and ERROR2 signals and the control method of the trigger 12112 and 12122 LAYER_SEL signals are still used. In a practical case, the method of reading and writing the state of the LAYER_SEL signal is needed for factory testing to prove that both layer 1 and layer 2 are functioning correctly.

In particular, the LAYER_SEL signal of each scan flip-flop can be stored in the programmable chip, for example, the volatile memory circuit is like a latch to store a bit of binary data (not shown in FIG. 121A ). In some cases, the correct value of each programmable chip or latch can be determined at system start-up, system reset or request as a routine part of system maintenance. Alternatively, the correct value of each programmable chip or latch can be determined earlier and stored in a non-volatile medium such as flash memory or saved through a programmable antifuse inside the 3D IC 12100, or These values may also be stored elsewhere in the system where the 3D IC 12100 is distributed. In those cases, the data stored on the non-volatile media can be read from its storage location and written to the LAYER_SEL latch in some way.

It is possible to use different ERROR1 and ERROR2 monitoring methods. For example, ERROR1 and ERROR2 values could be captured by separate shift register chains (not shown in Figure 121A) on each layer, although this would incur a large area penalty. Alternatively, the ERROR1 and ERROR2 signals may be coupled to scan flip-flops 12112 and 12122 (not shown in FIG. 121A ), respectively, captured and shifted out in test mode. This may reduce scan flip flop manufacturing costs, but is still expensive.

If the necessary circuit for reading and writing the latch for storing the LAYER_SEL information is matched, the monitoring cost of the ERROR1 and ERROR2 signals can be further reduced. In some cases, for example, a LAYER_SEL latch can be coupled to a corresponding scan flip-flop 12000 and read and write its value through the scan chain. Alternatively, logic cones, scan flip-flops, XOR gates and LAYER_SEL latches can be addressed by using the same addressing circuit.

FIG. 121B is a schematic circuit diagram of monitoring ERROR2 and controlling its related LAYER_SEL latch through addressing in 3D IC 12100. FIG. 121B includes 3D IC 12100 , a portion of the layer 2 circuitry discussed in FIG. 121A , including scan flip-flops 12122 and XOR gates 12124 . Level 1 contains substantially identical circuitry (not shown in FIG. 121B ) involving scan flip-flops 12112 and XOR gates 12114 .

Figure 121B also includes LAYER_SEL latch 12170, which is coupled to scan flip-flop 12122 via the LAYER_SEL signal. The data value stored in latch 12170 determines which cone of logic will be used by scan flip flop 12122 during normal operation. Latch 12170 is coupled to COL_ADDR line 12174 (column address line), ROW_ADDR line 12176 (row address line) and COL_BIT line 12178 . These lines read and write the contents of latch 12170 in the same manner as any SRAM circuit known in the art. In some cases, there will be a complementary COL_BIT line with inverted binary data (not shown in Figure 121B). In the logic setting, whether it is a full-custom setting, a semi-custom setting, a gate array, an ASIC setting or other setting methods, the scan flip-flops are not neatly arranged in rows like the way memory chips are used in the storage area. In some cases, the scan flip-flops can be assigned by the tool to dummy rows for addressing purposes, and then the different dummy rows will be routed in the same way as any other signal in the setup.

Using a circuit comprising N-type pass transistors 12182, 12184, 12186 and P-type pass transistors 12190 and 12192, ERROR2 line 12172 can be read at the same address as latch 12170. N-type pass transistor 12182 includes a gate terminal coupled to ERROR2 line 12172 , a source terminal coupled to ground, and a drain terminal coupled to the source of N-type pass transistor 12184 . N-type pass transistor 12184 includes a gate terminal coupled to COL_ADDR line 12174 , a source terminal coupled to N-type pass transistor 12182 , and a drain terminal coupled to the source of N-type pass transistor 12186 . N-type pass transistor 12186 includes a gate terminal coupled to ROW_ADDR line 12176, a source terminal coupled to N-type pass transistor 12184 drain, and a P-type pass transistor 12190 drain and P Type pass transistor 12192 gate drain terminal. P-type pass transistor 12190 includes a gate terminal coupled to ground, a source terminal coupled to the positive power supply, and a drain terminal coupled to line 12188 . P-type pass transistor 12192 includes a gate terminal coupled to line 12188 , a source terminal coupled to the positive power supply, and a drain terminal coupled to COL_BIT line 12178 .

If the ERROR2 dedicated line 12172 in the accompanying drawing 121B is not addressed (that is, either the COL_ADDR line 12174 is equal to the ground voltage level (logic value-0)), or the ROW_ADDR line 12176 is equal to the voltage level of the ground voltage supply (logic value-0) 0), then the transistor stack comprising three N-type pass transistors 12182, 12184 and 12186 is non-conductive. When the N-type pass transistor stack is non-conductive, then as a weaker pull-up component, the P-type pass transistor 12190 will pull the voltage level on the line 12188 to the positive supply voltage (logic value -1 ), so that the P-type pass transistor 12192 is non-conductive and brings high impedance to the COL_BIT line 12178.

A weaker pull-down component (not shown in FIG. 121B ) is coupled to COL_BIT line 12178 . When all memory chips coupled to the COL_BIT line 12178 exhibit high impedance, the pull-down component pulls the voltage level to ground (logic value -0).

If the particular ERROR2 line 12172 in FIG. 121B is addressed (i.e., COL_ADDR line 12174 and ROW_ADDR line 12176 are at a positive supply voltage level (logic value -1)), then three N-type pass transistors 12182, 12184, and 12186 are included The transistor stack does not conduct when the logic value of ERROR2 is -0, and conducts when the logic value of ERROR2 is -1. In this way, the logic value of ERROR2 can be propagated to COL_BIT line 12178 through P-type pass transistors 12190 and 12192.

One advantage of the addressing scheme of FIG. 63B is that by synchronous addressing of rows and columns, and monitoring of all column bit lines 12178, a broadcast ready mode can be achieved. When all column bit lines 12178 are logic-0, all ERROR2 signals are logic-0, indicating that there are no broken logic cones on layer 2. With relatively few field correctable errors, a large amount of error location time can be saved by using the scan flip-flop approach. If one or more bit lines are logic-1, then faulty logic cones will only exist on those columns, and the row addresses will quickly cycle through to find their exact addresses. Another advantage of this scheme is that in enable or reset mode, a large number or all LAYER_SEL latches can be quickly initialized to the default value logic-1 at the same time.

At each location where a faulty cone of logic (if any) exists, the defect is isolated to a specific layer so that a correctly functioning cone of logic can be triggered by the corresponding scan flip-flops located on layers 1 and 2 choose. If there is a large non-volatile memory in the 3D IC 12100 or in an external system, then automatic test pattern generation (ATPG) vectors are applied in the same way as in the factory repair case. In this case, the scan itself has the ability to determine the location and run the layers correctly. Unfortunately, this scan requires a large number of vectors and considerable non-volatile memory, which is not available in all cases.

The advantage of using some form of built-in self-test (BIST) method is that it is embedded in the 3D IC 12100 without the need to store a large number of test vectors. Unfortunately, BIST testing tends to be a "pass" or "fail" judgment, knowing that an error exists but not being particularly good at diagnosing the location or nature of the failure. Fortunately, the correct value of the LAYER_SEL latch can be quickly determined by combining the BIST technology and the corresponding setting method in the above error signal monitoring process.

Accompanying drawing 122 is an example adopted in 3D IC, refer to the schematic diagrams of typical logic settings such as 11900 in accompanying drawing 119 and 12100 in accompanying drawing 121A. Logical settings can be seen on Tier 1 and Tier 2 with roughly the same gate-level cases. Preferably, all flip-flops (not shown in FIG. 122 ) in the setup use scan flip-flops similar or identical to scan flip-flops 12000 in FIG. 120 . Preferably, all scan flip-flops on each layer have a certain degree of interconnection with the corresponding scan flip-flops on another layer, which is described in conjunction with FIG. 121A. Preferably, each scan flip-flop is equipped with an associated error signal generator (such as an XOR gate) to detect the presence of an error logic cone and the LAYER_SEL register to control which logic cone is fed to the flip-flop in normal operation mode, combined with Figures 121A and 121B are presented together.

An exemplary logic function block (LFB) 12200 is shown in Figure 122 . Typically, an LFB 12200 has many inputs, case ref 12202, and many outputs, case ref 12204. Preferably, the LFB 12200 is set in a hierarchical manner, indicating that it has specific smaller logic function blocks, specified as 12210 and 12220 in the text. The internal circuits of LFBs 12210 and 12220 are considered to be at lower levels of the hierarchy compared to the circuitry at the top level of LFB 12200 which is considered to be at a higher level of the hierarchy. LFB 12200 is for example only. Many other configurations are also possible. Inside the LFB 7500, there are at least (at most) two initialized LFBs. Also inside the LFB 12200 which is not shown in Figure 122, there will also be separate logic gates for initialization and other circuits to avoid over-complicating the disclosure. The LFB12210 and 12220 have internally initialized smaller modules that form even lower levels in the hierarchy. Likewise, the Logical Function Block 12200 itself may also be initialized in another LFB at an even higher level in the overall settings hierarchy.

The LFB 12200 includes a Linear Feedback Shift Register (LFSR) circuit 12230 that generates pseudo-random input vectors for the LFB 12200 by techniques well known in the art. In FIG. 122 , one bit LFSR 12230 is associated with each input 12202 of LFB 12200 . If the input 12202 is directly coupled to a flip-flop (preferably a scan flip-flop similar to the 12000), then the scan flip-flop can be modified to have the additional LFSR capability to generate pseudo-random input vectors. If input 12202 is directly coupled to combinational logic, it is intercepted in test mode and its value is determined and replaced by a corresponding bit in LFSR 12230 during test. Alternatively, the LFSR circuit 12230 will intercept all input signals during testing regardless of the type of circuit it is connected to the internal LFB 12200.

Therefore, in the BIST test, all inputs of LFB 12200 can use pseudo-random input vectors generated by LSFR 12230. As known in the art, LSFR 12230 can be a single LSFR or multiple smaller LSFRs, depending on the setting chosen. LSFR 12230 preferably uses a primitive polynomial to generate a pseudorandom vector of maximum length sequence. LSFR 12230 needs to be seeded to a known value so that the sequence of pseudorandom vectors is deterministic. The seeding logic can be cheaply implemented inside the LSFR 12230 flip-flop and initialized by responding to reset signals etc.

LFB 12200 also includes cyclic redundancy check (CRC) circuitry 12232 to generate pseudo-random input vectors in response to LFSR 12230 , in a manner well known in the art, to generate characteristics of LFB 12200 output. In FIG. 122, a one-bit CRC 12232 is associated with each output 12204 of the LFB 12200. If the output 12204 is directly coupled to a flip-flop (preferably a scan flip-flop similar to the 12000), then the scan flip-flop can be modified to have the additional CRC function to generate the signature. Alternatively, all bits of the CRC will passively monitor the output regardless of the signal source inside the LFB 12200.

Therefore, in the BIST test, all the outputs of the LFB 12200 can be analyzed to determine the correctness of the stimulus generated in response to the pseudo-random input generated by the LSFR 12230. According to this technology, CRC 12232 can be a single CRC or multiple smaller CRCs, depending on the setting selection. According to this technology, the CRC circuit is a special case of LSFR, and its additional circuit can incorporate the observed data into the pseudo-random code sequence generated by the base LSFR. CRC 12232 preferably uses a primitive polynomial to generate a maximum sequence pseudo-random code. CRC 12232 needs to be seeded to a known value so that the characteristics of the pseudo-random input vector generation are deterministic. The seeding logic can be cheaply implemented inside the LSFR 12230 flip-flop and initialized by responding to reset signals etc. After the test is complete, compare the value in CRC 12232 with the known value of the characteristic. If all bits in the CRC 12232 match, the identification is valid and the LFB 12200 is considered to be operating without error. If one or more bits in the CRC 12232 do not match, the identification is invalid and the LFB 12200 is considered to be malfunctioning. The value of the expected characteristic can be taken cheaply inside the CRC 12232 flip-flop and compared internally with the CRC 12232 responding to an evaluation signal.

As shown in FIG. 122 , LFB 12210 includes LFSR circuit 12212 , CRC circuit 12214 and logic function 12216 . Since its input/output structure is similar to that of LFB 12200, it can be tested in the same way with a smaller scale. If the 12200 is initialized as a larger block with the same input/output structure, the 12200 can be tested as part of that larger block or independently, depending on the setup selection. All blocks in the hierarchy do not necessarily have to have an input/output structure, if there is no need for individual testing. An example is where the LFB 12220 is initialized in the LFB 12200, and the LFB 12220 has no LFSR circuit on the input, no CRC circuit on the output, and is tested at the same time as the rest of the LFB 12200.

Those of ordinary skill in the art will appreciate that other BIST testing methods are known in the art, and that either method can be used to determine whether the LFB 12200 is functioning properly or failing.

To repair a 3D IC like 3D IC 12100 in Figure 121A by using the block BIST method, place the part in test mode, compare the DATA1 and DATA2 signals of each scan flip-flop 12000 on layer 1 and layer 2, and Monitor ERROR1 and ERROR2 composite signals as described in the case above, or use other methods where possible. The location of the failure logic cone is determined by its position in the logic setting hierarchy. For example, if the cone of fault logic is inside LFB 12210, then only the BIST program for that block can run on both layer 1 and layer 2. The results of the two tests determine which block (and, by implication, which cone of logic) is functioning well and which block is functioning with obstacles. Then the LAYER_SEL latch of the corresponding scan flip-flop 12000 can be set, so that each latch can receive the repair signal from the functional logic cone, and ignore the fault signal, so that in the short term without expensive ATPG test, Complete the layer determination of common hardware cost.

Figure 123 presents an optional example of field repair capability with independent logic cones. A typical 3D IC, indicated at 12300, contains two layers, indicated as layer 1 and layer 2, which are distinguished by dotted lines in the figure. Layer 1 and Layer 2 are bonded together to form 3D IC 12300 using methods known in the art and are interconnected by TSV or other interlayer interconnect technology. The first layer consists of control logic block 12310 , scan flip-flops 12311 and 12312 , multiplexers 12313 and 12314 , and logic cone 12315 . Likewise, layer 2 consists of control logic block 12320 , scan flip-flops 12321 and 123222 , multiplexers 12323 and 12324 and logic cone 12325 .

In layer 1, scan flip-flops 12311 and 12312 are coupled in series with control logic block 12310 to form a scan chain. Scan flip-flops 12311 and 12312 may be a common type of scan flip-flop known in the art. The Q outputs of scan flip-flops 12311 and 12312 are coupled to the D1 data entry of multiplexers 12313 and 12314, respectively. A typical cone of logic 12315 has one output coupled to a typical input of a multiplexer 12313 and another output coupled to the D input of a scan flip-flop 12312.

In layer 2, scan flip-flops 12321 and 12322 are coupled in series with control logic block 12320 to form a scan chain. Scan flip-flops 12321 and 12322 may be a common type of scan flip-flop known in the art. The Q outputs of scan flip-flops 12321 and 12312 are coupled to the D1 data entry of multiplexers 12323 and 12324, respectively. A typical cone of logic 12325 has one output coupled to a typical input of a multiplexer 12323 and another output coupled to the D input of a scan flip-flop 12322.

The Q output of scan flip-flop 12311 is coupled to the DO input of multiplexer 12323, the Q output of scan flip-flop 12321 is coupled to the DO input of multiplexer 12313, and the Q output of scan flip-flop 12312 is coupled to the multiplexed The D0 input of flip-flop 12324 and the Q output of scan flip-flop 12322 are coupled to the DO input of multiplexer 12314. Control logic block 12310 is coupled to control logic block 12320 in a manner that coordinates interlayer test functions. In some cases, the control logic blocks 12310 and 12320 can test themselves or each other, and when one fails, the other can also control the testing on both layers. These interlayer couplings can be achieved through TSVs or other interlayer interconnect technologies.

The logical functions on layer 1 are roughly the same as those on layer 2. The case of 3D IC 12300 in accompanying drawing 123 is similar to the case of 3D IC 11900 in accompanying drawing 11900, the main difference is: in the typical scan flip-flop 12000 of accompanying drawing 120 and the 3D IC 11900 of accompanying drawing 119, for logic The interlayer programmable or selective cross-coupling multiplexer for cone replacement is located immediately after the scan flip-flops instead of before them.

Accompanying drawing 124 is a schematic diagram of a typical 3D IC represented by 12400, which is also constructed by this method. A typical 3D IC 12400 includes two layers, respectively denoted as layer 1 and layer 2, which are distinguished by dotted lines in the drawing. Layer 1 and Layer 2 are bonded together to form 3D IC 12300 and interconnected by TSV or other interlayer interconnection technology. Level 1 consists of Level 1 logic cones 12410 , scan flip flops 12412 , multiplexers 12414 and XOR gates 12416 . Likewise, layer 2 consists of layer 2 logic cones 12420 , scan flip flops 12422 , multiplexers 12424 and XOR gates 12426 .

Level 1 logic cones 12410 and level 2 logic cones 12420 perform substantially the same logic functions. To detect faulty logic cones, the outputs of logic cones 12410 and 12420 are captured in test mode in scan flip-flops 12412 and 12422, respectively. The Q outputs of scan flip flops 12412 and 1262 are denoted Q1 and Q2, respectively, in FIG. 124 . Q1 and Q2 are compared by XOR gates 12416 and 12426 to generate error signals ERROR1 and ERROR2 respectively. Multiplexers 12414 and 12424 each have a select input coupled to a layer select latch (not shown in FIG. Relatively within close range, Q1 and Q2 are selectively or programmable coupled to DATA1 or DATA2.

According to the cases described in accompanying drawings 121A, 121B and 122, all ERROR1 and ERROR2 evaluation methods can be used to evaluate ERROR1 and ERROR2 in accompanying drawing 124. Likewise, once ERROR1 and ERROR2 are evaluated, the correct values can be applied to the layer select latches of multiplexers 12414 and 12424, enabling logic cone replacement, if necessary. In this case, the cone of logic substitution also contains the substitution-associated scan flip-flop.

Accompanying drawing 125A provided is a typical case that adopts more economical method to realize on-site restoration. A typical 3D IC 12400 denoted by 12500 includes two layers, respectively denoted as layer 1 and layer 2, which are distinguished by dotted lines in the figure. Layer 1 and Layer 2 each include at least one circuit layer. Layer 1 and Layer 2 are bonded together to form 3D IC 12500 by methods known in the art and interconnected by TSV or other interlayer interconnection technology. Each layer also contains a logic function block 12510 instance, and each case in turn constitutes a logic function block 12520 instance. LFB 12520 includes LSFR circuitry on its input (not shown in FIG. 125A ) and CRC circuitry on its output (not shown in FIG. 125A ), in a manner similar to that described for LFB 12200 in FIG. 122 .

Each instance of LFB 12520 has many, multiplexers 12522 associated with inputs, and multiplexers 12524 associated with outputs. And these multiplexers can be programmed or selectively replaced with the corresponding parts on the first layer or the second layer, all cases of LFB 12520 on the first layer or the second layer.

Different blocks in the hierarchy can be tested upon power-up, system reset, or request from the control logic inside the 3D IC 12500, or elsewhere in the system where the 3D IC 12500 is distributed. A faulty block at any level of the hierarchy, and BIST-capable, can be programmed and selectively replaced by a corresponding case at another level. Since it is determined at the blocking level, this decision can be made locally by the BIST control logic on each block (not shown in Figure 125A), although higher level blocks in the hierarchy still need to be coordinated, most Multiplexer 12522 provides input to which level of functional LFB 12520 in case of multiple repairs within the same range in the hierarchy. Since layers 1 and 2 are preferably fully or nearly fully operational when shipped, a simple method can be used to designate one of the two layers, such as layer 1, as the primary functional layer. The BIST controller of each block then coordinates locally and decides which block has the input and output of layer 1 coupled to via layer 1 multiplexers 12522 and 12524.

Those of ordinary skill in the art know that adopting this case can save a lot of space. For example, since only the LFB has been evaluated due to the replacement of independent logic cones, then each of the separate flip-flop levels between multiplexer 12006 in Figure 120 and multiplexer 12414 in Figure 124, select the multiplexer Can be removed together with LAYER_SEL latch 12179 in FIG. 121B, because this function is now performed by multiplexers 12522 and 12524 in FIG. 125A, all multiplexers can be controlled by one or more in parallel signal to control. Likewise, error signal generators (such as XOR gates 12114 and 12124 in FIG. 121A and 12416 and 7826 in FIG. 124 ) and any circuitry that needs to read them (such as coupling them to scan flip-flops), or The addressing circuit in Figure 121B should also be removed, since in this case the entire logic functional block, rather than the individual logic cones, is replaced.

Even scan chains can be removed in some cases, although this is a matter of configuration choice. In cases where the scan chains are removed, factory testing and repair must also rely on block BIST circuitry. When the detection finds a bad block, the repair layer must use the electron beam to calmly make a brand new block. In particular, since there are more patterns to be formed, it is more time consuming than making alternative logic cones, and the space savings need to be compared with the test time loss to determine an economically viable solution.

Removing the scan chains comes with the risk of setting up the early debug and prototyping stages, as the BIST circuitry is still limited in diagnosing the nature of the problem. If there is a problem with the setting itself, the absence of scan testing will increase the difficulty of finding and solving the problem, and the cost of losing market opportunities is very huge and difficult to quantify. For reasons unrelated to the field repair aspect of the present invention, it is prudent to prompt to leave the scan chain.

Another advantage of the case of using the block BIST approach is described in Figure 125B. One advantage of some of the earlier cases was that most of the circuitry on layer 1 and layer 2 was active during normal operation. Thus by operating only one block case located on one of the two layers, the power can be reduced considerably for the earlier case.

Figure 125B includes 3D IC 12500, Layer 1 and Layer 2, 2 instances each of LFB 12510 and 12520, and multiplexers 12522 and 12524 as previously discussed. Each layer of Figure 125B also includes a power selection multiplex rate 12530 associated with the mode LFB 12520 of that layer. Each power select multiplexer 12530 has an output coupled to the power terminal of its associated LFB 12520, with a first select input coupled to a positive supply (indicated as VCC in the figure), and a second input coupled to a ground potential supply (Denoted by GND in the attached figure). Each power select multiplexer 12530 has a select input (not shown in FIG. 125B ) coupled to control logic (not shown in FIG. 125B ) and exists in duplicate between Layer 1 and Layer 1 2, although it may be located elsewhere within the 3D IC 12500, or elsewhere in the system where the 3D IC 12500 is distributed.

Those of ordinary skill in the art know that there are many ways to programmably or selectively disable blocks located in integrated circuits known in the art, and the power multiplexer 12530 used in the case of Figure 125B is only for Example for demonstration purposes. Any method of stopping LFB 12520 is the content of this document. For example, a power switch can be used for both VCC and GND. Alternatively, when VCC is decoupled from the LFB 12530, the GND power switch can be ignored and the power node allowed to "float down" to ground. In some cases, VCC can be controlled by a transistor, like a source follower itself controlled by a voltage regulator, or an emitter follower, and VCC can be removed by masking or cutting off the transistor. Many other alternatives are also possible.

In some cases, the control logic (not shown in FIG. 125B ) employs the BIST circuitry present in each block to stitch a single copy of the settings (using each block's multiple input and output multiplexers, which function similarly to the LFB The multiplexers 12522 and 12524 associated with 12520 are similar) and contain functional copies of all LFBs. If the image is complete, power off all faulty LFBs and unused functional LFBs through their associated power select multiplexers (similar to power select multiplexer 12530). Thus, by using standard 2D IC technology, power savings to the level required for a single copy setup can be achieved.

Alternatively, if a layer, such as layer 1, is selected as the main layer, then the BIST controller in each block can independently decide which mode of block to use. Majority multiplexers 12522 and 12524 are then set to couple used blocks to layer 1, and majority multiplexer 12530 is set to switch off unused blocks. It is worth mentioning that in the case associated with not using the power select multiplexer 12530 or an equivalent multiplexer, this can save half the power consumption.

Test techniques known in the art are a compromise between the detailed diagnostic capabilities of scan tests and the simplicity of BIST tests. In the case of these schemes, each BIST block (smaller than a typical LFB, but containing tens to hundreds of logic cones) stores a small number of initial states, especially scan flip-flops, and most scan flip-flops can use the default value. Use CAD tools to analyze and set the netlist to determine the necessary scan triggers and complete efficient testing.

In the test mode, after the BIST controller moves into the initial value, it starts to set the timing. The BIST controller has a signature register, possibly a CRC or other circuit, that monitors the bits inside the test block. After a preset number of clock cycles, the BIST controller stops setting the timing, removes the data stored in the scan flip-flops, adds their contents to the block signature, and combines the signature with a small number of stored signatures (stored in the initial state for each a) for comparison.

This approach has the advantage that it does not require a large store of scan vectors and a simple "pass" or "fail" BIST test. Test blocks are not as fine-grained as the cone of logic for identifying individual faults, but are much coarser than large logic function blocks. In general, the finer the test granularity (i.e., the smaller the size of the circuit that replaces the faulty circuit), the smaller the probability of delayed failures on the same test block on layer 1 and layer 2. Once the functional state of a BIST block is determined, appropriate values can be written to the latches controlling the inter-layer multiplexers, thereby replacing faulty BIST blocks on a layer, if necessary. In some cases, faulty and unused BIST blocks can cut power, thereby saving power consumption.

The different typical cases discussed so far have found and repaired defective logic cones or logic blocks in static test mode on their own, and the present invention case can find fault addresses due to noise or timing problems. For example, in the 3D IC 11900 of FIG. 119 and the 3D IC 12300 of FIG. 123 , scan chains are used to carry out full-speed testing in a manner known in the art. Method one involves shifting in the vector through the scan chain, taking at least two full-speed clock pulses, and then shifting the result out through the scan chain. This captures cones of logic that run fine when tested at low speeds, but run too slowly to function in the circuit at full clock speed. But this approach enables field repair of slow logic cones, requiring the time, intelligence and memory capacity necessary to store, run and evaluate scan vectors.

Another approach is to use the block BIST test at power-on, reset or request to overclock each block at increasing frequencies until failure, determine which block's layer mode runs faster, and then use the Faster blocks replace slower ones. This approach has more of the usual time, intelligence and memory requirements associated with block BIST testing, but it still places the 3D IC in test mode.

Figure 126 illustrates a case where errors due to slow logic cones can be monitored in real time while the circuit is in normal operating mode. A typical 3D IC denoted by 12600 contains two layers, denoted as layer 1 and layer 2, which are distinguished by dotted lines in the figure. Each layer contains one or more circuit layers and is bonded together to form 3D IC 12600. Each layer can be electrically coupled through TSV or other interlayer interconnection technology.

Figure 126 is primarily operational on circuitry coupled to the output of a single layer 2 logic cone 12620, although substantially identical circuitry is also present in layer 1 (not shown in Figure 82). Also included in Figure 126 is the D input coupled to the Layer 2 logic cone 12620 output, and the Q output coupled to the scan flip-flop 12622 of the D1 input of the multiplexer 12624 through an interlayer line 12612 (represented as Q2 in the figure). Multiplexer 12624 has one input coupled to the output DATA2 of the logic cone (not shown in FIG. 126 ) and another input coupling layer 1 flip-flops to flip-flops 12622 (not shown in FIG. 1 ) via interlayer lines 12610 of D0.

XOR gate 12626 has an input coupled to a first input of Q1, a second input coupled to Q2 and an output coupled to a first input of AND gate 12646. AND gate 12646, with another input one coupled to the second input of TEST_EN line 12648 and one coupled to the set input of RS flip-flop 3828. The RS flip-flop also has an output coupled to the reset input of layer 2 reset line 12630 and another output coupled to the first input of OR gate 12632 and N-type pass transistor 12638 gate. OR gate 12632 also has one output coupled to a second input of level 2 OR chain input line 12634 and another output coupled to level 2 OR chain output line 12636 .

Layer 2 control logic (not shown in FIG. 126 ) controls the operation of XOR gate 12626 , AND gate 12646 , RS flip-flop 12628 and OR gate 12636 . TEST_EN line 12648 is used to mask the test process of Q1 and Q2. Ideally, such as functional bugs have been fixed, the difference between Q1 and Q2 is routinely expected, and may interfere with the background testing process for locating marginal timing errors.

Layer 2 reset line 12630 also resets the internal state of RS flip-flop 12628 to a logic value of -0, in addition to all other RS flip-flops associated with other logic cones on layer 2. OR gate 12632 is coupled with all other OR gates associated with other logic cones of level 2 to form a large level 2 distributed OR function coupled to level 2 RS flip-flops (eg, 12628 in FIG. 126). If all RS flip-flops are reset to logic-0, then the output of the assigned OR function is logic-0. If a logic state difference occurs between the flip-flops generating the Q1 and Q2 signals, XOR gate 12626 displays a logic value of -1 to the set input of RS flip-flop 12628 through AND gate 12646 (if TEST_EN = logic value -1), making it Changes state and presents a logic value of -1 to the first input of OR gate 12632, which in turn produces a logic value of -1 at the level 2 assigned OR function (not shown in Figure 126), prompting the control logic (not shown reflected in the attached figure) there is an error.

The control logic may use the stack of N-type pass transistors 12638, 12640 and 12642 to determine the location of the error generating logic cone. Transistor 12638 includes a gate terminal coupled to the Q output of RS flip-flop 12628, a source terminal with a drain terminal coupled to ground, and a drain terminal coupled to the source of transistor 12640. Transistor 12640 includes a gate terminal coupled to the row address line ROW_ADDR line, a drain terminal coupled to the source terminal of the drain of transistor 12638 and another drain terminal coupled to the source of transistor 12642. Transistor 12642 includes a gate terminal coupled to column address line COL_ADDR line, a drain terminal coupled to the upper drain terminal of transistor 12640 and another drain terminal coupled to sense line SENSE.

The row and column addresses are virtual addresses, because in the logic setting, the positions of the flip-flops are not neatly arranged in the rows and columns. In some cases, the netlist is modified by a computer-aided design (CAD) tool to correctly address each cone of logic, and the ROW_ADDR and COL_ADDR signals can then be routed like other signals in the setup.

This results in an efficient method of controlling the looping of logic through the virtual address space. If COL_ADDR = ROW_ADDR = logic-1 and the RS flip-flop state is logic-1, then the transistor stack will control SENSE = logic-1. Therefore, a logic value of -1 occurs only at the virtual address location where the RS flip-flop catches the error. Once an error is found, RS flip-flop 12628 can be reset to a logic value of -0 along with layer 2 reset line 12630 so that another possible error can be found.

Set the control logic to handle errors in one of many ways. For example, log errors and enter test mode when logic errors occur repeatedly at the same logic cone location to determine if the location needs to be repaired. This is a good way to deal with intermittent errors caused by marginal logic cones that fail only occasionally due to noise issues, but under normal testing, pass the test. Alternatively, depending on the setting selection, action can be taken on the first error notification received.

The use of triple-mode redundancy (TMR) at the logical level, in accordance with Figure 27 above, also operates as an effective field fix, although it does create a high level of redundancy that masks rather than repairs failures due to delayed mechanisms or Errors due to marginally slow logic cones. The level of redundancy will be even higher if factory remediation is used to verify that all equivalent cones of logic on each layer are tested to pass the 3D IC before it leaves the factory. Comparing three-ply versus two-ply, with or without repair ply, the cost must be taken into account when determining the best case for application.

Figure 127 illustrates an alternative TMR approach in exemplary 3D IC 12700. In Figure 127 there are a number of nearly identical layers, denoted as Layer 1, Layer 2 and Layer 3, separated by dotted lines in the drawing. Layer 1, Layer 2, and Layer 3 each contain one or more circuit layers. and bonded together to form a 3D IC 12700 using methods known in the art. Level 1 consists of level 1 logic cones 12710 , flip flops 12714 , and majority-of-three (MAJ3) gates 12716 . Layer 2 contains layer 2 logic cones 12720 , flip flops 12724 and MAJ3 gates 12726 . Layer 3 contains layer 3 logic cones 12730 , flip flops 12734 and MAJ3 gates 12736 .

Logic cones 12710, 12720, and 12730 all perform nearly the same logic function. Flip-flops 12714, 12724, and 12734 favor scan flip-flops. If there is a repair layer (not shown in FIG. 127 ), then the flip-flop 2502 in FIG. 25 can be used to repair the defective logic cone of the 3D IC 12700 before it leaves the factory. MAJ3 gates 12716, 12726 and 12736 compare the outputs of the three flip-flops 12714, 12724 and 12734, and output a logic value that is most consistent with the input. If two or three of the three inputs are equal to a logic value of -0, then the MAJ3 gate will output a logic value of -1. Therefore when one of the three logic cones or one of the three flip-flops is only defective, the outputs of all three MAJ3 gates will exhibit correct logic values.

One of the advantages of the example in Figure 127 is that layer 1, layer 2 or layer 3 can be encapsulated using all or almost the same mask. Another advantage is that the MAJ3 gates 12716, 12726 and 12736 also operate efficiently as single event upset (SEU) filtering, enabling high-dependency or radiation-hardened applications as described in Rezgui cited above.

Typical 3D IC 12800 in Figure 128 presents another example of TMR. In this case, the MAJ3 gate is placed between the logic cone and its respective flip-flop. In Figure 128 there are nearly identical layers, represented as Layer 1, Layer 2, and Layer 3, which are separated by dotted lines in the drawing. Layers 1, 2 and 3 each contain one or more circuit layers and are bonded together to form the 3D IC 12800 using methods known in the art. Level 1 consists of a level 1 logic cone 12810 , a flip-flop 12814 and a majority-of-three (MAJ3) gate 12812 . Layer 2 contains layer 2 logic cones 12820 , flip flops 12824 and MAJ3 gates 12822 . Layer 3 contains layer 3 logic cones 12830 , flip flops 12834 and MAJ3 gates 12832 .

Logic cones 12810, 12820, and 12830 all perform nearly the same logic function. Flip-flops 12814, 12824, and 12834 favor scan flip-flops. If there is a repair layer (not shown in FIG. 128 ), then the flip-flop 2502 in FIG. 25 can be used to repair the defective logic cones of the 3D IC 12800 before shipment. The MAJ3 gates 12812, 12822 and 12832 compare the outputs of the three logic cones 12810, 12820 and 12830, and then output a logic value that is most consistent with the input. Thus when one of the three logic cones is defective, the outputs of all three MAJ3 gates will exhibit correct logic values.

One of the advantages of the example in Figure 128 is that layer 1, layer 2 or layer 3 can be encapsulated using all or almost the same mask. Another advantage is that the MAJ3 gates 12712, 12722 and 12732 also operate effectively as single event transient (SET) filtering, thus enabling high-dependency or radiation-hardened applications as described in Rezgui cited above.

Typical 3D IC 12900 in Figure 129 presents another example of TMR. In this case, the MAJ3 gate is placed between the logic cone and its respective flip-flop. In Figure 129 there are nearly identical layers, represented as Layer 1, Layer 2, and Layer 3, which are separated by dotted lines in the drawing. Layers 1, 2 and 3, each comprising one or more circuit layers, are bonded together to form the 3D IC 12900 using methods known in the art. Level 1 consists of Level 1 logic cone 12910 , flip-flop 12914 , and majority-of-three (MAJ3) gates 12912 and 12916 . Layer 2 contains a layer 2 logic cone 12920 , flip-flop 12924 and MAJ3 gates 12922 and 12926 . Level 3 contains the level 3 logic cone 12930 , flip-flop 12934 and MAJ3 gates 12932 and 12936 .

Logic cones 12910, 12920, and 12930 all perform nearly the same logic function. Flip-flops 12914, 12924, and 12934 favor scan flip-flops. If there is a repair layer (not shown in FIG. 129 ), then the flip-flop 2502 in FIG. 25 can be used to repair the defective logic cones of the 3D IC 12900 before shipment. MAJ3 gates 12912, 12922 and 12932 compare the outputs of the three logic cones 12910, 12920 and 12930, and then output a logic value that is most consistent with the input. Similarly, the MAJ3 gates 12916, 12926 and 12936 compare the outputs of the three flip-flops 12914, 12924 and 12934, and then output a logic value that is most consistent with the input. Thus when one of the three logic cones or one of the three flip-flops is defective, the outputs of all six MAJ3 gates will have correct logic values.

One of the advantages of the example in Figure 129 is that layer 1, layer 2 or layer 3 can be encapsulated using all or almost the same mask. Another advantage is that MAJ3 gates 12712, 12722, and 12732 also operate effectively as single-event transient (SET) filters, and MAJ3 gates 12716, 12726, and 12736 also operate effectively as single-event upset (SEU) filters, thereby guaranteeing the above mentioned Highly dependent or radiation-hardened applications as described in Rezgui.

Some examples of the present invention can be applied to a large number of commercial and highly dependent aerospace and military fields. The ability to resolve defects in the factory with a repair layer, combined with the ability to automatically resolve delay defects (cover up with three-layer TMR cases or replace faulty circuits with two-layer replacement cases), compared to traditional two-dimensional integrated circuit (IC) technology In comparison, it is possible to generate larger and more complex three-dimensional systems. These various aspects of the invention can be coordinated with the cost requirements of the target application area.

According to some cases of the present invention, in order to reduce the cost of 3D IC, it is better to use the same mask set when manufacturing each layer. This is done by fabricating the same VIAS structure on each layer in an appropriate manner and then compensating by the desired amount when aligning layers 1 and 2.

Figure 130A illustrates a via pattern 13000 on layer 1 of 3D ICs 11900, 12100, 12200, 12300, 12400, 12500, and 12600 as described above. Metal stacks on each via location 13002, 13004, 13006 and 13008 are present on at least the metal layers above and below layer 1. Via pattern 13000 occurs close to each repair or replacement multiplexer on layer 1, and via metal stacks 13002 and 13004 (layer 1 input D0 denoted by L1/D0 in the figure) are coupled between that location D0 multiplexer input, and via metal stacks 13006 and 13008 (L1/D1 in the figure represent layer 1 input D1) are coupled to D1 multiplexer input.

Likewise, Figure 130B depicts a substantially uniform via pattern 13010 on layer 2 of 3D ICs 11900, 12100, 12200, 12300, 12400, 12500, and 12600 as described above. Metal stacks on each via location 13012, 13014, 13016, and 13018 exist on at least the metal layers above and below layer 2. Via pattern 13010 occurs close to each repair or replacement multiplexer on layer 2, and via metal stacks 13012 and 13014 (layer 2 input D0 denoted by L2/D0 in the figure) are coupled between that location D0 multiplexer input, and via metal stacks 13016 and 13018 (in the figure, L2/D1 represents layer 2 input D1) are coupled to D1 multiplexer input.

Figure 130C is a top view of via patterns 13000 and 13010 aligned and supplemented by interlayer interconnect pitches. The inter-layer interconnection can be realized through TSV or other inter-layer interconnection technologies. Figure 130C includes metal laminations 13002, 13004, 13006, 13008, 13012, 13014, 13016, and 13018 discussed above. In Figure 130C, layer 2 is supplemented by an interlayer connection pitch located to the right of layer 1. But the addition results in a physical stack of via metal laminations 13004 and 13018. Likewise, supplementation also results in a physical stack of via stacks 13006 and 13012. If TSV or other interlayer vertical coupling points are located at these two overlapping locations (via a single mask), then layer 2 mux input D1 is coupled to layer 1 mux input D0 and Coupling layer 2 multiplexer input D0 to layer 1 multiplexer input D1. This is exactly the inter-layer connection topology technology necessary for the repair or replacement of logical cones and functional blocks in the cases described in Figures 121A and 123 .

Figure 130D is a side view of a structure employing the method described in Figures 130A, 130B and 130C. Figure 130D illustrates a typical 3D IC, indicated at 13020, consisting of two instances of layer 13030, a top-level instance indicated as layer 2 and a bottom-level instance indicated as layer 1 in the drawing. Each instance of layer 13020 includes a typical transistor 13031 , a typical contact 13032 , typical metal 1 13033 , typical via 1 13034 , typical metal 2 13035 , typical via 2 13036 and typical metal 3 13037. The dotted ellipse indicated at 13000 indicates the portion of layer 1 corresponding to via pattern 13000 in FIGS. 130A and 130C. Likewise, the dotted ellipse indicated at 13010 indicates the portion of layer 2 corresponding to via pattern 13010 in FIGS. 130B and 130C. In this case, for example, an interlayer via of TSV 13040 couples the signal D1 of the second layer to the signal D0 of the first layer. Another interlayer via (not shown since it is not in the plane of Figure 130D) couples signal D01 of layer 2 to signal D1 of layer 1. As shown in Figure 130D, when layer 1 is identical to layer 2, layer 2 is complemented by an interlayer via pitch such that TSVs are properly aligned for each layer, but only a single interlayer via mask is required To achieve the correct inter-layer connection.

According to the above, in some cases of the present invention, it is better for the control logic on each layer of the 3D IC to know which layer it is. At the same time, it is also best to use the same mask for each layer. In one case where interlayer via pitch complementation was used to properly couple functionality and repair connections, a different via pattern was installed near the control logic to exploit interlayer complementation and uniquely identify each layer to its control logic.

Figure 131A shows a via pattern 13100 on layer 1 of 3D ICs 11900, 12100, 12200, 12300, 12400, 12500 and 12600 as described above. Metal stacks at each via location 13102, 13104, and 13106 are present on at least the metal layers above and below layer 1. The via pattern 13100 occurs adjacent to the control logic on layer 1 . Via metal stack 13102 is coupled to the ground (L1/G in the figure represents layer 1 ground). Via metal stack 13104 is coupled to a signal named ID (Level 1 ID is denoted by L1/ID in the figure). Via metal stack 13106 is coupled to the supply voltage (L1/V in the figure represents layer 1 VCC).

Figure 131B shows a via pattern 13110 on layer 1 of 3D ICs 11900, 12100, 12200, 12300, 12400, 12500 and 12600 as described above. Metal stacks at each via location 13112, 13114, and 13116 are present on at least the metal layers above and below layer 2. Via pattern 13110 occurs adjacent to the control logic on layer 2. Via metal stack 13112 is coupled to ground (Layer 2 ground is denoted by L2/G in the figure). Via metal stack 13114 is coupled to a signal named ID (Layer 2 ID is denoted by L2/ID in the figure). Via metal stack 13116 is coupled to the supply voltage (L2/V in the figure represents Layer 2 VCC).

Figure 131C is a top view of via patterns 13100 and 13110 aligned and complemented by inter-layer interconnect pitch. The interlayer interconnection can be realized through TSV or other interlayer interconnection technologies. Figure 130C includes the metal laminations 13102, 13104, 13106, 13108, 13112, 13114, and 13116 discussed above. In Figure 130C, layer 2 is supplemented by an interlayer connection pitch located to the right of layer 1. But supplementation results in a physical stack of via metal laminations 13104 and 13112. Likewise, supplementation also results in a physical stack of via stacks 13106 and 13114. If TSV or other interlayer vertical coupling points are at these two overlapping locations (via a single mask), ground the Layer 1 ID signal and couple the Layer 2 ID signal to VCC. This structure allows the control logic on layers 1 and 2 to uniquely know their vertical position in the stack.

Those skilled in the art generally know that the metal connection between layer 1 and layer 2 is larger because it includes larger stacks and many TSVs or other interlayer interconnects. The increased size facilitates alignment of the supply nodes and ensures that L1/V and L2/V are both at positive supply potentials and L1/G and L2/G are at node potentials.

Many examples of the present invention employ a triple-modular redundancy (RMR) approach in three-tier distribution. In these cases, the best approach is to use the same mask for all three layers.

Figure 132A illustrates a via metal overlay pattern 13200 comprising a 3x3 array of TSVs (or other interlayer coupling techniques). TMR interlayer connections occur near the majority-of-three (MAJ3) gates that fan-in or fan-out from flip-flops or functional blocks. Therefore, at each position, the function f(X0, X1, X2)=MAJ3(X0, X1, X2) is used on each layer of the three layers, where X0, X1 and X2 represent the three inputs of the MAJ3 gate. For the purposes of this discussion, since the MAJ3 gate and the X1 and X2 inputs come from the other two layers, the X0 input is always coupled to the signal pattern generated on the same layer.

In via pattern 13200, via metal stacks 13202, 13212, and 13216 are coupled to the X0 input of the MAJ3 gate on that layer, via metal stacks 13204, 13208, and 13218 are coupled to the X1 input of the MAJ3 gate on that layer, and Via metal stacks 13206, 13210 and 13214 are coupled to the X2 input of the MAJ3 gate on that level.

Figure 132B shows a typical 3D IC, designated 9220, having three layers, represented as layer 1, layer 2 and layer 3 from bottom to top. Each layer contains an instance of via pattern 13200 near the gate of MAJ3 for TMR related interlayer coupling. Layer 2 adds an interlayer via pitch to the right of layer 1, and layer 3 adds an interlayer via pitch to the right of layer 2. The description in accompanying drawing 132B is only an excerpt. While it shows the two interlayer via pitch complements correctly in the horizontal direction, generally those skilled in the art know that each row of via metal laminations in each case of the 13200 is left-to-right aligned with the same row in the other case.

Thus, the via metal laminations at three locations are aligned to all three layers. Figure 132B shows three interlayer vias 13230, 13240, and 13250 at those locations coupling layer 1 to layer 2, and three interlayer vias 13232, 13232, at those locations coupling layer 2 to layer 3. 13242 and 13252. The same via mask can be used in the via packaging stage.

Therefore, the interlayer vias 13230 and 13232 are aligned up and down, and couple the layer 1 X2 MAJ3 gate input, the layer 2 X0 MAJ3 gate input and the layer 3 X1 MAJ3 gate input. Likewise, interlayer vias 13240 and 13242 are aligned top and bottom and couple the layer 1 X1 MAJ3 gate input, layer 2 X2 MAJ3 gate input and layer 3 X0 MAJ3 gate input. Finally, the interlayer vias 13250 and 13252 are aligned up and down and couple the layer 1 X0 MAJ3 gate input, the layer 2 X1 MAJ3 gate input and the layer 3 X2 MAJ3 gate input. Since the X0 input of the MAJ3 gate in each layer is driven from that layer, each driver is coupled to a different MAJ3 gate input on each layer to avoid driver shorting, while each MAJ3 gate on each layer receives signals from three layers. The input of the last three drivers.

Some examples of the present invention can be widely applied in commercial and highly dependent aerospace and military fields. The ability to resolve defects in the factory with a repair layer combined with the ability to automatically resolve delayed defects (masking with a three-layer TMR case or replacing faulty circuits with a two-layer replacement case) enables The generation of larger and more complex three-dimensional systems becomes possible. These various aspects of the invention can offset the cost requirements of the targeted application areas.

For example, 3D ICs targeted at inexpensive consumer products see cost as a major consideration and can be repaired on-site at the factory to maximize yield, but exclude field-repaired circuits that minimize cost for short-lifetime products. 3D ICs targeting higher-end consumer or lower-end commercial products can incorporate two-tier field replacement in factory refurbishment. Aiming at balancing cost and reliability, 3D ICs for enterprise-class computing devices can eliminate factory repair steps and use TMR methods in qualified yield and field repair. 3D ICs targeting high-dependency, military, aerospace, space, or radiation-hardened applications can take factory repair to ensure that all three cases of each circuit are fully operational and employ TMR methods in field repair and SET and SEU filtering. Battery-driven components for the military market can add circuitry to allow the component to run only one of the three layers of TMR, thereby extending battery life, and include a radiation detection circuit that can automatically switch to TMR mode as needed when the operating environment changes. Many other combinations and alternations are possible within the scope of the invention.

It is worth noting that many principles of the present invention are also applicable to traditional two-dimensional integrated circuits (2D ICs). For example, a similar two-layer field repair case is built on a single layer, reworking the circuit for both modes on one 2D IC, and using the same cross-connect between the reworking modes. Programmable technologies such as fuses, antifuses, and flash memory can be used to effect factory and field repairs. Likewise, similar patterns of some TMR cases are unique topological techniques in both 2D IC and 3D IC, and if applied on a single layer, can also improve the yield or reliability of 2D IC systems.

Accompanying drawing 13 is the schematic flow chart of 3D logical division method. Dividing a logic setup into more than two vertically connected dies presents a new round of challenges for place-and-route-P&R tools. The layout and routing tool is a tool in CAD software, which has the ability to operate the logic chips (and other chips in the library) mentioned above. The layout flow planning of prior art P&R tools generally starts with layout, followed by routing. However, the logic setting of vertically connecting dies prioritizes the greatly reduced frequency between dies, thus creating the need for a special setting process and CAD software that specifically supports the setting process. In fact, judging from the flow chart in Figure 13, it is worth prioritizing part of the wiring for the 3D system.

The flowchart of accompanying drawing 13 adopts the following terms: M-logic TSV number; N(n)-connected to the number of nodes of net n; S(n)-slack in the middle of net n; Nets connecting two halves (MC) A known algorithm that splits the logical setup (netlist) into two halves of the same size; MC - the number of nets connecting the two halves; K1, K2 - two parameters selected by the setter.

One idea of the proposed flow in Fig. 13 is to build a netlist in the logical setup, so that the number of nodes greater than K1 and less than K2 is connected. K1 and K2 are parameters selected by the setter and can be modified during iteration. K1 should be high enough to limit the number of nets put into the netlist. The purpose of the process is to allocate TSVs into nets with tight timing constraints - critical nets. At the same time, there are many nodes that can extend the layout to many dies, which helps to shorten the overall physical length and meet timing constraints. The number of nets in the table should be close to the same, but not less than the number of TSVs. Correspondingly, the K1 setting value must be high, so as to achieve the purpose of the process. K2 is the upper limit of the line network, and its node number N(n) can be the subject of special treatment.

The critical net usually determines the critical path and the available slack time on the path by setting static timing analysis, and reaches the floor plan, place and route tool through the path constraint, so that the final setting will not be degraded because of exceeding the requirements.

After the netlist is built, make a priority command according to the incremental slack or median slack S(n) of the net. Then using a partitioning algorithm, such as but not limited to MinCut, the setting can be split into two parts, with the highest priority net being split equally between the two parts. The purpose is to give tight and slack nets a better chance of being placed closer together to meet the timing challenge. Nets with a higher number of nodes than K1 tend to cover larger spaces, and by extending into three dimensions, we can better meet the timing challenge.

The flow diagram of Figure 13 suggests an iterative process for distributing TSVs to many node nets with tightest timing challenges or minimal slack.

Obviously, the same flow can be scaled to 3-way splits or any other amount depending on how many dies the logic extends.

Building a 3D configurable system based on antifuse logic brings features that enable cost-effectiveness gains through the use of redundancy. But for the 3D structure in the case of the present invention, it can be even more convenient, because the memory will not be randomly distributed between the logic, but will be concentrated in the memory die connected vertically to the logic die. Memory redundancy and proper auto-repair procedures have less impact on logic and system performance.

A series of level scribe blocks in the present invention represents a partial loss of silicon area. The narrower the blocks, the less damage there is, so there are advantages to using advanced scribing methods that can be manufactured and work with narrow blocks.

Such an advanced dicing method uses a laser to scribe 3D IC wafers. Laser scribing technology, including cooling the substrate by water jets and removing debris, can be used to minimize damage to the 3D IC structure and cut the sensitive layers in the 3D IC, followed by the final normal dicing process.

An added advantage of the 3D configurable systems in each case of the present invention is the reduced cost of testing, which is a result of the use of standard 'Lego®' building blocks to create unique systems. Test standard block can reduce test cost by applying probe card and standard test program.

This disclosure includes two forms of 3D IC systems, the first is through TSV, and the second is through the method called "top floor" in the text. See Figures 21~35 and 39~40 for details. These two methods can be used together in the case of devices that generate multiple layers of mono- or poly-silicon by layer transfer or deposition and what is referred to herein as a 'foundation' and 'top floor' approach connected together with TSVs. The main difference is that the previous TSVs were associated with relatively large misalignments (about 1 micron) and limited connections (TSVs) of the order of 10,000 per square mm connecting fully packaged components, whereas the disclosed 'smart dicing' layer transfer method allows The 3D structures have tiny misalignments (<10nm) and a large number of connections (vias) around 100 million per square millimeter because they are produced in an integrated packaging process. One of the advantages of TSV-based 3D is the ability to test components before assembly and the ability to utilize known good die (KGD) in 3D stacks or systems, which is essential to ensure good 3D integrated system yield and reasonable cost It is very beneficial.

An additional alternative of the present invention is a method that allows redundancy so that highly integrated 3D systems using layer transfer techniques can have higher yields. To illustrate this redundancy concept, we will use the programmable tile array shown in Figure 11A 36-38.

Accompanying drawing 41 is the schematic diagram of the redundant 3D IC system, and it introduces that the 3D IC programmable system is composed of programmable first layer 4100 of 3X3 tiles 4102, covered with programmable first layer 4110 of 3X3 tiles 4112, and the top cover Programmable first layer 4120 of 3X3 tiles 4122. There are many programmable connections 4104 between a tile and its neighbors in the layer. Programmable device 4106 may be an antifuse, pass transistor controlled driver, floating gate flash transistor, or similar electrically programmable device. Each inter-tile connection 4104 has a branch programmable connection 4105 connected to an inter-layer vertical connection 4140 . The final product is configured such that at least one layer such as 4110 is reserved for redundancy.

When the end-product programmable system is programmed for the end application, each tile performs a built-in self-test using its own MCU. The tiles found to be defective are replaced by tiles in the redundant layer 4410 . The replacement process will be done with tiles located at the same location within redundant layers, so its effect on the functionality and performance of the overall product should be desirable. For example, if tile (1, 0, 0) is defective, then tile (1, 0, 1) will be programmed to perform the same function and replace tile (1, 0, 0) by precisely setting the programmable connections between the tiles. ). Thus, if a defective tile (1,0,0) is assumed to be connected to tile (2,0,0) by programmable component 4106 through connection 4104, then programmable component 4106 is turned off and programmable components 4116, 4117 and 4107 are turned on. Both internal and external connections of repeating tiles should use similar multi-level connection structures. Therefore, when a tile is defective, the redundant tile of the redundant layer will be programmed into the function of the defective tile, and the structure between the multi-layer tiles will be activated, and the redundant tile will be connected after the faulty tile is cut off. When the tile (2, 0, 0) is defective, the vertical connection 4140 between layers can also be used to insert the tile (2, 0, 1) of the redundant layer. In this case, tile (2,0,1) would be programmed to function the same as tile (2,0,0), with programmable component 4108 off and programmable components 4118, 4117, and 4107 on.

An additional example of the present invention is a modified TSV (Through Silicon Via) process. The process is targeted at wafer-to-wafer TSV and will provide a method that increases wafer thickness down to around 1 micron. Figures 93A-D illustrate such a method. The first wafer, 9302, is the base with hybrid 3D structures built on top. A second wafer 9304 is bonded on top of the first wafer 9302 . The new upper wafer faces down so that the circuitry 9305 faces the first tier wafer 9302 with circuitry 9303.

In some applications, the bonding is oxide-to-oxide; in others, the bonding is copper-to-copper. In addition, the joint is a hybrid joint, ie some joint surfaces are oxide and some are copper.

After bonding, the upper wafer 9304 is thinned to about 60 microns through common back grinding and CMP processes. FIG. 93B illustrates the bonding of the now thinned wafer 9306 to the first tier wafer 9302.

The next step includes high-precision measurement of the thickness of the upper wafer 9306, after which the cleavage plane 9310 can be determined in the upper wafer 9306 through high-power 1-4MeV H+ implantation. The cleavage surface 9310 can be positioned approximately 1 micron above the junction surface, as shown in Figure 93C. To perform this process, a specialized high-power implanter, such as that used by SiGen in its PV (photovoltaic) applications, can be installed.

The ability to accurately measure the thickness of the upper wafer 9306 and the height control of the implant program makes it possible to cleave most of the upper wafer 9306 and leave a very fine layer 9312 of about 1 micron bonded on top of the first wafer 9302, See shown in accompanying drawing 93D.

One advantage of this process flow is that additional wafers with circuitry can now be laid out and bonded in a similar manner over bonding structures 9322 . But first, a connection layer is built on the backside of 9312, allowing electrical connections to bond structure 9322 circuits. Thinning the upper layer to a single micron level allows such an electrical connection metal layer to be completely aligned with the circuit 9305 of the upper wafer 9312, and the via holes through the back of the upper layer 9312 are relatively small, with a diameter of about 100 nm.

The thinning of the upper layer 9312 enables modified TSVs at the 100nm level, compared to the 5 microns required for TSVs to pass through 50 microns of silicon. Unfortunately, the misalignment level of the wafer-to-wafer bonding process is still large, around +/-0.5 micron. Correspondingly, as described herein with respect to Figure 75, a bond pad of around 1x1 micron is used on top of the first wafer 9302 to connect to the second wafer via copper-to-copper bonding and a small metal contact 9304 on the surface. The process provides a connection density of about 1 connection per square micron.

The ideal way is to increase the connection density by introducing the concepts and related explanations in Figure 80. This is even more challenging in the case of modified TSVs, since the two wafers to be bonded have very limited access to the bonding electrodes if bonded after both wafers are fully processed. However, to form a via, it needs to be etched in all layers. Figure 94 presents a method and structure for addressing these issues.

FIG. 94A shows four metal bonding electrodes 9402 exposed on the upper layer of the first wafer 9302. The joint electrode 9402 is oriented east-west, and the maximum misalignment Mx of the east-west joint is the length of 9406 plus a triangle D, which will be explained later. The pitch of bonding electrodes is twice the minimum pitch Py of the upper layer of the first wafer 9302. 9403 indicates the unused potential space of an additional metal electrode.

FIG. 94B shows bonding electrodes 9412 and 9413 exposed on the upper layer of the second wafer 9312. Figure 94B also shows two rows of bonding electrodes, A and B running from north to south. The length of these bonding electrodes is 1.25Py. The two wafers 9302 and 9312 are copper-to-copper bonded, and the bonding electrodes in FIGS. 94A and 94B are configured such that the bonding misalignment does not exceed the maximum misalignment Mx in the east-west direction and My in the north-south direction. Joining electrodes 9412 and 9413 in accompanying drawing 94B are set such that they do not inadvertently short the joining electrodes 9402 in 94A, and whether it is the joining electrodes 9412 of the A row or the joining electrodes 9413 of the B row can connect with the joining electrodes 9402 Get complete contact. Triangle D is the size from the east side of row B bonding electrodes 9413 to the west side of row A bonding electrodes 9412 . The number of bonding electrodes 9412 and 9413 in FIG. 94B should be set to equal the value of bonding electrodes 9402 in FIG. 94A plus My to offset the maximum misalignment error in the north-south direction.

Substantially all of the bonding electrodes in FIG. 94B can be routed through the internal wiring of the upper wafer 9312 to the bottom of the wafer adjacent to the transistor layer. See Figure 93D for the location of the bottom of the wafer and the top view of the 9322 structure. At this point, new vias 9432 are formed to connect bonding electrodes to the top surface of the bonding structure through conventional wafer processing steps. Figure 94C shows all the through-hole connections routed to the bond electrodes in Figure 94B, in row A 9432 and row B 9433. In addition, the through hole 8436 for introducing signals should also be processed. All of these vias can be aligned with the upper wafer 9312.

A metal mask is used to connect, for example, four vias 9432 and 9433 to four vias 9436 via metal strips 9438, as shown in FIG. 93C. This metal strip is aligned with the upper wafer 9312 in the east-west direction, and can also be aligned with the upper wafer 9312 in the north-south direction, but a special offset must be set based on the bonding misalignment in the north-south direction, but the metal strip in the north-south direction Structure 9438 shall be of sufficient length to offset worst case north-south joint misalignment.

Again, the invention is applicable to many applications other than programmable logic such as graphics processors consisting of many repeatedly processed chips. Other areas of application include general logic setup in 3D ASICs (Application Specific Integrated Circuits) or systems combining ASIC layers with layers consisting of at least some other specialized functions. Usually those who are knowledgeable in the technical field know that many cases and combination schemes can be completed by using the inventive principles in this paper, and this case will introduce itself to these professional technicians in due course. The invention is not restricted in any way except by the appended claims.

But another option to improve yield by replacing defective circuits and using 3D redundancy is to use direct read e-beams instead of programmable connections.

Additional variations of the programmable 3D system include a tiled programmable logic tile connected to I/O structures pre-assembled on the base wafer 1402 shown in FIG. 14 .

But in an additional variation, by any of the methods shown in Figures 21-35 or Figures 39-40, the programmable 3D system should include a tiled programmable logic tile pre-assembled on the finished base The I/O structures on top of wafer 1402 are connected. In fact, any of the optional structures in Fig. 11 can be packaged on top of each other, as long as the 3D technology shown in Figs. 21-35 or Figs. 39-40 is used. Correspondingly, many variations of 3D programmable systems can be achieved through a limited set of masks, just by mixing different structures to form different 3D programmable systems, and changing the amount, logical 3D position, I/O type, memory type, etc. .

Additional flexibility and mask re-use is achieved by using a fraction of the full reticle exposure. Modern stepper motors allow covering portions of the reticle, thereby projecting a small portion of the reticle. Accordingly, one part of the mask set may be used for one function while another part is used for another function. For example, let the structure in Figure 37 represent the logical part of a 3D programmable system terminal device. On top of the 3X3 programmable tile structure, the I/O structure can be built by using the process in Figures 21-35 or Figures 39-40. There should be a set of masks whose different parts are used for the overlap of different I/O structures; part. Each group is configured to provide a tile of I/O, perfectly superimposed on the programmable logic tile. Then two parts on one mask set, many variations can be generated at the end system, including a simple I/O with all nine tiles, another with SerDes overlapping tiles (0, 0), and a simple I/O O stacked on eight other tiles, another with SerDes overlapping tiles (0,0), (0,1) and (0,2), simple I/O stacked on other six tiles, and so on . In fact, if properly set up, many layers can be produced one on top of the other to produce a wide variety of end products within a limited set of masks. It is generally known by those skilled in the art that the applicability of this approach extends beyond programmable logic, preferably in structures with many 3D ICs and 3D systems. The scope of the invention is therefore only as defined by the appended claims.

But in an additional option of the present invention, the 3D antifuse configurable system should also include a programming die. In some cases of FPGA products, mainly antifuse based products, an add-on is installed for programming. In many cases, this facilitates the user's integration of this programming capability into the FPGA component. This can easily lead to severe overhead of the die when the programming process requires higher voltages and control logic. Therefore, the programmer function can be set in a dedicated programming die. The charge pump of the programming die can generate a higher programming voltage, and a controller associated with programming programs the anti-fuse programmable die inside the 3D configurable circuit and the program verification circuit. Programmable die are produced using lower cost older semiconductor processes. An additional advantage of the 3D structure of the configurable system is its high throughput cost reduction solution, where the antifuse layer is replaced by a custom layer, whereby the programmable die is removed from the 3D system, enabling more Cost-saving and high-capacity production.

Those of ordinary skill in the art know that the present invention uses the term antifuse because it is a common name in the industry, but the present invention also refers to a microcomponent that operates like a switch, indicating that in its initial state, the microcomponent has a high Impedance OFF state, and electronically, it can be switched to very low resistance -ON state. It can also correspond to a component that switches ON-OFF multiple times - a reprogramming switch. For example, new inventions, such as the electrostatically actuated metal droplet micro-switches introduced by CJ Kim, a staff member of the Micro-Nano Manufacturing Laboratory at the University of California, Los Angeles, can be compatible and integrated into CMOS chips.

Those skilled in the art know that the present invention is not limited to antifuse configurable logic, and is applicable to other non-volatile configurable logic. A good example is Flash-based configurable logic. Flash programming also requires higher voltages, and the overall density of the base diffusion layer can be reduced by installing the programming transistors and programming circuitry within the base diffusion layer. It is advantageous to use different instances of the present invention and to achieve higher device densities. It is therefore proposed to build programming transistors and programming circuits in accordance with one or more embodiments of the present invention, rather than as part of the diffusion layer. In high-volume production, one or more custom masks are used to replace the flash programming function and accordingly retain the need to add programming transistors and programming circuitry.

Unlike metal-to-metal antifuse, which can be placed as part of the metal interconnect, the flash circuit needs to be encapsulated in the base diffusion layer. Therefore, it is not so efficient to install the programming transistor on a layer far above. Another option of the present invention: TSVs 816 are used to connect the configurable logic device and its flash device to the underlying structure 814 including programming transistors.

In this article, there are various terms for expressing components. For example, "box" refers to the first monocrystalline layer with transistors and metal interconnect layers. This monocrystalline layer is also sometimes referred to as the master wafer, acceptor wafer, or base wafer.

Some examples of the present invention include developing a selection method of IC (Integrated Circuit) components using techniques and methods of constructing 3D IC systems. Some instances of the present invention enable component solutions that consume less power than the prior art. These component solutions are very beneficial for increasing applications of mobile electronic components such as mobile phones, smart phones, cameras, etc. For example, the incorporation of 3D semiconductor components within these mobile electronic components according to some aspects of the present invention can provide advanced mobile chips that operate more efficiently and last longer than prior art.

According to some examples of the present invention, 3D ICs can also enable electronic and semiconductor components to operate at higher performance levels, in view of shorter interconnects and more complex vias multiple levels of semiconductor components, and provide repair or use redundancy. ability. According to some examples of the present invention, the complexity of semiconductor devices can be achieved far beyond the level of prior art practice. These advantages have just guaranteed the more powerful computer system of embedded computer and improved system.

Some examples of the present invention can also enable significant non-recurring (NRE) cost savings in the setup of prior art electronic systems with high-density 3D FPGAs or different forms of 3D array-based ICs with the aforementioned scaled-down custom masks. These systems can be distributed across many products and many market segments. By reducing the initial investment risk before developing the market, the reduction of NRE makes it possible to develop and deploy new product groups or applications early in the product cycle. The above mentioned advantages can also be achieved by different hybrid approaches, such as using the overall mask in the logic layer and other overall mask in the memory layer to reduce NRE, thus creating a very complex system, which overcomes the inherent yield limitation by repair technology question. Another hybrid approach is to build a 3D FPGA and add a 3D layer of custom logic and memory on top, so that the end system can have field programmable logic on top of the factory custom logic. In fact, there are many ways to combine highly creative components to form a 3D IC to support the needs of an end system, including using multiple components, more than one of which incorporates the inventive elements. End systems can benefit from the use of inventive 3D memories and high-performance 3D FPGAs, as well as high-density 3D logic. The use of components consisting of one or more of the inventive elements can guarantee better performance and/or lower power consumption, as well as the advantages brought by other inventions, thus providing a competitive advantage for the end system. Such end systems shall be electronics-based products or other types of systems including some level of embedded electronics such as automobiles, remote control vehicles, etc.

In order to increase the contact resistance of extremely fine-scale contacts, the semiconductor industry uses various metal silicides, such as cobalt silicide, titanium silicide, tantalum disilicide, and nickel silicide. Current advanced CMOS processes, such as 45nm, 32nm and 22nm, use nickel silicide to increase the resistance of deep submicron source and drain contacts. For background information on silicide used to reduce junction resistance, see "Scaled CMOS NiSi Self-Aligned Silicide Technology", H.Iwai et al., Microelectronics Engineering, 60 (2002), pp. 157~169; "Sub-50nm CMOS NiSi vs. CoSi2 Integration", B.Froment et al., IMEC ESS Circuits, 2003 and "65 and 45nm Components - Introduction", D.James, Semicon West, July 2008, ctr_024377. In order to achieve the lowest NiSi contact and source/drain resistance, the nickel-on-silicon must be heated to about 450°C.

Therefore, it is best to ensure the low resistance of the process flow in this article, and the layer transfer temperature exposure must be kept below 400°C after metallization such as copper, aluminum and low-k dielectrics. This typical process flow constitutes a recessed channel array transistor (RCAT), but this or a similar flow can be applied to other process flows and components such as S-RCAT, JLT, V-trough, JEFE, bipolar and replacement gate process.

A planar n-access recessed channel array transistor (RCAT) with metal silicide source and drain contacts for 3D ICs can be constructed. As shown in FIG. 133A , a donor wafer 13302 of a P-type substrate is processed and includes an N+ doped layer 13304 and a P- doped layer 13301 that pass through the wafer and are the same size as the wafer. The N+ doped layer 13304 can be formed by ion implantation and thermal annealing techniques. Additionally, the P-doped layer 13301 contains additional ion implantation and annealing processes that provide a different doping level than the P-substrate 13302. The P-doped layer 13301 also has graded P-doping, which can alleviate transistor performance problems, such as the short channel effect after RCAT formation. Layer stacking can be formed by continuous epitaxial deposition of doped silicon P-doped layer 13301 and N+ doped layer 13304, and can also be realized through a combination of epitaxy and implantation techniques. Implant annealing and doping will use a rapid thermal annealing (RTA or spike) optical annealing technique or type.

As shown in FIG. 133B, a silicon-reactive metal, such as nickel or cobalt, can be deposited onto the N+ doped layer 13304 and annealed, using RTA, thermal or optical annealing processes, thereby forming a metal silicide layer 13306. The top surface of the donor wafer 13301 should be prepared with an oxide wafer bonding oxide deposit to form the oxide layer 13308.

As shown in Figure 133C, a layer transfer separation plane (shown in dashed lines) 13399 may be formed by hydrogen implantation or other methods as described above.

As shown in Figure 133D, the donor wafer 13302 including layer transfer separation plane 13399, P-doped layer 13301, N+ doped layer 13304, metal silicide layer 13306 and oxide layer 13308 can be temporarily Bonded to a carrier or carrier substrate 13312. The carrier or holder substrate 13312 should be a glass substrate to enable state-of-the-art optical processing consistent with the acceptor wafer. The temporary bond between the carrier or carrier substrate 13312 and the donor wafer 13302 can be a polymeric material, such as polyimide DuPont HD3007, which can be released at a later stage by laser ablation, exposure to ultraviolet radiation, or thermal decomposition as shown The adhesive layer 13314. Alternatively, temporary joints can be prepared by unipolar or bipolar electrostatic techniques, such as the Apache tool from Beam Services.

As shown in Figure 133E, the portion of the donor wafer 13302 at the layer transfer separation plane 13399 may be removed by cleaving or other processes as described above such as ion ablation or other methods. The remaining donor wafer P-doped layer 13301 can be thinned by a chemical mechanical polishing (CMP) process so that the P-layer 13316 can reach the desired thickness. Oxide 13318 may be deposited onto the exposed side of the P- layer 13316 .

As shown in Figure 133F, both the donor wafer 13302 and the acceptor substrate or wafer 13301 can be prepared for the aforementioned wafer bonding, followed by low temperature (below 400°C) aligned, oxide-to-oxide bonding. The aforementioned acceptor substrate 13310 will take care of transistors, circuits, metals such as aluminum or copper, interconnection wires, and metal interconnection strips or disks through layer through holes, and then use low-temperature processes such as laser ablation to release the carrier or support substrate 13312 and donor wafer 13302. Oxide layer 13318 , P- layer 13316 , N+ doped layer 13304 , metal silicide layer 13306 and oxide layer 13308 are layer transferred to acceptor wafer 13310 . The top surface of oxide 13308 can be chemically or mechanically polished. Current RCAT transistors are post-aligned and acceptor wafer 13310 alignment marks (not shown) are formed using a low temperature (below 400°C) process.

As shown in FIG. 133G, the transistor isolation region 13322 is defined through the mask, and then the oxide layer 13308, the metal silicide layer 13306, the N+ doped layer 13304 and the P- layer 13316 are etched on top of the oxide layer 13318 by plasma/RIE. A low temperature interstitial oxide is then deposited and chemical mechanically polished, while the oxide remains in the isolation region 13322. Thus, the recessed channel 13323 is mask defined and etched. The recessed channel surface and corners are smoothed by wet chemical or plasma/RIE etch processes to mitigate high field effects. These process steps form oxide region 13324, metal suicide source and drain region 13326, N+ source and drain region 13328 and P- channel region 13330.

As shown in Figure 133H, gate dielectric 13332 is formed and gate metal material is deposited. Gate dielectric 13332 is an atomic layer deposition (ALD) gate dielectric paired with a work function specific gate metal in the industry standard high-k metal gate process scheme described above. Or the gate dielectric 13332 is formed on the silicon surface by low-temperature oxide deposition or low-temperature microwave plasma oxidation, and then the gate material such as tungsten or aluminum will be deposited. Finally, the gate material is chemically mechanically polished, and the area of the gate is determined by masking and etching to form the gate electrode 13334 .

As shown in Figure 133I, a low temperature thick oxide 13338 is deposited, and the source, gate and drain contacts and through layer via (not shown) openings are masked and etched to produce transistors connected through metallization. Thus, gate contact 13342 is connected to gate electrode 13334 , while source and drain contacts 13336 are connected to metal suicide source and drain regions 13326 .

Those of ordinary skill in the art will appreciate that the illustrations in Figures 133A through 133I are for illustration purposes only and thus are not drawn to scale. Those skilled in the art will further appreciate that many variations are possible, for example the temporary carrier substrate can be replaced by a carrier wafer and the permanently bonded carrier wafer flow shown in Figure 40 can be used. Many other modifications within the scope of the present invention will be recommended in due course by these professionals after careful reading. The scope of the invention is therefore only as defined by the appended claims.

Due to the high-density layer-to-layer interconnection and storage components and transistors involved in the case of the present invention, the use of new FPGA (Field Programmable Logic Gate Array) programming structure and components can save cost, space and improve the performance of 3D FPGA . The pass transistor or switch and the storage element that controls the switch state of the pass transistor can be located in different layers and connected to each other and the wiring network metal line through the through layer via (TLV), or the pass transistor and the storage element can be in the same layer, and Use TLV to connect to the network metal line.

As shown in Figure 134A, the acceptor wafer 13400 is processed to accommodate logic circuits, analog circuits and other components, with metal interconnects and metal configuration networks forming the basis of the FPGA. The acceptor wafer 13400 also includes configuration components such as switches, pass transistors, memory chips, programming transistors, and includes one or more base layers as described above.

As shown in Figure 134B, the donor wafer 13402 is preprocessed with one or more layers of pass transistors or switches or partially formed pass transistors or switches. Pass transistors can be constructed using the local transistor process flow described above (such as RCAT or JLT or others) or using replacement gate technology (such as CMOS or CMOS N~P OR gate array, with or without the above-mentioned carrier wafer). The donor wafer 13402 and acceptor substrate 13400 and associated surfaces are prepared for wafer bonding as described above.

As shown in Figure 134C, the donor wafer 13402 and the acceptor substrate 13400 are bonded at a low temperature (below 400°C), and a portion of the donor wafer 13402 is cleaved and polished or otherwise described above such as ion dicing or other method to remove, thereby forming the remaining pass transistor layer 13402. Currently, transistors or portions of transistors are formed or completed and aligned to the above-mentioned acceptor substrate 13400 alignment marks (not shown). The through layer via (TLV) 13410 can be formed through the above method, the interconnection and the dielectric layer are the same, and then the acceptor substrate with the pass transistor 13400A is formed, including the acceptor substrate 13400, the pass transistor layer 13402 and the TLV 13410.

As shown in Figure 134D, the memory wafer donor wafer 13404 is preprocessed with one or more layers of memory wafers or partially formed memory wafers. The memory chip can use the above-mentioned local memory process flow (such as RCAT DRAM, JLT or others) or use alternative gate technology such as CMOS gate array New Year's project SRAM components, with or without the above-mentioned carrier wafer, or through non-easy A volatile memory such as R-RAM or the aforementioned FG flash is constructed. Storage wafers The donor wafer 13402 and acceptor substrate 13400A and associated surfaces are prepared for wafer bonding as described above.

As shown in Figure 134E, the storage wafer donor wafer 13404 and the acceptor substrate 13400A are bonded at low temperature (below 400°C), and a portion of the storage wafer donor wafer 13404 is cleaved and polished or otherwise described as described above. Ion dicing or other methods remove, thereby forming the remaining memory wafer layer 13404. Currently, a memory wafer and transistors or portions of transistors are formed or completed and aligned to the above-described acceptor substrate 13400A alignment marks (not shown). Memory-to-switch TLV 13420 and memory-to-acceptor TLV 13430 and interconnects and dielectric layers are constructed in the manner described above to form the acceptor substrate with pass transistors and memory die 13400B, including the acceptor substrate 13400 , Pass Transistor Layer 13402 , TLV 13410 , Memory-to-Switch SLV 13420 , Memory-to-Acceptor SLV 13430 , and Memory Wafer Layer 13404 .

As shown in Figure 134F, which is a simplified schematic diagram of the main components of a receiver substrate with pass transistors and memory wafer 13400B. A typical memory die 13440 at the memory die layer 13404 can be electrically coupled to a typical pass transistor gate 13442 at the pass transistor layer, which includes memory to switch through layer vias 13420. A pass transistor source 13444 on pass transistor layer 13402 may be electrically coupled to FPGA configuration network metal line 13446 on acceptor substrate 13400 with TLV 13410A. A pass transistor drain 13445 in pass transistor layer 13402 can be electrically coupled to FPGA configuration network metal line 13447 on acceptor substrate 13400 with TLV 13410B. The programming signals for the memory chip 13440 come from outside the chip, or located above, inside or below the memory chip layer 13404 . Memory die 13440 also includes an inverse configuration where a memory element, such as a FG flash element, is turned on to couple the gate of the pass transistor to ground. Thus, the FPGA configuration net metal line 13446 carrying the output signal from the logic chip in the acceptor substrate 13400 can be electrically coupled to the FPGA configuration net metal line 13447, which will be routed to the input of one of the logic chips in the acceptor substrate 13430 superior.

Those of ordinary skill in the art appreciate that the illustrations in Figures 134A through 134F are for illustration purposes only and thus are not drawn to scale. Those skilled in the art will further appreciate that many variations are possible, for example memory die layer 13404 may be built under pass transistor layer 13402 . Additionally, pass transistor layer 13402 includes control and logic circuitry in addition to pass transistors and switches. In addition, the memory die layer 13404 contains control and logic circuits in addition to the memory die. Thus, the pass transistor element can in turn be a transmission gate, or an actively driven type switch. Many other modifications within the scope of the present invention will be recommended in due course by these professionals after careful reading. The scope of the invention is therefore only as defined by the appended claims.

The pass transistor or switch that controls the ON or OFF state of the pass transistor is on the same layer as the memory element, and the TLV can be used to connect to the net metal line. As shown in FIG. 135A , the acceptor wafer 13500 can be processed to accommodate logic circuits, analog circuits and other components, together with metal interconnects and metal configuration networks to form the basic FPGA. The acceptor wafer 13500 may also include configuration components such as switches, pass transistors, memory chips, programmable transistors, and a base layer comprising one or more layers of the foregoing.

As shown in Figure 135B, the donor wafer 13502 is preprocessed with one or more layers of pass transistors or switches or partially formed pass transistors or switches. Pass transistors can be constructed using the local transistor process flow described above (such as RCAT or JLT or others) or using replacement gate technology (such as CMOS or CMOS N~P or CMOS gate array, with or without the above-mentioned carrier wafer). Donor wafer 13502 is preprocessed with one or more layers of memory wafers or partially formed memory wafers. Memory chips can be constructed using the local memory process flow described above (such as RCAT DRAM or others) or using replacement gate technology (such as CMOS gate arrays, with or without the above-mentioned carrier wafer). For example, by using a CMOS gate array to replace the gate process, the simultaneous formation of memory chips and pass transistors can be realized, wherein CMOS pass transistors and SRAM memory chips, for example, a 6-transistor chip is produced or an RCAT pass transistor is produced with RCAT DRAM memory. The donor wafer 13502 and acceptor substrate 13500 and associated surfaces are prepared for wafer bonding as described above.

As shown in Figure 135C, the donor wafer 13502 and the acceptor substrate 13500 are bonded at a low temperature (below 400°C), and a portion of the donor wafer 13502 is cleaved and polished or otherwise described above such as ion dicing or other method to remove, thereby forming the remaining pass transistor layer and memory layer 13502. Currently, transistors or portions of transistors are formed or completed and aligned to the above-mentioned acceptor substrate 13500 alignment marks (not shown). Through layer vias (TLVs) 13510 can be formed in the above manner, and then the acceptor substrate with pass transistors and memory wafer 13500A is produced, which includes acceptor substrate 13500, pass transistor layer 13502 and TLV 13510.

As shown in Figure 135D, which is a simplified schematic diagram of the main components of a receiver substrate with pass transistors and memory wafer 13500A. A representative memory die 13540 at the pass transistor and memory layer 13502 can be electrically coupled to a representative pass transistor gate 13542 at the pass transistor layer 13502 , which includes the pass transistor and memory layer interconnect metallization 13525 . A pass transistor source 13544 on the pass transistor and storage layer 13502 can be electrically coupled to an FPGA configuration network metal line 13546 on the acceptor substrate 13500 with TLV 13510A. A pass transistor drain 13545 located in the pass transistor and memory layer 13502 can be electrically coupled to an FPGA configuration network metal line 13547 located on the acceptor substrate 13500 with TLV 13510B. The programming signals for the memory chip 13540 come from outside the chip, or above, inside or below the pass transistors and the memory chip layer 13502 . Memory die 13540 also includes an inverse configuration where one memory element, such as a FG flash element, is turned on to couple the gate of the pass transistor to the supply voltage, and the other FG flash element is turned on to couple the gate of the pass transistor to the supply voltage. to the ground. Thus, the FPGA configuration net metal line 13546 carrying the output signal from the logic chip in the acceptor substrate 13500 can be electrically coupled to the FPGA configuration net metal line 13547, which will be routed to the input of one of the logic chips in the acceptor substrate 13530 superior.

Those of ordinary skill in the art appreciate that the illustrations in Figures 135A through 134D are for illustration purposes only and thus are not drawn to scale. Those skilled in the art will further appreciate that many variations are possible, such as pass transistors and memory layer 13502 including control and logic circuitry in addition to pass transistors or switches and memory die. Furthermore, the pass transistor element can in turn be a transmission gate, or an actively driven type switch. Many other modifications within the scope of the present invention will be recommended in due course by these professionals after careful reading. The scope of the invention is therefore only as defined by the appended claims.

As shown in Figure 136, which is a schematic diagram of a flash memory with integrated floating gate (FG). Control gate 13602 and floating gate 13604 are commonly used for sense transistor pass 13620 and switch transistor pass 13610 . Switching transistor source 13612 and switching transistor drain 13614 are coupled to FPGA configuration network metal lines. Sense transistor source 13622 and sense transistor drain 13624 are coupled to programming, erasing and reading circuits. This integrated NVM switch is used by FPGA manufacturer Actel and is prepared by 2D embedded FG flash technology under high temperature (higher than 400°C).

As shown in Figures 137A-137G, a 1T NVM FPGA device is constructed by wafer-sized doped layer transfer and post-layer transfer suitable for single-layer transfer in a 3D IC production process. The programming signals for this device come from outside the chip, either above, inside or below the device layer.

As shown in FIG. 137A, a P-substrate donor wafer 13700 is processed to contain two wafer-sized N+ doped layers and P- doped layers 13706. Compared to the P-substrate 13700, the P-doped layer 13706 has the same or different doping concentration. The doped layer can be produced by ion implantation and thermal annealing. Layer stacking can be formed by continuous epitaxial deposition of doped silicon layers, or it can be realized by a combination of epitaxy, implantation and annealing. P-doped layer 13706 and N+ doped layer 13704 can also have graded doping to alleviate transistor performance issues such as short channel effects, and to improve programming and noise cancellation performance. Before implantation, a screen oxide 13701 will be grown or deposited to protect the silicon from implant contamination and provide an oxide surface for later wafer-to-wafer bonding. These processes should all be done above 400°C because layer transfer to the processed substrate with metal interconnects is yet to be done.

As shown in Figure 137B, the top surface of the donor wafer 13700 can be oxidized by depositing an oxide 13702 or by thermal oxidation of the P-doped layer 13706 to form an oxide layer 13702 or by re-oxidation of an implanted barrier oxide 13701 object wafer bonding preparation. A layer transfer separation plane 13799 (shown in dashed lines) can be formed in the donor wafer 13700 (shown) or the N+ doped layer 13704 by hydrogen implantation or other methods as described above. Both the donor wafer 13700 and the acceptor wafer 13710 can be prepared for wafer bonding as described above, followed by low temperature (less than 400° C.) bonding. Portions of the P-donor wafer substrate 13700 above the layer transfer separation plane 13799 may be removed by cleaving and polishing or other low temperature processes as described above. This ion implantation of atomic species, such as hydrogen, to form layer transfer separation planes and subsequent cleaving or thinning is called "ion cutting". Referring to FIG. 8 , the acceptor wafer 13710 has the same meaning as the aforementioned wafer 808 .

The remaining N+ doped layer 13704 and P- doped layer 13706 and oxide layer 13702 have been layer transferred to the acceptor wafer 13710 as shown in FIG. 137C . The top surface of the N+ doped layer 13704 can be smoothed by chemical or mechanical polishing. Therefore, FG and other transistors can be produced by low temperature (less than 400°C) process and aligned to the acceptor wafer 13710 alignment marks (not shown). Oxide layers, such as 13702, used to aid in wafer-to-wafer bonding are not shown in the subsequent drawings for clarity of illustration.

As shown in FIG. 137D , transistor isolation regions are lithographically defined, and a plurality of N+ doped layers 13704 and P- doped layers 13706 are removed via plasma/RIE etching to at least the oxide above the acceptor substrate 13710 . A low temperature interstitial oxide is then deposited and chemical mechanically polished, leaving transistor isolation region 13720 and southwest to southeast isolation region 13721. "Southwest" in the accompanying drawing 137 represents the position where the switching transistor is formed, while "southeast" represents the position where the sensing transistor is formed, thus producing the N+ doped layer 13714 and the P-doped layer 13716 in the southwestern region of the future transistor , and N+ doping 13715 and P-doping 13717 in the southeast region of future transistors

As shown in Figure 137E, the southwest recessed channel 13742 and the southeast recessed channel 13743 can be lithographically defined and etched to remove N+ doping 13714 and P- doping 13716 in the southwest region of future transistors, and N+ doping in the southwest region of future transistors. Doped 13715 and P-doped 13717. The surface and corners of the recessed trenches can be flattened by wet chemical or plasma/RIE etching processes to mitigate high field effects. The southwest recessed trench 13742 and the southeastern recessed trench 13743 are separately or simultaneously mask defined and etched. The southwest channel width is larger than the southeast channel width. These process steps form the southwest source and drain region 13724 , the southeast source and drain region 13725 , the southwest transistor channel region 13716 and the southeast transistor channel region 13717 .

As shown in Figure 137F, the tunnel construction medium 13711 is formed and the floating door material is deposited. Tunnel construction medium 13711 is an atomic layer deposition (ALD) medium. Or tunnel construction dielectric 13711 to form low temperature oxide deposition or low temperature microwave plasma oxidation of silicon surface. Then the floating gate material, such as doped polycrystalline or amorphous silicon, is deposited. Finally, the floating gate material is chemically mechanically polished, while the floating gate 13752 is partially or fully formed by lithographic definition and plasma/RIE etching.

As shown in Figure 137G, interpoly dielectric body 13741 is produced by low temperature oxidation and dielectric deposition or multi-layer dielectric, such as oxide-nitride-oxide (ONO) layer, and the control gate material, such as doped polycrystalline or amorphous Silicon, deposited. After the control gate material is chemically mechanically polished, the control gate 13754 is produced by lithographic definition and plasma/RIE etching. The etching range of the control gate 13754 also includes a plurality of polysilicon interlayer dielectric bodies and the floating gate 13752 using a self-aligned stack etching process. Logic transistors for control functions are created (not shown) by employing 3D IC compatible methods described herein (eg, RCAT, V-grooves and contacts, and through-layer vias), and interconnect metallization is constructed thereby. This process enables monocrystalline silicon 1T NVM FPGA configuration components to be built in prefabricated wafer-sized doped layers transferred from a single layer, and the doped layers are generated and connected to the underlying multi-metal layer at high temperatures without exposing the underlying components semiconductor components.

Those of ordinary skill in the art appreciate that the illustrations in Figures 137A to 137G are for illustration purposes only and thus are not drawn to scale. Those skilled in the art will further appreciate that many variations are possible, such as floating gates incorporating silicon nanocrystals and other materials. Additionally, a generic device can be created by removing the isolation region 13721 in the southwest to southeast direction. In addition, the slope of the recess of the channel transistor is 0-180 degrees. Also, logic transistors and components can be created by using control gates as component gates. Formation of logic component gates and control gates can be done separately. What needs to be added is that 1T NVM FPGA configuration components can be produced through charge trap technology NVM, anti-memory technology, and can also have junctionless SW or SE transistor structures. Many other modifications within the scope of the present invention will be recommended in due course by these professionals after careful reading. The scope of the invention is therefore only as defined by the appended claims.

Those skilled in the art also know that the present invention is not limited to what has been specifically described above. Rather, those skilled in the art upon reading the foregoing will find that the scope of the present invention includes combinations and sub-combinations as well as modifications and variations of the various features described herein. The scope of the invention is therefore only as defined by the appended claims.

19C10‧‧‧Chip

19C12‧‧‧through silicon via

19C14‧‧‧primary silicon

19C20‧‧‧Chip

19C22‧‧‧through silicon via

19C24‧‧‧primary silicon

19C30‧‧‧Chip

19C32‧‧‧through silicon via

19C34‧‧‧primary silicon

19C40‧‧‧Bump

Claims (20)

A method of manufacturing a 3D semiconductor wafer, the method comprising: providing a first wafer comprising a first semiconductor substrate, wherein the first semiconductor substrate comprises a plurality of first transistors; providing a second wafer comprising a second semiconductor substrate , wherein the second semiconductor substrate includes a plurality of second transistors, and the second semiconductor wafer is transferred and bonded on top of the first semiconductor wafer, wherein the bonding is hybrid bonding; and then the second Wafer thinning to less than twenty microns, wherein the hybrid bonding comprises oxide-to-oxide direct bonding and metal-to-metal direct bonding, and wherein the metal-to-metal direct bonding comprises copper-to-copper bonding, and wherein the oxide-to-oxide The physical bond and the metal-to-metal bond are formed in the same steps. The method according to claim 1, further comprising: forming a via hole through the second semiconductor substrate, wherein the via hole has a diameter smaller than one micron. The method described in claim 1, wherein the first wafer includes a memory cell array, and wherein the second wafer includes a control circuit that controls the memory cell array. The method described in claim 1, wherein the second wafer includes a memory cell array, and wherein the first wafer includes a control circuit that controls the memory cell array. The method of claim 1, wherein the second transistor is aligned with the first transistor with an alignment error of less than 600 nm. The method of claim 1, further comprising: forming a first plurality of connections to a first external device; and forming a second plurality of connections to the first external device or a second external device, wherein the first At least some of the plurality of connections are above the second transistors, and wherein at least some of the second plurality of connections are below the second transistors. A method of manufacturing a 3D semiconductor wafer, the method comprising: providing a first wafer comprising a first semiconductor substrate, wherein the first semiconductor substrate comprises a plurality of first transistors; providing a second wafer comprising a second semiconductor substrate , wherein the second semiconductor substrate includes a plurality of second transistors, and the second semiconductor wafer is transferred and bonded on top of the first semiconductor wafer, wherein the bonding is hybrid bonding; and then thinning the second wafer, wherein the hybrid bonding comprises oxide-to-oxide direct bonding and metal-to-metal direct bonding, wherein the metal-to-metal direct bonding comprises copper-to-copper bonding, wherein the oxide-to-oxide bonding and the Metal-to-metal bonding is formed in the same steps, where the second semiconductor substrate includes through-silicon vias, and where the vias have a diameter of less than one micron. The method as described in claim 7, wherein the thinning is less than 20 microns. The method of claim 7, wherein the first wafer includes a memory cell array, and wherein the second wafer includes control circuits that control the memory cell array. The method according to claim 7, wherein the second wafer includes a memory cell array, and wherein the first wafer includes a control circuit that controls the memory cell array. The method of claim 7, wherein the second transistor is aligned with the first transistor with an alignment error of less than 600 nm. The method of claim 7, further comprising: forming a first plurality of connections to a first external device; and forming a second plurality of connections to the first external device or the second external device connections, wherein at least some of the first plurality of connections are above the second transistors, and wherein at least some of the second plurality of connections are below the second transistors. A method of manufacturing a 3D semiconductor wafer, the method comprising: providing a first wafer comprising a first semiconductor substrate, wherein the first semiconductor substrate comprises a plurality of first transistors; providing a second wafer comprising a second semiconductor substrate , wherein the second semiconductor substrate includes a plurality of second transistors, and the second semiconductor wafer is transferred and bonded on top of the first semiconductor wafer, wherein the bonding is a hybrid bond; and then thinning the first semiconductor wafer Two wafers, wherein the hybrid bonding comprises oxide-to-oxide direct bonding and metal-to-metal direct bonding, wherein the metal-to-metal direct bonding comprises copper-to-copper bonding, wherein the oxide-to-oxide bonding and the metal-to-metal bonding Formed in the same step, the second transistor is aligned with the first transistor with an alignment error of less than 600 nm. The method of claim 13 of the scope of the patent application further includes: forming a through hole passing through the second semiconductor substrate, Wherein the through hole has a diameter less than one micron. The method of claim 13, wherein the first wafer includes an array of memory cells, and wherein the second wafer includes control circuitry that controls the array of memory cells. The method of claim 13, wherein the second wafer includes a memory cell array, and wherein the first wafer includes a control circuit that controls the memory cell array. The method of claim 13, wherein the thinning is performed to less than twenty microns. The method according to claim 13, further comprising: forming a first plurality of connections to a first external device; and forming a second plurality of connections to the first external device or a second external device, wherein the first At least some of the plurality of connections are above the second transistors, and wherein at least some of the second plurality of connections are below the second transistors. The method described in claim 7, wherein at least one of the second transistors is a vertical transistor. The method according to claim 13, wherein at least one of the second transistors is a vertical direction transistor.

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