TW201937692A - System comprising a semiconductor device and structure - Google Patents

Abstract

A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

Description

 System with semiconductor device and structure    Cross-reference to patents  

The present invention is entitled to the benefit of the above-referenced U.S. Patent Nos. 12/577,532, 12/706,520, 12/792,673, 12/797,493, 12/847,911, 12/849,272, 12/859,665, the disclosure of which is incorporated herein by reference. .

The present invention relates to the general field of integrated circuit (IC) components and fabrication processes, particularly the general field of multilayer/three-dimensional integrated circuit (3D IC) components and fabrication processes.

Semiconductor manufacturing increases component density at an exponential rate over time, but this improvement comes at a price. That is, the mask composition of each new process technology will also increase exponentially. Twenty years ago, the cost of a mask group was less than $20,000, and today's latest technology mask group typically costs $1 million.

These changes have created greater challenges for custom products, with smaller capacity and a single market for custom components, and will be subject to ever-increasing product development costs and even difficult steps.

Custom integrated circuits can be divided into two market segments: the first is that all layers of the product are custom components. The second is that the product layer is a common layer that can be applied to different customized products. Among the second products, there are well-known gate arrays, that is, all layers use a common layer up to the contact layer, the contact layer completes the connection between the germanium component and the metal conductor, and there is a programmable gate array (FPGA), all layers are It is a general layer. The general-purpose layers of the above components are almost entirely in a repetitive arrangement, called a main piece, in the form of an array.

Logic array technology is based on a common structure that can be customized for a specific design during the customization phase. Customization of an FPGA is usually done using electrical signal programming. For gate arrays, modern structures are often referred to as structured dedicated integrated circuits (or structured ASICs), and customization requires at least one custom layer, either by direct writing of the electron beam or by a custom mask. Since the number of logic and memory and I/O module types of the design may vary widely, vendors of logic arrays typically produce a product line, each product having a different number of masters, including a series of logic chips, Different sizes of storage chips and I/O chip configurations are available for customers to choose from. However, the determination of the smallest master group has always been a challenge, and the appropriate master group can be well adapted to large-scale designs, and if each product requires a special mask group, it will lead to cost increases.

U.S. Patent 4,733,288, issued to Sato in March 1977, discloses a method of fabricating a gate array LSI wafer that can be wafer-cut in pairs, each wafer having a desired size and number of gates in accordance with the circuit design. Sato is referenced in the reference of this patent, which provides several methods for utilizing common layers for custom components of different sizes.

The array structure meets the requirements of different sizes. The difficulty in providing different sized array structures is the need to provide I/O wafers and corresponding pads to connect the components to the packaged wafer set. To overcome this limitation, Sato suggests a method in which an I/O chip can be built using a transistor of a general logic gate. Anderson also suggests a similar method, which is assigned to Anderson et al. on July 8, 1993, to U.S. Patent No. 5,219,916, the disclosure of which is incorporated herein by reference. Types of wafers are used as logic chips to provide input and output functions. Accordingly, the input and output functions can also be placed around the logic array, the size of which depends on the application. A serious limitation of this method is that the I/O chip must use the same transistor as the logic chip, so the operating voltage of the I/O chip cannot be increased.

U.S. Patent No. 7,105,871 to Or-Bach et al., issued Sep. 12, 2006, discloses a semiconductor device including an unbounded logic array and a local I/O wafer. The logic array can contain a core of repetition and at least one local I/O that can be used as configurable I/O.

In the past, it was common to design a configurable I/O chip to meet different customer needs. The growing demand for higher data rate I/O has driven the development of dedicated serial I/O circuits called SerDes (serializer/serial-to-parallel converter) transceiver chips. These circuits are very complex and require a larger area of the chip than conventional I/O chips. Thus, different configurations are implemented by a different number of logic circuits, different numbers and types of memory chips, and different numbers and types of I/O chips. This means that even with the current technology's unbounded logic array, multiple expensive mask sets are still required.

Today, the most common FPGA chips on the market are based on static random access memory (SRAM) as a programming component. Floating gate flash memory programmable components also have some applications. There are also a small number of FPGAs that use anti-fuse storage as a programmable component. The first generation of anti-fuse storage FPGAs used anti-fuse storage directly embedded in the germanium substrate. The second generation moved the anti-fusing storage to a metal layer called metal-metal anti-fuse storage. The anti-fuse storage function is like a programmable via. However, unlike vias made of the same metal and used for interlayer connections, anti-fusing storage typically uses amorphous germanium and some interfacial layers. Although, theoretically, anti-fuse storage can support higher densities than SRAM, SRAM FPGAs have become the mainstream of today's market. In fact, it seems that no one has continued to develop the anti-fuse storage FPGA component. One of the serious problems with anti-fuse storage is the lack of reprogrammability. Another drawback is the specialized niobium production process required for anti-fusing storage, which requires additional R&D costs and results in a time lag relative to the benchmark IC technology calibration.

The drawback of common FPGA technology is their relatively inefficient use of the cymbal. While end users only focus on whether their components can perform the functions they want, the functional programming features of the FPGA require that most of the area of the chip be used for programming and program verification.

Some of the cases of this invention will seek to overcome the limitations of the current technology by using a special type of transistor on or under the anti-fuse storage programmable interconnect circuit to achieve additional functions, making the use of the slap area more effective.

One type of transistor is a thin film transistor commonly known in the art, also known as TFT. Thin film transistors have been proposed and used for more than 30 years. One of the more well-known applications is on the screen, where the TFTs are placed on the glass surface as a screen. Another type of transistor can also be fabricated onto an anti-fuse storage programmable interconnect circuit, known as a vacuum field effect transistor (FET), as proposed by U.S. Patent 4,721,885, 30 years ago.

The remaining technologies available include insulating germanium (SOI) technology. In U.S. Patents 6,355,501 and 6,832,826, each of which is assigned to IBM, proposes a multilayer 3-dimensional complementary metal oxide semiconductor (CMOS) integrated circuit. The patent proposes to bond a thin layer of SOI wafers on an SOI wafer, form another IC on one IC, and then connect the two circuits through a via via or a via via (TLV). Substrate manufacturer Soitec SA, Bernin, France, is now able to offer this technology by stacking a processed thin-layer wafer on a bottom wafer.

It is not uncommon to integrate a surface transistor on an insulating layer of the IC because the existing process results in a lower quality and density of the surface transistor than the underlying (substrate) layer. The substrate can use single crystal germanium, which is an ideal method for manufacturing high density and high quality transistors, and is also a preferred solution. It is also proposed in the patented invention to use a transistor to construct a memory wafer, such as U.S. Patent Nos. 6,815, 571, 7,456,563; and some SRAM-based FPGAs, such as U.S. Patents 65,515,511 and 7,265,421.

The patent case is intended to achieve a higher density of anti-fuse storage programmable logic wafers by taking advantage of the surface transistor. Another advantage of this is that by using a custom mask instead of the anti-fuse storage function, a way to further reduce the cost of mass production can be achieved, thereby eliminating the need for a surface anti-fuse storage logic wafer.

In addition, some of the cases in the present invention provide a new alternative to multi-layer 3D IC technology. As chip-mount interconnects become a limiting factor in component expansion performance and power boost, 3D ICs may be an important technology for future IC chips. Currently, the only packaging technology that 3D ICs can use is the via straight through hole (TSV). The problem with TSV is that the vias are relatively large (each area is a few microns) and can cause a large vertical connection. The invention patent may be able to provide a number of different alternatives for the 3D IC, improving the vertical connection to some extent.

Building a future 3D IC will require a new structure and a new mindset. In particular, to solve the problem of capacity and stability of its complex 3D systems, the biggest challenge facing the current sub-micron-generation process is to build the complexity and stability of complex ASICs.

Fortunately, current testing techniques are likely to prove suitable for 3D IC manufacturing, although the methods implemented may vary widely. Figure-116 shows the existing group scan architecture used in the 2D IC ASIC 11600. ASIC functions appear in logic clouds 11620, 11622, 11624, and 11626, separated by contiguous wafers, such as in the form of double flip flops appearing in 11612, 11614, and 11616. The ASIC 11600 also has an input pad 11630 and an output pad 11640. Triggers are usually equipped with circuitry so that they can be used as shift registers in test mode. In Figure 116, the flip-flops form a chain of scan registers such that pairs of flip-flops 11612, 11614, and 11616 are combined with scan test controller 11610 to form a sequence. Figure 116 shows a scan chain, but in the actual design contains millions of triggers and many sub-chains.

In the test structure of Figure 116, the test partition is shifted into the scan chain in test mode. This portion is then placed into the run mode during one or more clock cycles, after which the contents of the trigger are removed and compared to the expected result. Although the number of test partitions can be very large in the actual design and it is possible to use an external tester, this can provide a great way to isolate errors and diagnose problems.

Figure-117 shows a prior art boundary scan architecture shown as an example of an ASIC 11700. The functionality of this portion is displayed in logic function block 11710. There are also various input/output wafers 11720 in this section, each wafer including a bond pad 11722, an in/out buffer 11724, and a 3-state output buffer 11726. The boundary scan register chains 11732 and 11734 are both connected to the scan test control block 11730 in a chain. Such an architecture has a similar mode of operation as the group scan architecture of Figure 116. The test partition is moved in, the part starts timing, and the result is removed and compared with the expected result. Typically, group scans and boundary scans are used together in the same ASIC to form a complete test range.

Figure 118 shows the existing built-in self-test (BIST) architecture for testing logic block 11800, which contains a core block function 11810 (ie, tested chalk), input 11812, output 11814, and a BIST controller. 11820, an input linear feedback shift register (LFSR) 11822, and an output cyclic redundancy check (CRC) circuit 11824. Under the control of the BIST controller 11820, the LFSR 11822 and CRC 11824 are initialized (i.e., given a known initial value), block 11800 begins counting at a preset number of times, while the LFSR 11822 sends the pseudo-random test partition to the input of function block 11810, and The CRC 11824 detects the output of the function block 11810. After a predetermined clock cycle, the contents of CRC 11824 are compared to the expected value (or signature). If the signatures match, function block 11800 passes the test and will be considered to be working properly. This type of test is useful for fast "pass" or "fail" tests because the test is independent of the function block being tested and does not require classification of a large number of test partitions or use of an external tester. BIST, group scanning, and boundary-scan techniques are often combined in a complementary manner for use on the same ASIC. A detailed theoretical discussion of LSFR and CRC can be found in pages 432-447 of Digital System Testing and Testability Design. The author of the book is Abramovici, Breuer & Friedman, Computer Science Press, 1990.

Another technology for solving 3D IC capacity and reliability issues is triple module redundancy (three-mode redundancy). The technology uses three layers of redundancy to implement the circuit design and compare the results. Since the output of two or three circuits is always the same (such as a binary signal), the voting circuit (or most of the three /MAJ3) will have this same output as a result. Although this technology is mainly used in systems with high reliability requirements or high radiation resistance requirements, such as military, aerospace and space applications, it can also be used to cover faulty circuit faults, as long as any two of the three The circuit is normal and all functions of the system will work normally. A discussion of the radiation resistance of the TMR system, Single Event Effect (SEE), Single Event Upset (SEU), Single Event Transient (SET) can be found in US Patent Application Publication No. 2009/0204933, to the assignee Rezgui.

According to some cases of this invention, 3D technology can also form a very novel IC alternative, which can reduce R&D costs, increase production capacity, and bring other advantages.

The case of the present invention aims to find a most effective new process for the manufacture of semiconductor components for customized products. The case of the present invention suggests the use of reprogrammable anti-fuse storage and "Through Straight Through Hole (TSV)" to build a new programmable logic, ie, an FPGA component. The case of this invention may provide a solution to the high mask composition and low flexibility challenges faced in existing semiconductor fabrication general processes. Another advantage of some of the cases in this invention is the ability to reduce the high cost of manufacturing different mask sets, which can provide a series of commercial logic components and product lines such that each product has a different master set. The case of the present invention should be able to be improved in various aspects of the prior art, including the manner in which the semiconductor components are constructed, and the manufacturing process of the associated semiconductor components.

The case of this invention reflects efforts to save mask costs on the basis of existing investments, otherwise a set of commercial masters would need to be produced. The case of the present invention also seeks to include the ability to store different types of memory blocks on a configurable component. The case of the present invention provides a process for constructing a configurable component and can include the required number of logic, memory, I/O, and analog functions on the component.

In addition, the case of the present invention can also use a repeating logic board (LT) to provide a continuously distributed logic. The case of the present invention shows that a modular approach can be used to construct different configurable systems by means of a straight through hole (TSV). Once the standard size and position of the TSV is defined, one can create different configurable logic chips, set up memory chips, set up I/O chips, set up analog circuit chips, and then connect them to build different ones. Set the system. In fact, different programmable wafer mixes, hybrid functional wafers, and wafers fabricated using different processes can be fabricated.

Some of the examples of this invention will bring other advantages, such as the use of a special type of transistor above or below the anti-fuse storage settable circuit, making the use of the slab area more efficient. Typically, FPGA components use anti-fuse storage to set the functionality of the component, and may also include electronic circuitry that can be programmed against melt storage. The programming circuit can first be used to configure the component and, once the system is set up, becomes a system expense most of the time. The voltage used to program the anti-fuse storage is typically much larger than the operating voltage of the component circuit. The anti-fusing storage structure is designed to achieve an unused anti-fuse storage that does not melt easily. Therefore, programming the anti-fuse storage to include a high voltage that may require extra care programming on the germanium substrate may result in the need to dispense an additional wafer.

In order to meet the performance requirements of high speed components, the maximum requirement for a working transistor is speed, while the programming circuit can operate at a relatively low speed. Therefore, the programming circuit can use a thin film transistor, which can well meet the functional requirements and reduce the need for the area of the cymbal.

The programming circuit can be constructed with a thin film transistor that can be processed on a settable interconnect layer after the fabrication of the working circuit, and the interconnect layer contains and uses anti-fuse storage. Another advantage of the inventive case is the ability to reduce the cost of mass production. One might only need to use a mask-defined connection instead of an anti-fuse storage and programming circuit. It is also possible to use a custom via mask, which reduces the steps involved in fabricating a refractory storage layer, a thin film transistor, and/or a programming circuit interconnect layer.

According to the case of the present invention, the integrated circuit component is provided to include an anti-fuse settable interconnection circuit and a pair of transistors for setting one of the above anti-fuse storages, and the manufacture of the transistor is in anti-fuse storage. After that.

Further in accordance with the case of the present invention, the integrated circuit assembly is provided to include an anti-fuse settable interconnection circuit and a pair of transistors for setting one of the anti-fuse storages described above, and the manufacture of the transistor is anti-melting Storage is at least processed.

Still further in accordance with the present invention, the integrated circuit assembly includes a second anti-fuse storage settable logic chip and a pair of second transistors for setting one of the second anti-fuse stores, The fabrication of the second transistor is completed after the anti-fuse storage.

Similarly, in accordance with the case of the present invention, the integrated circuit assembly includes a second anti-fuse storage programmable logic chip and a pair of second transistors for setting one of the second anti-fuse storages. The second transistor is disposed below the second anti-fuse storage.

In accordance with the teachings of the present invention, the integrated circuit assembly includes a first refractory storage layer having at least two metal layers thereon and a second refractory storage layer over the two metal layers.

According to the case of the present invention, a configurable logic component includes: an anti-fuse storage can be set to look up the table logic, and the interconnection circuit can be set through the anti-fuse storage.

In accordance with the teachings of the present invention, a configurable logic component includes: a set-table logic that can be set up for the anti-fat storage, and a pair of programmable logic array (PLA) logic that can be set up to form an anti-fuse storage interconnect circuit.

In accordance with the teachings of the present invention, a configurable logic component includes: a tableware logic that can be set up for the anti-fat storage, a set of drive chips that can be set, and the wafers set by the anti-fuse storage.

According to the case of the present invention, a configurable logic component includes: a configurable logic chip, the interconnect circuit connection can be set by the anti-fuse storage, and at least one anti-fuse storage setting connection circuit in the circuit is configured through a permanent memory.

Still in accordance with the inventive example, a configurable logic component includes at least one anti-fuse storage interconnect circuit and can be set via the PLA function.

In accordance with an alternative embodiment of the present invention, an integrated circuit system includes: a configurable logic die and an I/O die connected to the I/O die using a via straight via (TSV) .

Still in accordance with an alternative to this invention, an integrated circuit system includes a configurable logic die and a memory die that are connected using a slap straight through hole (TSV).

Still in accordance with an alternative to the present invention, an integrated circuit system includes: a first settable logic die and a second settable logic die, the first settable logic die and the second settable logic die being directly through the die Vias (TSV) are connected.

Also, in accordance with the case of the present invention, the integrated circuit system includes an I/O chip which is fabricated using a different process, and the manufacturing process is different from the process of setting the logic chip.

Still in accordance with an alternative to the present invention, an integrated circuit system includes at least two logic chips connected through a through-wafer through-hole (TSV), and a plurality of segments are passed straight through the holes for transmitting system bus signals.

In accordance with the teachings of the present invention, an integrated circuit system includes at least one configurable logic component.

Still in accordance with an alternative to this invention, an integrated circuit system includes an anti-fuse storage configurable logic die and a programming die that are connected using a slap straight through hole (TSV).

In addition, there is a growing demand for reducing the impact of inter-wafer interconnect circuits. In fact, at present, interconnected circuits have become a major factor in IC performance and power. 3D IC is a way to shorten the interconnection circuit. Currently, for general purpose logic 3D ICs, it is known to use a chip straight through hole (TSV) to stack the fabricated components. The problem with TSV is that the vias are relatively large, each having an area of a few microns, which can severely limit the number of TSVs that can be used. Some examples of this invention present multiple alternatives for building 3D ICs. Many connections (TSVs) can be made smaller than 1 micron in size, making 3D IC technology available for most components.

In addition, the use of the 3D IC technology proposed in the present invention can also provide an alternative to the production of new components.

860-1~860-4‧‧‧Programmable transistor

820-1, 1~820-2, 2‧‧‧ anti-fuse

830-1‧‧‧Metal

850-1,1,850-1,2‧‧‧Anti-fuse

310-1~310-4‧‧‧Metal strip

308-1~308-4‧‧‧Metal strip

312-1~312-4‧‧‧Anti-fuse

300,320‧‧‧ porcelain

302‧‧‧Y selection logic

304‧‧‧Y programmable transistor

306‧‧‧Programmable voltage

314‧‧‧ Grounding

316‧‧‧X selection logic

318‧‧‧X programmable transistor

300B‧‧‧programmable interconnect structure

308-4B1, 308-4B2‧‧‧ Shorter

312-3B, 312-4B‧‧‧Anti-fuse

318B, 318B1‧‧‧X programmable transistor

402,404,408,412‧‧‧Metal strip

406,410‧‧‧Anti-fuse

502‧‧‧ Input

504‧‧‧Inverter

506‧‧‧ output

510‧‧ ‧Inverter

512‧‧‧ input

514‧‧‧buffer

516‧‧‧ Output

520‧‧‧Anti-fuse configurable drive unit

522‧‧‧Enter

524‧‧‧Configurable intensity buffer

524-1, 524-3‧‧ ‧ buffer

526‧‧‧ output

528-1~528-3‧‧‧Anti-fuse

530‧‧‧Delay trigger unit

532-2‧‧‧ Input

532-1, 532-3~532-5‧‧‧ Control input

534‧‧‧Delay trigger

536‧‧‧ output

600‧‧‧Logical components

602-1~602-4‧‧‧ Input

602-6, 602-7‧‧‧ extra input

604‧‧‧Check the information sheet 4

604-5‧‧‧2:1 multiplexer

606‧‧‧ output

608-1‧‧‧Anti-fuse

6A00‧‧‧Programmable Logic Array Logic Unit

6A01‧‧‧Anti-fuse

6A02‧‧‧ input value

6A06‧‧‧ output

6A14‧‧‧Multiple input and

6A15‧‧‧Multiple input or

700‧‧‧programmable unit

701‧‧‧Anti-fuse

701HV‧‧‧Anti-fuse

701VV‧‧‧Anti-fuse

701HH‧‧‧Anti-fuse

702‧‧‧ input value

706‧‧‧ Output value

708‧‧‧Input and output strips

710‧‧‧ logical unit

720‧‧‧Configurable interconnect structure

722V‧‧‧Separator

722H‧‧ ‧ level bar

724‧‧‧ long strip

724LH‧‧‧Anti-fuse

802‧‧‧Base

804‧‧‧First layer anti-fuse

806‧‧ ‧

807‧‧‧Second layer anti-fuse

808‧‧‧Pretreatment of crystal or layer

808A, 808B, 808C‧‧‧Pretreatment of crystal or layer

809,809A,809B‧‧‧Transport layer

810‧‧‧Configurable interconnect structure

812‧‧‧Connected to the outside

814‧‧‧Priority line

816‧‧‧Contact connection

402‧‧‧Base

404‧‧‧Direct Through Piercing (TSV)

102‧‧‧Ceramic bubble

102-1‧‧‧Ceramics

102-2‧‧‧Ceramics

104‧‧‧ lines

104-1‧‧‧Possible scribe lines

104-2‧‧‧ Possible scribe lines

106‧‧‧serializer four-core wire

108‧‧‧Scratch block

1100A‧‧‧Programmable logic fragments

1101‧‧‧Ceramics

1102‧‧‧ Possible scribe lines

110B‧‧‧Structured ASIC

1102‧‧‧ Possible scribe lines

1100C‧‧‧RAM tiles

1100D‧‧‧ DRAM tiles

1100E‧‧‧Microprocessor or microcontroller core

1100F‧‧‧I/O value fragmentation

1202A‧‧‧ base

1204A‧‧‧ wafer

1206A‧‧‧ wafer

1208A‧‧‧ wafer

1202B‧‧‧ base

1204B‧‧‧ wafer

1206B‧‧‧ wafer

1202C‧‧‧ base

1202D‧‧‧ base

1202E‧‧‧ underlying wafer

1204E‧‧‧ wafer

1206E‧‧‧ wafer

1208E‧‧‧ wafer

1402‧‧‧ wafer

1404‧‧ layer

1406‧‧‧ donor wafer

1408‧‧‧Intelligent cutting line

1410‧‧‧3D Wafer

1412‧‧‧Oxide layer

1414‧‧‧Top part

1501, 1502‧‧‧programmable crystal

1504‧‧‧Anti-fuse

1506, 1508‧‧‧programmable connection

1601, 1602‧‧‧Isolated transistor

1603‧‧‧Control lines

1604‧‧‧Anti-fuse

1606, 1608‧‧‧Logical Crystals

1610‧‧‧Anti-fuse

1710‧‧‧ partition

1711‧‧‧Reward bias circuit

1720‧‧‧Feeding bias stage control circuit

1721‧‧‧Voltage generator

1723, 1724‧‧‧ Connection

1725‧‧‧Negative voltage generator

1726‧‧‧Positive voltage generator

1727, 1729‧‧‧ oscillator

1732‧‧‧N-channel metal-oxide-semiconductor transistor

1734‧‧‧P-channel metal-oxide-semiconductor transistor

17C02‧‧‧Power Control Circuit Unit

17C04‧‧‧Control circuit

17C08, 17C10‧‧‧

17C12‧‧‧Power cord

17C16‧‧‧Master equipment

17D02‧‧‧Sequential active circuit components

17D06‧‧‧Interconnection line

17D08‧‧‧High impedance probe circuit

17D12‧‧‧Selection circuit

17D14‧‧‧ probe output signal

17D16‧‧‧ buffer

1802‧‧‧SRAM unit

1806, 1808‧‧‧ logic circuits

1812‧‧‧Connect

1912‧‧‧Output drive

1914‧‧‧Input/output connections

1916‧‧‧Input protection circuit

1920‧‧‧ input logic

1922‧‧‧buffer

1924‧‧‧Connect

19B06‧‧‧ PMOS and NMOS output transistors

19B08‧‧‧Back wafer or wafer bump

19B10‧‧‧through through crystal perforation

19C10‧‧‧ wafer

19C12‧‧‧through through crystal perforation

19C14‧‧‧ Primary crystal

19C20‧‧‧ wafer

19C22‧‧‧through through crystal perforation

19C24‧‧‧ Primary crystal

19C30‧‧‧ wafer

19C32‧‧‧through through crystal perforation

19C34‧‧‧ Primary crystal

19C40‧‧‧ bumps

19D02‧‧‧heatsink

19D04‧‧‧Homothermal substrate

19D06‧‧‧Intermediate

19D08‧‧‧through hole

19D12‧‧‧Hot film

19D14‧‧‧Microprocessor effective area

19D16‧‧‧ Foundation

19D18‧‧‧Multiple Compression DRAM

19D20‧‧‧through through crystal perforation

19D22‧‧‧through through crystal perforation

19D24‧‧‧DRAM stacking

19E24‧‧‧Wire welding

19E26‧‧‧ redistribution layer

19F00‧‧‧Nu perforation

19F01‧‧‧ buried oxide

19F02‧‧‧Substrate wafer

19F03‧‧‧Nu contacts

19F04‧‧‧Dnu contacts

19F05‧‧‧矽

19G00‧‧‧ body disc

19G02‧‧‧DTSV_Previous Technology

19H04‧‧‧ donor image

19H05‧‧‧ Surface

19H06‧‧ depth

19H07‧‧‧Nu perforation

19H08‧‧‧Acceptor Wafer

19H10‧‧‧ donor image section

19I09‧‧‧ processor

19I10‧‧‧DRAM

19I11‧‧‧heatsink

19I12‧‧‧Base

19I13, 19I14‧‧‧ Straight-through splicing connection

19J01‧‧‧Base

19J02‧‧‧Top layer

2002‧‧‧Preliminary processing of wafers

2004‧‧‧Additional layer

2006‧‧‧ donor wafer

2008‧‧‧Intelligent cutting line

2010‧‧‧3D Wafer

2011‧‧‧BEOL layer

2012‧‧‧Oxide layer

2014‧‧‧Top section

2019‧‧‧Semiconductor layer

2102‧‧‧P-type wafer

2104‧‧‧N type picture

2106‧‧‧P-epitaxial growth

2108‧‧‧P+ layer

2110‧‧‧Cleavage

2112‧‧‧Oxide

22B02‧‧‧Gate designated area

22B04‧‧‧Top transistor source

22B06‧‧‧Top transistor drain

22B08‧‧‧Isolated Area

22C02‧‧‧Low temperature oxide

22D02‧‧‧The gate is formed by self-aligned etching process

22D04‧‧‧Source and drain extensions

22E02‧‧‧Low temperature gate dielectric

22F02‧‧‧Metal grid

22G02‧‧‧ Thick Oxide

22G20‧‧‧Optoelectronics

22F02‧‧‧Gate

22F02-1‧‧‧ back gate

2302‧‧‧N-wafer

2304‧‧‧N+ layer

2306‧‧‧Cleavage

2308‧‧‧Oxide

24A04‧‧‧N+ layer

24B02‧‧‧Gate designated area

24B04‧‧‧Top transistor source

24B06‧‧‧Top transistor drain

24B08‧‧•Inter-anode isolation zone

24B09‧‧‧etching space

24C02‧‧•N-layer removed between transistors

24D02‧‧‧Shallow P+ zone

24D04‧‧‧reflective layer

24D06‧‧‧Light

24D08‧‧‧opening area

24D10‧‧‧reflective layer

24E02‧‧‧ Thick Oxide

24E04‧‧‧Photon energy absorption layer

24F02‧‧‧Gate contacts

24F04‧‧‧ Thick Oxide

24F06‧‧‧N+ contacts

2502‧‧‧N-wafer

2504‧‧‧N+

2506‧‧‧Intelligent cutting cleavage plane

2508‧‧‧N-epitaxial growth layer

2510‧‧‧P+ layer

2512‧‧‧Oxide

26B02‧‧‧Gate designated area

26B04‧‧‧Top transistor source

26B06‧‧‧Top transistor drain

26B08‧‧‧Inter-anode isolation area

26C09‧‧•P+ layer removed between transistors

26C12‧‧‧Remove N-layer between transistors

26D02‧‧‧Shallow P+ zone

26E02‧‧‧Gate contacts

26E04‧‧‧ Thick oxide

26E06‧‧‧N+ contacts

26E12‧‧‧Contacts

2702‧‧‧N+ wafer

2704‧‧‧P-layer

2706‧‧‧Intelligent cutting cleavage plane

2708‧‧‧N-layer

2710‧‧‧N+ layer

28A02‧‧‧N+ doped layer

2802‧‧‧ base

2804‧‧‧low temperature oxide

2806‧‧‧ Emitter

2808‧‧‧ Collector

2809‧‧‧Isolation

29B02‧‧‧Transistor isolation

29B04‧‧‧Base P+ source contact opening

29C02‧‧‧Isolated Area

29C04‧‧‧Low temperature oxide

29C06‧‧‧Abrasion suppression layer

29D02‧‧‧ source

29D04‧‧‧Drain

29D06‧‧‧Gate

29D08‧‧‧Source and drain extensions

29E02‧‧‧Gate dielectric

29E04‧‧‧Gate material

29G02‧‧‧ Thick Oxide

29G04‧‧‧Perforation

29G06‧‧‧Bottom interconnection wiring

3000‧‧‧ donor wafer

3000L‧‧‧Transfer layer

3002‧‧‧Inflatable projection

3004‧‧‧n type transistor rows

3006‧‧‧p type transistor row number

3008‧‧ West

3020‧‧‧ alignment mark

3040‧‧‧Four basic orientation indicators

3100‧‧‧Main Wafer

3120‧‧‧ alignment mark

3122‧‧‧North-South DY misalignment

3124‧‧‧DX misalignment

3202‧‧‧ residuals

33A02‧‧‧Perforation

33A04‧‧‧North-South Landing Belt

33B02‧‧‧Perforation

33B04‧‧‧North-South Landing Belt

3400‧‧‧repeated rows

3402‧‧‧P-type wafer

3404‧‧‧N+ layer

3406‧‧‧P+ layer

3408‧‧‧P-epitaxial growth

3410‧‧‧N-zone

3412‧‧‧Shallow P+

3414‧‧‧Shallow N+

3416‧‧‧Intelligent cutting cleavage plane

3418‧‧‧Oxide

3500‧‧‧Basic

3502‧‧‧Cleavage surface

35B02‧‧‧Optical crystal isolation

35B04‧‧‧ metal layer

35B06‧‧‧Base P+

35B08‧‧‧Base N+

35C02‧‧‧Isolated Area

35C04‧‧‧Oxide

35C06‧‧‧Abrasion suppression layer

35D02‧‧‧n type channel source

35D04‧‧‧n type channel drain

35D06‧‧‧n type channel self-aligned gate

35D08‧‧‧p-type channel source

35D10‧‧‧p type channel drain

35D12‧‧‧p-type channel self-aligned gate

35D14‧‧‧P+ angle source and drain extension

35E02‧‧‧Gate dielectric

35E04‧‧‧Metal grid

35G02‧‧‧Oxide

35G04‧‧‧Perforation

3600‧‧‧ wafer

3601‧‧‧Ceramics

3602‧‧‧ Possible scribe lines

3611‧‧‧ Terminal equipment

3612‧‧‧ Actual scribe line

3700‧‧‧ wafer

3701‧‧‧Ceramics

3702‧‧‧Micro Control Unit - MCU

3702-00‧‧‧MCU

3702-01‧‧‧MCU

3702-11‧‧‧MCU

3702-12‧‧‧MCU

3704‧‧‧MCU to MCU connection

3711‧‧‧Ceramics

3714‧‧‧MCU to MCU connection

3800‧‧‧Southwest corner tiles

3802‧‧‧Control input value

3814‧‧‧Time Delay Integration (TDI)

3816‧‧‧Time Delay Integration (TDI)

3820‧‧‧North East Anvil

3822‧‧‧TDO output

3902‧‧‧P-type wafer

3904‧‧‧N+ layer

3906‧‧‧P-layer

3908‧‧‧N+ layer

3910‧‧‧ Conductive barrier

3912‧‧‧Intelligent cutting cleavage plane

3914‧‧‧Al-Ge layer

3916‧‧‧ Conductive barrier

3920‧‧‧Indoor metal layer

4002‧‧‧etch suppression layer

4004‧‧‧ Conductive layer

4006‧‧‧Crystal Tower

4010‧‧‧Oxide

4014‧‧‧ sidewall gate oxide

4018‧‧‧ gate layer

4020‧‧‧Gate Mask Photoresist

4022‧‧‧ spaced gate electrode

4024‧‧‧ gate electrode

4030‧‧‧Oxide

4034‧‧‧Perforated contacts to tower N+

4036‧‧‧perforated contacts to gate electrodes

4040‧‧‧metal wire

4100‧‧‧First layer of programmable layer

4102‧‧‧3*3 tiles

4104‧‧‧Programmable connection

4105‧‧‧ branch programmable connection

4106‧‧‧Programmable components

4107‧‧‧Programmable components

4108‧‧‧Programmable components

4110‧‧‧Second layer of programmable layer

4112‧‧3*3 tiles

4116‧‧‧Programmable components

4117‧‧‧Programmable components

4118‧‧‧Programmable components

4120‧‧‧Layer 3 programmable layer

4122‧‧‧3*3 tiles

4140‧‧‧Vertical connection between floors

4202‧‧‧NMOS transistor

4204‧‧‧PMOS transistor

4206‧‧‧NMOS source

4207‧‧‧PMOS source

4208‧‧‧ NMOS and PMOS drain

4210‧‧‧NMOS & PMOS gate

4300‧‧‧Highly doped N-type single crystal

4301‧‧‧P-layer

4302‧‧‧Resistive layer

4304‧‧‧Oxide

4310‧‧‧P-type wafer

4312‧‧‧Oxide

4314‧‧‧Intelligent cutting cleavage plane

4316‧‧‧Cleavage surface

4400‧‧‧Oxide layer

4402‧‧‧Protective oxides

4404‧‧‧Abrasion suppression layer

4406‧‧‧ NMOS source to ground connection

4410‧‧‧Shallow Trench (STI) Quarantine

4411‧‧‧ Gate oxide

4412‧‧‧ NMOS gate

4414‧‧‧Polysilicon on STI channel interconnects

4416‧‧‧ implant offset interval

4418‧‧‧ NMOS transistor source and drain

4420‧‧‧Oxide

4422‧‧‧ wafer surface

4500‧‧‧Oxide layer

4502‧‧‧N-wafer

4504‧‧‧Oxide

4506‧‧‧Intelligent cutting cleavage surface

4508‧‧‧Cleavage surface

4510‧‧‧Oxide layer

4512‧‧‧Shallow Trench (STI) Quarantine

4514‧‧‧ Gate oxide

4516‧‧‧ PMOS gate

4518‧‧‧Polysilicon on STI channel interconnects

4520‧‧‧ implant offset interval

4522‧‧‧ PMOS transistor source and drain regions

4524‧‧‧Oxide

4530‧‧‧etch suppression and grinding suppression layer

4532‧‧‧ deepest contact

4540‧‧‧ NMOS drain unique contact

4542‧‧‧ NMOS & PMOS gate on STI interconnect contacts

4544‧‧‧ NMOS and PMOS drain contacts

4546‧‧‧ NMOS unique gate on STI contact

4550‧‧‧ PMOS gate interconnection on STI contacts

4552‧‧‧ PMOS unique gate contact

4554‧‧‧PMOS only drain contact

4600‧‧‧STI (shallow trench isolation)

4602‧‧‧NMOS and PMOS gates

4604‧‧‧ NMOS gate to STI contact PMOS gate on STI

4606‧‧‧N+ source contact to ground plane

4608‧‧‧PMOS source contact

4610‧‧‧ NMOS and PMOS drain shared contacts

4702‧‧‧NMOS transistor

4704‧‧‧ PMOS transistor

4706‧‧‧NMOS source

4707‧‧‧ PMOS source connected to +V

4708‧‧‧ PMOS drain

4710‧‧‧NMOS & PMOS gate

4800‧‧‧STI (shallow trench isolation)

4802‧‧‧NMOS and PMOS gates

4804‧‧‧STI on NMOS gate to PMOS gate on STI contact

4806‧‧‧N+ source contact to ground plane

4808‧‧‧PMOS source contact

4810‧‧‧ NMOS and PMOS drain shared contacts

4812‧‧‧ NMOS source contact

4900‧‧‧STI (shallow trench isolation)

4902‧‧‧ PMOS-B gate

4904‧‧‧Virtual grid

4906‧‧‧ PMOS-A gate

4908‧‧‧The only PMOS gate on the STI contact

4910‧‧‧NMOS-A gate

4912‧‧‧NMOS-B gate

4914‧‧‧ NMOS gate to STI contact PMOS gate on STI

4916‧‧‧ NMOS unique gate on STI contact

4918‧‧‧N+ source contact to ground plane

4920‧‧‧PMOS-B source contact

4922‧‧‧ NMOS-A, NMOS-B and PMOS-B drain common contacts

5000‧‧‧STI (shallow trench isolation)

5002‧‧‧NMOS transistor

5004‧‧‧ PMOS transistor

5006‧‧‧NMOS gate input

5008‧‧‧ PMOS gate input

5010‧‧‧ NMOS and PMOS source

5012‧‧‧ NMOS and PMOS drain

5014‧‧‧ PMOS gate

5016‧‧‧ NMOS gate

5018‧‧‧The only PMOS gate on the STI contact

5020‧‧‧Single NMOS gate on STI contact

5022‧‧‧ NMOS and PMOS source common contacts

5024‧‧‧ NMOS and PMOS drain shared contacts

5100‧‧‧Transistor isolation oxide

5102‧‧‧Storage transistor M2

5104‧‧‧Storage transistor M4

5106‧‧‧Word line transistor M6

5108‧‧‧Vdd

5110‧‧‧ Grounding

5112‧‧‧ PMOS polysilicon on STI to NMOS polysilicon on STI contacts

5114‧‧‧PMOS P+ to NMOS N+ contacts

5122‧‧‧ bit line

5124‧‧‧ bit line

5202‧‧‧Curve D=1E18/1E17

5204‧‧‧Curve D=1E17/1E18

5206‧‧‧Curve D=1E18/1E17

5208‧‧‧Curve D=1E17/1E18

5300‧‧‧Transistor isolation oxide

5302‧‧‧SRAM status reading transistor M7, M9

5304‧‧‧Transistors M1, M2

5306‧‧‧Transistors M3, M4

5308‧‧‧Metal to gate on STI contacts

5310‧‧‧PMOS metal-1

5312‧‧‧PMOS metal-1

5314‧‧‧ PMOS polysilicon on STI to bottom NMOS polysilicon on STI contact

5316‧‧‧Test line

5318‧‧‧Detection pole

5320‧‧‧NMOS N+ contacts

5322‧‧‧ Grounding

5324‧‧‧Contacts

5326‧‧‧ Pull-down transistor M8, M10

5330‧‧‧ Grounding

5332‧‧‧Word line transistor M6

5334‧‧‧Vdd

5336‧‧‧ Matching line

5340‧‧‧ bit line

5342‧‧‧ bit line

5402‧‧‧N-wafer

5404‧‧‧N+ layer

5410‧‧‧ Conductive barrier

5412‧‧‧Intelligent cutting cleavage plane

5414‧‧‧ Eutectic bonding

5416‧‧‧ Conductive barrier

5420‧‧‧Indoor top metal wire

5500‧‧‧Metal bonding layer

5502‧‧‧etch suppression layer

5504‧‧‧N+ layer

5506‧‧‧Crystal Tower

5510‧‧‧Oxide

5514‧‧‧Widewall gate oxide

5518‧‧‧P+ doped amorphous germanium

5520‧‧‧Gate Mask Photoresist

5530‧‧‧Oxide

5534‧‧‧Contacts

5536‧‧‧Contact to gate electrode

5540‧‧‧Metal wire

5600A‧‧N-wafer

5602A‧‧‧Gate oxide

5604A‧‧‧N+ layer

5600‧‧‧N-wafer

5602‧‧‧ Gate oxide

5604‧‧‧N+ layer

5606‧‧‧ implant

5608‧‧‧Cleavage

5610‧‧‧N+ layer

5612‧‧‧Gate oxide

5614‧‧‧ parallel lines

5616‧‧‧Gate oxide

5618‧‧‧Polysilicon

5620‧‧‧Oxygen

5608G‧‧‧Cleavage

5622‧‧‧Metal interconnect strips

5624‧‧‧Oxide

5626‧‧‧Abrasion suppression layer

5628‧‧‧Isolation opening

5629‧‧‧ openings

5630‧‧‧Top grid

5632‧‧‧gate contacts

5634‧‧‧Contacts

5636‧‧‧through through hole

5640‧‧‧Metal wire

5700‧‧‧N-wafer

5702‧‧‧Oxide

5704‧‧‧N+

5706‧‧‧Interconnection

5707‧‧‧ implant

5708‧‧‧Cleavage

5710‧‧‧ Gate oxide

5712‧‧‧Gate material

5714‧‧‧Top and side gates

5716‧‧‧Oxide

5720‧‧‧Gate contacts

5722‧‧‧Optoelectronic terminal contacts

5724‧‧‧through through hole

5800‧‧‧N-wafer

5802‧‧‧mask oxide

5804‧‧‧N+ layer

5805‧‧‧CMP and plasma etch suppression layer

5806‧‧‧Metal interconnect layer

5808‧‧‧Optical channel components

5810‧‧‧ Gate oxide

5812‧‧‧Gate material

5814‧‧‧Top and side grids

5816‧‧‧low temperature oxide

5820‧‧‧Gate contacts

5822‧‧‧Channel termination contacts

5824‧‧‧through through hole

5902‧‧‧Transistor layer

5904‧‧‧Contacts

5905‧‧‧Under perforation

5906‧‧‧Upper perforation

5907‧‧‧Perforation

5908‧‧‧Perforation

5909‧‧‧Perforation

5910‧‧‧First metal layer

5912‧‧‧Metal wire

5914‧‧‧Metal wire

5916‧‧‧Metal wire

5918‧‧‧Metal wire

5920‧‧‧Metal wire

5922‧‧‧ Bonding

6000‧‧‧through through hole piercing

6001‧‧‧ perforation

6002‧‧‧Perforation

6003‧‧‧Perforation

6004‧‧‧ perforation

6005‧‧‧ perforation

6006‧‧‧Perforation

6007‧‧‧Perforation

6008‧‧‧ perforation

6009‧‧‧Perforation

6010‧‧‧Contacts

6011‧‧‧metal wire

6012‧‧‧Metal wire

6013‧‧‧metal wire

6014‧‧‧Metal wire

6015‧‧‧Metal

6016‧‧‧ metal layer

6017‧‧‧Metal

6018‧‧‧Metal wire

6019‧‧‧metal layer

6020‧‧‧ metal layer

6022‧‧‧ PMOS layer transfer矽

6024‧‧‧First single crystal or polysilicon device layer

6100‧‧‧N-wafer

6102‧‧‧Oxide

6103‧‧‧N+ bottom layer

6104‧‧‧N+ top

6105‧‧‧ etching hard mask layer

6106‧‧‧Interconnected metal wafers or strips

6107‧‧‧ implant

6108‧‧‧No junction transistor channel

6109‧‧‧Cleavage

6110‧‧‧ Gate oxide

6112‧‧‧Gate material

6114‧‧‧Top and side grids

6116‧‧‧Oxide

6120‧‧‧Gate contacts

6122‧‧‧Transistor source/drain termination contacts

6124‧‧‧through through hole

6150‧‧‧Photoresist

6151‧‧‧ source

6152‧‧‧Drain

6153‧‧‧Channel

6200‧‧‧Transistor isolation oxide

6201‧‧‧ PMOS transistor

6202‧‧‧NMOS transistor

6203‧‧‧Enter A

6204‧‧‧Enter B

6211‧‧‧PMOS source

6212‧‧‧ PMOS B drain

6213‧‧‧ NMOS drain

6214‧‧‧PMOS metal 2

6215‧‧‧PMOS metal 1

6216‧‧‧V+ supply metal

6217‧‧‧ Output Y metal

6218‧‧‧Grounding wire

6220‧‧‧ NMOS A drain

6300‧‧‧Transistor isolation oxide

6301‧‧‧ PMOS transistor

6302‧‧‧NMOS transistor

6303‧‧‧ Input A to PMOS and NMOS Gate A junctions

6311‧‧‧PMOS transistor source

6312‧‧‧NMOS H source

6313‧‧‧ PMOS drain

6314‧‧‧PMOS metal 2

6315‧‧‧ Output Y supply metal

6316‧‧‧V+ supply metal

6317‧‧‧P+ to N+ contacts

6318‧‧‧ Grounding wire

6320‧‧‧ NMOS A source and NMOS B drain junction

6400‧‧‧Transistor isolation oxide

6401‧‧‧ PMOS transistor

6402‧‧‧NMOS transistor

6403‧‧‧ Input A fragment to PMOS A gate and NMOS A gate

6411‧‧‧PMOS H transistor source

6412‧‧‧ NMOS source debris to the ground

6413‧‧‧NMOS source node

6414‧‧S Gate on the STI to the gate of the upper contact of the ST

6415‧‧‧NMOS metal-2

6416‧‧‧V+ supply metal

6417‧‧‧P+ to N+ to PMOS metal-2 contacts

6418‧‧‧NMOS metal-1 line

6420‧‧‧PMOS H drain node

6421‧‧‧PMOS metal 2

6501‧‧‧ donor wafer oxide layer

6503‧‧‧N+ layer

6504‧‧‧Gate dielectric

6505‧‧‧Gate metal

6506‧‧‧Oxide isolation

6508‧‧‧Oxide

6510‧‧‧Contact opening

6700‧‧‧p-矽 wafer

6701‧‧‧Oxide layer

6702‧‧‧N+ layer

6703‧‧‧P-layer

6704‧‧‧ implanted hydrogen layer

6705‧‧‧Oxide isolation zone

6706‧‧‧ recessed channel

6707‧‧‧Gate dielectric

6708‧‧‧Gate

6709‧‧‧low temperature oxide

6710‧‧‧Contacts

6800‧‧‧p-矽 wafer

6801‧‧‧Oxide

6802‧‧‧N+ layer

6803‧‧‧P-layer

6804‧‧‧Hydrogen implantation

6805‧‧‧Oxide isolation zone

6806‧‧‧ interval precipitation

6807‧‧‧Spherical recess

6808‧‧‧Gate dielectric

6809‧‧‧Metal grid

6810‧‧‧Oxide

6811‧‧‧Contacts

6920‧‧‧Copy donor wafer alignment mark

6920C‧‧‧ recent donor wafer alignment mark

6922‧‧‧North-South misalignment

7000‧‧‧ donor wafer

7001‧‧‧矽

7002‧‧‧Isolation

7003‧‧‧sensitive gate area

7004‧‧‧Polysilicon

7005‧‧‧ Gate oxide

7006‧‧‧NMOS source and drain

7007‧‧‧PMOS source and drain

7008‧‧‧Interlayer dielectric

7010‧‧‧ implant

7012‧‧‧Cleavage

7014‧‧‧ Carrier substrate

7016‧‧" interface

7018‧‧‧ donor wafer surface

7020‧‧‧Oxide

7022‧‧‧Oxide surface

7001‧‧‧Pre-treatment of HKMG layer

7024‧‧‧Metal strip

7026‧‧‧High-k gate dielectric

7028‧‧‧ PMOS specific working function metal gate

7030‧‧‧ NMOS specific work engineering metal gate

7032‧‧‧Aluminum filling

7034‧‧‧Gate contacts

7036‧‧‧Source/Drain Contacts

7040‧‧‧through through hole

7050‧‧‧A barrier-inhibiting layer of dense material

7052‧‧‧Photoresist

7104‧‧‧p type transistor line width repeat width

7106‧‧‧p type transistor line width repeat width Wp

7108‧‧‧Total repetition W

7110‧‧‧Transistor isolation

7112‧‧‧Transistor source

7113‧‧‧ PMOS gate

7114‧‧‧Transistor drain

7116‧‧‧Transistor source

7117‧‧‧ NMOS gate

7118‧‧•Transistor drain

7202‧‧‧Isolated area

7215‧‧‧Replacement grid

7218‧‧‧Gate contact landing zone

7220‧‧‧gate connection

7222‧‧‧Source connection

7224‧‧‧Drain connection

7240‧‧‧Interlayer perforation connection

7302‧‧‧Inflatable projection

7304‧‧‧Wy

7306‧‧‧Wx

7308‧‧‧Rdx

7502‧‧‧through through hole

7504‧‧‧Rectangular Landing Area

7602‧‧‧Wv

7604‧‧‧Wn

7606‧‧‧Wp

7610‧‧‧Transistor isolation

7612,7614‧‧‧effective area

7616‧‧‧Shared quarantine

7618‧‧‧layer to layer perforated channel

7622,7622B‧‧‧Gate

77A02‧‧‧through through hole

77A04, 77A06‧‧‧ Landing belt

7802‧‧‧Wv

7804‧‧‧Wy

7806‧‧‧Wx

7810‧‧‧Transistor isolation

7900‧‧‧ Landing strip width increase

8000‧‧‧Indoor wafer wafer

8002‧‧‧General connectivity structure

8004‧‧‧Non-repeating structure

8006‧‧‧Maximum donor wafer to acceptor wafer misalignment in the east-west direction (Mx)

8008‧‧‧Maximum donor wafer to acceptor wafer misalignment (Mx) in the north-south direction

8010‧‧‧Acceptor Wafer North-South Landing Strip

8011‧‧‧ donor wafer east-west landing strip

8012‧‧‧through layer piercing

8100‧‧‧ donor wafer

8102‧‧‧ donor wafer surface

8104‧‧‧Oxide

8106‧‧‧Oxide surface

8124‧‧‧Metal strip

8128‧‧‧through through hole

8130‧‧‧STI (shallow trench isolation) isolation

8136‧‧‧Oxide

8140‧‧‧Contacts

8150‧‧‧metal wire

8160‧‧‧ Gate oxide

8162‧‧‧Gate material

8170‧‧‧ completely depleted SOI transistor junction

8171‧‧‧ completely depleted SOI transistor junction

8202‧‧‧Virtual Gate Crystal

8206‧‧‧The first donor wafer

8208‧‧‧Cleavage line

8216‧‧‧ implant

8218‧‧‧Second cleavage line

8226‧‧‧Second donor wafer

8232‧‧‧ surface

8246‧‧‧ implant

8300‧‧‧ donor wafer

8301‧‧‧Embedded oxide (BOX)

8302‧‧‧thin layer

8303‧‧‧Inter-anode isolation

8304‧‧‧Polysilicon

8305‧‧‧ Gate oxide

8306‧‧‧NMOS source and drain

8307‧‧‧NMOS channel

8308‧‧‧NMOS Interlayer Dielectric (ILD)

8310‧‧‧Atomic implants

8312‧‧‧Cleavage

8314‧‧‧ donor wafer surface

8316‧‧‧Oxide layer

8320‧‧‧ Carrier Wafer

8321‧‧‧Cleavage

8322‧‧‧ surface

8333‧‧‧Inter-anode isolation

8334‧‧‧Polysilicon

8335‧‧‧ Gate oxide

8336‧‧‧PMOS source and drain

8337‧‧‧PMOS transistor channel

8338‧‧‧ PMOS interlayer dielectric (ILD)

8339‧‧‧Dielectric layer

8340‧‧‧Atomic implants

8341‧‧‧ PMOS specific working function metal gate

8342‧‧‧Aluminum filling

8343‧‧‧Gate contacts and metallization

8344‧‧‧Source and drain contacts and metallization

8347‧‧‧ PMOS layer to NMOS layer perforation

8348‧‧‧Oxide layer

8350‧‧‧Metal landing strip

8360‧‧‧NMOS high-k gate dielectric

8361‧‧‧ NMOS specific work engineering metal gate

8362‧‧‧Aluminum filling

8363‧‧‧Gate contacts and metallization

8364‧‧‧Source and drain contacts and metallization

8367‧‧‧ NMOS layer to PMOS layer perforation

8369‧‧‧ dielectric layer

8370‧‧‧ dielectric layer

8372‧‧ ‧ layer to layer through through hole

83L00‧‧‧Repeating universal unit

83L04‧‧‧ NMOS transistor

83L05‧‧‧Shared diffusion

83L02‧‧‧ PMOS transistor

83L10‧‧‧Optoelectric grid

83L12, 83L20‧‧‧ perforation

83L06‧‧‧Vdd power cord

83L08‧‧‧Diffuse connection

83L17‧‧‧down general metal structure

83L14, 83L16, 83L18‧‧‧ through hole

83L22, 83L24‧‧‧ NMOS transistor contacts

83L26‧‧‧Customer Metal

83L25‧‧‧Vss power cord

8402‧‧‧Repeating logic patterns

8404‧‧‧ blocks

8420‧‧‧SRAM unit

8422,8438,8452‧‧‧Word line

8424, 8426, 8436, 8462‧‧‧ bit line

8430‧‧‧Continuous array

8432‧‧‧Memory Module

8434‧‧‧etching unit

8450, 8460‧‧‧ logical structure

8468‧‧‧Read sensing circuit

8502‧‧‧ Gate oxide

8504‧‧‧Gate material

8506‧‧‧Gate stacking

8508‧‧‧ dielectric

8510‧‧‧Local contacts

8512‧‧‧layer-to-layer contacts

8516‧‧‧metallization

8520‧‧‧Oxide layer

8522‧‧‧Contacts

8536‧‧‧Metal wire

8550‧‧‧Top transistor

8552‧‧‧Top transistor

8602‧‧‧Logical layer

8612‧‧‧Logical layer

8622‧‧‧Logical layer

8632‧‧‧Repairing the logical layer

86C02‧‧‧Base antenna

86C04‧‧‧RF to DC conversion circuit

86C06‧‧‧Power supply unit

86C08‧‧‧Three-dimensional integrated circuit

86C10‧‧‧Solar battery

86C12‧‧‧Micro Control Unit

86C14‧‧‧ Radio Module

8702‧‧‧ Trigger

8704‧‧‧Normal output

Branch of 8706‧‧‧

8708‧‧‧Repair input

8710‧‧‧Control

8712‧‧‧Normal input

8714‧‧‧Multiplexer

8801‧‧‧P-type wafer

8802‧‧‧N+ layer

8803‧‧‧ Hydrogen surface

8804‧‧‧ temporary carrier

8805‧‧‧Oxide

8806‧‧‧ peripheral circuits

8807‧‧‧ surface

8808‧‧‧ gate electrode

8809‧‧‧Gate dielectric

8810‧‧‧Oxide layer

8811‧‧‧First RCAT layer

8812‧‧‧Second RCAT layer

8813‧‧‧Highly doped polysilicon

8814‧‧‧Source line

8815‧‧‧ bit line

8816‧‧‧Gate

8817‧‧‧P-layer

8818‧‧‧P-layer

8902‧‧‧ bit line (BL)

8903‧‧‧Source Line (SL)

8904‧‧‧Word line (WL)

8905‧‧‧Oxide isolation zone

8906‧‧‧p-layer

8907‧‧‧WL

8908‧‧‧WL wiring

8909‧‧‧SL wiring 8909

8910‧‧‧BL wiring

9001‧‧‧P-type wafer

9002‧‧n+ epitaxial layer

9003‧‧‧p-epitaxial layer

9004‧‧‧Oxide layer

9005‧‧‧ Hydrogen surface

9006‧‧‧ peripheral circuits

9007‧‧‧Oxide

9008‧‧‧ gate electrode

9009‧‧‧Gate dielectric

9010‧‧‧Oxide layer

9011‧‧‧First RCAT layer

9012‧‧‧Second RCAT layer

9013‧‧‧Highly doped polysilicon

9014‧‧‧ source line

9015‧‧‧ bit line

9016‧‧‧ gate electrode

9101‧‧‧SOI p-wafer

9102‧‧‧Shallow trench isolation zone

9103‧‧‧Gate trench

9104‧‧‧ gate electrode

9105‧‧‧Gate dielectric layer

9106‧‧‧Source and drain n+ regions

9107‧‧‧Interlayer dielectric

9108‧‧‧P-type wafer

9109‧‧‧Oxide

9110‧‧‧ Hydrogen surface

9113‧‧‧RCAT layer

9114‧‧‧RCAT layer

9115‧‧‧through hole

9116‧‧‧ bit line BLs

9117‧‧‧Source line SLs

9118‧‧‧ peripheral circuits

9119‧‧‧ buried oxide layer

9201‧‧‧P-type wafer

9202‧‧‧Oxide layer

9203‧‧‧ Hydrogen surface

9204‧‧‧ peripheral circuits

9205‧‧‧ gate electrode

9206‧‧‧Oxide layer

9207‧‧‧Gate dielectric

9208‧‧‧Source/Drain Region

9209‧‧‧Second PD-SOI transistor layer

9210‧‧‧Perforation

9211‧‧‧ bit line

9212‧‧‧ source line

9213‧‧‧Optoelectric grid

9302‧‧‧First wafer

9303‧‧‧ Circuitry

9304‧‧‧Second wafer

9305‧‧‧ Circuitry

9306‧‧‧thin wafer

9310‧‧‧Cleavage

9312‧‧‧thin layer

9322‧‧‧bonding structure

9402‧‧‧Metal landing strip

9403‧‧‧Unusable room with additional metal strips

9406‧‧‧ Length

9412‧‧‧ Landing belt

9413‧‧‧ Landing belt

9432‧‧‧A row of perforations

9433‧‧‧B row perforation

9436‧‧‧through hole

9438‧‧‧Metal strip

9500‧‧‧P-substrate

9501‧‧‧Oxide

9502‧‧‧Oxide

9503‧‧‧N+ doped wafer size layer

9503'‧‧‧N+ layer

9504‧‧‧P-doped wafer size layer

9506‧‧‧P+ doped wafer size layer

9507‧‧‧ Hydrogen implantation

9508‧‧‧N-doped wafer size layer

9510‧‧‧Acceptor Wafer

9511‧‧‧ Gate oxide

9512‧‧‧ Gate oxide

9513‧‧‧N+ doped area

9514‧‧‧P-doped zone

9516‧‧‧P+ doped area

9518‧‧‧N-doped area

9520‧‧‧Cell isolation area

9526‧‧‧P+ source and drain regions

9528‧‧‧N-transistor channel region

9533‧‧‧N+ source and drain regions

9534‧‧‧P-Crystal Channel Region

9542‧‧‧p-RCAT recessed channel

9544‧‧‧n-RCAT recessed channel

9550‧‧‧Oxide

9552‧‧‧Oxide

9554'‧‧‧p-RCAT gate electrode

9556'‧‧‧n-RCAT gate electrode

9562‧‧‧n-RCAT source contact

9564‧‧‧n-RCAT gate contacts

9566‧‧‧n-RCAT drain contact

9572‧‧‧p-RCAT source contact

9574‧‧‧p-RCAT gate contacts

9576‧‧‧p-RCAT drain contact

9599‧‧‧ layer transfer division

9600‧‧‧ donor wafer

9602‧‧‧N+ doped layer

9604‧‧‧n+SiGe layer

9606‧‧‧N+ doped layer

9608‧‧‧n+SiGe layer

9610‧‧‧Acceptor Wafer

9611‧‧‧Gate dielectric

9612‧‧‧Gate material

9613‧‧‧Oxide

9614‧‧‧Oxide

9616‧‧‧n+SiGe area

9618‧‧‧N+

9620‧‧‧Oxide

9622‧‧‧Oxide

9630‧‧‧Common gate region

9636‧‧‧Optical gate trench

9699‧‧‧ layer transfer division

9702‧‧‧Excess hole

9704‧‧‧ source

9706‧‧‧Gate

9708‧‧‧Drain

9710‧‧‧ source

9712‧‧‧Gate

9714‧‧‧Drain

9716‧‧‧ buried oxide

9718‧‧‧ buried oxide

9720‧‧‧ floating body area

9730‧‧‧ Current differential

9734‧‧‧Drain current

9736‧‧‧ gate voltage

9800‧‧‧P-substrate

9801‧‧‧Oxide

9802‧‧‧Oxide

9804‧‧‧P-layer

9804'‧‧‧ Remaining P-doped layer

9807‧‧‧Hydrogen implantation

9810‧‧‧Acceptor Wafer

9820‧‧•Transistor source and drain

9824‧‧‧Gate stacking

9828‧‧‧NMOS channel

9830‧‧‧ second floor

9834‧‧‧Gate stacking

9840‧‧‧ bit line (BL) contacts

9842‧‧‧Source line (SL) contacts

9846‧‧‧Source line (SL) wiring

9848‧‧‧ bit line (BL) wiring

9850‧‧‧Oxide

9852‧‧‧N+ region on the source side of the transistor

9854‧‧‧N+ region on the drain side of the transistor

9864‧‧‧WL wiring

9865‧‧‧SL wiring

9866‧‧‧BL wiring

9899‧‧‧ layer transfer division

9902‧‧‧ peripheral circuit substrate

9904‧‧‧Oxide

9906‧‧‧P-substrate

9906'‧‧‧ Remaining P-layer

9908‧‧‧Oxide

9910‧‧‧ layer transfer division

9912‧‧‧ donor wafer

9914‧‧‧Acceptor Wafer

9916‧‧‧N+

9916'‧‧‧N+

9918‧‧‧p-矽

9918'‧‧‧p-矽

9920‧‧‧Oxide layer

9922‧‧‧First Si/SiO2 layer

9924‧‧‧Second/O2 layer

9926‧‧‧ Third Si/SiO2 layer

9928‧‧‧Gate dielectric area

9929‧‧‧Oxide layer

9930‧‧‧ gate electrode

9932‧‧‧Oxide

9934‧‧‧ bit line (BL) contacts

9936‧‧‧BL wire

9950‧‧‧Word Line Area (WL)

9952‧‧‧Source Line Area (SL)

10002‧‧‧ peripheral circuit substrate

10004‧‧‧Oxide

10006‧‧‧P-substrate

10006'‧‧‧ remaining P-layer

10008‧‧‧Oxide

10010‧‧‧ layer transfer plane

10012‧‧‧ donor wafer

10014‧‧‧Acceptor Wafer

10016‧‧‧p-矽

10017‧‧‧p-矽

10020‧‧‧Oxide layer

10022‧‧‧Oxide

10023‧‧‧First Si/SiO2 layer

10025‧‧‧Second/niobium oxide layer

10026‧‧‧N+矽

10027‧‧‧ Third Si/SiO2 layer

10028‧‧‧Gate dielectric area

10029‧‧‧Oxide layer

10030‧‧‧ gate electrode

10032‧‧‧Oxide

10034‧‧‧ bit line (BL) contacts

10036‧‧‧BL wire

10050‧‧‧Word Line Area (WL)

10052‧‧‧Source Line Area (SL)

10102‧‧‧ peripheral circuit substrate

10104, 10122, 10132‧‧‧ oxide

10114‧‧‧Acceptor Wafer

10112‧‧‧ donor wafer

10106‧‧‧N+ substrate

10110‧‧‧ layer transfer division

10106'‧‧‧Remaining N+ layer

10108, 10120, 10129‧‧‧ oxide layer

10123‧‧‧First Si/SiO2 layer

10125‧‧‧Second/O2 layer

10127‧‧‧ Third Si/SiO2 layer

10126‧‧‧N+

10128‧‧‧Gate dielectric area

10130‧‧‧ gate electrode

10150‧‧‧Word Line Area (WL)

10152‧‧‧Source Line Area (SL)

10134‧‧‧ bit line (BL) contacts

10138‧‧‧Resistance-changing memory materials

10136‧‧‧BL wire

10202‧‧‧ peripheral circuit substrate

10204‧‧‧Oxide

10206‧‧‧P-substrate

10206'‧‧‧P-layer

10208‧‧‧Oxide

10210‧‧‧ layer transfer division

10212‧‧‧ donor wafer

10214‧‧‧Acceptor Wafer

10216‧‧‧p-矽

10217‧‧‧p-矽

10220‧‧‧Oxide layer

10222‧‧‧Oxidation zone

10223‧‧‧First Si/SiO2 layer

10225‧‧‧Second/niobium oxide layer

10226‧‧‧N+

10227‧‧‧ Third Si/SiO2 layer

10228‧‧‧Gate dielectric area

10229‧‧‧Oxide layer

10230‧‧‧ gate electrode

10232‧‧‧Oxide

10234‧‧‧ bit line (BL) contacts

10236‧‧‧BL wire

10238‧‧‧Resistance change material

10250‧‧‧Word Line Area (WL)

10252‧‧‧Source Line Area (SL)

10302‧‧‧ peripheral circuit substrate

10304‧‧‧Oxide

10306‧‧‧P-substrate

10306'‧‧‧P-layer

10308‧‧‧Oxide

10310‧‧‧ layer transfer plane

10312‧‧‧ donor wafer

10314‧‧‧Acceptor Wafer

10316‧‧‧N+

10316'‧‧‧N+

10318‧‧‧p-矽

10318'‧‧‧p-矽

10320‧‧‧Oxide layer

10322‧‧‧Oxidation zone

10323‧‧‧First Si/SiO2 layer

10325‧‧‧Second/O2 layer

10326‧‧‧N+矽

10327‧‧‧ Third Si/SiO2 layer

10328‧‧‧Gate dielectric area

10329‧‧‧Oxide layer

10330‧‧‧ gate electrode

10332‧‧‧Oxide

10334‧‧‧ bit line (BL) contacts

10336‧‧‧BL wire

10338‧‧‧Resistance change material

10350‧‧‧Word Line Area (WL)

10352‧‧‧Source Line Area (SL)

10400‧‧‧ donor wafer

10401‧‧‧Oxide

10402‧‧‧Oxide

10404‧‧‧P-layer

10404'‧‧‧P-doped layer

10407‧‧‧Hydrogen implantation

10410‧‧‧Acceptor Wafer

10420‧‧‧Optical source and drain

10424‧‧‧Gate stacking

10428‧‧‧P-矽NMOS transistor channel

10430‧‧‧ Storage transistor second layer

10434‧‧‧Source line (SL) contacts

10440‧‧‧ bit line (BL) contacts

10442‧‧‧Resistance-changing memory material

10446‧‧‧Source line (SL) wiring

10448‧‧‧ bit line (BL) wiring

10450‧‧‧Oxide

10452‧‧‧N+ region on the source side of the transistor

10454‧‧‧N+ region on the drain side of the transistor

10499‧‧‧ layer transfer partition

10500‧‧‧ donor wafer

10501‧‧‧Oxide

10502‧‧‧Oxide

10504‧‧‧P-doped layer

10504'‧‧‧P-doped layer

10507‧‧‧ Hydrogen implantation

10510‧‧‧Acceptor Wafer

10520‧‧‧P-doped area

10522‧‧‧Charge trap gate dielectric

10524‧‧‧Gate metal material

10528‧‧‧Gate stacking

10530‧‧‧NAND string source and drain terminals

10534‧‧‧Source and drain between transistors

10542‧‧‧ Storage transistor first layer

10544‧‧‧Second layer of storage transistor

10548‧‧‧Source line (SL) ground contact

10549‧‧‧ bit line contacts

10550‧‧‧Oxide

10599‧‧‧ layer transfer division

10602‧‧‧ peripheral circuit substrate

10604‧‧‧Oxide

10606‧‧‧N+ substrate

10606'‧‧‧N+ layer

10608‧‧‧Oxide

10610‧‧‧ layer transfer division

10612‧‧‧ donor wafer

10614‧‧‧Acceptor Wafer

10620‧‧‧Oxide layer

10622‧‧‧Oxidation zone

10623‧‧‧First Si/SiO2 layer

10625‧‧‧Second/O2 layer

10626‧‧‧N+

10627‧‧‧ Third Si/SiO2 layer

10628‧‧‧Gate dielectric area

10629‧‧‧Oxide

10630‧‧‧Gate metal electrode area

10632‧‧‧Oxide

10634‧‧‧Selecting the gate contact

10636‧‧‧NAND area

10638‧‧‧Selecting the gate region

10644‧‧‧Source area

10646‧‧‧Select metal wire

10652‧‧‧ bit line area (BL)

10700‧‧‧ donor wafer

10701‧‧‧Oxide

10702‧‧‧Oxide

10704‧‧‧P-doped layer

10704'‧‧‧P-doped layer

10707‧‧‧Hydrogen implantation

10710‧‧‧Acceptor Wafer

10720‧‧‧P-doped area

10722‧‧‧ Tunnel Oxide

10722'‧‧‧ Tunnel Oxidation Zone

10724‧‧‧FG gate metal material

10724'‧‧‧FG gate metal area

10725‧‧‧Polycrystalline inter-turn oxide layer

10725'‧‧‧Polysilicon inter-turn oxide zone

10726‧‧‧Control grid (CG) gate metal material

10726'‧‧‧CG gate metal area

10728‧‧‧Gate stacking

10730‧‧‧NAND string source and drain terminals

10734‧‧•Source and drain between transistors

10742‧‧‧ Storage transistor first layer

10744‧‧‧Second layer of storage transistor

10748‧‧‧Source Line (SL) Ground Contact

10749‧‧‧ bit line contacts

10750‧‧‧Oxide

10799‧‧‧ layer transfer plane

10802‧‧‧ peripheral circuit substrate

10804‧‧‧Oxide

10806‧‧‧N+ substrate

10806'‧‧‧N+ layer

10808‧‧‧Oxide

10810‧‧‧ layer transfer division

10812‧‧‧ donor wafer

10814‧‧‧Acceptor Wafer

10816‧‧‧N+ District

10818‧‧‧Tunnel dielectric

10823‧‧‧First storage layer

10825‧‧‧Second storage layer

10828‧‧‧FG District

10829‧‧‧Oxide layer

10829'‧‧‧Thin oxide layer

10838‧‧‧FG District

10850‧‧‧Polycrystalline inter-turn oxide layer

10852‧‧‧Control grid (CG) gate material

10902‧‧‧ peripheral circuit substrate

10904‧‧‧Oxide

10906‧‧‧N+ doped polysilicon or amorphous layer

10908‧‧‧Oxide layer

10916‧‧‧ Crystalline N+ layer

10920‧‧‧Oxide layer

10922‧‧‧Oxidation zone

10923‧‧‧First Si/SiO2 layer

10925‧‧‧Second/O2 layer

10926‧‧‧ Crystalline N+

10927‧‧‧ Third Si/SiO2 layer

10928‧‧‧Gate dielectric area

10929‧‧‧Oxide

10930‧‧‧ gate electrode

10932‧‧‧Oxide

10934‧‧‧ bit line (BL) contacts

10936‧‧‧BL wire

10938‧‧‧Resistance-varying memory materials

10950‧‧‧Word Line Area (WL)

10952‧‧‧Source Line Area (SL)

11002‧‧‧矽 substrate

11004‧‧‧Oxide layer

11006‧‧‧N+ doped amorphous germanium or polycrystalline germanium

11016‧‧‧ Crystalline N+ layer

11020‧‧‧Oxide layer

11022‧‧‧Oxidation zone

11023‧‧‧First Si/SiO2 layer

11025‧‧‧Second/niobium oxide layer

11026‧‧‧Crystal N+矽

11027‧‧‧ Third Si/SiO2 layer

11028‧‧‧Gate dielectric area

11029‧‧‧Oxide layer

11030‧‧‧ gate electrode

11032‧‧‧Oxide

11034‧‧‧ bit line (BL) contacts

11036‧‧‧BL wire

11038‧‧‧Resistance-varying memory materials

11050‧‧‧Word Line Area (WL)

11052‧‧‧Source Line Area (SL)

11078‧‧‧ peripheral circuits

11100‧‧‧ donor wafer

11100'‧‧‧ donor wafer section

11101‧‧‧ Bonding surface

11102‧‧ layer

11110‧‧‧Acceptor Wafer

11111‧‧‧ Bonding surface

11130‧‧‧Alignment window

11130'‧‧‧ alignment window

11131‧‧‧Aligned window area

11150‧‧‧ donor wafer device structure

11160‧‧‧through layer perforation (TLVS)

11180‧‧‧Metal connection wafer or strip

11190‧‧‧Acceptor wafer alignment mark

11199‧‧‧ layer transfer division

11201‧‧‧Interconnect metallization

11202‧‧‧Base

11203‧‧‧Thin bismuth oxide layer

11204‧‧‧Oxide layer

11205‧‧‧Homothermal sheet

11206‧‧‧ donor wafer substrate

11206'‧‧‧Remaining transfer layer

11207‧‧‧mask oxide

11212‧‧‧ donor wafer

11214‧‧‧Acceptor Wafer

11299‧‧‧ layer transfer partition

11300‧‧‧Printed wiring board

11302‧‧‧Transistor bottom layer

11304‧‧‧through-layer power supply and grounding perforation

11305‧‧‧ Non-conducting heat spreader layer

11306‧‧‧Transistor top power supply and grounding grid

11307‧‧‧Transistor bottom layer power supply and grounding grid

11310‧‧‧ Bonded oxide

11312‧‧‧The top layer of the transistor

11325‧‧‧Package heat spreader

11330‧‧‧heatsink

11360‧‧‧ sidewall heat conductor

11401‧‧‧Logical layer

11402‧‧‧Logical layer

11405‧‧‧Vertical connection

11406‧‧‧Vertical connection

11411‧‧‧Logical cone

11412‧‧‧Logical cone

11421‧‧‧ Trigger

11422‧‧‧ Trigger

11431‧‧‧Multiplexer

11432‧‧‧Multiplexer

11441‧‧‧ control points

11442‧‧‧Control points

11451‧‧‧BIST controller/detector

11452‧‧‧BIST controller/detector

11501‧‧ layer

11502‧‧ layer

11503‧‧ layer

11511-1‧‧‧Logical cone

11511-2‧‧‧Logical cone

11511-3‧‧‧Logical cone

11521-1‧‧ Trigger

11521-2‧‧ Trigger

11521-3‧‧‧ Trigger

11531‧‧‧ majority voting circuit

11541-1‧‧‧Final Fault Tolerant FF Output

11541-2‧‧‧Final Fault Tolerant FF Output

11541-3‧‧‧Final Fault Tolerant FF Output

11551‧‧‧Local FF output

11552‧‧‧FF output value

11553‧‧‧FF output value

11600‧‧‧Two-dimensional integrated circuit ASIC

11610‧‧‧Scan test controller

11612‧‧‧Multiple triggers

11614‧‧‧Multiple triggers

11616‧‧‧Multiple triggers

11620‧‧‧Logic Cloud

11622‧‧‧Logic Cloud

11624‧‧‧Logic Cloud

11626‧‧‧Logic Cloud

11630‧‧‧Input chip

11640‧‧‧ Output chip

11700‧‧‧ASIC

11710‧‧‧In the logic function module

11720‧‧‧Input/output unit

11722‧‧‧bonded wafer

11724‧‧‧Input buffer

11726‧‧‧Three status output buffers

11730‧‧‧Scan test control module

11732‧‧‧Boundary Scan Register Chain

11734‧‧‧Boundary Scan Register Chain

11800‧‧‧Logic Module

11810‧‧‧Block function

11812‧‧‧ input value

11814‧‧‧ Output value

11820‧‧‧BIST controller

11822‧‧‧Linear Feedback Shift Register (LFSR)

11824‧‧‧Cyclic redundancy check circuit

11900‧‧‧Three-dimensional integrated circuit

11910‧‧‧Control logic

11911‧‧‧ scan trigger

11912‧‧‧ scan trigger

11913‧‧‧ scan trigger

11914‧‧‧Combined logical cloud

11915‧‧‧Combined logical cloud

11920‧‧‧Control logic

11921‧‧‧ scan trigger

11922‧‧‧ scan trigger

11923‧‧‧ scan trigger

11924‧‧‧Logic Cloud

11925‧‧‧Logic Cloud

12000‧‧‧ scan trigger

12002‧‧‧D type trigger

12004‧‧‧ Multiplexer

12006‧‧‧Multiplexer

12100‧‧‧Three-dimensional integrated circuit

12110‧‧‧1st layer of logic cone

12112‧‧‧ scan trigger

12114‧‧‧XOR gate

12120‧‧‧2nd layer of logic cone

12122‧‧‧ scan trigger

12124‧‧‧XOR gate

12170‧‧‧LAYER_SEL Latch

12172‧‧‧ERROR2 line

12174‧‧‧COL_ADDR line

12176‧‧‧ROW_ADDR line

12178‧‧‧COL_BIT line

12182‧‧‧N-channel transistor

12184‧‧‧N-channel transistor

12186‧‧‧N-channel transistor

Line 12188‧‧

12190‧‧‧P-type channel transistor

12192‧‧‧P-type channel transistor

12200‧‧‧Logical Function Module (LFB)

12202‧‧‧ Input

12204‧‧‧ Output

12210‧‧‧Small logic function module

12212‧‧‧Linear feedback shift register circuit

12214‧‧‧Cyclic redundancy check circuit

12216‧‧‧Logical function

12220‧‧‧Small logic function module

12230‧‧‧Linear Feedback Shift Register (LFSR) Circuit

12232‧‧‧Cyclic redundancy check circuit

12300‧‧‧Three-dimensional integrated circuit

12310‧‧‧Control logic module

12311‧‧‧ scan trigger

12312‧‧‧ scan trigger

12313‧‧‧Multiplexer

12314‧‧‧Multiplexer

12315‧‧‧Logical cone

12320‧‧‧Control logic module

12321‧‧‧ scan trigger

12322‧‧‧ scan trigger

12323‧‧‧ Multiplexer

12324‧‧‧ Multiplexer

12325‧‧‧Logical cone

12400‧‧‧Three-dimensional integrated circuit

12410‧‧‧1st layer of logic cone

12412‧‧‧ scan trigger

12414‧‧‧Multiplexer

12416‧‧‧XOR gate

12420‧‧‧2nd layer of logic cone

12422‧‧‧ scan trigger

12424‧‧‧Multiplexer

12426‧‧‧XOR gate

12500‧‧‧Three-dimensional integrated circuit

12510,12520‧‧‧Logic Function Module (LFB)

12522, 12524‧‧ ‧ Multiplexer

12530‧‧‧Power Select Multiplexer

12600‧‧‧Three-dimensional integrated circuit

12610‧‧‧Interconnection line

12612‧‧‧Interconnection line

12620‧‧‧2nd layer of logic cone

12622‧‧‧ scan trigger

12624‧‧‧Multiplexer

12626‧‧‧XOR gate

12628‧‧‧RS trigger

12630‧‧‧2nd layer reset line

12632‧‧‧ or grid

12634‧‧‧2nd layer OR-chain input line

12636‧‧‧2nd layer OR-chain output line

12638‧‧‧N-channel transistor

12640‧‧‧N-channel transistor

12642‧‧‧N-channel transistor

12644‧‧‧Induction

12646‧‧‧ and gate

12648‧‧‧TEST_EN line

12700‧‧‧Three-dimensional integrated circuit

12710‧‧‧1st layer of logic cone

12714‧‧‧ Trigger

12716‧‧‧Three majority (MAJ3) gates

12720‧‧‧2nd layer of logic cone

12724‧‧‧ Trigger

12726‧‧‧Three majority (MAJ3) gates

12730‧‧‧3rd layer of logic cone

12734‧‧‧ Trigger

12736‧‧‧Three majority (MAJ3) gates

12800‧‧‧Three-dimensional integrated circuit

12810‧‧‧1st layer of logic cone

12812‧‧‧Three majority (MAJ3) gates

12814‧‧‧ Trigger

12820‧‧‧2nd layer of logic cone

12822‧‧‧Three majority (MAJ3) gates

12824‧‧‧ Trigger

12830‧‧‧3rd layer of logic cone

12832‧‧‧Three majority (MAJ3) gates

12834‧‧‧ Trigger

12900‧‧‧Three-dimensional integrated circuit

12910‧‧‧1st layer of logic cone

12912‧‧‧Three majority (MAJ3) gates

12914‧‧‧ Trigger

12916‧‧‧Three majority (MAJ3) gates

12920‧‧‧2nd layer of logic cone

12922‧‧‧Three majority (MAJ3) gates

12924‧‧‧ Trigger

12926‧‧‧Three majority (MAJ3) gates

12930‧‧‧3rd layer of logic cone

12932‧‧‧Three majority (MAJ3) gates

12934‧‧‧ Trigger

12936‧‧‧Three majority (MAJ3) gates

13000‧‧‧Perforated pattern

13002‧‧‧Perforated metal overlapping wafer

13004‧‧‧Perforated metal overlapping wafer

13006‧‧‧Perforated metal overlapping wafer

13008‧‧‧Perforated metal overlapping wafer

13010‧‧‧Perforated pattern

13012‧‧‧Perforated metal overlapping wafer

13014‧‧‧Perforated metal overlapping wafer

13016‧‧‧Perforated metal overlapping wafer

13018‧‧‧Perforated metal overlapping wafer

13020‧‧‧Three-dimensional integrated circuit

13030‧‧ layer

13031‧‧‧Optoelectronics

13032‧‧‧Contacts

13033‧‧‧Metal 1

13034‧‧‧Perforation 1

13035‧‧‧Metal 2

13036‧‧‧Perforation 2

13037‧‧‧Metal 3

13040‧‧‧through through crystal perforation

13100‧‧‧Perforated pattern

13102‧‧‧Perforated metal overlapping wafer

13104‧‧‧Perforated metal overlapping wafer

13106‧‧‧Perforated metal overlapping wafer

13110‧‧‧Perforation pattern

13112‧‧‧Perforated metal overlapping wafer

13114‧‧‧Perforated metal overlapping wafer

13116‧‧‧Perforated metal overlapping wafer

13200‧‧‧Perforated pattern

13202‧‧‧Perforated metal overlapping wafer

13204‧‧‧Perforated metal overlapping wafer

13206‧‧‧Perforated metal overlapping wafer

13208‧‧‧Perforated metal overlapping wafer

13210‧‧‧Perforated metal overlapping wafer

13212‧‧‧Perforated metal overlapping wafer

13214‧‧‧Perforated metal overlapping wafer

13216‧‧‧Perforated metal overlapping wafer

13218‧‧‧Perforated metal overlapping wafer

13220‧‧‧Three-dimensional integrated circuit

13230‧‧‧Interconnect layer

13232‧‧‧Interconnect layer

13240‧‧‧Interconnect layer

13242‧‧‧Interconnection layer

13250‧‧‧Interconnect layer

13252‧‧‧Interconnect layer

13301‧‧‧P-doped layer

13302‧‧‧P-substrate donor wafer

13304‧‧‧N+ doped layer

13306‧‧‧Metal telluride layer

13308‧‧‧Oxide layer

13310‧‧‧Acceptor substrate or wafer

13312‧‧‧ Carrier or carrier substrate

13314‧‧‧ bonding layer

13316‧‧‧P-layer

13318‧‧‧Oxide layer

13322‧‧‧Cell isolation area

13323‧‧‧ recessed channel

13324‧‧‧Oxidation zone

13326‧‧‧Metal Telluride Source and Drain Regions

13328‧‧‧N+ source and drain regions

13330‧‧‧P-type channel region

13332‧‧‧Gate dielectric

13334‧‧‧ gate electrode

13336‧‧‧Source and drain contacts

13338‧‧‧ Thick oxide

13342‧‧‧Gate contacts

13399‧‧‧ layer transfer division

13400‧‧‧Acceptor Wafer

13400A‧‧‧Acceptor substrate with channel transistor

13400B‧‧‧Acceptor substrate with channel transistor and memory element

13402‧‧‧ donor wafer

13402'‧‧‧Channel transistor layer

13404‧‧‧Memory component donor wafer

13404'‧‧‧ memory element layer

13410‧‧‧through layer perforation (TLVS)

13410A‧‧‧through layer piercing

13410B‧‧‧through layer piercing

13420‧‧‧Storage to switch through layer perforation

13430‧‧‧Storage to the acceptor through layer perforation

13440‧‧‧Memory components

13442‧‧‧Channel transistor gate

13444‧‧‧Channel transistor source

13445‧‧‧Channel transistor drain

13446‧‧‧FPGA configuration network wire

13447‧‧‧FPGA configuration network wire

13500‧‧‧Acceptor Wafer

13500A‧‧‧Acceptor substrate with channel transistor and memory element

13502‧‧‧ donor wafer

13502'‧‧‧Channel transistor and storage layer

13510‧‧‧through-layer perforations (TLVs)

13510A‧‧‧through layer piercing

13510B‧‧‧through layer piercing

13525‧‧‧Channel transistor and memory layer interconnection metallization

13540‧‧‧Memory components

13542‧‧‧Channel transistor gate

13544‧‧‧Channel transistor source

13545‧‧‧Channel transistor drain

13546‧‧‧FPGA configuration network wire

13547‧‧‧FPGA configuration network wire

13602‧‧‧Control grid

13604‧‧‧Floating grid

13610‧‧‧Switching transistor channel

13612‧‧‧Switching transistor source

13614‧‧‧Switching transistor drain

13620‧‧‧Inductive transistor channel

13622‧‧‧Induction transistor source

13624‧‧‧Induction transistor drain

13700‧‧‧ donor wafer

13701‧‧‧mask oxide

13702‧‧‧Oxide

13704‧‧‧N+ doped layer

13704'‧‧‧Remaining highly doped layer

13706‧‧‧P-doped layer

13707‧‧‧Hydrogen implantation

13710‧‧‧Acceptor Wafer

13711‧‧‧Tunnel dielectric

13714‧‧‧Tunnel dielectric

13715‧‧‧High N+ doping in the southeast electro-crystal region

13716‧‧‧Southwestern crystal channel region

13717‧‧‧Southeast crystal channel region

13720‧‧‧Cell isolation area

13721‧‧‧Southwest to Southeastern Quarantine

13724‧‧‧Southwest source and drain regions

13725‧‧‧Southeast source and drain regions

13741‧‧‧Polysilicon interlayer dielectric

13742‧‧‧Southwest Sag Channel

13743‧‧‧Southeast depression channel

13752‧‧‧Floating grid

13754‧‧‧Control grid

13799‧‧‧ layer transfer plane

In conjunction with the pictures and the detailed description below, the reader can have a deeper understanding of the different cases in this invention.

1 is a schematic circuit diagram of a prior art.

Figure 2 is a partial cross-sectional view of the prior art circuit diagram of Figure 1.

3A is a schematic diagram of a programmable interconnect circuit structure.

3B is a schematic diagram of a programmable interconnect circuit structure; FIG. 4A is a schematic diagram of a programmable interconnect circuit board; FIG. 4B is a schematic diagram of a 2x2 programmable interconnect circuit board; FIG. 5A is a schematic diagram of an inverter logic chip; FIG. 5C is a schematic diagram of a buffer logic chip capable of setting intensity; FIG. 5D is a schematic diagram of a D-flip logic chip; FIG. 6 is a schematic diagram of a LUT4 logic chip; FIG. 6A is a schematic diagram of a PLA logic chip; FIG. 8 is a schematic diagram of a programmable component layer structure; FIG. 8A is a schematic diagram of a programmable component multilayer structure; FIG. 8B-8I is a pre-processed wafer and layers and a common layer is removed; FIGS. 9A-9C are An IC system that uses existing slab straight through hole (TSV) technology.

FIG. 10A is a schematic diagram of a continuous array wafer fabricated in the prior art.

Figure 10B is a partial schematic view of a prior art array of continuous array wafers.

Figure 10C is a partial schematic view of a prior art array of continuous array wafers.

11A-11F are schematic illustrations of actual masks on a wafer.

12A-12E are schematic diagrams of a configurable system; FIG. 13 is a schematic diagram of a 3D logical partitioning process; FIG. 14 is a schematic diagram of a layer cutting process; FIG. 15 is a schematic diagram of an underlying programming circuit; 17A is a schematic diagram of the topology of the bottom reverse bias circuit; FIG. 17B is a schematic diagram of the bottom reverse bias circuit; FIG. 17C is a schematic diagram of the power supply control circuit; FIG. 17D is a schematic diagram of the probe circuit; Figure 19A is a schematic diagram of the underlying I/O; Figure 19B is a schematic view of the side "cut"; Figure 19C is a schematic diagram of a 3D IC system; Figure 19D is a schematic diagram of a 3D IC processor and DRAM system; Figure 19E is a 3D IC processor Schematic of a DRAM system; Figure 19F is a schematic diagram of a straight-through connection of a cymbal using a custom SOI wafer.

Figure 19G is a schematic illustration of the fabrication of a slab straight through hole (TSV) using prior art techniques.

19H is a schematic diagram of a process for manufacturing a custom SOI wafer; FIG. 19I is a schematic diagram of a processor-DRAM stack; FIG. 19J is a schematic diagram of a process for manufacturing a custom SOI wafer; FIG. 20 is a schematic diagram of a layer removal process; FIG. 21B is a schematic view of a pre-processed wafer which can be subjected to layer resection; FIGS. 22A to 22H are schematic diagrams of surface planar transistor formation; and FIGS. 23A and 23B are schematic diagrams of layer resection using a preprocessed wafer. 24A-24F are schematic diagrams of surface plane transistor formation; FIGS. 25A and 25B are schematic diagrams of layer resection using a preprocessed wafer; FIGS. 26A-26E are schematic diagrams of surface plane transistor formation; FIGS. 27A and 27B are diagrams of using pretreatment crystal Figure 28A-28E is a schematic diagram of surface layer transistor formation; Figures 29A-29G are schematic diagrams of surface plane transistor formation; Figure 30 is a schematic diagram of electron supply wafer; Figure 31 is a resection layer on the main crystal garden FIG. 32 is a schematic diagram of measurement alignment deviation; FIGS. 33A and 33B are schematic diagrams of connection strips; FIGS. 34A-34E are schematic diagrams of layer resection of a plurality of preprocessed wafers; FIGS. 35A-35G FIG. 36 is a schematic diagram of a board array wafer; FIG. 37 is a schematic diagram of a programmable terminal assembly; FIG. 38 is a schematic diagram of an adjusted JTAG connection; and FIGS. 39A-39C are diagrams for manufacturing a vertical transistor. FIG. 40A-40I are schematic diagrams of a vertical n-MOSFET surface layer transistor; FIG. 41 is a schematic diagram of a 3D IC system with redundancy; FIG. 42 is a schematic diagram of an inverter chip; FIG. 43A-C is a 3D chip. Figure 4A-F is a schematic view of a 3D wafer forming step; Figures 45A-G are schematic views of a 3D wafer forming step; Figure 46A-C is a schematic cross-sectional view of a 3D inverter chip; Figure 47 is two Figure 7A-C is a schematic cross-sectional view of a 3D 2-input NOR wafer; Figures 49A-C are schematic diagrams of a 2-input NOR 3D wafer; Figures 50A-D are schematic views of a 3D CMOS transfer wafer; Figure 51A- D is a schematic diagram of a 3D CMOS SRAM wafer; FIGS. 52A and 52B are diagrams of a component of a connectorless transistor; FIGS. 53A-E are schematic diagrams of a 3D CAM wafer; and FIGS. 54A-C are schematic diagrams of a connectorless transistor; FIG. 55A-I It is a schematic diagram of the formation of a jointless transistor; Figure 5 6A-M is a schematic diagram of the formation of a jointless transistor; FIG. 57A-G is a schematic diagram of the formation of a jointless transistor; FIG. 58A-G is a schematic diagram of the formation of a jointless transistor; FIG. 59 is a schematic diagram of a metal interconnection stack of the prior art; 60 is a schematic diagram of a metal interconnect stack; FIG. 61A-I is a schematic diagram of a jointless transistor; FIGS. 62A-D are schematic views of a 3D NAND2 wafer; FIGS. 63A-G are schematic views of a 3D NAND8 wafer; and FIGS. 64A-G are 3D NOR8 wafers. Figure 65A-C is a schematic view of the formation of a jointless transistor; Figure 66 is a schematic view of a grooved channel array transistor; Figure 67A-F is a schematic view of the formation of a grooved channel array transistor; Figure 68A-F is a spherical concave Schematic diagram of the formation of the groove channel array transistor; Fig. 69 is a schematic diagram of the electron supply wafer; Figs. 70A, B, B-1 and CH are schematic diagrams of the surface planar transistor formation; Fig. 71 is a schematic diagram of the electron supply wafer; Fig. 72A- F is a schematic diagram of surface plane transistor formation; FIG. 73 is a schematic diagram of an electron supply wafer; FIG. 74 is a schematic diagram of measurement alignment deviation; FIG. 75 is a schematic diagram of a connection strip; FIG. 76 is a schematic diagram of an electron supply wafer; Schematic diagram 78A, 78B, and 78C are schematic views of a layer of electron supply wafer; Fig. 79 is a schematic view of a connection strip; Fig. 80 is a schematic diagram of a connection strip array structure; and Figs. 81A-81F-2 are schematic diagrams of surface plane transistor formation; Fig. 82A- G is a schematic diagram of surface plane transistor formation; FIG. 83A-L is a schematic diagram of surface plane transistor formation; FIG. 83L1-L4 is a schematic diagram of surface plane transistor formation; FIG. 84A-G is a schematic diagram of a continuous transistor array; FIG. 85A-E is FIG. 86A is a schematic diagram of a 3D logic IC for maintenance structure; FIG. 86B is a schematic diagram of a single layer scan chain 3D IC; FIG. 86C is a schematic diagram of a contactless test; and FIG. 87 is a trigger of a maintainable 3D IC logic Figure 88A-F is a schematic diagram of 3D DRAM formation; Figure 89A-D is a schematic diagram of 3D DRAM formation; Figure 90A-F is a schematic diagram of 3D DRAM formation; Figure 91A-L is a schematic diagram of 3D DRAM formation; Figure 92A- F is a schematic diagram of 3D DRAM formation; FIG. 93A-D is a schematic diagram of an advanced TSV process; FIG. 94A-C is a schematic diagram of an advanced multi-connection TSV process; FIG. 95A-J is a schematic diagram of a CMOS groove channel array transistor; FIG. -J is connectorless FIG. 97 is a schematic diagram of a basic floating body DRAM; FIG. 98A-H is a schematic view of forming a floating body DRAM transistor; FIG. 99A-M is a schematic view of forming a floating body DRAM transistor; FIG. 100A-L is a floating body FIG. 101A-K is a schematic view showing the formation of a resistive storage transistor; FIG. 102A-L is a schematic view of forming a resistive storage transistor; FIG. 103A-M is a schematic view of forming a resistive storage transistor; 104A-F is a schematic diagram of the formation of a resistive storage transistor; FIG. 105A-G is a schematic diagram of the formation of a charge trapping type transistor; FIG. 106A-G is a schematic diagram of the formation of a charge trapping type transistor; FIG. 107A-G is a floating gate storage type. Schematic diagram of crystal formation; Fig. 108A-H is a schematic view of the formation of a floating gate storage transistor; Fig. 109A-K is a schematic diagram of the formation of a resistive storage transistor; Fig. 110A-J is a molding of a resistive storage transistor with an upper edge Schematic diagrams; FIGS. 111A-D are schematic diagrams of a general layer ablation process and a window thereof; FIG. 112 is a schematic diagram of a 3D IC system with a heat sink; FIG. 113A-B is a schematic diagram of a 3D-IC of an integrated heat discharge device; Field repairable Schematic diagram of a 3D IC system; FIG. 115 is a schematic diagram of a 3-modal redundant 3D IC system; FIG. 116 is a schematic diagram of a group scanning architecture of the prior art; FIG. 117 is a schematic diagram of a boundary scan architecture of the prior art; and FIG. 118 is a BIST architecture of the prior art. FIG. 119 is a schematic diagram of another field repairable 3D IC system; FIG. 120 is a schematic diagram of a scan trigger that can be used for the 3D IC shown in FIG. 119; FIG. 121A is a schematic diagram of a third field repairable 3D IC system; 121B is the other side of the field repairable 3D IC system in Figure 121A; Figure 122 is a schematic diagram of the fourth field repairable 3D IC system; Figure 123 is a schematic diagram of the fifth field repairable 3D IC system; Figure 124 is the sixth A schematic diagram of a field-serviceable 3D IC system; Figure 125A is a schematic diagram of a seventh field-serviceable 3D IC system; Figure 125B is the other side of the field-serviceable 3D IC system in Figure 125A; Figure 126 is the eighth field-serviceable Schematic diagram of a 3D IC system; Figure 127 is a schematic diagram of a second 3-modal redundant 3D IC system; Figure 128 is a schematic diagram of a third 3-modal redundant 3D IC system; Figure 129 is a fourth 3-modal redundancy Schematic of the remaining 3D IC system FIG. 130A is a schematic diagram showing the overlapping manner of the first via technology; FIG. 130B is a schematic diagram of the overlapping manner of the second via technology; FIG. 130C is the alignment of the over-hole technology overlapping manner of the field repairable 3D IC in FIGS. 130A and 130B. Figure 130D is a side view of the structure of Figure 130C; Figure 131A is a schematic view of the third via technology overlap mode; Figure 131B is a schematic view of the fourth via technology overlap mode; Figure 131C is Figure 131A, 131B and 131C Schematic diagram of the overlap mode of the via technology; FIG. 132A is a schematic diagram of the fifth via technology overlapping manner; FIG. 132B is a schematic diagram of the alignment of the 3D IC via metal overlap mode in FIG. 132A; FIG. 133A-I is a source with a source Schematic diagram of the formation of the recessed channel array transistor of the germanium and germanium; FIG. 134A-F is a schematic diagram of the process of the 3D IC FPGA processor; FIG. 135A-D is a schematic diagram of an alternative of the 3D IC FPGA processor; Schematic diagram of the FPGA setting chip; Figures 137A-G are schematic diagrams of the 3D IC NVM FPGA setting wafer processing flow.

The case of this invention will be described below with reference to the drawings. It is generally understood that those skilled in the art will be able to explain the invention and not to limit the understanding of the invention, and the drawings need not be enlarged. At the same time, people will also realize that by applying the principles of this invention, more cases can be created, and these cases will fall within the scope of patent protection of this invention, unless otherwise stated in the attachment patent statement.

1 is a schematic circuit diagram of the prior art, for example, 860-1 to 860-4 are programmable transistors for programming 850-1,1.

2 is a partial cross-sectional view of the prior art circuit diagram of FIG. 1 with the programming transistor 860-1 incorporated as part of a germanium substrate.

Figure 3A is a schematic illustration of a programmable connection board. 310-1 is one of four horizontal metal strips that form a parallel strip. Today, general ICs have multiple metal layers. In a typical programmable component, the first two or the first three metal layers can be used to build logic components. Above them, the metal layer 4-metal layer 7 is used to construct the wiring circuit of the logic component. In an FPGA component, the logic components are programmable, as are the routing circuits between the logic components. The configurable wiring circuit of the present invention is constructed from the fourth metal layer or above. For example, the metal layers 4 and 5 can serve as long strips, and the metal layers 6 and 7 can constitute short strips. Typically, the strips form a programmable wiring circuit having the same length and direction of extension, just like 310-1, 310-2, 310-3, 310-4, forming parallel strips. Usually one band contains 10-40 plug strips. Typically, the strips of the subsequent layers will extend in a vertical direction, as shown in Figure 3A, with the strips 310 of the metal layer 6 and the strips 308 of the metal layer 7 (i.e., in a vertical relationship). In this example, the insulator between the metal layer 6 and the metal layer 7 forms a location for refractory storage at the intersection of the strips between the metal layers 6 and 7. Plate 300 includes 16 such anti-fuse stores. 312-1 is the anti-fuse storage located at the intersection of the strips 310-4 and 308-4. When turned on, it can be inserted into strip 310-4 and docking strip 308-4. Figure 3A is a simplified diagram. Typically, each layer of the board contains 10-40 strips and has a plurality of such boards containing an anti-fuse storage configurable wiring circuit structure.

304 is a Y programmable transistor connected to the strip 310-1. 318 is an X-programmable transistor connected to the strip 308-4. 302 is a Y selection logic that allows selection of a Y programming transistor during the programming phase. 316 is an X selection logic that allows selection of an X programming transistor during the programming phase. Once 304 and 318 are selected, the programming voltage 306 is generated on the strip 310-1 while the strip 308-4 is grounded such that the anti-fuse storage 312-4 is turned "on".

3B is a schematic diagram of a programmable connection structure 300B; 300B is a variation of 300A, and some of the strips of the energy band have different lengths. In this variant, there is no patch strip 308-4, only two shorter patch strips 308-4B1 and 308-4B2. This may be beneficial for the signal input and output of the programmable wiring circuit structure 300B. In order to reduce the number of the strips in one board, these short strips can be used for inputting and outputting signals in the wiring circuit structure, unlike the previous insertion. Pick up the strip for path selection. In this variation, the programming circuitry needs to be scaled up to support programming against the fused stores 312-4B and 312-4B.

Unlike the prior art, various cases in the present invention suggest not to construct a programmable transistor in the 扩散 substrate diffusion layer, but to set the operating voltage of the anti-fuse storage wiring. This is also part of the anti-fuse storage structure setting so that the anti-fuse storage is not easily turned on. In addition, it should be noted that settings may be required and the source is added to ensure that the programming process does not damage the working circuit. Therefore, when an anti-fuse memory programmable transistor is included on a germanium substrate, additional dummy areas are required and very careful.

In order to meet the performance requirements of high speed components, the maximum requirement for a working transistor is speed, while the programming circuit can operate at a relatively low speed. Therefore, the programming circuit can use a thin film transistor, which can well satisfy the function and reduce the requirement on the area of the cymbal.

There are other types of transistors, such as vacuum FETs, bipolar tubes, etc., which can also be used in a programmable circuit or not on a ruthenium base, but on an upper or lower layer of a refractory storage configurable wiring circuit.

However, in another alternative, the programmable transistor and programmable circuitry can be fabricated on an SOI wafer, then bonded to a configurable logic wafer and using a via straight through hole (TSV) Or through layer vias (TLV). The advantage of using the SOI wafer to implement the anti-fuse storage programming function is that it is built on the wafer.

High voltage transistors are very efficient and can be used to program circuits and support functions such as programming controller functions. In addition, a programmable circuit can be fabricated on previous SOI wafer processes to further reduce cost. It can also be used in other process technologies and/or manufacturing locations around the world.

There are other processing techniques that can integrate chip or other semiconductor layers on the anti-fuse storage configurable wiring circuit to realize the construction of the anti-fuse storage programmable circuit. As an example, there has recently been a technique for spraying a semiconductor grade crucible using a plasma gun to form a semiconductor structure, including, for example, a p-n junction. The type of corresponding semiconductor formed by spraying germanium is predictable. In addition, there are more and more technologies that use graphene and carbon nanotubes (CNTs) to achieve semiconductor functions. Based on the present invention, we will use the phrase "thin film transistor" as a general term for the above technology, and also includes all known or unknown similar techniques.

In short, a common goal is not to re-set, to reduce the cost of mass production at the minimum cost of masking. The use of thin film transistors as programmable transistors enables relatively simple and straightforward bulk cost savings. There is no need to embed anti-fuse storage in the isolation layer, and custom masks can be used to define vias in all final locations, even though each of these vias previously had separate open anti-fuse storage. In addition, the same connection that needs to be programmed before can be connected through a fixed via. This may save the cost associated with manufacturing the anti-fuse memory programming layer and programming circuitry. It should be noted that there may be a difference between the anti-fuse storage resistor and the via resistance defined by the mask. The conventional approach is to create an analog model of the two options, which is verified by the setter as to whether the settings in both cases are feasible.

Another purpose of building a programming circuit over the anti-fuse storage layer is to achieve higher circuit density. In order to connect the programming transistor to the respective metal strip, a number of connections may be required. If these connections are up, the routing circuit paths of the underlying connections may not be blocked, thereby reducing the circuitry above.

As shown in FIG. 3A, a 4x4 plug strip wiring circuit structure, usually a wiring circuit structure may include a plurality of 20x30 plug strips. For a 20x30 board, approximately 20+30=50 programming transistors are required. The 20x30 board area is approximately 30hpx30vp, with "hp" identifying the horizontal spacing and "vp" identifying the vertical spacing. This can result in a relatively large area of programmable transistors, approximately 12 hp x vp (20 hp x 30 vp / 50 = 12 hp x vp). In addition, there is a need to deal with: the available area between the programmable layers, each connection, and the programmable wiring circuit structure. Also, one or two of the redistribution layers may need to redistribute the connections within the available area, and then build these connections down, preferably aligned, such that the layer strips 310 are connected below the programmable wiring circuit structure. The obstacles caused by the process are minimal.

4A is a schematic illustration of a programmable connection board 300 and another programmable connection board 320. Due to the higher density of germanium, a configurable wiring circuit can be built on the board in the most compact manner. 4B is an illustration of a 2x2 programmable wiring circuit board; including a checkerboard shaped board 300 and a board 320, which is a variation of the board 300 rotated 90 degrees. When a signal is transmitted from south to north, anti-fuse storage, such as 406, is required to connect the north-south plug strip. Both 406 and 410 are anti-fuse storages located at the end of a patch strip that connects the other strips in the same direction. The signal is transmitted from the metal layer 6 to the metal layer 7 from south to north. If you need to change direction, use anti-fuse storage like 312-1.

The configurable wiring circuit structure may include: connecting the output logic chip and the input logic chip to construct a part of the custom logic required. The logic chip itself is constructed through the first few metal layers and the transistors on the germanium substrate. Metal layer 1 and metal layer 2 are typically used to build logic wafers. Sometimes it is also effective to use metal layer 3 or a portion of layer 3.

FIG. 5A is a schematic diagram of inverter 504 and its input 502 and output 506. The inverter is the simplest logic chip. Input 502 and output 506 can be connected through a strip of configurable wiring structures.

FIG. 5B is a schematic diagram of buffer 514 and its input 512 and output 516. Input 512 and output 516 can be connected through a strip of configurable wiring structures.

FIG. 5C is a schematic illustration of a settable intensity buffer 524 and its input 522 and output 526. Input 522 and output 526 can be connected through a strip of configurable wiring structure. 524 can be set through anti-fuse storages 528-1, 528-2, and 528-3, which constitute an anti-fuse storage configurable drive wafer.

Figure 5D is a schematic diagram of D-flip flop 534 and its inputs 532-2 and output 536, including control inputs 532-1, 532-3, 532-4, and 532-5. The control signal can be connected to a configurable wiring circuit or a local or global control signal.

Figure 6 is a schematic diagram of the LUT 4. The LUT4 604 is a common logic component in FPGA technology called the 16-bit lookup table or LUT4. The assembly has four inputs 602-1, 602-2, 602-3, and 602-4. An output 606. Usually a LUT4 can be programmed to implement any logic function that requires less than or equal to 4 inputs. The LUT function of Figure 6 can be implemented by 32 anti-fuse storage such as 608. The 604-5 is a 2-1 multiplexer. In FPGAs, the most common implementation of LUT4 is to use a 16-bit SRAM chip or a 15-way multiplexer. Figure 6 shows a method for setting up a look-up table for LUT4 anti-fuse storage through 32-bit anti-fuse storage and a 7-way multiplexer. The programmable die of Figure 6 includes additional inputs 602-6, 602-7, each with an 8-bit anti-fuse storage that allows for functions other than LUT4.

Figure 6A is a schematic diagram of a PLA logic chip 6A00. This chip is used in most common programmable logic machines before the LUT logic becomes mainstream. Other abbreviations for such logic are PLD and PAL. The 6A01 is a type of anti-fuse storage that allows selection of input signals for multiple inputs AND6A14. In this figure, all of the vertical and horizontal line intersections contain an anti-fuse storage that enables the connection to be made in accordance with the desired final function. The large AND chip 6A14 constitutes a product term, and implements an input selection AND function of 6A02 or a reverse copy. A multi-input or 6A15 implements the OR function based on the selection of the product term to form an output 6A06. Figure 6A shows an anti-fuse storage settable PLA logic.

The logic chips in Figures 5, 6 and 6A are only representative. There are many different ways to construct a programmable logic structure, including attaching logic wafers such as AND, MUX, and other wafers, as well as variations of the above described wafers. In addition, in the construction of the logic chip, there may be different forms due to the configurable wiring circuit structure used for the input and output connections or the connection using the direct non-configurable mode.

FIG. 7 is a schematic diagram of a programmable wafer 700. A programmable structure can be built by tiling the above wafers. The tiling of the same wafer can be repeated to form a homogenous structure. Additionally, mixing of different wafers can result in a non-uniform structure. Logic wafer 700 may be any of Figures 5 and 6, the above-described hybrids, and their predecessors. Logic chip 710, input 702, and output 706 are both coupled to settable wiring structure 720 through input and output strips 708 and associated anti-fuse storage 701. The shorter wiring circuit 722 includes a metal strip, the length of which is the same as the board, including the horizontal strip 722H, located in one metal layer, the vertical strip 722V, in another metal layer, and the anti-fuse storage 701HV is located at the intersection thereof. This makes it possible to select horizontal and vertical patch strips and connections. The connection of the horizontal plug strip to the other horizontal plug strip is achieved by the anti-fuse storage 701HH, and the function is the same as the anti-fuse storage 410 of FIG. The connection of the vertical plug strip to the other vertical strip is achieved by the anti-fuse storage 701 VV, which has the same function as the anti-fuse storage 406 of FIG. The long horizontal strip 724 is used to connect long distance signals, typically having a length of 8 boards or more. Usually a long-distance plug strip has an optional connection that reduces travel by anti-fuse storage 724LH, while the vertical long-distance plug strip uses 724. FIG. 7 is a two-dimensional diagram of a programmable wafer 700. In actual use, 700 is a three-dimensional structure, and the logic wafer 710 uses a germanium base, metal layers 1, 2, and 3. The programmable wiring structure includes a connected anti-fuse storage on which the anti-fuse storage is located.

Figure 8 is a schematic illustration of a programmable component layer structure, which is an alternative to the present invention. In this scheme, the anti-fuse storage consists of a two-layer structure. The first layer is used to set the logic area and, in some cases, to set the logical clock distribution. The first anti-fuse storage layer can also be used to manage certain power distributions, saving power by disconnecting power from unused circuitry. This layer can also be used to connect certain long-distance transmission paths and/or input and output of connected logic chips.

The fabrication of the assembly is illustrated in Figure 8, starting from a semiconductor substrate 802 comprising a logic die transistor, the substrate further comprising a first anti-fuse memory layer programmable transistor. Next is the 804 layer, including the metal layer 1, the insulator, the metal layer 2, and sometimes the metal layer 3. These layers are used to build logic wafers, I/O and other analog wafers. In this alternative, the first anti-fuse storage is included in the isolation layer, between the metal layer 1 and the metal layer 2, or an isolation layer between the metal layer 2 and the metal layer 3, the programming transistor can be embedded in Located in the germanium substrate 802 under the first anti-fuse storage. The first anti-fuse memory can be used to program logic chips, such as 520, 600, 700, and can also be used to connect individual wafers for greater logic. The first anti-fuse storage can also be used to edit the logic clock distribution. The first anti-fuse storage layer can also be used to manage certain power distributions, saving power by disconnecting power from unused circuitry. This layer can also be used to connect certain long distance transmission paths and/or to connect the inputs and outputs of these wafers.

The following layers 806 may form a long-distance routing channel for all or part of the power distribution and clocking network, complementing the structure of the first few layers 804.

The following base layer 807 may include an anti-fuse storage configurable wiring structure. It can also be called a short distance wiring structure. If the metal layers 6 and 7 are used for the strip of the configurable wiring structure, the second anti-fuse storage can be embedded in the insulating layer between the layer 6 and the layer 7.

The programming transistor and other portions of the programming circuit can be used for subsequent fabrication, over the configurable routing structure 810. The programming component can be a thin film transistor or other peroxide crystal as described above. At this point, the anti-fuse memory programming transistor is disposed over the anti-fuse layer, providing the possibility to implement the settable wiring circuit 808 or 804. It should be noted that in some cases it may be beneficial to construct a control logic for the second anti-fuse memory programming circuit on the base layers 802 and 804.

The final step is the connection to the external 812. Solder joints can be used for wire bonding, or solder balls can be used to connect flip chip, optoelectronic or other connection structures such as TSV connections.

In another alternative of the invention, the anti-fuse storage programmable wiring structure can be used to set a variety of uses. The same structure can be used as part of the wiring structure, or as part of a PLA logic chip, or as part of a read-only memory (ROM) function. In an FPGA product, one component may be required for multiple uses. Equipped with versatile system resources to increase the usability of FPGA components.

FIG. 8A is a schematic diagram of a programmable component layer structure, which is another alternative of the present invention. In this alternative, there is an attached circuit 814 that is in contact with 816 to the first anti-melting layer 804. The programming transistor of the first anti-fuse storage layer 804 is provided by the underlying components. Thus, the diffusion layer 816 of the programmable component does not have to bear the cost of programming the transistor for the first anti-fuse layer 804. Correspondingly, the programming connection of the first anti-fuse layer 804 can be directly connected to the lower programming component 804, and the programming connection with the second anti-fusing layer 807 can be directly connected to the programming circuit 810. This reduces congestion on the routing path inside the circuit.

The number 808 in the subsequent figures may be a combination of various pre-processed wafers or layers comprising a plurality of transport layers (combinations) of the present invention. The phrase "pre-processed wafer or layer" is used generically; when the number 808 is used in the drawings to illustrate the case of the invention, the number 808 may represent a plurality of different pre-processed wafer or layer types, including but not limited to Lower prefabricated layer, underlying wiring wire, base layer, substrate layer, outer casing wafer, target wafer, pre-processing circuit, pre-processed circuit acceptor wafer, substrate wafer layer, underlayer, underlying main wafer, base layer , top layer, or factory wafer.

Figure 8B is a general purpose preprocessed wafer or layer 808. The wafer or layer 808 may contain pre-processing circuitry, such as logic circuitry, microprocessors, circuitry including various transistors, other types of digital or analog circuitry, including, but not limited to, various examples in the present invention. The pre-processed wafer or layer 808 may contain pre-processed metal wiring circuitry, possibly made of copper or aluminum. The pre-processed metal wiring circuitry may be used for the setup or fabrication of layer transfers, and also includes electrical connections from pre-processed wafers or layers 808 to the layers or transport layers.

Figure 8C is a schematic illustration of the universal transfer layer 809 prior to processing to the preprocessed wafer or layer 808. The transport layer 809 can be processed onto a carrier wafer or substrate wafer during the layering process. The preprocessed wafer or layer 808 can be the target wafer, the receiver substrate or the receiver wafer. The receptor wafer may contain acceptor wafer metal bond pads or strips that are configured for electrical connection to the transfer layer 809. The transport layer 809 can be processed onto a carrier wafer or substrate wafer during the layering process. The transfer layer 809 can contain metal wiring circuitry that is fabricated for layer or electrical connection with the preprocessed wafer or layer 808. A via via (TLV) connection can be used for electrical connections from the transfer layer 809 to the preprocessed wafer or layer 808. The transport layer 809 may comprise single crystal germanium, crystalline germanium, or a predictable crystalline germanium single layer or multiple layers, other semiconductor, metal and insulator materials, layers, etc.; or a plurality of single crystal germanium regions, predictable single crystal germanium, or other semiconductors , metal, or insulator material.

Figure 8D is a schematic illustration of a pre-processed wafer or layer 808 formed by layer cutting of the upper transfer layer 809. Over the pre-processed wafer or layer 808, a pre-processed metal wiring circuit may be further processed for the fabrication of the layer transfer, including electrical connections from the pre-processed wafer or layer 808 to the layer or transport layer.

Figure 8E is a schematic illustration of the universal transfer layer 809A prior to processing to the preprocessed wafer or 808A layer. Transfer layer 809A can be processed onto a carrier wafer or substrate wafer during the layering process. The transfer layer 809A may contain metal wiring circuitry that is configured to be fabricated for layer or electrical connection with the preprocessed wafer or 808A layer.

Figure 8F shows the pre-processed wafer or 808B layer formed by layering of the overlying transfer layer 809A through the pre-processed wafer or layer 808A. Over the pre-processed wafer or layer 808B, the pre-processed metal wiring circuitry may be further processed for setup fabrication of the layer transfer, including electrical connections from the pre-processed wafer or 808B layer to the layer or transport layer.

Figure 8G is a schematic diagram of the universal transfer layer 809B prior to being processed into a preprocessed wafer or 808B layer. Transfer layer 809B can be processed onto a carrier wafer or substrate wafer during the layering process. The transfer layer 809B may contain metal wiring circuitry that is configured to be fabricated for layer or electrical connection with the preprocessed wafer or 808B layer.

Figure 8H shows the pre-processed wafer or 808C layer formed by layering of the overlying transfer layer 809B through the preprocessed wafer or layer 808B. Over the pre-processed wafer or 808C layer, the pre-processed metal wiring circuitry may be further processed for setup fabrication of the layer transfer, including electrical connections from the pre-processed wafer or 808C layer to the layer or transport layer.

Figure 8I is a pre-processed wafer or 808C layer, a 3D IC stack that may include trimmed layers 809A and 809B over a pre-processed wafer or layer 808. The cut-out layers 809A and 809B and one or more of the initial pre-processed wafer or layer 808 may comprise one or more types of transistors, metallization, such as one or more layers comprising copper or aluminum, interlayer upper and lower wiring circuits, and In-layer wiring circuit. Between the layers, the transistors within one layer can be of different types. The arrangement of the transistors can also be in a variety of ways. The arrangement of the transistors may be a repeating arrangement or a strip arrangement. The transistor can be arranged in multiple layers within the transport layer. The arrangement of the transistors can be an electrodeless transistor or a recess via transistor. The cut-out layers 809A and 809B, and the pre-processed wafer or layer 808 may also include semiconductor components such as resistors, capacitors, inductors, one or more programmable wiring circuits, storage structures and components, sensors, microwave components, and The optical wiring circuit to which the microwave transceiver is connected may be referred to as a "support wafer" or a "carrier substrate" as a "support wafer" or a "support substrate."

The layer-cutting process can be repeated multiple times to produce pre-processed wafers containing multiple cut-out layers that can be combined to continue layer-cutting as a pre-processed wafer or layer. The layer-cutting process is flexible enough to allow the pre-processed wafer and transfer layer to be flipped and cut on either side under appropriate manufacturing insertion conditions, continuing to cut in any direction according to the settings.

Only those with basic knowledge will readily understand the examples in Figure 8 - Figure 8 (not enlarged). At the same time, people will further realize that using pre-processed wafers or 808 layers as the base or substrate layer, or as a pre-processed or partially pre-processed circuit acceptor wafer, using the wafer ablation process can produce more The deformation. After reading this description, one will appreciate that the scope of the invention will encompass a number of modifications. Therefore, this invention is not limited to the patent claims in the attachment.

An alternative to this underlying circuit is the "SmartCut" smart cutting process. The “SmartCut” smart cutting process is widely used in the manufacture of SOI wafers. The smart cutting process, combined with wafer bonding technology, enables "layer cutting" to produce a thin layer of single crystal germanium wafers from one wafer after another. "Layer cutting" can be done below 400 degrees Celsius, and the cut-out layer produced can be less than 100 nm thick. There are two companies that have used multiple variants and names for commercial use, namely Soitec (Crolles, France) and SiGen-Silicon Genesis (San Jose, Calif.). The enamel bonding process at room temperature uses a particle beam to treat the ruthenium surface under vacuum and has recently been monopolized by Mitsubishi Heavy Industries Group (Tokyo, Japan). This process is capable of cutting the enamel layer at room temperature.

In addition, other technologies are included in the use. For example, other techniques can also be used for layer cutting, such as the IBM layer cutting process, as described in IEDM 2005, A. W. Topol, and the like. The IMB layering process uses an SOI technology and a glass substrate wafer. The power supply circuit can be subjected to high temperature processing on the SOI wafer, temporarily bonded to the borosilicate glass substrate wafer, chemically polished to thin the back surface, and then the buried oxide (BOX) is etched away. At this point, the thinned power supply wafer is aligned and the low temperature oxide is bonded to the receiving wafer surface. The thinned power supply wafer is then separated from the glass substrate wafer and processed through the via via connections. In addition, the electron beam transfer (ELO) technology, as described by P. Demeester et al., was published by IMEC in the 1993 issue of semiconductor science and technology and can also be used for layer cutting. The ELO selectively removes the very thin sacrificial layer between the substrate and the layer to be sliced. The GaAs or tantalum layer can be "rolled" using a viscous cylinder or removed from the substrate using a flexible carrier, such as black wax, which lifts the structure to be sliced. This process occurs simultaneously with selective etching, which can be diluted using etching. The hydrofluoric (HF) acid, which removes the layer from which the surface needs to be detached, may be an oxide of SOI or AlAs. After the bulk implantation, the cut-out layer is aligned and bonded to the desired receiving substrate or wafer. The production capacity of the ELO process in multi-layer cutting is improved by J. Yoon et al., J. Yoon from the University of Illinois at Champaign, and the article was published in the May 20, 2010 issue of Nature. Canon has developed a layer-cutting technique called ELTRAN-porous twin film layer cutting. ELTRAN can also be used. According to the Electrochemical Association Conference Abstract No. 438, 2000, and July 2001 JSAP International papers, seed wafers oxidized by HF/ethanol solution can produce pores on the surface of the crucible, which can be treated with low temperature oxidation. The pores are then sealed using hydrogen reduction at elevated temperatures. The twin film can then be placed on a porous crucible and oxidized to form a SOI BOX. The seed wafer can be bonded to the substrate wafer and aligned with the porous layer using high pressure water to split the seed wafer. The porous tantalum can then be selectively etched to form a dense layer of tantalum.

Figure 14 is a schematic diagram of a layer cutting process. In another alternative of the invention, "layer cut" is used to construct the underlying circuitry 814. 1402 is a processed wafer used to construct the underlying circuitry. Wafer 1402 can be used in most advanced processes, or in recent generations. It can contain programming circuitry 814, as well as other useful structures, and can be used as a pre-processed CMOS germanium wafer, or as a partially processed CMOS, or other fabrication germanium or semiconductor substrate. Wafer 1402 may also be referred to as a receiving substrate or a target wafer. Subsequently, an oxide layer 1412 will be placed on the wafer 1402 for sanding to achieve a better level and surface rating. The power supply wafer 1406 is then bonded to the 1402. The surfaces of the power supply wafer 1406 and the wafer 1402 are pretreated using various surface treatment methods for low temperature bonding, and the surface treatment includes RCA pre-cleaning, which may include diluted ammonium hydroxide or hydrochloric acid, and may also include electricity. Pulp surface treatment to reduce bonding energy and improve wafer-to-wafer bonding strength. The power supply wafer 1406 is pretreated by intelligent cutting of the particle implant, and the atomic type may include H+ ions, and the required depth is determined according to the line of the smart cut 1408. The wisdom cut score line 1408 can be a layer cut plane, as indicated by the dashed line. The smart cut score line 1408 or the layer cut division plane may be formed before or after the processing of the power supply wafer 1406. The power supply wafer 1406 can be bonded to the wafer 1402 by strengthening the oxide-oxide bond by contacting the surface of the power supply wafer 1406 with the surface of the wafer 1402 and then applying mechanical force and/or annealing reduction. The alignment of the power supply wafer 1406 with the wafer 1402 can be performed immediately after the wafer is bonded. Acceptable bond strengths, including annealing bonding cycles, should not exceed 4000C. After bonding the two wafers, a smart cut is made to cut and clear the top 1414 of the power supply wafer 1406 along the cut layer 1408. Cutting can be done using a variety of energy methods, cutting to the wisdom cutting line 1408 or layer cutting plane, including mechanical cutting of the knife, water jet impact, air cutting, or in-situ laser annealing or other suitable means. A 3D wafer 1410 is obtained comprising a wafer 1402 and a single layer germanium (or multilayer material) attachment layer 1404. Layer 1404 can be polished by chemical or mechanical means to achieve a suitable surface quality for subsequent processing. Layer 1404 can be very thin, between about 50-200 nm. The above required process is called "layer cutting". Layer cutting is commonly used in SOI manufacturing processes, and SIO is an insulating germanium wafer. For SOI wafers, the upper surface has been oxidized such that after "layer cutting", a buried oxide-BOX is obtained, separating the top thin single crystal germanium layer from the wafer body. The use of implanted atoms, such as hydrogen or helium or hydroquinone mixtures, is capable of producing the above-described cutting plane, and also "ion-cutting" in this document, which is a preferred solution for the layer cutting method.

Only those with basic knowledge will easily understand the examples in Figure 14 (not enlarged). In general, one can further realize that, for example, a deep doped (greater than 1e20 atoms/cm3) boron layer or germanium (SiGe) layer can be used as an etch stop for ion-cutting process flow, layer cutting division The plane can be placed in the etch stop layer or placed below the substrate material, or the stop layer can be etched without the implant cutting process, or the donor wafer can be preferentially etched until the etch stop layer is reached. It is further recognized that oxides in SOI or GeOI donor wafers can be used as etch stop layers. After reading this description, one will realize that the scope of the invention will encompass a wide variety of modifications. Therefore, this invention is not limited to the patent claims in the attachment.

Thus, the "layer-cut" process can be used to bond a thin single-crystal germanium layer 1404 on the pre-processed wafer 1402. A standard process ensures that the remainder of the desired circuitry is as shown in Figure 8A, from the cut-out layer 1404. The upper layer 802 begins. The printing step uses alignment marks on wafer 1402 to enable circuits 802 and 816 and the like to be correspondingly coupled to lower layer circuit 814. One factor that needs attention is the high temperature, which may require a high temperature environment during processing of the circuit 802. The pre-processing circuitry on wafer 1402 is subject to high temperatures and is used to turn on semiconductor transistor 802 constructed on layer 1404. The circuitry on wafer 1402 will contain transistors and polysilicon local wiring circuits (polysilicon or poly) and some other types of circuits that can withstand high temperatures, such as tungsten (circuitry). The processed wafer can support the subsequently processed transistor at a high temperature, which can be referred to as a "base" or substrate, a base layer, or a base circuit. The advantage of using layer-cutting to build the underlying circuit is that the layer-cut 1404 can be made very thin, allowing the via-via via 816, or via via (TLV) to have a low aspect ratio and be closer to the normal contact. So it can be done very small, minimizing the area of expenditure. The thinner cut-out layer can also increase the density of the via via connection 816 using conventional direct via alignment techniques.

Figure 15 is a schematic diagram of the underlying programming circuit. The become transistors 1501 and 1502 are both prefabricated on the substrate 1402, and then the programmable logic circuit and the anti-fuse storage 1504 are machined on the cut-out layer 1404. The programming connections 1506, 1508 are connected to the programming transistor by contact holes through the layer 1404, as shown at 816 in Figure 8A. The transistor is set to withstand the higher programming voltage when the anti-fuse memory 1504 is programmed.

Figure 16 is a schematic diagram of the underlying isolation transistor circuit. Changing the anti-fuse storage 1604 to a high voltage may damage the logic transistors 1606, 1608. In order to protect these logic circuits, the transistors 1601, 1602 are isolated, so that the set transistor can withstand higher voltages. The higher programming voltage is only used during the programming phase while the isolation transistor is turned off by the control circuit 1603. The underlying wafer 1402 can be used to build isolated transistors. Since the programming transistor and the isolation transistor on the substrate 1402 are large, the primary crystal 802 (1404) can be better utilized. Usually primary crystal germanium is manufactured in a prior process to achieve high density and performance. The substrate can be fabricated in a later process step to reduce cost and support high voltage transistors. It may also be processed without a CMOS transistor, such as with a double diffused metal oxide semiconductor (DMOS) or a bipolar power saver, which facilitates the turning and isolation functions. In most cases, the gate input requires a protective diode called an antenna. Such a protective deposition can effectively integrate the input of the isolation transistor into the substrate. In addition, the isolation transistors 1601, 1602 can also provide protection against antenna effects without the need for additional diodes.

Another alternative to this invention is to pre-process the base layer 1402 to machine a pair of reverse bias generators. One of the main challenges of advanced semiconductor logic components is wafer-to-wafer and parametric deviations within the wafer. Due to dopants and the like, various portions of the wafer may have different conductive characteristics. Among the parameters that have the greatest influence on the deviation is the 阙 voltage of the transistor. The difference in 阙 voltage across the wafer is primarily due to channel dopants, gate insulators, and critical dimension differences. The impact of these differences on the sub-45nm process node components is enormous. The usual way of thinking is to consider the worst case when setting, resulting in a large performance expense. In addition, a new set of ideas is being proposed to address the huge uncertainty in the capacity and cost of the bias problem. Possible solutions include the use of local reverse bias to improve the performance of the worst-case region and improve overall performance while consuming minimal additional power. Basic-local reverse bias can also be used to reduce leakage due to process variations.

17A is a topological diagram of a reverse bias circuit. The substrate 1402 carries the reverse bias circuit 1711, which can improve the performance of the primary component portion 1710, otherwise the performance of these regions will remain low.

17B is a schematic diagram of a reverse bias circuit; the reverse bias control circuit 1720 controls the oscillators 1727 and 1729 to drive the reverse bias generator 1721. The negative reverse bias generator 1725 will generate the desired negative bias voltage through connection 1723 to the main circuit to provide a reverse bias to the N-channel metal oxide semiconductor (NMOS) transistor 1732 on the primary germanium 1404. . The forward and reverse bias generator 1726 will generate the desired negative bias voltage through connection 1724 to the main circuit to provide a reverse bias to the P-channel metal oxide semiconductor (PMOS) transistor 1724 on the primary germanium 1404. . The magnitude of the corresponding reverse bias is set according to the region in the initialization phase. It can be set using an external tester and controller, or it can be done using a on-chip self-test circuit. Typically, permanent storage is used to preserve the reverse bias of each region so that the component can be properly initialized when it is turned on. In addition, dynamic scheduling can be used to set the required reverse bias magnitude for components of different operating modes. Setting the reverse bias circuit in the substrate can better utilize the chip resources of the primary crystal component, so that the logic operation distortion of the main chip component is less.

Figure 17C is an alternative circuit function that can also be used for "base." In many IC settings, power control needs to be integrated to reduce power to the magnetic regions of the component, or to cut off the corresponding power when the magnetic regions are completely "sleeping". Typically, these power control controls are preferably accomplished using high voltage transistors. Therefore, it may be necessary to build a power control circuit chip 17C02 on the substrate. The power control 17C02 can use its own high voltage to power and control or adjust the supply voltage of the 17C10 and 17C08 magnetic regions on the main chip assembly. Control can be initiated by the main piece assembly 17C16 and managed by 17C04 on the substrate.

Figure 17D is an alternative circuit function that can also be used for "base." In many IC settings, the probe assist system needs to be integrated so that components can be easily detected during the commissioning phase and production testing is supported. The probe circuit is also used in the prior art, using the same transistor as the main circuit. Figure 17D shows the probe circuit constructed under the active layer of the primary layer on the substrate. Figure 17D shows the connection to the continuous active circuit assembly 17D02. The connection is connected to the substrate through the interconnection circuit 17D06, and the high resistance probe circuit 17D08 is used to detect the output of the subsequent components. The selection circuit 17D12 allows one or more outputs to be transmitted through one or more buffers 17D16. The buffers can be controlled by signals on the primary crystal circuit to drive the sequential output signals to the probe signal output 17D14 for debugging or testing. It is generally understood that, for example, a plurality of probe circuits 17D08, a plurality of probe output signals 17D14, and a control buffer 17D16 whose signals are not output from the main circuit are possible configurations.

In another aspect, the substrate 1402 can carry an SRAM wafer, as shown in FIG. SRAM wafer 1802 is prefabricated on underlying substrate 1402 and may be coupled to main logic circuits 1806, 1808 on 1812 through 1404. As discussed above, the layers constructed at 1404 can be aligned with the prefabricated structures on the underlying substrate 1402 such that the logic wafers can be coupled to the corresponding underlying RAM wafers.

Figure 19A is a schematic diagram of the underlying I/O. The substrate 1402 can be pre-loaded with an I/O circuit, or a portion of I/O, such as an output drive 1912 that is relatively large. In addition, the TSV on the substrate can also be used to direct the I/O connection 1914 back to the back of the substrate. Figure 19B is a side cut of an integrated component in accordance with the present invention. The output drivers are shown as PMOS and NMOS output transistors 19B06, and the two transistors are aligned through the TSV 19B10 and connected to the back pad or ball pad 19B08. The material to be bonded in the substrate 1402 can be selected to withstand the high temperatures during the subsequent manufacturing process of the assembly on the entire 1404, as shown in Figures 8A-802, 804, 806, 807, 810, 812, which can be tungsten. The substrate may also be provided with an input protection circuit 1916 to connect the pad 19B08 to the input logic 1920 of the main circuit.

Another example of the invention is the use of TSVs on a substrate, such as TSV19B10, to connect the wafers to form a 3D integrated system. Typically, each TSV requires a larger area, typically a few square microns. When a large number of TSVs are required, the use of high-density transistors is excluded from the occupied area, making the area of all TSVs expensive. On the donor wafer, pre-processing these TSVs using the previous process can significantly reduce the effective cost of 3D TSV connections. The connection 1924 to the primary germanium circuit 1920 can be achieved using a minimum contact area of about a few square nanometers, two orders of magnitude smaller than the area of several square microns required for TSV. The illustrations in Figure 19B (not enlarged) will be readily apparent to those of ordinary skill. It is generally easy to understand that many other strengths and component arrangements can be constructed using the inventive principles described in Figure 19B, and Figure 19B is for reference only.

Figure 19C is a 3D system comprising three connected wafers (19C10, 19C20, 19C30) and TSVs (19C12, 19C22, 19C32), illustrated in a similar manner to TSV19B10 and Figure 19A. The stack of three wafers uses the TSV (19C12, 19C22, 19C32) on the substrate to build a 3D interconnect circuit, so that the primary crystals 19C14, 19C24, and 19C34 are connected to the respective substrates through the smallest-sized vias, and the impact and the area loss of the wafer are minimized. . The three wafer stacks can be connected to the PC motherboard using ball bond 19C40, which is connected to the back side of the wafer TSV19C32. The illustrations in Figure 19C (not enlarged) will be readily apparent to those of ordinary skill. It is generally easy to understand that many other strengths and component arrangements can be constructed using the inventive principles described in Figure 19C, and Figure 19C is for reference only. For example, a wafer stack can be placed in a package using a flip chip bond, or a ball bond 19C40 can be used instead of a bond pad, which is flipped and bonded together with the bond wire in a conventional package.

Figure 19D is a schematic diagram of a 3D IC processor and DRAM system; the well-known problem faced by the computer industry is that the "memory wall" is related to the speed at which the processor accesses the DRAM. The solution given by the prior art is to use a TSV connected directly to the processor to connect the DRAM stack and bump the heat sink against the back of the processor to dissipate heat from the processor. However, doing so requires a special via that passes through the DRAM to allow processor I/O and current to pass through. Excessive processors "wearing DRAM vias" can cause some serious drawbacks. First, it will reduce the available area of DRAM, up to a few percentage points. Then, it will increase the current transmitted above, and the increase is also a few percentage points. In addition, it will be a commercial challenge to require the DRAM settings to be coordinated with the processor settings. The case of Fig. 19D gives a solution to the above problem: the use of a substrate having TSV as shown in Figs. 19B and 19C. The use of a substrate and a primary germanium structure allows the connection to the processor without having to pass through the DRAM.

In Fig. 19D, the processor I/O and voltage can be connected to the underlying microprocessor active region 19D14 - the primary germanium layer, and through the via 19D08 through the heat sink substrate 19D04 to the backplane material 19D06. The heat sink 19D12, the heat sink bottom plate 19D04, and the heat sink 19D02 are all used to remove heat generated by the processor active area 19D14. The TSV (19D22) passing through the bottom plate 19D16 is used to connect the DRAM stack 19D24. The DRAM pair includes a plurality of thin DRAMs 19D18 interconnected by TSVs 19D20. Therefore, the DRAM stack does not need to pass through the processor I/O and voltage plane, and can be independently set and manufactured without regard to processor settings and arrangements. The DRAM wafer 19D18 is closest to the substrate 19D16 and can be set to be connected to the substrate TSV 19D22, or a separate redistribution layer (or RDL, not shown) can be added between them, or the substrate 19D16 can be used as a pre-processed high-temperature wiring layer. , such as the aforementioned tungsten. The other processor active area does not contain a TSV, unlike the substrate 19D16.

Additionally, substrate vias 19D22 can be used to pass through the processor I/O and power, connect substrate 19D04 and substrate material 19D06, while the DRAM stack can be directly coupled to processor active area 19D14. One can easily understand that within the scope of the present invention, more different combinations can be used.

Fig. 19E is another example of the present invention. The DRAM stack 19D24 can be connected to an RDL (Redistribution Layer) 19E26 via a bonding wire 19E24. The RDL connects the DRAM to the substrate via 19D22 and then places them with the processor facing downward. 19D14 is connected.

In another case, custom SOI wafers can be processed at the fab in the NuVias 19F00. The NuVias 19F00 can be used with conventional TSVs, approximately 1 micron in diameter, and is also processed by SOI wafer suppliers. As shown in Fig. 19F, the wafer 19F02 and the purchased oxide BOX 19F01 are processed. The processing wafer 19F02 is usually several hundred microns thick, and the BOX 19F01 has several hundred nanometers thick. The integrated component manufacturer (IDM) or foundry subsequently processes the NuContacts 19F03, which is connected to the NuVias 19F00. NuContact can be a conventional size contact and is etched on a thin SOI wafer 19F05 and BOX 19F01 and then filled with metal. The NuContact size DnuContact 19F04, as shown in Figure 19F, can be machined to the nanoscale. The prior art, as shown in Fig. 19G, is constructed on a bulk wafer 19G00, typically having a TSV diameter, DTSV_prior_art 19G02, and a size on the order of microns. NuContact DnuContact 19F04, as shown in Figure 19F, the reduced size may be important to the semiconductor setter. For the 矽 connection, NuContact can provide reduced wafer size, smaller ultra-thin wafer processing, and smaller setup complexity. On traditional SOI wafers, TSV placement is based on high-capacity integrated component manufacturers (IDMs) or foundries, or in accordance with recognized industry standards.

The flow chart shown in Figure 19H can be used to fabricate conventional SOI wafers. Wafer suppliers may use similar processes. The surface 19H05 can be oxidized by using the main wafer 19H04. An atom, such as helium, is then implanted (doped) to a certain depth of 19H06. The oxide-oxide bond described in other cases can be used to bond the wafer to the receiving wafer 19H08, which has a pre-treated NuVias 19H07 via. NuVias 19H07 can be constructed using conductive materials such as tungsten or doped yttrium to withstand the high temperatures of subsequent processing. An insulating barrier, such as tantalum oxide, may also be used to separate the NuVia 19H07 from the germanium on the receiving wafer 19H08. In addition, wafer suppliers can build NuVias 19H07 using niobium oxide. The integrated component manufacturer or foundry can etch the oxide after the high temperature (greater than 400 degrees) transistor is fabricated and can replace the oxide with metal, copper or aluminum. This process allows for lower melting points, but uses highly conductive metals such as copper or aluminum. After bonding, a portion 19H10 of the donor wafer 19H04 can be cut at 19H06 and then processed by chemical/mechanical polishing as described in other cases.

Figure 19J shows another technique for fabricating a conventional SOI wafer. A standard SOI wafer can be used, as well as the substrate 19J01, BOX 19F01, and the surface layer 19J02. The NuVias 19F00 can be processed in the order from the back side to the oxide layer. This technology may produce a thicker buried oxide 19F01 than the standard SOI process.

Figure 19I illustrates how a custom SOI wafer can be used for 3D stack processing of processor 19I09 and a DRAM 19I10. In the above configuration, the power distribution and I/O connections of one processor are both from the backplane 19I12, through the DRAM 19I10, and then to the processor 19I09. The above technique in Fig. 19F can make the contact area of the DRAM active germanium small, which is very convenient for the application of the preprocessor-DRAM stack. On the DRAM wafer, the area of the transistor lost due to the processing of the through-wafer connections 19I13 and 19I14 becomes very small due to the diameter of the NuContact 19I13 on the active DRAM chip (10 nanometers). When a large through-the-loop connection is located in the middle of the DRAM, occupying a larger area will increase the difficulty of setting. Smaller size piercing connections can cope with this problem. One can easily imagine that this technology can be used to build a processor-SRAM heap, a processor-flash memory stack, a processor-graphics storage heap, a combination of the above, or any other type of integrated circuit. Combinations such as SRAM programmable logic components, and associated setup ROM/PROM/EPROM/EEPROM components, ASIC and power regulators, microcontrollers and analog function circuits. In addition, the insulating germanium (SOI) may be polysilicon, GaAs, GaN or the like on the insulator. It is easy to imagine that the NuVia and NuContact technologies are very versatile and the scope of this invention is not limited to the claims in the annex.

Another example of the invention is that the substrate 1402 can be additionally equipped with a re-driver wafer (commonly referred to as a buffer). Re-driving the wafer is commonly used in the industry for signal transmission with relatively long paths. Since the path has a large resistance and capacity loss, inserting a re-driver along the transmission path helps to avoid severe attenuation of signal timing and shape. The advantage of carrying the re-drive on the substrate 1402 is that the re-drive can be built using a transistor and thus can withstand a large programming voltage. In addition, isolated transistors such as 1601 and 1602, or other isolation schemes, can also be used for the input and output of logic chips.

FIG. 8A is a schematic structural view of a multilayer structure of a programmable component, having two anti-fuse storage layers. The programmable transistor used as the first layer 804 can be prefabricated at 814, and then, using a smart cut, a single crystal germanium layer 1404 is fabricated, followed by the main programming logic 802 and advanced logic transistors and other circuitry. Subsequently, a lower anti-fuse storage 804, a wiring layer 806, a second anti-fuse storage layer, and a settable interconnect circuit 807 are also included in the processing of the multi-metal layer. For the second anti-fuse storage, the programming transistor 810 can also be processed using a second cut-only layer.

Figure 20 is a schematic diagram of the layering process of the second layer. The primary processed wafer 2002 includes all of the previous layers 814, 802, 804, 806, and 807. Subsequently, an oxide layer 2012 will be placed on wafer 2002 for sanding to achieve better leveling and surface grade. The power supply wafer 2006 (or the resectable wafer, as shown in the figure) is then bonded to 2002. The pre-processing of the donor wafer 2006 includes a semiconductor layer 2019 which can then be used to build the surface of the programming transistor 810 as an alternative to TFT transistors. The power supply wafer 2006 can also be pre-processed by intelligent cutting of particle implantation. The atomic type may contain H+ ions, and the required depth depends on the line of wisdom cutting 2008. After bonding the two wafers, a smart cut is performed along the cutting layer 2014 to remove the top layer 2008 of the power supply wafer 2006. In this way, the donor wafer can now also be used to process and reprocess more layers. What is obtained is a 3D wafer 2010 comprising a wafer 2002 and an additional layer 2004 of single crystal germanium (or multilayer material). The cut-out layer 2004 can be very thin, between about 10-200 nm. Using smart cutting, a single crystal semiconductor layer can be fabricated on a pre-processed wafer without annealing the pre-processed wafer to over 4000 degrees Celsius.

The use of a smart cut layer cut does not exceed the upper temperature limit of the underlying pretreatment structure. There are a number of alternative ways to construct the surface layer transistor and accurately align with the underlying pretreatment layer, such as pre-processed wafer or layer 808. Since the cut-out layer thickness is less than 200 nm, the above-defined transistor can be accurately aligned with the pre-processed wafer or the surface metal layer of the 808 layer as needed, and the alignment error of these transistors is less than 40 nm.

An alternative method is to use a thinner single crystal germanium cut-out layer for the growth of the outer edge Ge crystal, which is used as a seed crystal of germanium. Another method is to use a thinner single crystal germanium cut-out layer for growth of the outer edge GexSi1-x. The Ge/Si percentage in these layers is specified by the circuit transistor specification. The prior art provides a method in which a germanium substrate is used to crystallize germanium through oxide pores on the surface of the oxide, and crystals or lattice crystals are grown from the underlying twin crystal. However, this is very difficult on the surface of a plurality of wiring layers. Through layer cutting, we can obtain twin crystals on the surface and make the sowing and crystallization relatively simple, and obtain a superimposed layer. At 300 degrees Celsius, the amorphous ruthenium can be regularly distributed using CVD and aligned with the underlying pattern, which can be a pre-processed wafer or layer 808 and then packaged using a low temperature oxide. A shorter second-order heat pulse melts the tantalum layer while maintaining the temperature of the underlying structure below 400 degrees Celsius. The Ge/Si junction will begin to crystallize or lattice growth, crystallize into ruthenium, or form a Ge X Si1-x layer. Then, doping forms a Ge transistor, which is turned on by a laser pulse without damaging the underlying structure while utilizing the low activation temperature of the impurities in the crucible.

Another method is to perform a layer cut using a preprocessed wafer, as shown in FIG. 21A is a schematic diagram of layer cutting using a pre-treated crystal; a lightly doped P-type wafer (P-wafer) 2101 can process a highly doped N-type (N+) "buried" layer through Doping and opening can also be achieved by shallow N+ doping and diffusion after P-gravitation growth 2106. Additionally, if the performance of the transistor requires the use of a substrate contact, a shallow P+ layer 2108 can be additionally doped and turned on. Figure 21B shows a pre-processed wafer that can be used for layer cutting after doping with atoms. The dopant atoms can be H+. In the lower N+ region, a "cut-out plane" 2110 for smart cutting can be prepared and passed through the oxide. After deposition or growth 2112, an oxide layer for oxide bonding can be formed. A layering process can now be performed to process the pretreated single crystal P-germanium and N+ layers on top of the pretreated wafer or layer 808. The pre-processed wafer or layer 808 can be bonded using oxide deposition and/or surface treatment. It is generally foreseen that the above methods are only for reference, and other cases and applications may be derived based on the principles of the invention, and the scope of the invention is not limited by the appended claims.

22A-22H are schematic views showing the formation of an upper planar source extended transistor. Figure 22A shows the pre-processed wafer or the 808 layer upper cut-out layer. After smart cutting, N+2104 is on the surface. The surface transistor source 22B04 and the drain 22B06 are formed by etching away the N+ of the designated region of the gate 22B02, leaving a thin layer of a more finely doped N+ layer as an extension of the subsequent source and drain, and the transistor. 22B08 isolation layer. With an additional mask layer, isolation regions 22B) 8 are obtained by etching to the surface of the pretreated wafer or layer 808 to form isolation between the transistor or group of transistors. Etching the N+ layer between the transistors facilitates conduction of the N+ layer. This step is aligned with the surface of the preprocessed wafer or layer 808 such that the formed transistor can form a good bond with the pretreated wafer or the 808 layer metal layer. Then, a highly equivalent low temperature oxide 22C02 (or oxide/nitrogen stack) is obtained by deposition and etching to form the structure shown in Fig. 22C. Figure 22D shows the structure after the self-aligned etch preparation step, which is used to process the gate 22D02 and then form the source and drain extensions 22D04. Figure 22E shows the structure obtained after the low-temperature microwave oxidation technology, which may be a TEL SPA (Slotted Planar Antenna of Toyota Electronics Co., Ltd.) oxygen radical plasma, thereby growing or accumulating a low temperature gate insulator 22E02 for use as a MOSFET. The gate oxide, or an atomic layer deposition (ALD) technique, can also be used. In addition, the gate structure can also be obtained using the following high K-metal gate process. After an industry standard HF/SC1/SC2 cleaning, an atomically smooth surface is formed and a high k insulating layer 22E02 is deposited. The semiconductor industry has chosen Hafnium-based insulation as the material of choice for replacing SiO2 and niobium oxynitride. Hafnium base insulators contain hafnium oxide and hafnium niobate/hafnium niobium oxide. Hafnium oxide, HfO2, has an insulation constant of about 2 times that of hafnium niobate/hafnium niobium oxide. (HfSiO/HfSiON k~15) The choice of metal is the key to the normal operation of the component. Instead of the N+ polymer metal used as the electrode for the gate, a working 阙 value of approximately 4.2 eV is required to ensure proper operation of the component at normal 阙 voltage. In addition, instead of the P+ polymer metal used as the electrode of the gate, approximately 5.2 eV of work function is required to ensure proper operation. A family of TiAl and TiAlN based metals can be used to increase the metal work function from 4.2 eV to 5.2 eV.

Figure 22F shows the metal gate 22F02 after deposition, grinding and etching. In addition, in order to improve the performance of the transistor, a target pressure layer can be used to induce higher channel stress. A tensile nitride layer can be deposited at a low temperature to increase the channel stress of the NMOS device of FIG. The PMOS transistor can be constructed through the above process, only need to change the initial P-wafer or the outer edge of the 2104N+ layer to form the P-, which is the N-wafer on the N-wafer or P+ outer edge layer; and the N+ Layer 2104 is changed to a P+ layer. Then, after the metal gate is formed, a compressive stress nitride film can be deposited to improve the performance of the PMOS transistor.

A thick oxide layer 22G02 is eventually deposited and the opening of the contact is processed using a mask and etch to prepare for connection to the transistor, as shown in Figure 22G. The thicker oxide or low temperature oxide in this document can be processed by chemical vapor deposition (CVD), vapor deposition in the house (PVD) or plasma enhanced chemical vapor deposition (PECVD). The process is capable of forming a single-crystal surface MOS transistor that can be connected to the underlying multi-metal layer semiconductor component without the need to expose the underlying components and interconnecting circuit metal to high temperatures. These transistors can be used as a stor-resistant memory programming transistor for layer 807, connected to a pre-processed wafer or layer 808 to form a monolithic 3D circuit stack, or as a function of a 3D integrated circuit. These transistors can be considered as "planar MOSFET transistors", ie the current in the transistor channel is always in the horizontal direction. The above transistor, including other transistors in this file, can be a horizontal transistor, a horizontal direction, or a lateral transistor. Another advantage of this process is that the smart cutting of H+, or other atomic doping steps, is done before the MOS transistor gate is formed, avoiding damage to the gate function. If desired, the surface of the pre-processed wafer or layer 808 may include a "back gate" 22F02-1, which may be aligned directly from the top with the back gate 22F02-1, as shown in Figure 22H. The back gate 22F02-1 can be processed from the surface metal layer of the pre-processed wafer or the 808 layer, or the oxide layer can be deposited on the surface of the metal layer to bond the wafer (wafer not shown) as the back gate. The gate oxide of the pole.

In accordance with some of the cases of the present invention, in the normal manufacturing process of the component layers, as shown in Fig. 8, each new layer must be aligned with the next layer using the previously processed alignment marks. Sometimes, the alignment of one layer can be used to align multiple layers above, and sometimes a new layer must also have alignment marks for alignment with other layers above in subsequent manufacturing steps. Therefore layer 804 must be aligned with layer 802, layer 806 must be aligned with layer 804, and so on. Another advantage of the above process is that the cut-out layer can be made sufficiently thin, and in the subsequent drawing step (as depicted in Figure 22B), the cut-out layer can be aligned with the alignment mark of the pre-processed wafer or layer 808. The 3D IC can also be fabricated by aligning with any of the following layers, such as 806, 804, 802, or other layers. Therefore, the "back gate" 22F02-1, which is part of the pre-processed wafer or the surface metal layer of the 808 layer, can accurately align 22F02 from below because the marks of all layers are aligned layer by layer. In this paper, the accuracy of the alignment is largely dependent on the device being marked. For 45nm and below processes, the accuracy of overlay alignment is typically less than 5nm. Alignment requirements will increase with scaling up, and modern stepper motors can be more accurate than 2nm. The smaller order of alignment requirements can be implemented in TSVs based on 3D IC systems, as shown in Figure 12 and below, it is very difficult to achieve overlay alignment accuracy of 0.5 microns. The connection between the surface gate and the back gate can be achieved through surface vias or TLVs. This can further reduce the leakage current of the gate 22F02 and the back gate 22F02-1, and both gates can be connected to better cut off the transistor 22G20. At the same time, by dynamically changing the threshold voltage of the surface gate transistor - by independently changing the bias voltage of the back gate 22F02-1 - a sleep mode, a normal sleep mode, and a fast sleep mode can also be set. In addition, through the above process to build an accumulation mode (full depletion) MOSFET transistor, only need to change the initial P-wafer 2102, or form the outer edge of the 2104N+ layer P-2106, become N-wafer or N+ N-wafer on the edge layer.

Another factor in the production of surface transistors using this technique is the size of the vias or TLVs used to connect the surface transistor 22G20 to the metal layer of the preprocessed wafer and the lower 808 layer. A generally reliable empirical method is that the size of the via is greater than 1/10 of the thickness of the layer being penetrated. Since the layer thickness of the structure is typically greater than 50 microns as shown in Figure 12, the TSV of the structure is typically greater than 10 microns. The thickness of the cut-out layer in FIG. 22A is less than 100 nm, so the via size of the corresponding connection between the surface transistor 22G20 to the underlying pre-processed wafer and the 808 layer should be less than 50 nm. As the process is reduced, the thickness of the cut-out layer and the size of the vias corresponding to the underlying structure can also be reduced. For some advanced processes, the thickness of the cut-out layer can be less than 10 nm.

Another source and drain extended planar surface transistor forming scheme is to process the processed wafer of Figure 21B, as shown in Figures 29A-29G. Figure 29A shows the pre-processed wafer or the 808 layer upper cut-out layer. After smart cutting, N+2104, P-2106, and P+2108 are on the surface. The oxide layer of the auxiliary adhesion crystal circle is not shown. The contact opening of the substrate P+ source 29B04 and the transistor isolation 29B02 are masked and etched as shown in FIG. 29B. With an additional mask layer, isolation region 29B02 is obtained by etching to the pretreated wafer or 808 layer surface to form isolation between the transistor or group of transistors, as shown in Figure 29C. Etching the P+ layer between the transistors facilitates conduction of the P+ layer. The low temperature oxide 29C04 is then deposited and polished using a chemical mechanical process. Then, a thin sanding stop layer 29C06, which may be deposited by low temperature tantalum nitride, forms a structure as shown in Fig. 29C. The source 29D02, the drain 29D04, and the self-aligned gate 29D06 can be obtained by masking and etching on the thin sanding stop layer 29C06, followed by N+ bevel etching, as shown in FIG. 29D. The bevel (30-90 degrees, 45 degrees) etching or double bevel etching can be achieved using wet chemical or plasma etching techniques. This process can form an angled source and drain extension 29D08. As shown in FIG. 29E, the deposition and densification of the subsequent low temperature gate insulator 29E02, or the deposition and densification of the low temperature microwave plasma tantalum surface oxide, or atomic layer deposition (ALD) gate insulator, may be used. The MOSFET gate oxide is then deposited as a gate material 29E04, such as aluminum or tungsten.

In addition, a high-k metal gate structure can also be obtained using the following procedure. After an industry standard HF/SC1/SC2 cleaning, an atomically smooth surface is formed and a high k insulating layer 29E02 is deposited. The semiconductor industry has chosen Hafnium-based insulation as the material of choice for replacing SiO2 and niobium oxynitride. Hafnium base insulators contain hafnium oxide and hafnium niobate/hafnium niobium oxide. Hafnium oxide, HfO2, has an insulation constant of about 2 times that of hafnium niobate/hafnium niobium oxide. (HfSiO/HfSiON k~15) The choice of metal is the key to the normal operation of the component. Instead of the N+ polymer metal used as the electrode for the gate, a working 阙 value of approximately 4.2 eV is required to ensure proper operation of the component at normal 阙 voltage. In addition, instead of the P+ polymer metal used as the electrode of the gate, a work enthalpy of approximately 5.2 eV is required to ensure proper operation. A family of TiAl and TiAlN based metals can be used to increase the metal work function from 4.2 eV to 5.2 eV.

As shown in Fig. 29F, after the metal gate 29E04 is polished by chemical mechanical polishing, the structure obtained by the stop layer 29C06 is polished. The PMOS transistor can be constructed through the above process, only need to change the initial P-wafer or the outer edge of the 2104N+ layer to form the P-, which is the N-wafer on the N-wafer or P+ outer edge layer; and the N+ Layer 2104 is changed to a P+ layer. Similarly, if P+ is changed to N+, layer 2108 will also change if the substrate contacts are used.

A thick oxide layer 29G02 is finally deposited and the opening of the contact is processed using a mask and etch to prepare for connection to the transistor, as shown in Figure 29G. The figure also shows that the layer cut via 29G04, after masking and etching, provides a connection for the surface transistor line to the bottom layer 808 interconnect circuit 29G06. The process is capable of forming a single-crystal surface MOS transistor that can be connected to the underlying multi-metal layer semiconductor component without the need to expose the underlying components and interconnecting circuit metal to high temperatures. These transistors can be used as a stor-resistant memory programming transistor for layer 807, connected to a pre-processed wafer or layer 808 to form a monolithic 3D IC, or as a further function of a 3D integrated circuit. These transistors can be used as planar germanium OSFET transistors, ie the current in the transistor channel is horizontal. The above transistor, including other transistors in this file, can be a horizontal transistor, a horizontal direction, or a lateral transistor. Another advantage of this process is that the smart cutting of H+, or other atomic doping steps, is done before the MOS transistor gate is formed, avoiding damage to the gate function. In addition, through the above process to build an accumulation mode (full depletion) MOSFET transistor, just change the initial P-wafer, or form the outer edge of the 2104N+ layer P- into N-wafer or N+ rim N-wafer on the layer. Alternatively, a back gate similar to that of Figure 22H can be used.

Another method is to perform a layer cut using a preprocessed wafer, as shown in FIG. FIG. 23A is a schematic diagram of layer cutting using a pre-processed crystal; N-wafer 2302 can process a buried layer N+2304, which is realized by doping and opening, and can also pass through a shallow N+ doping after N-gravitation growth. Miscellaneous and diffusion implementation. Figure 23B shows a pre-processed wafer that can be used for layer cutting after deposition or oxide 2308 growth. After doping with atoms, such as H+, a smart cut cut plane 2306 can be prepared below the N+ region. A layering process can now be performed to process the pretreated single crystal N-germanium and N+ layers on top of the pretreated wafer or layer 808.

24A-24F are schematic diagrams of upper junction gate field effect (JFET) planar transistor formation. Figure 24A shows the structure formed by the pre-processed wafer or the upper portion of the 808 layer after layer-cutting. Therefore, after the wisdom cut, N+ 2304 appears on the surface and is now labeled 24A04. Surface transistor source 24B04 and drain 24B06 pass through an isolation layer between gate 24B02 and transistor 22B08. N+ etching of the designated area is formed. This step is aligned with the surface of the pre-processed wafer or layer 808 such that the formed transistor can form a good connection with the pre-processed wafer or underlying layers of the 808 layer. An additional masking and etching step is then performed to remove the N-layer between the transistors, as shown in Figure 24C02, thereby resulting in a better transistor isolation layer as shown in Figure 24C. Figure 24D is an alternative method of forming a P+ region 24D02 for processing a JFET gate. In this method, it may be necessary to use a laser or other optical slow cooling method to turn on P+. Figure 24E shows how laser annealing is performed on the pre-processed wafer or the upper portion of the 808 layer to reduce heat transfer. After the thick oxide is deposited 24E02, a layer of aluminum 24D04 or other reflective material will be added to the reflective layer. After the mask 24D08 of the reflective layer is masked and etched, the laser 24D06 is capable of annealing the P+ 24D02 doped region and reflecting most of the laser energy 24D06 from the pretreated wafer or layer 808. Typically, the area of the open area 24D08 is less than 10% of the entire wafer area. In addition, a layer of copper 24D10, or a layer of reflectivity, or other reflective material, can be processed onto the pre-processed wafer or layer 808, allowing the unwanted laser energy 24D06 to be reflected without passing heat to the pre-heat Process the wafer or layer 808. Layer 24D10 can also function as a ground plane or a conductive back gate when the molding assembly and circuitry are operating. Of course, layer 24D10 can also be machined to create a via that subsequently connects the second surface cut-out layer and the pre-processed wafer or 808 layer. The same reflective laser annealing or other optical annealing technique can be used to anneal any of the above structures such that the gate of the transistor can be doped open during the second layer cut-out process. Additionally, oil absorbing materials, and/or other luminescent materials, can be used in the laser or other optical annealing methods described above. As shown in Fig. 24E-1, the light absorbing layer 24E04, which may be amorphous carbon, may be deposited or sprayed at a low temperature to a region where laser annealing is required, and then masked and etched accordingly. In this way, the laser or other optical energy can be used to effectively anneal the area, turn on the dopant material, and minimize the thermal stress of the reflective layer 24D04 & 24D10, the preprocessed wafer or the 808 layer. Laser annealing can be used on the entire wafer surface or in the area where the gate circuit is located to further reduce total heat and ensure no damage to the underlying layer.

The structure shown in Fig. 24F is obtained after the following processing procedure. The laser reflective layer 24D04 is etched, deposited, masked, etched with a thick oxide layer 24F04 to obtain open contacts 24F06 and 24F02, deposited and partially etched (or chemically polished). (CMP)) Aluminum (or other metal, a Schottky or Ohmic contact at 24F02) forms a 24F06 contact and a gate 24F02. If necessary, the N+ contact 24F06 and the gate contact 24F02 can be separately masked and etched so that different metals can be deposited thereon to obtain Schottky or Ohmic contacts on the gate 24F02, at the N+ contact 24F06. Get ohmic connection on. The thick oxide layer 24F04 is a non-conductive insulating material that is also filled into the etched spaces 24B08 and 24B09 between the surface transistors, and other isolation materials such as tantalum nitride may be used. The surface transistor is finally surrounded by an isolating insulating material. Unlike conventional monolithic integrated circuit transistors, conventional transistors are processed on a single crystal germanium wafer surrounded by a non-conductive insulating material. The process is capable of forming a single-crystal surface JFET transistor that can be connected to the underlying multi-metal layer semiconductor component without the need to expose the underlying component to high temperatures.

In another aspect of the above process, a transistor technology-pseudo MOSFET can be used, but with a molecular layer that is covalently bonded to the channel region between the drain and the source. This process can be carried out at relatively low temperatures (below 400 degrees Celsius).

Another method is to use a pre-processed wafer for layer cutting, as shown in Figure 25. FIG. 25A is a schematic diagram of layer cutting using a pre-processed crystal; N-wafer 2502 can process a buried layer N+2304, which is realized by doping and opening, and can also pass through a shallow N+ after N-gravitation growth 2508. Doping and diffusion are achieved. The surface is additionally machined with a P+ layer 2510. The P+ layer 2510 can be processed again using doping and opening, or P+ grazing growth. Figure 25B shows a pre-processed wafer that can be used for layer cutting after deposition or oxide 2512 growth. After doping atoms, such as H+, a smart cut-out plane 2506 can be prepared below the N+ region 2504. . A layering process can now be performed to process the pretreated single crystal germanium, doped with a layer of N- and N+, which layer is over the pretreated wafer or layer 808.

26A-24E are schematic views of the formation of an upper junction gate field effect (JFET) planar transistor (with reverse bias gate or double gate). Figure 26A is a pre-processed wafer or a cut-out layer on the upper portion of the 808 layer. After smart cutting, N+ 2504 is on the surface. Surface transistor source 26B04 and drain 26B06 pass through an isolation layer between gate 26B02 and transistor 26B08. N+ etching of the designated area is formed. This step is aligned with the surface of the pre-processed wafer or layer 808 such that the formed transistor can form a good connection with the pre-processed wafer or underlying layers of the 808 layer. Thereafter, N- between the transistors 26C12 is removed by masking and etching to make contact with the buried P+ layer 2510. Another masking and etching step is then performed to remove the P+ layer 2510 between the transistors, thereby resulting in complete isolation as shown in Figure 26C. Figure 26D is an alternative molding method for the shallow P+ region 26D02 for constructing the gate. In this method, it may be necessary to use laser annealing to turn on P+. The structure shown in Fig. 26E is obtained by the following steps: deposition and etching/CMP of thick oxide layer 26E04, deposition and etch back of aluminum (or other metal, obtaining the best Schottky or ohmic contact at 26E02), Points 26E06, 26E12 and gate 26E02. If necessary, the N+ contact 26E06 and the gate contact 26E02 can be separately masked and etched such that different metals can be deposited thereon to obtain Schottky or Ohmic contacts on the gate 26E02, at the N+ contact 26E06 & ohmic connection on 26E12. The thick oxide layer 26E04 is a non-conductive insulating material that is also filled into the etched spaces 26B08 and 26B09 between the surface transistors, and other isolation materials such as tantalum nitride may be used. Contact 26E12 allows the addition of a transistor back gate or can be coupled to gate 26E02 to form a dual gate JFET. Alternatively, the back gate connection can be included in the pre-processed wafer or layer 808 to connect the layer 2510 from below. The process is capable of forming a single-crystal surface ultra-thin JFET transistor with a back gate or dual gate function that can be connected to the underlying multi-metal layer semiconductor component without the need to expose the underlying component to high temperatures.

Another method is to perform a layer cut using a preprocessed wafer, as shown in FIG. 27A is a schematic diagram of layer cutting using a pre-processed crystal; an N+ wafer 2702 has a buried layer after processing, which is realized by ion implantation and open annealing, and can also construct a vertical structure by diffusion to build an NPN block thereon (or PNP block) bipolar transistor. The layer of the grown crystal can be used to construct a doped multilayer structure. Starting from layer P 2704, then N-layer 2708, and finally N+ layer 2710, the layer is finally opened by annealing to a higher on temperature. Figure 27B shows a pre-processed wafer that can be used for layer cutting after deposition or oxide 2712 growth. After doping with atoms, such as H+, the plane 2706 can be cut in the N+ region for intelligent cutting. A layering process can now be performed to process the pretreatment layer, which is located over the preprocessed wafer or layer 808.

28A-E are schematic views of the formation of a surface bipolar transistor. Figure 28A shows the pre-processed wafer or the 808 layer upper cut-out layer. After smart cutting, N+28A02 (one part of 2702) is on the surface. Usually at this point, there is a giant transistor covering the entire wafer. The following are a number of etching steps, as shown in Figures 28B-28D, where the giant transistor is diced and, if desired, aligned with the underlying pre-processed wafer or layer 808. The etching step also exposes different layers including the bipolar transistor, achieving contact of the emitter 2806, the base 2802, and the collector 2808, and then etching to the surface oxide layer of the preprocessed wafer or the 808 layer, as shown in FIG. 28D The transistor is isolated. The surface layer N+ doped layer 28A02 can be masked and etched as shown in FIG. 28B to form an emitter 2806. Then, the P 2704 and N-2706 doped layers may be masked and etched as shown in FIG. 28C to form a base 2802. Subsequently, the collector layer 2710 is masked and etched until the wafer or 808 layer of surface oxide layer is pretreated to achieve the transistor isolation 2809 of FIG. 28D. All of the structure can be covered with a low temperature oxide 2804, the oxide is planarized using CMP, and then masked and etched to effect contact of the emitter 2806, base 2802, and collector 2808 shown in Figure 28E. The thick oxide layer 2804 is a non-conductive insulating material that fills the etched voids 2809 between the surface transistors and other isolation materials such as tantalum nitride can be used. The process is capable of forming a single-crystal surface bipolar transistor that can be connected to the underlying multi-metal layer semiconductor component without the need to expose the underlying component to high temperatures.

The bipolar transistor obtained in Figures 27 and 28 can be used to form an analog or digital BiCMOS circuit, the CMOS transistor is located on the substrate primary layer 802 and the preprocessed wafer or 808 layer, and the bipolar transistor can be arranged in the cut out The surface layer.

Another type of component can be constructed at a high temperature before layer cutting to a substrate with a metal interconnect circuit, and then completed at a low temperature after layer cutting to a junctionless transistor (JLT). For example, in the sub-micron process, copper sputtering is used, so that temperatures above about 400 degrees Celsius can be achieved, and temperatures below 400 degrees Celsius and below. The structure of the junctionless transistor avoids the sharply layered junctions required for 矽 technology shrinkage and enables the construction of thicker gate oxide layers with comparable performance to conventional MOSFET transistors. Non-junction transistors are also known as junctionless nanowire transistors, or gate-selective resistors, or nanowire transistors, see Nature, February 21, 2010, by Jean-Pierre Colinge et al. When constructing a junctionless transistor, the transistor channel can be a thin solid piece of uniformly doped single crystal germanium. The doping concentration of the channel can be the same as the source and drain. It is important to consider that the nanowire channel must be sufficiently thin and narrow enough that the carrier can be fully utilized when the component is turned off, and the doping of the channel must be sufficiently high to produce the desired current when the component is turned on. These considerations may result in little room for process variation, limiting the channel thickness, width, doping concentration required for the gate to achieve work function, and gate oxide thickness.

One of the challenges of the junctionless transistor assembly is that the leakage of the closed channel is minimized when the gate bias is zero. In order to improve the control of the gate to the transistor channel, the channel can be non-uniformly doped, the highest concentration doping is closest to the gate, and the channel doping is lighter than the gate electrode. For example, the middle of the junctionless transistor channel of 2, 3, or 4 gates is lighter than the edge doping concentration. This is the leakage current of the gate's work function is low, and control is achieved. As shown in FIGS. 52A and 52B, the current I of the drain to analog source is simulated as a function of the gate voltage V under logarithmic and linear scaling, respectively, to indicate the doping of different junctionless transistor channels, wherein The total thickness of the n-channel is 20 nm. Of the 4 plug strip curves for each pattern, 2 correspond to uniformly doped 20 nm channels to 1E17 and 1E18 atoms/cm3 concentrations. The analogy of the remaining 2 plug strip curves shows that the 20 nm channel consists of two layers of 10 nm thick doped layers. In the legendary explanation of the remaining 2 strip curves, the first number corresponds to the portion of the 10 nm layer closest to the gate electrode. For example, the curve D=1I18/1I17 indicates that the simulation result is that the 10 nm channel doping concentration is in the portion of 1E18, which is closest to the gate electrode, and in the 10 nm channel, the doping is 1E17 concentration is separated from the gate electrode. In Fig. 52A, curves 5202 and 5204 correspond to D = 1I18 / 1E17 of the doping pattern, respectively. According to Fig. 52A, at V = 0v, the doping region, the drain current of D = 1E18 / 1E17 is much 50 times lower than the opposite doping region D = 1E17 / 1E18. Similarly, in Figure 52B, curves 5206 and 5208 correspond to D = 1I18 / 1E17 of the doping pattern, respectively. In Fig. 52B, when V = 1 v, the I of the two doped regions differ by only a few percentage points.

The doping of the junctionless transistor channel can be performed uniformly, layered, or performed in a spacer. The transistor channel may also be unsuitable for doped monocrystalline germanium construction, such as polysilicon, other semiconductor, insulating, or conductive materials, such as graphite or other graphite materials, or a combination of materials similar or different from other layers. For example, the center of the channel may comprise a layer of oxide, or a lightly doped germanium, and the edge may be a heavily doped single crystal germanium. In this way, the control effect of the gate of the resistor in the power-off state can be improved, and the path current can be increased due to the strain effect of other layers in the channel. Strain technology can also be used to cover and insulate the upper and lower layers of the material, as well as the surrounding transistor channels and gates. Lattice modification can also be used to stretch germanium, such as embedded SiGe doping and annealing. The interface of the transistor channel can be rectangular, prototype, or elliptical in order to improve gate-to-channel control. In addition, in order to achieve the best behavior of the P-channel junctionless transistor in the 3D layer cutting process, the donor wafer can be rotated 90 degrees with respect to the acceptor wafer before bonding, to facilitate <110> The formation of a P-channel in the plane of the crucible.

In order to build an n-type 4-sided gate-controlled junctionless transistor, the germanium wafer needs to be pretreated and then layer cut as shown in Figures 56A-56G. These processes may need to be performed under plug conditions above 400 degrees Celsius because the layer is not yet cut to the substrate with the metal interconnect circuit. As shown in FIG. 56A, the N-wafer can process a layer of N+ 5604A, which is achieved by doping and opening, can also be grown by N+ crystallization, or by forming a deposited layer of heavily N+ doped polysilicon. Gate oxide 5602A can be grown before or after doping to a thickness of about one-half the thickness of the desired final surface gate oxide. Figure 56B is a pre-processed wafer that can be used for layer cutting. After doping atoms 5606, such as H+, the plane 5608 can be prepared in the N-region 5600A of the substrate and then processed by plasma or other surface treatment. The oxide surface of the wafer oxide layer is bonded to the oxide. The other wafer was processed as above, but was not doped with H+, and then as shown in Fig. 56C, the two wafers were bonded for layer-cutting of the pretreated single crystal germanium N- and N+ layers and the half gate. The oxide layer, similarly pretreated, but the undoped N-wafer 5600 and N+ layer 5604 and oxide layer 5602 are cut out. The surface wafer is layer cut and separated from the underlying wafer. In this way, the surface wafer can also be used to process and rework more layers to build the resistive layer. The remaining surface wafer N- and N+ layers were mechanically polished until a very thin N+ twinned layer 5610 was obtained, as shown in Figure 56D. The thin N+ doped twin layer 5610 has a thickness between 5 and 40 nm and ultimately constitutes a resistor having a gate control in four directions. Two "semi-" gate oxide layers 5602, 5602A, which can now be bonded together, form a gate oxide layer 5612 which is ultimately processed into a surface gate oxide layer of a junctionless transistor, as shown in Figure 56E. High temperature annealing can be used to remove residual oxide or surface charge.

Alternatively, the bottom wafer of Figure 56C will be constructed, N+ layer 5604 can be used to build heavily doped polysilicon, and half gate oxide layer 5602 can be deposited or grown prior to layer cutting. The bottom wafer N+ twinned or polycrystalline layer 5604 will eventually become the gate of the junctionless transistor.

As shown in Figures 56E-56G, the wafer is conventionally processed at a temperature above 400 degrees Celsius to produce a processed "shell" wafer 808 that can be layered into a junctionless transistor structure. A thin layer of oxide can be grown to protect the surface of the thin resistive layer 5610, and then a parallel conductor 5614 having a repeating pitch on the thin resistive layer can be masked, as shown in FIG. 56E, and then lithographically cleaned. gum. The thin oxide layer, if any, can be removed in a dilute hydrofluoric acid (HF) solution, and then a conventional oxide layer 5616 and a polysilicon layer 5618 can be grown, either doped or undoped, as shown in the figure. 56F is shown. The polycrystalline germanium is chemically and mechanically polished (CMP) flattened and a thin oxide layer 5620 is grown or deposited for subsequent low temperature oxide-oxide wafer bonding. Polysilicon 5618 can be additionally doped before or after CMP. The polysilicon is finally processed into the bottom and side gates of the junctionless transistor. Figure 56G is a pre-processed wafer that can be used for layer cutting. After doping atom 5606, such as H+, a "cut-out plane" 5608G can be prepared in the N-region 5600 of the substrate, and then subjected to plasma or other surface treatment. The oxide surface of the wafer oxide layer is formed for oxide bonding. The acceptor wafer 808 has a logic transistor and a metal interconnect circuit. After pretreatment, it can be used for low temperature oxide-oxide wafer bonding and surface oxide surface treatment, as shown in Figure 56H. After the surface donor wafer is layered, it is separated from the lower acceptor wafer 808, and the surface N-substrate is removed by CMP. The metal wiring strip 5622 in the outer casing 808 is as shown in Fig. 56H.

Figure 56I is a top view of the wafer, the same as step 56H, and with two cross-sectional views I and II. N+ layer 5604, which ultimately constitutes the top gate of the resistor, and top gate oxide layer 5612 will control one side of resistor line 5614, bottom and side gate oxide layer 5616 and poly layer bottom and side gate 5618 control resistors 5614 other three Side. Logic device housing wafer 808 has an upper oxide layer 5624 that wraps top metal wiring strips 5622 as shown by the outer dashed lines in the top view.

In FIG. 56J, the sanding stop layer 5626 can be deposited on the surface of the wafer using a material such as oxide or tantalum nitride, and the isolation opening 5628 is masked and etched to the depth of the oxide layer 5624 of the outer casing 808 to enable complete Isolate the transistor. Isolation opening 5628 is completely filled with low temperature oxide and then polished by chemical and mechanical polishing (CMP). The mask and etch of top gate 5630 is shown in Figure 56K, and then etch opening 5629 is filled using a low temperature fill oxide deposition, chemically and mechanically (CMP) polished, and then another layer of oxide is deposited to achieve the wiring metal. Layer isolation.

The mask and etch of the contacts are shown in Figure 56L. The gate contact 5632 is masked and etched such that the contact is etched through the top gate layer 5630. During the metal layer opening mask and etching process, the gate oxide is also etched such that the top gate 5630 and the bottom 5618 The gates are connected. The contacts 5634 connecting the two electrodes of the resistive layer 5614 are also masked and etched. Then, mask etching is performed to the via wafer 808 and the via via 5636 of the metal wiring strip 5622.

As shown in FIG. 56M, the metal line 5640 is defined by a mask and etched, filled with a barrier metal and copper interconnect circuit, processed through a CMP and conventional metal interconnect circuit scheme to complete the contact via 5632 and the surface layer 5630 and the bottom 5618 gate. At the same time, the connection of the two electrodes 5634 of the resistor 5614 and the connection of the metal interconnect circuit strip 5622 of the outer casing wafer 808 are connected. The process is capable of forming a single crystal 4-sided gate junctionless transistor that can be connected to the underlying multi-metal layer semiconductor component without the need to expose the underlying component to high temperatures.

In addition, as shown in Figures 96A-96J, an N-channel 4-sided gate-controlled junctionless transistor (JLT) can be built in the corresponding 3D IC fabrication process. The 4-sided gate control JL can also be a full gate controlled JLT, or a germanium nanowire JLT.

As shown in FIG. 96A, a P- or N-substrate donor wafer 9600 can be fabricated into N+ doped twin layers 9602 and 9606 including wafer dimensions, and N+SiGe9604 and 9608 layers of wafer size. Layers 9602, 9604, 9608 can be grown by crystallization and then carefully processed in accordance with thickness and stoichiometry to maintain defect density due to lattice mismatch between Si and underlying SiGe. The stoichiometry of SiGe may result in different etch rates due to different layers, as detailed below. Techniques for partially achieving different etch rates include: Maintaining a thickness of the SiGe layer below a critical thickness that forms a defect. The surface of the donor wafer 9600 can be deposited by an oxide layer 9613 so that oxide wafer bonding can be performed. These processes may need to be performed under plug conditions above 400 degrees Celsius because the layer is not yet cut to the substrate with the metal interconnect circuit. A wafer-sized layer can provide a continuous layer of material or combination of materials across the entire wafer up to the edge of the wafer and possibly have approximately uniform thickness. If the wafer size layer contains dopants, the doping concentration will generally remain the same in x and y directions, but may differ in the z-direction (vertical wafer surface).

As shown in Fig. 96B, the layer cut plane 9699 (shown in phantom) may be implemented on the donor wafer 9600 by doping or other methods as previously described.

As shown in FIG. 96C, both the donor wafer 9600 and the surface of the acceptor wafer 9610 can be processed for wafer bonding, and then the donor wafer 9600 is inverted and aligned with the acceptor wafer 9610 (not shown). ) Align and then bond at low temperatures (approximately below 400 degrees Celsius). The donor wafer and the oxide layer 9613 on the surface of the acceptor wafer 9610 are then atomically bonded as shown in Figure 9614.

As shown in Figure 96D, a portion of the P-donor wafer substrate 9600, which is over the layer-cut plane 9699, can be removed by dicing and sanding, etching, or other low temperature methods as previously described. The CMP process can be used to remove the remaining P-layer until the N+ twin layer 9602 is reached. The process of ion-implanting atoms, such as helium, is then used to form a layer-cutting plane, which is then cut or thinned, or may be referred to as "ion-cutting." The acceptor wafer 9610 can also be processed using a method similar to wafer 808, and the processing of wafer 808 is illustrated in FIG.

As shown in Fig. 96E, the N+ germanium stack and the N+SiGe layer can be processed into a transistor or a channel, and then the gate portion can pass through the printed scribe line and the N+ germanium layer 9602 & 9606 and the N+SiGe layer 9604 & 9608 plasma/RIE. Obtained by etching. As a result, a N+SiGe9616 stack and an N+矽9618 layer can be obtained. The separation between the stacks can be completely filled with low temperature filled oxide 9620 and then polished by chemical physical polishing (CMP). This completely separates the individual transistors. The ends of the pile are drawn in the figure for understanding.

As shown in Figure 96F, the final clustered or common gate portion 9630 can be obtained using printed scribe lines and oxide etch. This exposes the sides of the transistor channel and the gate region stack, consisting of alternating N+矽9618 and N+SiGe9616 layers, ultimately forming a group or common gate region 9630. The ends of the pile are drawn in the figure for understanding.

As shown in FIG. 96G, the exposed N+SiGe layer 9616 can be removed by a selective etch recipe without damaging the N+ germanium layer 9618. Thus, a voided N+ germanium region 9618 is formed in the final cluster or common gate region 9630. The above etching recipe is in "High Temperature 5 nm Radial Double-Nano Nanowire MOSFET (TSNWFET): Manufacturing, Characterization and Dependence on Si Wafer Stack", Proc. IEDM Tech, SDSuk et al., 717-720, 2005 Published in the year. The N+SiGe layer furthest from the top edge can be constructed stoichiometrically such that the layer (region) (eg, N+SiGe layer 9608) achieves a slightly faster etch rate relative to other layers closer to the top (eg, N+SiGe layer 9604), and can make the gate lengths of the final two stack transistors the same. The ends of the pile are drawn in the figure for understanding.

As shown in Figure 96H, there is an optional step to reduce surface weedness, round the edges, and thin the diameter of the N+ twinned region 9618, which is exposed in the cluster or common gate region and oxidized using low temperature. Then, the oxide layer is removed by HF etching. This step can be repeated multiple times. For exposed N+ twinned surfaces, helium may also be added during the oxidation process or by plasma treatment. This results in a rounded nanowire structure that forms the final transistor gated channel 9636. The ends of the pile are drawn in the figure for understanding.

As shown in FIG. 96I, a low temperature based gate insulator can be deposited and encrypted for use as a gate oxide of a junctionless transistor. Alternatively, the twinned surface of the gate-controlled channel 9636 of the final transistor can be treated using low temperature microwave ion beam oxidation to form the HKMG gate oxide as a JLT gate oxide or using atomic layer deposition (ALD) techniques. It is also possible to deposit a low temperature gate material 9612, such as a P+ doped amorphous crucible. In addition, a high-k metal gate structure can also be obtained using the following procedure. A CMP process is performed on the deposition of the gate material. The ends of the pile are drawn in the figure for understanding.

Figure 96J shows a complete JLT transistor stack formed in Figure 96I. For clarity, the oxide layer is not shown, and the cross-sectional cut I in Figure 96I is also included. The gate 9612 surrounds the transistor gated channel 9636, and each group of transistor turns are isolated from the other stack by the oxide 9622. The source and drain connections of the transistor stack can be moved to the N+矽9618 and N+SiGe9616 regions, which are not covered by the gate 9612.

The contacts with the four-sided gate-controlled JLT source, drain and gate can be processed using conventional back-end processing (BEOL), and the connection between the formed JLT and the acceptor wafer can be connected to the via via via (TLV). The main wafer is interconnected on the metal pad. The process is capable of forming a single crystal germanium channel 4-sided gate junctionless transistor that can be connected to the underlying multi-metal layer semiconductor component without the need to expose the lower component to high temperatures.

The P-channel 4-plane gate-controlled JLT can be constructed using the above-described N+ germanium layers 9602 and 9608 as P+ doping materials, and the work function of the gate metal 9612 can turn off the P-channel correspondingly when the gate voltage is zero.

The process flow is shown in Figure 96A-J. The key steps include the formation of 4-sided grid-controlled JLT and 3D stack components. It is not difficult for the industry's senior staff to imagine that the process can be improved on this basis. For example, steps and additional materials/areas can be added to increase the stress on the JLT. Alternatively, the N+SiGe layers 9604 and 9608 can comprise P+SiGe or undoped SiGe, as well as a selective abrasive solution formulation. Additionally, more than two layers of wafers or circuits can be added to the 3D stack. At the same time, a variety of methods can be used to construct the germanium nanowire transistor. The above is described in pages 1-4 and 7-9 of "High Performance and High Consistency Full Gate Control Nanowire MOSFETs and Scale Down", the book "Electronic Component Conference (IEDM)" 2009 Year, IEEE, written by Bangsaruntip.S, GM; Majundar.A, et al., December 2009. (High-performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire scale dependent scaling) ("Bangsaruntip") and the above-mentioned high-performance _5nm radius double-twisted nanowire MOSFET (TSNWFET): on the Si wafer stack Manufacturing, characterization and dependence, published by D. Suk, S.-Y. Lee, S.-M. Kim, ("Suk"), etc., Proc. IEDM Tech, 717-720, published in 2005. The above disclosure is incorporated herein by reference. The techniques of the above disclosure can be used to fabricate a four-sided gated JLT.

In addition, as shown in Figures 57A-57G, an N-channel 3-sided gate-controlled junctionless transistor (JLT) can be built in the corresponding 3D IC fabrication process. As shown in Figures 57A and 57B, the pretreated silicon wafer can be layer cut. These processes may need to be performed under plug conditions above 400 degrees Celsius because the layer is not yet cut to the substrate with the metal interconnect circuit. As shown in FIG. 57A, the N-wafer 5700 can process a layer N+ 5704, which is realized by doping and opening, can also be performed by N+ crystallization, or by forming a deposited layer in a heavily N+ doped polysilicon. Barrier oxide 502 can be grown prior to doping to protect the ruthenium during the doping process and to provide an oxide layer for subsequent wafer-to-wafer bonding. Figure 57B is a pre-processed wafer that can be used for layer cutting. After doping 5707 atoms, such as H+, the plane 5708 can be prepared in the N-region 5700A of the substrate and then processed by plasma or other surface treatment. The oxide surface of the wafer oxide layer is bonded to the oxide. The acceptor wafer or outer casing wafer 808 has a logic transistor and a metal interconnect circuit that can be used for low temperature oxide-oxide wafer bonding, and surface oxide surface treatment, as shown in Figure 57C. After the surface donor wafer is sliced, it is separated from the lower acceptor wafer 808, and the surface N-substrate is processed by CMP to the N+ layer 5704 to form a junctionless transistor surface gate layer. The metal wiring strip 5706 in the acceptor wafer or housing 808 is shown in Figure 57C. For simplicity and clarity, the donor wafer oxide layer 5702 and the acceptor wafer or outer layer 808 oxide layers are not shown separately, as shown in Figures 57D-57G.

A thin layer of oxide can be grown to protect the surface of the thiner transistor layer 5704, and then the thin transistor channel assembly 5708 can be mask etched, as shown in Figure 57D, and then the photoresist is cleaned. After the thin oxide layer is washed away by the diluted HF solution, the low temperature based gate insulator can be deposited and encrypted for use as the gate oxide layer 5710 of the junctionless transistor. Alternatively, the surface of the twin crystal may be oxidized using a low temperature microwave ion beam oxidation process to form a gate oxide layer 5710 of the junctionless transistor, or a HKMG gate oxide may be formed using an atomic layer deposition (ALD) technique.

Low temperature gate material 5712 deposition, such as P+ doped amorphous germanium, can also be performed, as shown in Figure 57E. In addition, a high-k metal gate structure can also be obtained using the above procedure. Thereafter, the gate material 5712 is cross-processed through the mask and etch to the surface of the transistor channel assembly 5708 and the side gates 5714, the intersections being generally perpendicular, as shown in FIG. 57F.

Thereafter, the entire structure is covered with a low temperature oxide layer 5716, which is smoothed using chemical and mechanical polishing, and masked and etched out contacts and metal interconnect circuits, as shown in Figure 57G. A gate contact 5720 is used to connect the gate 5714. The electrode contacts 5722 of the two transistor channels are connected to the transistor assembly 5708 and the gate 5714 on both sides, respectively. The via vias 5724 connect the transistor metal layer and the acceptor wafer or via wafer 808 at the interconnect circuit 5706. The process is capable of forming a single crystal germanium 4 gate-controlled junctionless transistor that can be connected to the underlying multi-metal layer semiconductor component without the need to expose the lower component to high temperatures.

Alternatively, as shown in Figures 58A-58G, an N-channel 3-sided gate-controlled thin-junction-free transistor (JLT) can be built in the corresponding 3D IC fabrication process. The thin-face-free junctionless transistor has the thinnest dimension when the channel cross-section is facing up (horizontally placed), and the cross-section is parallel to the surface of the germanium substrate. The thin, face-up, junctionless transistor described above in the context may also have the thinnest dimension when the channel cross-section faces up (vertically) and the cross-section is perpendicular to the surface of the germanium substrate. As shown in Figures 58A and 58B, the pretreated silicon wafer can be layer cut. These processes may need to be performed under plug conditions above 400 degrees Celsius because the layer is not yet cut to the substrate with the metal interconnect circuit. As shown in FIG. 58A, the N-wafer 5800 can process a layer N+ 5804, which is achieved by doping and opening, can also be grown by N+ crystallization, or by forming a deposited layer of heavily N+ doped polysilicon. Barrier oxide 5802 can be grown prior to doping to protect the ruthenium during the doping process and provide an oxide layer for subsequent wafer-to-wafer bonding. Figure 58B shows a pre-processed wafer that can be used for layer-cutting. After doping 5802 atoms, such as H+, a plane 5806 can be prepared in the N-region 5800 of the substrate and then plasma or other surface treated to form a crystal. The oxide surface of the round oxide layer is bonded to the oxide. The acceptor wafer 808 has a logic transistor and a metal interconnection circuit. After pretreatment, it can be used for low temperature oxide-oxide wafer bonding and surface oxide surface treatment, as shown in Fig. 58C. After the surface donor wafer is layered, it is separated from the lower acceptor wafer 808, and the surface N-substrate is CMP processed to the N+ layer 5804 to form a junctionless transistor channel layer. Figure 58C is a deposition of a CMP and plasma etch stop layer 5805, such as a low temperature SiN on the oxide surface, on the surface of the N+ layer 5804. The metal wiring layer 5806 in the acceptor wafer or housing 808 is shown in Figure 58C. For simplicity and clarity, the donor wafer oxide layer 5802 and the acceptor wafer or outer casing 808 oxide layers are not shown separately, as shown in Figures 58D-58G.

After the transistor channel assembly 5808 is processed through a mask and etch as shown in Figure 58D, the photoresist is removed. As shown in FIG. 48E, the low temperature based gate insulator is deposited and densified as the gate oxide layer 5810 of the junctionless transistor. Alternatively, the surface of the twin crystal may be oxidized using a low temperature microwave ion beam oxidation process to form a gate oxide layer 5810 of the junctionless transistor, or a HKMG gate oxide may be formed using an atomic layer deposition (ALD) technique. Low temperature gate material 5812 deposition, such as P+ doped amorphous germanium, can also be performed. In addition, a high-k metal gate structure can also be obtained using the above procedure. Thereafter, gate material 5812 is masked and etched onto the surface of transistor channel assembly 5808 and side gate 5814. As shown in Figure 58G, the entire structure is covered with a low temperature oxide layer 5816 which is planarized using chemical and mechanical polishing and masked and etched out contacts and metal interconnect circuits. Gate contact 5820 is coupled to resistive gate 5814 (eg, from the front and rear planes of other components, as shown in Figure 58G). The electrode contacts 5822 of the two transistor channels are connected to the transistor channel assembly 5808 and the gate 5814 on both sides, respectively. Through-via vias 5824 connect the transistor metal layer and the acceptor wafer or via wafer 808 at interconnect circuit 5806. The process is capable of forming a single-crystal 矽3 face-up gate-controlled junctionless transistor that can be connected to the underlying multi-metal layer semiconductor component without the need to expose the underlying component to high temperatures. Figures 57A-57G, and the illustrations in Figures 58A-58G (not enlarged), will be readily apparent to those having a basic knowledge. It is also readily conceivable that a variety of variations can be produced thereby. For example, the above described process of combining bodies 57A-57G can be used to fabricate a junctionless transistor having a height greater than the width, or a combination of 58A-58G. The process described can be used to fabricate a junctionless transistor having a width greater than a height. Upon reading this description, skilled artisans will appreciate that the scope of the invention will encompass a number of modifications. Therefore, this invention is not limited to the patent claims in the attachment.

In addition, as shown in Figures 61A-61I, a two-layer N-channel 3-sided gate-controlled junctionless transistor (JLT) can be built in the corresponding 3D IC fabrication process. This structure can increase the source and drain resistance by doping at the contact surface with a higher concentration than the channel. Moreover, the structure can be used to construct a 2-layer channel, and the channel doping concentration closer to the gate is higher. As shown in Figures 61A and 61B, the pretreated silicon wafer can be layer cut. These pre-treatment processes may need to be performed under plug-in conditions above 400 degrees Celsius because the layer cut to the substrate with the metal interconnect circuit has not been completed. As shown in FIG. 61A, the N-wafer 6100 can process a double-layer N+, and the surface layer 6104 has a lower doping concentration than the underlying N+ layer 6103. It can be realized by doping and opening, and can also be realized by N+ crystallization, or a combination method. . Vertically doped layers or gradients can also be constructed using one or more in situ doping of amorphous tantalum. Barrier oxide 6102 can be grown prior to doping to protect the ruthenium during the doping process and provide an oxide layer for subsequent wafer-to-wafer bonding. Figure 61B is a pre-processed wafer that can be used for layer cutting. After doping 6107 atoms, such as H+, the "cut-out plane" 6109 can be prepared in the N-region 6100A of the substrate, and then subjected to plasma or other surface treatment. Forming an oxide surface of the wafer oxide layer for oxide bonding.

The acceptor wafer or outer casing wafer 808 has a logic transistor and a metal interconnect circuit that can be used for low temperature oxide-oxide wafer bonding, and surface oxide surface treatment, as shown in Figure 61C. After the surface donor wafer is layered, it is separated from the lower acceptor wafer 808, and the surface N-substrate is CMP processed to the N+ layer 6103 to form a higher doping concentration N+ layer 6103. An etched hard film may be deposited on the surface of 6103 using a low temperature tantalum nitride 6105 comprising a thin oxide stress buffer layer. Metal interconnect circuit pads or strips 5706 in the acceptor wafer or housing 808 are shown in Figure 61C. For simplicity and clarity, the donor wafer oxide layer 6102 and the acceptor wafer or outer layer 808 oxide layers are not shown separately, as shown in Figures 61D-61I.

The source and drain connection regions can be masked, the tantalum nitride 6105 is etched away, and the photoresist is removed. Part or all of the ruthenium plasma etching may be performed, or the oxide may be etched using HF acid after low temperature oxidation until the thin layer 6103. As shown in Fig. 61D, the double-layered trench, previously described with reference to 52A and 52B, is illustrated and simulated. The thin layer 6103 formed by the above etching process is almost completely removed, and the portion 6103 where the raw portion is formed is on the surface of 6104, and then is 6105. The complete 6103 layer is retained below. The 6103 layer of the surface channel can be completely removed. This etch process will be used to adjust the wafer-to-wafer CMP deformation of the remaining donor wafer layers, such as 6100 and 6103, after the layer has removed a channel with a smaller thickness variation.

In Fig. 61E, the photoresist 6150 defines a source 6151 of a junctionless transistor (a 6103 region of a full thickness), a drain 6152 (another full thickness of 6104) region, and a channel 5153 (a partial thickness of 6130 and 6104) of full thickness.

The exposed twins on layer 6104, as shown in Figure 61F, can be etched with a plasma and the photoresist 6159 removed. This process will form isolation between the components and define the channel width of the junctionless transistor channel 6108.

As shown in FIG. 61G, the low temperature based gate insulator is deposited and densified as the gate oxide layer 6110 of the junctionless transistor. Alternatively, the surface of the twin crystal may be oxidized using a low temperature microwave ion beam oxidation process to form a gate oxide layer 6110 of a junctionless transistor, or a HKMG gate oxide may be formed using an atomic layer deposition (ALD) technique. It is also possible to deposit a low temperature gate material 6112, such as doped amorphous iridium, as shown in Figure 61G. In addition, a high-k metal gate structure can also be obtained using the above procedure.

Thereafter, the gate material 6112 is cross-processed through the mask and etch to the surface of the transistor channel assembly 6108 and the side gates 6114, the intersections being generally perpendicular, as shown in FIG. 61H. Upon completion, the entire structure can be covered with a low temperature oxide 6116 which can be planarized by CMP processing.

Thereafter, masking and etching of the contacts and the metal interconnection circuit are performed as shown in Fig. 61I. Gate contact 6120 is used to connect gate 6114. The source/drain electrode contacts 6122 of the two transistors are respectively connected to the heavily doped layers 6103 on both sides, and then connected to the transistor channel assembly 6108 and the gate 6114. The via vias 6124 connect the junctionless transistor metal layer and the acceptor wafer or via wafer 808 at the interconnect circuit 6106. Vias 6124 can be masked and etched separately to provide processing allowance for the other contacts 6122 and 6120. The process is capable of forming a single crystal germanium double-layered 3-sided gate-controlled junctionless transistor that can be connected to a plurality of metal layer semiconductor components of the lower layer without the need to expose the lower layer components to high temperatures.

In addition, as shown in Figures 65A-C, a 1-sided gate-controlled junctionless transistor (JLT) can be built in the corresponding 3D IC fabrication process. A thin layer of heavily doped twin layer 6503 can be etched through the surface of the acceptor wafer or the outer shell wafer 808. The layering technique described above can be used to make the oxide layer 6501 of the donor wafer available for use. The main wafer or outer casing wafer 808 is bonded by an oxide layer. The doped doped layer 6503 can be N+ doped, used as an N-type junctionless transistor, or P+ doped, as a P-structured knotless new transistor. As shown in FIG. 65B, oxide layer isolation 6506 can be obtained by masking and etching on N+ layer 6503, and subsequent low temperature oxide deposition can be chemical mechanically polished until the thickness of channel twinning 6503. The channel thickness 6504 can be adjusted at this step. The low temperature gate insulating layer 6504 and the gate metal layer 6505 can be deposited or grown by signing, and then photolithographically printed and etched. As shown in Fig. 65C, a low temperature oxide layer 6508 can then be deposited which can also provide the mechanical stresses required for the channel to enhance carrier activity. The contact opening 6510 can then be processed to function as an enabler for the junctionless transistor. It is foreseen by a person skilled in the art that the above methods are merely for reference, and other cases and applications may be derived based on the principles of the invention, and the scope of the invention is not limited by the appended claims.

Since the surface transistor and the underlying layer have been aligned with the fabrication of the acceptor wafer or the outer casing wafer 808, processing of the vertical component family is possible. The vertical component can be doped and annealed through the single crystal germanium layer of the transistor, using a "smart cutting" layering process in which the upper temperature limit must not exceed the limits of the underlying prefabricated structure. For example, vertical MOSFET transistors, floating gate flash memory transistors, attached DRAMs, thyristors, bipolar and Schottky gate-controlled JFET transistors, and memory components. A knotless transistor can also be constructed using a similar method. The vertical transistor or resistor gate can be controlled by a memory or logic component such as MOSFET, DRAM, SRAM, floating mountain village, anti-fuse storage, floating body components, etc., which are located above or below the vertical insert. For example, a vertical full gate-controlled N-MOSFET transistor can be constructed as follows.

The donor wafer is subjected to a general layering process as shown in FIG. 39 as a pretreatment. Obtaining a P-wafer 3902 can process a "buried" layer N+3904, which is achieved by doping and opening, and also by shallow N+ doping and diffusion. After the process, a P-grained growth layer 3906 is deposited and finally another N+ layer 3908 is machined on the surface. The N+ layer 2510 can be processed again using doping and opening, or N+ reticular growth.

39B is a pre-processed wafer capable of conducting a conductive bonding layer. After depositing a conductive barrier layer 3910, such as TiN or TaN, on the surface of the N+ layer 3908, and then doping atoms, such as H+, may be in the N+ region. The lower part of 3904 is ready for the cutting of the plane 3912.

As shown in FIG. 39C, the acceptor wafer may be pre-cleaned using an oxide layer and a conductive barrier layer 3916 and an Al-Ge layer 3914 deposited. The Al-Ge eutectic layer 3914 can be combined with the conductive barrier layer 3910 to form an Al-Ge eutectic bond, which is realized in an annealing and pressing wafer bonding process, and is part of the layer cutting process, after which the single crystal is pretreated. The N+ and P- layers are layer cut. Thus, a conductive path can be obtained on the surface metal layer 3920 of the outer casing 808 to connect the bottom N+ layer 3908 of the donor wafer. Alternatively, the Al-Ge eutectic layer 3914 can be processed using copper to obtain a copper-copper or copper-barrier layer annealed pressure bonding layer. Similarly, the outer surface of the donor wafer can be obtained by directly annealing and bonding the outer surface of the metal wire 3920 (from copper and barrier metal) to the copper layer 3910. The majority of the bonding surface is the copper and the outer surface of the donor wafer. The oxide layer of the wafer, the remaining surface is the copper of the donor wafer and the copper of the outer casing wafer 808 and the adhesion layer of the barrier metal.

40A-40I are schematic views of the formation of a vertical full gate-controlled n-MOSFET surface layer transistor. Figure 40A is the first step. After the above-described conductive via layer is diced, deposition of a CMP and plasma etch stop layer 4002, such as low temperature SiN, is achieved by deposition on the surface of the N+ layer 3904. For simplicity, the conductive barrier layers 3910, 3914, and 3916 are shown by conductive layer 4004 as shown in FIG. 40A.

Figures 40B-H are vertical projections (e.g., top views of horizontal and vertical interfaces) showing partial flow and vertical relationships. The transistor is square in plan view, but can be constructed in a rectangular shape to achieve different width and gate control effects. In addition, the square crystal can be intentionally configured to be circular in a plan view to form a vertical cylinder, or it can be obtained in a subsequent process, and finally becomes a vertical tower. Referring to Figure 40B, vertical transistor column 4006 is patterned through a mask, and plasma/reactive ion etching (RIE) etching to chemical mechanical polishing (CMP) stop layer 4004, N+ layers 3904 and 3908, and P-layer 3906, conductive. The metal bonding layer 4004, up to the oxide layer of the outer casing wafer 808, is subsequently removed, as shown in Figure 40B. This definition and etching allows the N-P-N stack to be built such that the bottom N+ layer 3908 is connected to the outer cladding metal layer 3920 through the conductive layer 4004.

The area between the column and the column is partially rotated, solidified, and etched back by the oxide 4010 through a spin-on glass (SPG), as shown in Figure 40C. Alternatively, a low temperature CVD void fill oxide layer can be deposited, then smoothed using CMP, and then selectively etched back to form the same oxide layer shape 4010 as shown in Figure 40C. The height of the oxide layer 4010 can be determined as follows: a small portion of the bottom N+ tower layer 3908 is not covered by the oxide layer. Alternatively, this step can be obtained by an equivalent low temperature oxide CVD deposition and etch back process to form an isolated contour covering of the bottom N+ tower layer 3908.

In addition, the side gate oxide 4014 is constructed by low temperature microwave oxidation technology, such as TEL SPA (Tokyo Electron Limited Slot Plane Antenna) oxygen free plasma, using an aqueous compound, such as diluted HF, to remove, and then as shown in Figure 40D Re-growth 4014.

A gate, such as an equivalent doped amorphous layer 4018, is then deposited, as shown in Figure 40E. Thereafter, a gate mask photoresist 4020 is drawn.

As shown in FIG. 40F, the etching of the gate layer 4018 should ensure that the isolated outline gate 4022 remains in the region and is not covered by the photoresist 4020. The full thickness of the gate layer 4018 should be fully retained where it is covered by the resistor 4020, and the gate layer 4020 should be completely removed from between the columns. Finally, the photoresist 4020 is removed. This method minimizes the gate coverage of the gate and ultimately achieves a clean contact connection to the gate.

As shown in Fig. 40G, the gap between the columns is filled and the column is covered by the oxide layer 4030 through the low temperature gap filling and CMP.

In FIG. 40H, via contact 4034 coupled to tower N+ layer 3904 is obtained through a mask and etch, followed by masking and etching via contact 4036 associated with gate polysilicon 4024.

The metal line 4040 is obtained by masking and etching, is filled with an isolation metal and a copper interconnection circuit, and is CMP-polished using a normal interconnection circuit scheme, thereby completing a via connection with the contact of the tower N+3904 and the gate 4024, as shown in the figure. 40I is shown.

The process is capable of forming a single crystal germanium surface MOS transistor that can be connected to the underlying multi-metal layer semiconductor component without the need to expose the underlying components and interconnecting circuit metal to high temperatures. These transistors can be used as the anti-fuse memory programming transistor of layer 807, connected to the metal layer of the wafer or layer 808 to form a monolithic 3D IC, as a transfer transistor on the wafer or layer 808, or the user FPGA, or For other 3D semiconductor components.

In addition, vertical full-gated junctionless transistors can also be constructed as shown in Figures 54 and 55. FIG. 54A is a schematic diagram of layer resection using a pre-processed crystal; an N-wafer 5402 can process an N+ layer 5404, which is realized by ion implantation and opening, and can also be realized by N+ regrown growth. FIG. 54B is a pre-processed wafer capable of conducting a conductive bonding layer. After depositing a conductive barrier layer 5410, such as TiN or TaN, on the surface of the N+ layer 5410, and then doping atoms, such as H+, may be in the N+ region. The lower part of 5404 is ready to cut out the plane 5412 of the wisdom cut.

The acceptor wafer or outer casing wafer 808 can also be processed by oxide pre-cleaning and deposition of the conductive isolation layer 5416 and the AL and Ge layers to form a Ge-Al eutectic bonding layer 5414, which is annealed in a pressurized wafer. Finished in the bond, which is part of the layer cutting process, and then the surface of the acceptor wafer or the outer shell wafer 808 is layer-cut with the pretreated single crystal germanium layer and an N+ layer 5404 shown in FIG. 54B, as shown in FIG. 54C. Show. The N+ layer 5405 can be polished to remove scratches left by the layer cutting process. Thus, a conductive path can be obtained on the surface metal layer 5420 of the acceptor wafer or housing 808 to connect the N+ layer 5404 of the donor wafer. Alternatively, the Al-Ge eutectic layer 5414 can be processed using copper to obtain a copper-copper or copper-barrier layer annealed pressure bonding layer. Similarly, the donor wafer or the outer conductor wafer 5420 (from copper and barrier metal) can be directly annealed and bonded to the copper layer 5410 to obtain a conductive path connecting the donor wafer, wherein most of the bonding surface is a donor wafer. The copper and the oxide layer of the outer casing wafer, the remaining surface being the copper of the donor wafer and the copper of the donor wafer or outer casing wafer 808 and the adhesion layer of the barrier metal.

55A-55I are schematic views of the formation of a vertical full gate controlled junctionless transistor over the pretreated acceptor wafer or housing 808 of FIG. 54C. Figure 55A shows the deposition of a CMP and plasma etch stop layer 5502, such as a low temperature SiN, on the surface of the N+ layer 5504. For simplicity, the barrier covered Al-Ge eutectic layers 5410, 5414, and 5416 in FIG. 54C are represented by conductive layer 5500.

Similarly, Figures 55B-H are vertical projections showing partial flow and vertical relationships. The junctionless transistor is square in plan view, but can be constructed in a rectangular shape to achieve different channel thickness, width, and gate control effects. In addition, the square crystal can be intentionally configured to be circular in a plan view to form a vertical cylinder, or it can be obtained in a subsequent process, and finally becomes a vertical tower. Vertical transistor tower 5506 is patterned through a mask, and plasma/reactive ion etching (RIE) etching to chemical mechanical polishing (CMP) stop layer 5502, N+ layers 5504 and 3908, conductive metal bonding layer 5500, up to the outer wafer The oxide layer of 808 is subsequently removed, as shown in Figure 55B. This definition and etch can build an N+ transistor channel stack that is isolated from each other, but the bottom of the N+ layer 5404 is conductive to the outer cladding metal layer 5420.

The area between the column and the column is partially rotated by the oxide 5510 through a spin-on glass (SPG), solidified at a low temperature, and etched back, as shown in Fig. 55C. Alternatively, a low temperature CVD void fill oxide layer can be deposited, then CMP smoothed, followed by selective etch back to form the same shape 5510 as shown in Figure 55C. Alternatively, this step can be obtained by an equivalent low temperature oxide CVD deposition and etch back process to form an isolated profile coverage of the N+ resistor tower layer 5504.

In addition, the side gate oxide 5514 is constructed by low temperature microwave oxidation technology, such as TEL SPA (Tokyo Electron Limited Slot Plane Antenna) oxygen free plasma, using an aqueous compound, such as diluted HF, removed, and then re-displayed as shown in Figure 55D Growing 5514.

A gate is then deposited, such as a P+ doped amorphous silicon layer 5518, followed by chemical mechanical polishing, smoothing, and then selective etch back to obtain the shape 5518 shown in Figure 55E, followed by gate mask light. The line drawn by the glue 5520 is as shown in Fig. 55E.

The gate layer 5518 is etched such that the gate layer is completely clear from between the columns, and then the photoresist is removed as shown in Figure 55F.

As shown in Fig. 55G, the gap between the columns is filled, the column is deposited by the oxide layer 5530 through the low temperature gap, and then subjected to CMP processing, and another oxide deposition, as shown in Fig. 55G.

In Figure 55H, contact 5534 coupled to transistor column N+ layer 5504 is obtained by masking and etching, followed by masking and etching contact 5518 associated with gate polysilicon 5518. Metal line 5540 is obtained by masking and etching, is filled with isolation metal and copper interconnect circuitry, and is CMP polished using a conventional dual damascene interconnect circuit scheme to complete contact with transistor channel tower N+5504 and gate 5518. Via connections are shown in Figure 55I.

The process is capable of forming a single crystal germanium surface vertical junctionless transistor that can be connected to the underlying multi-metal layer semiconductor component without the need to expose the underlying components and interconnecting circuit metal to high temperatures. These junctionless transistors can be used as a programmable transistor on the acceptor or shell wafer 808, or as a transfer transistor for logic components, or for FPG, or for other 3D semiconductor components.

A groove array transistor (RCAT) can be used with another family of transistors to enable the construction of low temperature bulk 3D ICs using layer cut and etch definitions. Two types of RCAT component structures are shown in Figure 66. It was explained by J. Kim et al. at the VLSI Technology Forum 2003-2005. It is noted that the background art described by Kim et al. belongs to a single layer transistor and does not use any layer cutting technique. They also use high-temperature processes in their work, such as source-drain opening annealing, which uses temperatures above 400 degrees Celsius. The difference is that the case of the transistor in a two-dimensional plane is used in the case of the present invention. All transistors (no junction, recessed or depleted, etc.) have source and drain in the same two-dimensional plane and can be considered planar transistors.

As shown in Figures 67A-F, the layer stacking method is used to construct a 3D integrated circuit and a standard RCAT. For an N-slot MOSFET, a P-矽 wafer 6700 can be used as a starting point for processing. The N+Si buried layer 6702 can be doped, as shown in FIG. 67A, to obtain a P-layer 6703 located on the surface of the donor wafer. Another method is to do a shallow N+Si doping and then deposit a P-Si layer 6703 on the outer edge. To turn on the doping material of the N+ layer 6702, the wafer can be annealed using standard annealing procedures such as gas annealing, tip annealing or laser annealing.

An oxide layer 6701 can then be grown or deposited as shown in Figure 67B. Nitrogen can be doped into the wafer 6704 and then subjected to a smart cutting process, as shown in Figure 67B.

Layer cutting can then be performed to bond the wafer shown in Figure 67B to a pre-processed circuit acceptor wafer 808, as shown in Figure 67C. The doped germanium layer 6704 can be used to cut the remainder of the wafer 6700.

After cutting, chemical mechanical polishing (CMP) can be performed. The oxide isolation region 6705 can be processed and etched to form a recess 6706 as shown in FIG. 67D. This etching process can be further adjusted so that the sharp corners are smoothed to avoid high points.

A gate insulating layer 6707 can then be deposited through the atomic layer deposition or through a low temperature oxide forming process. A metal gate 6708 can then be deposited, filled with recesses, and then CMP and gate drawn, as shown in Figure 67E.

A low temperature oxide layer 6709 can then be deposited and planarized using CMP. Contact 6710 is then machined to connect all of the electrodes of the transistor as shown in Figure 67F. The process is capable of forming a complete low temperature RCAT on the surface of the pre-processing circuit 808. The P-slot MOSFET can then be processed using an analog process. The P and N slots RCAT can be used to form a monolithic 3D CMOS circuit component library.

As shown in Figures 68A-F, the layer stacking method is used to construct a 3D integrated circuit and a standard RCAT. For an N-slot MOSFET, a P-矽 wafer 6800 can be used as a starting point for processing. The N+Si buried layer 6802 can be doped as shown in Figure 68A to provide a P-layer 6803 on the surface of the donor wafer. Another method is to do a shallow N+Si doping and then deposit a P-Si layer 6803 on the outer edge. The doping material of the N+ layer 6802 is turned on, and the wafer can be annealed using a standard annealing procedure such as gas annealing, tip annealing or laser annealing.

An oxide layer 6801 can then be grown or deposited as shown in Figure 68B. Hydrogen gas can be doped into the wafer 6804 and then subjected to smart cutting as shown in Figure 68B.

The layer cut can then be performed to bond the wafer shown in Figure 68B to a pre-processed circuit acceptor wafer 808, as shown in Figure 68C. The doped germanium layer 6804 can be used to dicing the remainder of the wafer 6800. After cutting, chemical mechanical polishing (CMP) can be performed.

The oxide isolation region 6805 can be processed as shown in Figure 68D. The resulting gate recess can be obtained by masking and partial etching, and then spacer deposition 6806 can be used for equivalent low temperature deposition, such as tantalum oxide or tantalum nitride or combinations thereof.

An anisotropic etch can be applied to the spacer such that the spacer material remains only on the vertical sides of the recess gate opening. A uniform twinning etch can then be performed to form a spherical recess 6807, as shown in Figure 68E. The spacing between the sides can be removed using a selective etch.

A gate insulating layer 6808 can then be deposited through the atomic layer deposition or through a low temperature oxide forming process. A metal gate 6809 can then be deposited, filled with recesses, and then CMP and gate drawn, as shown in Figure 68F. The gate material can also be doped using a low temperature conductor of amorphous or suitable work function. A low temperature oxide layer 6810 can then be deposited and planarized using CMP. Contact 6811 is then machined to connect all of the electrodes of the transistor as shown in Figure 68F.

This process enables the formation of a complete low temperature S-RCAT on the surface of the pre-processing circuit 808. The P-slot MOSFET can then be processed using an analog process. The P and N slots S-RCAT can be used to form a monolithic 3D CMOS circuit component library. In addition, SRAM circuits built using RCAT may have different groove depths than logic circuits. The RCAT and S-RCAT components can be used to build BiCMOS inverters and other hybrid circuits, as long as the outer casing 808 has a conventional bipolar junction transistor and can be layered to build a monolithic RCAT assembly.

The 3D component structure can be built in a single crystal germanium layer, and by utilizing the advantages of pre-treating the donor wafer, by constructing different material layers of the wafer size, without temperature limitation, then layer-cutting the donor wafer to the acceptor crystal Round, then select different processing steps for processing, then repeat the above process multiple times and use low temperature (less than 400 degrees Celsius) or high temperature (above 400 degrees Celsius) for processing, after the last layer is cut, in one or more A memory structure is constructed on the cut-out layers that are aligned with each other, such as a transistor, and the layers can be in communication with the acceptor wafer.

The new monolithic 3D dynamic access storage (DRAM) can be constructed using the above method. Some examples of the invention are floating DRAM type.

Floating DRAM is a new generation of DRAM, and several companies are currently developing DRAM, such as Innovative Silicon, Synix, and Toshiba. The floating DRAM saves the data as the charge of an SOI MOSFET or the charge of a multi-gate MOSFET. Details of the floating DRAM and the type of operation can be found in the following U.S. patents and other documents: 7541616, 7514748, 7499358, 7749352, 7492632, 74856563, 7447540, 7476939. The monolithic 3D integrated DRAM can be constructed using a floating body transistor. The prior art for building monolithic 3D DRAMs uses planar transistors, which are formed using selective epi techniques or laser recrystallization techniques. Selective epi technology and laser recrystallization technology are not capable of producing perfect single crystal germanium and often have high thermal energy expenditures. A description of the process can be found in the book "Integrated Interconnect Technologies for 3D Nanoelectronic System" by Bakir and Meindl.

As shown in Fig. 97, the basic elements of the floating DRAM in operation will be described below. In order to store the "1" byte, it may be necessary to have excess holes 9702 in the floating body region 9720 and change the threshold voltage of the memory wafer transistor. The transistor includes the source 9704, the gate 9706, the floating body 9720, and the buried body. Oxide layer (BOX) 9718. As shown in Figure 97a. In order to store 0 bytes, it may be necessary to have excess holes 9710 in the floating body region 9720 and change the threshold voltage of the memory wafer transistor. The transistor includes a source 9712, a gate 9714, a floating body 9720, and a buried oxide layer. (BOX) 9716. As shown in Figure 97b. The difference in the threshold voltage of the wafer transistor stored in Figures 97a and 97b is such that the transistor is in a different operating state in the drain current 9734, at which time the transistor gate voltage 9736 is a specified value. As shown in Figure 97c. The difference in current 9730 can be discriminated by the sense amplifier circuit as states of "0" and "1", respectively, and stored in the wafer.

As shown in Figures 98A-H, each of the horizontally arranged monolithic 3D DRAMs uses two masking steps, which can be constructed using a suitable 3D IC fabrication process.

As shown in FIG. 98A, a P-substrate donor wafer 9800 can be processed into a p-doped twin layer 9804 comprising a wafer size. P-layer 9804 can have the same or a different doping concentration than P-substrate 9800. The P-doped layer 9804 can be fabricated by ion implantation or annealing annealing. Barrier oxide layer 9801 can be grown prior to doping to protect the twins from being doped while providing an oxide layer for subsequent oxide layer bonding.

As shown in FIG. 98B, the surface of the donor wafer 9800 can be re-oxidized by depositing an oxide layer 9802 or annealing a P-layer 9804 for oxide layer wafer bonding or using a doped barrier oxide layer 9801. The layer-cut dividing plane 9899 (shown in phantom) may be implemented on donor wafer 9800 or P-layer 9804 (see figure) by doping 氦 9807 or other methods as previously described. Both the donor wafer 9800 and the acceptor wafer 9810 can be processed for wafer bonding. As previously mentioned, it is preferred to use low temperature (less than 400 degrees Celsius) to reduce stress during bonding. A portion of the P-donor wafer substrate 9804, and a portion of the P-donor wafer substrate 9800, is located above the layer-cut plane 9899 and can be removed by dicing and sanding, or other methods as previously described, such as ion cutting.

As shown in Figure 98C, the remaining P-doped layer 9804', and oxide layer 9802 are layered to the acceptor wafer 9810. The acceptor wafer 9810 can include peripheral circuitry that can withstand the effects of additional rapid thermal annealing (RTA) while maintaining operational capability and better performance. Therefore, the configuration of the peripheral circuit preferably does not use RTA to turn on the dopant, or use a weak RTA. Moreover, the peripheral circuit can use a high temperature resistant metal such as tungsten to withstand temperatures greater than 400 degrees Celsius. The surface of the P-doped layer 9804' can be smoothed using chemical and mechanical polishing. Today, the transistor can be constructed and aligned with alignment marks (not shown) of the acceptor wafer 9810.

As shown in Fig. 98D, a shallow trench isolation (STI) oxide region (not shown) may be etched using a printed line and plasma/RIE to at least the surface layer of oxide layer 9802 to remove the P-monocrystalline germanium layer 9804' region. The gap-fill oxide can be planarized by deposition and CMP to form an STI oxide region, and a transistor is constructed using a P-doped single crystal germanium region (not shown). At this point, you can choose whether to perform the threshold adjustment doping. Gate stack 9824 can be constructed using a gate insulator, such as an annealed oxide layer, and a gate metal material, such as a polysilicon. In addition, the gate oxide can be an atomic layer doped (ALD) gate insulating layer with a work function corresponding to the designated gate metal, which is a high K metal gate processing scheme according to industry standards. Alternatively, the gate oxide can be formed by rapid annealing oxidation (RTO) molding, low temperature oxide layer deposition, or low temperature microwave plasma oxidation of the germanium surface, and then clicking on a gate material such as tungsten or aluminum. The gate stack is aligned with the LDD (lightly doped drain) and then a circular heavily through layer doping can be performed to adjust the junction and transistor breakdown characteristics. Oxide and/or nitride gap deposition may also be used and a doping offset gap (not shown) may be built over gate stack 9824 by subsequent etch back. N+ source and drain doping, which can be self-aligned, can be performed to build the transistor source and drain 9820 and the remaining P-twist NMOS transistor channel 9828. At this point, you can choose whether to perform a high temperature annealing step to turn on the dopant and set the initial junction depth. Finally, the entire gap fill oxide 9850 can be covered with a low temperature oxide 9850 and planarized by CMP. The oxide surface can be processed as a twinned oxide oxide as previously described.

As shown in Fig. 98E, the formation of the transistor layer, bonding to the oxide layer 9850 of the acceptor wafer 9810, and subsequent transistor formation of Figs. 98A-D, can be repeated to construct a second layer 9830 of the storage transistor. After all of the memory layers have been constructed, the rapid doping annealing (RTA) can be used to turn on the doping material for all of the memory layers, as well as the peripheral circuitry in the acceptor substrate 9810. In addition, optical annealing such as laser annealing or the like can also be employed.

As shown in Figure 98F, the contacts and metal interconnect circuitry can be processed through printing and plasma/RIE etching. A bit line (BL) contact 9840 is in communication with the transistor N+ region of the memory layer, which is located in the transistor drain layer 9854, and the source line contact 9842 is connected to the memory layer transistor N+ region, which is located in the transistor Source side 9852. Bit line (BL) line 9848 and source line (SL) line 9846 are connected to bit line contact 9840 and source line contact 9842, respectively. A gate stack, such as 9834, can be connected to contacts and metal layers (not shown) to form a word line (WL). Through-via vias 9860 (not shown) may be in communication with the metal layers of BL, SL, WL and connected to the acceptor substrate metal bond pads 1980 (not shown).

As shown in FIG. 98G, for a top cross-sectional view of the surface of the memory array, WL line 9864 and SL line 9865 can be arranged perpendicular to BL line 9866.

As shown in Figure 98H, in a single layer DRAM array scheme, WL, BL, and SL are connected at each array layer. The multi-layer structure of the array shares the BL and SL contacts, but each layer has its own WL connection group and enables individual access to each byte.

The process is capable of forming a horizontally arranged monolithic 3D DRAM array by performing two mask processes on each memory array, by layer-cutting the wafer-sized doped single crystal germanium layer, and then the 3D DRAM array can be The underlying multi-metal layer semiconductor components are connected, and the underlying components may or may not include peripheral circuits for controlling the read and write functions of the DRAM.

The illustrations in Figures 98A-98H (not enlarged) will be readily apparent to those of ordinary skill. It will be readily apparent to those skilled in the art that many variations can be derived on this basis, for example, the transistor can be of other types such as RCAT or knotless. Alternatively, the contacts may also use doped polysilicon or other conductive materials. Alternatively, the stack of storage layers can be connected to the peripheral circuitry above. Upon reading this description, the skilled artisan will appreciate that the scope of the invention will encompass a number of modifications. Therefore, this invention is not limited to the patent claims in the attachment.

As shown in Figures 99A-99M, each of the horizontally arranged monolithic 3D DRAMs uses two masking steps, which can be constructed using a suitable 3D IC fabrication process.

As shown in FIG. 99A, the ruthenium-based plate having the peripheral circuit 9902 can be used with high temperature (above 400 degrees Celsius) wiring, such as tungsten. The peripheral circuit substrate 9902 can include memory control circuitry, as well as other functions and types of circuitry, such as analog, digital, microwave (RF) or storage functions. The peripheral circuit substrate 9902 can include peripheral circuits that can withstand the temperature of additional rapid annealing anneal (RTA) and maintain operating capability and better performance. Therefore, the configuration of the peripheral circuits is preferably such that the dopant is not turned on using RTA or turned on using a weak RTA. The surface of the donor wafer 9902 can be deposited by an oxide layer 9904 so that the oxide wafer can be bonded to form the acceptor wafer 2414.

As shown in FIG. 99B, a P-substrate donor wafer 9912 can be processed into a wafer-sized p-doped twin layer 9906 (not shown), which can be doped to a concentration of P-substrate 9906. different. The P-doped layer can be fabricated by ion implantation or annealing annealing. Barrier oxide layer 9908 can be grown or deposited prior to doping to protect the twins from being doped while providing oxidative formation for subsequent oxide layer bonding. The layer-cut dividing plane 9910 (shown in phantom) can be implemented by doping or other methods described above on the donor wafer 9912 of the P-substrate 9906 or on the P-doped layer. Both the donor wafer 9912 and the acceptor wafer 9914 can be processed for wafer bonding. As described above, the oxide layer 9904 and the oxide layer 9908 are bonded to the surface, and it is preferable to use a low temperature (less than 400 degrees Celsius) for bonding. Small stress, or use medium temperature (less than 900 degrees Celsius).

As shown in FIG. 99C, a portion of the P-donor wafer substrate 9906, and the P-wafer substrate 9906 located above the layer-cut plane 9910, can be removed by dicing and polishing, or other methods as previously described, such as ion cutting, etc. Thus, a single crystal 矽P-layer 9906 was constructed. The remaining P-layer 9906' and oxide layer 9908 can be layered to the acceptor wafer 9914. The surface of the P-layer 9906' can be smoothed using chemical and mechanical polishing. The transistor or portion of the transistor can then be constructed and aligned with alignment marks (not shown) of the acceptor wafer 9914.

As shown in Fig. 99D, the N+ twinned region 9916 can be determined by printing a line, and an N-type, such as arsenic, can be implanted into the P- twin layer 9906' using ions. This also allows the construction of the remaining P- twin region 9918.

As shown in Fig. 99E, an oxide layer 9920 may be deposited to prepare the necessary surface for the adhesion between the later oxide and oxide, thus forming a first Si/SiO2 layer 9922. The Si/SiO2 layer comprises a hafnium oxide layer 9920, an N+ germanium region 9916, and a P-fluorene region 9918.

As shown in FIG. 99F, Si/SiO2 layers as shown in FIGS. 99A to 99E may be additionally formed, such as a second Si/SiO2 layer 9924 and a third Si/SiO2 layer 9926. Oxide layer 9929 may be deposited. After all of the desired memory layers are built, rapid high thermal annealing (RTA) can be performed to fundamentally turn on the dopants in all of the memory layers 9922, 9924, and 9926 and peripheral circuitry 9902. Alternatively, optical annealing, such as laser annealing, can be performed.

As shown in FIG. 99G, the oxide layer 9929, the third Si/SiO2 layer 9926, the second Si/SiO2 layer 9924, and the first Si/SiO2 layer 9922 can be photolithographically and plasma/reactive ion etching. A portion of the memory wafer structure is formed. The etch may form a P-turn region 9918 (which forms a floating transistor trench) and an N+ germanium region 9916 (forming source, drain, and local source lines).

As shown in Figure 99H, the gate dielectric and gate electrode materials may be deposited, planarized by chemical-mechanical polishing (CMP), and then photolithographically and plasma/reactive ion etched to form a gate. Polar dielectric 9928. Gate dielectric 9928 may be self-aligned with gate electrode 9930 (as shown) and covered by gate electrode 9930, or may adequately cover the entire tantalum/oxide multilayer structure. The gate stack layer 9930 and gate dielectric 9928 gate stack layers are sized and aligned to ensure that the P-矽 region 9918' is sufficiently and completely covered. The gate stack layer (comprising gate electrode 9930 and gate dielectric 9928) is comprised of a gate dielectric (e.g., a high thermal oxide layer) and a gate electrode material (e.g., polysilicon). Alternatively, the gate dielectric can be selected from atomic layer deposition (ALD) materials that match the work function of the particular gate metal, in accordance with the industry standard for high-k metal gate process solutions as previously described. In addition, the gate dielectric can be formed by rapid high thermal oxidation (RTO). Rapid high thermal oxidation is a process of low temperature oxidation deposition or low temperature microwave plasma oxidation of the tantalum surface, which can eventually be deposited as a gate electrode, such as a tungsten electrode or an aluminum electrode.

As shown in FIG. 99I, the gap-fill oxide layer 9932 can completely cover the entire structure and can be planarized by chemical-mechanical polishing (CMP). For the sake of clarity, the oxide layer 9932 is shown as a transparent layer. In addition to this, there are a character line region (WL) 9950, a gate electrode 9930, a source line region (SL) 9952, and an N+ germanium region 9916' as shown.

As shown in FIG. 99J, the bit line (BL) contact 9934 can be photolithographically and plasma/reactive ion etched and processed by photoresist removal. Subsequently, a metal such as copper, aluminum or tungsten may be deposited, the butt joints filled, and then etched or ground to the top of the oxide layer 9932. Each BL contact 9314 can be fully shared with all of the memory layers, such as the three-layer memory layer shown in Figure 99J. A via via 9960 (not shown) may be formed to electrically couple the metallized regions of BL, SL, and WL to the peripheral circuitry of the acceptor substrate 9914 through the acceptor wafer metal bond pads 9980 (not shown).

As shown in Figure 99K, a BL metal line 9936 can be formed and connected to the associated BL contact 9934. Contacts of WL and SL and associated metal wiring (not shown) may be formed at the edge of the memory array. "Three-dimensional wafer lamination technology for ultra-high-density flash memory with punching and padding technology" ("IEEE Super Large Scale Integration Technology Symposium 2007"; volume number: none; page number: 14-15 12-14; 2007 June issue; author:.. Tanaka, H., Kido, M., Yahashi, K and so on Oomura, M people) technical description of the contacts made in the SL stepped structure.

99L, 99L1 and 99L2, a cross-sectional view of FIG. 99L is shown in FIG. 99L1, and a cross-sectional view of FIG. 99L is shown in FIG. 99L2. The BL metal line 9936, the oxide layer 9932, the BL contact 9934, the WL region 9950, the gate dielectric 9928, the P-turn region 9918', and the peripheral circuit substrate 9902 are shown in Fig. 99L1. The BL contact 9934 is connected to one of the three horizontal planes of the floating body transistor. The floating body transistor contains two N+ germanium regions 9916' and a corresponding P-turn region 9918' for each horizontal plane. The BL metal line 9936, the oxide layer 9932, the gate electrode 9930, the gate dielectric 9928, the P-turn region 9918', the interlayer oxidation region (OX), and the peripheral circuit substrate 9902 are shown in Fig. 99L2. Gate electrode 9930 is common in the six P-turn regions 9918' which form six double-sided gate-controlled floating body transistors.

As shown in FIG. 99M, a double-gate typical floating body transistor on the first Si/SiO2 layer 9922 may include a P- germanium region 9918' (acting as a floating transistor trench), and an N+ germanium region 9916. '(functioning as source and drain) and two gate electrodes 9930 (with corresponding gate dielectric 9928). The transistor can be insulated from the underside by an oxide layer 9908.

This process can form a horizontal monolithic 3D DRAM. The DRAM uses a masking process in a memory formed by transferring a wafer-sized single crystal doped germanium layer one by one. At the same time, the 3D DRAM is connected to the underlying metal layer semiconductor device.

Those of ordinary skill in the art can view the examples mentioned in Figures 99A through 99M only as a typical example and are not to scale down. Skilled people can consider more changes. For example, other types of transistors can be used, such as RCAT, or with fewer connectors. Alternatively, the doped polysilicon or other conductive material may be used for the contacts. Or a stacked memory layer can be connected to peripheral circuits above the storage stack. Alternatively, the Si/SiO2 layers 9922, 9924, and 9926 can be annealed layer by layer as long as the associated implantation process is accomplished using a laser annealing system. By reading this specification, one skilled in the art can think of how to modify other places within the scope of the present invention. Accordingly, the invention is limited only by the appended claims.

As shown in FIGS. 100A to 100L, a horizontal 3D DRAM can be constructed. After all layers have been completely transferred, this memory does not use an additional masking process in each storage layer through a common masking process. 3D DRAM is suitable for the production of 3D ICs.

As shown in FIG. 100A, a high temperature (over 400 ° C) wiring such as a tungsten wire can be used for the germanium substrate with the peripheral circuit 10002. Peripheral circuit substrate 10002 can include memory control circuitry and various circuits for other purposes, such as for analog, digital, radio frequency or storage. The peripheral circuit substrate 10002 may include peripheral circuits. This peripheral circuit can continue to operate even after additional rapid thermal annealing (RTA), maintaining good performance. For this reason, when constructing peripheral circuits, consideration should be given to selecting peripheral circuits that only need a slight RTA or no RTA to turn on the dopant. The uppermost layer of the peripheral circuit substrate 10002 can be used to bond the oxide wafer and the deposited layer of the cerium oxide 10004 to form the acceptor wafer 10014.

As shown in FIG. 100B, the single crystal germanium donor wafer 10012 can comprise a wafer sized P-doped layer (not shown), wherein the dopant concentration can be different than the P-substrate 1006. The P-doped layer can be formed by ion implantation and high thermal annealing. A mask oxide layer 10008 can be grown or deposited prior to implantation to ensure that the germanium is protected from contamination during implantation and provides an oxide layer for bonding between subsequent wafers. The layer transfer boundary plane 10010 (dashed line portion in the figure) may be formed in the donor wafer 10012 in the P-substrate 10006 or P-doped layer (not shown) by hydrogen ion implantation or other methods as described above. As described above, both the donor wafer 10012 and the acceptor wafer 10014 are used for wafer bonding and bonded together on the surface of the oxide layer 10004 and the oxide layer 10008. Since the stress is lowest at low temperatures, the bonding operation is preferably carried out at a low temperature (less than 400 ° C) or a medium temperature (not exceeding 900 ° C).

As shown in FIG. 100C, the P-layer portion (not shown) and the P-wafer substrate 10006 above the layer transfer boundary plane 10010 can be moved by cutting or grinding or by the processes described above (eg, ion cutting or other methods). Divide, thereby forming the remaining single crystal germanium P-layer 10006'. The remaining P-layer 10006' and oxide layer 10008 are layered onto the acceptor wafer 10014. The uppermost layer of the P-layer 10006' can be polished smooth and flat by chemical or mechanical means. The transistor is now fully or partially formed and aligned with the alignment mark (not shown) of the acceptor wafer 10014. Oxide layer 10020 may be deposited to provide a surface for bonding between later oxides. At this time, the first Si/SiO2 layer 10023 has been formed to include the ceria layer 10020, the P-germanium layer 10006', and the oxide layer 10008.

As shown in Fig. 100D, Si/SiO2 layers as shown in Figs. 100A to 100C may be additionally formed, such as a second Si/SiO2 layer 10025 and a third Si/SiO2 layer 10027. Oxide layer 10029 may be deposited to provide insulation from the top germanium layer.

As shown in FIG. 100E, the oxide layer 10029, the third Si/SiO2 layer 10027, the second Si/SiO2 layer 10025, and the first Si/SiO2 layer 10023 can be photolithographically and plasma/reactive ion etching. A portion of the memory wafer structure is formed. The memory wafer structure now includes a P- germanium region 10016 and an oxide layer region 10022.

As shown in FIG. 100F, the gate dielectric and gate electrode materials may be deposited, planarized by chemical-mechanical polishing (CMP), and then photolithographically and plasma/reactive ion etching may be performed to form a gate. Polar dielectric 10028. Gate dielectric 10028 may be self-aligned with gate electrode 10030 (as shown) and covered by gate electrode 10030, or may adequately cover the entire tantalum/oxide multilayer structure. The gate stack layer (including gate electrode 10030 and gate dielectric 10028) is comprised of a gate dielectric (eg, a high thermal oxide layer) and a gate electrode material (eg, polysilicon). Alternatively, the gate dielectric can be selected from atomic layer deposition (ALD) materials that match the work function of the particular gate metal, in accordance with the industry standard for high-k metal gate process solutions as previously described. In addition, the gate dielectric can be formed by rapid high thermal oxidation (RTO). Rapid high thermal oxidation is a process of low temperature oxidation deposition or low temperature microwave plasma oxidation of the tantalum surface, which can eventually be deposited as a gate electrode, such as a tungsten electrode or an aluminum electrode.

As shown in FIG. 100G, the N+ germanium region 10026 can be self-aligned with the gate electrode 10030 by a method of implanting N-type ions (eg, arsenic) into the P- germanium region 10016. The P- germanium region 10016 is not blocked by the gate electrode 10030. Thus, the remaining P-矽 region 10017 (not shown) is formed in the region where the gate electrode 10030 is blocked. Different implant energies or angles or injection ratios can be used when placing N-type ions into each of the P-turn regions 10016. The gate sidewalls (not shown) may be used in a multi-step implant process, and the gate sidewall widths used in the different stack layers may also be different to illustrate the different lateral spread of the N-type ion implant. The bottom layer (eg, 10023) may be wider than the gate sidewalls required for the top layer (eg, 10027). Similarly, angular ion implantation with substrate rotation can be used to compensate for different implant diffusions. The top implant may have a certain tilt angle that is not perpendicular to the wafer surface, and the white fungus places ions below the edge of the gate electrode 10030 to closely match the ion implantation of the lower vertical layer. Due to the higher implantation energy required to reach the bottom layer, a diffusion effect is generated, and ion implantation of the lower layer can place ions slightly below the gate electrode 10030. Rapid high thermal annealing (RTA) can be performed to fundamentally turn on the dopants in all of the memory layers 10023, 10025, and 10027 and the peripheral circuitry 10002. Alternatively, optical annealing, such as laser annealing, can be performed.

As shown in FIG. 100H, the gap-fill oxide layer 10032 can cover the entire structure and can be planarized by chemical-mechanical polishing (CMP). For the sake of clarity, the oxide layer 10032 is shown as a transparent layer. In addition to this, there is a word line region (WL) 10050, a gate electrode 10030, a source line region (SL) 10052, and an N+ germanium region 10026 as shown.

As shown in Fig. 100I, the bit line (BL) contact 10034 can be photolithographically and plasma/reactive ion etched and processed by photoresist removal. Subsequently, a metal such as copper, aluminum or tungsten may be deposited, the butt joints filled, and then etched or ground to the top of the oxide layer 10032. Each BL contact 10034 can be fully shared with all storage layers, such as the three-layer storage layer shown in FIG. 100I. Through-via vias 10060 (not shown) may be formed to electrically couple the metallized regions of BL, SL, and WL to the peripheral circuitry of the acceptor substrate 10080 through the acceptor wafer metal connection pads 10014 (not shown).

As shown in FIG. 100J, a BL metal line 10036 can be formed and connected to the associated BL contact 10034. Contacts of WL and SL and associated metal wiring (not shown) may be formed at the edge of the memory array.

A cross-sectional view of Fig. 100K is shown in Fig. 100K1, and a cross-sectional view of Fig. 100K is shown in Fig. 100K2. The BL metal line 10036, the oxide layer 10032, the BL contact 10034, the WL region 10050, the gate dielectric 10028, the N+ germanium region 10026, the P- germanium region 10017, and the peripheral circuit substrate 10002 are shown in FIG. 100K1. The BL contact 10034 is connected to one of three horizontal planes of the floating body transistor. The floating body transistor includes two N+ germanium regions 10026 for each horizontal plane and a corresponding P-turn region 10017. The BL metal line 10036, the oxide layer 10032, the gate electrode 10030, the gate dielectric 10028, the P-turn region 10017, the interlayer oxidation region (OX), and the peripheral circuit substrate 10002 are shown in FIG. 100K2. Gate electrode 10030 is common in six P-turn regions 10017 which form six double-sided gate-controlled floating body transistors.

As shown in FIG. 100M, a double-gate typical floating body transistor on the first Si/SiO2 layer 10023 may include a P- germanium region 10017 (acting as a floating transistor trench) and an N+ germanium region 10026 ( It functions as a source and a drain and two gate electrodes 10030 (with corresponding gate dielectrics 10028). The electric crystal can be insulated from the lower side by the oxide layer 10008.

This process can form a horizontal monolithic 3D DRAM. The 3D DRAM does not use a masking process in a memory formed by transferring a wafer-sized single crystal doped germanium layer one by one. At the same time, the DRAM is connected to the underlying multi-metal layer semiconductor device.

Those of ordinary skill in the art can view the examples mentioned in Figures 100A through 100L as merely exemplary examples and are not to scale down. Skilled people can consider more changes. For example, other types of transistors can be used, such as RCAT, or with fewer connectors. Alternatively, the doped polysilicon or other conductive material can be used for the contacts. Or a stacked memory layer can be connected to peripheral circuits above the storage stack. In addition, each gate of the dual gate 3D DRAM can be independently controlled to better control the memory die. By reading this specification, one skilled in the art can think of how to modify other places within the scope of the present invention. Accordingly, the invention is limited only by the appended claims.

A new monolithic 3D memory technology that utilizes material resistance variation characteristics can be used in a similar manner. There are many kinds of resistive memory, including phase change memory, metal oxide memory, resistive random memory (RRAM), memristor, solid dielectric memory, ferroelectric random memory and magnetic random memory. . For background information on these types of resistive memory, see "Technical Overview of Memory Candidate Devices for Storage Levels" (IBM Research and Development Magazine); Volume No.: 52; No. 4.5; Pages: 449-464; July 2008; author: GW, et al.). The relevant content of this document has been added to this manual for reference.

As shown in FIGS. 101A to 101K, a 3D memory can be constructed in each memory layer using a resistive no additional masking process. 3D memory is suitable for the production of 3D ICs. The 3D memory uses a junctionless transistor with a resistive memory component in series with a select transistor or access transistor.

As shown in FIG. 101A, the germanium substrate with the peripheral circuit 10102 can be made to with high temperature (about 400 ° C or more) wiring, such as tungsten wire. Peripheral circuit substrate 10102 can include memory control circuitry as well as various circuitry for other uses, such as for analog, digital, radio frequency or storage. The peripheral circuit substrate 10102 can include peripheral circuits. This peripheral circuit can continue to operate even after additional rapid thermal annealing (RTA), maintaining good performance. For this reason, when constructing peripheral circuits, consideration should be given to selecting peripheral circuits that only need a slight RTA or no RTA to turn on the dopant. The uppermost layer of the peripheral circuit substrate 10102 can be used to bond the oxide wafer and the deposited layer of the ceria 10104 to form the acceptor wafer 10114.

As shown in FIG. 101B, the single crystal germanium donor wafer 10112 can optionally include a wafer size N+ doped layer (not shown), wherein the dopant concentration can be different than the N+ substrate 10106. The N+ doped layer can be formed by ion implantation and high thermal annealing. The mask oxide layer 10108 can be grown or deposited prior to implantation to ensure that the germanium is protected from contamination during the implant process and provides an oxide layer for later bonding between the wafers. A layer transfer boundary plane 10110 (dashed line portion in the figure) may be formed in the donor wafer 10112 in the N+ substrate 10106 or the N+ doped layer (not shown) by hydrogen ion implantation or other methods as described above. As previously described, donor wafer 10112 and acceptor wafer 10114 are both used for wafer bonding and bonded together on the surface of oxide layer 10104 and oxide layer 10108. Since the stress is lowest at low temperatures, the bonding operation is preferably carried out at a low temperature (less than 400 ° C) or a medium temperature (not exceeding 900 ° C).

As shown in FIG. 101C, the N+ layer portion (not shown) and the N+ wafer substrate 10106 above the layer transfer boundary plane 10110 can be removed by cutting or sanding or a process as previously described (eg, ion cutting or other methods). Thereby, the remaining single crystal germanium N+ layer 10106 is formed. The remaining N+ layer 10106' and oxide layer 10108 are layered onto the acceptor wafer 10114. The uppermost layer of the N+ layer 10106' can be polished smooth and flat by chemical or mechanical means. The transistor is now fully or partially formed and aligned with the alignment mark (not shown) of the acceptor wafer 10114. Oxide layer 10120 may be deposited to provide a surface for bonding between later oxides. At this time, the first Si/SiO2 layer 10023 has been formed to include the hafnium oxide layer 10120, the N+ tantalum layer 10106', and the oxide layer 10108.

As shown in FIG. 101D, Si/SiO2 layers as shown in FIGS. 101A to 101C may be additionally formed, such as a second Si/SiO2 layer 10125 and a third Si/SiO2 layer 10127. Oxide layer 10129 may be deposited to provide insulation from the top N+ germanium layer.

As shown in FIG. 101E, the oxide layer 10129, the third Si/SiO2 layer 10127, the second Si/SiO2 layer 10125, and the first Si/SiO2 layer 10123 can be photolithographically and plasma/reactive ion etching. A portion of the memory wafer structure is formed. The memory wafer structure now includes an N+ germanium region 10126 and an oxide layer region 10122.

As shown in FIG. 101F, the gate dielectric and gate electrode materials may be deposited, planarized by chemical-mechanical polishing (CMP), and then photolithographically and plasma/reactive ion etching may be performed to form a gate. Polar dielectric 10128. Gate dielectric 10128 may be self-aligned with gate electrode 10130 (as shown) and covered by gate electrode 10130, or may adequately cover the entire N+ germanium region 10126 and oxide layer region 10122 multilayer structure. The gate stack layer (including gate electrode 10130 and gate dielectric 10128) is comprised of a gate dielectric (eg, a high thermal oxide layer) and a gate electrode material (eg, polysilicon). Alternatively, the gate dielectric can be selected from atomic layer deposition (ALD) materials that match the work function of the particular gate metal, in accordance with the industry standard for high-k metal gate process solutions as previously described. In addition, the gate dielectric can be formed by rapid high thermal oxidation (RTO). Rapid thermal oxidation is a process of low temperature oxidation deposition or low temperature microwave plasma oxidation of the tantalum surface, which can eventually be deposited as a gate electrode, such as a tungsten electrode or an aluminum electrode.

As shown in FIG. 101G, the gap-fill oxide layer 10132 can cover the entire structure and can be planarized by chemical-mechanical polishing (CMP). For the sake of clarity, the oxide layer 10132 is shown as a transparent layer. In addition to this, there is a word line region (WL) 10150, a gate electrode 10130, a source line region (SL) 10152, and an N+ germanium region 10126 as shown.

As shown in FIG. 101H, the bit line (BL) contact 10134 can be photolithographically and plasma/reactive ion etched through the oxide layer 10132, the three N+ germanium regions 10126, and the associated oxide vertical insulating regions to facilitate The storage layers are connected vertically. The BL contact 10134 is processed by a photoresist removal method. A resistive memory material 10138, such as hafnium oxide, may be deposited next, preferably by atomic layer deposition (ALD). The electrodes of the resistive memory component may then be deposited by ALD to form electrode/BL contacts 10134. The excess deposited material should be ground to the same surface as the top or bottom of the oxide layer 10132. Each of the BL contacts 10034 with the resistive material 10138 can be fully shared with all of the memory layers, such as the three memory layers shown in FIG. 101H.

As shown in FIG. 101I, a BL metal line 10136 can be formed and connected to the associated BL contact 10134 with a resistive material 10138. Contacts of WL and SL and associated metal wiring (not shown) may be formed at the edge of the memory array. A via via 10160 (not shown) may be formed to electrically couple the metallized regions of BL, SL, and WL to the peripheral circuitry of the acceptor substrate 10180 through the acceptor wafer metal bond pads 10114 (not shown).

A cross-sectional view of Fig. 101J is shown in Fig. 101J1, and a cross-sectional view of Fig. 101J is shown in Fig. 101J2. 101J1 shows a BL metal line 10136, an oxide layer 10132, a BL contact/electrode 10134, a resistive material 10138, a WL region 10150, a gate dielectric 10128, an N+ germanium region 10126, and a peripheral circuit substrate 10102. The BL contact/electrode 10134 is connected to one of the three horizontal planes of the resistive material 10138. The other side of the resistive material 10138 is coupled to the N+ region 10126. The BL metal line 10136, the oxide layer 10132, the gate electrode 10130, the gate dielectric 10128, the N+ germanium region 10126, the interlayer oxide region (OX), and the peripheral circuit substrate 10102 are shown in FIG. 101J2. Gate electrode 10130 is common in six N+ germanium regions 10126, which form six double-sided gate-controlled junctionless transistors for use as a memory selective transistor.

As shown in FIG. 101K, a typical double-gate junction transistor on the first Si/SiO2 layer 10123 may include an N+ germanium region 10126 (which functions as a source, a drain, and a transistor trench) and two A gate electrode 10130 (with a corresponding gate dielectric 10128). The transistor can be insulated from the underside by an oxide layer 10108.

The process can form a resistive multilayer or 3D memory array with no additional masking process for each memory layer. The memory layer uses a junctionless transistor with its resistive memory component in series with the select transistor. The memory array is constructed by layer-cutting wafer-sized doped single crystal germanium layers. At the same time, the 3D memory array is connected to the underlying metal layer semiconductor device.

Those having ordinary skill in the art can view the examples mentioned in FIGS. 101A to 101K as merely typical examples, and are not to scale down. Skilled people can consider more changes. For example, other types of transistors can be used, such as RCAT. In addition, the dopant of the N+ layer may be slightly different when compensating for the interconnect resistance. Or a stacked memory layer can be connected to peripheral circuits above the storage stack. In addition, each gate of the dual gate 3D resistive memory can be independently controlled to better control the memory die. By reading this specification, one skilled in the art can think of how to modify other places within the scope of the present invention. Accordingly, the invention is limited only by the appended claims.

As shown in FIGS. 102A to 102L, a 3D memory can be constructed in each memory layer using a resistive no additional masking process. 3D memory is suitable for the production of 3D ICs. The 3D memory uses a dual gated metal-oxide semiconductor field effect transistor (MOSFET) with a resistive memory component in series with the selected transistor.

As shown in FIG. 102A, a high temperature (over 400 ° C) wiring such as a tungsten wire can be used for the germanium substrate with the peripheral circuit 10202. Peripheral circuit substrate 10202 can include memory control circuitry and various circuits for other purposes, such as for analog, digital, radio frequency or storage. The peripheral circuit substrate 10202 can include peripheral circuits. This peripheral circuit can continue to operate even after additional rapid thermal annealing (RTA), maintaining good performance. For this reason, when constructing peripheral circuits, consideration should be given to selecting peripheral circuits that only need a slight RTA or no RTA to turn on the dopant. The uppermost layer of the peripheral circuit substrate 10202 can be used to bond the oxide wafer and the deposited layer of the ceria 10204 to form the acceptor wafer 10214.

As shown in FIG. 102B, the single crystal germanium donor wafer 10212 can comprise a wafer sized P-doped layer (not shown), wherein the dopant concentration can be different than the P-substrate 10206. The P-doped layer can be formed by ion implantation and high thermal annealing. The mask oxide layer 10208 can be grown or deposited prior to implantation to ensure that the germanium is protected from contamination during the implant process and provides an oxide layer for later bonding between the wafers. The layer transfer boundary plane 10210 (dashed line portion in the figure) may be formed in the donor wafer 10212 in the P-substrate 10206 or P-doped layer (not shown) by hydrogen ion implantation or other methods as described above. As mentioned above, both the donor wafer 10212 and the acceptor wafer 10214 are used for wafer bonding, at low temperatures (preferably below 400 ° C, where stress is lowest) or at moderate temperatures (not exceeding 900 ° C) in the oxide layer. The surface of 10204 and oxide layer 10208 are bonded together.

As shown in FIG. 102C, the P-layer portion (not shown) and the P-wafer substrate 10206 above the layer-cutting plane 10210 can be removed by cutting or sanding or a process as previously described (eg, ion cutting or other methods). Thereby, the remaining single crystal germanium P-layer 10206 is formed. The remaining P-layer 10206' and oxide layer 10208 are layered onto the acceptor wafer 10214. The uppermost layer of the P-layer 10206' can be polished smooth and flat by chemical or mechanical means. The transistor is now fully or partially formed and aligned with the alignment mark (not shown) of the acceptor wafer 10214. Oxide layer 10220 may be deposited to provide a surface for bonding between later oxides. At this time, the first Si/SiO2 layer 10223 has been formed to include the ceria layer 10220, the P-germanium layer 10206', and the oxide layer 10208.

As shown in FIG. 102D, Si/SiO2 layers as shown in FIGS. 102A to 102C may be additionally formed, such as a second Si/SiO2 layer 10225 and a third Si/SiO2 layer 10227. Oxide layer 10229 may be deposited to provide insulation from the top germanium layer.

As shown in FIG. 102E, the oxide layer 10229, the third Si/SiO2 layer 10227, the second Si/SiO2 layer 10225, and the first Si/SiO2 layer 10223 can be photolithographically and plasma/reactive ion etching. A portion of the memory wafer structure is formed. The memory wafer structure now includes a P- germanium region 10216 and an oxide layer region 10222.

As shown in FIG. 102F, the gate dielectric and gate electrode materials may be deposited, planarized by chemical-mechanical polishing (CMP), and then photolithographically and plasma/reactive ion etching may be performed to form a gate. Polar dielectric 10228. Gate dielectric 10228 may be self-aligned with gate electrode 10230 (as shown) and covered by gate electrode 10230, or may adequately cover the entire tantalum/oxide multilayer structure. The gate stack layer (including gate electrode 10230 and gate dielectric 10228) is comprised of a gate dielectric (eg, a high thermal oxide layer) and a gate electrode material (eg, polysilicon). Alternatively, the gate dielectric may be selected from atomic layer deposition (ALD) materials that match the work function of the particular gate metal, in accordance with the industry standard for high-k metal gate process solutions as previously described. In addition, the gate dielectric can be formed by rapid high thermal oxidation (RTO). Rapid thermal oxidation is a process of low temperature oxidation deposition or low temperature microwave plasma oxidation of the tantalum surface, which can eventually be deposited as a gate electrode, such as a tungsten electrode or an aluminum electrode.

As shown in FIG. 102G, the N+ germanium region 10226 can be self-aligned with the gate electrode 10230 by a method of implanting N-type ions (eg, arsenic) into the P- germanium region 10216. The P- germanium region 10216 is not blocked by the gate electrode 10230. Thus, the remaining P-turn region 10217 (not shown) is formed in the region where the gate electrode 10230 is blocked. Different implantation energies or angles or injection ratios can be employed when placing N-type ions into each of the P-germanium regions 10216. The gate sidewalls (not shown) may be used in a multi-step implant process, and the gate sidewall widths used in the different stack layers may also be different to illustrate the different lateral spread of the N-type ion implant. The bottom layer (eg, 10223) may be wider than the gate sidewalls required for the top layer (eg, 10027). Similarly, angular ion implantation with substrate rotation can be used to compensate for different implant diffusions. The top implant may have a certain tilt angle that is not perpendicular to the wafer surface, and the white fungus places ions below the edge of the gate electrode 10230 to closely match the ion implantation of the lower vertical layer. Due to the higher implantation energy required to reach the bottom layer, a diffusion effect is generated, and ion implantation of the lower layer can place ions slightly below the gate electrode 10230. Rapid high thermal annealing (RTA) can be performed to fundamentally turn on the dopants in all of the storage layers 10223, 10225, and 10227 and the peripheral circuitry 10202. Alternatively, optical annealing, such as laser annealing, can be performed.

As shown in FIG. 102H, the gap-fill oxide layer 10232 can cover the entire structure and can be planarized by chemical-mechanical polishing (CMP). For the sake of clarity, the oxide layer 10232 is shown as a transparent layer. In addition to this, there is a word line region (WL) 10250, a gate electrode 10230, a source line region (SL) 10252, and an N+ germanium region 10226 as shown.

As shown in FIG. 102I, the bit line (BL) contact 10234 can be photolithographically and plasma/reactive ion etched through the oxide layer 10232, the three N+ germanium regions 10226, and the associated oxide vertical insulating regions to fully All of the storage layers are connected vertically, followed by photoresist removal. A resistive memory material 10238, such as hafnium oxide, may be deposited next, preferably by atomic layer deposition (ALD). The electrodes of the resistive memory component may then be deposited by ALD to form electrode/BL contacts 10234. The excess deposited material should be ground to the same surface as the top or bottom of the oxide layer 10232. Each of the BL contacts 10234 with the resistive material 10238 can be fully shared with all of the memory layers, such as the three-layer memory layer shown in FIG.

As shown in FIG. 102J, a BL metal line 10236 can be formed and connected to the associated BL contact 10234 with the resistive material 10238. Contacts of WL and SL and associated metal wiring (not shown) may be formed at the edge of the memory array. A via via 10260 (not shown) may be formed to electrically couple the metallized regions of BL, SL, and WL to the peripheral circuitry of the acceptor substrate 10280 through the acceptor wafer metal bond pads 10214 (not shown).

A cross-sectional view of Fig. 102K is shown in Fig. 102K1, and a cross-sectional view of Fig. 102K is shown in Fig. 102K2. 102K1 shows BL metal line 10236, oxide layer 10232, BL contact/electrode 10234, resistive material 10238, WL region 10250, gate dielectric 10228, P-turn region 10217, N+ germanium region 10226, and peripheral circuit substrate 10202. The BL contact/electrode 10234 is connected to one of the three horizontal planes of the resistive material 10238. The other side of the resistive material 10238 is connected to the N+ germanium region 10226. As shown in Figure 102K2, P-region 10217 and corresponding N+ region 10226 on each side form the source, drain and trench of the selected transistor. The BL metal line 10236, the oxide layer 10232, the gate electrode 10230, the gate dielectric 10228, the P-turn region 10217, the interlayer oxidation region (OX), and the peripheral circuit substrate 10202 are shown in FIG. 102K2. Gate electrode 10230 is common in all six P-turn regions 10217, which control six dual gate-controlled MOSFET select transistors.

As shown in FIG. 102L, a typical dual gate-controlled MOSFET selection transistor on the first Si/SiO2 layer 10223 may include a P- germanium region 10217 (acting as a transistor trench) and an N+ germanium region 10226 (to The source and drain electrodes function) and two gate electrodes 10230 (with corresponding gate dielectrics 10228). The transistor can be insulated from the underside by an oxide layer 10208.

This process can form resistive 3D memory with no additional masking process for each storage layer. The 3D memory is constructed by layer-cutting the wafer-sized doped single crystal germanium layer. At the same time, the 3D memory is connected to the underlying metal layer semiconductor device.

Those of ordinary skill in the art can view the examples mentioned in Figures 102A through 102L as merely exemplary examples and are not to scale down. Skilled people can consider more changes. For example, other types of transistors can be used, such as RCAT. The MOSFET select component utilizes slightly doped drain and halo implants in trench engineering. Alternatively, the doped polysilicon or other conductive material can be used for the contacts. Or a stacked memory layer can be connected to peripheral circuits above the storage stack. In addition, each gate of the dual gate 3D DRAM can be independently controlled to better control the memory die. By reading this specification, one skilled in the art can think of how to modify other places within the scope of the present invention. Accordingly, the invention is limited only by the appended claims.

As shown in FIGS. 103A to 103M, an additional masking process 3D memory can be constructed in each storage layer using electrical resistance. 3D memory is suitable for the production of 3D ICs. The 3D memory uses a dual gated MOSFET to select the transistor and has a resistive memory component in series with the selected transistor.

As shown in FIG. 103A, the germanium substrate with the peripheral circuit 10302 can use high temperature (over 400 ° C) wiring, such as tungsten wire. Peripheral circuit substrate 10302 can include memory control circuitry and various circuits for other uses, such as for analog, digital, radio frequency, or memory. Peripheral circuit substrate 10302 can include circuitry. This circuit can continue to operate even after additional rapid thermal annealing (RTA), maintaining good performance. For this reason, when constructing peripheral circuits, consideration should be given to selecting peripheral circuits that only need a slight RTA or no RTA to turn on the dopant. The uppermost layer of the peripheral circuit substrate 10302 can be used to bond the oxide wafer and the deposited layer of the ceria 10304 to form the acceptor wafer 2414.

As shown in FIG. 103B, the single crystal germanium donor wafer 10312 can comprise a wafer sized P-doped layer (not shown), wherein the dopant concentration can be different than the P-substrate 10306. The P-doped layer can be formed by ion implantation and high thermal annealing. The mask oxide layer 10308 can be grown or deposited prior to implantation to ensure that the germanium is protected from contamination during the implant and provides an oxide layer for later bonding between the wafers. A layer transfer boundary plane 10306 (dashed line portion in the figure) may be formed in the donor wafer 10312 in the P-substrate 10310 or P-doped layer (not shown) by hydrogen ion implantation or other methods as described above. As mentioned above, both the donor wafer 10312 and the acceptor wafer 10314 are used for wafer bonding, at low temperatures (preferably below 400 ° C, where stress is lowest) or at moderate temperatures (not exceeding 900 ° C) in the oxide layer. The surface of 10304 and oxide layer 10308 are bonded together.

As shown in FIG. 103C, the P-layer portion (not shown) and the P-wafer substrate 10306 above the layer-cutting plane 10310 can be moved by cutting or sanding or a process as previously described (eg, ion cutting or other methods). Divide, thereby forming the remaining single crystal germanium P-layer 10306. The remaining P-layer 10306' and oxide layer 10308 are layered onto the acceptor wafer 10314. The uppermost layer of the P-layer 10306' can be polished smooth and flat by chemical or mechanical means. The transistor is now fully or partially formed and aligned with the alignment mark (not shown) of the acceptor wafer 10314.

As shown in FIG. 103D, the N+ germanium region 10316 can be photolithographically implanted and the remaining P- germanium regions 10318 can be formed.

As shown in Fig. 103E, an oxide layer 10320 may be deposited to prepare the necessary surface for the adhesion between the later oxide and oxide, thus forming a first Si/SiO2 layer 10323. The Si/SiO2 layer includes a ceria layer 10320, an N+ germanium region 10316, and a P-germanium region 10318.

As shown in Fig. 103F, Si/SiO2 layers as shown in Figs. 103A to 103E may be additionally formed, such as a second Si/SiO2 layer 10325 and a third Si/SiO2 layer 10327. Oxide layer 10329 may be deposited. After all of the intended storage layers are built, rapid high thermal annealing (RTA) can be performed to fundamentally turn on all of the storage layers 10323, 10325, and 10327 and the dopants in the peripheral circuitry 10302. Alternatively, optical annealing, such as laser annealing, can be performed.

As shown in FIG. 103G, the oxide layer 10329, the third Si/SiO2 layer 10327, the second Si/SiO2 layer 10325, and the first Si/SiO2 layer 10323 can be photolithographically and plasma/reactive ion etching. A portion of the memory wafer structure is formed. The etch may form a P-turn region 10318' (which forms a transistor trench) and an N+ germanium region 10316' (forming source, drain, and local source lines).

As shown in FIG. 103H, the gate dielectric and gate electrode materials may be deposited, planarized by chemical-mechanical polishing (CMP), and then photolithographically and plasma/reactive ion etching may be performed to form a gate. Polar dielectric 10328. Gate dielectric 10328 may be self-aligned with gate electrode 10330 (as shown) and covered by gate electrode 10330, or may adequately cover the entire tantalum/oxide multilayer structure. The size and alignment of the gate stack layers of the gate electrode 10330 and the gate dielectric 10328 should ensure that the P- germanium regions 10318' are sufficiently and completely covered. The gate stack layer (including gate electrode 10330 and gate dielectric 10328) is comprised of a gate dielectric (eg, a high thermal oxide layer) and a gate electrode material (eg, polysilicon). Alternatively, the gate dielectric can be selected from atomic layer deposition (ALD) materials that match the work function of the particular gate metal, in accordance with the industry standard for high-k metal gate process solutions as previously described. In addition, the gate dielectric can be formed by rapid high thermal oxidation (RTO). Rapid high thermal oxidation is a process of low temperature oxidation deposition or low temperature microwave plasma oxidation of the tantalum surface, which can eventually be deposited as a gate electrode, such as a tungsten electrode or an aluminum electrode.

As shown in FIG. 103I, the gap-fill oxide layer 10332 can cover the entire structure and can be planarized by chemical-mechanical polishing (CMP). For the sake of clarity, the oxide layer 10332 is shown as a transparent layer. In addition to this, there is a word line region (WL) 10350, a gate electrode 10330, a source line region (SL) 10352, and an N+ germanium region 10316 as shown.

As shown in FIG. 103J, the bit line (BL) contact 10334 can be photolithographically and plasma/reactive ion etched through the oxide layer 10332, the three N+ germanium regions 10316', and the associated oxide vertical insulating regions to All storage layers are connected vertically. The BL contact 10334 is processed by a photoresist removal method. A resistive memory material 10338, such as hafnium oxide, may be deposited next, preferably by atomic layer deposition (ALD). The electrodes of the resistive memory component may then be deposited by ALD to form electrode/BL contacts 10334. The excess deposited material should be ground to the same surface as the top or bottom of the oxide layer 10332. Each of the BL contacts/electrodes 10334 with resistive material 10338 can be sufficiently shared with all of the memory layers, such as the three-layer memory layer shown in FIG. 103J.

As shown in FIG. 103K, a BL metal line 10336 can be formed and connected to the associated BL contact 10334 with the resistive material 10338. Contacts of WL and SL and associated metal wiring (not shown) may be formed at the edge of the memory array. A via via 10360 (not shown) may be formed to electrically couple the metallized regions of BL, SL, and WL to the peripheral circuitry of the acceptor substrate 10314 through the acceptor wafer metal bond pads 10380 (not shown).

A cross-sectional view of Fig. 103L is shown in Fig. 103L1, and a cross-sectional view of Fig. 103L is shown in Fig. 103L2. 103L2 shows a BL metal line 10336, an oxide layer 10332, a BL contact/electrode 10334, a resistive material 10338, a WL region 10350, a gate dielectric 10328, a P-turn region 10318', an N+ germanium region 10316', and a peripheral circuit substrate. 10302. The BL contact/electrode 10334 is connected to one of the three horizontal planes of the resistive material 10338. The other side of the resistive material 10338 is connected to the N+ germanium region 10316'. As shown in Fig. 103L2, the P-region 1018' and the corresponding N+ region 10316' on each side form the source, drain and trench of the selective transistor. The BL metal line 10336, the oxide layer 10332, the gate electrode 10330, the gate dielectric 10328, the P-turn region 10318', the interlayer oxidation region (OX), and the peripheral circuit substrate 10302 are shown in Fig. 103L2. Gate electrode 10330 is common in all six P-turn regions 10318', which control six dual gate-controlled MOSFET select transistors.

As shown in FIG. 103L, a typical dual gate-controlled MOSFET selection transistor on the first Si/SiO2 layer 10323 may include a P- germanium region 10318 (acting as a transistor trench) and an N+ germanium region 10316 (to The source and drain electrodes act) and two gate electrodes 10330 (with corresponding gate dielectric 10328). The transistor can be insulated from the underside by an oxide layer 10308.

This process can form resistive 3D memories, each using an additional masking process. A resistive 3D memory is constructed by layer-cutting a wafer-sized doped single crystal germanium layer. At the same time, the 3D memory is connected to the underlying metal layer semiconductor device.

Those of ordinary skill in the art can view the examples mentioned in Figures 103A through 103M only as a typical example and are not to scale down. Skilled people can consider more changes. For example, other types of transistors can be used, such as RCAT. Alternatively, the doped polysilicon or other conductive material can be used for the contacts. Or a stacked memory layer can be connected to peripheral circuits above the storage stack. Alternatively, the Si/SiO2 layers 10322, 10324, and 10326 may be annealed layer by layer as long as the associated implantation process is accomplished using a laser annealing system. By reading this specification, one skilled in the art can think of how to modify other places within the scope of the present invention. Accordingly, the invention is limited only by the appended claims.

As shown in Figures 104A through 104F, two additional masking resistive 3D memories can be constructed in each memory layer. 3D memory is suitable for the production of 3D ICs. The 3D memory uses a single-gate MOSFET to select the transistor and has a resistive memory component in series with the selected transistor.

As shown in FIG. 104A, the P-substrate donor wafer 10400 is processed to include a wafer-sized P-doped layer 10404. The dopant concentration of the P-doped layer 10404 may be the same as or different from the P-substrate 10400. The P-doped layer 10404 can be formed by ion implantation and high thermal annealing. The mask oxide layer 10401 can be grown prior to implantation to ensure that the germanium is protected from contamination during implantation and to provide an oxide layer for bonding between subsequent wafers.

As shown in FIG. 104B, the top layer of the donor wafer 10400 can be used to bond the oxide wafer to the deposited layer of the oxide layer 10402, or through the high thermal oxidation of the P-layer 10404, or the secondary oxidation of the implant oxide layer 10401. An oxide layer 10402 is formed. A layer transfer boundary plane 10499 (dashed line portion in the figure) can be formed in donor wafer 10400 or P-layer 10404 (as shown) by hydrogen ion implantation 10407 or other methods as previously described. As described above, both the donor wafer 10400 and the acceptor wafer 10410 can be used as a bond between the wafers, and then the two are bonded together. The above bonding is preferably carried out at a low temperature (not exceeding 400 ° C) to control the stress to a minimum level. The P-layer portion and the P-donor wafer substrate 10400 above the layer transfer boundary plane 10499 can be removed by cutting or sanding or a process as previously described (eg, ion cutting or other methods).

As shown in FIG. 104C, the remaining P-doped 10404' and oxide layer 10402 have been layered onto the acceptor wafer 10410. The acceptor wafer 10410 can include circuitry. This circuit can continue to operate even after additional rapid high thermal annealing (RTA) to maintain good performance. For this reason, when constructing peripheral circuits, consideration should be given to selecting peripheral circuits that only need a slight RTA or no RTA to turn on the dopant. In addition, the peripheral circuit may use a refractory metal such as tungsten having a high temperature resistance of more than 400 °C. The uppermost layer of the P-doped layer 10404' can be polished smooth and flat by chemical or mechanical means. The transistor is now formed and aligned with the alignment mark (not shown) of the acceptor wafer 10410.

As shown in FIG. 104D, a shallow trench insulating layer (STI) oxide region (not shown) can be photolithographically and plasma/reactive ion etched until the top layer of the oxide layer 10402, thereby removing the P-single layer region. 10404. The gap-fill oxide layer may be deposited and planarized by chemical-mechanical polishing (CMP) to form a conventional STI oxide region and a P-doped single crystal germanium region (not shown) to form a transistor. It is also possible to perform the threshold adjustment injection simultaneously or not. The gate stack layer is composed of a gate dielectric (eg, a high thermal oxide layer) and a gate electrode material (eg, polysilicon). Alternatively, the gate oxide layer may select an atomic layer deposition (ALD) gate dielectric that matches the work function of the particular gate metal, in accordance with the industry standard for the high-k metal gate process scheme described above. In addition, the gate oxide region can be formed by rapid high thermal oxidation (RTO). Rapid thermal oxidation is a process of low temperature oxidation deposition or low temperature microwave plasma oxidation of the tantalum surface that can ultimately be deposited into a gate material such as tungsten or aluminum. At this point, the gate stack layer self-aligned LDD (lightly doped drain) and halo breakdown implant can be performed to adjust the breakdown characteristics of the joint and the transistor. Conventional gate sidewall deposition of oxides and nitrides can be performed and then etched back to form implanted gate sidewalls (not shown) on gate stack layer 10424. Self-aligned N+ source and drain implants can then be performed to produce the transistor source and drain 10420 and the remaining P-矽 NMOS (N-channel metal-oxide-semiconductor) transistor trenches 10428. At this time, it is necessary to turn on the implanted ions, set the initial joint depth, and perform high temperature annealing. Finally, the gap-fill oxide layer 10450 can cover the entire structure and can be planarized by chemical-mechanical polishing (CMP). As mentioned earlier, the oxidized surface can be used for bonding between the oxide and the oxidized wafer.

As shown in FIG. 104E, repeating the transistor layer formation depicted in FIGS. 104A-104D, bonding the acceptor wafer 10410 to the oxide layer 10450, and subsequent transistor formation processes, a second layer 10430 of memory transistors can be formed. After all of the intended storage layers are built, rapid high thermal annealing (RTA) can be performed to fundamentally turn on all of the storage layers and dopants in the peripheral circuitry of the acceptor substrate 10410. Alternatively, optical annealing, such as laser annealing, can be performed.

As shown in FIG. 104F, contacts and metal wiring can be formed by photolithography and plasma/reactive ion etching. The bit line (BL) contact 10440 is electrically coupled to the memory layer transistor N+ region on the transistor drain side 10454, and the source line contact 10442 and the storage layer transistor on the transistor source side 10452. The N+ region is electrically coupled. Bit line (BL) wiring 10448 and source line (SL) wiring 10446 are electrically coupled to bit line 10440 and source line contact 10442, respectively. A gate stack layer, such as 10434, can be connected to contacts and metallization regions (not shown) to form a word line region (WL). A via via 10460 (not shown) may be formed to electrically couple the metallized regions of BL, SL, and WL to the peripheral circuitry of the acceptor substrate 10410 through the acceptor wafer metal connection pads 1980 (not shown).

As shown in FIG. 104F, the source line (SL) contact 10434 can perform photolithography and plasma/reactive ion etching through the oxide layer 10450, the N+ germanium region 10420, and the associated oxide vertical insulating region of each of the memory layers. To connect vertically to all storage layers. The SL contacts can be processed by means of photoresist removal. A resistive memory material 10442, such as hafnium oxide, may be deposited next, preferably by atomic layer deposition (ALD). The electrodes of the resistive memory component may then be deposited by ALD to form SL electrodes/contacts 10434. The excess deposited material should be ground to the same surface as the top or bottom of the oxide layer 10450. Each of the SL contacts/electrodes 10434 with resistive material 10442 can be sufficiently shared with all of the memory layers, such as the three-layer memory layer shown in FIG. The SL contact 10434 is electrically coupled to the storage layer transistor N+ region on the transistor source side 10452. SL metal line 10446 can be formed and bonded to associated SL contact 10434 using resistive material 10442. Oxide layer 10452 may be deposited and planarized. A bit line (BL) contact 10440 can be photolithographically and plasma/reactive ion etched through the oxide layer 10450, the N+ germanium region 10420, and the associated oxide layer vertical insulating region of each of the memory layers to fully and fully The storage layer is connected vertically. The BL contact 10440 is processed by a photoresist removal method. The BL contact 10440 is electrically coupled to the storage layer transistor N+ region on the transistor drain side 10454. A BL metal line 10448 can be formed and connected to the associated BL contact 10440. A gate stack layer, such as 10424, can be coupled to contacts and metallization regions (not shown) to form a word line region (WL). A via via 10460 (not shown) may be formed to electrically couple the metallized regions of BL, SL, and WL to the peripheral circuitry of the acceptor substrate 10410 through the acceptor wafer metal bond pads 10480 (not shown).

This process can form resistive 3D memory with two additional masking steps for each memory layer. The 3D memory is constructed by layer-cutting the wafer-sized doped single crystal germanium layer. At the same time, the 3D memory is connected to the underlying metal layer semiconductor device.

Those of ordinary skill in the art can view the examples mentioned in Figures 104A through 104F as merely exemplary examples and are not to scale down. Skilled people can consider more changes. For example, other types of transistors can be used, such as PMOS (P-channel metal oxide semiconductor) or RCAT. Or a stacked memory layer can be connected to peripheral circuits above the storage stack. In addition, each storage layer can be configured with a slightly different donor wafer P-layer doping profile. In addition, the memory can be arranged in different ways, such as BL and SL interchange, or where the wiring is buried, the wiring of the memory array can be placed under the storage layer and above the peripheral circuit. By reading this specification, one skilled in the art can think of how to modify other places within the scope of the present invention. Accordingly, the invention is limited only by the appended claims.

Charge trapping NAND (anti-gate) memory devices are another common commercial non-volatile memory. A charge trapping device stores its charge in a charge trapping layer. The charge trapping layer in turn affects the transistor trench. BACKGROUND trap type of memory available information about charge "3D interconnect nanoelectronic systems integration" (Al Tektronix Press; 2009; OF: Bakir and Meindl- hereinafter abbreviated Bakir), "using a junction-type buried trench the height of the channel bE-SONOS device 8 scalable 3D vertical gate layer (VG) TFT NAND flash memory "(VLSI symposium related technologies; 2010; OF: Hang-Ting Lue, etc.) and" flash memory Overview "(Proc.IEEE91; pp. 489-502 (2003); author: Bez, etc.). The equipment described by Bakir uses selective crystal growth, laser recrystallization or polycrystalline germanium to form transistor trenches, resulting in less than ideal transistor performance. The structure shown in Figures 105 and 106 is used for any of the charge trapping memories.

As shown in Figures 105A through 104G, two additional masking process charge trapping type 3D memories can be constructed in each memory layer. 3D memory is suitable for the production of 3D ICs. The 3D memory uses a NAND string of charge trapping type transistors built in a single crystal germanium.

As shown in FIG. 105A, the P-substrate donor wafer 10500 is processed to include a wafer-sized P-doped layer 10504. The dopant concentration of the P-doped layer 10504 may be the same as or different from the P-substrate 10500. P-doped layer 10504 may have a vertical doping gradient. The P-doped layer 10504 can be formed by ion implantation and high thermal annealing. The mask oxide layer 10501 can be grown prior to implantation to ensure that the germanium is protected from contamination during the implant process and provides an oxide layer for later bonding between the wafers.

As shown in FIG. 105B, the top layer of the donor wafer 10500 can be used to bond the oxide wafer to the deposited layer of the oxide layer 10502, or to the high thermal oxidation of the P-doped layer 10504, or to the mask oxide layer 10501. The secondary oxidation forms an oxide layer 10502. A layer transfer boundary plane 10599 (dashed line portion in the figure) may be formed in donor wafer 10500 or P-layer 10504 (as shown) by hydrogen ion implantation 10507 or other methods as previously described. As described above, both the donor wafer 10500 and the acceptor wafer 10510 can be used as a bond between the wafers, and then the two are bonded together. The above bonding is preferably carried out at a low temperature (not exceeding 400 ° C) to control the stress to a minimum level. The P-layer portion 10504 and the P-donor wafer substrate 10500 above the layer transfer boundary plane 10599 can be removed by cutting or sanding or a process as previously described (eg, ion cutting or other methods).

As shown in FIG. 105C, the remaining P-doped 10504' and oxide layer 10502 have been layered onto the acceptor wafer 10510. The acceptor wafer 10510 can include circuitry. This circuit can continue to operate even after additional rapid thermal annealing (RTA), maintaining good performance. For this reason, when constructing peripheral circuits, consideration should be given to selecting peripheral circuits that only need a slight RTA or no RTA to turn on the dopant. In addition, the peripheral circuit may use a refractory metal such as tungsten having a high temperature resistance of more than 400 °C. The uppermost layer of the P-doped layer 10504' can be polished smooth and flat by chemical or mechanical means. The transistor is now formed and aligned with the alignment mark (not shown) of the acceptor wafer 10510.

As shown in FIG. 105D, a shallow trench insulating layer (STI) oxide region (not shown) can be photolithographically and plasma/reactive ion etched until the top layer of the oxide layer 10502, thereby removing the P-single layer region. 10504' and form a P-doped region 10520. The gap-fill oxide layer may be deposited and planarized by chemical-mechanical polishing (CMP) to form a conventional STI oxide region and a P-doped single crystal germanium region (not shown) to form a transistor. It is also possible to perform the threshold adjustment injection simultaneously or not. Deposition by growth or charge trapping gate dielectric 10522 (eg, high thermal oxide layer and tantalum nitride layer - ONO: oxide-nitride-oxide) and gate metal material 10524 (eg, doped or undoped polysilicon) A gate stack layer can be formed. Likewise, the charge trapping gate dielectric can comprise germanium or III-V nanocrystals encapsulated in an oxide.

As shown in FIG. 105E, the gate stack layer 10528 can be photolithographically and plasma/reactive ion etched to remove the gate metal material region 10524 and the charge trapping gate dielectric 10522. Self-aligned N+ source and drain implants can be performed to form inter-anode source and drain 10534 and NAND string source and drain end 10530. Finally, the gap-fill oxide layer 10550 and the oxide layer can cover the entire structure and can be planarized by chemical-mechanical polishing (CMP). As mentioned earlier, the oxidized surface can be used for bonding between the oxide and the oxidized wafer. A first layer of storage transistor 10542 has been formed, comprising a ruthenium dioxide layer 10550, a gate stack layer 10528, an inter-anode source and drain 10534, a NAND string source and gate terminal 10530, a P-矽 region 10520, and Oxide layer 10502.

As shown in FIG. 105F, repeating the transistor layer formation described in FIGS. 105A through 105D, bonding the acceptor wafer 10510 to the oxide layer 10550, and subsequent transistor formation processes, a memory can be formed on top of the first layer of the storage transistor 10542. The second layer of body transistor 10544. After all of the intended storage layers are built, rapid high thermal annealing (RTA) can be performed to fundamentally turn on all of the storage layers and dopants in the peripheral circuitry of the acceptor substrate 10510. Alternatively, optical annealing, such as laser annealing, can be performed.

As shown in FIG. 105G, source line (SL) contact 10548 and bit line contact 10549 can pass through oxide layer 10550, NAND string source and drain terminal 10530, P-region 10520 and associated oxidation of each memory layer. The vertical insulating regions of the layer are photolithographically and plasma/reactive ion etched to be vertically connected to all of the storage layers. The SL ground contacts and bit line contacts can then be processed by photoresist removal. The contacts and metallization regions can be filled with metal or heavily doped polysilicon to form BL and SL wiring regions (not shown). A gate stack layer, such as 10528, can be connected to the contacts and metallization regions to form a word line region (WL) and a WL wiring region (not shown). Through-via vias 10560 (not shown) may be formed to electrically couple the metallized regions of BL, SL, and WL to the peripheral circuitry of the acceptor substrate 10510 through the acceptor wafer metal bond pads 10580 (not shown).

This process can form charge trapping 3D memory with two additional masking steps for each storage layer. The 3D memory is constructed by layer-cutting the wafer-sized doped single crystal germanium layer. At the same time, the 3D memory is connected to the underlying metal layer semiconductor device.

Those of ordinary skill in the art can view the examples mentioned in Figures 105A through 105G only as a typical example and are not to scale down. More skilled people can consider more changes, for example, through the process of building BL or SL to select the transistor. Or a stacked memory layer can be connected to peripheral circuits above the storage stack. In addition, each storage layer can be configured with a slightly different donor wafer P-layer doping profile. In addition, the memory can be arranged in different ways, such as BL and SL interchange, or modify these structures into NOR flash memory storage format, or where the wiring is buried, the wiring of the memory array can be placed under the storage layer and around Above the circuit. In addition, the pre-layered charge trapping insulating layer and the gate layer may be deposited and temporarily bonded to the carrier or wafer holder or substrate and then transferred to the acceptor substrate using peripheral circuitry. By reading this specification, one skilled in the art can think of how to modify other places within the scope of the present invention. Accordingly, the invention is limited only by the appended claims.

As shown in Figures 106A through 106G, a charge trapping type 3D memory can be constructed in each memory layer without an additional masking process. 3D memory is suitable for the production of 3D ICs. The 3D memory uses a charge-capture type NAND string of a junctionless transistor with a junctionless selective transistor built in a single crystal germanium.

As shown in FIG. 106A, the germanium substrate with the peripheral circuit 10602 can use high temperature (over 400 ° C) wiring, such as tungsten wire. Peripheral circuit substrate 10602 can include memory control circuitry as well as various circuits for other uses, such as for analog, digital, radio frequency or storage. The peripheral circuit substrate 10602 can include peripheral circuits. This peripheral circuit can continue to operate even after additional rapid thermal annealing (RTA), maintaining good performance. For this reason, when constructing peripheral circuits, consider selecting peripheral circuits that only need a slight RTA or no RTA to turn on the dopant. The uppermost layer of peripheral circuit substrate 10602 can be used to bond the oxide wafer and the deposited layer of ceria 10604 to form acceptor wafer 10614.

As shown in FIG. 106B, the single crystal germanium donor wafer 10612 can comprise a wafer size N+ doped layer (not shown), wherein the dopant concentration can be different than the N+ substrate 10606. The N+ doped layer can be formed by ion implantation and high thermal annealing. The mask oxide layer 10608 can be grown or deposited prior to implantation to ensure that the germanium is protected from contamination during implantation and provides an oxide layer for bonding between subsequent wafers. A layer transfer boundary plane 10610 (dashed line portion in the figure) may be formed in the donor wafer 10612 in the N+ substrate 10606 or the N+ doped layer (not shown) by hydrogen ion implantation or other methods as described above. As previously described, donor wafer 10612 and acceptor wafer 10614 are both used for wafer bonding and bonded together on the surface of oxide layer 10604 and oxide layer 10608. Since the stress is lowest at low temperatures, the bonding operation is preferably carried out at a low temperature (less than 400 ° C) or a medium temperature (not exceeding 900 ° C).

As shown in FIG. 106C, the N+ layer portion (not shown) and the N+ wafer substrate 10606 above the layer transfer boundary plane 10610 can be removed by cutting or sanding or a process as previously described (eg, ion cutting or other methods), thereby The remaining single crystal germanium N+ layer 10606 is formed. The remaining N+ layer 10606' and oxide layer 10608 are layered onto the acceptor wafer 10614. The uppermost layer of the N+ layer 10606' can be polished smooth and flat by chemical or mechanical means. Oxide layer 10620 may be deposited to provide a surface for bonding between later oxides. At this time, a first Si/SiO2 layer 10623 has been formed, including a hafnium oxide layer 10620, an N+ tantalum layer 10606', and an oxide layer 10608.

As shown in FIG. 106D, Si/SiO2 layers as shown in FIGS. 106A to 106C may be additionally formed, such as a second Si/SiO2 layer 10625 and a third Si/SiO2 layer 10627. Oxide layer 10629 may be deposited to provide insulation from the top N+ germanium layer.

As shown in FIG. 106E, the oxide layer 10629, the third Si/SiO2 layer 10627, the second Si/SiO2 layer 10625, and the first Si/SiO2 layer 10623 can be photolithographically and plasma/reactive ion etching. A portion of the memory wafer structure is formed. The memory wafer structure now includes an N+ germanium region 10626 and an oxide layer region 10622.

As shown in FIG. 106F, a charge trapping type gate dielectric (eg, a high thermal oxide layer and a tantalum nitride layer-ONO: oxide-nitride-oxide) and a gate metal electrode layer (eg, doped or absent) are grown or precipitated. Doped polysilicon) can form a gate stack layer. The gate metal electrode layer can then be planarized by chemical-mechanical polishing (CMP). Likewise, the charge trapping gate dielectric can comprise germanium or III-V nanocrystals encapsulated in an oxide. Select gate region 10638 can comprise a non-charge trapping insulating layer. The NAND string region 10636 and the gate metal electrode region 10630 and the gate dielectric region 10628 of the select transistor region 10638 can be photolithographically and plasma/reactive ion etched.

As shown in FIG. 106G, the gap-fill oxide layer 10632 can cover the entire structure and can be planarized by chemical-mechanical polishing (CMP). For the sake of clarity, the oxide layer 10632 is shown as a transparent layer. A select metal line 10646 can be formed and coupled to the associated select gate contact 10634. Contacts of WL and SL and associated metal wiring (not shown) may be formed at the edge of the memory array. Text line region (WL) 10636, gate electrode 10630, and bit line region (BL) 10652, including the illustrated N+ 矽 region 10626 are shown. Source region 10644 can be formed by contact etch and fill to bond with the N+ germanium region at the source end of NAND string 10636. A via via 10660 (not shown) may be formed to electrically couple the metallized regions of BL, SL, and WL to the peripheral circuitry of the acceptor substrate 10614 through the acceptor wafer metal bond pads 10680 (not shown).

This process can form charge trapping 3D memory with no additional masking process for each storage layer. The 3D memory is constructed by layer-cutting the wafer-sized doped single crystal germanium layer. At the same time, the 3D memory is connected to the underlying metal layer semiconductor device.

Those of ordinary skill in the art can view the examples mentioned in Figures 106A through 106G as merely exemplary examples and are not to scale. Skilled people can consider more changes, for example, the BL or SL contacts can be built using the ladder method described in the previous section. Or a stacked memory layer can be connected to peripheral circuits above the storage stack. In addition, each storage layer can be configured with a slightly different donor wafer N+ layer doping profile. In addition, the memory can be arranged in different ways, such as BL and SL interchange, or where the wiring is buried, the wiring of the memory array can be placed under the storage layer and above the peripheral circuit. Other types of 3D charge trapping memory can be built by single crystal germanium layer cutting, for example, in a highly scalable 8-layer 3D vertical gate (VG) using a junctionless buried channel BE-SONOS device. TFTNAND flash memory "(VLSI symposium related technologies; 2010; OF: Hang-Ting Lue, etc.) and" an overcomes terabit memory bit density of the multilayer stack restriction vertical gate NAND flash memory. " (VLSI symposium related technologies; 2009; author: W.Kim, S.Choi, etc.) mentioned it in memory. By reading this specification, one skilled in the art can think of how to modify other places within the scope of the present invention. Accordingly, the invention is limited only by the appended claims.

Floating gate (FG) storage devices are another common commercial non-volatile memory. The floating gate device stores its charge in a conductive gate (FG) that is nominally insulated from the unintentional electric field. In these electric fields, the charge on the FG adversely affects the trenches of the transistor. Quick background about the memory of the floating gate information can be found in "Flash Memory Overview" (Proc.IEEE91; pp. 489-502 (2003); Author: R.Bez, etc.). The structure shown in Figures 107 and 108 is used for any type of floating gate memory.

As shown in Figures 107A through 104G, two additional masking process floating gate 3D memories can be constructed in each memory layer. 3D memory is suitable for the production of 3D ICs. The 3D memory uses a NAND string of floating gate transistors built in a single crystal germanium.

As shown in FIG. 107A, the P-substrate donor wafer 10700 can be processed to include a wafer-sized P-doped layer 10704. The dopant concentration of the P-doped layer 10704 may be the same as or different from the P-substrate 10700. P-doped layer 10704 may have a vertical doping gradient. The P-doped layer 10704 can be formed by ion implantation and high thermal annealing. The mask oxide layer 10701 can be grown prior to implantation to ensure that the germanium is protected from contamination during the implant process and provides an oxide layer for later bonding between the wafers.

As shown in FIG. 107B, the top layer of the donor wafer 10700 can be used to bond the oxide wafer and the deposited layer of the oxide layer 10702, or through the high thermal oxidation of the P-doped layer 10704, or into the mask oxide layer 10701. The secondary oxidation forms an oxide layer 10702. A layer transfer boundary plane 10799 (dashed line portion in the figure) can be formed in donor wafer 10700 or P-layer 10704 (as shown) by hydrogen ion implantation 10707 or other methods as previously described. As described above, both the donor wafer 10700 and the acceptor wafer 10710 can be used as a bond between the wafers, and then the two are bonded together. The above bonding is preferably carried out at a low temperature (not exceeding 400 ° C) to control the stress to a minimum level. The P-layer portion 10704 and the P-donor wafer substrate 10700 above the layer-cutting plane 10799 can be removed by cutting or sanding or a process as previously described (eg, ion cutting or other methods).

As shown in Figure 107C, the remaining P-doped 10704' and oxide layer 10702 have been layered onto the acceptor wafer 10710. The acceptor wafer 10710 can include circuitry. This circuit can continue to operate even after additional rapid thermal annealing (RTA), maintaining good performance. For this reason, when constructing peripheral circuits, consideration should be given to selecting peripheral circuits that only need a slight RTA or no RTA to turn on the dopant. In addition, the peripheral circuit may use a refractory metal such as tungsten having a high temperature resistance of more than 400 °C. The uppermost layer of the P-doped layer 10704' can be polished smooth and flat by chemical or mechanical means. The transistor is now formed and aligned with the alignment mark (not shown) of the acceptor wafer 10710.

As shown in FIG. 107D, a partial gate stack layer may be formed by growing or depositing a tunnel oxide layer 10722 (eg, a high thermal oxide layer) and an FG gate metal material 10724 (eg, doped or undoped polysilicon). Likewise, the charge trapping gate dielectric can comprise germanium or III-V nanocrystals encapsulated in an oxide. A shallow trench insulating layer (STI) oxide region (not shown) can be photolithographically and plasma/reactive ion etched until the top layer of oxide layer 10702, thereby removing P-single germanium layer region 10704 and forming P- Doped region 10720. The gap-fill oxide layer may be deposited and planarized by chemical-mechanical polishing (CMP) to form a conventional STI oxide region (not shown).

As shown in FIG. 107E, a polysilicon oxide layer 10725 (eg, a hafnium oxide layer and a tantalum nitride layer-ONO: oxide-nitride-oxide) and a control gate (CG) gate metal material 10726 (eg, doped or Undoped polysilicon) may be deposited. The gate stack layer 10728 can be photolithographically and plasma/reactive ion etched to remove the CG gate metal material region 10726, the polysilicon oxide layer 10725, the FG gate metal material 10724, and the tunnel oxide layer 10722. The removal operation can form a gate stack layer 10728 comprising a CG gate metal region 10726, a polysilicon oxide region 10725, an FG gate metal region 10724, and a tunnel oxide region 10722. For the sake of clarity, only one gate stack layer 10728 is labeled in the area layer line. Self-aligned N+ source and drain implants can be performed to form inter-anode source and drain 10734 and NAND string source and drain terminals 10730. Finally, the gap-fill oxide layer 10750 can cover the entire structure and can be planarized by chemical-mechanical polishing (CMP). As mentioned earlier, the oxidized surface can be used for bonding between the oxide and the oxidized wafer. A first layer of storage transistor 10742 has been formed, comprising a ruthenium dioxide layer 10750, a gate stack layer 10728, an inter-anode source and drain 10734, a NAND string source and gate terminal 10730, a P-矽 region 10720, and Oxide layer 10702.

As shown in FIG. 107F, repeating the transistor layer formation described in FIGS. 107A through 107D, bonding the acceptor wafer 10710 to the oxide layer 10750, and subsequent transistor formation processes, a memory can be formed on top of the first layer of the storage transistor 10742. The second layer of body transistor 10744. After all of the intended storage layers are built, rapid high thermal annealing (RTA) can be performed to fundamentally turn on all of the storage layers and dopants in the peripheral circuitry of the acceptor substrate 10710. Alternatively, optical annealing, such as laser annealing, can be performed.

As shown in FIG. 107G, the source line (SL) ground contact 10748 and the bit line contact 10749 can pass through the oxide layer 10750 of each memory layer, the NAND string source and the drain end 10730, the P-region 10720, and related The vertical insulating region of the oxide layer is photolithographically and plasma/reactive ion etched to be vertically connected to all of the storage layers. The SL ground contact 10748 and the bit line contact 10749 can then be processed by photoresist removal. The contacts and metallization regions can be filled with metal or heavily doped polysilicon to form BL and SL wiring regions (not shown). A gate stack layer, such as 10728, can be connected to the contacts and metallization regions to form a word line region (WL) and a WL wiring region (not shown). A via via 10760 (not shown) may be formed to electrically couple the metallized regions of BL, SL, and WL to the peripheral circuitry of the acceptor substrate 10780 through the acceptor wafer metal bond pads 10710 (not shown).

This process can form floating gate 3D memory, with each storage layer using two additional masking operations. The 3D memory is constructed by layer-cutting the wafer-sized doped single crystal germanium layer. At the same time, the 3D memory is connected to the underlying metal layer semiconductor device.

Those skilled in the art can view the examples mentioned in Figures 107A through 107G only as a typical example and are not to scale down. More skilled people can consider more changes, for example, through the process of building BL or SL to select the transistor. Or a stacked memory layer can be connected to peripheral circuits above the storage stack. In addition, each storage layer can be configured with a slightly different donor wafer P-layer doping profile. In addition, the memory can be arranged in different ways, such as BL and SL interchange, or where the wiring is buried, the wiring of the memory array can be placed under the storage layer and above the peripheral circuit. By reading this specification, one skilled in the art can think of how to modify other places within the scope of the present invention. Accordingly, the invention is limited only by the appended claims.

As shown in Figs. 108A to 108H, a floating gate 3D memory with an additional masking process in each of the memory layers can be constructed. 3D memory is suitable for the production of 3D ICs. The 3D memory uses a 3D floating gate junctionless transistor built in a single crystal germanium.

As shown in FIG. 108A, the germanium substrate with the peripheral circuit 10802 can use high temperature (over 400 ° C) wiring, such as tungsten wire. Peripheral circuit substrate 10802 can include memory control circuitry as well as various circuits for other uses, such as for analog, digital, radio frequency or storage. Peripheral circuit substrate 10802 can include peripheral circuitry. This peripheral circuit can continue to operate even after additional rapid thermal annealing (RTA), maintaining good performance. For this reason, when constructing peripheral circuits, consideration should be given to selecting peripheral circuits that only need a slight RTA or no RTA to turn on the dopant. The uppermost layer of peripheral circuit substrate 10802 can be used to bond the oxide wafer and the deposited layer of ceria 10804 to form acceptor wafer 10814.

As shown in FIG. 108B, the single crystal germanium N+ donor wafer 10812 can comprise a wafer size N+ doped layer (not shown), wherein the dopant concentration can be different than the N+ substrate 10806. The N+ doped layer can be formed by ion implantation and high thermal annealing. The mask oxide layer 10808 can be grown or deposited prior to implantation to ensure that the germanium is protected from contamination during implantation and provides an oxide layer for later bonding between the wafers. The layer transfer boundary plane 10810 (dashed line portion in the figure) may be formed in the donor wafer 10812 in the N+ substrate 10806 or the N+ doped layer (not shown) by hydrogen ion implantation or other methods as described above. As previously described, donor wafer 10812 and acceptor wafer 10814 are both used for wafer bonding and bonded together on the surface of oxide layer 10804 and oxide layer 10808. Since the stress is lowest at low temperatures, the bonding operation is preferably carried out at a low temperature (less than 400 ° C) or a medium temperature (not exceeding 900 ° C).

As shown in FIG. 108C, the N+ layer portion (not shown) and the N+ wafer substrate 10806 above the layer transfer boundary plane 10810 can be removed by cutting or sanding or a process as previously described (eg, ion cutting or other methods), thereby The remaining single crystal germanium N+ layer 10806 is formed. The remaining N+ layer 10806' and oxide layer 10808 are layered onto the acceptor wafer 10814. The uppermost layer of the N+ layer 10806 can be polished smooth and flat by chemical or mechanical means. The transistor is now fully or partially formed and aligned with the alignment mark (not shown) of the acceptor wafer 10814.

As shown in FIG. 108D, the N+ region 10816 can be photolithographically and plasma/reactive ion etched to remove the N+ layer region 10806 and remain on the oxide layer 10808 or partially in the oxide layer 10808.

As shown in Fig. 108E, tunnel dielectric 10818 (e.g., high thermal ruthenium dioxide) may be grown or deposited, and floating gate (FG) material 10828 (e.g., doped or undoped polysilicon) may be deposited. The structure can be placed on the same plane as the N+ region 10816 by chemical-mechanical polishing (CMP). As previously mentioned, the surface can be used for bonding between oxide and oxidized wafers, such as deposition between thin oxides. A first memory layer 10823 has been formed, including the future FG region 10828, tunnel dielectric 10818, N+ region 10816, and oxide layer 10808.

As shown in FIG. 108F, the N+ layer formation, the acceptor wafer bond, and the subsequent memory layer formation process described in FIGS. 108A-108E are repeated to form a second memory layer 10825 on top of the first layer of the memory layer 10823. Oxide layer 10829 may then be deposited.

As shown in FIG. 108G, the FG region 10838 can be subjected to chemical-mechanical polishing (CMP) to remove the oxide layer portion 10829 on the second memory layer 10825, the future FG region 10828 and the oxide layer 10808, and the first memory layer. The future FG region 10828 on 10823 resides on or partially resides in the oxide layer 10808 of the first memory layer 10823.

As shown in FIG. 108H, a polysilicon oxide layer 10850 (eg, a hafnium oxide layer and a tantalum nitride layer-ONO: oxide-nitride-oxide) and a control gate (CG) gate material 10852 (eg, doped or absent) Doped polysilicon) may be deposited. The surface is planarized by a chemical-mechanical polishing (CMP) method to obtain a thin oxide layer 10829'. As shown, this provides information on four horizontal floating gate memory chips with N+ junctionless transistors. The contacts and metal wiring forming the well-known memory exit/decoding circuit can be processed to form a via via (TLV). The receiver wafer metal connection pad is electrically coupled to the memory exit and the peripheral circuit of the acceptor substrate is decoded.

This process can form floating gate 3D memory, with each storage layer using an additional masking process. The 3D memory is constructed by layer-cutting the wafer-sized doped single crystal germanium layer. At the same time, the 3D memory is connected to the underlying metal layer semiconductor device.

Those of ordinary skill in the art can view the examples mentioned in Figures 108A through 108H as merely exemplary examples and are not to scale. More skilled people can consider more changes, for example, building memory control lines at different levels than at the same level. Or a stacked memory layer can be connected to peripheral circuits above the storage stack. In addition, each storage layer can be configured with a slightly different donor wafer N+ layer doping profile. In addition, the memory can be arranged in different ways, such as BL and SL interchange, or modify these structures into NOR flash memory storage format, or where the wiring is buried, the wiring of the memory array can be placed under the storage layer and around Above the circuit. By reading this specification, one skilled in the art can think of how to modify other places within the scope of the present invention.

The monolithic 3D integration concept mentioned in this patent application can lead to novel cases of polycrystalline germanium based memory structures. When using the resistive memory structure as an example to explain the concepts in the following Figures 109 and 110, those familiar with the field can clearly see that similar concepts can be used in NAND fast memory, charge trapping type. The memory, the DRAM memory structure, and the processing flow described in the foregoing patent application.

As shown in Figs. 109A to 109K, a resistive 3D memory can be constructed without an additional masking process in each memory layer, and the method is suitable for producing a 3D IC. The 3D memory uses a polycrystalline germanium junctionless transistor. Such a transistor uses a positive or sub-threshold voltage and a resistive memory component in series with a select transistor or access transistor.

As shown in FIG. 109A, a high temperature (over 400 ° C) wiring such as a tungsten wire can be used for the germanium substrate with the peripheral circuit 10902. Peripheral circuit substrate 10902 can include memory control circuitry as well as various circuitry for other uses, such as for analog, digital, radio frequency or storage. The peripheral circuit substrate 10902 can include peripheral circuits. This peripheral circuit can continue to operate even after additional rapid thermal annealing (RTA), maintaining good performance. For this reason, when constructing peripheral circuits, consideration should be given to selecting peripheral circuits that only need partial or slight RTA or no RTA to turn on the dopant. The ruthenium dioxide layer 10904 is deposited on the top layer of the peripheral circuit substrate.

As shown in FIG. 109B, an N+ doped polysilicon layer or an amorphous germanium layer 10906 may be deposited. The amorphous germanium layer or polysilicon layer 10906 may be deposited by chemical vapor deposition (e.g., low pressure chemical vapor deposition - LPCVD or plasma enhanced chemical vapor deposition - PECVD or other processes). The N+ dopant, such as arsenic or phosphorous, may be doped during deposition; it may also be undoped during deposition, and then doped after deposition, such as by ion implantation or PLAD (plasma doping) techniques. The cerium oxide layer 10920 can then be deposited or grown. A first Si/SiO2 layer 10923 is formed, comprising an N+ doped polysilicon layer or an amorphous germanium layer 10906 and a hafnium oxide layer 10920.

As shown in FIG. 109C, a Si/SiO2 layer as shown in FIG. 109B may be additionally formed, such as a second Si/SiO2 layer 10925 and a third Si/SiO2 layer 10927. Oxide layer 10929 may be deposited to achieve insulation from the top N+ doped polysilicon or amorphous germanium layer.

As shown in FIG. 109D, rapid high thermal annealing (RTA) can be performed to make the first layer of Si/SiO2 layer 10923, the second Si/SiO2 layer 10925, and the third layer of Si/SiO2 layer 10927 N+ doped polysilicon layer or non- The germanium layer 10906 is crystallized to form a crystallized N+ germanium layer 10916. The temperature can be as high as 800 ° C during the RTA process. Alternatively, optical annealing (such as laser annealing) may be used alone, or both optical annealing and RTA may be employed, or other annealing processes may be employed.

As shown in FIG. 109E, the oxide layer 10929, the third Si/SiO2 layer 10927, the second Si/SiO2 layer 10925, and the first Si/SiO2 layer 10923 can be photolithographically and plasma/reactive ion etching. A portion of the memory wafer structure is formed. The memory wafer structure now includes a multi-layered crystallized N+ germanium region 10926 (previously crystallized N+ germanium layer 10916) and an oxide layer region 10922.

As shown in FIG. 109F, the gate dielectric and gate electrode materials may be deposited, planarized by chemical-mechanical polishing (CMP), and then photolithographically and plasma/reactive ion etching may be performed to form a gate. Polar dielectric region 10928. Gate dielectric region 10928 may be self-aligned with gate electrode 10930 (as shown) and covered by gate electrode 10930, or may adequately cover the entire N+ germanium region 10126 and oxide layer region 10922 multilayer structure. The gate stack layer (including gate electrode 10930 and gate dielectric region 10928) is comprised of a gate dielectric region (eg, a high thermal oxide layer) and a gate electrode material (eg, polysilicon). Alternatively, the gate dielectric can be selected from atomic layer deposition (ALD) materials that match the work function of the particular gate metal, in accordance with the industry standard for high-k metal gate process solutions as previously described. In addition, the gate dielectric can be formed by rapid high thermal oxidation (RTO). Rapid thermal oxidation is a process of low temperature oxidation deposition or low temperature microwave plasma oxidation of the tantalum surface, which can eventually be deposited as a gate electrode, such as a tungsten electrode or an aluminum electrode.

As shown in FIG. 109G, the gap-fill oxide layer 10932 can cover the entire structure and can be planarized by chemical-mechanical polishing. For the sake of clarity, the oxide layer 10932 is shown as a transparent layer. In addition to this, there is a text line region (WL) 10950, a gate electrode 10930, a source line region (SL) 10952, and a crystallized N+ germanium region 10926 as shown.

As shown in FIG. 109H, the bit line (BL) contact 10934 can be photolithographically and plasma/reactive ion etched through the oxide layer 10932, the three crystallized N+ germanium regions 10926, and the associated oxide vertical insulating regions. In order to fully connect with all the storage layers, and then remove the photoresist. A resistive memory material 10938, such as hafnium oxide or titanium oxide, may be deposited next, preferably by atomic layer deposition (ALD). The electrodes of the resistive memory component may then be deposited by ALD to form electrode/BL contacts 10934. The excess deposited material should be ground to the same surface as the top or bottom of the oxide layer 10932. Each of the BL contacts 10934 with resistive material 10938 can be fully shared with all of the memory layers, such as the three-layer memory layer shown in FIG.

As shown in FIG. 109I, a BL metal line 10936 can be formed and joined to an associated BL contact 10934 with a resistive material 10938. Contacts of WL and SL and associated metal wiring (not shown) may be formed at the edge of the memory array. A via via 10960 (not shown) may be formed to electrically couple the metallized regions of BL, SL, and WL to the peripheral circuitry of the acceptor substrate through the acceptor wafer metal bond pads 10980 (not shown).

Fig. 109J is a cross-sectional view of Fig. 109J. Fig. 109J1, and Fig. 109J is a cross-sectional view of Fig. 109J. 101J1 shows a BL metal line 10936, an oxide layer 10932, a BL contact/electrode 10934, a resistive material 10938, a WL region 10950, a gate dielectric 10928, a crystallized N+ germanium region 10926, and a peripheral circuit substrate 10902. The BL contact/electrode 10934 is connected to one of the three horizontal planes of the resistive material 10938. The other side of the resistive material 10938 is coupled to the crystallized N+ region 10196. The BL metal line 10936, the oxide layer 10932, the gate electrode 10930, the gate dielectric 10928, the crystallized N+ germanium region 10926, the interlayer oxide region (OX), and the peripheral circuit substrate 10902 are shown in FIG. 109J2. Gate electrode 10930 is common in the six crystallized N+ germanium regions 10926, which form six double-sided gate-controlled junctionless transistors for use as a memory selective transistor.

As shown in FIG. 109K, a typical double-sided gate-controlled junctionless transistor on the first Si/SiO2 layer 10923 may include a crystallized N+ germanium region 10926 (which functions as a source, a drain, and a transistor). The role of the trench) and the dual gate electrode 10930 (with a corresponding gate insulating layer 10928). The transistor can be insulated from the underside by an oxide layer 10908.

The process can form a resistive multilayer or 3D memory array with no additional masking process for each memory layer. The memory layer uses a junctionless polysilicon transistor with its resistive memory component in series with the selected transistor. The memory array is constructed by layer-cutting a wafer-sized doped polysilicon layer. At the same time, the 3D memory array is connected to the underlying metal layer semiconductor device.

Those of ordinary skill in the art can view the examples mentioned in Figures 109A through 109K only as a typical example, and are not to scale down. Skilled people can consider more changes. For example, after the formation of the various Si/SiO2 layers in FIG. 109C, the N+ doped polysilicon layer or amorphous germanium layer 10906 in FIG. 109D may be subjected to RTA and/or optical annealing. In addition, the N+ doped polysilicon layer or amorphous germanium layer 10906 can be doped with P+, or both dopants and other polysilicon network modifiers can be added to enhance RTA or optical annealing and subsequent crystallization, reducing N+ The resistivity of the germanium layer 10916. In addition, the dopant of the crystallized N+ layer may be slightly different when compensating for the interconnect resistance. In addition, each gate of the dual gate controlled 3D resistive memory can be independently controlled to better control the memory die. By reading this specification, one skilled in the art can think of how to modify other places within the scope of the present invention. Accordingly, the invention is limited only by the appended claims.

As shown in Figs. 110A to 110J, another example of a resistive 3D memory having no additional masking process in each memory layer can be constructed, and the method is suitable for producing a 3D IC. The 3D memory uses a polycrystalline germanium junctionless transistor. Such a transistor uses a positive or sub-threshold voltage and a resistive memory component in series with a select transistor or access transistor. It helps to form a peripheral circuit layer or slice the circuit layer to the top of the 3D memory array.

As shown in FIG. 110A, the hafnium oxide layer 11004 may be deposited or grown on top of the tantalum substrate 11002.

As shown in FIG. 110B, an N+ doped polysilicon layer or an amorphous germanium layer 11006 may be deposited. The amorphous germanium layer or polysilicon layer 11006 can be deposited by chemical vapor deposition (e.g., low pressure chemical vapor deposition - LPCVD or plasma enhanced chemical vapor deposition - PECVD or other processes). The N+ dopant, such as arsenic or phosphorous, may be doped during deposition; it may also be undoped during deposition, and then doped after deposition, such as by ion implantation or PLAD (plasma doping) techniques. The cerium oxide layer 11020 can then be deposited or grown. A first Si/SiO2 layer 11023 is formed, comprising an N+ doped polysilicon layer or amorphous germanium layer 11006 and a hafnium oxide layer 11020.

As shown in FIG. 110C, a Si/SiO2 layer as shown in FIG. 110B may be additionally formed, such as a second Si/SiO2 layer 11025 and a third Si/SiO2 layer 11027. Oxide layer 11029 may be deposited to provide insulation from the top N+ doped polysilicon or amorphous germanium layer.

As shown in FIG. 110D, rapid high thermal annealing (RTA) can be performed to make the first layer of Si/SiO2 layer 11023, the second Si/SiO2 layer 11025, and the third layer of Si/SiO2 layer 11027 N+ doped polysilicon layer or non- The germanium layer 11006 is crystallized to form a crystallized N+ germanium layer 11016. Alternatively, optical annealing (such as laser annealing) may be used alone, or both optical annealing and RTA may be employed, or other annealing processes may be employed. The temperature can be as high as 700 ° C or even 1400 ° C during the RTA process. Since there is no circuit or metallization layer underneath these crystallized N+ germanium layers, very high temperatures (such as 1400 ° C) can be used during the annealing process, which makes the quality of the polycrystalline germanium very good, the grain boundaries are few, and the carriers are close. The flexibility of single crystal germanium is higher.

As shown in FIG. 110E, the oxide layer 11029, the third Si/SiO2 layer 11027, the second Si/SiO2 layer 11025, and the first Si/SiO2 layer 11023 can be photolithographically and plasma/reactive ion etching. A portion of the memory wafer structure is formed. The memory wafer structure now comprises a multi-layered crystallized N+ germanium region 11026 (previously crystallized N+ germanium layer 11016) and an oxide layer region 11022.

As shown in FIG. 110F, the gate dielectric and gate electrode materials may be deposited, planarized by chemical-mechanical polishing (CMP), and then photolithographically and plasma/reactive ion etching may be performed to form a gate. Polar dielectric region 11028. Gate dielectric region 11028 may be self-aligned with gate electrode 11030 (as shown) and covered by gate electrode 11030, or may cover the entire crystallized N+ germanium region 11026 and oxide layer region 11022 multilayer structure. The gate stack layer (including gate electrode 11030 and gate dielectric 11028) is comprised of a gate dielectric (eg, a high thermal oxide layer) and a gate electrode material (eg, polysilicon). Alternatively, the gate dielectric can be selected from atomic layer deposition (ALD) materials that match the work function of the particular gate metal, in accordance with the industry standard for high-k metal gate process solutions as previously described. In addition, the gate dielectric can be formed by rapid high thermal oxidation (RTO). Rapid thermal oxidation is a process of low temperature oxidation deposition or low temperature microwave plasma oxidation of the tantalum surface, which can eventually be deposited as a gate electrode, such as a tungsten electrode or an aluminum electrode.

As shown in FIG. 110G, the gap-fill oxide layer 11032 can cover the entire structure and can be planarized by chemical-mechanical polishing. For the sake of clarity, the oxide layer 11032 is shown as a transparent layer. In addition to this, there are a text line region (WL) 11050, a gate electrode 11030, a source line region (SL) 11052, and a crystallized N+ germanium region 11026 as shown.

As shown in FIG. 110H, the bit line (BL) contact 11034 can be photolithographically and plasma/reactive ion etched through the oxide layer 11032, the three crystallized N+ germanium regions 11026, and the associated oxide vertical insulating regions. To connect vertically to all storage layers. The BL contact 11034 is processed by a photoresist removal method. A resistive memory material 11038, such as hafnium oxide or titanium oxide, may be deposited next, preferably by atomic layer deposition (ALD). The electrodes of the resistive memory component may then be deposited by ALD to form electrode/BL contacts 11034. The excess deposited material should be sanded to the same surface as the top or bottom of the oxide layer 11032. Each of the BL contacts 11034 with the resistive material 11038 can be fully shared with all of the memory layers, such as the three-layer memory layer shown in FIG.

As shown in FIG. 110I, a BL metal line 11036 can be formed and connected to an associated BL contact 11034 with a resistive material 11038. Contacts of WL and SL and associated metal wiring (not shown) may be formed at the edge of the memory array.

As shown in FIG. 110J, the peripheral circuit 11078 can be first constructed using the methods described above (eg, ion cutting and replacing the gate), then layered to the memory array, and then formed through vias (not shown) to enable The peripheral circuits are electrically coupled to the memory arrays BL, WL, SL, and other connecting lines, such as power lines and ground lines. Alternatively, the perimeter circuit can be constructed using a layered wafer size doped layer and subsequent processing, such as the junctionless, recessed array transistor, V-groove or bipolar transistor forming process described above, and Directly aligned with the memory array and the germanium substrate 11002.

The process can form a resistive multilayer or 3D memory array with no additional masking process for each memory layer. The memory layer uses a junctionless polysilicon transistor with its resistive memory component in series with the selected transistor. The memory array is constructed by layer-cutting a wafer-sized doped polysilicon layer. At the same time, the 3D memory array is connected to the upper multi-metal layer semiconductor device or peripheral circuitry.

Those of ordinary skill in the art can view the examples mentioned in Figures 110A through 110J as merely exemplary examples and are not to scale. Skilled people can consider more changes. For example, after formation of the various Si/SiO2 layers in FIG. 110C, the N+ doped polysilicon layer or amorphous germanium layer 11006 of FIG. 110D may be subjected to RTA and/or optical annealing. In addition, the N+ doped polysilicon layer or amorphous germanium layer 11006 can be doped with P+, or both dopants and other polysilicon network modifiers can be added to enhance the RTA or optical annealing effect and subsequent crystallization, reducing N+ The resistivity of the germanium layer 11016. In addition, the dopant of the crystallized N+ layer may be slightly different when compensating for the interconnect resistance. In addition, each gate of the dual gate controlled 3D resistive memory can be independently controlled to better control the memory die. Moreover, standard CMOS transistors can be processed at high temperatures (over 700 ° C) by selecting the correct storage layer transistor and storage layer wire materials (such as tungsten wire and other materials that can withstand high temperatures during wiring processing). A peripheral circuit 11078 is formed. By reading this specification, one skilled in the art can think of how to modify other places within the scope of the present invention. Accordingly, the invention is limited only by the appended claims.

A monolithic 3D DRAM is another example of the present invention, which we call NuDRAM. It may use the layer cutting and cutting methods mentioned in this document. This method can provide high quality single crystal germanium, and the effective heat change is small, which is a qualitative leap in the prior art.

A case of the present invention can be constructed by taking the flow shown in Figs. 88(A) to (F). Figure 88 (A) depicts the first step of the process. An n-type dopant can be implanted into the p-wafer 8801 to form an n+ layer 8802, which can then be subjected to RTA. The n+ layer 8802 can also be formed by a method of crystal growth.

Figure 88 (B) shows a step in the process. Hydrogen can be injected into the wafer at a certain depth of the p-region 8801. The final position of hydrogen is shown by the dashed line 8803.

Figure 88 (C) depicts a step in the process. The wafer is adhered to the wafer temporary carrier 8804 using an adhesive. For example, to achieve this, we can use the polybenzamine adhesive produced by DuPont to adhere the wafer to the wafer temporary carrier 8804. The wafer can then be diced on hydrogen plane 8803 using the dicing method described in this document. After the cutting, the cut surface is polished by a chemical-mechanical polishing method so that the oxide layer 8805 is deposited on the surface. The wafer structure after all the steps are completely completed is shown in Fig. 88(C).

Figure 88 (D) shows a step in the process. A wafer with a DRAM peripheral circuit 8806 (eg, a sense amplifier, a row decoder, etc.) can now be used as the base. The wafer in Fig. 88(C) can be adhered to the top of the base by using an oxide-oxide bond on the surface 8807. The temporary carrier 8804 can now be removed. Then, masking, etching, and oxidation operations can be performed to determine the diffusion line, which is insulated like the 8905 oxide layer in Figure 89(B). The diffusion row and the insulating row can be aligned with the peripheral circuitry 8806 below. After the insulating region is formed, RCAT (a recessed array transistor) can be constructed by etching and then depositing a gate dielectric 8809 and a gate electrode 8808. The program is further explained in the description of Fig. 67. The gate electrode mask can be aligned with the peripheral circuitry 8806 below. Oxide layer 8810 may be deposited and polished by chemical-mechanical polishing.

Figure 88 (E) shows a step in the process. A second layer of RCAT layer 8812 can be formed on top of the first layer of RCAT layer 8811 using similar steps in Figures 88(A)-(D). Repeat the above steps several times to get the ideal multilayer 3D DRAM.

Figure 88 (F) depicts a step in the process. The vias can be etched through all of the stacked layers to source 8814 and drain 8815. Since this step is repeated during alignment with peripheral circuitry 8806, an etch stop layer needs to be set, otherwise a fragile component should not be placed below the specified etch location. This is similar to a traditional DRAM array. In a conventional DRAM array, the gates 8816 of a plurality of RCAT transistors are connected by polysilicon wires or wires perpendicular to the plane in FIG. The connection gate electrode can form a word line similar to that illustrated in Figures 89A-D. The layout will unfold the text lines of the multi-layer DRAM structure such that each layer has a vertical contact hole connection that allows the peripheral circuit 8806 to individually control the text lines of each layer. Filling can then be performed using heavily doped polysilicon 8813. The heavily doped polysilicon 8813 can be constructed using a low temperature (less than 400 ° C) process (eg, PECVD). The heavily doped polysilicon 8813 not only improves the contact of multiple source, drain and word lines of the 3D DRAM, but also functions to separate adjacent p-layers 8817 and 8818. Alternatively, an oxide layer can also be used for isolation. Multiple layers of interconnect layers and vias can then be formed to form bit line 8815 and source line 8814 to complete the entire DRAM array. The RCAT transistor is shown in Figure 88. Other types of low temperature stacked transistors can also be constructed using process flow similar to that shown in Figures 88A-F. For example, V-groove transistors can be constructed and other transistors described in other examples in the present invention.

Figures 89(A)-(D) show side views, layout and schematic views, respectively, of a portion of the NuDRAM array depicted in Figures 88(A)-(F). Figure 89 (A) shows a specific cross-sectional view of the NuDRAM array. The bit line (BL) 8902 can operate in a direction perpendicular to the word line (WL) 8904 and the source line (SL) 8903.

Fig. 89(B) shows a cross-sectional view seen from the plane indicated by the broken line. The oxidized insulating region 8905 can separate the p-layers 8906 of adjacent transistors. Essentially, WL8907 can include the gate electrodes of the various transistors connected together.

Figure 89 (C) shows the layout of the array. The WL wiring 8908 and the SL wiring 8909 may be perpendicular to the BL wiring 8910. The NuDRAM array schematic (Fig. 89(D)) reveals the connection of WL, BL, and SL at the array level.

Figures 90(A)-(F) depict another example of the present invention. Figure 90 (A) depicts the first step of the process. The p-wafer 9001 includes an n+ type crystal growth layer 9002 and a p-type crystal growth layer 9003 grown over the n+ type crystal growth layer. In addition, these layers are also formed by injection. Oxide layer 9004 may also be grown or deposited over the wafer.

Figure 90 (B) shows a step in the process. Hydrogen H+ or other atomic species can be implanted into the wafer at a certain depth of the n+ region 9002. The final position of hydrogen is shown as dashed line 9005.

Figure 90 (C) depicts a step in the process. The wafer is flipped over and bonded to the wafer with DRAM peripheral circuit 9006 by bonding between the oxides. The wafer can then be diced on a hydrogen plane 9005 using the low temperature (less than 400 °C) dicing method described in this document. After cutting, the surface after cutting can be polished by chemical-mechanical polishing.

As shown in Fig. 90(D), a masking, etching, and low-temperature oxide layer deposition operation can be performed to determine the diffusion line insulated by the above oxide layer. The diffusion lines and insulation rows described above can be aligned with the peripheral circuitry 9006 below. After the insulating region is formed, the RCAT (the recessed array transistor) can be constructed by masking, etching, depositing the gate dielectric 9009 and the gate electrode 9008. The program is further explained in the description of Fig. 67. The gate can be aligned with the peripheral circuitry 9006 below. Oxide layer 9010 may be deposited and polished by chemical-mechanical polishing.

Figure 90 (E) shows a step in the process. A second layer of RCAT layer 9012 can be formed on top of the first layer of RCAT layer 9011 using similar steps in Figures 90(A)-(D). Repeat the above steps several times to get the ideal multilayer 3D DRAM.

Figure 90 (F) depicts a step in the process. The vias can be etched through all of the stacked layers to the source and drain connections. This is similar to a traditional DRAM array. In a conventional DRAM array, gate electrodes 9016 of a plurality of RCAT transistors are connected by polysilicon wires perpendicular to the plane in FIG. The connection gate electrode can be formed similar to a word line. The layout will unfold the text lines of the multi-layer DRAM structure such that each layer has a vertical hole that allows the peripheral circuit 9006 to individually control the text lines of each layer. Filling can then be performed using heavily doped polysilicon 9013. The heavily doped yttrium 9013 can be constructed using a low temperature (less than 400 ° C) process (eg, PECVD). Multiple layers of interconnect layers and vias can then be formed to form bit line 9015 and source line 9014 to complete the entire DRAM array. The array structure of the NuDRAM described in Fig. 90 is similar to the array in Fig. 89. The RCAT transistor is shown in Figure 90. Other types of low temperature stacked transistors can also be constructed using a process flow similar to that shown in FIG. For example, a V-groove transistor can be constructed and other transistors in other examples of the invention described above.

Other process flows for building NuDRAM are also shown in Figures 91A-L. The process described starting from FIG. 91A shows the formed shallow trench insulating layer 9102 in the SOI p-wafer 9101. The buried oxide layer is labeled 9119.

Subsequently, gate trench etching 9103 is performed as shown in FIG. 91B. 91A is a cross-sectional view of the NuDRAM on the XZ plane, and FIG. 91B is a cross-sectional view on the YZ plane (the shallow trench insulating layer 9102 is not shown in FIG. 91B).

Figure 91C shows a step below the process. Gate dielectric layer 9105 and RCAT gate electrode 9104 can be formed using a similar procedure to that of FIG. 67E. Ion implantation can then be performed to form the source and drain of the n+ region 9106.

Figure 91D illustrates the forming and sanding process of the interlayer dielectric layer 9107.

The 91E shows a step below the process. Another p-wafer 9108 can be taken. Oxide layer 9109 is grown on p-wafer 9108. For the purpose of cutting, hydrogen H+ or other atomic species may be implanted into wafer 9108 at a depth of 9110.

This "higher layer" 9108 can then be flipped over and adhered to the lower wafer 9101 by bonding between the oxides. Cutting can then be performed on the hydrogen plane 9110 followed by chemical-mechanical polishing to obtain the structure shown in Figure 91F.

Figure 91G shows a step in the process. An additional layer of RCAT9113 can be constructed using a procedure similar to that shown in Figures 91B-D. This layer of RCAT can be aligned with the components of the bottom wafer 9101.

As shown in Figure 91H, one or more layers of RCAT 9114 can be constructed using a procedure similar to that shown in Figures 91B-D.

Figure 91I shows the vias 9115 formed into the different n+ and WL layers. These vias 9115 can be constructed using heavily doped polysilicon.

Figure 91J shows a step below the process. This step accomplishes rapid high thermal annealing (RTA) to turn on the implanted dopants and thoroughly crystallize the polysilicon regions of all layers.

Figure 91K shows the formed bit line BL 9116 and source line SL 9117.

After the BL 9116 and SL 9117 are formed, FIG. 91L illustrates a method of forming a transistor and a new via layer of the DRAM peripheral circuit 9118 using the above-described procedure (eg, forming a V-groove MOSFET using the method of FIGS. 29A-G). . These peripheral circuits 9118 can be aligned with the underlying DRAM transistor layer. The DRAM transistor in this case can be of any type (high-temperature (ie over 400 ° C) processing or low temperature (ie below 400 ° C) processing of the transistor can be); since the peripheral circuit will be in the aluminum or copper wiring layer 9116 and After 9117 construction, the peripheral circuit can be processed by low temperature processing. The array structure of the case in Fig. 91 can be similar to the array structure shown in Fig. 89.

The evolution flow shown in Figures 91A-L can be used as an alternative process for making NuDRAM. The peripheral circuit layer can be built before the RTA is performed after all steps of the transistor are outside the city. One or more layers of metal tungsten may be used during local routing of these peripheral circuits. Thereafter, as shown in Fig. 91, a multilayer RCAT can be constructed by layer cutting, followed by RTA. Next, a highly conductive copper or aluminum wire layer can be added to complete the DRAM process. This process reduces manufacturing costs by sharing the high-temperature step RTA and completely processing all of the crystallized layers at once, while also using settings similar to those used in traditional 2D DRAM in 3D NuDRAM peripheral circuits. In this process flow, any type of DRAM transistor can be used, and is not limited to low temperature lithography transistors, such as RCAT or V-groove transistors.

Figures 92A-F illustrate a NuDRAM constructed using a partially depleted SOI transistor. Figure 99A depicts the first step of the process. Oxide layer 9202 may grow on p-wafer 9201. 92B shows a step below the process. Hydrogen can be injected into the wafer at a certain depth of the p-region 9201. The final position of hydrogen is shown by the dotted line 9203. Figure 92C shows a step below the process. A wafer with a DRAM peripheral circuit 9204 can be prepared. This wafer has a transistor that has not been subjected to RTA processing. In addition, the peripheral circuit can also perform a slight or partial RTA. A multilayer tungsten interconnect layer that bonds the transistors in 9204 together is prepared. The wafer of FIG. 92B is flipped over and bonded to the wafer with DRAM peripheral circuit 9204 by bonding between oxides. The wafer can then be diced on a hydrogen plane 9203 using the dicing method described in this document. After cutting, the cut surface is polished by chemical-mechanical grinding. Figure 92D shows a step below the process. As shown in Fig. 92D, a masking, etching, and low temperature oxide layer deposition operation may be performed to determine the diffusion line insulated by the above oxide layer. The diffusion lines and the insulating rows described above may be aligned with the peripheral circuitry 9204 below. After the insulating region is formed, a partially depleted SOI (PD-SOI) transistor is formed, and the gate dielectric 9207 and the gate electrode 9205 are formed, and then 9207 and 9205 are patterned and etched, and then an ion implantation source/汲 is formed. Polar zone 9208. Note that there is no need to perform an RTA turn-on injection source/drain region 9208 in this step. The mask shown in Figure 92D can be aligned with the peripheral circuitry 9204 below. Oxide layer 9206 may be deposited and polished by chemical-mechanical polishing. The 92E shows a step below the process. A second layer of PD-SOI transistor layer 9209 can be formed on top of the first layer of PD-SOI transistor layers using similar steps in Figures 92A-D. Repeat the above steps several times to get the ideal multilayer 3D DRAM. RTA can then be performed to turn on the dopants to completely crystallize the polysilicon regions of all of the transistor layers. Figure 92F depicts one step in the process. The vias 9210 can be masked and etched through all of the stacked layers to the text lines, source and drain lines. Please note that the gates of the transistor 9213 are connected in a manner similar to that of FIG. 89 to form a word line. The vias can then be filled with a metal such as tungsten. Alternatively, heavily doped polysilicon can also be used. Multiple layers of interconnect layers and vias can then be formed to form bit line 9211 and source line 9212 to complete the entire DRAM array. The array structure of the NuDRAM described in Fig. 92 is similar to the array in Fig. 89.

For programming transistors, it is sufficient to use one type of upper layer transistor. For logic circuits, two complementary transistors may be more advantageous for CMOS type logic. Therefore, the above various monomer transistor processes can be performed twice. First, all steps are thoroughly performed to construct an "n" type transistor, followed by another layer cutting, and a "p" type transistor is built on top of the "n" type transistor.

Another method is to construct an "n" type transistor and a "p" type transistor on the same layer. The difficulty is how to align these transistors with the underlying layer 808. The innovative solution will be explained below with reference to Figures 30 to 33. This process is suitable for any transistor built for wafer transfer, including but not limited to horizontal or vertical MOSFETs, JFETs, horizontal and vertical junctionless transistors, RCAT and spherical RCAT. As shown in FIG. 30, the main difference is that the donor wafer 3000 has been pre-processed to build more than one type of transistor, but two kinds of transistors, including the donor wafer 3000 for building an "n" type transistor 3004. The trip and the alternate line of construction of the "p" type of transistor. Figure 30 also shows four basic direction indicators 3040, which are explained in Figure 33 by these indicators. The width of the n-type row 3004 is Wn, the width of the p-type row 3006 is Wp, and the sum of the two W 3008 is equal to the width of the repeating pattern. The rows are repeated from east to west, and the alternating rows are repeated from north to south. The donor wafer rows 3004 and 3006 extend lengthwise from east to west for a distance equal to the acceptor die width plus the maximum distance between the donor wafer and the acceptor wafer misalignment. Alternatively, the length of the entire donor wafer can be extended from east to west. In fact, the wafer can be used as a scribing projection area. In most cases, these projection areas will contain multiple bare wafers of images or fields. In most cases, the scriber slot width set to further slice the wafer into individual bare wafers may exceed 20 microns. The distance between the wafer and the wafer misalignment is approximately 1 micron. Therefore, extending the pattern to the scribe groove can fully utilize the pattern within the bare wafer range, with as little impact as possible on the dicing trench. Wn and Wp can be set to the minimum width of the corresponding transistor plus its isolation width in the selected process node. Wafer 3000 also has an alignment mark 3020 that is on the same layer as the donor wafer as n 3004 and p 3006 rows. Therefore, in order to align other image drawing and processing processes with the above n 3004 and n 3006 rows, the wafer 3000 can be used later.

As previously mentioned, the acceptor wafer 3000 will be placed on top of the main wafer 3100 to complete the layer cut. The current technological development can achieve the angular alignment of the perfect bonding step, but it is very difficult to achieve a perfect alignment than 1 tooth m.

Those with ordinary skills will think that the four directions of the southeast and the northwest are only for illustrative purposes, and have nothing to do with the true geographic direction; and they will think that the north-south direction can be changed to the east-west direction by rotating the wafer by 90° (or vice versa); The "n" type transistor row 3004 and the "p" type transistor row 3006 can also be operated in the north-south direction, depending mainly on the setting options and the corresponding adjustments to the rest of the fabrication process. Skilled people can choose different configurations for the "n" type transistor row 3004 and the "p" row transistor row in different setting options. For example, the "n" type transistor row 3004 and the "p" type transistor row 3006 may each comprise a single row of parallel transistors, a plurality of rows of parallel transistors, and a plurality of sets of transistors of different specifications, different directions, and different types (single Only a transistor or a combination of transistors can be used, and a different transistor size or number can be selected for the "n" type transistor row 3004 and the "p" type transistor row 3006. Therefore, the scope of the invention is limited by the appended claims.

Figure 31 shows a cut-out layer 3000L of main wafer 3100 (with alignment mark 3120) and donor wafer 3000 (with alignment mark 3020). The east-west direction misalignment line is DX 3124, and the north-south direction misalignment line is DY 3122. To simplify the description below, it can be assumed that the alignment marks 3120 and 3020 have been set so that, regardless of whether the alignment mark 3020 is perfectly aligned (within tolerance), it is aligned in an approximate manner. Aligning the south of the mark 3120, the alignment mark of the cut-out layer 3020 will always be north of the alignment line of the substrate 3120. In addition, these alignment marks can only be set at certain positions on each wafer, and can be set in other step fields, in each bare wafer, in each repeated pattern W, or in other positions according to different settings.

In constructing the monolithic 3D integrated circuit described herein, the goal is to connect the structure on layer 3000L to the structure on the underlying main wafer 3100 and 808 layers with the same density and precision of the bond lines of the layers in 808. The alignment accuracy required in this process is approximately tens of nanometers or more.

The method employed in the east-west direction can be the same as the method described in FIGS. 21 to 29. Regardless of whether the misaligned lines DX 3124 are the same, the prefabricated structures on the donor wafer 3000 are the same. Therefore, as with the previous steps, the prefabricated structures can be aligned using the alignment marks 3120 below, and the "n" type transistor row 3004 and the "p" type transistor row 3006 can be formed by etching and separate processing, without considering DX. As the graphics change, the situation in the north and south is different. However, the fact that the pattern repeats each of the distances W 3008 shows the advantage of the expected structure of the repeating pattern of the alternating north-south direction shown in FIG. Therefore, since the north-south pattern can keep repeating each segment W, the uncertainty of effective alignment can be reduced to W 3008.

Therefore, the uncertainty of the effective alignment can be calculated by the method shown in FIG. 32 to determine the number of Ws required by DY 3122 - the complete "n" row 3004 and the "p" row 3006 combination graph, and the residual Rdy 3202 is calculated. (The remainder of the DY modulus W, 0 <= Rdy < W). Therefore, to be accurately aligned with the nearest n 3004 and p 3006 in the north and south, it must be aligned with the alignment mark 3120 of the Rdy 3202 offset below. Therefore, alignment should be performed in accordance with the misalignment between the acceptor wafer alignment mark 3120 and the donor wafer alignment mark 3020, and the overlap distance W 3008 is considered to calculate the resultant vector of the offset Rdy 3202. When using infrared lamps and optical components, alignment marks 3120 that are covered by wafer 3000L during alignment can be seen and can be used in a segmenter or lithography tool alignment system.

Alternatively, multiple alignment marks on the donor wafer can be used as shown in FIG. The donor wafer alignment mark 3020 can be accurately replicated on each segment of the north-south W 6920 at a distance sufficient to completely cover the north-south misalignment line M 6922 that may occur between the donor wafer and the acceptor wafer. It is appropriate. Therefore, the residual Rdy 3202 may be a north-south misalignment between the nearest donor wafer alignment mark 6920C and the acceptor wafer alignment mark 3120. Thus, the alignment mark 9620C closest to the donor wafer layer is aligned, rather than being aligned with the underlying Rdy 3202 offset alignment mark 3120. Therefore, alignment can be performed in accordance with the misalignment between the acceptor wafer alignment mark 3120 and the donor wafer alignment mark 6920 by selecting the closest alignment mark 6920C on the donor wafer.

The illustration can be simplified by the illustration in Fig. 69. In practical applications, the alignment mark may exceed the size of WxW. In this case, to avoid overlapping of the alignment marks 6920, an offset technique can be used to take appropriate marks to achieve the desired alignment.

Each wafer processed through the process has a specific Rdy 3202, specifically based on the actual misalignment line DY 3122. However, masks used to draw various patterns need to be pre-set and fabricated; all wafers (wafers used for the same end device) use the same mask, regardless of the actual misalignment. As shown in FIG. 33A, in order to improve the connection between the structure on the cut-off layer 3000L and the underlying main wafer 3100, the underlying wafer 3100 is provided with a north-south direction strip bond pad 33A04 along the length of W 3008. And the extensions necessary for the through hole setting rules. The bond pad extensions that satisfy the length or width direction of the via setting rules may include compensation for angular misalignment due to adhesion between the wafer and the wafer, as well as uncompensated donor wafer bow and warpage. The stepper motor overlap algorithm does not compensate for angular misalignment. The strip 33A04 can be part of the substrate 3100 and thus aligned with its alignment mark 3120. The top-down via 33A02 (which is part of the top 3000L pattern, aligned with the underlying alignment mark 3120 with Rdy offset) will be coupled to bond pad 33A04.

Alternatively, a joint insertion strip 33B04 having a length of at least W in the north-south direction may be formed on the top layer 3000L, and an extension portion of the through hole setting rule and the other compensation portion may be formed, and the pair with the Rdy offset below the corresponding region may be formed. The alignment mark 3120 is connected thereto so as to be connected to the through hole 33B02 as a part of the lower pattern (aligned with the alignment mark 3120 below, without offset).

An example of a process flow for producing a complementary transistor on a separate cut-out layer for CMOS logic is listed below. First, the donor wafer can be pre-processed to prepare for the layer-cut operation. As shown in Figure 34A, the complementary donor wafer can be specifically processed to produce repeat rows 3400 of p and n wells, the total width of which is W3008. The length of the repeating row 3400 may be equal to the maximum distance between the acceptor die width plus the donor wafer and the acceptor wafer misalignment; alternatively, the length of the repeating row may be equal to the total length of the donor wafer. The Fig. 34A is rotated by 90 with respect to Fig. 30 as indicated by the indicators of the four basic directions, so that the direction of Fig. 34A is the same as that of Figs. 34B to 35G.

Figure 34B is a cross-sectional view of a pre-processed wafer for layer cutting. The P-wafer 3402 processed through the mask, ion implantation and opening process in the width W 3008 has a layer of "buried" N+ layer 3404 and a layer P+ layer 3406.

What follows is the masking, ion implantation and annealing of P-type crystal growth growth 3408 and N-region 3410 in Fig. 34C.

Next, as shown in Fig. 34D, shallow trenches P+ 3412 and N+ 3414 are formed through a mask, shallow trench ion implantation, and RTA turn-on.

Figure 34E shows a wafer drawing for layer cutting by injection pre-processing of atomic species (e.g., H+), with a SmartCut "cutting plane" 3416 formed in the bottom region of the deeper N+ and P+ regions. A thin oxide layer 3418 may be deposited or grown to promote adhesion of the oxide to layer 808. Oxide layer 3418 can be deposited or grown prior to H+ implantation, including P+ 3412 and N+ 3414 regions of different thicknesses, resulting in a more uniform termination of the H+ implant range, facilitating injection flattening and producing a continuous SmartCut cutting plane 3416. Other ways can be used to adjust the depth of the H+ implant as necessary, including setting different implant depths for the P+ 3412 and N+ 3414 regions.

As shown in Figure 20, a layering process can now be performed to transfer the pre-processed plug strip multi-well single crystal germanium wafer on top of 808 as shown in Figure 35A. CMP and chemical sanding can now be used to smooth the cut surface or not.

The above-mentioned p & n well ribbon donor wafer pretreatment process can also be pre-well isolation by shallow trench etching, dielectric filling and CMP prior to layer cutting.

Figures 35A through 35G illustrate side views of a low temperature formed planar CMOS transistor on a complementary donor wafer (shown in Figure 34). Figure 35A shows the layer transferred to the top of the wafer or layer 808 after the smart cut 3502; where N+ 3404 and P+ 3406 are at the top, as judged by the basic direction 3500, they are oriented east-west (ie perpendicular to the figure) Plane), and the repeat width is north-south.

Next, as shown in FIG. 35B, the substrate P+35B06 and N+35B08 source and 808 metal layer 35B04 inspection port and transistor isolation region 35B02 can be shielded and etched. This layer is then aligned with all of the mask layers shown in Figures 30 through 32 and Figure 35B, wherein the layer alignment marks 3020 are aligned with the alignment marks 3120 of the substrate layer 808 by offset Rdy.

By using an additional masking layer, isolation region 35C02 is sufficiently etched all the way to the top of pre-processed wafer or layer 808 to completely isolate the transistor or group of transistors shown in Figure 35C. Next, the low temperature oxide layer 35C04 is deposited and polished by chemical-mechanical polishing. Then, a thin layer of the polishing stop layer 35C06, such as low temperature tantalum nitride, is deposited to form a structure as shown in Fig. 35C.

As shown in FIG. 35D, an n-groove source 35D02, a drain 35D04, and a self-aligned gate 35D06 can be formed by masking and etching a thin layer of the polish stop layer 35C06 and the sloped N+ etch layer. Repeating the above steps on the P+ layer can form p-groove source 35D08, drain 35D10, and self-aligned gate 35D12, creating complementary components and forming a complementary metal oxide semiconductor (CMOS) tilt (35° to 90°, shown in the figure) Wet chemical or plasma etching techniques can be employed after 45°) etching. This etching operation can form an N+ source and drain angle extension 35D12 and a P+ source and a drain angle extension 35D14.

Figure 35E shows the structure of the low temperature gate dielectric 35E02 after deposition and densification, or the structure of the germanium surface (serving as the gate oxide of the n & p MOSFET) after low temperature microwave plasma oxidation, followed by the gate material. The deposition of 35E04 (such as aluminum or tungsten). In addition, the following methods can be employed to form a high-k metal gate structure. The high-k dielectric 35E02 will be deposited after the atomic smooth surface is produced using a cleaning method that conforms to the industry standard HF/SC1/SC2. The semiconductor industry has chosen tantalum dielectric as the main material to replace SiO2 and bismuth oxynitride. The ruthenium dielectric series contains ruthenium dioxide and ruthenium ruthenate/ruthenium oxynitride. The dielectric constant of cerium oxide (HfO 2 ) is twice the dielectric constant of cerium lanthanum hydride / cerium oxynitride (HfSiO/HfSiON k~15). The choice of metal materials plays a crucial role in the proper functioning of the components. The work function of the metal replacing the N+ polysilicon as the gate electrode should be approximately 4.2 eV so that the component can operate normally at the correct threshold voltage. Alternatively, instead of P+ polysilicon, the work function of the metal that becomes the gate electrode should be approximately 5.2 eV for the component to function properly. For example, the TiAl and TiAlN metal series can be used to adjust the metal work function from 4.2 eV to 5.2 eV. The gate oxide and gate metal in the n- and p-trench components may vary, and one type of gate oxide and gate metal may be selectively removed and replaced with other types.

Figure 35F shows the structure of metal gate 35E04 after chemical-mechanical polishing using nitride-etched stop layer 35C06. Finally, as shown in Fig. 35G, a thick oxide layer 35G02 is deposited, the contact openings are masked, etched, and the transistors to be connected together are prepared. Figure 35F also shows a layer cut through hole 35G04. The layer cut vias will be masked and etched to interconnect the upper transistor wiring and the bottom layer 808 interconnect wiring 35B04. This process forms a single crystal top-level CMOS transistor and interconnects the metal with the high temperature components. These transistors are connected to the underlying multi-metal semiconductor component and do not expose the underlying components. These transistors can be used as a resistive memory programming transistor on layer 807 or can be used for other functions, such as logic in a 3D integrated circuit that is electrically coupled to a metal layer or layer 808 of a preprocessed wafer or Memory. Another advantage of this process is that the injection step of the SmartCut H+ or other atomic species is done prior to MOS transistor gate formation, avoiding potential damage to the gate function.

Those skilled in the art will recognize that, for the sake of clarity, in explaining the method of simultaneously fabricating P-trench and N-trench transistors, the conductive trenches of the transistors fabricated in accordance with Figures 34A through 35G are north-south, Their gate electrodes are in the east-west direction. In fact, other directions and structures can be taken. Those skilled in the art can further consider that the transistor can be rotated 90° around the gate electrode in the north-south direction. For example, highly skilled people can easily understand that the transistors aligned in the east-west direction can be insulated from each other by the low-temperature oxide layer 35C04, or the common source and drain regions and contacts can be selected according to different settings. Skilled people will also realize that the "n" type transistor row 3004 can include a plurality of north-south aligned N-trench transistors, and the "p" type transistor row 3006 can include a plurality of north-south aligned P-channels. The slot transistors form sub-rows of P-trench and N-trench transistors that are back-to-back identical to the effective logic layout. In a logical layout, sub-rows of the same type share power and connection lines. Many other setting options are also possible within the scope of the present invention, which is instructive for highly skilled people. Accordingly, this disclosure is only limited by the appended claims.

Alternatively, a complete CMOS component can be constructed using a simple layer cut of a doped layer of wafer size. The process flow will be described below by taking n-RCAT and p-RCAT as examples, but the process is not applicable to the above-described components using wafer size transfer doping layer construction.

As shown in Figures 95A through 95I, n-RCAT and p-RCAT can be constructed using a simple layer cut of a doped layer of wafer size. The process flow is also suitable for the production of 3D ICs.

As shown in FIG. 95A, the P-substrate donor wafer 9500 can include four wafer-sized layers, which are an N+ doped layer 9503, a P-doped layer 9504, a P+ doped layer 9506, and an N-doped layer, respectively. 9508. The dopant concentration of the P-doped layer 9504 may be the same as or different from the P-substrate 9500. Four doped layers 9503, 9504, 9506, and 9508 can be formed by ion implantation and high thermal annealing. Alternatively, the stacked layers may be deposited by continuous crystal growth deposition of the doped germanium layer or by both crystal growth, ion implantation, and high thermal annealing. P-layer 9504 and N-layer 9508 can also be gradient doped to address transistor performance issues, such as short pass to effects. A mask oxide layer 9501 can be grown or deposited prior to implantation to ensure that the germanium is protected from contamination during implantation and provides an oxide layer for bonding between subsequent wafers. Since the metal wiring has not been moved to the processed substrate, these steps can be performed at temperatures exceeding 400 °C.

As shown in FIG. 95B, the top layer of the donor wafer 9500 can be used to bond the oxide wafer to the deposited layer of the oxide layer 9502, or through the high thermal oxidation of the N-layer 9508, or the secondary oxidation of the implant oxide layer 9501. An oxide layer 9502 is formed. A layer cut boundary plane 9599 (dashed line portion in the figure) may be formed in the donor wafer 9500 or the N+ layer 9503 (as shown) by hydrogen ion implantation 9507 or other methods as described above. As described above, both the donor wafer 9500 and the acceptor wafer 9510 can be used as a bond between the wafers, and then the two are bonded at a low temperature (not exceeding 400 ° C). The N+ layer portion 9503 and the P-donor wafer substrate 9500 above the layer cut boundary plane 9599 can be removed by cutting or sanding or the process described above. A method of forming a layer-cutting boundary plane by ion-injecting atomic species, such as hydrogen implantation, followed by cutting or grinding may be referred to as "ion-cutting". The acceptor wafer is similar to the wafer 808 described above, please refer to Figure 8.

As shown in FIG. 95C, the remaining N+ layer 9503, P-doped layer 9504, P+ doped layer 9506, N-doped layer 9508, and oxide layer 9502 have been layered onto the acceptor wafer 9510. The uppermost layer of the N+ doped layer 9503' can be polished smooth and flat by chemical or mechanical means. A plurality of transistors have now been formed using a low temperature (less than 400 ° C) process and aligned with the acceptor wafer 9510 alignment mark (not shown). For ease of explanation, the subsequent drawings will no longer show oxide layers (eg, 9502) used to promote bonding between wafers and wafers.

As shown in FIG. 95D, the transistor isolation region may be first photolithographically patterned, and then passed through a plasma/reactive ion etch to at least reach the top oxide layer of the acceptor substrate 9510 to remove the N+ doped layer portion. 9503, P-doped layer 9504, P+ doped layer 9506, and N-doped layer 9508. Next, the low temperature gap fill oxide layer can be deposited and polished by chemical-mechanical means, remaining in the transistor isolation region 9520. Thus, the RCAT transistor N+ doped region 9513, the P-doped region 9514, the P+ doped region 9516, and the N-doped region 9518 have been further formed.

As shown in FIG. 95E, the p-RCAT portion N+ doping region 9513 and P-doping region 9514 of the wafer can be photolithographically removed by plasma/reactive ion etching or selective wet etching. . Next, the p-RCAT hidden trenches 9542 can be masked and etched. Wet chemical or plasma/reactive ion etching techniques can be used to smooth the surface and edges of the hidden trenches, reducing the strong electric field effect. These process steps result in a P+ source and drain region 9526 and an N-transistor trench region 9528.

As shown in FIG. 95F, a gate oxide layer 9511 can be formed, and a gate metal material 9554 may be deposited. The gate oxide layer 9511 can select an atomic layer deposition (ALD) gate dielectric that matches the work function of the particular gate metal 9554, in accordance with the industry standard for the high-k metal gate process scheme described above, positioned as P-groove RCAT use. In addition, the gate oxide region 9511 can be formed by low temperature microwave plasma oxidation of low temperature oxidation deposition or germanium surface. Subsequent gate materials such as platinum or aluminum may be deposited. The gate material 9554 can then be chemically and mechanically polished, and the p-RCAT gate electrode 9554' can be processed by masking and etching.

As shown in Fig. 95G, the low temperature oxide layer 9550 can be deposited and planarized to cover the formed p-RCAT. This allows processing to begin and form n-RCAT.

As shown in Figure 95H, the n-RCAT hidden trenches 9544 can be masked and etched. Wet chemical or plasma/reactive ion etching techniques can be used to smooth the surface and edges of the hidden trenches, reducing the strong electric field effect. These process steps result in an N+ source and drain region 9533 and a P-transistor trench region 9534.

As shown in FIG. 95I, a gate oxide layer 9512 may be formed, and a gate metal material 9556 may be deposited. The gate oxide layer 9512 can select an atomic layer deposition (ALD) gate dielectric that matches the work function of the particular gate metal 9556, in accordance with the industry standard for the high-k metal gate process scheme described above, positioned as N-groove RCAT. In addition, the gate oxide region 9512 can be formed by low temperature microwave plasma oxidation of a low temperature oxide deposition or tantalum surface. Subsequent gate materials such as tungsten or aluminum may be deposited. The gate material 9556 can then be chemically and mechanically polished, and the gate electrode 9556' can be processed by masking and etching.

As shown in Fig. 95J, the low temperature oxide layer 9552 can cover the entire structure and can be planarized by chemical-mechanical polishing. Contacts and metal wiring can be formed by photolithography and plasma/reactive ion etching. The n-RCAT N+ source and drain regions 9533, P-transistor trench region 9534, gate dielectric 9512, and gate electrode 9556' are shown. p-RCAT P+ source and drain regions 9526, N-transistor trench regions 9528, gate dielectric 9511 and gate electrode 9554' are shown. The transistor isolation region 9520, the oxide layer 9552, the n-RCAT source contact 9562, the gate contact 9564, and the drain contact 9566 are shown. The p-RCAT source contact 9572, the gate contact 9574, and the drain contact 9576 are as shown. The n-RCAT source contact 9562 and the drain contact 9566 are electrically coupled to the respective N+ region 9533. The n-RCAT gate contact 9564 is electrically coupled to the gate electrode 9556'. The p-RCAT source contact 9572 and the drain contact 9576 are electrically coupled to the respective N+ regions 9526. The n-RCAT gate contact 9574 is electrically coupled to the gate electrode 9554'. Junctions (not shown) of P+ doped region 9516 and N-doped region 9518 can be used to allow noise suppression bias and back gate/substrate bias.

The wiring metallization region can then be formed using conventional methods. A via via 9560 (not shown) may be formed to electrically couple the metallization region of the complementary RCAT to the acceptor substrate 9510 at the acceptor wafer metal connection pad 9580 (not shown). This process allows the formation of single crystal 矽n-RCAT and p-RCAT by simple layering of pre-fabricated wafer-sized doped layers. They can be connected to the underlying multi-metal layer semiconductor components to avoid exposing the underlying components to high temperatures.

Those of ordinary skill in the art can view the examples mentioned in Figures 95A through 95J as merely exemplary examples and are not to scale. Skilled people can consider more changes. For example, n-RCAT can be processed prior to p-RCAT or various etched hard films can be applied. Skilled people may further consider changing the process flow to create components rather than complementary RCAT, such as bipolar junction complementary transistors, or complementary transistors with raised source and drain extensions, or no junctions. A complementary crystal, or a V-shaped complementary crystal. By reading this specification, one skilled in the art can think of how to modify other places within the scope of the present invention. Accordingly, the invention is limited only by the appended claims.

Another way to build "n" and "p" rows of transistors on the same layer is to first perform the first step of the transistor formation on the donor wafer (with conventional CMOS processing), including the "virtual gate" This process is suitable for back gate transistors. In this case of the invention, the layering operation of the single crystal germanium can be performed after the completion of the dummy gate and before the gate formation. There is no temperature limit for the operation before the layer cutting. The operation during the layer cutting process and after the layer cutting should be carried out at a low temperature, usually lower than 400 °C. The dummy gate and the replacement gate can be made of a variety of materials (such as tantalum and niobium dioxide), or metals and low-k materials (such as TiAlN and HfO2). Another example is the high-k metal gate (HKMG) CMOS transistor, which has 45nm, 32nm, 22nm and other generations of CMOS Intel (Intel) and Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC) have confirmed " The advantages of the high-performance HKMG CMOS transistor for the "gate-gate" method (C, Auth et al; VLSI 2008; page: 128-129 and CHJan et al; 2009 IEDM; page: 647).

As shown in FIG. 70A, the advanced processed body 矽 donor wafer 7000 is used in the form of HKMG "back gate" until the CMP dummy gate is exposed to CMP. Figure 70A shows a cross section of a body donor wafer 7000, a gate sidewall 7002 between transistors, a polysilicon 7004 of n-type and p-type CMOS dummy gates, and a gate oxide layer 7005, their corresponding source and Bungee 7006 (NMOS) and 7007 (PMOS) and interlayer dielectric (ILD) 7008. These structures in Fig. 70A illustrate the completion of the first step of the transistor forming process. As shown in FIG. 70B, in this stage, either the layer 7008 is just CMPed to expose the polysilicon dummy gate, or the oxide layer 7008 is planarized, the dummy gate is not exposed, and the atomic species 7010 (eg, H+) can be implanted. A cutting plane 7012 is prepared for the body of the donor substrate suitable for layer cutting.

As shown in FIG. 70C, the donor wafer 7000 and the carrier substrate 7014 can now be temporarily bonded using a low temperature process that promotes low temperature release. The carrier substrate 7014 can be made of a glass substrate to achieve the most advanced optical alignment of the acceptor wafer. The temporary bonding between the carrier substrate 7014 and the donor wafer 7000 between the interfaces 7016 may use a polymeric material such as polyimine DuPont HD3007. This material can be released in the next step by laser ablation, ultraviolet radiation or thermal decomposition. Alternatively, temporary bonding can be done using monopolar or bipolar electrostatic techniques, such as the Apache tool from Beam Services Inc.

As shown in Fig. 70D, the donor wafer 7000 can then be cut on the cutting plane and thinned by chemical-mechanical polishing (CMP). As such, the transistor gate sidewall 7002 can be exposed on the donor wafer surface 7018. Alternatively, the CMP operation can continue to the bottom of the joint, creating a completely depleted SOI layer.

As shown in FIG. 70E, a thin single crystal donor wafer surface 7018 can be used for layer cutting by low temperature oxidation or precipitation of oxide layer 7020, as well as plasma or other surface treatment to provide wafer oxides and oxides. The bond between them is ready for the oxidized surface 7022. A similar surface treatment can also be applied to the 808 acceptor wafer when preparing the surface for bonding between oxide and oxide.

As shown in FIG. 70E, a low temperature (for example, less than 400 ° C) layer cut can be performed to transfer the thinned HKMA tantalum layer 7001 (with the carrier substrate 7014) in the first step of the transistor forming preprocessed to The acceptor wafer 808 (top metallization) includes a metal strip 7024 that serves as a bond pad for the bond line between the circuit formed on the cut-out layer and the underlying circuit-layer 808.

As shown in FIG. 70F, the carrier substrate 7014 can be released by a low temperature process such as laser ablation.

The bonded master wafer 808 and HKMG transistor germanium layer 7001 are now ready for use in the formation of advanced "gate" transistors. As shown in Figure 70G, the interlayer dielectric 7008 can be chemically and mechanically polished to expose the top layer of the polysilicon dummy gate. The polysilicon dummy gate can then be removed by etching, and the high-k gate dielectric 7026 and the PMOS specific work function metal gate 7028 can be deposited. The PMOS work function metal gate can be removed from the NMOS transistor, and the NMOS specific work function metal gate 7030 can be deposited. The NMOS and PMOS gates are filled with aluminum 7032 and the metal is subjected to a chemical-mechanical polishing operation.

As shown in FIG. 70H, dielectric layer 7032 may be deposited, and conventional gate 7034 and source/drain 7036 junction forming and metallization operations can now be performed to connect the transistors on the single crystal layer, and Connected to the top metallized strip 7024 of the acceptor wafer 808 through vias 7040. In this way, the donor wafer and the acceptor wafer can be connected through the cut-out layer. A top metal layer can be formed to become the acceptor wafer bond pad. The above process flow is repeated to position another pre-processed single crystal two-step shaped transistor crystal layer. Other types of gates can also be constructed using the above scheme, such as doped polysilicon on the thermal oxide layer, doped polysilicon on the oxynitride, or other metal gate configurations. These gates can be used as "virtual gates" to perform thin layering of thin single crystal layers, replacing gate electrodes and gates, and then performing low temperature wiring processing.

Alternatively, a germanium wafer can be used as the carrier substrate 7014, aligned using infrared and optical components. 82A through 82G can be used to illustrate the use of a carrier wafer. Figure 82A illustrates the first step of preparing a transistor with dummy gate 8202 on the first donor wafer 8206. The first step completes the first stage of transistor formation.

Figure 82B illustrates a method of forming a dicing line 8208 by injecting atomic particles 8216 (e.g., H+).

Figure 82C illustrates a method of permanently bonding a first donor wafer 8206 to a second donor wafer 8226. As mentioned earlier, permanent bonding may be the bond between the oxide and oxide wafers.

Figure 82D shows a second donor wafer 8226 (which becomes a carrier wafer after the first wafer is diced), leaving a thin layer 8206 with the embedded dummy gate transistor 8202.

Figure 82E illustrates the formation of a second dicing line 8218 by injecting an atomic type 8246 (e.g., H+) into the second donor wafer 8226.

Figure 82F illustrates the second step of layer cutting. Through this step, the dummy gate transistor 8202, which is ready to be permanently bonded, can be brought into the housing 808. For ease of explanation, the steps relating to the preparation of the surface layer for each bonding step are omitted here.

Figure 82G shows a housing 808 with a dummy gate transistor 8202 on top. At this point the second donor wafer has been cut and the layer on top of the dummy gate transistor has been removed. This process can now be started to replace the virtual gate with the final gate to form a metal interconnect layer and continue the 3D fabrication process.

Another interesting method can be used when taking a carrier wafer process. In this process, we can use the two sides of the cut-out layer, build NMOS on one side and PMOS on the other side. Correctly documenting the time during which the gate is replaced during this process ensures that the interconnected transistors have good performance. This process can also build compressed 3D module library chips.

As shown in FIG. 83A, the SOI (on-insulator substrate) donor wafer 8300 can be processed using advanced techniques such as the HKMG "gate-gate" process, using the adjusted thermal cycle to compensate for the late heat treatment until the polysilicon dummy gate appears. The CMP is bare. Alternatively, donor wafer 8300 can be used as a bulk wafer at the beginning to form a buried oxide layer using oxygen ion implantation and high thermal annealing, such as the SIMOX process (ie, isolation using oxygen ion implantation). 83A shows a cross section of an SOI donor wafer substrate 8300, a buried oxide layer (ie, BOX) 8301, a thin oxide layer 8302 of an SOI wafer, a gate sidewall 8303 between transistors, an n-type CMOS dummy gate. A very polycrystalline germanium 8304 and a gate oxide layer 8305, and an NMOS associated source and drain 8306, an NMOS transistor trench 8307, and an NMOS interlayer dielectric (ILD) 8308. Alternatively, a PMOS component or a complete CMOS component can be built at this stage. This step completes the first stage of transistor formation.

As shown in FIG. 83B, in this stage, either the layer 8308 is just CMPed to expose the polysilicon dummy gate, or the oxide layer 8308 is planarized, the dummy gate is not exposed, and the atomic species 8310 (eg, H+) can be implanted. A cutting plane 8312 is prepared for the body of the donor substrate suitable for layer cutting.

As shown in FIG. 83C, the SOI donor wafer 8300 can now be permanently bonded to the carrier wafer 8320. The carrier wafer 8320 has an oxide layer 8316 that can be used for bonding between the oxide-oxide and the donor wafer surface 8314.

As shown in Fig. 83D, the donor wafer 8300 can then be cut on the cutting plane 8312 and then thinned by chemical-mechanical polishing (CMP), which can be used for transistor molding.

The donor wafer layer 8300 on the surface 8322 can be processed using an advanced "gate-last" process to form a PMOS transistor with a dummy gate. 83A shows a cross section of a buried oxide layer (BOX) 8301 after PMOS component formation, a thin germanium layer 8300 of the SOI substrate, a gate sidewall 8333 between the transistors, a p-type CMOS dummy gate polysilicon 8334, and A gate oxide layer 8335, and a PMOS associated source and drain 8336, a PMOS transistor, a body trench 8337, and a PMOS interlayer dielectric (ILD) 8338. Since the shared substrate 8300 has the same alignment mark, an advanced process can precisely align the PMOS transistor with the NMOS transistor. In this step, or just CMP is performed on layer 8338, this process can expose the PMOS polysilicon dummy gate or planarize oxide layer 8338 without exposing the dummy gate. The wafer can now be placed in a high temperature annealing furnace to turn on the NMOS and PMOS transistors.

As shown in Fig. 83F, the next implantable atomic species 8340 (e.g., H+) can be used to prepare the cutting plane 8321 for the body of the carrier wafer substrate 8320 that is suitable for layer cutting.

PMOS transistors are now ready to use the most advanced process to complete the "gate-gate" transistor shaping step. As shown in Figure 83G, the interlayer dielectric 8338 can be chemically and mechanically polished to expose the top layer of the polysilicon dummy gate. The polysilicon dummy gate can then be removed by etching, and the PMOS high-k gate dielectric 8340 and the PMOS specific work function metal gate 8341 can be deposited. The PMOS gate is filled with aluminum 8342 and the metal is subjected to a chemical-mechanical polishing operation. Dielectric layer 8339 can be deposited and conventional gate 8343 and source/drain 8344 junctions can be formed and metallized. As shown in FIG. 83G, the PMOS layer to the NMOS layer via 8347 can be partially formed and metallized, and the oxide layer 8348 can be deposited to prepare for bonding.

As shown in Figure 83H, the next carrier wafer and the bilateral n/p layers can be aligned and permanently bonded to the outer acceptor wafer 808 using the associated bond strip metal 8350.

As shown in FIG. 83I, the carrier wafer 8320 can then be cut on the cutting plane 8321 and thinned to the oxide layer 8316 by chemical-mechanical polishing (CMP).

NMOS transistors are now ready for the "gate-gate" transistor shaping step using state-of-the-art processes. As shown in FIG. 83J, the NMOS interlayer dielectric 8308 can be chemically and mechanically polished to expose the top layer of the NMOS polysilicon dummy gate. The polysilicon dummy gate can then be removed by etching, and the NMOS high-k gate dielectric 8360 and the NMOS specific work function metal gate 8361 can be deposited. The NMOS gate is filled with aluminum 8362 and the metal is subjected to a chemical-mechanical polishing operation. Dielectric layer 8369 can be deposited and conventional gate 8363 and source/drain 8364 junctions can be formed and metallized. A via 8367 of the connection 8347 can be formed between the NMOS layer and the PMOS layer, and the via is metallized.

As shown in Figure 83K, dielectric layer 8370 can be deposited. The vias 8372 between the layers can then be aligned, masked, etched, and metallized to electrically connect them to the acceptor wafer 808 and the metal bond strip 8350. As shown in Figure 83K, the topmost metal layer can be formed to become the acceptor wafer bond pad. The above process flow is repeated to position another thin layer of pre-processed single crystal transistor. Those of ordinary skill in the art can view the examples mentioned in Figures 83A through 83K as merely exemplary examples and are not to scale. Skilled people can consider more changes. For example, the transistors on each side of the BOX8301 can be fully CMOS; either CMOS on one side or other n-type MOSFET transistors on the other side; or other combinations and other types of semiconductor components. By reading this specification, one skilled in the art can think of how to modify other places within the scope of the present invention. Accordingly, the invention is limited only by the appended claims.

83L is a repeating wafer 83L00 (which is a base wafer forming a gate array) and two NMOS transistors 83L04 (with a common diffusion layer 83L05, "face down") and two PMOS transistors 83L02 (with a common diffusion layer). The top view NMOS transistor gate covers the PMOS transistor gate 83L10, and the covered gate is connected to each other through the via 83L12. The VDD power line 83L06 becomes part of the front-down general structure during operation, and is connected to the upper layer through the through hole 83L20. The diffusion connection 83L08 will use the face down general structure 83L17 and carry it through the through holes 83L14, 83L16 and 83L18.

Figure 83L1 shows a general purpose wafer 83L00 tailored to custom NMOS contacts 83L22, 83L24 and custom metal 83L26 to form a dual inverter. The Vss power line 83L25 can operate on top of the NMOS transistor.

Fig. 83L2 is a drawing of a general-purpose wafer 83L00 for customizing the NOR function; Fig. 83L3 is a drawing of a general-purpose wafer 83L00 for customizing NAND functions; and Fig. 83L3 is a drawing of a general-purpose wafer 83L00 for customizing the multiplexer function. Therefore, the 83L00 can be widely used to customize a variety of desired logic functions. Thus, a common gate array using wafer 83L00 can be used to customize any logic function using custom contact vias and metal layers.

Please refer to Figure 70 and its description for another method. Figure 70B-1 illustrates this method in detail. The implanted atomic species 7010 (eg, H+) can be masked from the sensitive gate region 7003 and bonded to the 5000 angstrom photoresist by first implanting an etch stop layer 7050 (eg, 5000 angstroms) through mask and etched dense material protection. stand up. This creates a segmented cutting plane 7012 in the body of the donor wafer and the wafer. In addition, a smooth bonding surface suitable for layer cutting can be provided by sanding.

It is also possible to use another method of isolating the transistor in the vertical direction by means of a SOI donor wafer. For example, pn junctions can be formed between vertically stacked transistors, which may be biased. In addition, oxygen ions can be implanted between the vertically stacked transistors and annealed to form a buried oxide layer. Similarly, SRI techniques can be used on first-formed dummy transistors in which the SiGe layer can be selectively etched and re-filled with oxide to create insulating islands.

For another example of the above process flow, please refer to FIG. 70. FIGS. 81A-81F illustrate the suction of the case, and a front-down CMOS planar transistor layer can be provided on top of the pre-processed case substrate. As can be seen below and in Figures 70A and 70B, a CMOS planar transistor can be fabricated using a dummy gate and a dicing plane 7012 can be created in the donor wafer. According to the foregoing description and the related content of FIG. 81A, the virtual gate can be removed at this time.

The contact and metallization steps can be performed as shown in Fig. 81B to connect the transistors to each other when the front side is facing down.

As shown in FIG. 81C, the front side 8102 of the donor wafer 8100 can be bonded by oxide deposition 8104, plasma or other surface treatment to prepare the wafer and wafer directly between the oxide and the oxide. Good oxidation surface 8106.

A similar surface treatment can also be applied to the 808 acceptor wafer when preparing the surface for bonding between oxide and oxide. As shown in FIG. 81D, a low temperature (not exceeding 400 ° C) layering process can now be performed to transfer the prepared donor wafer 8100 (with top surface 8106) onto the acceptor wafer 808. The acceptor wafer 808 can be pre-processed using a transistor line and metal wiring. The acceptor wafer 808 can be metallized on top, including a metal strip 8124 that becomes the bond pad for the bond line between the circuit formed on the cut-out layer and the circuit layer in the lower housing 808. For convenience of explanation, an STI (Shallow Slot Insulation) isolation region 8130 (without via holes 7040) is additionally added to FIGS. 81D to 81F.

As shown in Fig. 81E, the donor wafer 8100 can then be cut on the cutting plane 7012 and then thinned by chemical-mechanical polishing (CMP). As such, the transistor gate sidewalls 7002 and 8130 can be exposed. Alternatively, the CMP operation can continue to the bottom of the joint, creating a completely depleted SOI layer.

As shown in FIG. 81F, a low temperature oxide layer or low-k dielectric 8136 can be deposited and planarized. The via 8128 to the outer casing 808, the acceptor wafer bond strip 8124 and the contact 8140 and the via 7040 are etched, metallized and connected by a metal line 8150 to implement the donor wafer transistor and the acceptor crystal. Power connection between the circles. As shown in Figures 32 and 33A, the length of the mating strip 8124 should be at least the repeat width W plus the width of the edge that satisfies the appropriate through hole setting rules. The bond pad strip extensions that meet the via setting rules can include compensation for angular misalignment due to adhesion between the wafer and the wafer, as well as uncompensated donor wafer bow and warpage. The stepper motor overlap algorithm does not compensate for angular misalignment.

The front down process has some advantages. For example, a dual gate transistor, a reverse bias transistor, or a floating body in a memory application can be turned on. As another example, the back gate of the dual gate transistor can be constructed as shown in FIG. 81E-1. As previously described, the low temperature gate oxide layer 8160 with gate material 8162 may be grown or deposited and processed by photolithography and a time process.

The metal wiring diagram is constructed as shown in Fig. 81F-1.

As shown in Fig. 81F-2, a completely depleted SOI transistor with strap connectors 8170 and 8171 can also be constructed in accordance with the requirements of this flow, and thinned by CMP according to Fig. 81E.

Figures 85A through 85E illustrate another example of the dual gate process described above, which may be provided in a front-up flow, as described in Figure 70. As can be seen below and in Figures 70A and 70B, a CMOS planar transistor can be fabricated using a dummy gate and a cutting plane 7012 can be created in a donor wafer (body or SOI). As can be seen below and in Figure 70C, the donor wafer can be permanently or temporarily adhered to the carrier substrate, followed by cutting and thinning to STI 7002 as shown in Figure 70D. Alternatively, the CMP operation can continue to the bottom of the joint, creating a completely depleted SOI layer.

As shown in FIG. 85A, a second layer of gate oxide layer 8502 can be grown or deposited, and gate material 8504 can be deposited. Gate oxide layer 8502 and gate material 8504 can be formed using low temperature (not more than 400 ° C) materials and processes, such as the TEL SPA gate oxide and amorphous germanium described above, ALD technology or high-k metal gate stacking (HKMG); If the carrier substrate is permanently bonded and the existing planar transistor dopant motion has been described, a higher temperature gate oxide or oxynitride and doped polysilicon may also be employed.

As shown in FIG. 85B, the outline of the gate stack layer 8506 can be outlined. The dielectric 8508 can be deposited and planarized, and then the contact 8512 and the metallization between the local contact 8510 and the layer-layer can be formed. Layer 8516.

As shown in Fig. 85C, a thin single crystal donor and carrier substrate stack for layer cutting can be prepared by the method described above, including an oxide layer 8520. A similar surface treatment can also be employed on the main wafer of the outer casing 808 when preparing the surface for bonding between oxide and oxide. As shown in FIG. 85C, a low temperature (for example, lower than 400 ° C) layer cut can be performed to thin the HKMA layer 7001 and the back gate 8506 (attached carrier) which are pre-processed in the first stage of the transistor. The substrate 7014) is transferred to the acceptor wafer 808 (top metallization) and includes a metal strip 8124 which serves as a bond pad for the connection line between the circuit formed on the cut-out layer and the underlying circuit layer 808.

As shown in FIG. 85D, the carrier substrate 7014 can be released on the surface 7016 as described above.

As shown in Fig. 85E, the bonded acceptor wafer 808 and HKMG transistor germanium layer 7001 are now ready, and advanced techniques can be used to shape the "back gate" transistor and accept the master wafer. The outer casing 808 is connected to the through hole 7040 through the layer. The top gate is connected to the bottom gate, the metal line 8538 and the contact 8522 through the gate contact 7034, and is connected to the donor wafer layer through the layer contact 8512, so that the upper transistor 8550 has the back gate. The upper transistor 8552 is reverse biased by connecting the metal line 8516 to the feedback bias circuit. The feedback bias circuit may appear in the upper transistor stage or in the outer casing 808.

The present invention overcomes the difficulties encountered in forming a planar transistor aligned with the underlying layer 808, as seen in Figures 71-79 and Figures 30-33. As described above, referring to Figs. 70A to 70H, a general flow can be taken in the transistor molding process. In one of the cases, the donor wafer 3000 can be processed in advance so that instead of constructing only one transistor type, two types are used, including alternating rows in parallel. The alternate row is equal to the bare die width plus the maximum length between the donor wafer and the acceptor wafer misalignment. In addition, as shown in FIG. 30, in the first stage of "n" type 3004 and "p" type 3006 transistor molding, alternate rows can be made as long as the wafer, and FIG. 30 also shows four basic directions. Indicator 3040, Figures 71 through 78 are explained by these indicators. As shown in the enlarged projection view 3002, the width of the n-type row 3004 is Wn, the width of the p-type row 3006 is Wp, and the sum of the two is W3008 equal to the width of the repeating pattern. The rows are repeated from east to west, and the alternating patterns are repeatedly arranged from north to south across the wafer. Wn and Wp can be set to the minimum width of the corresponding transistor plus its isolation width in the selected process node. Wafer 3000 also has an alignment mark 3020 that is on the same layer as the donor wafer as n 3004 and p 3006 rows. Therefore, in order to align other image drawing and processing processes with the above n 3004 and n 3006 rows, the wafer 3000 can be used later.

As shown in FIG. 71, the width repeating of the p-type transistor row Wp 7106 may include two transistor insulating regions 7110 each having a width of 2F; plus a transistor source 7112 having a width of 2.5 F; and a PMOS gate 7113 , width F and a transistor bungee 7114, width 2.5F. The total width Wp may be equal to 10F, where F is 2 x λ, the minimum setting rule. The n-type transistor row width repeat Wn 7104 may comprise two transistor insulating regions 7110 each having a width of 2F; plus a transistor source 7116 having a width of 2.5F; an NMOS gate 7117, a width F and an electric Crystal bungee 7118, width 2.5F. The total width Wn may be equal to 10F and the total repeat width W 7108 is equal to 20F.

As described above and with reference to FIG. 70E, the donor wafer layer 3000L which has been thinned now and the HKMG layer 7001 (with the attached carrier substrate 7014) of the first-stage transistor molding pre-process can be placed as shown in FIG. The top of the acceptor wafer 3100. The current technological development can achieve the angular alignment of the perfect bonding step, but it is very difficult to achieve a perfect alignment than 1 mb. Figure 31 shows the cut-out layer 3000L of the acceptor wafer 3100 (with corresponding alignment marks 3120) and the donor wafer (with alignment marks 3020). The east-west direction misalignment line is DX 3124, and the north-south direction misalignment line is DY 3122. These alignment marks 3120 and 3020 can only be set at certain locations on each wafer, and can be set in each step field, in each bare wafer, or in each repeating pattern W. As previously described and with reference to Figures 32, 33A and 33B, the alignment method includes residual Rdy 3202 and bond pad strips 33A04 and 33B04 that can be used to increase the density and dependence of the electrical connection between the transfer donor wafer layer and the acceptor wafer. Sex.

Figures 72A through 72F illustrate a low temperature layering process for a donor wafer layout (with a gate in parallel with the source and drain shown in Figure 71).

Figure 72A shows the bonding structure of a thin single crystal pre-processed donor layer after layer-cutting to the acceptor wafer and after bonding it to the acceptor wafer and the previous chapter in Figure 70F (inclusive). Top and cross-sectional views of the wafer after removal from the carrier substrate.

The interlayer dielectric (ILD) 7008 is chemically-mechanically polished to expose the top of the dummy polysilicon; and the layer-via via 7040 is etched, metal filled, and chemically-mechanically polished as shown in FIG. 72B. .

As shown in Figure 72C, a longer row of preformed transistors can be etched to the desired length or segment by forming isolation regions 7202. Low temperature oxidation can be performed to repair the damaged portion of the edge of the transistor; the dielectric can be filled into the region 7202 and smoothed by chemical-mechanical polishing to isolate the segments of the transistor.

Alternatively, the PMOS and NMOS regions 7202 can be selectively opened or filled to improve the transistor trenches or increase the tensile stress thereof, which is advantageous for improving carrier mobility.

The polysilicon 7004 and oxide 7005 dummy gates can now be etched to provide some gates at the isolation region 7202 boundary and the common replacement gate deposition of the high-k dielectric 7026, PMOS metal gate 7028, and NMOS metal gate 7030. Cover layer. In addition, aluminum overfill 7032 can be performed. As shown in Fig. 72D, the aluminum 7032 can be chemically and mechanically polished for surface planarization of the outline of the gate profile.

As shown in FIG. 72E, a pattern of the replacement gate 7215 can be drawn and etched, and a gate contact bond pad 7218 can be provided.

Interlayer dielectrics may be deposited and planarized by chemical-mechanical polishing. As shown in FIG. 72F, a common contact forming and metallization step can be performed to fabricate a gate 7220, a source 7222, a drain 7224, and an interlayer via 7240 connection line.

In another example, donor wafer 7000 can be pre-processed in the first stage of transistor formation to build n- and p-type dummy wafers, including repeating patterns in both directions. Figures 73, 74 and 75 also show four basic direction indicators 3040, which can be interpreted by these indicators. As shown in the enlarged projection view 7302 in Fig. 73, the width Wy 7304 coincides with the repeating pattern line. The repeating pattern line is equal to the width of the donor die from east to west plus the maximum length between the donor wafer and the acceptor wafer misalignment; or equal to the length of the donor wafer from east to west; repeating the pattern through the crystal The circles are repeated from north to south. Similarly, Wx 7306 is consistent with repeating graphics lines. The repeating pattern line is equal to the width of the donor die from north to south plus the maximum length between the donor wafer and the acceptor wafer misalignment; or equal to the length of the donor wafer from north to south; repeating the pattern through the crystal The circle is repeated from east to west. The wafer 7000 also has an alignment mark 3020 that is on the same layer as the donor wafer that is a pattern line that conflicts with Wx 7306 and Wy 7304. Therefore, in order to align other image drawing and processing processes with the above lines, the alignment mark 3020 can be used later.

As described above and with reference to FIG. 70E, the donor wafer layer 3000L which has been thinned now and the HKMG layer 7001 (with the attached carrier substrate 7014) of the first-stage transistor molding pre-process can be placed as shown in FIG. The top of the acceptor wafer 3100. The current technological development can achieve the angular alignment of the perfect bonding step, but it is very difficult to achieve a perfect alignment than 1 tooth m. Figure 31 shows the cut-out layer 3000L of the acceptor wafer 3100 (with corresponding alignment marks 3120) and the donor wafer (with alignment marks 3020). The east-west direction misalignment line is DX 3124, and the north-south direction misalignment line is DY 3122. These alignment marks can only be set at certain locations on each wafer, and can be set in each step field, in each bare wafer, or in each repeating pattern W.

As shown in Fig. 74, the proposed structure includes repeating patterns of north-south and east-west directions of alternate rows of parallel transistor energy bands. The advantage of the proposed structure is that the processing of the transistor is similar to that of the acceptor wafer, thereby greatly reducing the development cost of the 3D integrated component. Therefore, the uncertainty of effective alignment can be reduced to Wy 7304 (North-South direction) and Wx 7306 (East-West direction). Accordingly, the alignment residual Rdy 3202 (the remainder of the DY modulus Wy, 0 <= Rdy < Wy) in the north-south direction can be calculated. To be accurately aligned with the nearest Wy, it must be aligned with the underlying Rdy 3202 offset alignment mark 3120 in the north-south direction. Similarly, the uncertainty of effective alignment in the east-west direction can be reduced to Wx 7306. The alignment residual Rdx 3708 (the remainder of the DX modulus Wx, 0 <= Rdx < Wx) in the east-west direction can be calculated in a similar manner to the Rdy 3202. Again, to be accurately aligned with the nearest Wx, it must be aligned with the underlying Rdx 7308 offset alignment mark 3120 in the east-west direction.

Each wafer to be processed in accordance with this procedure shall have at least one specific Rdx 7308 and Rdy 3202, depending on the actual misalignment lines DX 3124 and DY 3122 and Wx and Wy. However, masks used to draw various patterns need to be pre-set and fabricated; all wafers (wafers used for the same terminal device) must use the same mask, regardless of the actual wafer-to-wafer Misaligned condition. As shown in FIG. 75, in order to ensure that the structure on the donor wafer 7001 is better connected to the underlying donor wafer 808, the underlying wafer 808 should be provided with a rectangular bond pad 7504 extending north-south along the length Wy 7304, plus The extension of the through hole setting rule is satisfied; in addition, the bonding pad should also extend along the length Wx 7306 in the east-west direction, plus an extension that satisfies the through hole setting rule. A rectangular extension of the bond pad that satisfies the via setting rules can include compensating for angular misalignment due to adhesion between the wafer and the wafer, as well as uncompensated donor wafer bow and warpage. The stepper motor overlap algorithm does not compensate for angular misalignment. The bond pad 7504 can be part of the acceptor wafer 808 and thus aligned with its alignment mark 3120. The via hole 7502 is a falling direction and is a portion of the pattern of the donor wafer 7001. It is connected to the bond pad 7504 by offsetting the Rdx 7308 and Rdy 3202 with the underlying alignment mark 3120, respectively.

As shown in Figure 77, in another example, the rectangular bond pads 7504 in the acceptor substrate 808 can be replaced with bond pads 77A04 in the acceptor wafer and vertical bond pins 77A06 in the acceptor layer. The via 77A02 is in the down direction and is part of the donor wafer 7001 pattern. It is connected to the bond pad 77A06 by offsetting the Rdx 7308 and Rdy 3202 with the underlying alignment mark 3120, respectively.

Figure 76 shows the repeating pattern from the north-south direction and the east-west direction, respectively. This repeating pattern may be a repeating pattern of transistors in which each transistor has a gate 7622 that forms a transistor band along the east-west axis. The repeating pattern in the north-south direction may comprise parallel transistor energy bands, each of which has an active region 7612 or 7614. The transistor can be fully defined by its gate 7622. Therefore, repeating Wx 7306 allows the structure to be repeatedly arranged in the east-west direction. The structure repeats each Wy 7304 in the north-south direction. The width Wv 7602 of the via trenches 7618 between the layers is 5F, and the width Wn 7604 of the n-type transistor rows may include two transistor isolation regions 7610 (width 3F), a common isolation region 7616 (width 1F), and The transistor active region 7614 (width 2.5F). The p-type transistor row width Wp 7606 can include two transistor isolation regions 7610 (width 3F), a common isolation region 7616 (width 1F), and a transistor active region 7612 (width 2.5F). The total width Wy may be equal to 18F, which is the sum of Wv+Wn+Wp, where F is 2×λ, the minimum setting rule. The width of the gate 7622 is F, and the interval between the gates in the east-west direction is 4F. The thing repeat width Wx 7306 is 5F. By biasing the intermediate gate to the appropriate open state, the adjacent transistors in the east-west direction can be insulated from each other, such as the ground gate for the NMOS and the Vdd gate for the PMOS.

As described above and with reference to FIG. 70E, the donor wafer layer 3000L which has been thinned now and the HKMG layer 7001 (with the attached carrier substrate 7014) of the first-stage transistor molding pre-process can be placed as shown in FIG. The top of the acceptor wafer 3100. As previously described, the DX 3124 and DY 3122 misalignments and associated Rdx 7308 and Rdy 3202 can be calculated. As shown in FIG. 77A, in order to ensure that the structure on the donor wafer 7001 is better connected to the underlying wafer 808, the underlying wafer 808 should be provided with a bonding pad 77A04 extending in the north-south direction along the length Wy 7304. An extension of the hole setting rule. The bond pad extensions that meet the via setting rules can include compensating for angular misalignment due to adhesion between the wafer and the wafer, as well as uncompensated donor wafer bow and warpage. The stepper motor overlap algorithm does not compensate for angular misalignment. The strip 77A04 can be part of the wafer 808 and thus aligned with its alignment mark 3120. The bond strip 77A06 can be part of the donor wafer layer in a direction parallel to the transistor band and therefore also in the east-west direction. Bonding strip 77A06 can be aligned with main wafer alignment mark 3120 with Rdx and Rdy bias (that is, equivalent to alignment with donor wafer alignment mark 3020). The through hole 77A02 connecting the two joint strips 77A04 and 77A06 can be a part of the top layer 7001 pattern. The via 77A02 can be aligned with the main wafer 808 alignment mark in the east-west direction and also aligned with the main wafer alignment mark 3120 (with Rdy bias) in the north-south direction.

Alternatively, as shown in FIG. 78A, the repeating pattern of the continuous diffusion regions of the gates depicted in FIG. 76 may be provided with an enlarged Wv 7802 for amplifying the row of the mating strips 77A06. The width Wv 7802 of the via trenches 7618 between the layers is equal to 10F, and the total width Wy 7804 of the north-south direction pattern repeat is equal to 23F.

As shown in Figure 77B, in another example, the gate 7622B can be repeated in the east-west direction, mating with the additional gate sidewall repeat 7810. The repeating pattern of this transistor forms a band of transistors along the east-west axis, with each transistor having a gate 7622B. The repeating pattern in the north-south direction may comprise parallel transistor energy bands, each of which has an active region 7612 or 7614. The east-west pattern repeat width Wx 7806 is 14F, and the length of the donor wafer bond strip 77A06 can be set to the length Wx 7806 plus the length of the extension necessary to meet the set rule as previously described. The direction of the donor wafer bond strip 77A06 can be parallel to the transistor band and therefore also the east-west direction.

Figure 78C shows a cross section of a portion of a gate array with a repeating transistor wafer structure. The wafer is similar to one of the wafers of Fig. 78B in which the N transistor gates are connected to the gates corresponding to the P transistors. Figure 78C shows the injection of basic logic chips: Inv, NAND, NOR, and MUX.

Alternatively, as shown in FIG. 79, to increase the density of the via hole connection line in the via hole between the donor wafer layer and the layer, the length of the donor wafer bond pad 77A06 is set lower than Wx 7306 by adding The outer casing 77A04 engages 7900 of the width of the strip and biases the via hole 77A02. The mating connector strips 77A04 and 77A06 are aligned as previously described. As previously described, the vias 77A02 are aligned with the north-south main wafer alignment mark 3120 (with Rdy bias), aligned with the alignment mark 3120 of the acceptor wafer 808 in the east-west direction, slightly biased toward the east. The offset size is equal to the reduction of the donor wafer bond strip 77A06.

In another case, functional blocks of non-repeating graphical component structures can be prepared on the donor wafer and the cut-out layer using the techniques described above. The donor wafer of this non-repeating graphics component structure may be a memory block of a DRAM, or a functional block of an input-output circuit, or other functional blocks. The donor wafer non-repeating pattern assembly structure 8004 can be attached to the acceptor wafer-shell wafer bare wafer 8000 using a conventional connection structure 8002.

The outer casing 808 wafer bare wafer 8000 is shown in FIG. Connection structure 8002 can be placed inside or outside of non-repeating structure 8004. As mentioned earlier, during the layering process, Mx 8006 is equal to the maximum distance in the east-west direction between the donor wafer and the acceptor wafer 8000 misalignment plus the extension necessary to meet the set rule; My 8008 is equal to The maximum distance between the donor wafer and the acceptor wafer misalignment in the north-south direction plus the extension necessary to meet the set rules. Mx 8006 and My 8008 can include increased angular misalignment due to wafer-to-wafer bonding, as well as uncompensated donor wafer bow and warpage. The stepper motor overlap algorithm does not compensate for angular misalignment. The length of the bond pad 8010 of the acceptor wafer north and south upwards is equal to My 8008, aligned with the acceptor wafer alignment mark 3120. The length of the bond strip 8011 in the east-west direction of the donor wafer is equal to Mx 8006, aligned with the donor wafer alignment mark 3020. The via holes 8012 connecting them are aligned with the acceptor wafer alignment mark 3120 in the east-west direction and aligned with the donor wafer alignment mark 3020 in the north-south direction. For ease of explanation, the lower metal bond strips of the donor wafer are east-west, and the higher metal bond strips of the donor wafer are north-south. The orientation of the mating plug strips is interchangeable.

The donor wafer can include components of the repeating component structural components (as shown in Figures 76 and 78B) and non-repetitive component structural components. As mentioned earlier, one of the two components is a duplicate component and the other is a non-repeating component that can draw graphics separately. The reason is that the pattern of non-repetitive components can be aligned with the donor wafer alignment mark 3020, while the pattern of repeating components can be aligned with the acceptor wafer alignment mark 3120 (with Rdx and Rdy bias). Therefore, the general connection structure shown in Fig. 80 can be used for the connection between the two components. The east-west joint strip 8011 can be aligned with the donor wafer alignment mark 3020 and the non-repetitive assembly, while the north-south joint strip 8010 can be aligned with the acceptor wafer mark 3120 (with offset) and repeating components Graphic alignment. The vias 8012 connecting the strips need to be aligned with the donor wafer alignment mark 3020 in the north-south direction and aligned with the acceptor wafer alignment mark 3120 (band bias) in the east-west direction.

The above process, whether it is a single transistor donor wafer or a complementary transistor donor wafer, can be repeated multiple times when building a multi-layer 3D monolithic integrated system. These processes can also provide multiple component technologies in a single 3D manner. For example, a component I/O or analog circuit (such as a phase-locked loop-PLL), a clock distribution, or a radio frequency circuit can be integrated into a CMOS logic circuit through a layer-cut method; or a bipolar circuit can be integrated into a CMOS logic circuit; Or integrate analog components into logic circuits, and so on. Previous technologies have also provided other technologies for building 3D components. The most common techniques are the use of thin film transistors (TFTs) to build a single 3D component; or stacking prefabricated wafers, followed by the use of through vias (TSVs) to connect prefabricated wafers. Since the 3D layer is approximately 60 microns on one side of the relatively wide side, the density of the via holes connecting them is relatively low, and the TFT method depends on the performance of the thin film transistor, and the stacking method depends on the relatively large TSV via hole. The size of one side (approximately equal to a few microns). As can be seen from many of the cases in which the 3D IC is constructed by layer cutting in the present invention, the cut-out layer is usually a thin layer having a thickness of less than 0.4 μm. As can be seen from some cases of the present invention, the 3D IC with the cut-out layer is in sharp contrast with the 3D IC previously constructed using TSV technology. With TSV technology, the thickness of the TSV connection layer exceeds 5 microns, and in many cases exceeds 50 microns.

Other process flows shown in Figures 20 through 35, 40, 54 through 61, and 65 through 94 provide a true monolithic 3D integrated circuit. The process can use a single crystal germanium transistor layer, layers that are aligned with one another, and layers that are only limited by the performance of the stepper motor. The single crystal germanium transistor layer should be capable of aligning the upper transistor with the underlying circuitry. Similarly, the contact spacing between the upper transistor and the lower circuit should be the same as the contact spacing of the underlying layers. Stacked wafers are only a few microns thick when using the latest stacking methods. When using the alternative process mentioned in Figures 20 to 35, 40, 40 to 61, and 65 to 94, the layer is very thin, typically only 100 nanometers; and recently the workpiece can prove that the thickness of the layer is only about 20 Nano.

Therefore, an alternative process of demonstration can be used for the production of truly monolithic 3D components. This monolithic 3D technology allows for full density integration, with tighter feature measurements, and is synchronised with the semiconductor industry.

In addition, a true monolithic 3D component can generate various sub-circuit structures in an effective three-dimensional space, and its performance is superior to that of an equivalent 2D structure. Below is an example of how to build a 3D wafer library using a true monolithic 3D approach.

Figure 42 shows a typical 2D CMOS inverter layout and schematic in which NMOS transistor 4202 and PMOS transistor 4204 are discharged together in wells of varying degrees of doping. The NMOS source 4206 is grounded in a general manner, the NMOS and PMOS gates 4208 are electrically connected together, the NMOS and PMOS gates 4210 are electrically connected together, and the PMOS 4207 source is connected to +Vdd. The 3D structure described below will utilize these third dimensional connections.

The pre-processed method of the acceptor wafer is shown in Figure 43A. A large dose of N+ ions can be implanted into the heavily doped N single crystal germanium wafer 4300 and annealed to form a lower resistivity layer 4302. Alternatively, a refractory metal such as tungsten may be added as a low resistance interconnect layer, or a thin layer or a treated geometric metallization layer. Oxide 4304 will grow or be deposited to prepare the bonded wafer. As shown in Figure 43B, the donor wafer is pre-processed to prepare for the layer cut operation. Figure 43B is a pre-processed drawing of a donor wafer for layer cutting. P-wafer 4310 can be used to prepare for layer cutting operations by deposition or growth of oxide 4312, surface plasma processing, atomic type implantation (eg, H+ is implanted when preparing SmartCut cutting plane 4314). As shown in Figure 43C, the layering process can now begin by cutting the pre-processed single crystal germanium donor wafer layer to the top of the acceptor wafer. The cutting surface 4316 can now be smoothed by CMP, chemical polishing, and epitaxial growth (EPI) sanding, or it can be polished.

44A through 44G illustrate the process flow for generating components and wiring and building a 3D module library. As shown in FIG. 44A, a sanding stop layer 4404, such as tantalum nitride or amorphous carbon, may be deposited after protecting the oxide layer 4402. The NMOS source-ground 4406 is masked and etched into contact with the heavily doped N+ layer 4302 as a ground plane. This step can be done with typical contact layer size and accuracy. For the sake of clarity, the two oxide layers (the acceptor wafer oxide layer 4304 and the donor wafer oxide layer 4312) are combined together, referred to as 4400. The NMOS source-ground 4406 is filled with a heavily doped polysilicon or amorphous germanium, or a high melting point metal such as tungsten; it is then chemical-mechanically polished as shown in FIG. 44B until it is capable of protecting the oxide layer 4404.

The standard NMOS transistor molding process can now be started, with two exceptions. In the first case, the lithography mask program is omitted in the implantation step of distinguishing the NMOS and PMOS components, and only the NMOS device is formed. The second case: the high temperature annealing step is taken or not taken during the NMOS molding process, and some or all of the necessary annealing procedures described later can only be completed after the PMOS molding. As shown in FIG. 44C, the unmasked P-layer 4301 is plasma-etched through the mask to the oxide layer 4400, the mask layer is removed, the gap-filled oxide layer is deposited, and the gap is formed by chemical-mechanical polishing. The fill oxide layer is ground and a typical shallow trench isolation (STI) region 4410 is formed in the middle of the last NMOS transistor. It is also possible to perform the threshold adjustment injection simultaneously or not. The remaining oxide is removed by HF (hydrofluoric acid) etching to clean the surface of the crucible.

The gate oxide 4411 undergoes thermal growth, and the doped polysilicon is deposited to form a gate stack layer. As shown in FIG. 44D, the gate stack layer is photolithographically and etched to form an NMOS gate 4412 and form a polymer on the STI wiring 4414. Alternatively, a high-k metal gate process step can be utilized at this stage to form a gate stack layer 4412 and form a wiring over the STI 4414. At this point, the gate stack layer self-aligned LDD (lightly doped drain) and halo breakdown implant can be performed to adjust the breakdown characteristics of the joint and the transistor.

Figure 44E shows a typical spacer deposition of oxide and nitride and a subsequent etch back process to form an implant bias spacer 4416 on the gate stack. A self-aligned N+ source and drain implant is then performed to generate the NMOS transistor source and drain 4418. At this time, it is necessary to turn on the implanted ions, set the initial joint depth, and perform high temperature annealing. A self-aligned telluride can then be formed. Alternatively, one or more interconnect layers with corresponding contacts and vias (not shown) can be fabricated using standard semiconductor fabrication processes. The metal layer is constructed at a low temperature using a metal such as copper or aluminum, or is constructed using a refractory metal such as tungsten to be used normally at a high temperature exceeding 400 °C. As shown in Fig. 44F, a thick oxide film 4420 is deposited and flattened by chemical-mechanical polishing (CMP). During the processing of the wafer to become the acceptor wafer for the next layering operation, the wafer surface 4422 is treated by means of plasma activation.

As shown in FIG. 45A, the PMOS-producing donor wafer is pre-processed to prepare for the layer-cut operation. N-wafer 4502 can be used to prepare for the layer cut operation by deposition or growth of oxide 4504, surface plasmonic treatment, atomic type implantation (eg, to inject H+ when preparing the SmartCut dicing plane 4506).

As shown in Fig. 45B, the layer cutting process can now be started. The pre-processed single crystal germanium donor wafer layer is cut to the top of the acceptor wafer, and the acceptor wafer oxide 4420 layer is cut to the donor wafer for oxidation. On object 4504. To optimize the flexibility of the PMOS, the donor wafer can be rotated 90° to make the acceptor wafer part of the bonding process, facilitating the generation of PMOS trenches in the <110> 矽 plane direction. The cutting surface 4508 can now be smoothed by CMP, chemical polishing, and epitaxial growth (EPI) polishing, or without sanding.

For the sake of clarity, the two oxide layers (the acceptor wafer oxide layer 4420 and the donor wafer oxide layer 4504) are combined together, referred to as 4500. The standard PMOS transistor molding process can now be started, with one exception. The lithography mask program is omitted in the implantation step of distinguishing the NMOS and PMOS components, and only the PMOS device is formed. One advantage of such a 3D wafer structure is that the PMOS transistor and the NMOS transistor can be formed independently. Therefore, the molding process of each transistor can be optimized separately. This process can be accomplished by separately selecting the crystal orientation and various stress materials and techniques (eg, doping profile, material thickness and composition, temperature cycling, etc.).

A sanding stop layer 4404, such as tantalum nitride or amorphous carbon, may be deposited after the protective oxide layer 4510. As shown in FIG. 45C, the gap-filled oxide layer is smoothed by photolithography, plasma etching to the oxide layer 4500, deposition of the gap-filled oxide layer, and by chemical-mechanical polishing, forming a typical between the last PMOS transistors. Shallow trench insulation (STI) region 4512. It is also possible to perform the threshold adjustment injection simultaneously or not.

The remaining oxide is removed by HF (hydrofluoric acid) etching to clean the surface of the crucible. The gate oxide 4514 undergoes thermal growth, and the doped polysilicon is deposited to form a gate stack layer. As shown in FIG. 45D, the gate stack layer is photolithographically and etched to form a PMOS gate 4516 and a polymer is formed on the STI wiring 4518. Alternatively, a high-k metal gate process step can be utilized at this stage to form a gate stack layer 4516 and form a wiring over the STI 4418. A gate stack layer self-aligned LDD (lightly doped drain) and a halo breakdown implant can be performed to adjust the breakdown characteristics of the joint and the transistor.

Figure 45E shows a typical spacer deposition of oxide and nitride and a subsequent etch back process in which an implant bias spacer 4520 is formed over the gate stack. A self-aligned P+ source and drain implant is then performed to generate a PMOS transistor source and a drain 4242. High thermal annealing in PMOS and NMOS components using RTA (Rapid High Thermal Annealing) or Furnace Thermal Exposed to open the graft and set the joint. Alternatively, laser annealing can be performed after NMOS and PMOS source and drain implants to open the graft and set the joint. As indicated above, the graft can be returned with an optical absorption and reflective layer and the joint opened.

As shown in Fig. 45F, a thick oxide film 4524 is deposited and flattened by chemical-mechanical polishing (CMP).

Figure 45G illustrates a three-set eight-layer indirect point program. The etch stop layer and the polish stop layer or layer 4530 can be deposited, such as nitride or amorphous carbon. First, the deepest contact 4532 of the N+ ground plane layer 4302, and the NMOS unique gate of the NMOS drain unique contact 4540 and the STI contact 4546 are masked and etched in the first contact step. Next, the NMOS & PMOS gates on the STI interconnections 4542 and the NMOS and PMOS gate contacts 4544 are masked and etched in a second contact step. Next, the PMOS contact pads are masked and etched: the PMOS gate wiring on the STI junction 4550, the PMOS unique source contact 4552, and the PMOS unique drain contact 4554 in the third contact step. Alternatively, first mask and etch the shallowest contact, then the middle contact, and finally the deepest contact. The metal lines are masked, etched, and filled with barrier metal, and CMP is performed using a conventional dual embedded interconnect method to complete eight contact connections.

As shown in Figures 46A through 46C, with respect to the 2D CMOS inverter wafer layout and schematic shown in Figure 42, the compressed 3D CMOS inverter wafer paradigm can be constructed using the above process flow. A top view of the 3D wafer is shown in Figure 46A, where the NMOS and PMOS shallow trench isolation (STI) 4600 are aligned and the PMOS is on top of the NMOS.

A cross-sectional view in the X direction is shown in Fig. 46B, and a cross-sectional view in the Y direction is shown in Fig. 46C. The NMOS and PMOS gates 4602 are aligned and stacked and connected to the PMOS gate on the STI contact 4604 by an NMOS gate on the STI. Figure 42A shows the connection of the inverter input signal A. As shown in FIG. 42, the N+ source contact of ground plane 4606 in FIGS. 46A & 46C (similar to contact 4406 of FIG. 44B) grounds the NMOS source. As shown in FIG. 42, PMOS source contact 4608 (similar to contact 4552 in FIG. 45G) connects the PMOS source to +V 4207. As shown in FIG. 42, the NMOS and PMOS drain common contacts 4610 (similar to contacts 4544 in FIG. 45G) have the common contact 4208 as the output Y. The ground-ground plane contact is not shown (similar to contact 4532 in Figure 45G). This contact is not required in every wafer and can be shared.

Other 3D logic or memory chips can be built in a similar manner. Figure 47 shows a typical 2D dual input NOR wafer layout and schematic in which NMOS transistor 4702 and PMOS transistor 4704 are discharged together in wells of varying degrees of doping. The NMOS source 4706 is grounded in a conventional manner, and the two NMOS sources and one of the PMOS gates 4708 are electrically connected together to form an input Y. The NMOS & PMOs gates 4710 are electrically connected together to form input A or output B. The 3D structure described below will utilize these three-dimensional connections.

As shown in Figures 44A-48C, a compressed 3D dual input NOR wafer paradigm can be constructed using the process flow described above. A top view of the 3D wafer is shown in Figure 48A, where the NMOS and PMOS shallow trench isolation (STI) 4800 are uniform at the bottom and sides, not on the top germanium, and only the NMOS drains are connected. A cross-sectional view of the wafer in the X direction is shown in Fig. 48B, and a cross-sectional view in the Y direction is shown in Fig. 48C.

The NMOS and PMOS gates 4802 are aligned and stacked, with each gate being connected to the PMOS gate on the STI contact 4804 by an NMOS gate on the STI (similar to the contact 4542 shown in Figure 45G). Figure 47 shows how the input signals A & B are connected.

As shown in Figure 47, the N+ source contact of ground plane 4806 in Figures 48A and 48C grounds the NMOS source. As shown in FIG. 47, PMOS source contact 4808 (similar to contact 4552 in FIG. 45G) connects the PMOS source to +V 4707. As shown in FIG. 47, the NMOS and PMOS drain common contacts 4810 (similar to contacts 4544 in FIG. 45G) have the common contact 4708 as the output Y. NMOS source contact 4812 (similar to contact 4540 in Figure 45) connects the NMOS to output Y. The output Y is connected to the NMOS and PMOS drain common contacts 4810 using metal to form the output Y in FIG. The ground-ground plane contact is not shown (similar to contact 4532 in Figure 45G). This contact is not required in every wafer and can be shared.

As shown in Figures 49A-49C, an alternate compressed 3D dual input NOR wafer paradigm can be constructed using the process flow described above. A top view of the 3D wafer is shown in Figure 49A, where the NMOS and PMOS shallow trench isolation (STI) 4900 are consistent at the top and side, not on the top germanium layer. This creates insulation between the NMOS-A and NMOS-B transistors and connects the individual gates. As shown in Figure 47, an NMOS or PMOS transistor with the letters -A or -B indicates the gate-connected NMOS or PMOS transistor, either an A input or a B input. A cross-sectional view of the wafer in the X direction is shown in Fig. 49B, and a cross-sectional view in the Y direction is shown in Fig. 49C.

The PMOS-B gate 4902 and the dummy gate 4904 are always stacked on the gate; the PMOS-B gate 4902 is connected to the input B only through the PMOS gate on the STI contact 4908. Both NMOS-A gate 4910 and NMOS-B gate 4912 are below PMOS-A gate 4906. The NMOS-A gate 4910 and the PMOS-A gate 4912 are connected together and connected to the input A by the NMOS gate on the STI, and then connected to the PMOS gate on the STI contact 4914 (similar to FIG. 45G). The contact shown in Figure 4542). NMOS-B gate 4912 is coupled to input B by an NMOS unique gate on STI junction 4916, similar to junction 4546 shown in FIG. Figure 47 shows how the input signals A & B 4710 are connected.

As shown in Figure 47B, the N+ source contact of ground plane 4918 in Figures 49A and 49C grounds the NMOS source, similar to ground 4406 in Figure 44B. As shown in Figure 47, Vdd's PMOS-B source contact 4920 (similar to contact 4552 in Figure 45G) connects the PMOS source to +V 4707. As shown in FIG. 47, NMOS-A, NMOS-B, and PMOS drain common contacts 4922 (similar to contacts 4544 in FIG. 45G) have shared contacts 4708 as output Y. The ground-ground plane contact is not shown (similar to contact 4532 in Figure 45G). This contact is not required in every wafer and can be shared.

The CMOS transfer gate can be constructed using the above process flow. Figure 50A shows an example of a typical 2D CMOS transfer gate and a layout diagram. The NMOS transistor 5002 and the PMOS transistor 5004 are discharged together in wells of different doping levels. Control signal A (as NMOS gate input 5006) and its complement  (as PMOS gate input 5008) allow the input signal to be completely transmitted to the output signal when both the NMOS and PMOS transistors are turned on (A = 1,  = 0). When both the NMOS and PMOS transistors are off (A=0, Â=1), no input signal is transmitted. The NMOS and PMOS source 5010 are electrically connected together and connected to the output; the NMOS and PMOS drains 5012 are electrically connected together to produce an output. The 3D structure described below will utilize these three-dimensional connections.

As shown in Figures 50B through 50D, an example of a compressed 3D CMOS transfer wafer can be constructed using the above process flow. A top view of the 3D wafer is shown in Figure 50B, where the shallow trench isolation (STI) 5000 of NMOS and PMOS is consistent at the top and side. A cross-sectional view of the wafer in the X direction is shown in Fig. 50C, and a cross-sectional view in the Y direction is shown in Fig. 50D. The PMOS gate 5014 is aligned with the NMOS gate 5016 and stacked. The PMOS gate on STI contact 5018 connects PMOS gate 5014 to control signal Â5008. The NMOS gate on STI contact 5020 connects NMOS gate 5016 with control signal A 5006. The NMOS and PMOS source common contacts 5022 connect the common connection layer 5010 to the input in Figure 50A. The NMOS and PMOS drain common contacts 5024 connect the common connection layer 5012 to the output of Figure 50A.

Other 3D process flows and methods can be used to build other logic and memory chips, such as dual input NAND gates, transfer gates, NMOS drivers, flip-flops, 6T SRAM, floating DRAM, CAM (address-addressed memory) Arrays, etc.

It is also possible to build more types of compressed 3D module libraries such that one or more layers of metal wiring exist between the NMOS and PMOS components. This approach allows for the construction of more compact wafers, especially for complex wafers; however, as mentioned earlier, the top PMOS component should now be built using low temperature layer dicing and transistor forming processes, unless the metal between the NMOS and PMOS layers is used. A refractory metal such as tungsten.

Therefore, the above-described module library process flow can be adopted in FIGS. 43 and 44. As shown in Figures 21, 22, 29, 39 and 40, next, one or more layers of conventional metal wiring layers are built on top of the NMOS components, and then that wafer is considered to be the master wafer or "shell" Wafer 808, layer-cutting the PMOS components and constructing them using one of the low temperature processes.

As shown in FIGS. 51A to 51D, a compressed 3D CMOS 6-transistor SRAM (Static Random Access Memory) wafer can be constructed using the above process flow. A schematic of the SRAM wafer is shown in Figure 51A. Reading the wafer is controlled by text line transistors M5 and M6, where M6 is labeled 5106. The read transistor controls the connection of the bit line 5122 and the bit line bar line 5124. The two cross-coupled inverters M1-M4 are pulled up to Vdd 5108 by M1 or M2 5102 and pulled through the transistor M3 or M4 5104 to the ground 5110.

A top view of the NMOS (not shown metal) of the 3D SRAM wafer is shown in Fig. 51B; a cross sectional view of the SRAM wafer in the X direction is shown in Fig. 51C; and a cross sectional view in the Y direction is shown in Fig. 51D. The NMOS word line access transistor M6 5106 is connected to the bit line bar type line 5124 (with the contact of the NMOS metal 1). The NMOS pull-down transistor 5104 is connected to the ground line 5110 by the contact of the NMOS metal 1 and is connected to the backplane N+ ground plane. The bit line 5122 and the transistor insulating oxide 5100 in the NMOS metal 1 are as shown. The Vdd power supply 5108 is brought into the die on the PMOS metal 1 and connected to the M2 5102 through the P+ contacts. The PMOS polysilicon on the STI to the NMOS polysilicon on the STI contact 5112 connects the gate of the M2 5102 to the gate of the M4 5104, illustrating the method of 3D cross-coupling. The common drain of M2 and M4 is connected to the bit line read transistor M6 through PMOS P+ to NMOS N+ contact 5114.

As shown in Figures 62A-62D, a compressed 3D CMOS dual input NAND wafer paradigm can be constructed using the above process flow. A schematic of the NAND-2 wafer and a 2D layout are shown in Figure 62A. Two PMOS transistors 6201 source 6211 are connected together and connected to the V+ supply. Two PMOS drains are connected together, one connected to the NMOS drain 6213 and the other connected to the output Y. Input A 6203 is connected to a PMOS gate and an NMOS gate. Input B 6204 is connected to the other PMOS and NMOS gates. The NMOS A drain connects 6220 to the NMOS B source and the PMOS B drain 6212 to ground. The 3D structure described below will utilize these three-dimensional connections.

A top view of the 3D NAND-2 wafer (not shown) is shown in Figure 62B; a cross-sectional view of the NAND-2 wafer in the X direction is shown in Figure 62C; and a cross section in the Y direction is shown in 62D. Two PMOS source 6211 are connected together in the PMOS layer and connected to the V+ power metal 6216 through the contacts in the PMOS metal 1 layer. NMOS A drain and PMOS A drain are connected to the N+ contact using P+, and connected to the output Y metal 6217 of the PMOS metal 2, and connected to the PMOS B gate via PMOS metal 1 6215. on. Input A on PMOS metal 2 6214 connects 6203 to the PMOS A gate and NMOS A gate, and the NMOS A gate connects to the NMOS gate on the STI junction through the PMOS gate on the STI. Input B connects 6204 to the PMOS B gate, which is connected to the NMOS gate on the STI junction using the P+ gate on the STI. The NMOS A source and the NMOS B drain are connected together 6220 on the NMOS layer. The NMOS B source 6212 is connected to the ground line 6218 by the junction of the NMOS metal 1 and is connected to the backplane N+ ground plane. The transistor insulating oxide 6200 is as shown.

It is also possible to build other types of compressed 3D module libraries such that one or more layers of metal wiring exist between the NMOS and PMOS component layers. This approach allows for the construction of more compact wafer structures, especially for complex wafers; however, as mentioned earlier, low temperature layer cutting and transistor forming processes should now be used to build components over the first NMOS layer.

Therefore, the above-described module library process flow can be adopted in FIGS. 43 and 44. As shown in Figures 21, 22, 29, 39 and 40, next, one or more layers of conventional metal wiring layers are built on top of the NMOS components, and then that wafer is considered to be the master wafer or "shell" Wafer 808, layer-cutting the PMOS components and constructing them using one of the low temperature processes. This low temperature process can then be repeated to form another layer of PMOS or NMOS components, and so on.

As shown in Figures 53A-53E, a compressed 3D CMOS address-based address memory (CAM) array can be constructed using the above process flow. A schematic of the CAM wafer is shown in Figure 53A. The read SRAM wafer is controlled by text line transistors M5 and M6, where M6 is labeled 5332. The read transistor controls the connection of the bit line 5342 and the bit line bar line 5340. The two cross-coupled inverters M1-M4 are pulled up to Vdd 5334 by M1 or M2 5304 and pulled through the transistor M3 or M4 5306 to ground 5330. Match line 5336 transmits the coincidence or non-compliance status of the comparison circuit to the matching address decoder. Detect line 5316 and sensed line 5318 select the comparator circuit for address retrieval and ground the gates 5322 of pull-down transistors M8 and M10 5326. SRAM state read transistors M7 and M9 5302 gates are connected to SRAM wafer nodes n1 and n2 to read the state of the SRAM wafer into the comparator circuit. The 3D structure described below will utilize these three-dimensional connections.

3D CAM wafer (not shown metal) top layer NMOS top view shown in Figure 53B; 3D CAM wafer (display metal) top layer NMOS top view shown in Figure 53C; 3D CAM wafer X direction cross-sectional view shown in Figure 53D; Y direction cross-sectional view See Figure 53E. The NMOS word line access transistor M6 5332 is connected to the bit line bar type line 5342 (with N+ contacts of the NMOS metal 1). The NMOS pull-down transistor 5306 is connected to the ground line 5330 by the N+ contact of the NMOS metal 1 and is connected to the backplane N+ ground plane. The bit line 5340 and the transistor insulating oxide 5300 in the NMOS metal 1 are as shown. Ground layer 5322 is brought into the wafer on the upper NMOS metal-2. The Vdd power supply 5334 is brought into the wafer on the PMOS metal-1 and connected to the M2 5304 through the P+ contact. The PMOS polysilicon on the STI to the bottom NMOS polysilicon on the STI contact 5314 connects the gate of the M2 5304 with the gate of the M4 5306, illustrating the SRAM 3D cross-coupling method and is connected to the comparison wafer node via the PMOS metal-1 5312. N1. The common drain of M2 and M4 is connected to the bit line read transistor M6 through the PMOS P+ to NMOS N+ contact 5320, and the node n2 is connected to the M9 gate 5302 through the PMOS metal-1 5310 and connected to it through the metal. The gate of the STI contact 5308. The upper NMOS align wafer ground pull down transistor M10 gate 5326 is coupled to sense line 5316 and is coupled to the gate polysilicon on the STI junction by NMOS metal-2. A detection line 5318 in the upper NMOS metal-2 connects the through junction 5324 to the gate of M8 in the upper NMOS layer. A match line 5336 in the upper NMOS metal-2 is connected to the drain sides of M9 and M7.

It is also possible to build other types of compressed 3D module libraries such that one or more layers of metal wiring exist between the NMOS and PMOS component layers and one or more components are built vertically.

A compressed 3D CMOS eight-input NAND wafer is constructed as shown in Figures 63A through 63G. A schematic of the NAND-8 wafer and a 2D layout are shown in Figure 63A. Eight PMOS transistors 6301 source 6311 are connected together and connected to the V+ supply. Two PMOS drains are connected together 6313, one connected to the NMOS A drain and the other connected to the output Y. Inputs A through H are connected to a PMOS gate and an NMOS gate. Input A is connected to the PMOS A gate and NMOS A gate, and input B is connected to the PMOS B gate and the NMOS B gate. In turn, input H is connected to the PMOS H gate and the NMOS H gate. The eight NMOS transistors between the output Y, PMOS drain and ground plane are connected in series. The 3D structure described below will utilize these third dimensional connections.

A top view of a 3D NAND-8 wafer (metal not shown, with horizontal NMOS and PMOS components) is shown in Figure 63B; a cross-sectional view of the wafer X direction is shown in Figure 63C; and a cross-sectional view of the Y direction is shown at 63D. A top view of NAND-8 with vertical PMOS and horizontal NMOS components is shown in Figure 63E; a cross-sectional view in the X direction is shown in Figure 63F; and a cross-sectional view in the Y direction is shown at 63H. The same reference numerals can also be used for the same structure in the cases shown in Figs. 63B to 63D and Figs. 63E to 63G. The eight PMOS source 6311s are connected together in the PMOS layer and are connected to the V+ supply metal 6316 through the metal contacts P+ in the PMOS metal 1 layer. The NMOS A drain and the PMOS A drain 6131 are connected to the N+ contact using P+, and are connected to the output Y power metal 6315 of the PMOS metal 2, and then connected to the PMOS gate through the PMOS metal 1 6215. Point. Input A on PMOS metal 2 6314 connects 6303 to the PMOS A gate and NMOS A gate, and the NMOS A gate connects it to the NMOS gate on STI contact 6314 through the PMOS gate on STI. All other inputs are connected to the P and N gates in a similar manner. The NMOS A source and the NMOS B drain are connected together 6320 on the NMOS layer. The NMOS H source 6232 is connected to the ground line 6318 by the contact of the NMOS metal 1 and is connected to the backplane N+ ground plane. The transistor insulating oxide 6300 is as shown.

A compressed 3D CMOS eight-input NOR wafer is constructed as shown in Figures 64A through 64G. A schematic of the NOR-8 wafer and a 2D layout are shown in Figure 64A. The PMOS H transistor source 6411 is connected to the V+ supply. The NMOS drains are connected together 6413 and connected to the drain of PMOS A and output Y. Inputs A through H are connected to a PMOS gate and an NMOS gate. Input A 6403 is connected to the PMOS A gate and the NMOS A gate. All NMOS sources are grounded to 6412. In the gate stack layer, PMOS G, the PMOS H drain is connected 6420 to the next PMOS source, and so on. The 3D structure described below will utilize these three-dimensional connections.

A top view of a 3D NOR-8 wafer (metal not shown, with horizontal NMOS and PMOS components) is shown in Figure 64B; a cross-sectional view of the wafer X direction is shown in Figure 64C; and a cross-sectional view of the Y direction is shown at 64D. A top view of NAND-8 with vertical PMOS and horizontal NMOS components is shown in Figure 64E; a cross-sectional view of the X direction is shown in Figure 64F; and a cross-sectional view of the Y direction is shown at 64G. The PMOS H source 6411 is connected to the V+ supply metal 6416 in the PMOS metal 1 layer via P+ of the metal contact. The PMOS H drain connects 6420 to the PMOS G source in the PMOS layer. The NMOS source 6412 is fully grounded through N+ of the NMOS metal-1 junction and is connected to the N-substrate metal line 6418 and the backplane N+ ground plane. Input A on PMOS metal-2 is connected to PMOS and NMOS gate 6403 using a gate on the STI, and then to the gate on STI contact 6414. The NMOS drain is fully connected to the NMOS A drain and the PMOS A drain 6413 using NMOS metal-2 6415, which is connected to the N+, PMOS metal-2 contact 6417 (connected to output Y). Figure 64G illustrates the use of a vertical PMOS transistor to closely connect the stacked source and drain electrodes and form the compressed region wafer shown in Figure 64E. The transistor insulating oxide 6400 is as shown.

Thus, a CMOS circuit can be constructed in which various circuit chips are built on two germanium layers to make the circuit area smaller and the distance between the inside and the middle of the transistor wiring is shorter. Since wiring is the dominant factor in power consumption and speed, the smaller the area, the lower the power consumption of the terminal components.

Those skilled in the art would consider this document to introduce a number of different process flows using typical logic gates and memory chips as representative circuits. Skilled people will further consider which process to use in each setting. A module library may be created with all the necessary logic functions required during the setup process so that the wafers can be easily reused either in a separate setup or in other settings in the same process. Skilled people will also adopt a variety of different styles in their established settings. For example, a library of logic die modules can be constructed using wafers of the same height (standard wafers as is often referred to in the industry). Alternatively, a library of modules used in longer continuous transistor strips can be generated, which is commonly referred to in the art as a gated array. In another case, a library of wafer modules can be built and used in manual or custom settings, which is also common in the art. For example, in another alternate case, a logical chip module library tailored to the setting method can be used in a specific setting, which is a problem of setting options. If the module library is used on the same layer of the 3D IC, the same process flow can be used for the selected module library. Different processes can be used at different levels of the 3D IC, and one or more chip module banks can be selected for each level in a separate setting.

Computer program products are also commonly used in the art. These products are stored on computer readable media and used in data processing systems to automate the setup process, which is commonly referred to as computer-aided setup (CAD) software. Skills The average person will consider the advantages of setting up the chip module library in a way that is compatible with the CAD software.

Those skilled in the art will recognize one or more process flows used in the setup process or module libraries that generate I/O chips, mimic functional chips, various types of complete memory blocks, and other circuits that should be CAD software is compatible. After reading this manual, many other uses and cases are instructive for highly skilled people. Accordingly, this disclosure is only limited by the appended claims.

In addition, as described above, if a circuit wafer is built on one or more thin layers of thin layers and a dense, vertical through-silicon interconnect layer is used, the setting scheme of the metallization layer using the dense 3D technology can be performed. Perfect, as follows. Figure 59 illustrates the prior art of a cascading circuit metallization setting scheme. A conventional transistor germanium layer 5902 is connected to the first metal layer 5910 through contacts 5904. The size of such interconnected pairs of contacts and metal lines is typically at the minimum line resolution of the lithography and etch capabilities of the technology flow node. It is often referred to as the "1X" setting rule metal layer. In general, the next metal layer also follows the "1X" setting rule, the vias under the metal lines 5112, 5905, and the vias above the 5906 (all metal 5912 can be connected to the 5910 or 5914). Next, the next few layers of metal are typically made twice as small as the lithography and etch capabilities, known as the "2X" metal layer. Its metal is thicker and has a higher current carrying capacity. This can be illustrated by a metal wire 5914 matching the through hole 5907 in FIG. 59 and a metal wire 5916 matching the through hole 5908. Thus, 5918 metal vias (with 5909) and 5920 (with bond pad openings 5922) represent "4X" metallization layers where the planar and thickness dimensions are larger and thicker than the 2X and 1X layers. The exact number of 1X or 2X or 4X layers will often vary, depending on the requirements of the interconnect layer and other requirements; however, the general process is that the larger the size of the metal lines and metal spacers, the better the via hole as the metal layer. The farther the transistor is, the closer it is to the bond pad.

As shown in Fig. 60, the metallization layer setting scheme of the 3D line can be improved. The first single crystal germanium or poly germanium component layer 6024 can be understood as the NMOS germanium transistor layer of the above 3D module library wafer, and can also be understood as a conventional logic transistor germanium substrate or layer. The "1X" metal layers 6020 and 6019 are connected to the germanium transistor using contacts 6010, and are interconnected or connected to the metal lines 6018 using vias 6008 and 6009. The 2X layer is connected to the metal 6018 through the through hole 6007, and the 2X layer is connected to the metal 6017 through the through hole 6006. The 4X metal layer 6016 is connected to the metal 6015 on the 4X layer through the via 6005. However, the through hole 6004 is now constructed in accordance with the 2X setting rule so that the metal wire 6014 is also in the 2X layer. The metal wire 6013 and the through hole 6003 also conform to the 2X setting rule to satisfy the thickness requirement. Through holes 6002 and 6001 are connected to metal wires 6012 and 6011 to meet the size and thickness requirements of the 1X minimum setting rule. Next, the via hole 6000 of the PMOS layer switch 6022 is constructed in accordance with the 1X minimum setting rule, and the highest density of the top layer is provided. The exact number of 1X or 2X or 4X layers will often vary, depending primarily on circuit area and current metallization setting rules and set tradeoffs. The layered upper transistor layer 6022 can take any of the cryogenic components described herein.

If the cut-out layer is unable to transmit light of a shorter wavelength, it is impossible to detect an alignment mark and an image having a resolution of one nanometer or several tens of nanometers due to the thickness of the cut-out layer or its carrier or substrate holder. Alignment can be done using infrared (IR) optics and imaging techniques. However, its resolution and alignment capabilities may not be satisfactory. In this case, an alignment window is created in the layering process, which can be aligned using shorter wavelength light.

As shown in FIG. 111A, a donor wafer 11100 (using conductive deposition, ion implantation and annealing, oxidation, crystal growth, simultaneous use of the above methods, or other semiconductor processing steps and methods) is used at the beginning of the ordinary process flow. Layer 11102, semiconducting material or insulating material is pre-processed). The donor wafer 11100 can also be pre-processed by a layer-cutting plane (eg, a hydrogen injection cutting plane) before or after the layer 11102 is formed, or thinned by the methods described above. The alignment window 11130 is first lithographically and plasma/reactive ion etched, then filled with a shorter wavelength transparent material (e.g., hafnium oxide) and planarized by chemical-mechanical polishing (CMP). Alternatively, a chemical-mechanical polishing (CMP) method can be employed to further thin the donor wafer. The size and layout of the donor wafer aligned with the window 11130 depends on the maximum misalignment tolerance of the alignment plan used when bonding the donor wafer 11100 to the acceptor wafer 11110, and the acceptor wafer is not aligned The layout position of the standard mark 11190. The window 11130 can be machined before or after the layer 11102 is formed. The acceptor wafer 11110 can be a pre-processed wafer with a full-featured circuit, or a wafer with a pre-cut layer, or a blank carrier or a holding wafer or other type of substrate, also referred to as Target wafer. For example, the acceptor wafer 11110 and the donor wafer 11100 can be a single crystal germanium wafer or a germanium (SOI) wafer or an insulating overlying germanium (GeOI) wafer on an insulating substrate. The acceptor wafer 11110 metal connection pads or the interposer strips 11180 and the acceptor wafer alignment marks are as shown.

The donor wafer 11100 and the acceptor wafer 11110 bonding surfaces 11101 and 11111 can be deposited, polished, plasma or wet chemically processed for wafer bonding to facilitate wafer-to-wafer bonding.

As shown in FIG. 111B, the donor wafer 11100 of the tape layer 11102, the alignment window 11130, and the layer-cutting boundary plane 11199 can be turned over, with higher resolution, and then aligned to the acceptor wafer alignment mark 11190. And bonded to the acceptor wafer 11110.

As shown in FIG. 1111C, the donor wafer 11100 is diced or thinned to a layer-cutting boundary plane at the layer-cutting boundary plane, and the portion of the donor wafer 11100, the alignment window 11130, and the pre-processed layer 11102 are aligned and bonded to Acceptor wafer 11110.

As shown in FIG. 111D, the donor wafer remaining portion 11100 can be removed by grinding or etching; the cut-out layer 11102 can be further processed to create a donor wafer assembly structure 11150. The donor wafer assembly structure 11150 is precisely aligned with the acceptor wafer alignment mark 11190. The alignment window 11130' can be further processed to the alignment window area 11131. These donor wafer assembly structures 11150 can use a via via (TLV) 11160 to connect the donor wafer assembly structure 11150 to the acceptor wafer metal connection pads or the strips 11180 in a coordinated manner. Since the cut-out layer 11102 is thin and has a thickness of about 200 nm or less, the TLV can be easily processed into a through hole between a common metal and a metal. The diameter of the above TLV reaches the highest technical level, such as a few nanometers or tens of nanometers.

Another use of the high-density TLV 11160 in Figure 111D or this type of TLV in this document is to transfer heat generated by the active circuit from one layer to another through the heat transfer, such as from the donor layer and the device structure to the acceptor crystal. On a circle or substrate. TLV 11160 can also be used to transfer heat to a thermoelectric cooler, heat sink or other heat release component on the wafer. It can be mainly used to electrically couple the TLV part on the 3D IC, or it can be mainly used for heat transfer. In many cases, TLVs can be used for both electrical and heat transfer.

Since the layers are all stacked on the 3D IC, the power density per unit area will increase. The heat transfer function of single crystal germanium is the weakest at 150 W/m-K. Cerium oxide (the most common electrical insulator in modern enthalpy circuits) has the weakest heat transfer function at 1.4 W/m-K. If there is no heat sink on the 3D IC stack, the bottom wafer or layer (farthest from the heat sink) has the worst heat transfer function for that heat sink because the heat emitted from the bottom layer must pass through the wafer above it or Layers of cerium oxide and cerium.

As shown in FIG. 112A, a heat dissipation layer 11205 is deposited on top of the thin ceria layer 11203, and a ceria layer is deposited on the top surface of the interconnect metallization layer 11201 of the substrate 11202. The heat dissipation layer 11205 may comprise a plasma enhanced chemical vapor deposition diamond-like carbon (PECVD DLC) having a heat transfer rate of 1000 W/mK, or other heat transfer materials such as chemical vapor deposition (CVD) graphene (5000 W/). mK) or copper (400W/mK). The thickness of the heat dissipation layer 5015 is approximately between 20 nanometers and 1 micrometer. The most ideal thickness range is 50 nanometers to 100 nanometers. The insulator is the most ideal accessory for the thermal conductivity of the heat dissipation layer 11205, ensuring that the through-via vias meet the minimum diameter specified by the set rules. If the heat sink layer is electrically conductive, the opening of the TLV needs to be properly amplified such that the non-conductive cover layer is deposited on the TLV wall prior to the deposition of the conductive core of the TLV. Alternatively, if the heat sink layer 11205 is electrically conductive, it can be masked and etched to provide bond pads for through-via vias and a larger gate for heat transfer around the pads. The heat sink can also be used as a ground plane or power trunk and ground bus for the circuit above or below it. Oxide layer 11204 can be deposited (and planarized to fill the gaps in the heat transfer layer) to prepare for bonding between the wafer and the wafer oxide. The acceptor substrate 11214 can include a substrate 11202, an interconnect metallization layer 11201, a thin ceria layer 11203, a heat dissipation layer 11205, and an oxide layer 11204. As described above, after layer-cutting, the wafer-sized doped layer can be used to process the donor wafer substrate during the preparation of the transistor and circuitry (eg, junctionless, RCAT, V-groove, and bipolar). 11206. If an implantation method is used, the mask oxide layer 11207 can be grown or deposited prior to implantation to ensure that the germanium is protected from contamination during the implantation process and provides an oxide layer for adhesion between subsequent wafers. A layer cut boundary plane 11299 (dashed line portion in the figure) may be formed in the donor wafer substrate 11206 by hydrogen ion implantation, "ion dicing" or other methods as described above. As discussed above, the donor wafer 11212 can include a donor substrate 11206, a layer cut boundary plane 11299, a mask oxide layer 11207, and other layers (not shown) during preparation for transistor formation. As described above, both the donor wafer 11212 and the acceptor wafer 11214 are used for wafer bonding and bonded together on the surface of the oxide layer 11204 and the oxide layer 11207 at low temperatures (below 400 ° C). The donor wafer portion 11206 above the layer cut-off plane 11299 can be removed by cutting or sanding or a process as previously described (e.g., ion cutting or other method) to form the remaining cut-out layer 11206'. Alternatively, the facility master wafer 11212 can be first fabricated using the methods described above, for example, using a replacement gate (not shown) for ion dicing, and then layered onto the acceptor substrate 11214. The transistor is now fully or partially formed and aligned with the previously formed acceptor wafer alignment mark (not shown) and the through layer via. In this way, the 3D IC with integrated heat sink is built.

As shown in FIG. 113, a set of power supply gates and grounded gates (eg, bottom transistor power supply gate and ground gate 11307 and top transistor power supply gate and ground gate 11306) are permeable to through-layer power supply vias and ground. The vias 11304 are connected together and thermally coupled to the non-conductive heat sink layer 11305. If the heat sink is an electrical conductor, either it can only be used as a ground plane or a pattern can be formed between the bond pads of the TLV using the power board and ground plane. The density of the power and ground gates and the through-via vias of the power and ground gates are set to increase the total heat transfer resistance of all of the circuits in the 3D IC stack. Bond oxide 11310, printed circuit board 11300, package heat sink layer 11325, bottom transistor layer 11302, top transistor layer 11321, and heat sink are shown. In this way, the 3D IC with the integrated heat sink, heat sink, and through-via vias for the power supply gate and ground gate is built.

As shown in FIG. 113B, a thermally conductive material (eg, PECVD DLC) may be formed on the sidewalls of the 3D IC structure of FIG. 113A to form sidewall heat conductors 11360 that may be used for heat removal of the sidewalls. Bottom transistor layer power supply gate and ground gate 11307, top transistor layer power supply gate and ground gate 11306, through layer power supply via and ground via 11304, thermal layer 11305, adhesion oxide 11310, printed circuit 11300 The package heat dissipation layer 11325, the bottom transistor layer 11302, the top transistor layer 11312, and the heat sink 11330 are as shown.

Each cell-independent type also encourages the construction of transistors using materials other than germanium. For example, a thin layer can be used on one or more of the above 3D layers by direct layer cutting or deposition and using buffer composites (GaAs and InAlAs, which act to buffer erbium and III-V lattice mismatch). III-V composite quantum well trenches (eg InGaAs and InSb). This forms a high mobility transistor that can separately optimize the p and n trench transistors, which solves the integration problem of simultaneously adding n and p III-V transistors on the same substrate, and also solves the same problem. The problem of integrating II-V transistors with conventional germanium transistors on one substrate. For example, the first layer of germanium transistors and metallization layers typically cannot be exposed to elevated temperatures above 400 °C. The processing temperatures required for III-V composites, buffer layers and dopants typically exceed the limits of 400 °C. By using the pre-deposition, doped, annealed layer donor wafer formation and subsequent donor-to-acceptor wafer layering techniques described above and illustrated in Figures 14, 20-29, and 43-45, Construction of III-V transistors and circuits on top of the germanium transistors and circuits will not damage the underlying transistors and circuits. In addition, even if there is a stress mismatch in the heterogeneous materials to be integrated, such as ruthenium and III-V composites, the stress mismatch can be mitigated by an oxide layer or a special buffer layer that is vertically between the layers of the heterogeneous material. In addition, this method can also integrate optoelectronic components, communication components, and data paths processed through conventional 矽 logic transistors, memory transistors, and germanium circuits. In addition to germanium, individual crystal layers can be constructed separately using germanium.

It should be noted that this 3D IC technology can be used in many applications. By using the techniques described in Figures 21 through 35, the various structures shown in Figures 15 through 19 are constructed on a "base" that may be located below the primary or first or outer layer. These structures can also be fabricated on the "top layer", possibly above the main layer or the first layer or outer shell layer.

It should also be noted that the 3D programmable system, whose logical construction size is determined by the wafer that cuts the tiled array, as shown in FIG. 36, can utilize the 'monolithic integrated circuit' 3D technology related to 'basic' with FIG. Or add an IO wafer or memory wafer via the applicable 'tip' 35 technique shown in Figure 21, as shown in FIG. So in many cases it is preferable to use TSV to construct a 3D programmable system, and sometimes it is better to use the 'basic' or 'tip' technology.

Herein, if the substrate wafer, the transfer wafer or the donor wafer is thinned by cracking and chemical mechanical polishing, there are other methods for thinning the wafer. For example, boron implantation and annealing can be used to create a surface on the tantalum substrate that is thinned to create a wet chemical etch stop plane. Dry etching, such as a halogen agglomerate, can be used to thin the tantalum substrate and then smooth the tantalum substrate with oxygen clusters. These thinning techniques can be tailored to the process to meet the appropriate thickness and surface smoothness, either alone or in combination.

FIG. 9A illustrates a 3D-3D composite mold integrated construction IC system and a construction method using a through-hole via 9C. Figure 9A illustrates the construction of an overall cross-mode connection through all of the molds to maintain the through-holes to continue vertical.

Figure 9B illustrates a similarly sized mold construction 3D system. Figure 9B shows that the through vias 404 are in the same relative position in all of the mold construction standard interfaces.

Figure 9C illustrates a 3D system of different sized molds. Figure 9C also illustrates the use of wire bonding to connect all of the three dies to the external chain? .

Figure 10A is a schematic illustration of the current state of the art U.S. Patent 7,337,425 continuous array wafer. The bubble 102 represents a continuous array of circulating blocks, and the line 104 represents horizontal and vertical potential cut lines. Block 102 may be constructed in accordance with Figure 10B102-1 with potential cut line 104-1 or Figure 10C with parallel converter fillet 106, which is block 102-2 and potential cut line 104-2 Part of it.

Often logic components contain a wide variety of logic components, memory and I/O chips. The continuous array of current technology allows the die size to be defined outside of the same wafer, whereby the logic components will change accordingly, but the three-way ratio between the logic components, the I/O die and the memory is difficult to vary. In addition, there are various types of memory, such as static random access memory (SARM), dynamic random access memory (DRAM), flash memory, etc., and I/O chips are also various in form, such as parallel converters. Some applications may still require other features, such as handlers, digital signal processing, analog functions, and so on.

According to the case of the invention, it can adopt a different method. Rather than trying to fuse these functions on a programmable mold, this requires a large number of expensive mask sets, but rather the use of through vias to construct a configurable system. This "integrated circuit and vertically integrated packaging" technology has become US Patent 6,322,903 and was awarded to Oleg Siniaguine and Sergey Savastiouk on November 27, 2001.

In accordance with the case of the present invention, it may be advisable to concentrate on one or more functions using successive blocks of blocks. Next, the 3D integrated circuit system constructs the terminal system by integrating the desired values of each of the blocks.

Figure 11A is a schematic illustration of an actual mask on a wafer containing field editable gate array blocks as indicated by programmable logic 1100A. The wafer is a continuous array of programmable logic. 1102 is a potential cutting line to support the construction of different molds and logic on a mask set. This mold can be used as the basis for 1202A, 1202B, 1202C or 1202D in the 3D system shown in FIG. As an alternative to the present invention, these molds can be used to transfer most of the logic, and the desired memory and I/O wafers can also be obtained through other molds that are connected through the vias. It should be noted that in many cases there is no steel wire, even in the cutting line 108. In this case, at least for the logic mold, a single mask can be connected by connecting unused virgin cutting lines in accordance with the desired mold size using a dedicated mask. The actual cutting line can also be called a trunk line.

It should be noted that in the usual case, the etching on the wafer is completed by repeated projection, and the projection is referred to as a mask on the wafer in a "high-quality electronic step-and-repeat" manner. In many cases, it is preferable to consider the separation between the loop blocks 102 respectively. The loop block 102 is in the ratio of the mask image to the block, and is related to two projections. A brief description is the use of a wafer, but in many cases a wafer is only on one block with a mask.

The loop block 102 is in various forms. For field programmable gate array applications, the set block 1101 is preferably between 0.5 mm and 1 mm, which may result in a difference in terminal component size and acceptable relative area loss due to the unused potential cut line 1102. Maintain a good balance.

The uniform cycle block of Figure 11A has many advantages, and the programmable components can be constructed by cutting the wafer to the required component size. It also helps the terminal component as a complete composite component rather than just a collection of individual blocks 1101. Figure 36 shows a wafer with a potential cut line 3602 and carrying a 3601 block arrangement, cut along the actual cut line 3612 to construct a 3x3 block terminal assembly 3611. Terminal assembly 3611 is constrained by actual cutting line 3612.

37 is a schematic diagram of terminal component 3611, which includes nine 3701 blocks, such as 3601. Each block 3701 contains a small micro-control chip, the MCU 3702. This control chip has a common architecture, such as the 8051, with its own program memory and data memory. The micro-control wafer on each block will register the field programmable gate array block 3701 with its programmed function and the set initial value required for proper operation of the component. They are interconnected to be controlled by the west or south of their block in order of priority. For example, the MCU 3702-11 will be controlled by the MCU 3702-01. There is no MCU on the west side of the MCU 3702-01, so it is controlled by the MCU of the 3702-00 south. Correspondingly, the MCU 3702-00 at the southwest corner has no block MCU to control it, it is the main control chip of the terminal component.

Figure 38 illustrates a simple control connection that uses a slightly improved joint test action group -- based on the MCU architecture -- to support this block approach. Each MCU has two Time Delay Integrated Inputs (TDIs) with the TDI3816 on the west side and the TDIb 3814 on the MCU on the south side. As long as the input of the TDI3816 on the west side is turned on, it is the control chip, otherwise the TDIb 3814 on the south side is the control chip. In this diagram, the 3800 block in the southwest corner will become the master, and the input 3802 it controls will be used to control the terminal components and pass through the MCU3800 to other blocks. In the schematic diagram of FIG. 38, the output of the terminal assembly 3611 is connected by the MCU located in the block 3820 in the northeast corner, and the 3820 is located at the test data output of the 3822. These MCUs and their connections are used to register terminal component functions for initialization and testing, debugging, timing, and other desired functions. Once the terminal components have completed their setup and other control or initialization functions such as testing or debugging, these MCUs can be used as user functions and become part of the terminal component operation.

Another advantage of constructing a tiled field programmable gate array (FPGA) with MCUS is that it can be used to construct system level wafers with embedded programmable gate array functionality. A single block 3601 can be connected to a system level wafer using a via via-TSV, thus creating a separate embedded programmable gate array function.

Obviously, after the same scheme has been improved, the East/North (or other orthogonal direction combination) direction can be used to effectively write the same priority scheme.

Figure 11B is a schematic illustration of a mask positional replacement on a wafer consisting of a structured dedicated integrated circuit block (ASIC) 1100B. Such a wafer may be a continuous arrangement of configurable logic chips. 1102 is a potential cutting line used to support the construction of various molds and logic chips. Such a mold can be used as the basis for the 3D system 1202A, 1202B, 1202C or 1202D of FIG.

Figure 11C is a schematic illustration of another mask position on a wafer consisting of random access memory (RAM) 1100C blocks. The wafer may be a memory in a continuous array. The mold block outside the wafer may be the storage mold assembly of the 3D synthesis system. It may include an anti-fuse storage layer or other form of configuration technology to function as a configurable storage mold. It is possible to build through multiple memory connections, ie through multiple connections through the vias to the configurable mold, the mold can be used in a configurable system to configure the original memory of the storage mold to achieve its intended function.

Figure 11D is a schematic illustration of another mask position on a wafer consisting of a block of dynamic random memory 1100D. The wafer may be a dynamic random memory in a continuous array.

Figure 11E is a schematic illustration of another mask position on a wafer consisting of a microprocessor block or microcontroller core 1100E. The wafer may be a processor in a continuous array.

Figure 11F is a schematic illustration of another mask position on a wafer consisting of I/O wafer blocks 1100F containing sets of parallel converters (SerDes). The wafer may be a continuous block of I/O wafers. The die block outside the wafer may be the I/O die mold component of the 3D synthesis system. It may include an anti-fuse memory layer or other form of configuration technology such as static random memory to set up I/O chips for configurable I/O molds to perform their role in a configurable system. It is possible to build through multiple I/O connections, that is, through multiple connections through the vias to the configurable mold, the mold can be used in a configurable system to configure the original I/O die of the I/O mold to achieve Its intended function.

The I/O circuit is a good example of how it can be used to open programs with older versions. Usually the program driver is static random memory and logic. It takes a long time to perform analog functions related to I/O circuits, parallel converter circuits, phase-locked loop circuits (PLLs), and other linear functions. In addition, it is also advantageous to use smaller transistors to perform logic functions. I/O wafers may require stronger drivers and relatively larger transistors. Therefore, the use of the old program may be more cost-effective, because the old program chip costs less and the functionality is not reduced.

Another feature is that it may be advantageous to remove the programmable logic mold and enter other molds in the 3D system. It is connected through the via via, possibly the clock circuit and its associated phase-locked loop (PLL), dynamically connected ( DLL) circuits and control circuits, etc. Phase-locked loops and distribution. These circuits are often used in areas and may be more demanding in view of noise generation. In many cases they can be implemented efficiently using old programs. Clock trees and distribution lines may be included in the I/O mold. The clock signal can be transferred to the programmable mold by means of through-hole vias (TSVs) or fiber optics. The technology for transferring data between molds by means of optical fiber has been issued to the British company as US Patent 6052498.

As an option, fiber optic clock distributors can also be utilized. There are a number of new technologies available for constructing fiber guides on crucibles or other substrates. Fiber optic clock distributors can be used to minimize the energy used to distribute clock signals, reducing distortion and noise in digital systems. On the same mold, compared to the prior art integrated fiber-optic clock distributor with logic chip, the fiber-optic clock can be built on different molds and can be connected to the digital mold through the through-hole or fiber-optic means, making it very practical.

Alternatively, the fiber optic clock distribution auxiliary line and some of the potentially supporting electronic devices can be converted from optical signals to electronic signals, for example, by using a combination of memory layer transfer and smart cut methods as described in Figures 14 and 20. The fiber optic clock distribution auxiliary line and some of the potential supporting electronic devices can be built first on the "base" of the chip 1402, and then the thin wafer 1404 can be converted using "smart cutting", so that the construction of all of the following primary circuits will proceed. The fiber optic clock distribution auxiliary line and supporting electronics can withstand high temperatures during the processing of the memory layer 1404 transistor.

In connection with Fig. 20, the light guide and a suitable semiconductor structure (which will later be used to process the supporting electronic device) are to be pre-set on the storage layer 2019. With the "smart cut" stream, it can be transferred to wafer 808 for full processing. For the purpose of "smart cutting", the light guide should be able to withstand ion 2008 injection, and the supporting electronic device will end in the cycle, which is similar to Fig. 21 to Fig. 35, Fig. 39 to 94. This means that the landing target of the clock signal needs to accommodate the displacement of the steering storage layer 2004 of about 1 micron for the pre-processing - primary circuit and upper layer 808. This displacement is acceptable in many settings. Alternatively, the pedestal of the supporting electronic device will be prefabricated on the storage layer 2019, and the light guide will be constructed after the final loop of the storage layer and the supporting electronic device are transferred together. This is the case with FIG. 21 to FIG. 35, FIG. 39. Similar to 94. Another option is to assemble the supporting electronic device after processing the wafer by using a similar cycle of Figs. 21 to 35 and Figs. 39 to 94. The optical waveguide can then be constructed at low temperatures using a storage layer transfer on the supporting electronic device.

It is precisely because of these functions of the chip that it can support the production of large-capacity non-patent products. Similar to Lego bricks, many different configurable systems can be built with a variety of logical memory and I/O chips. In addition to the alternative shown in Figure 11A, Figure 11F also has a number of features that can be created and incorporated into a 3D configurable system. Such as image sensors, analogs, data acquisition functions, optoelectronic components, non-volatile memory, etc.

Another function of the 3D system after passing through the via is power regulation. In many cases, it can turn off part of the power supply when the integrated circuit is not operating. When the power supply voltage of the external mold may be high, it is advantageous to use a power control distributor of the external mold through the through-hole connections (TSVs) because it uses the old program. High supply voltages make power distribution of controlled molds easier and better controlled.

The components of the configurable system can be built by one or more suppliers, and the supplier should agree on the mold mix and match for the standard interface.

Customized 3D programmable systems are available for general market needs or customer specific needs.

Another advantage of this patent case is that it can be mixed and matched with different programs. It is advantageous to use memory from cutting-edge technology programs, but I/O chips and analog functional molds can be used by older programs of mature technology (as discussed above).

12A through 12E illustrate an integrated circuit system that is a schematic diagram of an integrated circuit system or a configurable system with multiple mold options in a 3D system and in a mold pattern. The 3D structure is shown in the side of Figure 12E. A few molds such as 1204E, 1206E, and 1208E are placed on the same base 1202E, which allows relatively smaller molds to be placed on the same master. For example, mold 1204E may be parallel to the converter mold, while mold 1206E may be an analog data acquisition mold. It is better to combine these molds on different wafers using different programs than to synthesize them on a single system. When the molds are relatively small, they are placed side by side (Fig. 12E) rather than one by one (Fig. 12A-D).

The technology of wearing through holes is constantly improving. In the early days, the vias were 10 microns in diameter and have now grown to less than 1 micron in diameter. However, the density of horizontal connections in the mold using this technique is still much greater than the density of vertical connections.

Another use of the invention is that the logical memory portion is broken down into a plurality of dies that are equal in size and can be integrated into a 3D configurable system. Similarly, it is also possible to divide the memory into multiple molds, as can other functions.

Recent advances in 3D synthesis have demonstrated an effective way for wafer bonding and dicing of these bonded wafers. This combination will form a mold structure as shown in Fig. 12A or Fig. 12D. For 3D assembly technology, it may be better to have different sizes of molds. Moreover, the decomposition of logic functions into vertical synthesis molds can be used to reduce the average length of heavy-duty wires, such as clock signals, data busses, and these components can improve performance.

Another variation of the invention is that the continuous array is adapted (Figs. 10 and 11) for general purpose logic components and even 3D integrated circuitry. For this advanced component setup, the limitations of etching should be considered. Therefore, the rule structure is a suitable choice, and each storage layer can be constructed in the most appropriate mode, in most cases one orientation at a time. In addition, highly vertically connected 3D integrated circuit systems can be efficiently constructed by separating logic memory and I/O chips into dedicated memory layers. For a logical storage layer only, its structure is shown in Figure 76 and Figure 78, which can be fully utilized, as illustrated in Figure 84. Thus, the cyclic logic mode 8402 may be combined into a complete mask. Figure 84A illustrates a cyclic mode of the logic chip of Figure 78B, which is cycled 8x12 times. Figure 84B illustrates the unified logic loop more times to fill a mask. A plurality of surface modes for constructing a logical range can be used for multiple logical storage layers and multiple integrated circuits of a 3D integrated circuit. Such a cyclic structure may comprise a logical memory P and an N transistor, and their corresponding contact layers, even a landing strip connecting the base layers. The interconnection layer of these logical ranges is followed by self-determination or partial customization, depending on the setting method. Custom metal interconnects keep the logic range unused in the cutting line area. A cut line die can also be used to etch unused transistors in the cut line 8404, as shown in Figure 84C.

The continuous logic range can be used with any style of transistor, including those previously shown. Another advantage of some of the previously mentioned 3D memory layer conversion techniques is that it is possible to construct a large-capacity transistor in advance in order to reduce the manufacturing cost of the 3D custom integrated circuit.

Similarly, a memory range can be constructed as a continuous loop memory structure with a mask attached. The non-cyclic component of most memories can be an address decoder, sometimes a current sense line. These acyclic components can be constructed using the underlying storage tier or a logical transistor overlying the storage tier.

Figures 84D-G are schematic illustrations of the range of static random access memory (SRAM). It illustrates six conventional transistor static random access memory (SRAM) cells 8420 controlled by word line (WL) 8422 and bit lines (BL.BLB) 8424 and 8426, which are typically set for static random memory bit lines. Very compact.

The general continuum array 8430 can be a mask field range of static random access memory (SRAM) bit wafers 8420, where the transistor memory layer or even the metal 1 memory layer can be used substantially in all settings. Figure 84E illustrates a continuous array 8430 in which a 4x4 memory block is determined by etching a wafer around the 8434. The memory can be customized through custom metal molds such as metal 2 and metal 3. To control the memory block, word line 8438 and bit line 8436 can be connected through vias below or above the logic range.

Figure 84F illustrates that logic structure 8450 can be built over a logical range to drive word line 8452. Figure 84G illustrates that logic structure 8460 can be built over a logical range to drive word line 8462. Figure 84G also illustrates that read current sense line 8468 can read memory contents from bit line 8462. Similarly, other memory structures can be constructed from unlicensed memory ranges using an unauthorized memory range that is close to the expected memory structure. Similar memories, other memory such as flash memory or dynamic random access memory (DRAM) can contain memory ranges. Moreover, the memory range can be etched at the edge of the projection mold to define the cutting line, which is similar to the logical range shown in Figure 84C.

If a 3D integrated circuit is constructed by using a multi-layer storage layer with different functions, the 3D storage layer can be combined by using the storage layer transfer technology according to the case of the present invention, and the components of the prefabricated combination can be connected by the industry standard through-hole technology.

Another feature of the invention is that the finished patch can be provided for any logic. Here, the 3D integrated circuit technology can construct a complex logic 3D integrated circuit using a multi-layered logic storage layer. In this integrated circuit, it is likely to be satisfactory to repair any common defects in the fabrication of integrated circuits. Patching repeat structures is well known and commonly used in memory, see Figure 41. Another point is to patch arbitrary logic to provide support for current 3D integrated circuit technology and direct write electron beam technology features, such as those provided by Japan Advantec, Fujitsu Microelectronics and Vistec.

Figure 86A illustrates a 3D logic integrated circuit to be repaired. It contains 3 logical storage layers 8602, 8612, 8622 and 8632 to be patched by the upper storage layer. Each logical storage layer has a primary output, and the trigger circuit can be passed to the 8632. The 8632 initially contains a loop structure of unlicensed logic transistors, similar to that shown in Figures 76 and 78.

Figure 87 illustrates the trigger circuit for the logic setting of the repairable 3D integrated circuit. The trigger circuit 8702 includes a branch 8706 to the upper storage layer in addition to the normal output 8704, and the logical storage layer 8632 is patched. For each trigger circuit, there are two lines from the 8632, which is the patch input 8708 and the control 8710. The normal input to the trigger circuit 8712 can be selected through the specially configured multiplexer 8714 to select the normal input 8712 as long as the top level control 8710 is floating. However, once the top level control 8710 activity is reduced, the multiplexer 8714 can optionally patch the input 8708. The effect of the fault input may be greater than the main input. Patching restores all required logic to replace faulty inputs in similar situations.

There are a number of options for inserting new inputs, including the use of programmability, such as the need for a top control line 8710, which switches the original input 8712 multiplexer 8714 to the desired input 8708.

In terms of construction, the 3D integrated circuit chip can pass the full scan inspection. If a defect is detected, a patch can be applied. The patching logic can be set up in the upper storage layer 8632 by using the setting database. Patching logic has access to all basic output as long as it is valid at the top level. Therefore, those outputs that need to be patched can be used for the reconstruction of flawed exact logic. Refactoring logic can enhance certain functions, such as the drive becoming larger or the wire strength becoming larger to compensate for the rise and fall of the long line. Patching logic as an actual replacement for the fault logic 'cone' can be constructed using an authorized transistor on the top memory. The top memory with a custom metal layer is customized by directly writing the electron beam, and the metal layer is determined for each mold on the wafer. The alternate signal 8708 can be coupled to a suitable trigger circuit and become active by the reduced activity of the top level control signal 8710.

The patching process can also be used to enhance performance. If the wafer test contains time measurements, then a slow-performing logic 'cone' may be replaced in a similar manner to the fault logic 'cone' described in the previous paragraph.

Figure 86B is a schematic illustration of a 3D integrated circuit in which the scan chain is set to be limited to one memory layer. This limitation allows each layer of storage to be tested at construction time and is useful in many ways. If the test is performed badly after the end of the circuit layer, the removable wafer no longer continues to build a poorly based 3D circuit layer. In addition, a modular setup can be constructed so that the transfer circuit layer below includes an alternative module for the underlying fault layer, similar to the suggestion of FIG.

The inventive elements of Figures 86A and 86B require wafer inspection during the manufacturing phase, and if the wafer is detected during inspection, it is associated with debris that is in physical contact with the inspection wafer. Figure 86C is a schematic, schematic view of a self-test without contact. With the loop antenna 86C02, RF to DC converter circuit 86C04 and power supply unit 86C06, the contactless power supply collection component collects the electromagnetic energy on the relevant circuit, thereby generating the necessary power supply voltage to operate the self-test circuit and various 3Ds to be tested. IC circuit 86C08. Alternatively, a small photovoltaic cell 86C10 is used to convert the beam energy into a current, which is then converted to the desired voltage via a power supply unit 86C06. Once the circuit is powered up, the microcontroller 86C12 can perform a full scan detection of all existing circuits 86C08. There are two options for self-testing: full scan or BIST (built-in self-test). The test results can be transmitted via radio module 86C14 to a basic device located outside the 3D IC wafer. Such contactless wafer inspection can be used for testing or other applications cited in Figures 86A and 86B, such as wafer-to-wafer or die-to-wafer TSV bonding. An alternative use of contactless detection can be applied to different combinations of the invention. For example, the carrier wafer method can be used to create a wafer transfer layer, while the transistors and the metal layers connecting them form functional electronic circuits. These functional circuits open the validate proper yield through contactless detection; if possible, complete the repair action or turn on internal redundancy. Then through the layer transfer, the detected functional circuit layer is transferred to another processing wafer 808 and then connected using one of the methods previously described.

According to the yield repair setting methodology, almost all of the main output signals 8706 will grow, and almost all of the main input signals 8712 will be replaced by the top 8708 signals.

An additional advantage of the yield repair setting methodology is the ability to reuse the logic layer between one setting and another. For example, a layer of a 3D IC system contains a WiFi transceiver that is being required by a completely different 3D IC. Therefore, it is advantageous to reuse the same WiFi transceiver in the new settings, only by using the receiver as one of the new 3D IC setting layers to achieve NRE (one-time cost) without resetting and saving masks. . The reuse principle can also be applied in many other functions, making 3D ICs tend to be old-style bonding functions, ie PC (printed circuit) boards. In order to ensure the smooth implementation of the concept, the most ideal way is to develop a connectivity standard for connecting the upper and lower lines.

Other applications of these concepts include the use of upper-level tuning of the actual device's clock and its different manufacturing components to achieve the purpose of modifying the clock timing. The scanning circuit can be used to measure the clock pulse phase difference and report it to an external setting tool. The external setting tool can be modified periodically by the clock modification circuit, and then the direct-reading electron beam is used to form the transistor and the upper layer circuit, thereby realizing the better yield and performance flatness of the 3D IC terminal product through the clock modification.

Another way to increase the yield of complex systems by 3D structure is to duplicate the same settings on the two layers superimposed on top and bottom, and use the same BIST setting technique as the above method of identifying and replacing the anomalous logic cone. This should demonstrate that the use of disposable or difficult-to-reverse repair structures (such as anti-fuse or direct-reading dedicated electron beams) during the production phase can be very effective in repairing large numbers of ICs even at low yields. The same repair method can also be, for each power-on sequence (power-on sequence), through the memory-based repair structure described in FIG. 114 below. Help with systems that require self-healing capabilities.

Figure 114 is a schematic illustration of a possible example of this concept. The two upper and lower superimposed logic layers 11401 and 11402 are basically set in the same manner. This setting (all layers are the same) is based on scanning, and the layers 11451 and 11452 that communicate directly or through an external tester contain a BIST controller/verifier. 11421 is a representative first layer flip-flop (FF), and a corresponding FF 11422 on layer 2 is fed to respective identical logic cones 11411 and 11412. The output of flip-flop 11421 is coupled through vertical connection 11406 to the A input of multiplexer 11431 and the B input of multiplexer 11432, while the output of flip flop 11422 is coupled to A input and multiplex of multiplexer 11432 via vertical connection 11405. The input of the device 11431 is B. Each output multiplexer is controlled from control points 11541 and 11442, respectively, and the multiplexer output drives the next logical phase of each layer. Thus, whether logical cone 11411 and flip-flop 11421 or logic cone 11412 and flip-flop 11422, are programmable or selectively coupled to the next logical stage of each layer.

The multiplexer control points 11441 and 11442 are implemented using a memory die, an anti-fuse, or any other custom component, such as a Direct-Write e-Beam machine. If a memory chip is used, its contents can be stored in ROM, flash memory or other non-volatile storage media, or stored in a 3D IC or distributed during system startup, reconfiguration or system maintenance requests, and loaded. The content of the system.

Once enabled, the BCC initializes all multiplexer control programs to select input A and run diagnostic tests on each layer setting. By detecting the fault trigger (FF) on each logic layer through scanning and BIST technology, as long as a pair of corresponding FFs do not fail at the same time, the BCC can communicate with each other (directly or through an external tester) to determine which operation Good FF usage and set multiplexer control programs 11441 and 11442.

If the multiplexer control programs 11441 and 11442 are reprogrammable by the memory wafer, then the test and repair process can occur each time it is turned on or requested, thereby enabling self-healing of the 3D IC in the circuit. If the multiplexer control program can only be programmed once, the diagnostic and repair process is implemented by an external device. Please note that the jointless test and repair techniques described in Figure 86C above can be applied in this case.

Another example of this concept is the use of multiplexing 8714 at the FF input depicted in FIG. In that case, if present, both FF Q and reverse Q can be used.

It is known to those skilled in the art that such a repair method from two substantially identical and superimposed components can be applied to other components than the above FF. Examples include, but are not limited to, analog blocks, I/O, memory, and other components. In this case, the choice of work output requires specialized multiplexing techniques (multiplex technology), but the nature of the technology remains the same.

Those skilled in the art will also recognize that once the two layers of BIST diagnostics are complete, the same mechanism used to determine the multiplexer control program can also be used to selectively cut off power to unused portions of the logic layer, thereby saving Power consumption.

Yet another difference of the present invention is that the vertical stacking method is employed in the fast (fast) repair by a redundancy concept such as three-mode (or higher) redundancy ("TMR"). TMR is a well-known concept in the high-dependency industry, where each circuit produces three copies each, and their output is passed through a majority voting circuit. As long as no more than one single fault occurs in the TMR module, the TMR system can continue to operate without problems. One of the main problems when setting up the TMR IC is that when the circuit is tripled, the interconnect will become much longer and the system will slow down, and the route selection will become more complicated, causing the system to slow down. Another major problem with TMR is that the set process is expensive compared to the larger set size, but the market is limited.

The vertical stacking method provides a natural solution for copying each top system map. Figure 115 illustrates a system containing three layers 11501 11502 11503, where the combinational logic is copied into the logical cones 11151-1, 11511-2, and 11511-3, and the FFs are copied to 11521-1, 11521-2, and 11521- 3. One of the layers 11501 in this paragraph contains a majority voting circuit 11531 that makes a decision between the local FF output 11661 and the vertical stack FF outputs 11552 and 11553, resulting in a need to be assigned to 11541-1, 11541-2, and 11541. -3 and other logical layers of the final fault-tolerant FF output.

Those skilled in the art will appreciate that configuration changes are achievable, such as assigning a separate layer to the voting circuit such that the layers 11501, 11502, and 11503 are logically consistent; relocating the voting circuit to the input of the FF instead of On the output; or extend the redundant copy range to at least 3 times (and overlays).

The above-described method of setting three-mode redundancy (TMR) all mentions the disadvantages at the same time. First, because of the presence of TMR, there is essentially no additional cabling in each layer, and the setting of each layer can be optimized in a single mapping rather than a triple mapping. Secondly, by setting up the vertical stacking of the three original mappings and adding a majority voting circuit to any of the layers, all three layers or a separate layer in Figure 115, any setting in the non-highly dependent market can be minimized. Efforts to achieve TMR setting conversion. The TMR circuit can be shipped from the factory with a known existing error (TMR redundancy mask) or a repair layer added to fix any known errors, thus ensuring higher dependencies.

The cases discussed so far are mainly related to the increase in yield and factory repair issues before shipment of 3D ICs to customers. Another aspect of the present invention provides redundancy and self-healing when distributing 3D ICs in product rates. This is an ideal product feature because defects can occur in the test product even if it is run flawlessly in the factory. For example, the cause of the defect may be a delayed fault mechanism, such as a faulty gate dielectric of the transistor that evolves into a short circuit between the gate and the underlying transistor source, drain or base. After the assembly is completed, the transistor is tested at the factory without errors, but over time and the applied voltage and temperature, the defect can evolve into a fault that can be found in subsequent field tests. Many other delays have been known to the world. Regardless of the nature of the defect, if it introduces a logic error into the 3D IC, it can be detected and repaired using subsequent tests in accordance with the present invention.

In accordance with the present invention, Figure 119 illustrates a 3D IC, indicated at 11900. The 3D IC 11900 includes two layers, each represented by a first layer and a second layer, which are separated by a broken line in the drawing. The first layer and the second layer can be joined to a 3D IC by methods known in the art. The signal between the first layer and the second layer can be electrically coupled through a through-hole via technology (TSV) or other inter-layer technology. The first and second layers each comprise a layer of semiconductor devices, called a transistor layer, and their associated interconnects (implemented in one or more physical metal layers) are called interconnect layers. A transistor layer and one or more interconnect layers are referred to as circuit layers. Each of the first layer and the second layer may include one or more circuit layers of devices and interconnects, depending on the configuration scheme.

Although there are differences in the detailed structure, the first layer and the second layer in the 3D IC 11900 generally employ the same logic function. In some cases, Layers 1 and 2 are packaged separately using the same mask as all layers to reduce production costs. In other cases, there is still a slight deviation in one or more of the mask layers. For example, there is still a choice for a logical layer that produces different logical signals on each layer, which tells the fact that the control logic blocks on Layers 1 and 2 are the first and the first in each important case. 2-layer controller. Other differences between layers exist depending on the settings.

The first layer contains control logic 11910, representative scan flip-flops 11911, 11912, and 11113 and representative combinational logic clouds 11914 and 11915, while the second layer contains control logic 11920, representative scan flip-flops 11921, 11922, and 11923 and representative Logical clouds 11924 and 11925. Control logic 11910 and scan flip-flops 11911, 11912, and 11113 are coupled together to form a scan chain that scans test combinational logic clouds 11914 and 11915 in the manner described above. Control logic 11920 and scan flip-flops 11921, 11922, and 11923 are also coupled together to form a scan chain for group scan test combinational logic clouds 11924 and 11925. Control logic blocks 11910 and 11920 are coupled together to coordinate the testing performed on both layers. In some cases, control logic blocks 11910 and 11920 can test themselves or each other. If one of them is broken, the other can also control the tests performed on Layers 1 and 2.

Those of ordinary skill in the art will readily appreciate that the representative features of the scan chain of Figure 119 are preceded by the fact that millions of triggers are actually set up to form multiple scan chains, and that the principles of the invention disclosed herein are applicable, Not affected by the size and scope of the settings.

As in the previous case, the Layer 1 and Layer 2 scan chains can be used for different test purposes in the factory. For example, the first layer and the second layer may each have an associated repair layer (not shown in FIG. 119) for correcting the defective logic cone that first appears on the first or second layer during the packaging process or Logical block. Alternatively, Layer 1 and Layer 2 share a repair layer.

Figure 120 illustrates a typical scan flip-flop 12000 (portion in the dashed box in the drawing) suitable for use in some of the examples of the present invention. Scan flip-flop 12000 is used for scan flip-flops 11911, 11912, 11113, 11121, 11922, and 11923 in FIG. In Fig. 120 is a D flip-flop 12002 having a Q output coupled to the output of the scan flip-flop 12000Q and a D input coupled to the output of the multiplexer 12004, and a clock input coupled to the CLK signal. Multiplexer 12004 also has a first data entry coupled to the output of multiplexer 12006, coupled to a scan flip-flop 12000 SI (scan input) input, and a select input coupled to the SE (scan open) signal. Multiplexer 12006 also has first and second data registers coupled to the D0 and D1 inputs of scan flip-flop 12000, and a select input coupled to the LAYER_SEL signal.

The SE, LAYER_SEL, and CLK signals are not shown coupled to the input of scan flip-flop 12000 to avoid over-complication of the disclosure - particularly a drawing similar to that of Figure 119, where multiple examples of scan flip-flop 12000 indicate and clear routing The shift is to express the attention of the idea. In the actual setting, all three signals are typically coupled into each respective circuit of scan flip-flop 12000.

When determined, the SE signal will scan the flip-flop 12000 in scan mode causing the multiplexer 12004 gate control SI input to the D input of the D-type flip-flop 12002. Since the signal is turned to all scan flip-flops 12000 in the scan chain, they are connected to form a shift register, causing the vector to shift in and the test result to be shifted out. When the SE is undefined, the multiplexer 12004 selects the output of the multiplexer 12006 to the D input of the D flip-flop 12002.

The CLK signal appears as an "internal" signal, because its starting point will be different due to the choice of settings. In the actual setting, a clock signal (or its variant) is specially wired to each flip-flop in its functional domain. In some scan test overall structures, during function operations, the third multiplexer (not shown in Figure 120) selects CLK from the domain clock; when scanning the test, it selects from the scan clock. In these cases, the SCAN_EN signal will be specifically coupled to the selection input of the third multiplexer so that the D-type flip-flop 12002 can be clocked correctly in both the scan and function modes. In other scan overall architectures, the functional clock is used when the scan clock is in test mode, eliminating the need for an additional multiplexer. Those of ordinary skill in the art are aware that many different scanning overall structures are well known and that the particular scanning overall structure in any given case will depend on the choice of settings and is not limited to the present invention.

The LAYER_SEL signal determines the source of the scan trigger 12000 in normal operation mode. As shown in FIG. 119, input D1 is coupled to the output of a layer (Layer 1 or Layer 2) logic cone where scan flip-flop 12000 is located, and input D0 is coupled to the output of the corresponding logic cone of another layer. The default value of LAYER_SEL is a logical value of -1, and the output of the same layer is selected. Each scan flip-flop 12000 has its own unique ALYER_SEL signal. This allows the defective logic cone on one layer to accept its programmable or selective replacement of the corresponding cone on the other layer. In this case, the signal that is replaced and coupled to D1 is called a fault signal, and the signal that is coupled to D0 is called a repair signal.

Figure 121A illustrates a typical 3D IC, indicated at 12100. As in the case of Fig. 119, the 3D IC 12000 includes two layers, denoted by the first layer and the second layer, respectively, which are separated by a broken line in the drawing. The first layer includes a first prior logic cone 12110, a scan flip flop 12112, and an XOR gate 12114, while the second layer includes a second layer logic cone 12120, a scan flip flop 12122, and an XOR gate 12124. The scan flip-flop 12000 of Figure 120 can be used to scan the flip-flops 12112 and 12122, although SI and other internal connections are not shown in Figure 121A. The output of layer 1 logic cone 12110 (represented by DATA1 in the pattern) is coupled to the D1 input of layer 1 scan flip flop 12112 and the D0 input of layer 2 scan flip flop 12122, respectively. Similarly, the output of layer 2 logic cone 12120 (represented by DATA2 in the pattern) is coupled to the D1 input of layer 2 scan flip-flop 12122 and the D0 input of layer 1 scan flip-flop 12112, respectively. Scan flip-flops 12112 and 12122 have respective LAYER_SEL signals (not shown in Figure 121A) to select between D0 and D1 inputs in the same manner as illustrated in Figure 120.

XOR gate 12114 has a first input coupled to the input of DATA1, a second coupled to the input of DATA2 and an output coupled to signal ERROR1. Similarly, XOR gate 12124 has an input coupled to DATA2, a second coupled to the input of DATA1 and an output coupled to signal ERROR2. If the logic values of the signals on DATA1 and DATA2 are different, ERROR1 and ERROR2 will take a logic value of -1 to indicate that there is a logic error. If the logic values of the signals on DATA1 and DATA2 are the same, ERROR1 and ERROR2 will take a logic value of -0, indicating that there is no logic error. Those of ordinary skill in the art are aware that the assumptions implied here are that one of the logical cones 12110 and 12120 will fail at the same time. Since Layers 1 and 2 have been factory tested, verified, and repaired in some cases, the statistical similarity of the two logic cones that failed in the field, even without any factor repair, is not possible. This confirms this assumption.

In 3D IC 12100, visual setting selection needs to be tested in many different ways. For example, the clock is abruptly aborted, and the status of the ERROR1 and ERROR2 signals is monitored by spot check during the system maintenance phase. Alternatively, the run is aborted and the scan vector is run against the alignment made by each vector. In some cases, a linear feedback shift register commonly used in BIST test schemes is used to generate pseudo-random vectors for cyclic redundancy check. These methods all involve stopping the system from running and entering test mode. Other methods of monitoring possible error conditions in real time are discussed below.

In order to achieve the repair of the 3D IC 12100, two measurements were made: (1) the position of the wrong logic cone, and (2) which of the two corresponding logic cones was operating at that position. Therefore, although there are other methods, the monitoring methods of the ERROR1 and ERROR2 signals and the control methods of the flip-flops 12112 and 12122LAYER_SEL signals are used. In a practical case, the read and write method of the LAYER_SEL signal state is required for factory testing to prove that both the first layer and the second layer are running correctly.

In particular, the LAYER_SEL signal of each scan flip-flop can be stored in a programmable chip, such as a volatile memory circuit as if a latch stores a bit of binary data (not shown in Figure 121A). In some cases, the correct value for each programmable wafer or latch can be determined as a routine for system maintenance when the system is turned on, system reset, or requested. Alternatively, the correct value of each programmable die or latch can be measured and stored earlier in a non-volatile medium such as a flash memory or saved through a programmable anti-fuse inside the 3D IC 12100, or These values can also be stored elsewhere in the system where the 3D IC 12100 is distributed. In those cases, the data stored in the non-volatile medium can be read from one of its storage locations and written to the LAYER_SEL latch in some way.

It is possible to use different ERROR1 and ERROR2 monitoring methods. For example, the ERROR1 and ERROR2 values can be captured through a separate shift register chain on each layer (not shown in Figure 121A), although this can cause large area losses. Alternatively, the ERROR1 and ERROR2 signals can each be coupled to scan flip-flops 12112 and 12122 (not shown in FIG. 121A) and captured after being captured in test mode. This may reduce the cost of scanning trigger manufacturing, but it is still expensive.

The monitoring cost of the ERROR1 and ERROR2 signals can be further reduced if the matching read/write storage of the LAYER_SEL information latch is necessary. In some cases, for example, the LAYER_SEL latch can be coupled to a corresponding scan flip-flop 12000 and read and write its value through the scan chain. Alternatively, the logic cone, scan flip-flop, XOR gate, and LAYER_SEL latch can be addressed using the same addressing circuit.

Figure 121B is a schematic diagram of circuitry for monitoring ERROR2 and controlling its associated LAYER_SEL latch in the 3D IC 12100. Figure 121B includes a 3D IC 12100, a portion of the second layer of circuitry discussed in Figure 121A, including a scan flip flop 12122 and an XOR gate 12124. The first layer includes a substantially identical circuit (not shown in FIG. 121B) and includes a scan flip flop 12112 and an XOR gate 12114.

121B also includes a LAYER_SEL latch 12170 coupled to scan flip-flop 12122 via a LAYER_SEL signal. The value of the data stored in latch 12170 determines which logic cone the scan flip-flop 12122 will employ under normal operation. Latch 12170 is coupled to COL_ADDR line 12174 (column address line), ROW_ADDR line 12176 (row address line), and COL_BIT line 12178. These lines read and write the contents of latch 12170 in the same manner as any of the SRAM circuits of the art known in the art. In some cases, there will be a complementary COL_BIT line with inverse binary data (not shown in Figure 121B). In the logic settings, regardless of the full custom settings, semi-custom settings, gate array or ASIC settings or other setting methods, the scan flip-flops are not neatly arranged in the same way as the memory chips are used in the memory area. In some cases, the scan trigger can be assigned to the virtual row by the tool for addressing purposes, and then the different rows and columns will be routed in the same way as any other signal in the setup.

Using circuitry including N-type via transistors 12182, 12184, 12186 and P-type via transistors 12190 and 12192, the ERROR2 line 12172 can be read at the same address as the latch 12170. N-type via transistor 12182 includes a gate terminal coupled to ERROR2 line 12172, a source terminal coupled to ground, and a drain terminal coupled to the source of N-type via transistor 12184. N-type via transistor 12184 includes a gate terminal coupled to COL_ADDR line 12174, a source terminal coupled to N-type via transistor 12182, and a drain terminal coupled to the source of N-type via transistor 12186. N-type via transistor 12186 includes a gate terminal coupled to ROW_ADDR line 12176, a source terminal coupled to the drain of N-type via transistor 12184, and a source coupled to P-channel transistor 12190 drain and P via line 12188. The drain terminal of the gate of the type via transistor 12192. P-type via transistor 12190 includes a gate terminal coupled to ground, a source terminal coupled to the positive supply, and a drain terminal coupled to line 12188. P-type via transistor 12192 includes a gate terminal coupled to line 12188, a source terminal coupled to the positive supply, and a drain terminal coupled to COL_BIT line 12178.

If the ERROR2 dedicated line 12172 in Figure 121B is not addressed (i.e., either the COL_ADDR line 12174 is equivalent to the ground voltage level (logic value -0)), or the ROW_ADDR line 12176 is equivalent to the voltage level of the ground voltage supply (logical value - 0), then the transistor stack comprising three N-type via transistors 12182, 12184 and 12186 is electrically non-conductive. When the N-type via transistor stack is non-conductive, then as a weaker pull-up component, the P-type pass transistor 12190 will pull the voltage level on line 12188 to the positive supply voltage (logic value -1) The role of the P-type via transistor 12192 is non-conductive, giving the COL_BIT line 12178 high impedance.

The weaker lower pull assembly (not shown in Figure 121B) is coupled to the COL_BIT line 12178. When all of the memory chips coupled to COL_BIT line 12178 are shown to exhibit high impedance, the pull-down component pulls the voltage level to ground (logic value -0).

If the particular ERROR2 line 12172 in Figure 121B is addressed (ie, the COL_ADDR line 12174 and the ROW_ADDR line 12176 are at the positive supply voltage level (logic value -1)), then three N-type via transistors 12182, 12184, and 12186 are included. The transistor stack is non-conductive when the logic value of ERROR2 is -0, and is conductive when the logic value of ERROR2 is -1. In this case, the logic value of ERROR2 can be propagated through P-type via transistors 12190 and 12192 to COL_BIT line 12178.

One advantage of the addressing scheme of Figure 63B is that the broadcast ready mode can be implemented by synchronous addressing of rows and columns, as well as monitoring of all column bit lines 12178. When all column bit lines 12178 are logic value -0, all ERROR2 signals are logic value -0, indicating that there are no broken logic cones on layer 2. With the relatively small number of correctable errors in the field, a large number of incorrect positioning times can be saved by using the scan trigger method. If one or more of the bit lines are logically -1, then the faulty logic cone will only exist on those columns, and the row address will quickly cycle through to find their exact address. Another advantage of this scheme is that in the on or reassert mode, a large number or all of the LAYER_SEL latches can be quickly initialized to the default logic value of -1 at the same time.

At each location where the faulty logic cone (if any) exists, the defect is isolated to a particular layer, so that the correctly functioning logic cone can be placed on the first and second layers of the corresponding scan flip-flop select. If there is a large non-volatile memory in the 3D IC 12100 or external system, then the Automatic Test Code Generation (ATPG) vector will be applied in the same way as the factory repair case. In this case, the scan itself has the ability to determine the position and operate the layer correctly. Unfortunately, this scan requires a large amount of vector and a fairly large amount of non-volatile memory that is not available in all cases.

The advantage of using some form of built-in self-test (BIST) method is that it is included in the 3D IC 12100 without the need to store a large number of test vectors. Unfortunately, BIST testing tends to be "qualified" or "failed", although it is known to have errors, but it is not particularly good at diagnosing the location or nature of the fault. Fortunately, the BIST technique and the corresponding setting method can be used to quickly determine the correct value of the LAYER_SEL latch during the above error signal monitoring process.

Figure 122 is a diagram showing an example of the use in the 3D IC, see the typical portion of the logical setting such as 11900 in Figure 119 and 12100 in Figure 121A. The logic settings can be seen in layers 1 and 2 with roughly the same gate level case. Preferably, all of the flip-flops in the setup (not shown in Figure 122) employ a scan flip-flop similar or identical to scan flip-flop 12000 of Figure 120. Preferably, all of the scan flip-flops on each layer are interconnected with corresponding scan flip-flops on another layer, as described in connection with FIG. 121A. Preferably, each scan flip-flop is equipped with an associated error signal generator (such as an XOR gate) to detect the presence of the error logic cone and the LAYER_SEL register, thereby controlling which logic cone is fed to the trigger in normal operation mode, combined Figures 121A and 121B are presented together.

In Figure 122 there is a typical logic function block (LFB) 12200. Typically, the LFB 12200 has many inputs, the case reference number is 12202, and many outputs, the case reference number is 12204. Preferably, the LFB 12200 is set in a hierarchical manner, indicating that it has a special smaller logical function block, which is specifically described in the text by 12210 and 12220. The internal circuitry of LFBs 12210 and 12220 is considered to be at a lower level of the hierarchy than the circuitry considered to be at the top level of the LFB 12200 at a higher level. The LFB 12200 is for example only. Many other configurations are also possible. Inside the LFB 7500, there are at least (at most) two initialized LFBs. Also not shown within the LFB 12200 of Figure 122, there will be initialization of separate logic gates and other circuitry to avoid overcomplicating the disclosure. The LFBs 12210 and 12220 have smaller internal initialization modules that form even lower levels in the hierarchy. Likewise, the logic function block 12200 itself may also be initialized in another LFB with an even higher level in the overall setting hierarchy.

A linear feedback shift register (LFSR) circuit 12230 is included in the LFB 12200 to generate a pseudo-random input vector for the LFB 12200 in a manner well known in the art. In FIG. 122, a one bit LFSR 12230 is associated with each input 12202 of the LFB 12200. If input 12202 is directly coupled to a flip-flop (preferably a scan trigger similar to 12000), then the scan flip-flop can be modified to provide additional LFSR functionality to generate a pseudo-random input vector. If input 12202 is directly coupled to the combinatorial logic, it is intercepted in test mode and its value is determined and replaced by a corresponding bit in LFSR 12230 during the test. Alternatively, LFSR circuit 12230 will intercept all input signals during the test, regardless of the type of circuit it is connected to internal LFB 12200.

Therefore, in the BIST test, all inputs to the LFB 12200 can be pseudo-random input vectors generated by the LSFR 12230. As known in the art, the LSFR 12230 can be a single LSFR or a plurality of smaller LSFRs, depending on the choice of settings. The LSFR 12230 preferably employs a primitive polynomial to generate a pseudo-random vector of a maximum length sequence. The LSFR 12230 needs to be seeded to a known value so that the sequence of pseudo-random vectors is deterministic. The seeding logic can take the inexpensive method inside the LSFR 12230 trigger and initialize it by responding to the re-signing signal.

A cyclic redundancy check (CRC) circuit 12232 is also included in the LFB 12200 to generate a response LFSR 12230 that produces a pseudo-random input vector in a manner well known in the art to produce the characteristics of the LFB 12200 output. In FIG. 122, a one bit CRC 12232 is associated with each output 12204 of the LFB 12200. If the output 12204 is directly coupled to a flip-flop (preferably a scan flip-flop similar to 12000), then the scan flip-flop can be modified to provide additional CRC functionality to generate features. Alternatively, all bits of the CRC will negatively monitor the output regardless of the source of the signal within the LFB 12200.

Therefore, in the BIST test, all outputs of the LFB 12200 can be determined to respond to the pseudo-random input generated by LSFR 12230 after analysis, in response to the correctness of the provided stimulus. According to this technique, the CRC 12232 can be a single CRC or a plurality of smaller CRCs, depending on the choice of settings. According to this technique, the CRC circuit is a special case of LSFR, and its additional circuit can incorporate the observed data into the pseudo-random code sequence generated by the base LSFR. The CRC 12232 preferably employs a primitive polynomial to generate a pseudo-random encoding of the largest sequence. The CRC 12232 needs to be seeded to a known value so that the characteristics of the pseudo-random input vector generation are deterministic. The seeding logic can take the inexpensive method inside the LSFR 12230 trigger and initialize it by responding to the re-signing signal. After the test is completed, the value in CRC 12232 is compared to the known value of the feature. If all bits in the CRC 12232 match, the identification is valid and the LFB 12200 is considered to be operational. If one or more of the bits in the CRC 12232 do not match, the identification is invalid and the LFB 12200 is considered to be operating incorrectly. The expected characteristic value can be taken as a cheaper internal CRC 12232 trigger and compared internally to a CRC 12232 that responds to an evaluation signal.

As shown in FIG. 122, LFB 12210 includes LFSR circuit 12212, CRC circuit 12214, and logic function 12216. Since its input/output structure is similar to the input/output structure of the LFB 12200, it can be tested in a smaller proportion in the same way. If the 12200 is initialized to a larger block with the same input/output structure, the 12200 can be tested as part of that larger block or tested separately, depending on the settings chosen. If there is no need for separate testing, then all blocks in the hierarchy do not necessarily have to have an input/output structure. An example is to illustrate that the LFB 12220 is initialized in the LFB 12200, while the LFB 12220 has no LFSR circuitry on the input, has no CRC circuitry on the output, and is tested concurrently with the rest of the LFB 12200.

Those of ordinary skill in the art are aware that other BIST test methods are well known in the art, and any one of the methods can be used to determine that the LFB 12200 is functioning well or is malfunctioning.

By using the block BIST method to repair the 3D IC of the 3D IC 12100 in FIG. 121A, the component is placed in the test mode, and the DATA1 and DATA2 signals of the respective scan flip-flops 12000 on the first layer and the second layer are compared, and Monitor the ERROR1 and ERROR2 composite signals described in the above case, or use other methods to monitor if possible. The location of the faulty logic cone is determined by its position in the logic setting hierarchy. For example, if the faulty logic cone is inside the LFB 12210, then only the BIST program for that block can run on both Layer 1 and Layer 2. The results of the two tests determine which block (and which logic cone is implied) is working well and which block is running. Then the corresponding LAYER_SEL latch of the scan flip-flop 12000 can be set, so that each latch can receive the repair signal from the functional logic cone and ignore the fault signal, so that in the short-term without expensive ATPG test, Complete the layer measurement of common hardware costs.

Figure 123 shows an alternative case with on-site repair capabilities with independent logic cones. A typical 3D IC, represented at 12300, consists of two layers, denoted by Layer 1 and Layer 2, respectively, separated by dashed lines in the drawing. The first layer and the second layer are bonded together to form the 3D IC 12300 by methods known in the art and interconnected by TSV or other interlayer interconnection techniques. The first layer consists of control logic block 12310, scan flip-flops 12311 and 12312, multiplexers 12313 and 12314, and a logic cone 12315. Similarly, Layer 2 consists of control logic block 12320, scan flip-flops 12321 and 123222, multiplexers 12323 and 12324, and a logic cone 12325.

In layer 1, scan flip-flops 12311 and 12312 are coupled in series with control logic block 12310 to form a scan chain. Scan flip flops 12311 and 12312 can be a conventional type of scan flip flop known in the art. The Q outputs of scan flip-flops 12311 and 12312 are each coupled to D1 data registers of multiplexers 12313 and 12314. A typical logic cone 12315 has an output coupled to a typical input of multiplexer 12313 and another output coupled to a D input of scan flip flop 12312.

At layer 2, scan flip-flops 12321 and 12322 are coupled in series with control logic block 12320 to form a scan chain. Scan flip-flops 12321 and 12322 can be a conventional type of scan flip-flop known in the art. The Q outputs of scan flip-flops 12321 and 12312 are each coupled to the D1 data registers of multiplexers 12323 and 12324. A typical logic cone 12325 has an output coupled to a typical input of multiplexer 12323 and another output coupled to a D input of scan flip flop 12322.

The Q output of the scan flip-flop 12311 is coupled to the D0 input of the multiplexer 12323, the Q output of the scan flip-flop 12321 is coupled to the D0 input of the multiplexer 12313, and the Q output of the scan flip-flop 12312 is coupled to, multiplexed The D0 input of the 12324 is coupled to, and the Q output of the scan flip-flop 12322 is coupled to the D0 input of the multiplexer 12314. Control logic block 12310 is coupled to control logic block 12320 in a manner that coordinates inter-layer test functions. In some cases, control logic blocks 12310 and 12320 can test themselves or test each other, and when one of them fails, the other can simultaneously control the tests on both layers. These interlayer couplings can be achieved through TSV or other inter-layer interconnect techniques.

The logic function on layer 1 is roughly the same as the logic function on layer 2. The case of the 3D IC 12300 in FIG. 123 is similar to the case of the 3D IC 11900 in FIG. 11900, the main difference being: in the typical scan flip-flop 12000 of FIG. 120 and the 3D IC 11900 of FIG. 119, for logic A multiplexer that replaces the layer between programmable or selective cross-couplings, with the position immediately following the scan flip-flop, not the front.

Figure 124 is a schematic illustration of a typical 3D IC, indicated at 12400, which is also patterned in this manner. A typical 3D IC 12400 consists of two layers, each represented by a first layer and a second layer, separated by dashed lines in the drawing. The first layer and the second layer are bonded together to form a 3D IC 12300 and interconnected by TSV or other interlayer interconnection techniques. The first layer consists of a layer 1 logic cone 12410, a scan flip flop 12412, a multiplexer 12414 and an XOR gate 12416. Similarly, layer 2 consists of a layer 2 logic cone 12420, a scan flip flop 12422, a multiplexer 12424, and an XOR gate 12426.

The first layer logic cone 12410 and the second layer logic cone 12420 are implemented with substantially the same logic function. To detect the found faulty logic cone, the outputs of the logic cones 12410 and 12420 are captured in scan flip-flops 12412 and 12422, respectively, in test mode. The Q outputs of scan flip flops 12412 and 1262 are represented in Figures 124 by Q1 and Q2, respectively. Q1 and Q2 are compared by XOR gates 12416 and 12426 to generate error signals ERROR1 and ERROR2, respectively. Multiplexers 12414 and 12424 each have a select input coupled to a layer select latch (not shown in Figure 124), preferably located in the layer of the respective multiplexer, and the multiplexer Relatively in the vicinity, Q1 and Q2 are selectively or programmable coupled to DATA1 or DATA2.

In the case described with reference to Figures 121A, 121B and 122, all ERROR1 and ERROR2 evaluation methods can be used to evaluate ERROR1 and ERROR2 in Figure 124. Similarly, once ERROR1 and ERROR2 are evaluated, the correct value can be applied to the layer select latches of multiplexers 12414 and 12424 to implement a logic cone replacement, if necessary. In this case, the logical cone replacement also includes an alternative correlation scan trigger.

Figure 125A shows a typical case of a more economical approach to on-site repair. A typical 3D IC 12400, represented at 12500, comprises two layers, each represented by a first layer and a second layer, separated by dashed lines in the drawings. The first layer and the second layer each comprise at least one circuit layer. The first and second layers are joined to form a 3D IC 12500 by methods known in the art and interconnected by TSV or other interlayer interconnection techniques. Each layer also contains a logical function block 12510 case, which in turn constitutes a logical function block 12520 case. In a manner similar to that described for LFB 12200 in FIG. 122, LFB 12520 includes an LSFR circuit on its input (not shown in FIG. 125A) and a CRC circuit on its output (not shown in FIG. 125A). .

Each of the LFB 12520 has a number of multiplexers 12522 associated with the input and a multiplexer 12524 associated with the output. These multiplexers are either programmable or selectively replaced by corresponding portions on layer 1 or layer 2, and all cases of LFB 12520 on layer 1 or layer 2.

Different blocks in the hierarchy can be tested when a request to open, reconfigure, or request from the 3D IC 12500 internal control logic, or elsewhere in the system where the 3D IC 12500 is distributed. Fault blocks that are at any level of the hierarchy and have BIST capabilities can be programmed and selectively replaced by corresponding cases on another layer. Since this is determined at the blocking level, this resolution can be made locally by the BIST control logic on each block (not shown in Figure 125A), although it is also necessary to coordinate the higher level blocks in the hierarchy, The multiplexer 12522 provides an input to which layer of the functional LFB 12520 in the case of multiple repairs within the same range in the set hierarchy. Since the first and second layers are preferably fully operational or almost fully operational, a simple method can be used to designate one of the two layers, such as the first layer, as the primary functional layer. Thereafter, each block of BIST controllers will be locally coordinated and will decide which block has the inputs and outputs coupled to Layer 1, via Layer 1 multiplexers 12522 and 12524.

Those of ordinary skill in the art are aware that the use of such a case can save a lot of space. For example, because of the substitution, independent logic cones, and only the LFBs are evaluated, then each of the independent flip-flop layers, like the multiplexer 12006 of Figure 120, and the multiplexer 12414 of Figure 124, selects the multiplexer. Can be removed along with the LAYER_SEL latch 12179 in Figure 121B, since this function is now implemented by the majority of the multiplexers 12522 and 12524 in Figure 125A, all of which can be controlled by one or more parallels. Signal, control. Similarly, an error signal generator (such as XOR gates 12114 and 12124 in Figure 121A and 12416 and 7826 in Figure 124) and any circuitry that needs to read them (e.g., couple them to a scan flip-flop), or The addressing circuit in Figure 121B should also be removed, as in this case all logic function blocks, rather than separate logic cones, are replaced.

The scan chain can be removed even in some cases, although this is determined by the choice of settings. In the case of removing the scan chain, factory testing and repair must also rely on the block BIST circuit. When a bad block is detected, the repair layer must make a brand new block with electron beam meditation. In particular, since more patterns need to be formed, this is more time consuming than making alternative logic cones, and the space savings need to be compared to the test time loss to determine an economically viable solution.

The risk of setting up the early stages of debugging and prototyping is included with the removal of the scan chain, as the BIST circuit is still lacking in diagnosing the nature of the problem. If the setting itself has a problem, the scan test does not exist, it will increase the difficulty of finding and solving the problem, and the cost of losing the market opportunity is very huge and difficult to quantify. Careful cue to leave the scan chain for reasons unrelated to the field repair aspect of the present invention.

Another advantage of the case of using the block BIST method is described in Figure 125B. One advantage of some earlier cases is that most of the circuits on Layers 1 and 2 are active circuits during normal operation. Therefore, by operating a single block case located on one of the two layers, power can be greatly reduced for earlier cases.

Figure 125B includes 3D IC 12500, Layer 1 and Layer 2, two cases of LFB 12510 and 12520, and the majority of multiplexers 12522 and 12524 previously discussed. Figure 125B also includes a power selection multiplexing rate 12530 associated with the layer mode LFB 12520. Each power selection multiplexer 12530 has a coupled to its associated LFB 12520 power terminal output, a first select input coupled to a positive supply (shown as VCC in the drawing), and a second input coupled to a ground potential supply (in the drawing, it is indicated by GND). Each power selection multiplexer 12530 has a selection input (not shown in Figure 125B) coupled to control logic (not shown in Figure 125B) and exists in duplicates in layers 1 and On the 2nd floor, although it may be located elsewhere in the 3D IC 12500, or elsewhere in the system where the 3D IC 12500 is distributed.

It is known to those skilled in the art that there are many ways to programmably or selectively stop a block located in an integrated circuit known in the art, and the power multiplexer 12530 used in the case of Figure 125B is only For example purposes. Any method of stopping LFB 12520 is a civilized content. For example, a power switch can be used for both VCC and GND. Alternatively, when VCC is decoupled from the LFB 12530, the GND power switch can be ignored and the power node can be allowed to "float" to the ground. In some cases, the VCC can be controlled by a transistor, like the source output controlled by the regulator itself, or the emitter output, and the VCC can be removed by masking or cutting the transistor. Many other alternatives are also possible.

In some cases, the control logic (not shown in Figure 125B) uses the BIST circuit present in each block to stitch a single copy setting (using the majority of the input and output multiplexers per block, its function and LFB) The 12520-related majority multiplexers 12522 and 12524 are similar) and contain functional copies of all LFBs. If the map is complete, the power to all failed LFBs and unused functional LFBs is turned off by their associated power selective multiplexers (similar to power select multiplexer 12530). Therefore, by using the standard two-dimensional integrated circuit technology, the power saving to the single copy setting can be achieved.

Alternatively, if a layer, such as Layer 1, is selected as the primary layer, then the BIST controller in each block can independently decide which mode block to use. The set values of the plurality of multiplexers 12522 and 12524 are then set to couple the used blocks to the first layer, and the set values of the plurality of multiplexers 12530 are set to cut off the unused blocks. It is worth mentioning that this can save half of the power consumption in the case of not using the power selection multiplexer 12530 or equivalent multiplexer.

The testing techniques known in the art are a compromise between the detailed diagnostic capabilities of scanning tests and the simplicity of BIST testing. In the case of these schemes, each BIST block (small than the typical LFB, but containing tens to hundreds of logic cones) stores a small number of initial states, especially scan flip-flops, and most scan triggers The default value can be used. The CAD tool is used to analyze the set netlist to determine the necessary scan triggers for efficient testing.

In the test mode, after the BIST controller moves into the initial value, it starts to set the timing. The BIST controller has a feature register, possibly a CRC or other circuit that monitors the bits inside the test block. After a preset number of clock cycles, the BIST controller stops setting the timing, removes the data stored in the scan trigger, and adds their contents to the block features, and features and a small number of storage features (stored in the initial state One) to make an alignment.

This method has the advantage of not requiring a large amount of stored scan vectors and a simple "qualified" or "failed" BIST test. The test block is not as detailed as the single fault logic cone, but much coarser than the large logic function block. In general, the finer the test granularity (ie, the smaller the circuit size of the faulty circuit is replaced), the less likely the delay of the same test block on the first and second layers is. Once the functional state of the BIST block is determined, the appropriate value can be written to the latch of the control layer multiplexer to replace the failed BIST block on the layer, if necessary. In some cases, faulty and unused BIST blocks cut power and save power.

To date, the discussion of the different typical cases, with respect to their own discovery and repair of logical cones or logic blocks of defects in static test mode, the inventive case can find fault addresses due to noise or timing problems. For example, in 3D IC 11900 of Figure 119, and 3D IC 12300 of Figure 123, a full chain test is performed using a scan chain in a manner known in the art. Method one involves moving the vector through the scan chain, using at least two full-speed clock pulses, and then shifting the result through the scan chain. This captures the logic cone that runs without error during low-speed testing, but it runs too slowly and can't work in the circuit at full clock speed. But this approach makes on-site repair of slow logic cones possible, requiring the time, intelligence, and storage capacity necessary to store, run, and evaluate scan vectors.

Another method is to use the block BIST test when opening, resetting, or requesting, overclocking each block in increasing frequency until a failure occurs, determining which layer mode runs faster, and then using it in each case set. The faster block replaces the slower block. This method has more common time, intelligence, and storage requirements associated with block BIST testing, but it still requires placement of 3D ICs in test mode.

Figure 126 illustrates an example where errors due to slow logic cones can be monitored instantaneously while the circuit is in normal operating mode. A typical 3D IC, represented at 12600, consists of two layers, each represented by a first layer and a second layer, separated by dashed lines in the drawing. Each layer contains one or more circuit layers and is bonded to form a 3D IC 12600. The layers can be electrically coupled through TSV or other inter-layer interconnect technology.

Figure 126 is primarily a circuit operation coupled to the output of a single layer 2 logic cone 12620, although substantially uniform circuitry also appears in layer 1 (not shown in Figure 82). 126 also includes a D input coupled to the second layer logic cone 12620 output, and a Q output coupled to the scan flip flop 12622 of the D1 input of the multiplexer 12624 via the interlayer line 12612 (shown as Q2 in the drawing). Multiplexer 12624 has an output DATA2 that is coupled to a logic cone (not shown in FIG. 126), and the other input couples the first layer of flip-flops through inter-layer line 12610 to flip-flop 12622 (not shown in the drawing) D0.

XOR gate 12626 has an input coupled to the first input of Q1, coupled to the second input of Q2 and to the output of the first input of AND gate 12646. AND gate 12646, while the other input has a second input coupled to TEST_EN line 12648 and a set input coupled to RS flip-flop 3828. The RS flip-flop has an output coupled to the reset input of the layer 2 reset line 12630, and the other output is coupled to the first input of the OR gate 12632 and the N-type pass transistor 12638. OR gate 12632 has an output coupled to the second input of layer 2 OR link input line 12634, and the other output is coupled to layer 2 OR link output line 12636.

Layer 2 control logic (not shown in FIG. 126) controls the operations of XOR gate 12626, AND gate 12646, RS flip-flop 12628, and OR gate 12636. The TEST_EN line 12648 is used to mask the testing process of Q1 and Q2. Ideally, for example, a functional error has been fixed, and the difference between Q1 and Q2 has been routinely expected and may interfere with the background testing process for locating marginal timing errors.

In addition to all other RS flip-flops associated with other logic cones on layer 2, layer 2 reset line 12630 also resets the internal state of RS flip-flop 12628 to a logic value of -0. OR gate 12632 is coupled with all other OR gates associated with the other logic cones of layer 2 to form a large layer 2 OR function coupled to the layer 2 RS flip-flop (12628 in Figure 126). If all RS flip-flops are reset to a logic value of -0, the output of the assigned OR function is a logic value of -0. If a logic state difference occurs between the flip-flops that generate the Q1 and Q2 signals, the XOR gate 12626 displays the logic value -1 through the AND gate 12646 (if TEST_EN = logic value -1) to the set input of the RS flip-flop 12628, causing it to The state is changed and the logical value -1 is displayed on the first input of the OR gate 12632, which in turn generates a logical value of -1 at the layer 2 assigned OR function (not shown in Figure 126), prompting the control logic (not In the figure, there is an error.

Control logic can use stacked N-type via transistors 12638, 12640, and 12642 to determine the location of the error generating logic cone. Transistor 12638 includes a gate terminal coupled to the output of RS flip-flop 12628 Q, one drain terminal coupled to the source terminal of the ground and the other drain terminal coupled to the source of transistor 12640. The transistor 12640 includes a gate terminal coupled to the row address line ROW_ADDR line, one drain terminal coupled to the source terminal of the drain of the transistor 12638 and the other drain terminal coupled to the source of the transistor 12642. The transistor 12642 includes a gate terminal coupled to the column address line COL_ADDR line, one drain terminal coupled to the drain of the transistor 12640 and the other drain terminal coupled to the sense line SENSE.

The row and address addresses are virtual addresses because the position of the triggers is not neatly arranged in the rows and columns in the logic setting. In some cases, the netlist is modified by a computer-aided setting (CAD) tool to properly address each logic cone, and then the ROW_ADDR and COL_ADDR signals can be routed like any other signal in the setup.

This creates an efficient way to control the logic loop through the virtual address space. If COL_ADDR = ROW_ADDR = logic value -1 and the RS flip-flop state is a logic value -1, then the transistor stack will control SENSE = logic value -1. Therefore, the logical value -1 only occurs at the virtual address location where the RS trigger captures the error. Once an error is found, the RS flip-flop 12628 can be reset to a logic value of -0 along with the layer 2 reset line 12630 so that another possible error can be found.

Setting control logic handles errors in one of many ways. For example, if an error is logged and a logic error occurs repeatedly at the same logical cone position, the test mode is entered to determine if the location needs to be repaired. This is a good way to deal with intermittent errors caused by noise problems and occasional failures, but under normal testing, the marginal logic cones that pass the test pass. Alternatively, action can be taken when the first error notification is received, depending on the settings selected.

According to Figure 27 above, the three-mode redundancy (TMR) is used in the logic cone, and it can also be operated as an effective field repair method, although it does generate high-level redundancy, masking rather than repairing the faulty mechanism or The error caused by the marginal slow logic cone. If factory repairs are used to verify that all equivalent logic cones on each layer are tested before the 3D IC is shipped, the redundancy level will be higher. The cost of comparing the three and two layers, with or without the repair layer, must be taken into account when determining the best case to apply.

Figure 127 illustrates an alternative TMR method in a typical 3D IC 12700. In Figure 127, there are many nearly identical layers, designated as Layer 1, Layer 2, and Layer 3, respectively, separated by dashed lines in the drawings. The first layer, the second layer, and the third layer each include one or more circuit layers. And joined to form a 3D IC 12700 that uses methods known in the art. The first layer is composed of a first layer logic cone 12710, a flip flop 12714, and a three majority (MAJ3) gate 12716. The second layer includes a layer 2 logic cone 12720, a flip flop 12724, and a MAJ3 gate 12726. The third layer includes a layer 3 logic cone 12730, a flip flop 12734, and a MAJ3 gate 12736.

The logic cones 12710, 12720, and 12730 perform almost the same logic function. Triggers 12714, 12724, and 12734 prefer scan triggers. If a repair layer is present (not shown in Figure 127), the flip-flop 2502 of Figure 25 can be used to repair the defective logic cone of the 3D IC 12700 prior to shipment. The MAJ3 gates 12716, 12726, and 12736 compare the outputs of the three flip-flops 12714, 12724, and 12734 and output a logic value that is consistent with most of the inputs. If two or three of the three inputs are equal to a logic value of -0, the MAJ3 gate will output a logic value of -1. So when one of the three logic cones or one of the three triggers has a defect, the correct logical value appears for the output of all three MAJ3 gates.

One of the advantages of the case in Figure 127 is that the first, second or third layer can be packaged using all or nearly the same mask. Another advantage is that MAJ3 gates 12716, 12726, and 12736 can also operate effectively as single event flip (SEU) filtering to ensure high dependency or radiation resistant applications as described in Rezgui cited above.

Another typical TMR 12800 in Figure 128 introduces another TMR case. In this case, the MAJ3 gate is placed between the logic cone and its respective trigger. In Fig. 128, there are almost the same layers, which are denoted by the first layer, the second layer and the third layer, respectively, and are separated by a broken line in the drawing. The first layer, the second layer, and the third layer each include one or more circuit layers and are bonded to a single piece to form a 3D IC 12800 using methods known in the art. The first layer consists of a first layer logic cone 12810, a flip flop 12814, and a three majority (MAJ3) gate 12812. The second layer includes a layer 2 logic cone 12820, a flip-flop 12824, and a MAJ3 gate 12822. The third layer includes a layer 3 logic cone 12830, a flip flop 12834, and a MAJ3 gate 12832.

Logic cones 12810, 12820, and 12830 perform almost the same logic function. Triggers 12814, 12824, and 12834 prefer scan triggers. If a repair layer is present (not shown in Figure 128), the flip-flop 2502 of Figure 25 can be used to repair the defective logic cone of the 3D IC 12800 before shipment. The MAJ3 gates 12812, 12822, and 12832 compare the outputs of the three logic cones 12810, 12820, and 12830 to output a logical value that is consistent with most of the inputs. So when one of the three logic cones is defective, the correct logical value appears for the output of all three MAJ3 gates.

One of the advantages of the case in Figure 128 is that the first, second or third layer can be packaged using all or nearly the same mask. Another advantage is that MAJ3 gates 12712, 12722, and 12732 can also operate effectively as single event transient (SET) filtering to ensure high dependency or radiation resistant applications as described in Rezgui, cited above.

Another typical TMR 12900 in Figure 129 introduces another TMR case. In this case, the MAJ3 gate is placed between the logic cone and its respective trigger. There are almost the same layers in Fig. 129, which are denoted by the first layer, the second layer and the third layer, respectively, and are separated by a broken line in the drawing. The first layer, the second layer, and the third layer, each comprising one or more circuit layers, are bonded together to form a 3D IC 12900 using methods known in the art. The first layer consists of a layer 1 logical cone 12910, a flip-flop 12914, and three majority (MAJ3) gates 12912 and 12916. The second layer includes a layer 2 logic cone 12920, a flip-flop 12924, and MAJ3 gates 12922 and 12926. The third layer includes a layer 3 logic cone 12930, a flip flop 12934, and MAJ3 gates 12932 and 12936.

The logic cones 12910, 12920, and 12930 perform almost the same logic function. Triggers 12914, 12924, and 12934 prefer scan triggers. If a repair layer is present (not shown in Figure 129), the flip-flop 2502 of Figure 25 can be used to repair the defective logic cone of the 3D IC 12900 before shipment. The MAJ3 gates 12912, 12922, and 12932 compare the outputs of the three logic cones 12910, 12920, and 12930 to output a logical value that is consistent with the majority of the input. Similarly, MAJ3 gates 12916, 12926, and 12936 compare the outputs of the three flip-flops 12914, 12924, and 12934 to output a logical value that is consistent with the majority of the input. So when one of the three logic cones or one of the three triggers has a defect, the correct logical value appears for the output of all six MAJ3 gates.

One of the advantages of the case in Figure 129 is that the first, second or third layer can be packaged using all or nearly the same mask. Another advantage is that MAJ3 gates 12712, 12722 and 12732 can also be effectively operated as single event transient (SET) filtering. MAJ3 gates 12716, 12726 and 12736 can also be effectively operated as single event flip (SEU) filtering to ensure the above reference. High dependence or anti-radiation applications described in Rezgui.

Some of the cases of the present invention can be applied to a large number of commercial and highly dependent aerospace and military fields. The ability to solve defects in the factory with a repair layer, combined with the ability to automatically resolve delay defects (masking with a three-layer TMR case or replacing a faulty circuit with a two-layer replacement case) compared to traditional two-dimensional integrated circuit (IC) technology In contrast, the creation of larger and more complex three-dimensional systems is possible. These various aspects of the invention can coordinate the cost requirements of the target application area.

In accordance with some aspects of the invention, in order to reduce the cost of the 3D IC, it is preferred to use the same mask set in the fabrication of each layer. This can be done by making the same VIAS structure on each layer in an appropriate manner and then compensating for the expected amount by aligning the 1st and 2nd layers.

Figure 130A illustrates a via mode 13000 located on a first layer of 3D ICs 11900, 12100, 12200, 12300, 12400, 12500, and 12600 as described above. The metal laminations on each of the via locations 13012, 13004, 13006, and 13008 are present on at least the lower metal layer of the first layer. The via mode 13000 occurs close to each repair or replacement multiplexer on the first layer, while the via metal laminations 13002 and 13004 (where L1/D0 represents the first layer input D0) are coupled to that location. On the D0 multiplexer input, via metal laminations 13006 and 13008 (in the figure, L1/D1 represents the first layer input D1) are coupled to the D1 multiplexer input.

Similarly, Figure 130B illustrates a substantially uniform via pattern 13010 located on a second layer of 3D ICs 11900, 12100, 12200, 12300, 12400, 12500, and 12600 as described above. The metal laminations on each of the via locations 13012, 13014, 13016, and 13018 are present on at least the lower metal layer above the second layer. The via mode 13010 occurs near each repair or replacement multiplexer on the second layer, while the via metal laminations 13012 and 13014 (where L2/D0 represents the second layer input D0) are coupled to that location. On the D0 multiplexer input, via metal laminations 13016 and 13018 (in the figure, L2/D1 represents the second layer input D1) are coupled to the D1 multiplexer input.

Figure 130C is a top plan view of via patterns 13000 and 13010 aligned and supplemented by a layer interconnect pitch. Inter-layer interconnects can be implemented via TSV or other inter-layer interconnect techniques. The metal laminates 13002, 13004, 13006, 13008, 13012, 13014, 13016 and 13018 discussed above are included in FIG. 130C. In Fig. 130C, the second layer is supplemented by the inter-layer connection pitch located on the right side of the first layer. However, the addition results in a physical stack of through-hole metal laminations 13004 and 13018. As such, the supplement will also result in a physical stack of via stacks 13006 and 13012. If the via via technique or other inter-layer vertical coupling point is at these two overlapping locations (by a single mask), the second layer multiplexer input D1 is coupled to the layer 1 multiplexer input D0, and The layer 2 multiplexer input D0 is coupled to the layer 1 multiplexer input D1. This is the inter-layer connection topology technique necessary to implement the repair or replacement of logic cones and functional blocks in the cases described in Figures 121A and 123.

Figure 130D is a side view showing the structure of the method described with reference to Figures 130A, 130B and 130C. Figure 130D shows a typical 3D IC, indicated at 13020, consisting of two cases of layer 13030, which are the top case represented by the second layer in the drawing and the bottom case represented by the first layer. Each of the layers 13020 includes a typical transistor 13031, a typical contact 13032, a typical metal 1 13033, a typical via 1 13034, a typical metal 2 13035, a typical via 2 13036, and a typical metal 3 13037. The dotted ellipse indicated by 13000 refers to the first layer portion corresponding to the via pattern 13000 in FIGS. 130A and 130C. Similarly, the dashed oval indicated by 13010 refers to the second layer portion corresponding to the via pattern 13010 in FIGS. 130B and 130C. In this case, for example, an interlayer via of the TSV 13040 couples the signal D1 of the second layer to the signal D0 of the first layer. Another inter-layer via (not shown because it is not in the plane of Figure 130D) couples the second layer signal D01 to the first layer signal D1. According to FIG. 130D, when the first layer is the same as the second layer, the second layer is supplemented by an inter-layer via pitch, so that the TSV can correctly align each layer, but only a single interlayer via mask is required. Can achieve the correct layer connection.

In accordance with the above, in some cases of the present invention, the control logic on each layer of the 3D IC preferably knows which layer. At the same time, it is best to use the same mask for each layer. In a case where an inter-layer via pitch complement is used to properly couple functionality and repair connections, a different via pattern is installed near the control logic to develop inter-layer complement and uniquely determine the layers to their control logic.

Figure 131A illustrates a via pattern 13100 on a first layer such as the 3D ICs 11900, 12100, 12200, 12300, 12400, 12500, and 12600 described above. The metal laminations on each of the via locations 13102, 13104, and 13106 are present on at least the lower metal layer of the first layer. The via pattern 13100 occurs adjacent to the control logic on the first layer. The through-hole metal laminations 13102 are coupled to the ground (the first layer of ground is indicated by L1/G in the drawing). The via metal laminations 13104 are coupled to a signal named ID (the first layer ID is indicated by L1/ID in the drawing). The via metal laminations 13106 are coupled to the supply voltage (in the figure, L1/V represents the first layer VCC).

Figure 131B illustrates a via pattern 13110 located on a first layer such as the 3D ICs 11900, 12100, 12200, 12300, 12400, 12500, and 12600 described above. The metal laminations on each of the via locations 13112, 13114, and 13116 are present at least over the lower metal layer of the second layer. The via pattern 13110 occurs adjacent to the control logic on the second layer. The through-hole metal laminations 13112 are coupled to the ground (the second floor is indicated by L2/G in the drawing). The via metal laminations 13114 are coupled to a signal named ID (the second layer ID is indicated by L2/ID in the drawing). The via metal laminations 13116 are coupled to the supply voltage (in the figure, L2/V represents the second layer VCC).

Figure 131C is a top plan view of via patterns 13100 and 13110 aligned and supplemented by a layer interconnect pitch. Interlayer interconnections can be implemented through TSV or other inter-layer interconnect techniques. The metal laminations 13102, 13104, 13106, 13108, 13112, 13114 and 13116 discussed above are included in Figure 130C. In Fig. 130C, the second layer is supplemented by the inter-layer connection pitch located on the right side of the first layer. However, the addition results in a physical stack of via metal laminations 13104 and 13112. As such, the supplement will also result in a physical stack of via stacks 13106 and 13114. If the via via technique or other inter-layer vertical coupling point is located at these two overlapping locations (by a single mask), the first layer ID signal is grounded and the layer 2 ID signal is coupled to VCC. This configuration allows the control logic on Layers 1 and 2 to know only their vertical position in the stack.

It is generally known to those skilled in the art that the metal connection between layer 1 and layer 2 is greater because it includes larger laminations and many TSV or other inter-layer interconnections. The increased size contributes to the alignment of the power supply nodes and ensures that both L1/V and L2/V are at the positive supply potential and both L1/G and L2/G are at the node potential.

Many of the cases of the present invention utilize a three mode redundancy (RMR) approach in three layer allocation. In these cases, the best way is to use the same mask for all three layers.

Figure 132A illustrates a via metal overlap pattern 13200 comprising a 3x3 array of TSVs (or other interlayer coupling techniques). The TMR inter-layer connection occurs near the majority (MAJ3) gate of the trigger or function block fan-in or fan-out. Therefore, at each position, the functions f(X0, X1, X2) = MAJ3 (X0, X1, X2) are used on each of the three layers, where X0, X1 and X2 represent the three inputs of the MAJ3 gate. For the purposes of this discussion, since the MAJ3 gate and the X1 and X2 inputs are from the other two layers, the X0 input is always coupled to the signal pattern generated on the same layer.

In the via pattern 13200, the via metal stacks 13202, 13212, and 13216 are coupled to the X0 input of the MAJ3 gate, and the via metal stacks 13204, 13208, and 13218 are coupled to the X1 input of the MAJ3 gate. Through-hole metal stacks 13206, 13210, and 13214 are coupled to the X2 input of that layer of MAJ3 gates.

Figure 132B illustrates a typical 3D IC, shown as 9220, having three layers, each of which is represented by layers 1, 2, and 3 from bottom to top. In the vicinity of the MAJ3 gate for performing TMR-related interlayer coupling, each layer includes a case of a via pattern 13200. The second layer adds an inter-layer via pitch to the right side of the first layer, while the third layer replenishes an inter-layer via pitch to the right of the second layer. The description in Figure 132B is only a cut-out portion. When it correctly displays the two inter-layer via pitch complements in the horizontal direction, it is generally known to those skilled in the art that the perforated metal laminations of each row of 13200 are aligned to the left and right of the same row in another case.

Therefore, the through-hole metal laminations of the three locations are aligned to all three layers. Figure 132B shows three inter-layer vias 13230, 13240, and 13250 at those locations that couple the first to second layers, and three inter-layer vias 13232 at those locations that couple the second to third layers, 13242 and 13252. The same interlayer via mask can be used for the interlayer via packaging stage.

Therefore, the interlayer vias 13230 and 13232 are vertically aligned and coupled to the first layer X2 MAJ3 gate input, the second layer X0 MAJ3 gate input, and the third layer X1 MAJ3 gate input. Similarly, the interlayer vias 13240 and 13242 are vertically aligned and coupled to the first layer of X1 MAJ3 gate inputs, the second layer of X2 MAJ3 gate inputs, and the third layer of X0 MAJ3 gate inputs. Finally, the interlayer vias 13250 and 13252 are vertically aligned and coupled to the first layer X0 MAJ3 gate input, the second layer X1 MAJ3 gate input and the third layer X2 MAJ3 gate input. Since the MAJ3 gate X0 input in each layer is driven from that layer, each driver is coupled to a different MAJ3 gate input on each layer to avoid driver shorting, and each MAJ3 gate on each layer receives three layers. Input on the top three drives.

Some of the cases of the present invention can be applied to a large number of commercial and highly dependent aerospace and military fields. The ability to resolve defects in the factory with a repair layer combined with the ability to automatically resolve delay defects (masked with a three-layer TMR case or replace a faulty circuit with a two-layer replacement case), compared to traditional two-dimensional integrated circuit (IC) technology The creation of larger and more complex 3D systems is possible. These various aspects of the invention can offset the cost requirements of the target application area.

For example, 3D ICs that target low-cost consumer goods are primarily cost considerations and can be repaired at the factory to maximize yield, but do not include field repair circuits that minimize the cost of short-lived products. 3D ICs targeting higher-end consumers or lower-end commercial products can combine two-layer field replacement in factory repair. The 3D IC, an enterprise-class computing device with the goal of balancing cost and reliability, can omit factory repair steps and adopt the TMR method for qualified yield and on-site repair. 3D ICs targeted for high-dependency, military, aerospace, space, or radiation-resistant applications can be factory-repaired to ensure that all three cases of each circuit are fully operational and use the TMR method for on-site repair and SET and SEU filtering. The battery drive assembly for the military market can be added to the circuit so that the assembly runs only one of the three layers of the TMR to extend battery life and includes a radiation detection circuit that automatically converts to TMR mode as needed when the operating environment changes. Many other combinations and alternate uses are possible within the scope of the invention.

It is worth noting that many of the principles of the present invention are also applicable to conventional two-dimensional integrated circuits (2D ICs). For example, a similar two-layer field repair case is built on a single layer. Both modes of the rework circuit are on a 2D IC, while the same cross-connection is used between the rework modes. Programmable technologies such as fuses, anti-fuse, and flash memory can be used to validate factory repairs and field repairs. Similarly, some similar models in the TMR case are unique topologies in both 2D ICs and 3D ICs. If applied on a single layer, they can improve the yield or reliability of 2D IC systems.

Figure 13 is a flow chart showing the 3D logic division method. Dividing a logical setting into more than two perpendicularly connected dies presents a new round of challenges to place and route-P&R tools. The place and route tool is one of the tools in the CAD software that has the ability to compute the above-described library of logic tiles (and to build other banks). The layout process plan of the prior art P&R tool generally starts from the layout and then is routed. However, the logic setting of the vertical connection die takes into account the greatly reduced frequency between the dies, resulting in a special setup process and the need to specifically support the CAD software for the setup process. In fact, from the flow in Figure 13, the 3D system is worth a priority for a portion of the wiring.

The flowchart of Figure 13 adopts the following terms: the number of TSVs of M-logic; N(n) - the number of nodes connected to the network n; the slack of S(n)-line n, and the minimum number of MinCut- The network connecting the two halves (MC) divides the logic setting (net table) into two known algorithms of the same size; MC-the number of nets connecting the two parts; K1, K2 - two parameters selected by the setter.

One idea of the flow proposed in Figure 13 is to create a netlist in the logical settings to connect nodes with a number greater than K1 and less than K2. K1 and K2 are the parameters selected by the setter and can be modified during the iteration. K1 should be high enough to limit the number of nets placed in the netlist. The purpose of the process is to assign TSVs to the network of tight timing constraints - the critical line network. At the same time, there are many nodes that can extend the layout to many grains, which helps to shorten the overall physical length and meet timing constraints. The number of nets in the table should be close to the same, but not less than the number of TSVs. Correspondingly, the K1 setting must be high in order to achieve the purpose of the process. K2 is the upper limit of the net network, and its number of nodes N(n) can be a special treatment.

The critical line network usually determines the critical path and the available slack time on the path by setting static timing analysis. The path constraint reaches the plane planning, layout and routing tools, so that the final setting will not be degraded because it exceeds the requirement.

After the netlist is built, the priority order is made according to the incremental slack or median slack S(n) of the net. Then using a partitioning algorithm, such as but not limited to MinCut, the setting can be divided into two parts, and the highest priority line is equally divided between the two parts. The goal is to provide a better chance of tighter slack nets to be laid out closer to meet timing challenges. A network with a higher number of nodes than K1 tends to cover a larger space, and by extending into three dimensions, we can better meet the timing challenge.

The flow chart of Figure 13 illustrates an iterative process of assigning TSVs to a number of node nets, with the most compact timing challenges or minimum slack.

Obviously, the same process can be adjusted to a three-way segmentation or any other number depending on the number of grains that the logic extends.

Building a feature created by a 3D configurable system based on anti-fuse logic can increase the cost ratio through the use of redundancy. However, it is even more convenient for the 3D structure of the inventive case because the memory is not randomly distributed between the logics, but is concentrated in the memory die that is perpendicularly connected to the logic die. Memory redundancy and the correct automatic repair process have less impact on logic and system performance.

One of the series of level dicing blocks of the present invention represents a partial loss of 矽 area. The narrower the block, the smaller the loss, so there is still an advantage in using advanced dicing methods that can be built and worked with narrow blocks.

Such an advanced dicing method scribes 3D IC wafers by laser. Laser dicing techniques, including cooling the substrate by water column and removing debris, can be used to minimize damage to the 3D IC structure and cut sensitive layers in the 3D IC before final dicing.

An added advantage of the 3D configurable system of each case of the present invention is the reduction in test costs, which is the result of the application of the standard 'Lego®' building block to create a unique system. Test standard blocks reduce test costs through the application of probe boards and standard test programs.

This disclosure includes two forms of 3D IC systems, the first being by TSV and the second being by the method referred to herein as 'top floor', as described in Figures 21-35 and 39-40. These two methods can be used together in the case where the components are referred to as 'foundation' and 'top floor' by layer transfer and precipitation and are connected to each other by TSV to form a multilayer single or polycrystalline germanium. The main difference is that the previous TSV is associated with a relatively large misalignment (about 1 micron) and a limited connection (TSV) of about 10,000 per square millimeter to connect a fully packaged component, while the disclosed 'smart cut' layer transfer method allows The 3D structure has tiny misalignments (<10 nm) and a large number of connections (through holes) of around 100 million per square millimeter because they are produced in an integrated packaging process. One advantage of TSV-based 3D is the ability to test components before assembly and the ability to utilize known qualified die (KGD) in 3D stacks or systems, which guarantees good 3D integrated system yield and reasonable cost. It is very beneficial.

An additional alternative to the present invention is a method that allows redundancy to exist, such that a highly integrated 3D system employing layer transfer techniques can achieve higher yields. To illustrate this redundancy concept, we will use the programmable tile array of Figures 11A 36-38.

Figure 41 is a schematic diagram of a redundant 3D IC system, which illustrates that the 3D IC programmable system consists of a programmable first layer 4100 of 3X3 tile 4102 overlaid with a programmable first layer 4110 of 3X3 tile 4112, with the topmost overlay The programmable first layer 4120 of the 3X3 tile 4122. There are many programmable connections 4104 between a tile on this layer and its adjacent tiles. Programmable component 4106 can be an anti-fuse, pass transistor controlled driver, floating gate flash transistor, or similar electrically programmable component. Each tile connection 4104 has a branch programmable connection 4105 that is connected to the interlayer vertical connection 4140. The final product is set such that at least one layer, such as 4110, is reserved for redundancy.

When the final product programmable system is programmed for the end application, each tile will use its own MCU for built-in self-testing. The tile found to be defective was replaced by a tile in the redundant layer 4410. The replacement process will be done by tiles located at the same location within the redundant layer, so its impact on the functionality and performance of the overall product should be desirable. For example, if the tile (1,0,0) is defective, the tile (1,0,1) will be programmed to have the same function and replace the tile by accurately setting the programmable connection between the tiles (1,0,0) ). Thus, if the defective tile (1,0,0) is assumed to be connected to the tile (2,0,0) via the connection 4104 via the programmable component 4106, the programmable component 4106 will be turned off, and the programmable components 4116, 4117 And 4107 is turned on. Whether it is repeating the interior of the tile or the external connection, a similar multilayer connection structure should be used. Therefore, when the tile is defective, the redundant tiles of the redundant layer will be programmed into the function of the defective tile, and the multi-layer tile structure is activated, and the redundant tile is turned on after the faulty tile is cut. When the tile (2,0,0) is a defective product, the tile (2,0,1) of the redundant layer may also be inserted by the interlayer vertical connection 4140. In this case, the tiles (2, 0, 1) will be programmed to have the same function as the tiles (2, 0, 0), while the programmable component 4108 is turned off and the programmable components 4118, 4117, and 4107 are turned on.

An additional case of the present invention is a modified TSV (矽通孔技术) process. This process is for wafer-to-wafer TSVs and provides a way to increase the thickness of the wafer to around 1 micron. Figures 93A-D illustrate such a method. The first wafer 9302 is the base and the top is constructed with a hybrid 3D structure. The second wafer 9304 is bonded to the top of the first wafer 9302. The new upper wafer faces down so that the circuit 9305 is face to face with the first wafer 9302 circuit 9303.

In some applications, the bonding is oxide to oxide; in other applications, the bonding is copper to copper. In addition, the joints are in a hybrid joint manner, that is, some of the joint faces are oxides and some are copper.

After bonding, the upper wafer 9304 is thinned to about 60 microns by conventional backgrinding and CMP processes. Figure 93B illustrates the case where the now thinned wafer 9306 is bonded to the first layer of wafer 9302.

The next step involves high-precision measurement of the thickness of the upper wafer 9306, followed by high-power 1-4MeV H+ implantation to define the cleave plane 9310 in the upper wafer 9306. The cleave plane 9310 can be positioned about 1 micron above the joint surface, as shown in Figure 93C. When performing this process, a special high-power implanter can be installed, such as the implanter used by SiGen in its PV (photovoltaic) applications.

The ability to accurately measure the thickness and height of the wafer on the 9306 allows for the removal of most of the wafer 9306, leaving a very fine layer 9312 of about 1 micron bonded to the first wafer 9302. See Figure 93D.

One advantage of this process flow is that the additional wafer with circuitry can now be laid out and bonded to the bonding structure 9322 in a similar manner. But first, the tie layer is built on the back of the 9312, allowing electrical connection to the bond structure 9322 circuit. Thinning the upper layer to a single micron level allows such an electrically connected metal layer to be completely aligned with the upper wafer 9312 circuit 9305, and the through hole through the back of the upper layer 9312 is relatively small, having a diameter of about 100 nm.

The thinning of the upper layer 9312 enables the modified TSV to be at a level of 100 nm, which is 5 microns required for a TSV to pass through 50 micrometers. Unfortunately, the misalignment levels of wafer-to-wafer bonding processes are still large, around +/- 0.5 microns. Accordingly, as described herein with reference to FIG. 75, a 1x1 micron bond pad is used over the first wafer 9302, and is connected to the second wafer through a copper-to-copper bond and a small metal bond. On the surface of 9304. The process provides a bond density of about 1 connection per square micron.

The most ideal way is to increase the connection density by the concept and related explanations introduced in Figure 80. In the case of modifying the TSV, this is more challenging because the space leading to the bonding electrode is very limited if the two wafers that are bonded are all processed and joined. Nevertheless, in order to form a through hole, etching is required in all layers. Figure 94 illustrates a method and structure for addressing these issues.

Figure 94A illustrates four metal bond electrodes 9402 that are exposed on top of the first wafer 9302. The bonding electrode 9402 is oriented east-west, and the maximum misalignment of the east-west joint Mx is the length of 9406 plus a triangle D, which will be explained later. The pitch of the bonding electrode is twice the minimum pitch Py of the upper layer of the first wafer 9302. 9403 shows an unused potential space for an additional metal electrode.

Figure 94B illustrates bonding electrodes 9412 and 9413 exposed on the upper layer of the second wafer 9312. Figure 94B also shows two rows of bonding electrodes, A and B running from north to south. These joint electrodes have a length of 1.25 Py. The two wafers 9302 and 9312 are joined in a copper-to-copper manner, and the bonding electrodes in FIGS. 94A and 94B are set such that the joint misalignment does not exceed the maximum misalignment Mx in the east-west direction and My in the north-south direction. The bonding electrodes 9412 and 9413 in Fig. 94B are set such that they are not inadvertently shorted to the bonding electrode 9402 in 94A, and the bonding electrode 9412 of the A row or the bonding electrode 9413 of the B row can be bonded to the bonding electrode 9402. Get the full contact. The triangle D is the size from the east side of the B line bonding electrode 9413 to the west side of the A line bonding electrode 9412. The number of bonding electrodes 9412 and 9413 in Fig. 94B should be set equal to the value of bonding electrode 9402 plus My in Fig. 94A to offset the maximum misalignment error in the north-south direction.

In general, all of the bonding electrodes of FIG. 94B can be routed through the internal wiring of the upper wafer 9312 to the bottom of the wafer adjacent to the transistor layer. The location of the bottom of the wafer and the top of the 9322 structure are shown in Figure 93D. At this point, a new via 9432 is formed which connects the bonding electrode to the top surface of the bonding structure through conventional wafer processing steps. Figure 94C shows all of the via connections for routing the bonding electrodes to Figure 94B, in row A 9432 and row B 9433. In addition, the through hole 8436 into which the signal is introduced should also be processed. All of these vias can be aligned with the upper wafer 9312.

According to Fig. 93C, a metal mask is used to connect, for example, four through holes 9432 and 9433 to four through holes 9436 by metal strips 9438. This metal strip is aligned with the upper wafer 9312 in the east-west direction, and can also be aligned with the upper wafer 9312 in the north-south direction, but a special offset based on the north-south direction misalignment must be set, but the north-south direction metal The length of the structure 9438 should be sufficient to counteract the worst case joint misalignment in the north-south direction.

It is again stated that the present invention is applicable to many application fields other than programmable logic such as a graphics processor composed of many repetitive processing chips. Other fields of application include general logic settings in a 3D ASIC (application specific integrated circuit) or a system that combines an ASIC layer with a layer consisting of at least some other specialized functions. It is generally known to those skilled in the art that many cases and combinations can be accomplished by applying the principles of the invention herein, and such cases will be introduced to those skilled in the art in due course. Except as set forth in the appended claims, the invention is not limited in any way.

But another option to improve yield by replacing defective circuits and using 3D redundancy is to use direct-reading electron beams instead of programmable connections.

Additional variations to the programmable 3D system include a tiled programmable logic tile that is connected to an I/O structure pre-assembled on the base wafer 1402 shown in FIG.

However, in an additional variation, the programmable 3D system should include a tiled programmable logic tile, and pre-assembled in the finished product, by any of the methods shown in Figures 21-35 or Figures 39-40. The I/O structure at the top of the pole wafer 1402 is connected. In fact, any of the alternative structures of Figure 11 can be packaged over each other as long as the 3D techniques shown in Figures 21-35 or Figures 39-40 are utilized. Accordingly, many changes to 3D programmable systems can be achieved with a limited set of masks, mixing different structures to form different 3D programmable systems, and varying amounts, logic 3D positions, I/O types, memory types, etc. .

Additional flexibility and mask multiplexing are achieved by using a small portion of the full reticle exposure. Modern stepper motors allow the reticle portion to be covered, thereby projecting a small portion of the reticle. Accordingly, one portion of the mask set can be used for one function and the other portion for another function. For example, let the structure in Figure 37 represent the logical portion of the 3D programmable system terminal device. Above the 3X3 programmable tile structure, the I/O structure can be established by using the process of Figures 21-35 or Figures 39-40. There should be a set of masks, the different parts of which are used for the overlap of different I/O structures; for example, one part of a simple I/O and the serializer/deserializer (Ser/Des) I/O portion. Each set is set to provide I/O of watts, perfectly superimposed on the programmable logic tiles. Then in two parts of a mask set, many changes can be generated in the end system, including a simple I/O with all nine tiles, and another with SerDes overlapping tiles (0,0), while simple I/ O is superimposed on the other eight tiles, the other with SerDes overlapping tiles (0,0), (0,1) and (0,2), while simple I/O is superimposed on the other six tiles, and so on. . In fact, if the settings are reasonable, many layers can be produced by superimposing one layer on the other, producing a wide variety of end products in a limited set of masks. It is generally known to those skilled in the art that the applicability of this method is beyond the scope of programmable logic and is best used in structures with many 3D ICs and 3D systems. The scope of the invention is therefore intended to be limited only by the appended claims.

However, in an additional option of the invention, the 3D anti-fuse configurable system should also include a programming die. In some cases of FPGA products, mainly anti-fuse basic products, an external component is installed for programming. In many cases, this facilitates the user's integration of this programming function into the FPGA component. When the programming process requires higher voltages and control logic, this can easily lead to severe overhead of the die. Therefore, the programmer function can be set in a dedicated programming die. This programmed die charge pump can generate a higher programming voltage, while a programming-related controller programs the anti-fuse programmable die inside the 3D configurable circuit and the program verify circuit. Programmable dies are produced through the use of lower cost, older semiconductor processes. An added advantage of the configurable system's 3D architecture is its high-capacity cost reduction scheme, in which the anti-fuse layer is replaced by a custom layer, whereby the programmable die is removed from the 3D system, thereby achieving more Cost-saving and high-capacity production.

It is generally known to those skilled in the art that the present invention uses anti-fuse terminology because it is a generic name for the industry, but the present invention also refers to a micro-component that operates like a switch, indicating that the micro-assembly has a high state in the initial state. The impedance is OFF, and electronically, it can be switched to a very low resistance-ON state. It can also correspond to a component-reprogramming switch that switches ON-OFF multiple times. For example, the new invention, such as the electrostatically excited metal microdrop microswitch introduced by CJKim, a staff member of the University of California, Los Angeles micro-nano manufacturing lab, is compatible with CMOS chips.

Those skilled in the art will recognize that the present invention is not limited to anti-fuse configurable logic and is applicable to other non-volatile configurable logic. A good example is flash-based configurable logic. Flash programming also requires higher voltages, and the placement of programming transistors and programming circuitry in the base diffusion layer reduces the overall density of the base diffusion layer. It is advantageous to use the different cases of the invention and to achieve higher component densities. It is therefore recommended to create a programming transistor and a programming circuit in accordance with one or more of the examples of the present invention, rather than as part of a diffusion layer. In high-capacity production, one or more custom masks are used to replace the flash programming function and the need to add to the programming transistor and programming circuitry is retained accordingly.

Unlike metal-to-metal anti-fuse, which can be laid out as part of a metal interconnect, the flash circuit needs to be packaged in the base diffusion layer. Thus, installing a programming transistor far above a layer is not as efficient. Another alternative to the present invention is to connect the configurable logic component and its flash component to the underlying structure 814 including the programming transistor by via via 816.

In this document, the expression of components is expressed in a variety of terms. For example, "receiving box" refers to the first single crystal layer with a transistor and a metal interconnect layer. This single crystal layer can sometimes also refer to a primary wafer, an acceptor wafer, or a base wafer.

Some examples of the invention include the selection of methods for developing IC (integrated circuit) components using techniques and methods of constructing 3D IC systems. In some instances of the invention, component solutions can be implemented with less power than prior art. These component solutions are beneficial for increased use of mobile electronic components such as mobile phones, smart phones, cameras, and the like. For example, the incorporation of 3D semiconductor components within the scope of these mobile electronic components in accordance with some aspects of the present invention provides advanced mobile wafers that are more efficient and durable than prior art operations.

In accordance with some examples of the present invention, 3D ICs can also enable electronic and semiconductor components to operate at higher performance levels, in view of shorter interconnects and more complex vias of multiple levels of semiconductor components, and provide repair or redundancy. ability. In accordance with some of the cases of the present invention, the complexity of semiconductor components can be far beyond the level of prior art practice. These advantages ensure a more powerful computer system and improved system for embedded computers.

Some examples of the present invention also enable significant savings in one-time (NRE) costs for prior art electronic system setups by high density 3D FPGAs or different forms of 3D array base ICs with the reduced custom masks described above. These systems can be distributed across many products and many market segments. By reducing the risk of previous investments before developing the market, the reduction in NRE makes it possible to develop and deploy applications in the early stages of new product groups or product cycles. These advantages can also be achieved through different hybrid approaches, such as using a total mask in the logic layer and using other total masks in the memory layer to reduce the NRE, thereby creating a very complex system that overcomes the inherent yield limitations by repair techniques. problem. Another hybrid approach is to build a 3D FPGA and add 3D layer of custom logic and memory to it so that the end system can have field programmable logic on top of the factory custom logic. In fact, there are many ways to mix highly creative components to form a 3D IC to support the needs of an end system, including the use of multiple components, of which more than one component incorporates the inventive elements. End systems benefit from the use of inventive 3D memory and high performance 3D FPGAs as well as high density 3D logic. The use of components consisting of one or more inventive elements ensures better performance and/or lower power consumption and the advantages of other inventions, providing a competitive advantage for end systems. Such end systems should be electronic based products or other types of systems including a level of embedded electronics such as automobiles and remotely controlled vehicles.

In order to increase the contact resistance of very small scale contacts, the semiconductor industry uses a variety of metal halides such as cobalt telluride, titanium telluride, tantalum telluride, and nickel telluride. Current advanced CMOS processes, such as 45nm, 32nm, and 22nm, use deuterated nickel to increase the resistance of deep submicron source and drain contacts. Background information on the telluride used to reduce the resistance of the joint can be found in "Scale CMOS NiSi Self-Aligned Telluride Technology", H. Iwai et al., Microelectronics Engineering, 60 (2002), pp. 157-169; Sub-50 nm CMOS The comparison of nickel and cobalt telluride integration, B. Froment et al., IMEC ESS Circuit, 2003 and 65 and 45 nm Components - Introduction, D. James, Semicon West, July 2008, ctr_024377. In order to achieve the lowest tantalum nickel contact and source/drain resistance, the nickel on the crucible must be heated to 450 °C on Thursday.

Therefore, it is best to ensure the low resistance of the process flow in this paper, and the exposure temperature of the metallization layer after copper metallization and low-k dielectric must be kept below 400 °C. This typical process consists of a recessed channel array transistor (RCAT), but this or similar processes can be applied to other processes and components such as S-RCAT, JLT, V-slot, JEFE, bipolar and replacement gates. Process.

A planar n-type via recessed channel array transistor (RCAT) suitable for metal halide source and drain junctions of 3D ICs can be constructed. As shown in FIG. 133A, the donor wafer 13302 of the P-type substrate is processed to include an N+ doped layer 13304 and a P-doped layer 13301 of the same wafer size through the wafer. The N+ doped layer 13304 can be formed by ion implantation and thermal annealing techniques. In addition, P-doped layer 13301 contains additional ion implantation and annealing processes that provide different levels of doping than P-substrate 13302. The P-doped layer 13301 also has a graded P-doping that alleviates transistor performance issues such as short pass effects after RCAT formation. The layer stacking may be formed by continuous epitaxial deposition of doped P-doped layer 13301 and N+ doped layer 13304, or by epitaxial and implant combining techniques. Implant annealing and doping will use rapid thermal annealing (RTA or spike) optical annealing techniques or types.

As shown in FIG. 133B, a ruthenium-reactive metal, such as nickel or cobalt, can be deposited onto the N+ doped layer 13304 and annealed using an RTA, thermal or optical annealing process to form a metal deuterated layer 13306. The top surface of the donor wafer 13301 should be prepared with an oxide wafer bonded oxide precipitate to form an oxide layer 13308.

As shown in Figure 133C, a layer transfer separation plane (shown in phantom) 13399 can be formed by hydrogen injection or other methods as described above.

As shown in FIG. 133D, the donor wafer 13302 including the layer transfer spacer plane 13399, the P-doped layer 13301, the N+ doped layer 13304, the metal deuteration layer 13306, and the oxide layer 13308 can be temporarily passed through a low voltage process assisting low voltage release. Bonded to the carrier or carrier substrate 13312. The carrier or carrier substrate 13312 should be a glass substrate such that a state-of-the-art optical process is consistent with the acceptor wafer. The temporary bond between the carrier or carrier substrate 13312 and the donor wafer 13302 can be a polymeric material, such as polyimide DuPont HD3007, which can be later released by laser ablation, ultraviolet radiation exposure, or thermal decomposition. Adhesive layer 13314. Alternatively, temporary joints can be prepared by unipolar or bipolar electrostatic techniques, such as the Apache tool from Beam Services.

As shown in FIG. 133E, portions of the donor wafer 13302 located on the layer transfer separation plane 13399 can be removed by cleavage or other processes such as ion ablation or other methods. The remaining donor wafer P-doped layer 13301 can be thinned by a chemical mechanical polishing (CMP) process such that the P-layer 13316 can achieve the desired thickness. Oxide 13318 can be deposited onto the exposed side of P-layer 13316.

As shown in FIG. 133F, both the donor wafer 13302 and the acceptor substrate or wafer 13301 can be prepared for the aforementioned wafer bonding, followed by low temperature (less than 400 ° C) alignment, oxide-to-oxide bonding. The aforementioned acceptor substrate 13310 will take into account transistors, circuits, metals such as aluminum or copper, interconnect wiring and through-layer via metal interconnect strips or disks, and then release the carrier or carrier substrate 13312 by a low temperature process such as laser ablation. And donor wafer 13302. The oxide layer 13318, the P-layer 13316, the N+ doped layer 13304, the metal deuterated layer 13306, and the oxide layer 13308 layer are transferred to the acceptor wafer 13310. The top surface of the oxide 13308 can be polished by chemical or mechanical means. Current RCAT transistors are formed with a low temperature (less than 400 ° C) process to form alignment marks with the acceptor wafer 13310 (not shown).

As shown in FIG. 133G, transistor isolation region 13322 is formed through a mask definition, after which plasma/RIE etches oxide layer 13308, metal deuteration layer 13306, N+ doped layer 13304, and P-layer 13316 onto oxide layer 13318. The low temperature interstitial oxide is then deposited and chemical mechanically polished while the oxide remains in isolation region 13322. Therefore, the recessed channel 13323 performs mask definition and etching. The depressed channel surfaces and corners become smooth through a wet chemical or plasma/RIE etch process, thereby mitigating high field effects. These process steps constitute oxide region 13324, metal telluride source and drain regions 13326, N+ source and drain regions 13328, and P-channel region 13330.

As shown in FIG. 133H, a gate dielectric 13332 is formed and a gate metal material is deposited. The gate dielectric 13332 is an atomic layer deposition (ALD) gate dielectric that is paired with a work function specific gate metal in the aforementioned equivalent standard high k metal gate process scheme. Alternatively, the gate dielectric 13332 is formed by low temperature oxide deposition or low temperature microwave plasma oxidation on the surface of the crucible, and then a gate material such as tungsten or aluminum is deposited. Finally, the gate material is chemically mechanically polished, and the gate area is determined by masking and etching to form a gate electrode 13334.

As shown in FIG. 133I, the low temperature thick oxide 13338 is deposited, and the source, gate and drain contacts and the through layer via (not shown) openings are masked and etched to prepare the transistor for metallization. Thus, gate contact 13342 is coupled to gate electrode 13334 and source and drain junction 13336 is coupled to metal germanide source and drain regions 13326.

It is generally understood by those skilled in the art that the description of Figures 133A through 133I is for illustrative purposes only and is not to scale. Those skilled in the art will further recognize that many variations are possible, such as a temporary carrier substrate that can be replaced by a carrier wafer, and the permanent bonded carrier wafer process shown in Figure 40 can be applied. Many other modifications within the scope of the present invention will be referred to by those skilled in the art after careful reading. The scope of the invention is therefore intended to be limited only by the appended claims.

The use of new FPGA (Field Programmable Logic Array) programming structures and components saves cost, space, and improves the performance of 3D FPGAs due to the high-density layer-to-layer interconnects involved in the case of the present invention and the formation of memory components and transistors. . The memory components of the pass transistor or switch and the control path transistor switch state can be located in different layers and connected to each other and the wiring network metal line through a through-via via (TLV), or the via transistor and the memory component can be on the same layer. Connect to the network cable using TLV.

As shown in FIG. 134A, the master wafer 13400 is processed into a logic circuit, an analog circuit, and other components, and forms a basic FPGA with the metal interconnection and the metal configuration network. The acceptor wafer 13400 also includes configuration components such as switches, pass transistors, memory chips, programming transistors, and includes one or more of the above-described base layers.

As shown in FIG. 134B, the donor wafer 13402 is pretreated with one or more pass transistors or switches or partially formed pass transistors or switches. The pass transistor can be constructed using the local transistor process described above (such as RCAT or JLT or others) or using a replacement gate technology (such as a CMOS or CMOS N~P or gate array with or without the carrier wafer described above). The donor wafer 13402 and the acceptor substrate 13400 and associated surfaces are ready for wafer bonding as described above.

As shown in FIG. 134C, the donor wafer 13402 and the acceptor substrate 13400 are bonded at a low temperature (below 400 ° C), while a portion of the donor wafer 13402 is permeable to cracking and polishing or other means such as ion cutting or other. The method is removed to form the remaining via transistor layer 13402. Currently, portions of the transistor or transistor are formed or completed and aligned with the alignment substrate (not shown) of the acceptor substrate 13400 described above. A through via (TLV) 13410 can be formed in the manner described above, with the interconnect and dielectric layers being the same, and then forming an acceptor substrate with via transistor 13400A, including acceptor substrate 13400, pass transistor layer 13402, and TLV 13410.

As shown in FIG. 134D, the memory wafer donor wafer 13404 is pretreated with one or more layers of memory wafers or partially formed memory wafers. The memory chip can utilize the above-described local memory process flow (such as RCAT DRAM, JLT or others) or use a replacement gate technology such as a CMOS gate array New Year engineering SRAM component, with or without the above carrier wafer, or through non-easy A lossless memory such as R-RAM or the above FG flash is constructed. The memory wafer donor wafer 13402 and the acceptor substrate 13400A and associated surfaces are prepared for wafer bonding as described above.

As shown in FIG. 134E, the memory wafer donor wafer 13404 and the acceptor substrate 13400A are bonded at a low temperature (below 400 ° C), while a portion of the memory wafer donor wafer 13404 is permeable to cracking and polishing or other means such as Ion cutting or other methods are removed to form the remaining memory wafer layer 13404. Currently, portions of the memory die and transistor or transistor are formed or completed and aligned with the above-described acceptor substrate 13400A alignment mark (not shown). The memory-to-switch through-via vias 13420 and the memory-to-acceptor through-via vias 13430 and the interconnect and dielectric layers are constructed in the manner described above to form an acceptor substrate with via transistors and memory die 13400B, including an acceptor substrate 13400, pass transistor layer 13402, TLV 13410, memory to switch through layer vias 13420, memory to acceptor through layer vias 13430, and memory wafer layer 13404.

As shown in FIG. 134F, this is a simplified schematic diagram of an important component of the acceptor substrate with via transistors and memory die 13400B. A typical memory die 13440 located on the memory die layer 13404 can be electrically coupled to a typical pass transistor gate 13442 located in the pass transistor layer, which includes a memory-to-switch pass-through via 13420. A pass transistor source 13444 located in pass transistor layer 13402 can be electrically coupled to an FPGA configuration network metal line 13446 located on acceptor substrate 13400 with TLV 13410A. A pass transistor drain 13445 at pass transistor layer 13402 can be electrically coupled to an FPGA configuration network metal line 13447 located on acceptor substrate 13400 with TLV 13410B. The programming signal for the memory wafer 13440 is from the outside of the chip or is located above, inside or below the memory wafer layer 13404. The memory die 13440 also includes a reverse configuration in which a memory component, such as an FG flash component, is coupled to couple the gate of the pass transistor to ground. Thus, the FPGA configuration network metal line 13446 carrying the output signal from the acceptor substrate 13400 logic chip can be electrically coupled to the FPGA configuration network metal line 13447, which is routed to the input of a logic chip in the acceptor substrate 13430. on.

It is generally understood by those skilled in the art that the description in Figures 134A through 134F is for illustrative purposes only and is not to scale. Those skilled in the art will further recognize that many variations are possible, for example, the memory wafer layer 13404 can be built under the via transistor layer 13402. In addition, pass transistor layer 13402 includes control and logic circuitry in addition to pass transistors and switches. In addition, memory die layer 13404 includes control and logic circuitry in addition to the memory die. Thus, the pass transistor component can in turn be a pass gate circuit or an active drive type switch. Many other modifications within the scope of the present invention will be referred to by those skilled in the art after careful reading. The scope of the invention is therefore intended to be limited only by the appended claims.

The pass transistors or switches and the memory components that control the ON or OFF state of the pass transistor are in the same layer, and the TLV can be used to connect to the network metal lines. As shown in FIG. 135A, the master wafer 13500 can be processed to take into account logic circuits, analog circuits, and other components, and together with the metal interconnect and the metal configuration network constitute a basic FPGA. The acceptor wafer 13500 can also include configuration components such as switches, pass transistors, memory chips, programmable transistors, and a base layer comprising one or more of the layers described above.

As shown in FIG. 135B, the donor wafer 13502 is pretreated with one or more pass transistors or switches or partially formed pass transistors or switches. The pass transistor can be constructed using the local transistor process described above (such as RCAT or JLT or others) or using a replacement gate technology (such as a CMOS or CMOS N~P or CMOS gate array with or without the carrier wafer described above). The donor wafer 13502 is pretreated with one or more layers of memory wafers or partially constructed memory wafers. The memory wafer can be constructed using the local memory process described above (e.g., RCAT DRAM or others) or using a replacement gate technique (e.g., a CMOS gate array with or without the carrier wafer described above). For example, by using a CMOS gate array instead of a gate process, a synchronous formation of a memory chip and a via transistor can be realized, wherein a CMOS pass transistor and an SRAM memory chip, such as a 6 transistor chip generation or an RCAT pass transistor and a RCAT DRAM memory. The donor wafer 13502 and the acceptor substrate 13500 and associated surfaces are ready for wafer bonding as described above.

As shown in FIG. 135C, the donor wafer 13502 and the acceptor substrate 13500 are bonded at a low temperature (below 400 ° C), while a portion of the donor wafer 13502 is permeable to cracking and polishing or other means such as ion cutting or other. The method is removed to form the remaining via transistor layer and memory layer 13502. Currently, portions of the transistor or transistor are formed or completed and aligned with the alignment substrate (not shown) of the acceptor substrate 13500 described above. A through-via via (TLV) 13510 can be formed in the manner described above and then produced by an acceptor substrate with via transistors and memory die 13500A, including an acceptor substrate 13500, a pass transistor layer 13502, and a TLV 13510.

As shown in FIG. 135D, this is a simplified schematic diagram of an important component of an acceptor substrate with via transistors and memory die 13500A. A typical memory die 13540 located in pass transistor and memory layer 13502 can be electrically coupled to a typical pass transistor gate 13542 located in pass transistor layer 13502, which includes pass transistor and memory layer interconnect metallization 13525. A pass transistor source 13544 at pass transistor and memory layer 13502 can be electrically coupled to an FPGA configuration network metal line 13546 located on acceptor substrate 13500 with TLV 13510A. A pass transistor drain 13545 at pass transistor and memory layer 13502 can be electrically coupled to an FPGA configuration network metal line 13547 located on acceptor substrate 13500 with TLV 13510B. The programming signals for the memory die 13540 are from off-chip or are located above, inside or below the pass transistor and memory wafer layer 13502. The memory die 13540 also includes a reverse configuration in which a memory component, such as an FG flash component, can couple the gate of the pass transistor to the supply voltage when turned on, and the gate of the pass transistor when the other FG flash component is turned on. To the ground. Thus, the FPGA configuration network metal line 13546 carrying the output signal from the acceptor substrate 13500 logic chip can be electrically coupled to the FPGA configuration network metal line 13547, which is routed to the input of a logic chip in the acceptor substrate 13530. on.

It is generally understood by those skilled in the art that the descriptions of Figures 135A through 134D are for illustrative purposes only and are not to scale. Those skilled in the art will further recognize that many variations are possible, such as pass transistor and memory layer 13502, in addition to pass transistors or switches and memory chips, including control and logic circuitry. In addition, the pass transistor component can in turn be a pass gate circuit or an active drive type of switch. Many other modifications within the scope of the present invention will be referred to by those skilled in the art after careful reading. The scope of the invention is therefore intended to be limited only by the appended claims.

As shown in Figure 136, this is a schematic diagram with an integrated floating gate (FG) flash memory. Control gate 13602 and floating gate 13604 are commonly used to sense transistor via 13620 and switch transistor via 13610. Switching transistor source 13612 and switching transistor drain 13614 are coupled to the FPGA configuration network metal line. The sense transistor source 13622 and the sense transistor drain 13624 are coupled to the program, erase and read circuits. This integrated NVM switch is used by FPGA manufacturer Actel and is manufactured using 2D embedded FG flash technology at high temperatures (above 400 °C).

As shown in Figures 137A-137G, a 1T NVM FPGA component is constructed through a wafer-sized doped layer and a post-layer transfer suitable for single-layer transfer of a 3D IC production process. The programming signal for this component comes from outside the chip, or above, inside or below the component layer.

As shown in FIG. 137A, a P-substrate donor wafer 13700 is processed to include two wafer-sized N+ doped layers and a P-doped layer 13706. The P-doped layer 13706 has the same or a different doping concentration than the P-substrate 13700. The doped layer can be produced by ion implantation and thermal annealing. Layer stacking can be performed by continuous epitaxial deposition of doped germanium layers, or by epitaxial and implant and annealing combination techniques. P-doped layer 13706 and N+ doped layer 13704 can also have graded doping to alleviate transistor performance issues, such as short pass effects, and improve programming and silencing performance. Prior to implantation, the shield oxide 13701 will grow or deposit to protect the germanium from implant contamination and provide an oxide surface for subsequent wafer-to-wafer bonding. These processes should all be completed above 400 ° C as the transfer of layers to the processed substrate with metal interconnects is yet to be completed.

As shown in FIG. 137B, the top surface of the donor wafer 13700 can be oxidized by depositing oxide 13702 or by thermal oxidation of P-doped layer 13706 to form oxide layer 13702 or by reoxidation of implanted shield oxide 13701. Wafer bonding preparation. A layer transfer separation plane 13799 (shown in phantom) can be formed in the donor wafer 13700 (embodied) or N+ doped layer 13704 by hydrogen injection or other methods as described above. Both donor wafer 13700 and acceptor wafer 13710 can be prepared for wafer bonding as described above, followed by low temperature (less than 400 ° C) bonding. Portions of the P-donor wafer substrate 13700 above the layer transfer spacer plane 13799 can be removed by cleavage and polishing or other low temperature processes as described above. This type of ion implantation of atomic species, such as hydrogen, to form a layer transfer separation plane and subsequent cracking or thinning is referred to as "ion cutting." Referring to Figure 8, the acceptor wafer 13710 has the same meaning as the wafer 808 described above.

As shown in FIG. 137C, the remaining N+ doped layer 13704 and P-doped layer 13706 and oxide layer 13702 have been layer transferred to acceptor wafer 13710. The top surface of the N+ doped layer 13704 can be smoothed by chemical or mechanical polishing. Thus, FG and other transistors can be generated by a low temperature (less than 400 ° C) process and aligned with the acceptor wafer 13710 alignment mark (not shown). For clarity of explanation, the oxide layer used to assist wafer-to-wafer bonding, such as 13702, is not shown in the subsequent drawings.

As shown in FIG. 137D, the transistor isolation regions are lithographically defined and the plurality of N+ doped layers 13704 and P-doped layers 13706 are removed via plasma/RIE etching to at least the oxide overlying the host substrate 13710. A low temperature interstitial oxide is then deposited and chemically mechanically polished to remain in the transistor isolation region 13720 and the southwest to southeast isolation region 13721. In FIG. 137, "southwest" represents the position where the switching transistor is formed, and "southeast" represents the position where the sensing transistor is formed, thus resulting in the N+ doped layer 13714 and the P-doped layer 13716 of the southwest region of the future transistor. And the future southeast region of the transistor N+ doped 13715 and P-doped 13718

As shown in FIG. 137E, the southwest recess channel 13742 and the southeast recess channel 13743 can be lithographically defined and etched to remove N+ doping 13714 and P-doped 13716 in the southwest region of the plurality of future transistors, and N+ doping in the southwest region of the future transistor. Miscellaneous 13715 and P-doped 13718. The surface and corners of the recessed channel can be flattened by a wet chemical or plasma/RIE etch process to mitigate high field effects. The channel 13742 of the southwest depression and the channel 13743 of the southeast depression are separated or synchronized mask definition and etching. The width of the southwest channel is larger than the width of the southeast channel. These process steps form a southwest source and drain region 13724, a southeast source and drain region 13725, a southwest transistor channel region 13716, and a southeast transistor channel region 13719.

As shown in Fig. 137F, a tunnel construction medium 13711 is formed and a floating door material is deposited. The tunnel construction medium 13711 is an atomic layer deposition (ALD) medium. Or the tunnel construction medium 13711 forms a low temperature oxide plasma deposition or a low temperature microwave plasma oxidation of the crucible surface. The floating gate material, such as doped polycrystalline or amorphous germanium, is then deposited. Finally, the floating gate material is chemically mechanically polished, while the floating gate 13752 is formed partially or wholly by lithography definition and plasma/RIE etching.

As shown in FIG. 137G, the polysilicon inter-layer dielectric body 13741 is generated by low temperature oxidation and dielectric deposition or a multilayer dielectric such as an oxide-nitride-oxide (ONO) layer, and the gate material is controlled, for example, doped polycrystalline or amorphous. Hey, it’s deposited. After the gate material is chemically mechanically polished, control gate 13754 is created by lithography definition and plasma/RIE etching. The etched range of control gate 13754 also includes a plurality of polysilicon inter-layer dielectric bodies and floating gates 13752 that employ a self-aligned lamination etch process. The logic transistors of the control function are generated (not embodied) by employing the 3D IC compatible methods described herein (eg, RCAT, V-slots and connectors, and through-layer vias), and interconnect metallization is constructed therefrom. This process enables a single crystal 矽1T NVM FPGA configuration component to be built into a single layer transferred prefabricated wafer size doped layer, while the doped layer is created and connected to the underlying multimetal layer without exposing the underlying component at high temperatures. Semiconductor components.

It is generally understood by those skilled in the art that the description of Figures 137A through 137G is for illustrative purposes only and is not to scale. These technicians will further recognize that many variations are possible, such as floating gates containing germanium nanocrystals and other materials. In addition, a common component can be created by removing the isolation zone 13721 from southwest to southeast. In addition, the channel slope of the channel transistor is 0 to 180 degrees. Moreover, logic transistors and components can be created by using a control gate as a component gate. The logic component door and control gate formation can be done separately. In addition, the 1T NVM FPGA configuration component can be generated by charge trapping technology NVM, anti-storage technology, or a non-bonded southwest or southeast transistor configuration. Many other modifications within the scope of the present invention will be referred to by those skilled in the art after careful reading. The scope of the invention is therefore intended to be limited only by the appended claims.

It will be apparent to those skilled in the art that the present invention is not limited to what has been specifically described above. To the contrary, the scope of the present invention is to be understood by those skilled in the art, and the scope of the present invention includes the combinations and sub-combinations and variations and variations of the various features described herein. The scope of the invention is therefore intended to be limited only by the appended claims.

Claims (18)

 A method of fabricating a 3D semiconductor wafer, the method comprising: providing a first wafer comprising a first semiconductor substrate, wherein the first semiconductor substrate comprises a plurality of first transistors; and providing a second wafer comprising a second semiconductor substrate The second semiconductor substrate includes a plurality of second transistors; the second semiconductor wafer is transferred and bonded on top of the first semiconductor wafer; and the second wafer is thinned to less than ten micrometers .    The method of claim 1, further comprising: passing the second semiconductor substrate via, wherein the via has a diameter of less than 400 nm.    The method of claim 1, wherein the first wafer comprises a memory cell array, and wherein the second wafer comprises a control circuit, the control circuit controls the memory cell array.    The method of claim 1, wherein the second wafer comprises a memory cell array, and wherein the first wafer comprises a control circuit that controls the memory cell array.    The method of claim 1, wherein the second transistor and the first transistor are aligned with an alignment error of less than 62 nm.    The method of claim 1, further comprising: a first plurality of connections to the first external device; and a second plurality of connections to the first external device or the second external device, wherein the first plurality of connections At least a portion of the connections are over the second transistors, and wherein at least a portion of the second plurality of connections are below the second transistors.    A method of fabricating a 3D semiconductor wafer, the method comprising: providing a first wafer comprising a first semiconductor substrate, wherein the first semiconductor substrate comprises a plurality of first transistors; and providing a second wafer comprising a second semiconductor substrate The second semiconductor substrate includes a plurality of second transistors; and the second semiconductor wafer is transferred and bonded on top of the first semiconductor wafer; and the second wafer is thinned, wherein the The second semiconductor substrate includes a through-via via; and wherein the via has a diameter of less than 400 nanometers.    The method of claim 7, wherein the thinning system is less than 10 microns.    The method of claim 7, wherein the first wafer comprises a memory cell array, and wherein the second wafer comprises a control circuit, the control circuit controlling the memory cell array.    The method of claim 7, wherein the second wafer comprises a memory cell array, and wherein the first wafer comprises a control circuit, the control circuit controls the memory cell array.    The method of claim 7, wherein the second transistor and the first transistor are aligned with an alignment error of less than 62 nm.    The method of claim 7, further comprising: a first plurality of connections to the first external device; and a second plurality of connections to the first external device or the second external device, wherein the first plurality of connections At least a portion of the connections are over the second transistors, and wherein at least a portion of the second plurality of connections are below the second transistors.    A method of fabricating a 3D semiconductor wafer, the method comprising: providing a first wafer comprising a first semiconductor substrate, wherein the first semiconductor substrate comprises a plurality of first transistors; and providing a second wafer comprising a second semiconductor substrate The second semiconductor substrate includes a plurality of second transistors; the second semiconductor wafer is transferred and bonded on top of the first semiconductor wafer; and the second wafer is thinned, wherein the second The transistor is aligned with the first transistor with an alignment error of less than 62 nm.    The method of claim 13, further comprising: passing the second semiconductor substrate via, wherein the via has a diameter of less than 400 nm.    The method of claim 13, wherein the first wafer comprises a memory cell array, and wherein the second wafer comprises a control circuit, the control circuit controlling the memory cell array.    The method of claim 13, wherein the second wafer comprises a memory cell array, and wherein the first wafer comprises a control circuit that controls the memory cell array.    The method of claim 13, wherein the thinning is performed to be less than 10 microns.    The method of claim 13, further comprising: a first plurality of connections to the first external device; and a second plurality of connections to the first external device or the second external device, wherein the first plurality of connections At least a portion of the connections are over the second transistors, and wherein at least a portion of the second plurality of connections are below the second transistors.