CN111033728A

CN111033728A - Bonded semiconductor device with programmable logic device and dynamic random access memory and method of forming the same

Info

Publication number: CN111033728A
Application number: CN201980002583.2A
Authority: CN
Inventors: 刘峻; 程卫华
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2019-04-15
Filing date: 2019-10-14
Publication date: 2020-04-17
Also published as: US20200328190A1; US11721668B2; US20210175211A1; US11996389B2

Abstract

Embodiments of a semiconductor device and a method of manufacturing the same are disclosed. In an example, a semiconductor device includes a first semiconductor structure including a programmable logic device, an array of Static Random Access Memory (SRAM) cells, and a first bonding layer including a plurality of first bonding contacts. The semiconductor device also includes a second semiconductor structure including an array of Dynamic Random Access Memory (DRAM) cells, and a second bonding layer including a plurality of second bonding contacts. The semiconductor device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contact is in contact with the second bonding contact at the bonding interface.

Description

Bonded semiconductor device with programmable logic device and dynamic random access memory and method of forming the same

Cross Reference to Related Applications

International application nos. pct/CN2019/082607 filed in 2019, month 11 AND entitled "bonded semiconductor device with PROCESSOR AND dynamic random ACCESS MEMORY AND method of FORMING the same" (bonded semiconductor device DEVICES HAVING process AND dynamic random ACCESS MEMORY dom-ACCESS MEMORY AND method FOR FORMING the same) "AND international application nos. pct/CN2019/105290 AND 2019, month 15 filed in 2019 AND entitled" INTEGRATION of three-DIMENSIONAL NAND MEMORY device with multifunction chip (INTEGRATION of three-DIMENSIONAL MEMORY device AND multiple DEVICES manufacturing method using semiconductor device CHIPS) "are claimed AND incorporated herein by reference in their entirety.

Technical Field

Embodiments of the present disclosure relate to a semiconductor device and a method of manufacturing the same.

Background

A Field Programmable Gate Array (FPGA) is a reprogrammable integrated circuit containing an array of programmable logic blocks. The adoption of FPGA chips is driven by their flexibility, hardware timing speed and reliability, and parallelism. FPGAs provide benefits to designers of many types of electronic devices, including smart energy networks, aircraft navigation, motorist assistance, medical ultrasound, and data center search engines. Today, FPGAs are also receiving increasing attention in another area: deep Neural Networks (DNNs) for Artificial Intelligence (AI), such as in the analysis of large amounts of data for machine learning.

Disclosure of Invention

Embodiments of a semiconductor device and a method of manufacturing the same are disclosed.

In one example, a semiconductor device includes a first semiconductor structure including a programmable logic device, an array of Static Random Access Memory (SRAM) cells, and a first bonding layer including a plurality of first bonding contacts. The semiconductor device also includes a second semiconductor structure including an array of DRAM cells and a second bonding layer including a plurality of second bonding contacts. The semiconductor device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contact is in contact with the second bonding contact at the bonding interface.

In another example, a method for forming a semiconductor device is disclosed. A plurality of first semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures comprises: the programmable logic device includes a programmable logic device, an array of SRAM cells, and a first bonding layer including a plurality of first bonding contacts. A plurality of second semiconductor structures is formed on the second wafer. At least one of the second semiconductor structures comprises: an array of DRAM cells, and a second bonding layer comprising a plurality of second bonding contacts. Bonding the first wafer and the second wafer in a face-to-face manner such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contact of the first semiconductor structure is in contact with the second bonding contact of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into a plurality of dies. At least one of the dies includes a bonded first semiconductor structure and a second semiconductor structure.

In yet another example, a method for forming a semiconductor device is disclosed. A plurality of first semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures comprises: the programmable logic device includes a programmable logic device, an array of SRAM cells, and a first bonding layer including a plurality of first bonding contacts. Dicing the first wafer into a plurality of first dies such that at least one of the first dies includes the at least one of the first semiconductor structures. A plurality of second semiconductor structures is formed on the second wafer. At least one of the second semiconductor structures comprises: an array of DRAM cells, and a second bonding layer comprising a plurality of second bonding contacts. Dicing the second wafer into a plurality of second dies such that at least one of the second dies includes the at least one of the second semiconductor structures. Bonding the first die and the second die in a face-to-face manner such that the first semiconductor structure is bonded to the second semiconductor structure. The first bonding contact of the first semiconductor structure is in contact with the second bonding contact of the second semiconductor structure at a bonding interface.

Drawings

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable a person skilled in the pertinent art to make and use the disclosure.

Fig. 1A illustrates a schematic view of a cross-section of an exemplary semiconductor device, in accordance with some embodiments.

Fig. 1B illustrates a schematic view of a cross-section of another exemplary semiconductor device, in accordance with some embodiments.

Fig. 2A illustrates a schematic plan view of an exemplary semiconductor structure with a programmable logic device and SRAM, in accordance with some embodiments.

Figure 2B illustrates a schematic plan view of an exemplary semiconductor structure with DRAM and peripheral circuitry, in accordance with some embodiments.

Fig. 3A illustrates a schematic plan view of an exemplary semiconductor structure with programmable logic devices, SRAMs, and peripheral circuits, in accordance with some embodiments.

Figure 3B illustrates a schematic plan view of an exemplary semiconductor structure with a DRAM, according to some embodiments.

Fig. 4A illustrates a cross-section of an exemplary semiconductor device, according to some embodiments.

Fig. 4B illustrates a cross-section of another exemplary semiconductor device, in accordance with some embodiments.

Fig. 5A illustrates a cross-section of yet another exemplary semiconductor device, according to some embodiments.

Fig. 5B illustrates a cross-section of yet another exemplary semiconductor device, in accordance with some embodiments.

Fig. 6A and 6B illustrate a fabrication process for forming an exemplary semiconductor structure with a programmable logic device, SRAM, and peripheral circuitry, in accordance with some embodiments.

Figures 7A-7C illustrate a fabrication process for forming an exemplary semiconductor structure with DRAM and peripheral circuitry, in accordance with some embodiments.

Fig. 8A and 8B illustrate a fabrication process for forming an exemplary semiconductor device, according to some embodiments.

Fig. 9A-9C illustrate a fabrication process for bonding and dicing an exemplary semiconductor structure, according to some embodiments.

Fig. 10A-10C illustrate a fabrication process for cutting and bonding an exemplary semiconductor structure, according to some embodiments.

Fig. 11 is a flow chart of an exemplary method for forming a semiconductor device according to some embodiments.

Fig. 12 is a flow chart of another exemplary method for forming a semiconductor device according to some embodiments.

Fig. 13 is a flow chart of an example method for programming a semiconductor device having a programmable logic device and an SRAM, in accordance with some embodiments.

Embodiments of the present disclosure will be described with reference to the accompanying drawings.

Detailed Description

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the relevant art will recognize that other configurations and arrangements can be used without parting from the spirit and scope of the disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used in a variety of other applications.

It should be noted that references in the specification to "one embodiment," "an example embodiment," "some embodiments," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, and/or characteristic in connection with other embodiments whether or not explicitly described.

In general, terms may be understood, at least in part, according to usage in context. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular or may be used to describe a combination of features, structures, or characteristics in the plural, depending, at least in part, on the context. Similarly, terms such as "a," "an," or "the" may still be understood to convey a singular use or to convey a plural use, depending, at least in part, on the context. Additionally, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, but may instead, depending at least in part on the context, allow for the presence of other factors not necessarily explicitly described.

It will be readily understood that the meanings of "on … …", "above … …", and "above … …" in this disclosure should be interpreted in the broadest manner such that "on … …" means not only "directly on … … (something), but also includes the meaning of" on … … (something) with intervening features or layers therebetween, and "above … …" or "above … …" means not only "above … … (something)" or "above … … (something)" but may also include the meaning of "above … … (something) or" above … … (something) without intervening features or layers therebetween (i.e., directly on something).

Furthermore, spatially relative terms, such as "below … …," "below … …," "lower," "above … …," "upper," and the like, may be used for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the term "substrate" refers to a material to which a subsequent layer of material is to be added. The substrate itself may be patterned. The material added atop the substrate may be patterned or may remain unpatterned. In addition, the substrate may comprise a wide range of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be composed of a non-conductive material such as glass, plastic, or sapphire wafers.

As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The layer may extend over the entirety of the underlying or overlying structure, or may have a smaller extent than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of the continuous structure having a thickness less than the thickness of the homogeneous or heterogeneous continuous structure. For example, a layer may be located between any pair of horizontal planes between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. The layers may extend horizontally, vertically, and/or along a tapered surface. The substrate may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, above, and/or below. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers (where interconnect lines, and/or via contacts are formed) and one or more dielectric layers.

As used herein, the term "about" indicates a value of a given amount that may vary based on the particular technology node associated with the subject semiconductor device. The term "about" can indicate that a given amount of a value can vary, for example, within 10-30% of the value (e.g., ± 10%, ± 20%, or ± 30% of the value), based on the particular technology node.

As used herein, a "wafer" is a block of semiconductor material in and/or on which semiconductor devices are built and may undergo various fabrication processes before being separated into dies.

The use of Programmable Logic Devices (PLDs), particularly FPGAs, is limited by their cost and frequency of operation. The relatively large chip area consumption of FPGA chips results in high cost and signal propagation delays, such as resistance-capacitance (RC) delays from metal wiring, limiting the operating frequency.

Various embodiments according to the present disclosure provide a semiconductor device having a programmable logic device core, a cache (cache), and a main memory integrated on a bonded chip to achieve higher operating frequency, wider data bandwidth, lower power consumption, and lower cost. The semiconductor device disclosed herein may include: a first semiconductor structure having a programmable logic device core and an SRAM (e.g., as a cache); and a second semiconductor structure having a DRAM (e.g., as a main memory), the second semiconductor structure bonded to the first semiconductor structure by a large number of short-range vertical metal interconnects rather than peripherally distributed long-range metal wires or even conventional through-silicon vias (TSVs). In some embodiments, a programmable logic device core includes a large number of programmable logic blocks to increase the efficiency of chip area utilization, thereby reducing cost.

As a result, shorter manufacturing cycle times can be achieved at higher yields due to less interaction in the fabrication of programmable logic devices from programmable logic device wafers and DRAM wafers and known good hybrid bonding yields. Shorter connection distances between the programmable logic device and the DRAM (such as from millimeter or centimeter to micron levels) may improve device performance at faster data transfer rates, improve programmable logic device core logic efficiency at wider bandwidths, and improve system speed.

Fig. 1A illustrates a schematic view of a cross-section of an exemplary semiconductor device 100, in accordance with some embodiments. Semiconductor device 100 represents an example of a bonded chip. The components of semiconductor device 100 (e.g., PLD/SRAM and DRAM) may be formed independently on different substrates and then bonded to form a bonded chip. The semiconductor device 100 may include a first semiconductor structure 102, the first semiconductor structure 102 including an array of programmable logic devices and SRAM cells. In some embodiments, the programmable logic device and the SRAM cell array in the first semiconductor structure 102 use Complementary Metal Oxide Semiconductor (CMOS) technology. Both the programmable logic device and the SRAM cell array may be implemented in advanced logic processes (e.g., technology nodes of 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.) to achieve high speed.

A programmable logic device is an electronic component for constructing a reconfigurable digital circuit, which has an undefined function at the time of manufacture and is programmed (reconfigured) by using a program after manufacture. Programmable logic devices may include, for example, Programmable Logic Arrays (PLAs), Programmable Array Logic (PALs), Generic Array Logic (GALs), Complex Programmable Logic Devices (CPLDs), and FPGAs.

An FPGA is an integrated circuit that can be configured by a consumer or designer after manufacture using a Hardware Description Language (HDL), i.e., "field programmable". According to some embodiments, an FPGA includes an array of programmable logic blocks and a hierarchy of reconfigurable interconnects that allow the programmable logic blocks to be connected in different configurations to implement different logic functions. Programmable logic blocks, also called Configurable Logic Blocks (CLBs), slices or logic cells, are basic logic cells of FPGAs and can be composed of two basic components: flip-flops, and look-up tables (LUTs). Some FPGAs also include fixed function logic blocks (e.g., multipliers), memory (e.g., embedded RAM), and input/output (I/O) blocks.

According to some embodiments, unlike processors, FPGAs are truly parallel in nature, so different processing operations do not have to compete for the same resources. Each independent processing task may be assigned to a dedicated part of the FPGA and may function autonomously without any influence from other logic blocks. As a result, according to some embodiments, the performance of a portion of the application is not affected when more processing is added. In some embodiments, another benefit of FPGAs compared to processor-based systems is that the application logic is implemented in hardware circuitry, rather than executing on top of the Operating System (OS), drivers, and application software.

In addition to programmable logic devices, other processing elements (also referred to as "logic circuits") may also be formed in the first semiconductor structure 102, such as all or a portion of the peripheral circuitry of the DRAM of the second semiconductor structure 104. The peripheral circuits (also referred to as control and sense circuits) may include any suitable digital, analog, and/or mixed-signal circuits for facilitating operation of the DRAM. For example, the peripheral circuitry may include one or more of: input/output buffers, decoders (e.g., row and column decoders), sense amplifiers, or any active or passive component of a circuit (e.g., a transistor, diode, resistor, or capacitor).

SRAM is integrated on the same substrate as logic circuits (e.g., programmable logic devices and peripheral circuits), allowing for wider busses and higher operating speeds, which is also referred to as "on-die SRAM. The memory controller of the SRAM may be embedded as part of the peripheral circuitry. In some embodiments, each SRAM cell includes a plurality of transistors for storing a data bit as a positive or negative charge and one or more transistors to control access thereto. In one example, each SRAM cell has six transistors (e.g., Metal Oxide Semiconductor Field Effect Transistors (MOSFETs)), e.g., four transistors for storing data bits and two transistors for controlling access to data. SRAM cells may be located in areas not occupied by logic circuits (e.g., programmable logic devices and peripheral circuits) and thus do not require the formation of additional space. The on-die SRAM may enable high-speed operation of the semiconductor device 100, serving as one or more caches (e.g., an instruction cache or a data cache) and/or data buffers. In some embodiments, SRAM is used to store data sets or to transfer values between parallel tasks. In some embodiments, SRAM is used to support reprogramming of programmable logic devices, such as Partial Reconfiguration (PR) of an FPGA, which dynamically reconfigures a portion of the FPGA while the rest of the FPGA design continues to function.

The semiconductor device 100 may also include a second semiconductor structure 104 that includes an array of DRAM cells. That is, the second semiconductor structure 104 may be a DRAM memory device. DRAM requires periodic refreshing of memory cells. A memory controller for refreshing a DRAM may be embedded as another example of the peripheral circuit described above. In some embodiments, each DRAM cell includes a capacitor for storing a data bit as a positive or negative charge and one or more transistors that control access thereto. In one example, each DRAM cell is a one transistor, one capacitor (1T1C) cell.

As shown in fig. 1A, the semiconductor device 100 further includes a bonding interface 106 vertically located between the first semiconductor structure 102 and the second semiconductor structure 104. As described in detail below, the first and

second semiconductor structures

102 and 104 may be fabricated independently (and in some embodiments in parallel) such that a thermal budget for fabricating one of the first and

second semiconductor structures

102 and 104 does not limit a process for fabricating the other of the first and

second semiconductor structures

102 and 104. Furthermore, a large number of interconnects (e.g., bond contacts) may be formed via the bond interface 106 to make direct, short-range (e.g., micron-scale) electrical connections between the first and

second semiconductor structures

102 and 104, as opposed to long-range (e.g., millimeter or centimeter-scale) chip-to-chip data buses on a circuit board, such as a Printed Circuit Board (PCB), thereby eliminating chip interface delays and achieving high-speed I/O throughput with reduced power consumption. Data transfer between the DRAMs in the second semiconductor structure 104 and the programmable logic devices in the first semiconductor structure 102 and between the DRAMs in the second semiconductor structure 104 and the SRAMs in the first semiconductor structure 102 may be performed through interconnects (e.g., bonding contacts) across the bonding interface 106. By vertically integrating the first and

second semiconductor structures

102 and 104, the chip size may be reduced and the memory cell density may be increased. Further, as a "monolithic" chip, faster system speeds and smaller PCB sizes may also be achieved by integrating multiple discrete chips (e.g., programmable logic devices and various memories) into a single bonded chip (e.g., semiconductor device 100).

It should be understood that the relative positions of the stacked first and

second semiconductor structures

102 and 104 are not limited. Fig. 1B shows a schematic, schematic view of a cross-section of another exemplary semiconductor device 101, in accordance with some embodiments. Unlike the semiconductor device 100 in fig. 1A, in which the second semiconductor structure 104 comprising an array of DRAM cells is over the first semiconductor structure 102 comprising an array of programmable logic devices and SRAM cells, in the semiconductor device 101 of fig. 1B, the first semiconductor structure 102 comprising an array of programmable logic devices and SRAM cells is over the second semiconductor structure 104 comprising an array of DRAM cells. However, according to some embodiments, the bonding interface 106 is vertically formed between the first and

second semiconductor structures

102 and 104 in the semiconductor device 101, and the first and

second semiconductor structures

102 and 104 are vertically bonded by bonding (e.g., hybrid bonding). Data transfer between the DRAMs in the second semiconductor structure 104 and the programmable logic devices in the first semiconductor structure 102 and between the DRAMs in the second semiconductor structure 104 and the SRAMs in the first semiconductor structure 102 may be performed through interconnects (e.g., bond contacts) across the bonding interface 106.

Fig. 2A illustrates a schematic plan view of an exemplary semiconductor structure 200 having a programmable logic device and an SRAM, in accordance with some embodiments. The semiconductor structure 200 may be one example of the first semiconductor structure 102. The semiconductor structure 200 may include a Programmable Logic Device (PLD)202 on the same substrate as the SRAM204 and be fabricated using the same logic process as the SRAM 204. PLD202 may include one or more of PLA, PAL, GAL, CPLD, FPGA, to name a few. According to some embodiments, PLD202 includes one or more FPGA cores, each of which includes a plurality of programmable logic blocks 212 arranged in an array. For example, each programmable logic block 212 may include one or more LUTs. One or more of the programmable logic blocks 212 may be configured to perform independent processing tasks. In some embodiments, PLD202 also includes I/O block 214.

The SRAM204 may be disposed outside the PLD 202. For example, fig. 2A shows an exemplary layout of SRAM204, where an array of SRAM cells are distributed in multiple, independent areas in semiconductor structure 200 outside PLD 202. That is, the memory module formed by SRAM204 may be divided into smaller memory areas distributed outside PLD202 in semiconductor structure 200. In one example, the distribution of memory regions may be based on the design of the bonding contacts, e.g., occupying an area without bonding contacts. In another example, the distribution of storage areas may be random. As a result, more internal memory may be placed around PLD202 (e.g., using on-die SRAM) without taking up additional chip area.

Fig. 2B illustrates a schematic plan view of an exemplary semiconductor structure 201 with DRAM and peripheral circuitry, in accordance with some embodiments. The semiconductor structure 201 may be an example of the second semiconductor structure 104. Semiconductor structure 201 may include DRAM 206 on the same substrate as the peripheral circuitry of DRAM 206. Semiconductor structure 201 may include all peripheral circuitry for controlling and sensing DRAM 206, including: such as row decoder 208, column decoder 210, and any other suitable devices. Fig. 2B shows an exemplary layout of peripheral circuitry (e.g., row decoder 208, column decoder 210) and DRAM 206, where the peripheral circuitry (e.g., row decoder 208, column decoder 210) and DRAM 206 are formed in different regions on the same plane. For example, peripheral circuits (e.g., row decoder 208, column decoder 210) may be formed external to DRAM 206.

It should be understood that the layout of the

semiconductor structures

200 and 201 is not limited to the exemplary layout in fig. 2A and 2B. In some embodiments, a portion of the peripheral circuitry of DRAM 206 (e.g., one or more row decoders 208, column decoders 210, and any other suitable devices) may be in semiconductor structure 201 with PLD202 and SRAM 204. That is, according to some other embodiments, the peripheral circuitry of DRAM 206 may be distributed across both

semiconductor structures

200 and 201. In some embodiments, at least some of the peripheral circuitry (e.g., row decoder 208, column decoder 210) and DRAM 206 (e.g., an array of DRAM cells) are stacked on top of each other, i.e., in different planes. For example, the DRAM 206 (e.g., an array of DRAM cells) may be formed above or below the peripheral circuitry to further reduce chip size. Similarly, in some embodiments, at least a portion of PLD202 and SRAM204 (e.g., an array of SRAM cells) are stacked on top of each other, i.e., in different planes. For example, SRAM204 (e.g., an array of SRAM cells) may be formed above or below PLD202 to further reduce chip size.

Fig. 3A illustrates a schematic plan view of an exemplary semiconductor structure 300 having a programmable logic device, SRAM, and peripheral circuitry, in accordance with some embodiments. The semiconductor structure 300 may be one example of the first semiconductor structure 102. The semiconductor structure 300 may include the PLD202 on the same substrate as the SRAM204 and peripheral circuitry (e.g., row decoder 208, column decoder 210) and be fabricated using the same logic process as the SRAM204 and peripheral circuitry. PLD202 may include one or more of PLA, PAL, GAL, CPLD, FPGA, to name a few. According to some embodiments, PLD202 includes one or more FPGA cores, each of which includes programmable logic blocks 212 arranged in an array. For example, each programmable logic block 212 may include one or more LUTs. In some embodiments, PLD202 also includes I/O block 214.

The SRAM204 and peripheral circuitry (e.g., row decoder 208, column decoder 210) may both be disposed external to the PLD 202. For example, fig. 3A shows an exemplary layout of SRAM204, where an array of SRAM cells are distributed in multiple, independent areas in semiconductor structure 300 outside PLD 202. Semiconductor structure 300 may include all peripheral circuitry for controlling and sensing DRAM 206, including, for example, row decoder 208, column decoder 210, and any other suitable devices. Fig. 3A shows an exemplary layout of peripheral circuitry (e.g., row decoder 208, column decoder 210), where the peripheral circuitry (e.g., row decoder 208, column decoder 210) and SRAM204 are formed in different areas outside PLD202 on the same plane. It should be understood that in some embodiments, at least some of the peripheral circuitry (e.g., row decoder 208, column decoder 210), SRAM204 (e.g., an array of SRAM cells), and PLD202 are stacked on top of each other, i.e., in different planes. For example, SRAM204 (e.g., an array of SRAM cells) may be formed above or below peripheral circuitry to further reduce chip size.

Fig. 3B illustrates a schematic plan view of an exemplary semiconductor structure 301 having a DRAM, in accordance with some embodiments. The semiconductor structure 301 may be one example of the second semiconductor structure 104. By moving all peripheral circuitry (e.g., row decoder 208, column decoder 210) away from semiconductor structure 301 (e.g., to semiconductor structure 300), the size of DRAM 206 (e.g., the number of DRAM cells) in semiconductor structure 301 may be increased.

Fig. 4A illustrates a cross-section of an exemplary semiconductor device 400 according to some embodiments. As one example of the semiconductor device 100 described above with respect to fig. 1A, the semiconductor device 400 is a bonded chip including a first semiconductor structure 402 and a second semiconductor structure 404 stacked over the first semiconductor structure 402. According to some embodiments, the first and

second semiconductor structures

402 and 404 are joined at a bonding interface 406 therebetween. As shown in fig. 4A, the first semiconductor structure 402 may include a substrate 408, which may include silicon (e.g., single crystal silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material.

The first semiconductor structure 402 of the semiconductor device 400 may include a device layer 410 over a substrate 408. Notably, the x-axis and y-axis are added in fig. 4A to further illustrate the spatial relationship of components in the semiconductor device 400. The substrate 408 includes two lateral surfaces (e.g., a top surface and a bottom surface) that extend laterally along the x-direction (lateral or width direction). As used herein, whether a component (e.g., a layer or device) is "on," "above," or "below" another component (e.g., a layer or device) of a semiconductor device (e.g., semiconductor device 400) is determined in the y-direction (vertical direction or thickness direction) relative to a substrate (e.g., substrate 408) of the semiconductor device when the substrate is located in the y-direction in the lowest plane of the semiconductor device. Throughout this disclosure, the same concepts used to describe spatial relationships are employed.

In some embodiments, device layer 410 includes a programmable logic device 412 on substrate 408 and an array of SRAM cells 414 on substrate 408 and external to programmable logic device 412. In some embodiments, device layer 410 also includes peripheral circuitry 416 on substrate 408 and external to programmable logic device 412. For example, the peripheral circuitry 416 may be part or all of the peripheral circuitry for controlling and sensing the DRAM of the semiconductor device 400, as described in detail below. In some embodiments, the programmable logic device 412 includes a plurality of transistors 418 that form an array of programmable logic blocks (in some cases any I/O blocks), as described in detail above. In some embodiments, the transistors 418 also form an array of SRAM cells 414 that function as, for example, a cache and/or data buffer for the semiconductor device 400. For example, an array of SRAM cells 414 may be used as data memory and/or internal instruction memory for programmable logic device 412. The array of SRAM cells 414 may be distributed in a plurality of separate regions in the first semiconductor structure 402. In some embodiments, the transistors 418 also form peripheral circuitry 416, i.e., any suitable digital, analog, and/or mixed signal control and sensing circuitry for facilitating operation of the DRAM, including but not limited to input/output buffers, decoders (e.g., row and column decoders), and sense amplifiers.

The transistor 418 may be formed "on" the substrate 408, with all or a portion of the transistor 418 formed in the substrate 408 (e.g., below a top surface of the substrate 408) and/or directly on the substrate 408. Isolation regions (e.g., Shallow Trench Isolation (STI) and doped regions (e.g., source and drain regions of transistor 418) may also be formed in the substrate 408 according to some embodiments, the transistor 418 is high speed, with advanced logic processes (e.g., technology nodes of 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

In some embodiments, the first semiconductor structure 402 of the semiconductor device 400 also includes an interconnect layer 420 above the device layer 410 to transmit electrical signals to and from the programmable logic device 412 and the array of SRAM cells 414 (and peripheral circuitry 416, if any) and the peripheral circuitry 416 (and peripheral circuitry 416, if any) of the SRAM cells 414. The interconnect layer 420 may include a plurality of interconnects (also referred to herein as "contacts"), including lateral interconnect lines and vertical interconnect access (via) contacts. As used herein, the term "interconnect" may broadly include any suitable type of interconnect, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. The interconnect layer 420 may also include one or more inter-layer dielectric (ILD) layers (also referred to as "inter-metal dielectric (IMD) layers") in which interconnect lines and via contacts may be formed. That is, the interconnect layer 420 may include interconnect lines and via contacts in multiple ILD layers. The interconnect lines and via contacts in the interconnect layer 420 may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof. The ILD layer in interconnect layer 420 may comprise a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant (low-k) dielectric, or any combination thereof. In some embodiments, devices in device layer 410 are electrically connected to each other through interconnects in interconnect layer 420. For example, an array of SRAM cells 414 may be electrically connected to programmable logic device 412 through interconnect layer 420.

As shown in fig. 4A, the first semiconductor structure 402 of the semiconductor device 400 may further include a bonding layer 422 at the bonding interface 406 and above the interconnect layer 420 and the device layer 410 (including the array of programmable logic devices 412 and SRAM cells 414). Bonding layer 422 may include a plurality of bonding contacts 424 and a dielectric that electrically isolates bonding contacts 424. Bonding contact 424 may comprise a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The remaining regions of bonding layer 422 may be formed of a dielectric including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. Bonding contact 424 and surrounding dielectric in bonding layer 422 may be used for hybrid bonding.

Similarly, as shown in fig. 4A, the second semiconductor structure 404 of the semiconductor device 400 may further include a bonding layer 426 at the bonding interface 406 and over the bonding layer 422 of the first semiconductor structure 402. The bonding layer 426 may include a plurality of bonding contacts 428 and a dielectric that electrically isolates the bonding contacts 428. The bonding contacts 428 may comprise a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The remaining regions of bonding layer 426 may be formed with a dielectric including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contact 428 and surrounding dielectric in the bonding layer 426 may be used for hybrid bonding. According to some embodiments, the bonding contact 428 contacts the bonding contact 424 at the bonding interface 406.

As described above, the second semiconductor structure 404 may be bonded on top of the first semiconductor structure 402 in a face-to-face manner at the bonding interface 406. In some embodiments, bonding interface 406 is disposed between

bonding layers

422 and 426 as a result of a hybrid bond (also referred to as a "hybrid metal/dielectric bond"), which is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer, such as solder or an adhesive), and can result in both a metal-to-metal bond and a dielectric-to-dielectric bond. In some embodiments, bonding interface 406 is where bonding layers 422 and 426 meet and bond. In practice, bonding interface 406 may be a layer having a thickness that includes a top surface of bonding layer 422 of first semiconductor structure 402 and a bottom surface of bonding layer 426 of second semiconductor structure 404.

In some embodiments, the second semiconductor structure 404 of the semiconductor device 400 further includes an interconnect layer 430 over the bonding layer 426 to transmit electrical signals. The interconnect layer 430 may include a plurality of interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects in interconnect layer 430 also include local interconnects, such as bit line contacts and word line contacts. The interconnect layer 430 may also include one or more ILD layers in which interconnect lines and via contacts may be formed. The interconnect lines and via contacts in interconnect layer 430 may comprise a conductive material including, but not limited to, W, Co, Cu, Al, suicide, or any combination thereof. The ILD layer in interconnect layer 430 may comprise a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof.

The second semiconductor structure 404 of the semiconductor device 400 may further include a device layer 432 above the interconnect layer 430 and the bonding layer 426. In some embodiments, device layer 432 includes an array of DRAM cells 450 above interconnect layer 430 and bonding layer 426. In some embodiments, each DRAM cell 450 includes a DRAM select transistor 436 and a capacitor 438. DRAM cell 450 may be a 1T1C cell consisting of one transistor and one capacitor. It should be appreciated that DRAM cells 450 may have any suitable configuration, such as 2T1C cells, 3T1C cells, and so forth. In some embodiments, DRAM select transistors 436 are formed "on" semiconductor layer 434, wherein all or a portion of DRAM select transistors 436 are formed in semiconductor layer 434 (e.g., below a top surface of semiconductor layer 434) and/or directly on semiconductor layer 434. Isolation regions (e.g., STI) and doped regions (e.g., source and drain regions of DRAM select transistor 436) may also be formed in semiconductor layer 434. In some embodiments, capacitor 438 is disposed below DRAM select transistor 436. According to some embodiments, each capacitor 438 includes two electrodes, one of which is electrically connected to a node of a corresponding DRAM select transistor 436. According to some embodiments, another node of each DRAM select transistor 436 is electrically connected to a DRAM bit line 440. The other electrode of each capacitor 438 may be electrically connected to a common plate 442, such as a common ground. It should be understood that the structure and configuration of DRAM cell 450 is not limited to the example in FIG. 4A and may include any suitable structure and configuration. For example, the capacitor 438 may be a planar capacitor, a stacked capacitor, a multi-fin capacitor, a cylindrical capacitor, a trench capacitor, or a substrate plate capacitor.

In some embodiments, the second semiconductor structure 404 further includes a semiconductor layer 434 disposed over the device layer 432. Semiconductor layer 434 may be over and in contact with the array of DRAM cells 450. Semiconductor layer 434 may be a thinned substrate on which DRAM select forming transistors 436 are formed. In some embodiments, semiconductor layer 434 comprises monocrystalline silicon. In some embodiments, semiconductor layer 434 may comprise polysilicon, amorphous silicon, SiGe, GaAs, Ge, or any other suitable material. Semiconductor layer 434 may also include isolation regions and doped regions (e.g., as sources and drains for DRAM select transistor 436).

As shown in fig. 4A, the second semiconductor structure 404 of the semiconductor device 400 may further include a pad-out interconnect layer 444 above the semiconductor layer 434. The bond pad exit interconnect layer 444 may include interconnects, such as contact pads 446, in one or more ILD layers. A pad extraction interconnect layer 444 and an interconnect layer 430 may be formed on opposite sides of the semiconductor layer 434. In some embodiments, the interconnects in pad extraction interconnect layer 444 may transmit electrical signals between semiconductor device 400 and external circuitry, for example for pad extraction purposes.

In some embodiments, second semiconductor structure 404 further includes one or more contacts 448 extending through semiconductor layer 434 to electrically connect pad out interconnect layer 444 and

interconnect layers

430 and 420. As a result, the programmable logic device 412 and the array of SRAM cells 414 (and peripheral circuitry 416, if any) may be electrically connected to the array of DRAM cells 450 through

interconnect layers

430 and 420 and

bond contacts

428 and 424. Further, the programmable logic device 412, the array of SRAM cells 414, and the array of DRAM cells 450 may be electrically connected to external circuitry through contacts 448 and pad out interconnect layer 444.

Fig. 4B illustrates a cross-section of another exemplary semiconductor device 401, in accordance with some embodiments. As one example of the semiconductor device 101 described above with respect to fig. 1B, the semiconductor device 401 is a bonded chip including the second semiconductor structure 403 and the first semiconductor structure 405 stacked over the second semiconductor structure 403. Similar to the semiconductor device 400 described above in fig. 4A, the semiconductor device 401 represents an example of a bonded chip in which a first semiconductor structure 405 including a programmable logic device and an SRAM and a second semiconductor structure 403 including a DRAM are formed separately and bonded in a face-to-face manner at a bonding interface 407. Unlike the semiconductor device 400 described above in fig. 4A, where the first semiconductor structure 402 including the programmable logic device and the SRAM is below the second semiconductor structure 404 including the DRAM, the semiconductor device 401 in fig. 4B includes the first semiconductor structure 405 including the programmable logic device and the SRAM disposed above the second semiconductor structure 403 including the DRAM. It is to be understood that details of similar structures (e.g., materials, fabrication processes, functions, etc.) in both

semiconductor devices

400 and 401 may not be repeated below.

The second semiconductor structure 403 of the semiconductor device 401 may include a substrate 409 and a device layer 411 over the substrate 409. Device layer 411 may include an array of DRAM cells 449 on substrate 409. In some embodiments, each DRAM cell 449 includes a DRAM select transistor 413 and a capacitor 415. DRAM cell 449 may be a 1T1C cell consisting of one transistor and one capacitor. It should be appreciated that DRAM cells 449 may have any suitable configuration, such as 2T1C cells, 3T1C cells, etc. In some embodiments, DRAM select transistor 413 is formed "on" substrate 409, where all or a portion of DRAM select transistor 413 is formed in substrate 409 and/or directly on substrate 409. In some embodiments, capacitor 415 is disposed over DRAM select transistor 413. According to some embodiments, each capacitor 415 includes two electrodes, one of which is electrically connected to a node of a corresponding DRAM select transistor 413. According to some embodiments, another node of each DRAM select transistor 413 is electrically connected to a DRAM bit line 417. The other electrode of each capacitor 415 may be electrically connected to a common plate 419, such as a common ground. It should be understood that the structure and configuration of DRAM cells 449 are not limited to the example in figure 4B and may include any suitable structure and configuration.

In some embodiments, second semiconductor structure 403 of semiconductor device 401 also includes an interconnect layer 421 over device layer 411 to transmit electrical signals to and from array of DRAM cells 449. The interconnect layer 421 may include a plurality of interconnects, including interconnect lines and via contacts. In some embodiments, the interconnects in interconnect layer 421 also include local interconnects, such as bit line contacts and word line contacts. In some embodiments, the second semiconductor structure 403 of the semiconductor device 401 further includes a bonding layer 423 at the bonding interface 407 and above the interconnect layer 421 and the device layer 411. Bonding layer 423 may include a plurality of bonding contacts 425 and a dielectric surrounding and electrically isolating bonding contacts 425.

As shown in fig. 4B, the first semiconductor structure 405 of the semiconductor device 401 includes another bonding layer 451 at the bonding interface 407 and above the bonding layer 423. The bonding layer 451 may include a plurality of bonding contacts 427 and a dielectric surrounding and electrically isolating the bonding contacts 427. According to some embodiments, the keying contacts 427 are in contact with the keying contacts 425 at the keying interface 407. In some embodiments, the first semiconductor structure 405 of the semiconductor device 401 further includes an interconnect layer 429 above the bonding layer 451 to transmit electrical signals. The interconnect layer 429 may include a plurality of interconnects, including interconnect lines and via contacts.

The first semiconductor structure 405 of the semiconductor device 401 may further include a device layer 431 over the interconnect layer 429 and the bonding layer 451. In some embodiments, device layer 431 includes a programmable logic device 435 over interconnect layer 429 and bonding layer 451, and an array of SRAM cells 437 over interconnect layer 429 and bonding layer 451 and external to programmable logic device 435. In some embodiments, the device layer 431 also includes peripheral circuitry 439 over the interconnect layer 429 and the bonding layer 451 and external to the programmable logic device 435. For example, peripheral circuitry 439 may be part or all of the peripheral circuitry for controlling and sensing the array of DRAM cells 449. In some embodiments, devices in device layer 431 are electrically connected to each other through interconnects in interconnect layer 429. For example, an array of SRAM cells 437 may be electrically connected to programmable logic device 435 through interconnect layer 429.

In some embodiments, programmable logic device 435 includes a plurality of transistors 441 that form an array of programmable logic blocks (and in some cases any I/O blocks), as described in detail above. Transistor 441 may be formed "on" semiconductor layer 433, where all or a portion of transistor 441 is formed in semiconductor layer 433 and/or directly on semiconductor layer 433. Isolation regions (e.g., STI) and doped regions (e.g., source and drain regions of transistor 441) may also be formed in semiconductor layer 433. The transistors 441 may form an array of SRAM cells 437 (and peripheral circuitry 439, if any). According to some embodiments, transistor 441 is high-speed with advanced logic processes (e.g., technology nodes of 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

In some embodiments, the first semiconductor structure 405 further includes a semiconductor layer 433 disposed over the device layer 431. Semiconductor layer 433 may be over and in contact with the array of programmable logic devices 435 and SRAM cells 437. The semiconductor layer 433 may be a thinned substrate on which the transistor 441 is formed. In some embodiments, semiconductor layer 433 comprises monocrystalline silicon. In some embodiments, semiconductor layer 433 may include polysilicon, amorphous silicon, SiGe, GaAs, Ge, or any other suitable material. Semiconductor layer 433 can also include isolation regions and doped regions.

As shown in fig. 4B, the first semiconductor structure 405 of the semiconductor device 401 may further include a pad extraction interconnect layer 443 over the semiconductor layer 433. The pad out interconnect layer 443 may include interconnects, such as contact pads 445, in one or more ILD layers. In some embodiments, the interconnects in the pad-out interconnect layer 443 may transmit electrical signals between the semiconductor device 401 and external circuitry, e.g., for pad-out purposes. In some embodiments, the first semiconductor structure 405 further includes one or more contacts 447 extending through the semiconductor layer 433 to electrically connect the pad out interconnect layer 443 and the interconnect layers 429 and 421. As a result, the array of programmable logic devices 435 and SRAM cells 437 (and peripheral circuitry 439, if any) may also be electrically connected to the array of DRAM cells 449 by

interconnect layers

429 and 421 and bond contacts 427 and 425. Further, the programmable logic device 435, the array of SRAM cells 437, and the array of DRAM cells 449 may be electrically connected to external circuitry through the contact 447 and the pad-out interconnect layer 443.

Fig. 5A illustrates a cross-section of yet another exemplary semiconductor device 500, according to some embodiments. Similar to the semiconductor device 400 described above in fig. 4, the semiconductor device 500 represents an example of a bonded chip including: a first semiconductor structure 502 having an array of programmable logic devices 512 and SRAM cells 514; and a second semiconductor structure 504 having an array of DRAM cells 536 over the first semiconductor structure 502. Unlike the semiconductor device 400 described above in fig. 4A (where the peripheral circuitry 416 is in the first semiconductor structure 402 and not in the second semiconductor structure 404), the peripheral circuitry 538 is formed in the second semiconductor structure 504 and the array of DRAM cells 536 is formed in the second semiconductor structure 504. Similar to the semiconductor device 400 described above in fig. 4A, the first and

second semiconductor structures

502 and 504 of the semiconductor device 500 are bonded in a face-to-face manner at a bonding interface 506, as shown in fig. 5A. It is to be understood that details of similar structures (e.g., materials, fabrication processes, functions, etc.) in both

semiconductor devices

400 and 500 may not be repeated below.

The first semiconductor structure 502 of the semiconductor device 500 may include a device layer 510 over a substrate 508. In some embodiments, the device layer 510 includes a programmable logic device 512 on the substrate 508, and an array of SRAM cells 514 on the substrate 508 and external to the programmable logic device 512. In some embodiments, programmable logic device 512 includes a plurality of transistors 518 that form an array of programmable logic blocks (and in some cases any I/O blocks), as described in detail above. In some embodiments, the transistors 518 also form an array of SRAM cells 514, which serve as, for example, a cache and/or data buffer for the semiconductor device 500.

In some embodiments, the first semiconductor structure 502 of the semiconductor device 500 also includes an interconnect layer 520 above the device layer 510 to transmit electrical signals to and from the array of programmable logic devices 512 and SRAM cells 514. Interconnect layer 520 may include a plurality of interconnects, including interconnect lines and via contacts. In some embodiments, the first semiconductor structure 502 of the semiconductor device 500 further includes a bonding layer 522 at the bonding interface 506 and above the interconnect layer 520 and the device layer 510 (including the programmable logic device 512 and the SRAM cell array 514). The bonding layer 522 may include a plurality of bonding contacts 524 and a dielectric surrounding and electrically isolating the bonding contacts 524.

Similarly, as shown in fig. 5A, the second semiconductor structure 504 of the semiconductor device 500 may further include a bonding layer 526 at the bonding interface 506 and over the bonding layer 522 of the first semiconductor structure 502. Bonding layer 526 may include a plurality of bonding contacts 528 and a dielectric that electrically isolates bonding contacts 528. According to some embodiments, the bonding contact 528 is in contact with the bonding contact 524 at the bonding interface 506. In some embodiments, the second semiconductor structure 504 of the semiconductor device 500 further includes an interconnect layer 530 above the bonding layer 526 to transmit electrical signals. The interconnect layer 530 may include a plurality of interconnects, including interconnect lines and via contacts.

The second semiconductor structure 504 of the semiconductor device 500 may further include a device layer 532 above the interconnect layer 530 and the bonding layer 526. In some embodiments, device layer 532 includes an array of DRAM cells 536 above interconnect layer 530 and bonding layer 526. In some embodiments, each DRAM cell 536 includes a DRAM select transistor 540 and a capacitor 542. DRAM cell 536 may be a 1T1C cell consisting of one transistor and one capacitor. It should be appreciated that DRAM cells 536 may have any suitable configuration, such as 2T1C cells, 3T1C cells, and so forth. In some embodiments, DRAM select transistors 540 are formed "on" semiconductor layer 534, wherein all or a portion of DRAM select transistors 540 are formed in semiconductor layer 534 (e.g., below a top surface of semiconductor layer 534) and/or directly on semiconductor layer 534. Isolation regions (e.g., STI) and doped regions (e.g., source and drain regions of DRAM select transistor 540) may also be formed in semiconductor layer 534. In some embodiments, capacitor 542 is disposed below DRAM select transistor 540. According to some embodiments, each capacitor 542 includes two electrodes, one of which is electrically connected to a node of a corresponding DRAM select transistor 540. According to some embodiments, another node of each DRAM select transistor 540 is electrically connected to a DRAM bit line 544. The other electrode of each capacitor 542 may be electrically connected to a common plate 546, such as a common ground. It should be understood that the structure and configuration of DRAM cell 536 is not limited to the example in fig. 5A and may include any suitable structure and configuration.

In some embodiments, device layer 532 also includes peripheral circuitry 538 above interconnect layer 530 and bonding layer 526 and outside the array of DRAM cells 536. For example, peripheral circuit 538 may be a portion or all of the peripheral circuitry used to control and sense the array of DRAM cells 536. In some embodiments, peripheral circuitry 538, including a plurality of transistors 548 forming any suitable digital, analog, and/or mixed signal control and sensing circuitry for facilitating operation of the array of DRAM cells 536, includes, but is not limited to, input/output buffers, decoders (e.g., row and column decoders), and sense amplifiers. The peripheral circuitry 538 and the array of DRAM cells 536 may be electrically connected by interconnects of the interconnect layer 530.

In some embodiments, the second semiconductor structure 504 further includes a semiconductor layer 534 disposed over the device layer 532. Semiconductor layer 534 can be over and in contact with the array of DRAM cells 536. Semiconductor layer 534 can be a thinned substrate on which transistor 548 and DRAM select transistor 540 are formed. In some embodiments, semiconductor layer 534 comprises monocrystalline silicon. In some embodiments, semiconductor layer 534 may include polysilicon, amorphous silicon, SiGe, GaAs, Ge, or any other suitable material. Semiconductor layer 534 may also include isolation regions and doped regions.

As shown in fig. 5A, the second semiconductor structure 504 of the semiconductor device 500 may further include a pad extraction interconnect layer 550 above the semiconductor layer 534. The pad out interconnect layer 550 includes interconnects, such as contact pads 552, in one or more ILD layers. In some embodiments, the interconnects in the pad-out interconnect layer 550 may transmit electrical signals between the semiconductor device 500 and external circuitry, e.g., for pad-out purposes. In some embodiments, second semiconductor structure 504 further includes one or more contacts 554, the contacts 554 extending through semiconductor layer 534 to electrically connect pad extraction interconnect layer 550 and

interconnect layers

530 and 520. As a result, the array of programmable logic devices 512 and SRAM cells 514 may be electrically connected to the array of DRAM cells 536 through

interconnect layers

530 and 520 and

bond contacts

528 and 524. In addition, the programmable logic device 512, the array of SRAM cells 514, and the array of DRAM cells 536 may be electrically connected to external circuitry through contacts 554 and pad-out interconnect layers 550.

Fig. 5B illustrates a cross-section of yet another exemplary semiconductor device 501 according to some embodiments. As one example of the semiconductor device 101 described above with respect to fig. 1B, the semiconductor device 501 is a bonded chip including the second semiconductor structure 503 and the first semiconductor structure 505 stacked over the second semiconductor structure 503. Similar to the semiconductor device 500 described above in fig. 5A, the semiconductor device 501 represents an example of a bonded chip in which a first semiconductor structure 505 including a programmable logic device and an SRAM and a second semiconductor structure 503 including a peripheral circuit and a DRAM are independently formed and bonded in a face-to-face manner at a bonding interface 507. Unlike the semiconductor device 500 described above in fig. 5 (in which the first semiconductor structure 502 including the programmable logic device and the SRAM is below the second semiconductor structure 504 including the peripheral circuit and the DRAM), the semiconductor device 501 in fig. 5B includes the first semiconductor structure 505 including the programmable logic device and the SRAM disposed above the second semiconductor structure 503 including the peripheral circuit and the DRAM. It is to be understood that details of similar structures (e.g., materials, fabrication processes, functions, etc.) in both

semiconductor devices

500 and 501 may not be repeated below.

The second semiconductor structure 503 of the semiconductor device 501 may include a substrate 509 and a device layer 511 over the substrate 509. The device layer 511 may include an array of DRAM cells 513 on a substrate 509. In some embodiments, each DRAM cell 513 includes a DRAM select transistor 517 and a capacitor 519. DRAM cell 513 may be a 1T1C cell consisting of one transistor and one capacitor. It should be appreciated that DRAM cells 513 may have any suitable configuration, such as 2T1C cells, 3T1C cells, and so forth. In some embodiments, DRAM select transistors 517 are formed "on" substrate 509, with all or a portion of DRAM select transistors 517 being formed in substrate 509 and/or directly on substrate 509. In some embodiments, the capacitor 519 is disposed over the DRAM select transistor 517. According to some embodiments, each capacitor 519 includes two electrodes, one of which is electrically connected to a node of a corresponding DRAM select transistor 517. According to some embodiments, another node of each DRAM select transistor 517 is electrically connected to a bitline 521 of the DRAM. The other electrode of each capacitor 519 may be electrically connected to a common plate 523, such as a common ground. It should be understood that the structure and configuration of DRAM cell 513 is not limited to the example in fig. 5B and may include any suitable structure and configuration.

In some embodiments, device layer 511 also includes peripheral circuitry 515 on substrate 509 and external to the array of DRAM cells 513. For example, peripheral circuit 515 may be part or all of a peripheral circuit for controlling and sensing an array of DRAM cells 513. In some embodiments, peripheral circuitry 515 includes a plurality of transistors 525 forming any suitable digital, analog, and/or mixed-signal control and sensing circuitry for facilitating operation of the array of DRAM cells 513, including, but not limited to, input/output buffers, decoders (e.g., row and column decoders), and sense amplifiers.

In some embodiments, the second semiconductor structure 503 of the semiconductor device 501 further includes an interconnect layer 527 above the device layer 511 to transmit electrical signals to and from the array of DRAM cells 513. The interconnect layer 527 may include a plurality of interconnects, including interconnect lines and via contacts. In some embodiments, the interconnects in interconnect layer 527 also include local interconnects, such as bit line contacts and word line contacts. The peripheral circuitry 515 and the array of DRAM cells 513 may be electrically connected by interconnects of an interconnect layer 527. In some embodiments, the second semiconductor structure 503 of the semiconductor device 501 further includes a bonding layer 529 at the bonding interface 507 and over the interconnect layer 527 and the device layer 511. Bonding layer 529 may include a plurality of bonding contacts 531 and a dielectric surrounding and electrically isolating bonding contacts 531.

As shown in fig. 5B, first semiconductor structure 505 of semiconductor device 501 includes another bonding layer 533 at bonding interface 507 and above bonding layer 529. Bonding layer 533 may include a plurality of bonding contacts 535 and a dielectric surrounding and electrically isolating bonding contacts 535. According to some embodiments, the bonding contact 535 contacts the bonding contact 531 at the bonding interface 507. In some embodiments, the first semiconductor structure 505 of the semiconductor device 501 further includes an interconnect layer 537 above the bonding layer 533 to transport electrical signals. The interconnect layer 537 may include a plurality of interconnects, including interconnect lines and via contacts.

The first semiconductor structure 505 of the semiconductor device 501 may further include a device layer 539 above the interconnect layer 537 and the bonding layer 533. In some embodiments, device layer 539 includes programmable logic device 543 above interconnect layer 537 and bonding layer 533, and an array of SRAM cells 545 above interconnect layer 537 and bonding layer 533 and external to programmable logic device 543. In some embodiments, the devices in device layer 539 are electrically connected to each other by interconnects in interconnect layer 537. For example, an array of SRAM cells 545 may be electrically connected to programmable logic device 543 through interconnect layer 537.

In some embodiments, the programmable logic device 543 includes a plurality of transistors 547 that form an array of programmable logic blocks (and in some cases, I/O blocks). The transistor 547 can be formed "over" the semiconductor layer 541, wherein all or a portion of the transistor 547 is formed in the semiconductor layer 541 and/or directly over the semiconductor layer 541. Isolation regions (e.g., STI) and doped regions (e.g., source and drain regions of transistor 547) may also be formed in semiconductor layer 541. The transistors 547 may also form an array of SRAM cells 545. According to some embodiments, the transistor 547 is a high speed, advanced logic process (e.g., 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc. technology nodes).

In some embodiments, the first semiconductor structure 505 further includes a semiconductor layer 541 disposed over the device layer 539. The semiconductor layer 541 may be over and in contact with the array of programmable logic devices 543 and SRAM cells 545. The semiconductor layer 541 may be a thinned substrate over which the transistor 547 is formed. In some embodiments, the semiconductor layer 541 comprises single crystal silicon. In some embodiments, semiconductor layer 541 may include polysilicon, amorphous silicon, SiGe, GaAs, Ge, or any other suitable material. Semiconductor layer 541 may also include isolation regions and doped regions.

As shown in fig. 5B, the first semiconductor structure 505 of the semiconductor device 501 may further include a pad extraction interconnect layer 549 over the semiconductor layer 541. Pad extraction interconnect layer 549 includes interconnects, e.g., contact pads 551, in one or more ILD layers. In some embodiments, interconnects in pad pull interconnect layer 549 may transmit electrical signals between semiconductor device 501 and external circuitry, e.g., for pad pull purposes. In some embodiments, the first semiconductor structure 505 further includes one or more contacts 553, the contacts 553 extending through the semiconductor layer 541 to electrically connect the pad extraction interconnect layer 549 and the interconnect layers 537 and 527. As a result, the array of programmable logic devices 543 and SRAM cells 545 can be electrically connected to the array of DRAM cells 513 through

interconnect layers

537 and 527 and bonding contacts 535 and 531. In addition, the programmable logic device 543, the array of SRAM cells 545, and the array of DRAM cells 513 may be electrically connected to external circuitry through contacts 553 and pad out interconnect layers 549.

Fig. 6A and 6B illustrate a fabrication process for forming an exemplary semiconductor structure with a programmable logic device, SRAM, and peripheral circuitry, in accordance with some embodiments. Figures 7A-7C illustrate a fabrication process for forming an exemplary semiconductor structure with DRAM and peripheral circuitry, in accordance with some embodiments. Fig. 8A and 8B illustrate a fabrication process for forming an exemplary semiconductor device, according to some embodiments. Fig. 9A-9C illustrate a fabrication process for bonding and dicing an exemplary semiconductor structure, according to some embodiments. Fig. 10A-10C illustrate a fabrication process for cutting and bonding an exemplary semiconductor structure, according to some embodiments. Fig. 11 is a flow diagram of an exemplary method 1100 for forming a semiconductor device according to some embodiments. Fig. 12 is a flow chart of another exemplary method 1200 for forming a semiconductor device according to some embodiments. Examples of the semiconductor devices depicted in fig. 6A, 6B, 7A-7C, 8A, 8B, 9A-9C, 10A-10C, 11, and 12 include the

semiconductor devices

400, 401, 500, 501 depicted in fig. 4A, 4B, 5A, and 5B, respectively. FIGS. 6A, 6B, 7A-7C, 8A, 8B, 9A-9C, 10A-10C, 11 and 12 will be described together. It should be understood that the operations illustrated in

methods

1100 and 1200 are not exhaustive, and that other operations may be performed before, after, or between any of the illustrated operations. Further, some operations may be performed simultaneously, or in a different order than that shown in fig. 11 and 12.

As depicted in fig. 6A and 6B, a first semiconductor structure is formed that includes a programmable logic device, an array of SRAM cells, peripheral circuitry, and a first bonding layer that includes a plurality of first bonding contacts. As depicted in fig. 7A-7C, a second semiconductor structure is formed that includes an array of DRAM cells, peripheral circuitry, and a second bonding layer that includes a plurality of second bonding contacts. As depicted in fig. 8A and 8B, the first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner such that the first bonding contact is in contact with the second bonding contact at the bonding interface.

Referring to fig. 11, the method 1100 begins at operation 1102, where a plurality of first semiconductor structures is formed on a first wafer. At least one of the first semiconductor structures includes a programmable logic device, an array of SRAM cells, and a first bonding layer including a plurality of first bonding contacts. The first wafer may be a silicon wafer. In some embodiments, to form a plurality of first semiconductor structures, an array of programmable logic devices and SRAM cells is formed on a first wafer. In some embodiments, to form an array of programmable logic devices and SRAM cells, a plurality of transistors are formed on a first wafer. In some embodiments, to form a plurality of first semiconductor structures, peripheral circuitry for an array of DRAM cells is also formed on the first wafer.

As shown in fig. 9A, a plurality of first semiconductor structures 906 are formed on the first wafer 902. The first wafer 902 may include a plurality of shots (shots) separated by scribe lines. According to some embodiments, each picture of the first wafer 902 includes one or more first semiconductor structures 906. Fig. 6A and 6B illustrate one example of the formation of a first semiconductor structure 906.

As shown in fig. 6A, a plurality of transistors 604 are formed on a silicon substrate 602 (as part of a first wafer 902, e.g., a silicon wafer). Transistor 604 may be formed by a number of processes including, but not limited to, photolithography, dry/wet etching, thin film deposition, thermal growth, implantation, Chemical Mechanical Polishing (CMP), and any other suitable process. In some embodiments, doped regions are formed in the silicon substrate 602 by ion implantation and/or thermal diffusion, which serve, for example, as source and/or drain regions for the transistor 604. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 602 by wet/dry etching and thin film deposition. The transistor 604 may form a device layer 606 on the silicon substrate 602. In some embodiments, device layer 606 includes programmable logic device 608, an array of SRAM cells 610, and peripheral circuitry 612.

The method 1100 proceeds to operation 1104, as shown in FIG. 11, where a first interconnect layer is formed over the array of programmable logic devices and SRAM cells. The first interconnect layer may include a first plurality of interconnects in one or more ILD layers. As shown in fig. 6B, an interconnect layer 614 may be formed over the device layer 606 including the programmable logic device 608 and the array of SRAM cells 610. The interconnect layer 614 may include MEOL and/or BEOL interconnects in a plurality of ILDs to make electrical connections with the device layer 606. In some embodiments, interconnect layer 614 includes multiple ILD layers and interconnects formed therein in multiple processes. For example, the interconnects in interconnect layer 614 may comprise conductive materials deposited by one or more thin film deposition processes including, but not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), electroplating, electroless plating, or any combination thereof. The fabrication process to form the interconnects may also include photolithography, CMP, wet/dry etching, or any other suitable process. The ILD layer may comprise a dielectric material deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. The ILD layers and interconnects shown in fig. 6B may be collectively referred to as interconnect layers 614.

The method 1100 proceeds to operation 1106, as shown in fig. 11, where a first bonding layer is formed over the first interconnect layer. The first bonding layer may include a plurality of first bonding contacts. As shown in fig. 6B, a bonding layer 616 is formed over interconnect layer 614. Bonding layer 616 may include a plurality of bonding contacts 618 surrounded by dielectric. In some embodiments, the dielectric layer is deposited on the top surface of the interconnect layer 614 by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. The contact holes through the dielectric layer may then be first patterned by using a patterning process (e.g., photolithography and dry/wet etching of the dielectric material in the dielectric layer), forming bonding contacts 618 through the dielectric layer and in contact with the interconnects in interconnect layer 614. The contact holes may be filled with a conductor (e.g., copper). In some embodiments, filling the contact hole includes depositing a barrier layer, an adhesion layer, and/or a seed layer prior to depositing the conductor.

The method 1100 proceeds to operation 1108 as shown in fig. 11, where a plurality of second semiconductor structures are formed on the second wafer. At least one of the second semiconductor structures includes an array of DRAM cells and a second bonding layer including a plurality of second bonding contacts. The second wafer may be a silicon wafer. In some embodiments, to form a plurality of second semiconductor structures, an array of DRAM cells is formed on the second wafer. In some embodiments, to form an array of DRAM cells, a plurality of transistors are formed on the second wafer, and a plurality of capacitors are formed over and in contact with at least some of the transistors. In some embodiments, to form a plurality of second semiconductor structures, peripheral circuitry of the array of DRAM cells is also formed on the second wafer.

As shown in fig. 9A, a plurality of second semiconductor structures 908 are formed on the second wafer 904. The second wafer 904 may include a plurality of pictures separated by scribe lines. According to some embodiments, each frame of the second wafer 904 includes one or more second semiconductor structures 908. Fig. 7A-7C illustrate one example of the formation of the second semiconductor structure 908.

As shown in fig. 7A, a plurality of transistors 704 (as part of a second wafer 904, e.g., a silicon wafer) are formed on a silicon substrate 702. Transistor 704 may be formed by a number of processes including, but not limited to, photolithography, dry/wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. In some embodiments, doped regions are formed in the silicon substrate 702 by ion implantation and/or thermal diffusion, which serve, for example, as source and/or drain regions for the transistor 704. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 702 by wet/dry etching and thin film deposition.

As shown in fig. 7B, a plurality of capacitors 706 are formed over and in contact with at least some of the transistors 704 (i.e., DRAM select transistors). Each capacitor 706 may be patterned to align with a corresponding DRAM select transistor by photography to form a 1T1C memory cell, for example, by electrically connecting one electrode of the capacitor 706 with one node of the corresponding DRAM select transistor. In some embodiments, bit lines 707 and common plate 709 are also formed to electrically connect the DRAM select transistors and capacitors 706. The capacitor 706 may be formed by a number of processes including, but not limited to, photolithography, dry/wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. Forming a device layer 708 comprising an array of DRAM cells 710 (each having a DRAM select transistor and a capacitor 706) and peripheral circuitry 711 (having transistors 704 other than DRAM select transistors).

The method 1100 proceeds to operation 1110, shown in FIG. 11, where a second interconnect layer is formed over the array of DRAM cells. The second interconnect layer may include a second plurality of interconnects in one or more ILD layers. As shown in fig. 7C, an interconnect layer 714 may be formed over the array of DRAM cells 710. Interconnect layer 714 may include MEOL and/or BEOL interconnects in multiple ILD layers to make electrical connections to the array of DRAM cells 710 (and peripheral circuitry 711, if present). In some embodiments, the interconnect layer 714 includes multiple ILD layers and interconnects formed therein in multiple processes. For example, the interconnects in interconnect layer 714 may comprise conductive material deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication process to form the interconnects may also include photolithography, CMP, wet/dry etching, or any other suitable process. The ILD layer may comprise a dielectric material deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. The ILD layer and interconnects shown in fig. 7C may be collectively referred to as interconnect layer 714.

The method 1100 proceeds to operation 1112, as shown in fig. 11, where a second bonding layer is formed over the second interconnect layer. The second bonding layer may include a plurality of second bonding contacts. As shown in fig. 7C, a bonding layer 716 is formed over the interconnect layer 714. Bonding layer 716 may include a plurality of bonding contacts 718 surrounded by a dielectric. In some embodiments, the dielectric layer is deposited on the top surface of the interconnect layer 714 by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. The contact holes through the dielectric layer may then be first patterned by using a patterning process (e.g., photolithography and dry/wet etching of the dielectric material in the dielectric layer), forming bonding contacts 718 through the dielectric layer and in contact with the interconnects in the interconnect layer 714. The contact holes may be filled with a conductor (e.g., copper). In some embodiments, filling the contact hole includes depositing an adhesion (glue) layer, a barrier layer, and/or a seed layer prior to depositing the conductor.

The method 1100 proceeds to operation 1114 as shown in fig. 11, where the first wafer and the second wafer are bonded in a face-to-face manner such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contact of the first semiconductor structure contacts the second bonding contact of the second semiconductor structure at the bonding interface. The bonding may be a hybrid bonding. In some embodiments, the second semiconductor structure is over the first semiconductor structure after bonding. In some embodiments, the first semiconductor structure is over the second semiconductor structure after bonding.

As shown in fig. 9B, the first wafer 902 and the second wafer 904 are bonded in a face-to-face manner such that at least one of the first semiconductor structures 906 is bonded to at least one of the second semiconductor structures 908 at a bonding interface 909. Although the first wafer 902 is above the second wafer 904 after bonding, as shown in fig. 9B, it should be understood that the second wafer 904 may be above the first wafer 902 after bonding in some embodiments. Fig. 8A illustrates one example of the formation of bonded first and

second semiconductor structures

906 and 908.

As shown in fig. 8A, the silicon substrate 702 and the components formed thereon (e.g., the device layer 712 comprising the array of DRAM cells 710) are turned upside down. Bonding layer 716 facing downward bonds with bonding layer 616 facing upward, i.e., in a face-to-face manner, to form bonding interface 802 (shown in fig. 8B). In some embodiments, a treatment process, such as a plasma treatment, a wet treatment, and/or a thermal treatment, is applied to the bonding surface prior to bonding. Although not shown in fig. 8A, the silicon substrate 602 and components formed thereon (e.g., the device layer 606 including the programmable logic device 608, the array of SRAM cells 610, and the peripheral circuitry 612) may be turned upside down, and the downward-facing bonding layer 616 may be bonded, i.e., in a face-to-face manner, with the upward-facing bonding layer 716, thereby forming the bonding interface 802. After bonding, bonding contacts 718 in bonding layer 716 and bonding contacts 618 in bonding layer 616 are aligned and in contact with each other so that device layer 712 (e.g., an array of DRAM cells 710 therein) may be electrically connected to device layer 606 (e.g., programmable logic device 608, an array of SRAM cells 610 therein, and peripheral circuitry 612). It should be appreciated that in a bonded chip, the device layer 606 (e.g., the programmable logic device 608, the array of SRAM cells 610, and the peripheral circuitry 612 therein) may be above or below the device layer 712 (e.g., the array of DRAM cells 710 therein). However, after bonding, a bonding interface 802 may be formed between the device layer 606 (e.g., the programmable logic device 608, the array of SRAM cells 610, and the peripheral circuitry 612 therein) and the device layer 712 (e.g., the array of DRAM cells 710 therein), as shown in fig. 8B. It should be understood that although device layer 712 in fig. 8A does not include peripheral circuitry 711 (as shown in fig. 7C), in some embodiments, peripheral circuitry 711 may be included as part of device layer 712 in a bonded chip. It should also be understood that although the device layer 606 in fig. 8A includes the peripheral circuitry 612, in some embodiments, the peripheral circuitry 612 may not be included as part of the device layer 606 in the bonded chip.

The method 1100 proceeds to operation 1116 where the first wafer or the second wafer is thinned to form a semiconductor layer, as shown in fig. 11. In some embodiments, the first wafer of first semiconductor structures over the second wafer of second semiconductor structures is thinned after bonding to form a semiconductor layer. In some embodiments, the second wafer of second semiconductor structures over the first wafer of first semiconductor structures is thinned after bonding to form a semiconductor layer.

As shown in fig. 8B, the substrate at the top of the bonded chip (e.g., silicon substrate 702 shown in fig. 8A) is thinned so that the thinned top substrate can serve as a semiconductor layer 804, e.g., a single crystal silicon layer. The silicon substrate 702 may be thinned by processes including, but not limited to, the following: wafer grinding, dry etching, wet etching, CMP, any other suitable process, or any combination thereof. In one embodiment, the thickness of the thinned substrate may be between about 1 μm and about 20 μm, such as between 1 μm and 20 μm (e.g., 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 15 μm, 20 μm, any range bounded at the lower end by any of these values, or any range defined by any two of these values), for example, using a combination of etching and CMP processes. It should be appreciated that in some embodiments, the thickness of the thinned substrate may be further reduced to below 1 μm, for example, in the sub-micron range, by further applying additional etching processes. It should be understood that when the silicon substrate 602 is the substrate at the top of the bonded chip, another semiconductor layer may be formed by thinning the silicon substrate 602.

The method 1100 proceeds to operation 1118 where a pad out interconnect layer is formed over the semiconductor layer, as shown in fig. 11. As shown in fig. 8B, a pad extraction interconnect layer 806 is formed over the semiconductor layer 804 (thinned top substrate). The pad out interconnect layer 806 may include interconnects formed in one or more ILD layers, such as pad contacts 808. The pad contact 808 may comprise a conductive material including, but not limited to, W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The ILD layer may comprise a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. In some embodiments, after bonding and thinning, a contact 810 extending vertically through semiconductor layer 804 is formed, for example by wet/dry etching, followed by deposition of a conductive material. The contact 810 may contact an interconnect in the pad out interconnect layer 806.

The method 1100 proceeds to operation 1120, as shown in fig. 11, where the bonded first and second wafers are cut into a plurality of dies. At least one of the dies includes bonded first and second semiconductor structures. As shown in fig. 9C, the bonded first and second wafers 902 and 904 (shown in fig. 9B) are diced into a plurality of dies 912. At least one of the dies 912 includes bonded first and

second semiconductor structures

906 and 908. In some embodiments, each picture of the bonded first and

second wafers

902 and 904 is cut from the bonded first and

second wafers

902 and 904 along the scribe lines using wafer laser cutting and/or mechanical cutting techniques to become the respective die 912. Die 912 may include bonded first and

second semiconductor structures

906 and 908, e.g., a bonded structure as shown in fig. 8B.

Instead of a packaging scheme based on wafer level bonding before dicing as described above with respect to fig. 9A-9C and 11, fig. 10A-10C and 12 illustrate another packaging scheme based on die level bonding after dicing, according to some embodiments.

Operations

1102, 1104, and 1106 of method 1200 in fig. 12 are described above with respect to method 1100 in fig. 11 and are therefore not repeated. As shown in fig. 10A, a plurality of first semiconductor structures 1006 are formed on a first wafer 1002. The first wafer 1002 may include a plurality of panels separated by scribe lines. According to some embodiments, each picture of the first wafer 1002 includes one or more first semiconductor structures 1006. Fig. 6A and 6B illustrate one example of the formation of the first semiconductor structure 1006.

The method 1200 proceeds to operation 1202 as shown in fig. 12, where the first wafer is diced into a plurality of first dies such that at least one of the first dies includes the at least one of the first semiconductor structures. As shown in fig. 10B, the first wafer 1002 (shown in fig. 10A) is diced into a plurality of dies 1010 such that at least one die 1010 includes a first semiconductor structure 1006. In some embodiments, each panel of the first wafer 1002 is cut from the first wafer along the scribe lines using wafer laser cutting and/or mechanical cutting techniques to become a respective die 1010. Die 1010 may include a first semiconductor structure 1006, e.g., the structure shown in fig. 6B.

Operations

1108, 1110, and 1112 of method 1200 in fig. 12 are described above with respect to method 1100 in fig. 11 and, thus, are not repeated. As shown in fig. 10A, a plurality of second semiconductor structures 1008 are formed on the second wafer 1004. The second wafer 1004 may include a plurality of pictures separated by scribe lines. According to some embodiments, each picture of the second wafer 1004 includes one or more second semiconductor structures 1008. Fig. 7A-7C illustrate one example of the formation of a second semiconductor structure 1008.

The method 1200 proceeds to operation 1204, as shown in fig. 12, where the second wafer is diced into a plurality of second dies such that at least one of the second dies includes the at least one of the second semiconductor structures. As shown in fig. 10B, the second wafer 1004 (shown in fig. 10A) is diced into a plurality of dies 1012 such that at least one die 1012 includes the second semiconductor structure 1008. In some embodiments, each panel of the second wafer 1004 is cut from the second wafer 1004 along a scribe line using wafer laser dicing and/or mechanical dicing techniques to become a respective die 1012. The die 1012 may include a second semiconductor structure 1008, for example, as shown in fig. 7C.

The method 1200 proceeds to operation 1206, as shown in fig. 12, where the first die and the second die are bonded in a face-to-face manner such that the first semiconductor structure is bonded to the second semiconductor structure. The first bonding contact of the first semiconductor structure contacts the second bonding contact of the second semiconductor structure at the bonding interface. As shown in fig. 10C, the die 1010 including the first semiconductor structure 1006 and the die 1012 including the second semiconductor structure 1008 are bonded in a face-to-face manner such that the first semiconductor structure 1006 is bonded to the second semiconductor structure 1008 at a bonding interface 1014. Although the first semiconductor structure 1006 is over the second semiconductor structure 1008 after bonding as shown in fig. 10C, it should be understood that the second semiconductor structure 1008 may be over the first semiconductor structure 1006 after bonding in some embodiments. Fig. 8A illustrates one example of the formation of bonded first and

second semiconductor structures

1006 and 1008.

The method 1200 proceeds to operation 1208, as shown in fig. 12, where the first wafer or the second wafer is thinned to form a semiconductor layer. In some embodiments, the first wafer of first semiconductor structures over the second wafer of second semiconductor structures is thinned after bonding to form a semiconductor layer. In some embodiments, the second wafer of second semiconductor structures over the first wafer of first semiconductor structures is thinned after bonding to form a semiconductor layer.

As shown in fig. 8B, the substrate at the top of the bonded chip (e.g., silicon substrate 702 shown in fig. 8A) is thinned so that the thinned top substrate can serve as a semiconductor layer 804, e.g., a single crystal silicon layer. The silicon substrate 702 may be thinned by processes including, but not limited to, the following: wafer grinding, dry etching, wet etching, CMP, any other suitable process, or any combination thereof. In one example, the thickness of the thinned substrate can be between about 1 μm and about 20 μm, such as between 1 μm and 20 μm (e.g., 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 15 μm, 20 μm, any range bounded at the lower end by any of these values, or any range defined by any two of these values), for example, using a combination of etching and CMP processes. It should be appreciated that in some embodiments, the thickness of the thinned substrate may be further reduced to below 1 μm, for example in the sub-micron range, by further applying additional etching processes. It should be understood that when the silicon substrate 602 is the substrate at the top of the bonded chip, another semiconductor layer may be formed by thinning the silicon substrate 602.

The method 1200 proceeds to operation 1210 where a pad extraction interconnect layer is formed over the semiconductor layer, as shown in fig. 12. As shown in fig. 8B, a pad extraction interconnect layer 806 is formed over the semiconductor layer 804 (thinned top substrate). The pad out interconnect layer 806 may include interconnects formed in one or more ILD layers, such as pad contacts 808. The pad contact 808 may comprise a conductive material including, but not limited to, W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The ILD layer may comprise a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. In some embodiments, after bonding and thinning, a contact 810 extending vertically through semiconductor layer 804 is formed, for example by wet/dry etching, followed by deposition of a conductive material. The contact 810 may contact an interconnect in the pad out interconnect layer 806.

As described above, according to some embodiments, a semiconductor device having a programmable logic device manufactured according to method 1200 has undefined functions at the time of manufacture and needs to be programmed after manufacture to perform its desired functions. For example, fig. 13 is a flow diagram of an example method 1300 for programming a semiconductor device having a programmable logic device, in accordance with some embodiments. The semiconductor device depicted in fig. 13 may be any of the semiconductor devices described herein, including, for example, the

semiconductor devices

400, 401, 500, 501 depicted in fig. 4A, 4B, 5A, and 5B, respectively.

Referring to fig. 13, a method 1300 begins at operation 1302 where a function to be performed by a semiconductor device having a programmable logic device (e.g., an FPGA) is specified. For example, at this stage, the I/O interface, functional behavior, and/or different levels of modules and their internal interfaces, as well as the system clock, may be defined as a functional specification. Method 1300 proceeds to operation 1304, as shown in FIG. 13, where the functional specification, such as VHDL or Verilog, is provided in the form of HDL. For example, Register Transfer Level (RTL) descriptions in HDL may be created and simulated. Method 1300 proceeds to operation 1306, shown in FIG. 13, where the design specified in the HDL is synthesized. For example, a bit stream/netlist for a programmable logic device may be generated by a logic synthesis process that translates (e.g., at RTL) an abstract specification of the desired functional behavior to a logic block level design. The method 1300 proceeds to operation 1308, as shown in fig. 13, where logic blocks are placed and routed (interconnected) on the grid of programmable logic devices. For example, an automatic placement and routing program may be executed to generate pinouts based on the netlist, which will be used to connect to portions external to the programmable logic device.

Operations

1302, 1304, 1306 and 1308 may be performed by Electronic Design Automation (EDA) tools.

The method 1300 proceeds to operation 1310, as shown in fig. 13, where a semiconductor device having a programmable logic device is configured. For example, once the design and verification process is complete, the programmable logic device may be configured using a binary file generated, for example, using proprietary software of an FPGA vendor. In one example, the file in bitstream format is transferred/downloaded into an FPGA via an interface (e.g., a serial interface (JTAG)), or into a memory device (e.g., SRAM and/or DRAM) in a semiconductor device. It should be appreciated that in some embodiments, the method 1300 may proceed to operation 1312, as shown in fig. 13, where the semiconductor device with the programmable logic device may be partially reconfigured in a dynamic manner while the remaining programmable logic device design continues to function. For example, a subset of programmable logic blocks in an FPGA design in operation may be reconfigured by downloading portions of a bitstream into an FPGA in a semiconductor device. Partial reconfiguration may dynamically change functional modules within an active FPGA design.

According to one aspect of the present disclosure, in one example, a semiconductor device includes a first semiconductor structure including a programmable logic device, an array of SRAM cells, and a first bonding layer including a plurality of first bonding contacts. The semiconductor device also includes a second semiconductor structure including an array of DRAM cells and a second bonding layer including a plurality of second bonding contacts. The semiconductor device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contact is in contact with the second bonding contact at the bonding interface.

In some embodiments, the first semiconductor structure comprises: a substrate; the programmable logic device on the substrate; an array of the SRAM cells on the substrate and external to the programmable logic device; and the first bonding layer over the programmable logic device and the array of SRAM cells.

In some embodiments, the second semiconductor structure comprises: the second bonding layer over the first bonding layer; an array of the DRAM cells over the second bonding layer; and a semiconductor layer over and in contact with the array of DRAM cells.

In some embodiments, the semiconductor device further comprises a pad extraction interconnect layer over the semiconductor layer. In some embodiments, the semiconductor layer comprises single crystal silicon.

In some embodiments, the second semiconductor structure comprises: a substrate; an array of the DRAM cells on the substrate; and the second bonding layer over the array of DRAM cells.

In some embodiments, the first semiconductor structure comprises: the first bonding layer over the second bonding layer; the programmable logic device over the first bonding layer; an array of the SRAM cells over the first bonding layer and external to the programmable logic device; and a semiconductor layer over and in contact with the array of programmable logic devices and the SRAM cells.

In some embodiments, the first semiconductor structure further includes peripheral circuitry of the array of DRAM cells. In some embodiments, the second semiconductor structure further includes peripheral circuitry of the array of DRAM cells.

In some embodiments, the first semiconductor structure includes a first interconnect layer vertically positioned between the first bonding layer and the programmable logic device, and the second semiconductor structure includes a second interconnect layer vertically positioned between the second bonding layer and the array of DRAM cells.

In some embodiments, the programmable logic device is electrically connected to the array of DRAM cells through the first and second interconnect layers and the first and second bonding contacts.

In some embodiments, the array of SRAM cells is electrically connected to the array of DRAM cells through the first and second interconnect layers and the first and second bonding contacts.

In some embodiments, the programmable logic device includes a plurality of programmable logic blocks.

In some embodiments, each DRAM cell includes a transistor and a capacitor.

In accordance with another aspect of the present disclosure, a method for forming a semiconductor device is disclosed. A plurality of first semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures comprises: the programmable logic device includes a programmable logic device, an array of SRAM cells, and a first bonding layer including a plurality of first bonding contacts. A plurality of second semiconductor structures is formed on the second wafer. At least one of the second semiconductor structures comprises: an array of DRAM cells, and a second bonding layer comprising a plurality of second bonding contacts. Bonding the first wafer and the second wafer in a face-to-face manner such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contact of the first semiconductor structure is in contact with the second bonding contact of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into a plurality of dies. At least one of the dies includes a bonded first semiconductor structure and a second semiconductor structure.

In some embodiments, to form the plurality of first semiconductor structures, an array of the programmable logic devices and the SRAM cells is formed on the first wafer, a first interconnect layer is formed over the array of the programmable logic devices and the SRAM cells, and the first bonding layer is formed over the first interconnect layer. In some embodiments, to form the array of programmable logic devices and the SRAM cells, a plurality of transistors are formed on the first wafer.

In some embodiments, to form the plurality of first semiconductor structures, peripheral circuitry of the array of DRAM cells is formed on the first die.

In some embodiments, to form the plurality of second semiconductor structures, the array of DRAM cells is formed on the second wafer, a second interconnect layer is formed over the array of DRAM cells, and the second bonding layer is formed over the second interconnect layer.

In some embodiments, to form the array of DRAM cells, a plurality of transistors are formed on the second wafer, and a plurality of capacitors are formed over at least some of the transistors in contact with the at least some of the transistors.

In some embodiments, to form the plurality of second semiconductor structures, peripheral circuitry of the array of DRAM cells is formed on the second wafer.

In some embodiments, the second semiconductor structure is over the first semiconductor structure after the bonding. In some embodiments, after the bonding and before the dicing, the second wafer is thinned to form a semiconductor layer, and a pad-out interconnect layer is formed over the semiconductor layer.

In some embodiments, the first semiconductor structure is over the second semiconductor structure after the bonding. In some embodiments, after the bonding and before the dicing, the first wafer is thinned to form a semiconductor layer, and a pad-out interconnect layer is formed over the semiconductor layer.

In some embodiments, the bonding comprises hybrid bonding.

According to yet another aspect of the present disclosure, a method for forming a semiconductor device is disclosed. A plurality of first semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures comprises: the programmable logic device includes a programmable logic device, an array of SRAM cells, and a first bonding layer including a plurality of first bonding contacts. Dicing the first wafer into a plurality of first dies such that at least one of the first dies includes the at least one of the first semiconductor structures. A plurality of second semiconductor structures is formed on the second wafer. At least one of the second semiconductor structures comprises: an array of DRAM cells, and a second bonding layer comprising a plurality of second bonding contacts. Dicing the second wafer into a plurality of second dies such that at least one of the second dies includes the at least one of the second semiconductor structures. Bonding the first die and the second die in a face-to-face manner such that the first semiconductor structure is bonded to the second semiconductor structure. The first bonding contact of the first semiconductor structure is in contact with the second bonding contact of the second semiconductor structure at a bonding interface.

In some embodiments, the second semiconductor structure is over the first semiconductor structure after the bonding. In some embodiments, the second wafer is thinned after the bonding to form a semiconductor layer, and a pad-out interconnect layer is formed over the semiconductor layer.

In some embodiments, the first semiconductor structure is over the second semiconductor structure after the bonding. In some embodiments, thinning the first wafer after the bonding to form a semiconductor layer, and forming a pad-out interconnect layer over the semiconductor layer.

In some embodiments, the bonding comprises hybrid bonding.

The foregoing description of the specific embodiments will reveal the general nature of the disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments without undue experimentation, without departing from the general concept of the present disclosure. Therefore, based on the teachings and guidance presented herein, these adaptations and modifications are intended to fall within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. Boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

The summary and abstract sections may set forth one or more, but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and are therefore not intended to limit the disclosure and the appended claims in any way.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims appended hereto and their equivalents.

Claims

1. A semiconductor device, comprising:

a first semiconductor structure comprising: a programmable logic device, an array of Static Random Access Memory (SRAM) cells, and a first bonding layer comprising a plurality of first bonding contacts;

a second semiconductor structure comprising: an array of Dynamic Random Access Memory (DRAM) cells, and a second bonding layer comprising a plurality of second bonding contacts; and

a bonding interface between the first bonding layer and the second bonding layer, wherein the first bonding contact is in contact with the second bonding contact at the bonding interface.

2. The semiconductor device of claim 1, wherein the first semiconductor structure comprises:

a substrate;

the programmable logic device on the substrate;

an array of the SRAM cells on the substrate and external to the programmable logic device; and

the first bonding layer over the programmable logic device and the array of SRAM cells.

3. The semiconductor device of claim 2, wherein the second semiconductor structure comprises:

the second bonding layer over the first bonding layer;

an array of the DRAM cells over the second bonding layer; and

a semiconductor layer over and in contact with the array of DRAM cells.

4. The semiconductor device of claim 3, further comprising a pad extraction interconnect layer over the semiconductor layer.

5. The semiconductor device of claim 3 or 4, wherein the semiconductor layer comprises single crystal silicon.

6. The semiconductor device of claim 1, wherein the second semiconductor structure comprises:

a substrate;

an array of the DRAM cells on the substrate; and

the second bonding layer over the array of DRAM cells.

7. The semiconductor device of claim 6, wherein the first semiconductor structure comprises:

the first bonding layer over the second bonding layer;

the programmable logic device over the first bonding layer;

an array of the SRAM cells over the first bonding layer and external to the programmable logic device; and

a semiconductor layer over and in contact with the array of programmable logic devices and the SRAM cells.

8. The semiconductor device of claim 7, further comprising a pad extraction interconnect layer over the semiconductor layer.

9. The semiconductor device of claim 7 or 8, wherein the semiconductor layer comprises single crystal silicon.

10. The semiconductor device of any of claims 1-9, wherein the first semiconductor structure further comprises peripheral circuitry of the array of DRAM cells.

11. The semiconductor device of any of claims 1-9, wherein the second semiconductor structure further comprises peripheral circuitry of the array of DRAM cells.

12. The semiconductor device of any of claims 1-11, wherein the first semiconductor structure comprises a first interconnect layer vertically between the first bonding layer and the programmable logic device, and the second semiconductor structure comprises a second interconnect layer vertically between the second bonding layer and the array of DRAM cells.

13. The semiconductor device of claim 12, wherein the programmable logic device is electrically connected to the array of DRAM cells through the first and second interconnect layers and the first and second bonding contacts.

14. The semiconductor device of claim 12 or 13, wherein the array of SRAM cells is electrically connected to the array of DRAM cells through the first and second interconnect layers and the first and second bonding contacts.

15. The semiconductor device according to any one of claims 1 to 14, wherein the programmable logic device includes a plurality of programmable logic blocks.

16. The semiconductor device of any one of claims 1 to 15, wherein each DRAM cell comprises a transistor and a capacitor.

17. A method for forming a semiconductor device, comprising:

forming a plurality of first semiconductor structures on a first wafer, wherein at least one of the first semiconductor structures comprises: a programmable logic device, an array of Static Random Access Memory (SRAM) cells, and a first bonding layer comprising a plurality of first bonding contacts;

forming a plurality of second semiconductor structures on a second wafer, wherein at least one of the second semiconductor structures comprises: an array of Dynamic Random Access Memory (DRAM) cells, and a second bonding layer comprising a plurality of second bonding contacts;

bonding the first and second wafers in a face-to-face manner such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures, wherein the first bonding contact of the first semiconductor structure is in contact with the second bonding contact of the second semiconductor structure at a bonding interface; and

dicing the bonded first and second wafers into a plurality of dies, wherein at least one of the dies includes the bonded first and second semiconductor structures.

18. The method of claim 17, wherein forming the plurality of first semiconductor structures comprises:

forming an array of the programmable logic devices and the SRAM cells on the first wafer;

forming a first interconnect layer over the programmable logic device and the array of SRAM cells; and

forming the first bonding layer over the first interconnect layer.

19. The method of claim 18, wherein forming the array of programmable logic devices and SRAM cells comprises forming a plurality of transistors on the first wafer.

20. The method of claim 18 or 19, wherein forming the plurality of first semiconductor structures further comprises forming peripheral circuitry of the array of DRAM cells on the first die.

21. The method of any of claims 17 to 20, wherein forming the plurality of second semiconductor structures comprises:

forming an array of the DRAM cells on the second wafer;

forming a second interconnect layer over the array of DRAM cells; and

forming the second bonding layer over the second interconnect layer.

22. The method of claim 21, wherein forming the array of DRAM cells comprises:

forming a plurality of transistors on the second wafer; and

a plurality of capacitors is formed over at least some of the transistors in contact with the at least some of the transistors.

23. The method of claim 21 or 22, wherein forming the plurality of second semiconductor structures further comprises forming peripheral circuitry of the array of DRAM cells on the second wafer.

24. The method of any of claims 17-23, wherein the second semiconductor structure is over the first semiconductor structure after the bonding.

25. The method of claim 24, further comprising, after the bonding and before the cutting:

thinning the second wafer to form a semiconductor layer; and

a pad extraction interconnect layer is formed over the semiconductor layer.

26. The method of any of claims 17-23, wherein the first semiconductor structure is over the second semiconductor structure after the bonding.

27. The method of claim 26, further comprising, after the bonding and before the cutting:

thinning the first wafer to form a semiconductor layer; and

a pad extraction interconnect layer is formed over the semiconductor layer.

28. The method of any one of claims 17 to 27, wherein the bonding comprises hybrid bonding.

29. A method for forming a semiconductor device, comprising:

dicing the first wafer into a plurality of first dies such that at least one of the first dies includes the at least one of the first semiconductor structures;

dicing the second wafer into a plurality of second dies such that at least one of the second dies includes the at least one of the second semiconductor structures; and

bonding the first die and the second die in a face-to-face manner such that the first semiconductor structure is bonded to the second semiconductor structure, wherein the first bonding contact of the first semiconductor structure is in contact with the second bonding contact of the second semiconductor structure at a bonding interface.

30. The method of claim 29, wherein forming the plurality of first semiconductor structures comprises:

forming the first bonding layer over the first interconnect layer.

31. The method of claim 30, wherein forming the array of programmable logic devices and SRAM cells comprises forming a plurality of transistors on the first wafer.

32. The method of claim 30 or 31, wherein forming the plurality of first semiconductor structures further comprises forming peripheral circuitry of the array of DRAM cells on the first die.

33. The method of any of claims 29 to 32, wherein forming the plurality of second semiconductor structures comprises:

forming an array of the DRAM cells on the second wafer;

forming a second interconnect layer over the array of DRAM cells; and

forming the second bonding layer over the second interconnect layer.

34. The method of claim 33, wherein forming the array of DRAM cells comprises:

forming a plurality of transistors on the second wafer; and

35. The method of claim 33 or 34, wherein forming the plurality of second semiconductor structures further comprises forming peripheral circuitry of the array of DRAM cells on the second wafer.

36. The method of any of claims 29-35, wherein the second semiconductor structure is over the first semiconductor structure after the bonding.

37. The method of claim 36, further comprising:

thinning the second wafer after the bonding to form a semiconductor layer; and

a pad extraction interconnect layer is formed over the semiconductor layer.

38. The method of any of claims 29-35, wherein the first semiconductor structure is over the second semiconductor structure after the bonding.

39. The method of claim 38, further comprising:

thinning the first wafer after the bonding to form a semiconductor layer; and

a pad extraction interconnect layer is formed over the semiconductor layer.

40. The method of any one of claims 29 to 39, wherein the bonding comprises hybrid bonding.