TW202315050A - Method of manufacturing a 3d semiconductor wafer - Google Patents

Method of manufacturing a 3d semiconductor wafer

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TW202315050A
TW202315050A TW111147651A TW111147651A TW202315050A TW 202315050 A TW202315050 A TW 202315050A TW 111147651 A TW111147651 A TW 111147651A TW 111147651 A TW111147651 A TW 111147651A TW 202315050 A TW202315050 A TW 202315050A
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layer
wafer
transistors
transistor
oxide
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TW111147651A
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Chinese (zh)
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凡 歐貝克
布萊恩 克隆奇斯特
伊斯瑞爾 濱葛拉斯
傑 德榮
狄帕克 瑟卡
齊夫 武曼
Original Assignee
凡 歐貝克
布萊恩 克隆奇斯特
伊斯瑞爾 濱葛拉斯
傑 德榮
狄帕克 瑟卡
齊夫 武曼
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Priority claimed from US12/706,520 external-priority patent/US20110199116A1/en
Priority claimed from US12/792,673 external-priority patent/US7964916B2/en
Priority claimed from US12/797,493 external-priority patent/US8115511B2/en
Priority claimed from US12/847,911 external-priority patent/US7960242B2/en
Priority claimed from US12/849,272 external-priority patent/US7986042B2/en
Priority claimed from US12/859,665 external-priority patent/US8405420B2/en
Priority claimed from US12/900,379 external-priority patent/US8395191B2/en
Application filed by 凡 歐貝克, 布萊恩 克隆奇斯特, 伊斯瑞爾 濱葛拉斯, 傑 德榮, 狄帕克 瑟卡, 齊夫 武曼 filed Critical 凡 歐貝克
Publication of TW202315050A publication Critical patent/TW202315050A/en

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  • Design And Manufacture Of Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Slot Machines And Peripheral Devices (AREA)
  • Noodles (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

Description

製造3D半導體晶圓的方法 Method for manufacturing 3D semiconductor wafers 有關專利之交叉引用 Cross references to patents

本專利發明相對於同時申請之美國專利12/577,532, 12/706,520, 12/792,673, 12/797,493, 12/847,911, 12/849,272, 12/859,665享有優先權,其內容以引用的方式納入本文中。 This patented invention enjoys priority over concurrently filed U.S. Patents 12/577,532, 12/706,520, 12/792,673, 12/797,493, 12/847,911, 12/849,272, 12/859,665, the contents of which are incorporated herein by reference .

本項發明涉及積體電路(IC)組件和製造工藝的一般領域,特別是多層/或三維積體電路(3D IC)組件及製造工藝的一般領域。 The invention relates to the general field of integrated circuit (IC) components and manufacturing processes, in particular to the general field of multilayer and/or three-dimensional integrated circuit (3D IC) components and manufacturing processes.

半導體製造隨時間以指數級速度增加組件密度,但是這種改良是有代價的。就是,每個新工藝技術之掩膜組成本也會以指數級增加。在20年前,一個掩膜組之成本小於2萬美元,今天之最新技術掩膜組則通常需要100萬美元。 Semiconductor manufacturing has increased component density exponentially over time, but this improvement has come at a price. That is, the cost of mask sets for each new process technology will also increase exponentially. Twenty years ago, a mask set cost less than $20,000; today's state-of-the-art mask sets typically cost $1 million.

這些變化主要給定制產品帶來了更大之挑戰,定制組件所針對之更小產能和更加單一之市場,將承擔不斷增加之產品研發成本,甚至於舉步維艱。 These changes mainly bring greater challenges to customized products. The smaller production capacity and more single market for customized components will bear the ever-increasing cost of product development, and even struggle.

定制積體電路可以分為2個細分市場:第一個是產品之所有層均為定制之組件。第二個是產品之部分層是通用層,可以應用於不同之定制產品。第二種產品中,有著名之閘陣列,即所有之層均使用通用層直至接觸層,由接觸層完成矽組件與金屬導體之連接,還有就是可編程閘陣列(FPGA),所有層均為通用層。上述組件之通用層幾乎全部採用重複排列之結構,稱為主片,為一個陣列之形式。 Custom ICs can be divided into 2 market segments: The first is components where all layers of the product are custom. The second is that the partial layer of the product is a general layer, which can be applied to different customized products. In the second type of product, there is the famous gate array, that is, all layers use the common layer to the contact layer, and the contact layer completes the connection between silicon components and metal conductors, and there is a programmable gate array (FPGA), all layers are for the general layer. The common layers of the above-mentioned components are almost all arranged in a repeating structure, called the main chip, which is in the form of an array.

邏輯陣列技術即基於通用結構,可以在定制階段為特定設計進行定制。一個FPGA之定制通常使用電訊號編程完成。對於閘陣列,現代之結構通常稱為結構化專用積體電路(或,結構化ASIC),定制至少需要一個定制層,可透過直接寫入電子束或一個定制掩模完成。由於設計之邏輯器和記憶體以及I/O模組類型之數量可能大不相同,邏輯陣列之供應商通常生產產品系列,每個產品有不同數量之主片,其中包含一系列之邏輯晶片、不同大小之儲存晶片和I/O晶片配置,供客戶選擇。但是,最小主片組之確定一直都是挑戰,合適之主片組能夠很好之適應大規模之設計方案,而如果每個產品均需要專門之掩膜組,則會導致成本飆升。 Logic array technology is based on a common structure that can be customized for a specific design during the customization phase. Customization of an FPGA is usually done using electrical programming. For gate arrays, modern structures are often referred to as structured application-specific integrated circuits (or, structured ASICs), and customization requires at least one custom layer, which can be done by direct writing with electron beams or a custom mask. Because the number of logic and memory and I/O module types in the design may vary greatly, suppliers of logic arrays usually produce product families, each product has a different number of main chips, which include a series of logic chips, Different sizes of storage chips and I/O chip configurations are available for customers to choose. However, determining the minimum master set has always been a challenge. A suitable master set can well accommodate large-scale designs, and if each product requires a dedicated mask set, the cost will skyrocket.

美國專利4733288,於1977年3月授權給Sato,公開了 一種能夠製造閘陣列LSI晶片之方法,可進行成對晶片切割,每個晶片依照電路設計具有所需尺寸和數量之門電路。本專利之參考文獻中引用了Sato,該思路能夠為不同尺寸之定制組件提供幾種利用通用層之方法。 US Patent 4733288, authorized to Sato in March 1977, discloses A method capable of manufacturing gate array LSI wafers, capable of dicing paired wafers, each wafer having required size and number of gate circuits according to circuit design. Sato is cited in the references of this patent, and this idea can provide several ways to utilize the common layer for custom components of different sizes.

陣列結構符合不同尺寸之要求。提供不同尺寸陣列結構之難點在於需要提供I/O晶片及相應的焊盤,將組件與封裝晶片組連接起來。為了突破這一限制,Sato建議了一種方法,I/O晶片可以使用通用邏輯門之電晶體來構建。Anderson也建議了一種類似之方法,在美國專利5217916中,該專利於1993年7月8日授權給Anderson等人,公開了一種使用電晶體門晶片突破預設界限自由設定閘陣列之方法,相同類型之晶片用作邏輯晶片,提供輸入和輸出功能。相應的,輸入和輸出功能也可以佈置在邏輯陣列周圍,邏輯陣列之大小依照用途決定。該方法之嚴重限制在於I/O晶片必須使用邏輯晶片相同之電晶體,因此I/O晶片之工作電壓也無法升高。 The array structure meets the requirements of different sizes. The difficulty in providing array structures of different sizes lies in the need to provide I/O chips and corresponding pads to connect components and package chips. To overcome this limitation, Sato suggested a method in which I/O chips could be built using transistors for general-purpose logic gates. Anderson also suggested a similar method. In U.S. Patent 5,217,916, this patent was authorized to Anderson et al. on July 8, 1993, disclosing a method of using transistor gate wafers to break through the preset limit and freely set the gate array. Type chips are used as logic chips, providing input and output functions. Correspondingly, the input and output functions can also be arranged around the logic array, and the size of the logic array is determined according to the application. The serious limitation of this method is that the I/O chip must use the same transistor as the logic chip, so the operating voltage of the I/O chip cannot be increased.

授權給Or-Bach等人之美國專利7105871,2006年9月12日,公開了一種半導體裝置,包括無界限之邏輯陣列和局部I/O晶片。邏輯陣列可包含一個重複之核心,以及至少一個局部I/O,該局部I/O可以作為可配置之I/O。 US Patent 7,105,871 issued September 12, 2006 to Or-Bach et al. discloses a semiconductor device including an unbounded logic array and local I/O chips. The logic array may contain a duplicated core, and at least one local I/O, which may serve as a configurable I/O.

過去,設計一個可以配置之I/O晶片來滿足不同客戶需求是很平常之事情。對更高資料傳輸率I/O之增長需求推動了專用串列I/O電路之研發,稱為SerDes(串列器/串並轉換器)收發晶片。這些電路均十分複雜,比常規I/O 晶片需要更大面積之矽片。因此,不同之配置透過不同數量之邏輯電路、不同數量和類型之儲存晶片、以及不同數量和類型之I/O晶片來實現。這就意味著即便是用當前技術之無界限邏輯陣列,依然需要使用多個昂貴之掩膜組。 In the past, it was common to design a configurable I/O chip to meet different customer needs. The growing demand for higher data rate I/O has driven the development of dedicated serial I/O circuits known as SerDes (Serializer/Serial to Parallel Converter) transceiver chips. These circuits are very complex, compared with conventional I/O Chips require larger silicon wafers. Thus, different configurations are implemented with different numbers of logic circuits, different numbers and types of memory chips, and different numbers and types of I/O chips. This means that even with current state-of-the-art unbounded logic arrays, multiple expensive mask sets still need to be used.

今天,市售最常見之FPGA晶片均基於靜態隨機記憶體(SRAM),作為編程組件。浮柵快閃記憶體可編程組件也有一些應用。也有少量FPGA使用抗熔儲存作為可編程組件。第一代抗熔儲存FPGA使用直接內嵌在矽基板上之抗熔儲存。第二代則將抗熔儲存移至金屬層,稱為金屬-金屬抗熔儲存。抗熔儲存之功能就像可編程之過孔。但是,與過孔使用相同金屬製成並用於層間連接不同,抗熔儲存通常使用非晶矽和一些介面層。雖然,理論上抗熔儲存能夠支援比SRAM更高之密度,SRAM FPGA成為了今天市場之主流。實際上,抗熔儲存FPGA組件似乎已經沒有人繼續研發。抗熔儲存之嚴重問題之一就是缺乏可重複編程之功能。另外一個缺陷是抗熔儲存所需之專門矽生產工藝,該工藝需要額外之研發成本,還會導致相對於基準IC技術定標之時間滯後。 Today, the most common FPGA chips commercially available are based on static random access memory (SRAM) as the programming component. Floating-gate flash memory programmable devices also have some applications. There are also a small number of FPGAs that use antifuse memory as a programmable component. The first generation of antifuse FPGAs used antifuse directly embedded on the silicon substrate. The second generation moves the antifuse storage to the metal layer, which is called metal-metal antifuse storage. Antifuse functions like programmable vias. However, unlike vias that are made of the same metal and used to connect layers, antifuse typically uses amorphous silicon and some interfacial layers. Although, theoretically, antifuse memory can support a higher density than SRAM, SRAM FPGA has become the mainstream of the market today. In fact, antifuse storage FPGA components seem to have no one to continue to develop. One of the serious problems of antifuse memory is the lack of reprogrammable function. Another drawback is the specialized silicon production process required for antifuse storage, which requires additional R&D costs and causes a time lag relative to benchmark IC technology scaling.

而常見FPGA技術之缺陷則在於他們相對低效之矽片利用面積。雖然終端用戶僅僅關注他們之組件能否實現他們想要之功能,FPGA之功能編程特點要求佔用矽片之大部分面積,用於編程和程式校驗功能。 The drawback of common FPGA technology is their relatively inefficient use of silicon area. Although end users only care about whether their components can achieve the functions they want, the functional programming characteristics of FPGAs require that most of the silicon area be occupied for programming and program verification functions.

本項發明之某些案例將尋求突破目前技術之限制,透過在抗熔儲存可編程互聯電路之上或之下使用特殊類型之 電晶體來實現附加之功能,使得對矽片面積之利用更為有效。 Some examples of this invention will seek to overcome the limitations of current technology by using special types of Transistors are used to implement additional functions, making the use of silicon chip area more effective.

其中一種類型之電晶體就是目前技術中常見之薄膜電晶體,也稱為TFT。薄膜電晶體提出和使用已經經歷了30多年。其中一項更為熟知之應用是在螢幕上,將TFT佈置在玻璃表面,作為螢幕螢屏。另外一種電晶體也可以加工到抗熔儲存可編程互聯電路上,稱為真空場效應電晶體(FET),由30年前之美國專利4721885提出。 One type of transistor is the thin film transistor, also known as TFT, which is common in the art today. Thin film transistors have been proposed and used for more than 30 years. One of the more well-known applications is in screens, where TFTs are arranged on glass surfaces as screen screens. Another kind of transistor can also be processed on the antifuse memory programmable interconnection circuit, which is called vacuum field effect transistor (FET), which was proposed by US Patent 4721885 30 years ago.

其餘可用之技術還包括絕緣矽(SOI)技術。在美國專利6355501和6832826中,均授權給IBM,提出了一個多層3維互補金屬氧化物半導體(CMOS)積體電路。該項專利提出在SOI晶圓上再黏合一薄層SOI晶圓,在一個IC上形成另外一個IC,然後透過穿矽過孔或穿層過孔(TLV)將兩個電路連接起來。基板製造商Soitec SA,法國貝赫南(Bernin)現在已經能夠提供這項技術,在一個底層晶圓上堆疊一個經過加工之薄層晶圓。 Other available technologies include silicon-on-insulator (SOI) technology. In US patents 6,355,501 and 6,832,826, both granted to IBM, a multilayer 3-dimensional complementary metal oxide semiconductor (CMOS) integrated circuit is proposed. The patent proposes bonding a thin SOI wafer on top of the SOI wafer, forming another IC on one IC, and then connecting the two circuits through silicon vias or through-layer vias (TLV). Substrate manufacturer Soitec SA, Bernin, France, is now able to offer the technology, which stacks a processed thin-layer wafer on a bottom wafer.

在IC之一個絕緣層上集成一個表層電晶體並不常見,因為現有工藝會導致表層電晶體之品質和密度比底層(基板)層要差。基板可以使用單晶矽,是製造高密度和高品質電晶體之理想辦法,也是優選方案。也有專利發明中建議過使用電晶體來構建儲存晶片,比如美國專利6815781、7446563;還有部分基於SRAM之FPGA,如美國專利6515511和7265421。 Integrating a surface transistor on an insulating layer of an IC is uncommon because existing processes result in lower quality and density of the surface transistor than the bottom (substrate) layer. Monocrystalline silicon can be used as the substrate, which is an ideal and preferred solution for manufacturing high-density and high-quality transistors. There are also patent inventions that suggest the use of transistors to build storage chips, such as US patents 6815781 and 7446563; and some FPGAs based on SRAM, such as US patents 6515511 and 7265421.

本專利之案例旨在透過利用表層電晶體之優勢來獲得 更高密度之抗熔儲存可編程邏輯晶片。這樣做之另外一個優勢就是透過使用定制掩模來代替抗熔儲存功能,可以獲得進一步降低大批量生產成本之方法,從而最終無需使用表層抗熔儲存邏輯晶片。 The case of this patent aims to obtain Higher density antifuse programmable logic chips. An additional advantage of this is that by using a custom mask to replace the antifuse function, a method can be obtained to further reduce the cost of high-volume production, thereby ultimately eliminating the need for surface antifuse logic chips.

另外,本發明中之部分案例還為多層3D IC技術提供了新之替代方案。隨著片裝互聯電路成為組件擴展性能和功率提升之限制因素,3D IC也許能夠稱為未來IC晶片之一個重要技術。目前,3D IC僅能夠使用之封裝技術就是矽片直穿過孔(TSV)。TSV之問題在於過孔相對較大(每個之面積為幾微米)同時可能導致垂直連接大幅受限。本發明專利或許能夠為3D IC提供多個不同之替代方案,在一定程度上改良垂直連接。 In addition, some cases in the present invention also provide new alternatives for multi-layer 3D IC technology. As on-chip interconnect circuits become the limiting factor for component scalability and power enhancement, 3D ICs may be an important technology for future IC chips. Currently, the only packaging technology that can be used for 3D ICs is through silicon vias (TSV). The problem with TSVs is that the vias are relatively large (a few microns in area each) and can result in significantly limited vertical connectivity. The patent of this invention may be able to provide several different alternatives for 3D IC and improve the vertical connection to a certain extent.

構建未來之3D IC將需要新之結構和新之思維模式。尤其是,解決及其複雜3D系統之產能和穩定性問題,目前之深度次微米級一代制程面臨之最大挑戰就是構建複雜ASIC之產能和穩定性難題。 Building the 3D ICs of the future will require new structures and new ways of thinking. In particular, to solve the production capacity and stability problems of extremely complex 3D systems, the biggest challenge facing the current deep sub-micron generation process is the production capacity and stability problems of building complex ASICs.

幸運的是,目前之測試技術很可能被證明適用於3D IC製造,儘管實施之方法可能大不相同。圖-116給出了2D IC ASIC 11600中使用之現有之組掃描架構。ASIC功能出現在邏輯雲11620、11622、11624和11626中,由連續之晶片隔開,如11612、11614和11616中出現之成雙觸發器之形式。ASIC 11600也有輸入焊盤11630和輸出焊盤11640。觸發器通常配有電路,使得它們在測試模式下能夠用作移位寄存器。圖116中,觸發器構成一個掃描寄存器鏈,使 得成雙之觸發器11612、11614、和11616與掃描測試控制器11610結合形成一個序列。圖116給出了一個掃描鏈,但是在實際設計中包含有成百萬個觸發器和很多個子鏈。 Fortunately, current testing techniques are likely to prove suitable for 3D IC manufacturing, although the method of implementation may be very different. Figure-116 shows the existing group scan architecture used in 2D IC ASIC 11600. ASIC functions appear in logic clouds 11620, 11622, 11624, and 11626, separated by contiguous chips, in the form of dual flip-flops as in 11612, 11614, and 11616. ASIC 11600 also has input pads 11630 and output pads 11640 . Flip-flops are usually equipped with circuitry that enables them to function as shift registers in test mode. In Figure 116, flip-flops form a chain of scan registers such that Duplicated flip-flops 11612, 11614, and 11616 combine with scan test controller 11610 to form a sequence. Figure 116 shows a scan chain, but the actual design contains millions of flip-flops and many sub-chains.

圖116之測試結構中,測試分區在測試模式下移位至掃描鏈中。然後,在一個或多個時鐘週期中這一部分被置於運行模式,之後,觸發器之內容被移出,並與預期結果進行比較。儘管測試分區之數目在實際設計中可能非常大,並且有可能使用外部測試器,但是這樣就有可能為分離錯誤和診斷問題提供一個絕佳之方式。 In the test structure of FIG. 116, the test partitions are shifted into scan chains in test mode. The part is then placed in run mode for one or more clock cycles, after which the contents of the flip-flops are shifted out and compared with the expected result. Although the number of test partitions can be quite large in real designs, and it is possible to use an external tester, this may provide an excellent way to isolate errors and diagnose problems.

圖-117給出了以ASIC 11700為例顯示之現有技術之邊界掃描架構。該部分之功能在邏輯功能塊11710中顯示。該部分還有各種輸入/輸出晶片11720,每個晶片包含一個黏接焊盤11722、一個出入緩衝器11724、一個3態輸出緩衝器11726。邊界掃描寄存器鏈11732和11734都與掃描測試控制塊11730相連成鏈狀。這樣之架構與圖116中之組掃描架構有類似之工作模式。測試分區移入,該部分開始計時,結果移出後與預期結果進行比較。通常,組掃描和邊界掃描在同一個ASIC中是一起使用的,這樣就形成完整之測試範圍。 Figure-117 shows the Boundary Scan architecture of the prior art shown with ASIC 11700 as an example. The function of this part is shown in logic function block 11710. Also in this section are various I/O dies 11720, each die containing a bond pad 11722, an in-out buffer 11724, a 3-state output buffer 11726. Boundary scan register chains 11732 and 11734 are connected to scan test control block 11730 in a chain. Such an architecture has a similar working mode to the group scan architecture in FIG. 116 . The test partition is moved in, the part is started to be timed, and the results are compared with the expected results after they are moved out. Usually, group scan and boundary scan are used together in the same ASIC, thus forming a complete test range.

圖118給出了已有之內置自我測試(BIST)架構,用於測試邏輯塊11800,該塊中包含一個核心塊功能11810(即被測試白堊粉)、輸入11812、輸出11814、一個BIST控制器11820、一個輸入線性回饋移位寄存器(LFSR)11822、一個輸出循環冗餘校驗(CRC)電路11824。在 BIST控制器11820之控制下,LFSR11822和CRC11824被初始化(即,賦予已知之初始值),塊11800開始以預設次數計時,同時LFSR11822將偽隨機測試分區發送給功能塊11810之輸入,並且由CRC 11824對功能塊11810之輸出進行檢測。在預設之時鐘週期之後,CRC 11824之內容被與預期之值(或簽名)進行比較。如果簽名相符,功能塊11800透過測試,並將被認為工作正常。這種測試對於快速之“通過”或“不通過”測試是有用的,因為測試對於被測試之功能塊是獨立的,並不要求對大量之測試分區進行分類或使用外部測試器。BIST、組掃描和邊界掃描技術通常會以互補之方式結合起來,在同一個ASIC上使用。關於LSFR和CRC之詳細理論探討可以參見《數位系統測試和可測性設計》之432-447頁。該書作者為Abramovici,Breuer & Friedman,電腦科學出版社(Computer Science Press),1990年。 Figure 118 shows the existing built-in self-test (BIST) architecture for testing logic block 11800, which includes a core block function 11810 (i.e. the chalk to be tested), input 11812, output 11814, a BIST controller 11820, an input linear feedback shift register (LFSR) 11822, an output cyclic redundancy check (CRC) circuit 11824. exist Under the control of BIST controller 11820, LFSR11822 and CRC11824 are initialized (i.e., given a known initial value), block 11800 starts timing with a preset number of times, and LFSR11822 sends a pseudo-random test partition to the input of function block 11810, and is determined by CRC 11824 checks the output of function block 11810. After a preset clock cycle, the content of CRC 11824 is compared with the expected value (or signature). If the signatures match, the function block 11800 passes the test and will be considered to be working properly. This type of testing is useful for quick "go" or "fail" testing because the test is independent of the functional block being tested and does not require sorting through a large number of test partitions or using an external tester. BIST, group-scan and boundary-scan technologies are often combined in a complementary manner and used on the same ASIC. For a detailed theoretical discussion on LSFR and CRC, please refer to pages 432-447 of "Digital System Testing and Design for Testability". The author of the book is Abramovici, Breuer & Friedman, Computer Science Press (Computer Science Press), 1990.

另外一個適用於解決3D IC產能和可靠性問題之技術是三重模組冗餘(三模冗餘)。該項技術即是使用三層冗餘實現電路設計,並將結果進行比對。因為2個或3個電路之輸出總是相同(比如2進制訊號),表決電路(或者3個中之大多數/MAJ3)就會將這一相同之輸出作為結果。儘管這一技術主要用於可靠性要求較高或耐輻射要求較高之系統,如軍事、航空和空間應用領域,它也可以用來掩蓋故障電路之錯誤,因為只要3個中之任意2個電路正常,系統之所有功能都會正常工作。有關TMR系統、單粒子效應 (SEE)、單粒子翻轉(SEU)、單粒子瞬變(SET)之耐輻射討論,可以在US專利申請公開2009/0204933中找到,授權人Rezgui。 Another technology suitable for solving 3D IC productivity and reliability issues is triple module redundancy (triple-mode redundancy). This technique is to implement circuit design using three layers of redundancy and compare the results. Since the output of 2 or 3 circuits is always the same (such as a binary signal), the voting circuit (or majority of 3/MAJ3) will take this same output as the result. Although this technology is mainly used in systems with high reliability requirements or high radiation resistance requirements, such as military, aerospace and space applications, it can also be used to cover up faulty circuit errors, because only two of the three The circuit is normal, and all functions of the system will work normally. About TMR system, single event effect Radiation Tolerance Discussion of (SEE), Single Event Upset (SEU), Single Event Transient (SET), can be found in US Patent Application Publication 2009/0204933, assigned to Rezgui.

依照本項發明之部分案例,3D技術也可以形成非常新穎之IC替代方案,能夠減少研發成本,增加產能,帶來其他優勢。 According to some cases of this invention, 3D technology can also form a very novel IC alternative, which can reduce research and development costs, increase production capacity, and bring other advantages.

本項發明之案例旨在為定制產品之半導體組件製造尋找一種最有效之新工藝。本項發明之案例建議使用可重複編程之抗熔儲存和“矽片直穿過孔(TSV)”來構建新之可編程邏輯器,亦即FPGA組件。本項發明之案例可能為現有之半導體製造通用工藝中面臨之高掩膜組成本和低靈活性挑戰提供解決方案。本項發明中部分案例之另外一個優勢在於能夠減少製造不同掩膜組之高成本,不同掩膜組能夠提供商用邏輯組件系列和產品線,使得每個產品均具有不同之主片組。本項發明之案例應能夠在現有技術之多個方面實現改良,包括半導體組件之構建方式,相關半導體組件之製造工藝。 The case of this invention is to find a most efficient new process for the manufacture of semiconductor components for custom products. The example of this invention proposes the use of reprogrammable antifuse and "Through-Silicon Via (TSV)" to build a new programmable logic device, ie FPGA device. Examples of this invention may provide solutions to the challenges of high mask set cost and low flexibility faced in existing common processes for semiconductor manufacturing. Another advantage of some cases of this invention is that it can reduce the high cost of manufacturing different mask sets that can provide commercial logic device series and product lines, so that each product has a different main die set. The case of this invention should be able to achieve improvements in many aspects of the existing technology, including the construction method of semiconductor components and the manufacturing process of related semiconductor components.

本項發明之案例反映了在已有投資基礎上節約掩模成本之努力,否則則需要生產一組商用主片。本項發明之案例同時也尋求在可設定組件上包含不同類型之儲存塊之能力。本項發明之案例為構造可設定組件提供了一種工藝,並能夠在組件上包含所需數量之邏輯器、記憶體、I/O、 和模擬功能。 The example of this invention reflects an effort to save mask costs over existing investments that would otherwise require the production of a set of commercial masters. Examples of this invention also seek the ability to include different types of memory blocks on a configurable component. Examples of this invention provide a process for constructing programmable modules that can contain as many logic, memory, I/O, and simulation functions.

另外,本項發明之案例還能使用重複邏輯器板(LT),能夠提供連續分佈之邏輯器。本項發明之案例表明,借助於矽片直穿過孔(TSV),一種模組化方法可以構建不同之可設定系統。一旦定義了TSV之標準尺寸和位置,人們就可以製造不同之可設定邏輯器晶片,可設定記憶體晶片、可設定I/O晶片,可設定類比電路晶片,然後將之連接起來構建不同之可設定系統。事實上,可以製造出不同之可編程晶片混合搭配,混合功能晶片、以及使用不同工藝製造之晶片。 In addition, examples of the present invention can also use duplicate logic boards (LT), which can provide sequentially distributed logic. The example of this invention demonstrates that, with the help of through-silicon vias (TSVs), a modular approach can be used to build different configurable systems. Once the standard size and location of TSVs are defined, one can manufacture different configurable logic chips, configurable memory chips, configurable I/O chips, configurable analog circuit chips, and then connect them to build different configurable chips. Set up the system. In fact, it is possible to create a mix and match of different programmable chips, mixed function chips, and chips made using different processes.

本項發明之某些案例將帶來其他優勢,如透過在抗熔儲存可設定互聯電路之上或之下使用特殊類型之電晶體,使得對矽片面積之利用更為有效。通常,FPGA組件使用抗熔儲存來設定組件之功能,還可能包括可對抗熔儲存編程之電子電路。編程電路首先可以用來配置組件,並且一旦系統設定完成,在大多數時候成為系統開支。用來給抗熔儲存編程之電壓通常要遠遠大於組件電路之工作電壓。抗熔儲存結構之設計可以實現未使用之抗熔儲存不會輕易熔融。因此,將抗熔儲存編程包含在矽基板上可能需要額外小心編程之高電壓,相應的可能需要分配一塊額外之矽片。 Some examples of this invention will bring other advantages, such as more efficient use of silicon area by using special types of transistors above and below the antifuse programmable interconnect circuit. Typically, FPGA devices use antifuse memory to set the function of the device, and may also include electronic circuits that can program the antifuse memory. Programming circuits can be used to configure components first, and become a system expense most of the time once system setup is complete. The voltage used to program the antifuse is usually much higher than the operating voltage of the component circuit. The design of the anti-melt storage structure can realize that the unused anti-melt storage will not melt easily. Therefore, incorporating antifuse programming on the silicon substrate may require extra care to program the high voltages, which in turn may require allocating an additional silicon die.

為了滿足高速組件之性能要求,工作中之電晶體之最大要求是速度,而編程電路可以相對以較低速度工作。所以編程電路可以使用薄膜電晶體,能夠很好的滿足功能要 求,並能減少對矽片面積之需要。 In order to meet the performance requirements of high-speed components, the maximum requirement of the working transistor is speed, and the programming circuit can work relatively at a lower speed. Therefore, the programming circuit can use thin film transistors, which can well meet the functional requirements. requirements, and can reduce the need for silicon area.

編程電路可以和薄膜電晶體一起構建,可以在工作電路製造完成之後,在可設定互聯層上加工,互聯層則包含並使用抗熔儲存。本發明案例之另外一個優勢就是能夠降低大批量生產之成本。人們可能只需要使用掩模定義之連接,而不是抗熔儲存和編程電路。也可能會使用一個定制過孔掩模,這樣能減少製造抗熔儲存層、薄膜電晶體、和/或編程電路互聯層有關之步驟。 Programming circuits can be built with thin film transistors, which can be fabricated on a programmable interconnect layer that contains and uses antifuse memory after the working circuit has been fabricated. Another advantage of the present invention is that it can reduce the cost of mass production. One may only need to use mask-defined connections, rather than antifuse and programming circuits. It is also possible to use a custom via mask, which reduces the number of steps involved in fabricating the antifuse memory layer, thin film transistor, and/or programming circuit interconnect layer.

依照本項發明之案例,所給出之積體電路組件包括一個成對抗熔可設定互聯電路和成對電晶體,用於對上述抗熔儲存之一進行設定,電晶體之製造在抗熔儲存之後進行。 In accordance with the examples of the present invention, an integrated circuit module is shown comprising a pair of antifuse programmable interconnection circuits and a pair of transistors for programming one of the above-mentioned antifuse memories, the transistors being fabricated in the antifuse memory Afterwards.

進一步依照本項發明之案例,所給出之積體電路組件包括一個成對抗熔可設定互聯電路和成對電晶體,用於對上述抗熔儲存之一進行設定,電晶體之製造在抗熔儲存至少加工完成。 Further in accordance with the examples of the present invention, an integrated circuit module is presented comprising a pair of antifuse programmable interconnection circuits and a pair of transistors for programming one of the aforementioned antifuse memories, the transistors being fabricated in the antifuse Storage is at least processed.

更進一步依照本項發明之案例,給出之積體電路組件包括第二成對抗熔儲存可設定邏輯晶片和成對之第二電晶體,用於對上述第二抗熔儲存之一進行設定,第二電晶體之製造在抗熔儲存之後加工完成。 Further according to the example of the present invention, the provided integrated circuit assembly includes a second pair of antifuse programmable logic chips and a pair of second transistors for setting one of the above-mentioned second antifuse memory, Fabrication of the second transistor is processed after antifuse storage.

同理,依照本項發明之案例,給出之積體電路組件包括第二成對抗熔儲存可設定邏輯晶片和成對之第二電晶體,用於對上述第二抗熔儲存之一進行設定,第二電晶體佈置在第二抗熔儲存之下方。 Similarly, according to the case of the present invention, the given integrated circuit assembly includes a second pair of antifuse memory programmable logic chips and a pair of second transistors for setting one of the above-mentioned second antifuse memory , the second transistor is disposed under the second antifuse storage.

依照本項發明之案例,積體電路組件包括:第一抗熔儲存層,之上至少有兩個金屬層,並且有一個第二抗熔儲存層位於兩金屬層之上。 According to an example of the present invention, the integrated circuit assembly includes: a first antifuse storage layer with at least two metal layers on it, and a second antifuse storage layer on the two metal layers.

依照本項發明之案例,一個可設定邏輯組件包括:抗熔儲存可設定查表邏輯器,透過抗熔儲存可設定互聯電路相連。 According to the case of the present invention, a settable logic component includes: an antifuse settable look-up table logic, which is connected through an antifuse settable interconnection circuit.

依照本項發明之案例,一個可設定邏輯組件包括:成對抗熔儲存可設定查表邏輯器,成對可設定可編程邏輯陣列(PLA)邏輯器,成對抗熔儲存互聯電路。 According to the case of the present invention, a settable logic component includes: paired antifuse programmable look-up logic devices, paired programmable logic array (PLA) logic devices, and paired antifuse interconnected circuits.

依照本項發明之案例,一個可設定邏輯組件包括:成對抗熔儲存可設定查表邏輯器,成對可設定驅動晶片,晶片透過成對抗熔儲存來設定。 According to the case of the present invention, a settable logic component includes: paired antifuse memory settable look-up table logic, paired settable drive chips, and the chips are set through paired antifuse memory.

依照本項發明之案例,一個可設定邏輯組件包括:可設定邏輯晶片,由成對抗熔儲存可設定互聯電路連接,電路中至少有一個抗熔儲存設定連接電路透過永久性記憶設定。 According to the example of the present invention, a settable logic component includes: a settable logic chip connected by a pair of antifuse settable interconnection circuits, and at least one antifuse settling interconnection circuit in the circuit is set through a permanent memory.

依然依照本項發明之案例,一個可設定邏輯組件至少包含一個抗熔儲存互聯電路,並且可透過PLA功能進行設定。 Still according to the example of the present invention, a configurable logic element includes at least one antifuse interconnection circuit, and can be set through the PLA function.

依照本項發明之替代案例,一個積體電路系統包括:一個可設定邏輯晶片和一個I/O晶片,該可設定I/O晶片使用矽片直穿過孔(TSV)與I/O晶片相連。 In accordance with an alternate embodiment of the invention, an integrated circuit system includes: a programmable logic die and an I/O die, the programmable I/O die is connected to the I/O die using straight-through-silicon vias (TSVs) .

依然依照本項發明之替代案例,一個積體電路系統包括:一個可設定邏輯晶片和一個儲存晶片,上述晶片使用 矽片直穿過孔(TSV)連接。 Still in accordance with an alternative example of the invention, an integrated circuit system includes: a programmable logic chip and a storage chip, said chip using Straight through silicon via (TSV) connections.

依然依照本項發明之替代案例,一個積體電路系統包括:一個第一可設定邏輯晶片和一個第二可設定邏輯晶片,第一可設定邏輯晶片和第二可設定邏輯晶片使用矽片直穿過孔(TSV)相連。 Still in accordance with an alternative example of the present invention, an integrated circuit system includes: a first configurable logic chip and a second configurable logic chip, the first configurable logic chip and the second configurable logic chip use silicon die through Via (TSV) connected.

並且,依照本項發明之案例,積體電路系統包含一個I/O晶片,該I/O晶片使用不同之工藝製造,製造工藝與可設定邏輯晶片之工藝不同。 Also, in accordance with the example of the present invention, the integrated circuit system includes an I/O chip fabricated using a different process than the configurable logic chip.

依然依照本項發明之替代案例,一個積體電路系統至少包括:兩個透過矽片直穿過孔(TSV)相連之邏輯晶片,部分矽片直穿過孔用來傳輸系統匯流排訊號。 Still according to an alternative example of the present invention, an integrated circuit system includes at least two logic chips connected through through-silicon vias (TSVs), some of which are used to transmit system bus signals.

依照本項發明之案例,積體電路系統包含至少一個可設定邏輯組件。 According to an example of the present invention, an integrated circuit system includes at least one programmable logic device.

依然依照本項發明之替代案例,一個積體電路系統包括:一個抗熔儲存可設定邏輯晶片和一個編程晶片,上述晶片使用矽片直穿過孔(TSV)相連。 Still in accordance with an alternative embodiment of the invention, an integrated circuit system includes: an antifuse programmable logic chip and a programming chip, said chips being connected using through-silicon vias (TSVs).

另外,人們對於減少晶片間互聯電路之影響有逐步增長之需求。實際上,目前,互聯電路已經成為了IC性能和功率之主要因素。3D IC不失為一個縮短互聯電路之辦法。目前,對於通用邏輯器3D IC,已知可用之方法就是使用矽片直穿過孔(TSV)將加工好之組件堆疊佈置。TSV之問題在於過孔相對較大,每個之面積為幾微米,可能會嚴重限制可以採用之TSV數量。本項發明之部分案例給出了構建3D IC之多個替代方案,很多連接(TSV)之 大小可以製成小於1微米,使得3D IC技術能夠為大多數組件所使用。 In addition, there is an increasing need to reduce the impact of interconnecting circuits between chips. In fact, interconnect circuitry is now a major factor in IC performance and power. 3D IC can be regarded as a way to shorten the interconnection circuit. At present, for general-purpose logic 3D ICs, a known and available method is to use through-silicon vias (TSVs) to stack processed components. The problem with TSVs is that the vias are relatively large, each measuring a few microns in area, which can severely limit the number of TSVs that can be used. Some examples of this invention present several alternatives for building 3D ICs, between many connections (TSVs) The size can be made less than 1 micron, making 3D IC technology usable for most components.

另外,使用本發明中提出3D IC技術還可以為新組件之生產提供替代方案。 In addition, using the 3D IC technology proposed in this invention can also provide an alternative for the production of new components.

860-1~860-4:可程式設計電晶體 860-1~860-4: programmable transistor

820-1,1~820-2,2:反熔絲 820-1,1~820-2,2: Antifuse

830-1:金屬 830-1: metal

850-1,1,850-1,2:反熔絲 850-1,1,850-1,2: Antifuse

310-1~310-4:金屬條 310-1~310-4: metal strip

308-1~308-4:金屬條 308-1~308-4: metal strip

312-1~312-4:反熔絲 312-1~312-4: Antifuse

300,320:瓷片 300,320: Porcelain

302:Y選擇邏輯 302: Y selection logic

304:Y可程式設計電晶體 304:Y programmable transistor

306:可程式設計電壓 306: Programmable voltage

314:接地 314: grounding

316:X選擇邏輯 316: X selection logic

318:X可程式設計電晶體 318:X programmable transistor

300B:可程式設計互連結構 300B: Programmable Interconnect Architecture

308-4B1,308-4B2:較短條 308-4B1, 308-4B2: shorter strip

312-3B,312-4B:反熔絲 312-3B, 312-4B: Antifuse

318B,318B1:X可程式設計電晶體 318B, 318B1: X programmable transistor

402,404,408,412:金屬條 402, 404, 408, 412: metal bars

406,410:反熔絲 406,410: Antifuse

502:輸入 502: input

504:倒相器 504: Inverter

506:輸出 506: output

510:倒相器 510: Inverter

512:輸入 512: input

514:緩衝器 514: buffer

516:輸出 516: output

520:反熔絲可配置驅動單元 520: Antifuse Configurable Driver Unit

522:輸入 522: input

524:可配置強度緩衝器 524: Configurable Strength Buffer

524-1,524-3:緩衝器 524-1, 524-3: Buffer

526:輸出 526: output

528-1~528-3:反熔絲 528-1~528-3: Antifuse

530:延時觸發器單元 530: Delay trigger unit

532-2:輸入 532-2: input

532-1,532-3~532-5:控制輸入 532-1, 532-3~532-5: Control input

534:延時觸發器 534: Delay trigger

536:輸出 536: output

600:邏輯元件 600: logic element

602-1~602-4:輸入 602-1~602-4: input

602-6,602-7:額外輸入 602-6, 602-7: additional input

604:查閱資料表4 604: Consult data sheet 4

604-5:2:1複用器 604-5:2:1 Multiplexer

606:輸出 606: output

608-1:反熔絲 608-1: Antifuse

6A00:可程式設計邏輯陣列邏輯單元 6A00: Programmable Logic Array Logic Cells

6A01:反熔絲 6A01: Antifuse

6A02:輸入值 6A02: Input value

6A06:輸出 6A06: Output

6A14:多輸入和 6A14: Multiple input and

6A15:多輸入或 6A15: Multiple input or

700:可程式設計單元 700: Programmable Design Unit

701:反熔絲 701: Antifuse

701HV:反熔絲 701HV: Antifuse

701VV:反熔絲 701VV: Antifuse

701HH:反熔絲 701HH: Antifuse

702:輸入值 702: Input value

706:輸出值 706: output value

708:輸入和輸出條 708: Input and output bars

710:邏輯單元 710: logic unit

720:可配置互連結構 720: Configurable interconnect structure

722V:分隔號 722V: separator

722H:水準條 722H: level bar

724:長條 724: strip

724LH:反熔絲 724LH: Antifuse

802:基底 802: base

804:第一層反熔絲 804: The first layer of antifuse

806:層 806: layer

807:第二層反熔絲 807: The second layer of antifuse

808:預處理圓晶或層 808: pre-processing wafer or layer

808A,808B,808C:預處理圓晶或層 808A, 808B, 808C: pre-processing wafers or layers

809,809A,809B:傳遞層 809, 809A, 809B: transfer layer

810:可配置互連結構 810: Configurable interconnect structure

812:連接到外部 812: Connect to the outside

814:優先線路 814: priority line

816:觸點連接 816: contact connection

402:基底 402: base

404:直通矽穿孔(TSV) 404:Through Silicon Via (TSV)

102:瓷片汽泡 102: Porcelain Bubbles

102-1:瓷片 102-1: Porcelain

102-2:瓷片 102-2: Porcelain

104:線路 104: line

104-1:可能的劃片線 104-1: Possible scribe line

104-2:可能的劃片線 104-2: Possible scribe line

106:串化器四芯導線 106: Serializer four-core wire

108:劃片街區 108: Divide blocks

1100A:可程式設計邏輯碎片 1100A: Programmable logic fragments

1101:瓷片 1101: Porcelain

1102:可能的劃片線 1102: Possible scribe line

110B:結構化ASIC 110B: Structured ASIC

1102:可能的劃片線 1102: Possible scribe line

1100C:RAM瓷片 1100C: RAM tile

1100D:DRAM瓷片 1100D: DRAM tile

1100E:微處理器或微控制器內核 1100E: Microprocessor or microcontroller core

1100F:輸入/輸出值碎片 1100F: Input/Output Value Fragmentation

1202A:基極 1202A: base

1204A:晶片 1204A: chip

1206A:晶片 1206A: chip

1208A:晶片 1208A: chip

1202B:基極 1202B: base

1204B:晶片 1204B: chip

1206B:晶片 1206B: chip

1202C:基極 1202C: base

1202D:基極 1202D: base

1202E:底層晶片 1202E: Bottom Chip

1204E:晶片 1204E: chip

1206E:晶片 1206E: chip

1208E:晶片 1208E: chip

1402:晶圓 1402: Wafer

1404:層 1404: layer

1406:施主晶圓 1406: Donor Wafer

1408:智能切割線 1408: Intelligent cutting line

1410:三維晶圓 1410: 3D Wafer

1412:氧化層 1412: oxide layer

1414:頂端部分 1414: top part

1501,1502:可程式設計電晶體 1501,1502: Programmable Transistors

1504:反熔絲 1504: Antifuse

1506,1508:可程式設計連接 1506, 1508: Programmable Connections

1601,1602:隔離電晶體 1601, 1602: isolated transistor

1603:控制線路 1603: Control circuit

1604:反熔絲 1604: Antifuse

1606,1608:邏輯電晶體 1606,1608: logic transistors

1610:反熔絲 1610: Antifuse

1710:分區 1710: partition

1711:回饋偏壓電路 1711: feedback bias circuit

1720:回饋偏壓級控制電路 1720: feedback bias stage control circuit

1721:電壓發生器 1721: Voltage generator

1723,1724:連接 1723, 1724: connection

1725:負電壓發生器 1725: negative voltage generator

1726:正電壓發生器 1726: Positive Voltage Generator

1727,1729:振盪器 1727, 1729: Oscillators

1732:N型溝道金屬-氧化物-半導體電晶體 1732: N-channel metal-oxide-semiconductor transistor

1734:P型溝道金屬-氧化物-半導體電晶體 1734: P-type channel metal-oxide-semiconductor transistor

17C02:功率控制電路單元 17C02: Power control circuit unit

17C04:控制線路 17C04: control circuit

17C08,17C10:區 17C08, 17C10: area

17C12:電源線 17C12: Power cord

17C16:主設備 17C16: master device

17D02:順序有源電路元件 17D02: Sequential Active Circuit Components

17D06:互連線 17D06: Interconnecting wire

17D08:高阻抗探針電路 17D08: High Impedance Probe Circuit

17D12:選擇電路 17D12: Selection circuit

17D14:探針輸出信號 17D14: Probe output signal

17D16:緩衝器 17D16: Buffer

1802:SRAM單元 1802: SRAM cell

1806,1808:邏輯電路 1806, 1808: logic circuits

1812:連接 1812: connect

1912:輸出驅動 1912: Output drive

1914:輸入/輸出連接 1914: Input/Output Connections

1916:輸入保護電路 1916: Input protection circuit

1920:輸入邏輯 1920: Input logic

1922:緩衝器 1922: Buffer

1924:連接 1924: Connection

19B06:PMOS和NMOS輸出電晶體 19B06: PMOS and NMOS output transistors

19B08:背面晶片或晶片凸點 19B08: Backside Wafer or Wafer Bumps

19B10:直通矽晶穿孔 19B10: Through silicon via

19C10:晶片 19C10: chip

19C12:直通矽晶穿孔 19C12: Through silicon via

19C14:初晶矽 19C14: Primary silicon

19C20:晶片 19C20: chip

19C22:直通矽晶穿孔 19C22: Through silicon via

19C24:初晶矽 19C24: Primary silicon

19C30:晶片 19C30: chip

19C32:直通矽晶穿孔 19C32: Through silicon via

19C34:初晶矽 19C34: Primary silicon

19C40:凸點 19C40: bump

19D02:散熱器 19D02: Radiator

19D04:均熱片基底 19D04: Spreader base

19D06:仲介層 19D06: Intermediary layer

19D08:通孔 19D08: Through hole

19D12:均熱片 19D12: Heat spreader

19D14:微處理器有效面積 19D14: Microprocessor effective area

19D16:基礎 19D16: Basics

19D18:多重壓縮DRAM 19D18: Multiple Compression DRAM

19D20:直通矽晶穿孔 19D20: Through silicon via

19D22:直通矽晶穿孔 19D22: Through silicon via

19D24:DRAM堆疊 19D24: DRAM stacking

19E24:絲焊 19E24: Wire bonding

19E26:重新分佈層 19E26: Redistribution layer

19F00:Nu穿孔 19F00: Nu perforation

19F01:掩埋氧化物 19F01: buried oxide

19F02:基材晶片 19F02: Substrate wafer

19F03:Nu觸點 19F03:Nu contact

19F04:Dnu觸點 19F04:Dnu contact

19F05:薄矽 19F05: thin silicon

19G00:體矽圓片 19G00: bulk silicon wafer

19G02:DTSV_先有技術 19G02: DTSV_Prior Technology

19H04:施主矽片 19H04: Donor Wafers

19H05:表面 19H05: Surface

19H06:深度 19H06: Depth

19H07:Nu穿孔 19H07: Nu perforation

19H08:受主晶圓 19H08: Acceptor Wafers

19H10:施主矽片部分 19H10: Donor wafer part

19I09:處理器 19I09: Processor

19I10:DRAM 19I10:DRAM

19I11:散熱器 19I11: Radiator

19I12:基底 19I12: Base

19I13,19I14:直通矽片連接 19I13, 19I14: Through silicon connection

19J01:基底 19J01: Base

19J02:頂部矽層 19J02: Top silicon layer

2002:初步處理晶圓 2002: Preliminary wafer processing

2004:附加層 2004: Additional layers

2006:施主晶圓 2006: Donor Wafers

2008:智能切割線 2008: Intelligent cutting line

2010:三維晶圓 2010: 3D Wafer

2011:BEOL層 2011: BEOL layer

2012:氧化層 2012: oxide layer

2014:頂端部分 2014: top section

2019:半導體層 2019: Semiconductor layer

2102:P型晶圓 2102:P type wafer

2104:N型矽片 2104: N-type silicon wafer

2106:P-外延生長 2106:P-Epitaxial growth

2108:P+層 2108: P+ layer

2110:解理面 2110: cleavage surface

2112:氧化物 2112:Oxide

22B02:柵極指定區 22B02: Gate designation area

22B04:頂部電晶體源極 22B04: Top Transistor Source

22B06:頂部電晶體漏極 22B06: Top Transistor Drain

22B08:隔離區 22B08: Quarantine

22C02:低溫氧化物 22C02: low temperature oxide

22D02:柵極形成自對準蝕刻工藝製備 22D02: gate formation self-aligned etching process preparation

22D04:源極和漏極延伸區域 22D04: Source and drain extension regions

22E02:低溫柵極電介質 22E02: Low temperature gate dielectric

22F02:金屬柵極 22F02: Metal grid

22G02:厚氧化物 22G02: thick oxide

22G20:電晶體 22G20: Transistor

22F02:柵極 22F02: Gate

22F02-1:後柵極 22F02-1: rear gate

2302:N-晶圓 2302: N-Wafer

2304:N+層 2304: N+ layers

2306:解理面 2306: cleavage surface

2308:氧化物 2308:Oxide

24A04:N+層 24A04: N+ layer

24B02:柵極指定區 24B02: Gate designation area

24B04:頂部電晶體源極 24B04: Top Transistor Source

24B06:頂部電晶體漏極 24B06: Top Transistor Drain

24B08:電晶體間隔離區 24B08: Isolation area between transistors

24B09:蝕刻空間 24B09: Etched space

24C02:電晶體間移除N-層 24C02: Remove N-layer between transistors

24D02:淺P+區 24D02: Shallow P+ area

24D04:反射層 24D04: reflective layer

24D06:光線 24D06: Light

24D08:開孔面積 24D08: Opening area

24D10:反射層 24D10: reflective layer

24E02:厚氧化物 24E02: thick oxide

24E04:光子能吸收層 24E04: Photon energy absorbing layer

24F02:柵極觸點 24F02: Gate contact

24F04:厚氧化物 24F04: thick oxide

24F06:N+觸點 24F06: N+ contact

2502:N-晶圓 2502: N-Wafer

2504:N+ 2504:N+

2506:智能切割解理面 2506: Intelligent cutting cleavage plane

2508:N-外延生長層 2508: N- epitaxial growth layer

2510:P+層 2510: P+ layer

2512:氧化物 2512:Oxide

26B02:柵極指定區 26B02: Gate designation area

26B04:頂部電晶體源極 26B04: Top Transistor Source

26B06:頂部電晶體漏極 26B06: Top Transistor Drain

26B08:電晶體間隔離區 26B08: Isolation area between transistors

26C09:電晶體間移除P+層 26C09: Remove P+ layer between transistors

26C12:電晶體間移除N-層 26C12: Remove N-layer between transistors

26D02:淺P+區 26D02: Shallow P+ area

26E02:柵極觸點 26E02: Gate contact

26E04:厚氧化物 26E04: thick oxide

26E06:N+觸點 26E06: N+ contact

26E12:觸點 26E12: Contact

2702:N+晶圓 2702:N+wafer

2704:P-層 2704: P-layer

2706:智能切割解理面 2706: Intelligent cutting cleavage plane

2708:N-層 2708: N-layer

2710:N+層 2710: N+ layers

28A02:N+摻雜層 28A02: N+ doped layer

2802:基極 2802: base

2804:低溫氧化物 2804: low temperature oxide

2806:發射體 2806: emitter

2808:集合器 2808: aggregator

2809:隔離 2809: Isolation

29B02:電晶體隔離 29B02: Transistor isolation

29B04:基底P+源極觸點開口 29B04: Substrate P+ source contact opening

29C02:隔離區 29C02: Quarantine

29C04:低溫氧化物 29C04: low temperature oxide

29C06:研磨抑制層 29C06: grinding inhibition layer

29D02:源極 29D02: source

29D04:漏極 29D04: drain

29D06:柵極 29D06:Gate

29D08:源極和漏極延伸區域 29D08: Source and Drain Extension Regions

29E02:柵極電介質 29E02: Gate Dielectric

29E04:柵極材料 29E04: Gate material

29G02:厚氧化物 29G02: thick oxide

29G04:穿孔 29G04: perforation

29G06:底層互連接線 29G06: Bottom layer interconnect wiring

3000:施主晶圓 3000: Donor wafers

3000L:轉移層 3000L: transfer layer

3002:充氣投影 3002: inflatable projection

3004:n型電晶體行數 3004: Number of n-type transistor rows

3006:p型電晶體行數 3006: Number of rows of p-type transistors

3008:西 3008:West

3020:對準標記 3020: Alignment Mark

3040:四個基本方位指示器 3040: Four Cardinal Bearing Indicators

3100:主晶圓 3100: master wafer

3120:對準標記 3120: alignment mark

3122:南北向DY未對準 3122:North-south DY misalignment

3124:DX未對準 3124: DX misaligned

3202:殘數 3202: residual

33A02:穿孔 33A02: perforation

33A04:南北著陸帶 33A04: North and South Landing Strips

33B02:穿孔 33B02: perforation

33B04:南北著陸帶 33B04: North and South Landing Strips

3400:重複行數 3400: the number of repeated rows

3402:P-型晶圓 3402:P-type wafer

3404:N+層 3404: N+ layers

3406:P+層 3406: P+ layer

3408:P-外延生長 3408:P-Epitaxial Growth

3410:N-區 3410:N-District

3412:淺P+ 3412: Shallow P+

3414:淺N+ 3414: Shallow N+

3416:智能切割解理面 3416: Intelligent cutting cleavage plane

3418:氧化物 3418:Oxide

3500:基本 3500: basic

3502:解理表面 3502: Cleavage surface

35B02:電晶體隔離 35B02: Transistor isolation

35B04:金屬層 35B04: metal layer

35B06:基底P+ 35B06: Base P+

35B08:基底N+ 35B08: Substrate N+

35C02:隔離區 35C02: Quarantine

35C04:氧化物 35C04: oxide

35C06:研磨抑制層 35C06: grinding inhibition layer

35D02:n型溝道源極 35D02: n-type channel source

35D04:n型溝道漏極 35D04: n-type channel drain

35D06:n型溝道自對準柵極 35D06: n-type channel self-aligned gate

35D08:p型溝道源極 35D08: p-type channel source

35D10:p型溝道漏極 35D10: p-type channel drain

35D12:p型溝道自對準柵極 35D12:p-type channel self-aligned gate

35D14:p+角源極和漏極延伸區域 35D14: p+ corner source and drain extension regions

35E02:柵極電介質 35E02: Gate Dielectric

35E04:金屬柵極 35E04: Metal grid

35G02:氧化物 35G02: oxide

35G04:穿孔 35G04: perforation

3600:晶圓 3600: Wafer

3601:瓷片 3601: Porcelain

3602:可能的劃片線 3602: Possible scribe line

3611:終端設備 3611: terminal equipment

3612:實際劃片線 3612: Actual scribing line

3700:晶圓 3700: Wafer

3701:瓷片 3701: Porcelain

3702:微控制單元-MCU 3702: Micro Control Unit - MCU

3702-00:MCU 3702-00: MCU

3702-01:MCU 3702-01: MCU

3702-11:MCU 3702-11:MCU

3702-12:MCU 3702-12: MCU

3704:MCU到MCU連接 3704: MCU to MCU connection

3711:瓷片 3711: Porcelain

3714:MCU到MCU連接 3714: MCU to MCU connection

3800:西南角瓷片 3800: Southwest corner tile

3802:控制輸入值 3802: Control input value

3814:延時集成(TDI) 3814: Time Delay Integration (TDI)

3816:延時集成(TDI) 3816: Time Delay Integration (TDI)

3820:東北角碎片 3820: Northeast corner fragment

3822:TDO輸出 3822: TDO output

3902:P-型晶圓 3902:P-type wafer

3904:N+層 3904: N+ layers

3906:P-層 3906: P-layer

3908:N+層 3908: N+ layers

3910:導電阻擋層 3910: Conductive barrier layer

3912:智能切割解理面 3912: Intelligent cutting cleavage plane

3914:Al-Ge層 3914: Al-Ge layer

3916:導電阻擋層 3916: Conductive barrier layer

3920:室內金屬層 3920: Indoor metal layer

4002:蝕刻抑制層 4002: etch inhibition layer

4004:導電層 4004: conductive layer

4006:電晶體塔 4006: Transistor Tower

4010:氧化物 4010: oxide

4014:側壁柵極氧化物 4014: sidewall gate oxide

4018:柵極層 4018: gate layer

4020:柵極掩模光致抗蝕劑 4020: Gate mask photoresist

4022:間隔型柵電極 4022: spaced gate electrode

4024:柵電極 4024: Gate electrode

4030:氧化物 4030: oxide

4034:穿孔觸點至塔N+ 4034: Pierced Contact to Tower N+

4036:穿孔觸點至柵電極 4036: Pierced contact to gate electrode

4040:金屬線 4040: metal wire

4100:第一層可程式設計層 4100: The first layer of programming layer

4102:3*3瓷片 4102: 3*3 tiles

4104:可程式設計連接 4104: Programmable Connection

4105:分支可程式設計連接 4105: Branch Programmable Connection

4106:可程式設計元件 4106: Programmable Design Components

4107:可程式設計元件 4107: Programmable Design Components

4108:可程式設計元件 4108: Programmable Design Components

4110:第二層可程式設計層 4110: The Second Programmable Layer

4112:3*3瓷片 4112: 3*3 tiles

4116:可程式設計元件 4116: Programmable Design Components

4117:可程式設計元件 4117: Programmable Design Components

4118:可程式設計元件 4118: Programmable Design Components

4120:第三層可程式設計層 4120: Layer 3 Programmable Design Layer

4122:3*3瓷片 4122: 3*3 tiles

4140:層間垂直連接 4140: vertical connection between layers

4202:NMOS電晶體 4202: NMOS transistor

4204:PMOS電晶體 4204: PMOS transistor

4206:NMOS源極 4206: NMOS source

4207:PMOS源極 4207: PMOS source

4208:NMOS和PMOS漏極 4208: NMOS and PMOS drain

4210:NMOS&PMOS柵極 4210: NMOS&PMOS gate

4300:高摻雜N型單晶矽片 4300: Highly doped N-type single crystal silicon wafer

4301:P-層 4301: P-layer

4302:電阻層 4302: resistance layer

4304:氧化物 4304:Oxide

4310:P-型晶圓 4310:P-type wafer

4312:氧化物 4312:Oxide

4314:智能切割解理面 4314: Intelligent cutting cleavage plane

4316:解理表面 4316: Cleavage Surface

4400:氧化層 4400: oxide layer

4402:保護氧化物 4402: protective oxide

4404:研磨抑制層 4404: grinding inhibition layer

4406:NMOS源極至接地連接 4406: NMOS source to ground connection

4410:淺溝槽(STI)隔離區 4410: Shallow Trench (STI) Isolation

4411:柵極氧化物 4411: gate oxide

4412:NMOS柵極 4412: NMOS gate

4414:在STI溝道互連上的多晶矽 4414: Polysilicon on STI Trench Interconnect

4416:植入偏移間隔 4416: implant offset interval

4418:NMOS電晶體源極和漏極 4418: NMOS transistor source and drain

4420:氧化物 4420:Oxide

4422:晶圓表面 4422: Wafer surface

4500:氧化層 4500: oxide layer

4502:N-晶圓 4502: N-Wafer

4504:氧化物 4504: oxide

4506:智能切割解理面 4506: Intelligent cutting cleavage plane

4508:解理表面 4508: Cleavage Surface

4510:氧化層 4510: oxide layer

4512:淺溝槽(STI)隔離區 4512: Shallow Trench (STI) Isolation

4514:柵極氧化物 4514: gate oxide

4516:PMOS柵極 4516: PMOS gate

4518:在STI溝道互連上的多晶矽 4518: Polysilicon on STI Trench Interconnects

4520:植入偏移間隔 4520: implant offset interval

4522:PMOS電晶體源極和漏極區 4522: PMOS transistor source and drain regions

4524:氧化物 4524:Oxide

4530:蝕刻抑制和研磨抑制層 4530: etch inhibition and grinding inhibition layer

4532:最深觸點 4532: Deepest contact

4540:NMOS漏極唯一觸點 4540: NMOS drain only contact

4542:在STI互連觸點上的NMOS&PMOS柵極 4542: NMOS & PMOS Gates on STI Interconnect Contacts

4544:NMOS和PMOS漏極觸點 4544: NMOS and PMOS drain contacts

4546:在STI觸點上的NMOS唯一柵極 4546: NMOS unique gate on STI contact

4550:在STI觸點上的PMOS柵極互連 4550: PMOS gate interconnect on STI contacts

4552:PMOS唯一柵極觸點 4552: PMOS unique gate contact

4554:PMOS唯一漏極觸點 4554: PMOS only drain contact

4600:STI(淺溝槽隔離) 4600: STI (Shallow Trench Isolation)

4602:NMOS和PMOS柵極 4602: NMOS and PMOS gates

4604:STI上NMOS柵極至STI觸點上PMOS柵極 4604: NMOS gate on STI to PMOS gate on STI contact

4606:N+源極觸點至接地層 4606: N+ source contact to ground plane

4608:PMOS源極觸點 4608: PMOS source contact

4610:NMOS和PMOS漏極共用觸點 4610: NMOS and PMOS Drain Common Contact

4702:NMOS電晶體 4702: NMOS transistor

4704:PMOS電晶體 4704: PMOS transistor

4706:NMOS源極 4706: NMOS source

4707:PMOS源極連接至+V 4707: PMOS source connected to +V

4708:PMOS漏極 4708: PMOS drain

4710:NMOS&PMOS柵極 4710:NMOS&PMOS gate

4800:STI(淺溝槽隔離) 4800: STI (Shallow Trench Isolation)

4802:NMOS和PMOS柵極 4802: NMOS and PMOS gates

4804:STI上NMOS柵極至STI觸點上PMOS柵極 4804: NMOS gate on STI to PMOS gate on STI contact

4806:N+源極觸點至接地層 4806: N+ source contact to ground plane

4808:PMOS源極觸點 4808: PMOS source contact

4810:NMOS和PMOS漏極共用觸點 4810: NMOS and PMOS drain common contact

4812:NMOS源極觸點 4812: NMOS source contact

4900:STI(淺溝槽隔離) 4900: STI (Shallow Trench Isolation)

4902:PMOS-B柵極 4902: PMOS-B gate

4904:虛擬柵極 4904: Virtual gate

4906:PMOS-A柵極 4906: PMOS-A gate

4908:在STI觸點上的唯一PMOS柵極 4908: Unique PMOS gate on STI contact

4910:NMOS-A柵極 4910: NMOS-A gate

4912:NMOS-B柵極 4912: NMOS-B gate

4914:STI上NMOS柵極至STI觸點上PMOS柵極 4914: NMOS gate on STI to PMOS gate on STI contact

4916:在STI觸點上的NMOS唯一柵極 4916: NMOS unique gate on STI contact

4918:N+源極觸點至接地層 4918: N+ Source Contact to Ground Plane

4920:PMOS-B源極觸點 4920: PMOS-B source contact

4922:NMOS-A,NMOS-B和PMOS-B漏極共用觸點 4922: NMOS-A, NMOS-B and PMOS-B drain common contacts

5000:STI(淺溝槽隔離) 5000: STI (Shallow Trench Isolation)

5002:NMOS電晶體 5002: NMOS transistor

5004:PMOS電晶體 5004: PMOS transistor

5006:NMOS柵極輸入 5006: NMOS gate input

5008:PMOS柵極輸入 5008: PMOS gate input

5010:NMOS和PMOS源極 5010: NMOS and PMOS source

5012:NMOS和PMOS漏極 5012: NMOS and PMOS drain

5014:PMOS柵極 5014: PMOS gate

5016:NMOS柵極 5016: NMOS gate

5018:在STI觸點上的唯一PMOS柵極 5018: Unique PMOS gate on STI contact

5020:在STI觸點上的唯一NMOS柵極 5020: Unique NMOS gate on STI contact

5022:NMOS和PMOS源極共用觸點 5022: NMOS and PMOS source common contact

5024:NMOS和PMOS漏極共用觸點 5024: NMOS and PMOS drain common contact

5100:電晶體隔離氧化物 5100: Transistor Isolation Oxide

5102:存儲電晶體M2 5102: storage transistor M2

5104:存儲電晶體M4 5104: storage transistor M4

5106:字線電晶體M6 5106: word line transistor M6

5108:Vdd 5108:Vdd

5110:接地 5110: grounding

5112:STI上的PMOS多晶矽至STI觸點上的NMOS多晶矽 5112: PMOS polysilicon on STI to NMOS polysilicon on STI contacts

5114:PMOS P+至NMOS N+觸點 5114: PMOS P+ to NMOS N+ contact

5122:位線 5122: bit line

5124:位線 小節線 5124: bit line bar line

5202:曲線D=1E18/1E17 5202: Curve D=1E18/1E17

5204:曲線D=1E17/1E18 5204: Curve D=1E17/1E18

5206:曲線D=1E18/1E17 5206: Curve D=1E18/1E17

5208:曲線D=1E17/1E18 5208: Curve D=1E17/1E18

5300:電晶體隔離氧化物 5300: Transistor Isolation Oxide

5302:SRAM狀態讀取電晶體M7、M9 5302: SRAM state read transistor M7, M9

5304:電晶體M1、M2 5304: Transistor M1, M2

5306:電晶體M3、M4 5306: Transistor M3, M4

5308:STI觸點上的金屬至柵極 5308: Metal to Gate on STI Contacts

5310:PMOS金屬-1 5310: PMOS metal-1

5312:PMOS金屬-1 5312: PMOS Metal-1

5314:STI上的PMOS多晶矽至STI觸點上的底部NMOS多晶矽 5314: PMOS polysilicon on STI to bottom NMOS polysilicon on STI contacts

5316:檢測線 5316: detection line

5318:檢測線杆 5318: Detection pole

5320:NMOS N+觸點 5320: NMOS N+ contact

5322:接地 5322: ground

5324:觸點 5324: contact

5326:下拉電晶體M8、M10 5326: pull-down transistor M8, M10

5330:接地 5330: ground

5332:字線電晶體M6 5332: word line transistor M6

5334:Vdd 5334:Vdd

5336:匹配線 5336: Matching line

5340:位線 小節線 5340: bit line bar line

5342:位線 5342: bit line

5402:N-晶圓 5402: N-Wafer

5404:N+層 5404: N+ layers

5410:導電阻擋層 5410: Conductive barrier layer

5412:智能切割解理面 5412: Intelligent cutting cleavage plane

5414:共晶鍵合 5414: eutectic bonding

5416:導電阻擋層 5416: Conductive barrier layer

5420:室內頂部金屬線 5420: Indoor Roof Metal Wire

5500:金屬鍵合層 5500: Metal bonding layer

5502:蝕刻抑制層 5502: etch inhibition layer

5504:N+層 5504: N+ layers

5506:電晶體塔 5506:Transistor Tower

5510:氧化物 5510: oxide

5514:側壁柵極氧化物 5514: sidewall gate oxide

5518:P+摻雜非晶矽 5518: P+ doped amorphous silicon

5520:柵極掩模光致抗蝕劑 5520: Gate Mask Photoresist

5530:氧化物 5530: oxide

5534:觸點 5534: contact

5536:觸點至柵電極 5536: contact to gate electrode

5540:金屬線 5540: metal wire

5600A:N-晶圓 5600A: N-Wafer

5602A:柵極氧化物 5602A: Gate Oxide

5604A:N+層 5604A: N+ layers

5600:N-晶圓 5600: N-Wafer

5602:柵極氧化物 5602: gate oxide

5604:N+層 5604: N+ layers

5606:植入 5606:Implant

5608:解理面 5608: cleavage surface

5610:N+層 5610: N+ layers

5612:柵極氧化物 5612: gate oxide

5614:平行線 5614: parallel lines

5616:柵極氧化物 5616: gate oxide

5618:多晶矽 5618: Polysilicon

5620:薄氧 5620: thin oxygen

5608G:解理面 5608G: cleavage plane

5622:金屬互連條 5622: Metal Interconnect Strips

5624:氧化物 5624:Oxide

5626:研磨抑制層 5626: grinding inhibition layer

5628:隔離開口 5628: Isolation opening

5629:開口 5629: opening

5630:頂部柵極 5630: top gate

5632:柵極觸點 5632:Gate contact

5634:觸點 5634: contact

5636:直通穿孔 5636: Straight through hole

5640:金屬線 5640: metal wire

5700:N-晶圓 5700: N-Wafer

5702:氧化物 5702:Oxide

5704:N+ 5704:N+

5706:互連 5706: Interconnect

5707:植入 5707:Implant

5708:解理面 5708: cleavage surface

5710:柵極氧化物 5710: gate oxide

5712:柵極材料 5712: Gate material

5714:頂部和側邊柵極 5714: Top and Side Gates

5716:氧化物 5716:Oxide

5720:柵極觸點 5720:Gate contact

5722:電晶體終端觸點 5722: Transistor terminal contacts

5724:直通穿孔 5724: Straight through perforation

5800:N-晶圓 5800:N-Wafer

5802:遮罩氧化物 5802: mask oxide

5804:N+層 5804: N+ layers

5805:CMP和等離子蝕刻抑制層 5805: CMP and Plasma Etch Inhibitors

5806:金屬互連層 5806: metal interconnect layer

5808:電晶體溝道元件 5808: Transistor channel element

5810:柵極氧化物 5810: gate oxide

5812:柵極材料 5812: Gate material

5814:頂部和側邊柵極 5814: Top and Side Gates

5816:低溫氧化物 5816: low temperature oxide

5820:柵極觸點 5820:Gate contact

5822:溝道終端觸點 5822: Trench termination contacts

5824:直通穿孔 5824: Straight through hole

5902:電晶體矽層 5902: Transistor silicon layer

5904:觸點 5904: contact

5905:下穿孔 5905: Lower perforation

5906:上穿孔 5906: upper perforation

5907:穿孔 5907: perforation

5908:穿孔 5908: perforation

5909:穿孔 5909: perforation

5910:第一金屬層 5910: first metal layer

5912:金屬線 5912: metal wire

5914:金屬線 5914: metal wire

5916:金屬線 5916: metal wire

5918:金屬線 5918: metal wire

5920:金屬線 5920: metal wire

5922:鍵合 5922: Bonding

6000:直通矽穿孔 6000: TSV

6001:穿孔 6001: perforation

6002:穿孔 6002: perforation

6003:穿孔 6003: perforation

6004:穿孔 6004: perforation

6005:穿孔 6005: perforation

6006:穿孔 6006: perforation

6007:穿孔 6007: perforation

6008:穿孔 6008: perforation

6009:穿孔 6009: perforation

6010:觸點 6010: contact

6011:金屬線 6011: metal wire

6012:金屬線 6012: metal wire

6013:金屬線 6013: metal wire

6014:金屬線 6014: metal wire

6015:金屬 6015: metal

6016:金屬層 6016: metal layer

6017:金屬 6017: metal

6018:金屬線 6018: metal wire

6019:金屬層 6019: metal layer

6020:金屬層 6020: metal layer

6022:PMOS層轉移矽 6022: PMOS layer transfer silicon

6024:第一單晶或多晶矽設備層 6024: First monocrystalline or polycrystalline silicon device layer

6100:N-晶圓 6100: N-Wafer

6102:氧化物 6102: oxide

6103:N+底層 6103: N+ bottom layer

6104:N+頂層 6104: N+ top layer

6105:蝕刻硬掩模層 6105: Etching the hard mask layer

6106:互連金屬晶片或條 6106: Interconnecting metal wafers or strips

6107:植入 6107:Implanted

6108:無結晶體管溝道 6108: Junctionless Transistor Channel

6109:解理面 6109: cleavage surface

6110:柵極氧化物 6110: gate oxide

6112:柵極材料 6112: Gate material

6114:頂部和側邊柵極 6114: Top and Side Gates

6116:氧化物 6116: oxide

6120:柵極觸點 6120:Gate contact

6122:電晶體源極/漏極終端觸點 6122: Transistor source/drain terminal contacts

6124:直通穿孔 6124: Straight through hole

6150:光致抗蝕劑 6150: photoresist

6151:源極 6151: source

6152:漏極 6152: drain

6153:溝道 6153: channel

6200:電晶體隔離氧化物 6200: Transistor isolation oxide

6201:PMOS電晶體 6201: PMOS transistor

6202:NMOS電晶體 6202: NMOS transistor

6203:輸入A 6203: Input A

6204:輸入B 6204: Input B

6211:PMOS源極 6211: PMOS source

6212:PMOS B漏極 6212: PMOS B drain

6213:NMOS漏極 6213: NMOS drain

6214:PMOS金屬2 6214: PMOS metal 2

6215:PMOS金屬1 6215: PMOS metal 1

6216:V+供應金屬 6216: V+ supply metal

6217:輸出Y金屬 6217: output Y metal

6218:接地線 6218: Ground wire

6220:NMOS A漏極 6220: NMOS A drain

6300:電晶體隔離氧化物 6300: Transistor isolation oxide

6301:PMOS電晶體 6301: PMOS transistor

6302:NMOS電晶體 6302: NMOS transistor

6303:輸入A至PMOS和NMOS柵極A結點 6303: Input A to PMOS and NMOS gate A junction

6311:PMOS電晶體源極 6311: PMOS transistor source

6312:NMOS H源極 6312: NMOS H source

6313:PMOS漏極 6313: PMOS drain

6314:PMOS金屬2 6314: PMOS metal 2

6315:輸出Y供應金屬 6315: output Y supply metal

6316:V+供應金屬 6316: V+ supply metal

6317:P+至N+觸點 6317: P+ to N+ contact

6318:接地線 6318: Ground wire

6320:NMOS A源極和NMOS B漏極結點 6320: NMOS A source and NMOS B drain junctions

6400:電晶體隔離氧化物 6400: Transistor isolation oxide

6401:PMOS電晶體 6401: PMOS transistor

6402:NMOS電晶體 6402: NMOS transistor

6403:輸入A碎片至PMOS A柵極和NMOS A柵極 6403: Input A fragment to PMOS A gate and NMOS A gate

6411:PMOS H電晶體源極 6411: PMOS H transistor source

6412:NMOS源極碎片至地面 6412: NMOS source fragment to ground

6413:NMOS源極結點 6413: NMOS source node

6414:STI上的柵極至ST上觸點的柵極 6414: Gate on STI to gate on contact on ST

6415:NMOS金屬-2 6415: NMOS Metal-2

6416:V+供應金屬 6416: V+ supply metal

6417:P+至N+至PMOS金屬-2觸點 6417: P+ to N+ to PMOS metal-2 contact

6418:NMOS金屬-1線 6418: NMOS metal-1 line

6420:PMOS H漏極結點 6420: PMOS H-drain junction

6421:PMOS金屬2 6421: PMOS metal 2

6501:施主晶圓氧化層 6501: Donor Wafer Oxide

6503:N+層 6503: N+ layers

6504:柵極電介質 6504: gate dielectric

6505:柵極金屬 6505: Gate metal

6506:氧化物隔離 6506: Oxide isolation

6508:氧化物 6508: oxide

6510:觸點開口 6510: contact opening

6700:p-矽圓片 6700: p-silicon wafer

6701:氧化層 6701: oxide layer

6702:N+層 6702: N+ layers

6703:P-層 6703: P-layer

6704:植入氫層 6704: implanted hydrogen layer

6705:氧化物隔離區 6705: Oxide isolation area

6706:凹陷溝道 6706: Recessed channel

6707:柵極電介質 6707: Gate dielectric

6708:柵極 6708:Gate

6709:低溫氧化物 6709: low temperature oxide

6710:觸點 6710: contact

6800:p-矽圓片 6800:p-silicon wafer

6801:氧化物 6801: oxide

6802:N+層 6802: N+ layers

6803:P-層 6803: P-layer

6804:氫植入 6804: Hydrogen Implantation

6805:氧化物隔離區 6805: oxide isolation area

6806:間隔沉澱 6806: interval precipitation

6807:球形凹處 6807: Spherical recess

6808:柵極電介質 6808: Gate Dielectric

6809:金屬柵極 6809: metal grid

6810:氧化物 6810:Oxide

6811:觸點 6811: contact

6920:複製施主晶圓對準標記 6920: Duplicate Donor Wafer Alignment Marks

6920C:最近施主晶圓對準標記 6920C: Nearest Donor Wafer Alignment Mark

6922:南北未對準 6922:North-south misalignment

7000:施主晶圓 7000: Donor Wafers

7001:矽層 7001: silicon layer

7002:隔離 7002: Isolation

7003:敏感柵極區 7003: Sensitive gate area

7004:多晶矽 7004: Polysilicon

7005:柵極氧化物 7005: gate oxide

7006:NMOS源極和漏極 7006: NMOS source and drain

7007:PMOS源極和漏極 7007: PMOS source and drain

7008:層間電介質 7008: interlayer dielectric

7010:植入 7010: Implantation

7012:解理面 7012: cleavage surface

7014:載體襯底 7014: carrier substrate

7016:介面 7016: interface

7018:施主晶圓面 7018: Donor Wafer Side

7020:氧化物 7020: oxide

7022:氧化物表面 7022: oxide surface

7001:預處理HKMG矽層 7001: Pretreatment of HKMG silicon layer

7024:金屬條 7024: metal strip

7026:高-k柵極電介質 7026: High-k Gate Dielectric

7028:PMOS特定工作功能金屬柵極 7028: PMOS specific work function metal gate

7030:NMOS特定工作工程金屬柵極 7030: NMOS Job Specific Engineered Metal Gate

7032:鋁充填 7032: aluminum filling

7034:柵極觸點 7034:Gate contact

7036:源極/漏極觸點 7036: Source/Drain Contacts

7040:直通穿孔 7040: Straight through perforation

7050:一種密緻材料的隔離植入抑制層 7050: Isolation Implanted Inhibition Layers of Dense Materials

7052:光致抗蝕劑 7052: photoresist

7104:p型電晶體行寬重複寬度 7104: p-type transistor row width repetition width

7106:p型電晶體行寬重複寬度Wp 7106: p-type transistor row width repetition width Wp

7108:總重複W 7108: total repeat W

7110:電晶體隔離 7110: Transistor isolation

7112:電晶體源極 7112: Transistor source

7113:PMOS柵極 7113: PMOS gate

7114:電晶體漏極 7114: transistor drain

7116:電晶體源極 7116: Transistor source

7117:NMOS柵極 7117: NMOS gate

7118:電晶體漏極 7118: transistor drain

7202:隔離區 7202: Quarantine

7215:置換柵極 7215: replacement gate

7218:柵極觸點著陸區 7218: Gate Contact Landing Area

7220:柵極連接 7220: Gate connection

7222:源極連接 7222: source connection

7224:漏極連接 7224: drain connection

7240:層間穿孔連接 7240: Interlayer perforated connection

7302:充氣投影 7302: inflatable projection

7304:Wy 7304:Wy

7306:Wx 7306:Wx

7308:Rdx 7308:Rdx

7502:直通穿孔 7502: Straight through perforation

7504:矩形著陸區 7504: Rectangular Landing Area

7602:Wv 7602:Wv

7604:Wn 7604:Wn

7606:Wp 7606:Wp

7610:電晶體隔離 7610: Transistor isolation

7612,7614:有效面積 7612,7614: effective area

7616:共用隔離區 7616: Shared Quarantine

7618:層到層穿孔溝道 7618: layer-to-layer perforation channel

7622,7622B:柵極 7622, 7622B: gate

77A02:直通穿孔 77A02: Through hole

77A04,77A06:著陸帶 77A04,77A06: Landing Strip

7802:Wv 7802:Wv

7804:Wy 7804:Wy

7806:Wx 7806:Wx

7810:電晶體隔離 7810: Transistor isolation

7900:著陸條寬度增加值 7900: Landing strip width increase value

8000:室內晶圓晶片 8000:Indoor Wafer Wafer

8002:一般連通性結構 8002: General Connectivity Structure

8004:非重複結構 8004: non-repeating structure

8006:最大施主晶圓至受主晶圓在東西方向上的未對準(Mx) 8006: Maximum Donor Wafer to Acceptor Wafer Misalignment in East-West Direction (Mx)

8008:最大施主晶圓至受主晶圓在南北方向上的未對準(Mx) 8008: Maximum Donor Wafer to Acceptor Wafer Misalignment in North-South Direction (Mx)

8010:受主晶圓南北著陸條 8010: Acceptor Wafer North-South Landing Strips

8011:施主晶圓東西著陸條 8011: Donor Wafer East-West Landing Strip

8012:直通層穿孔 8012: Straight through layer perforation

8100:施主晶圓 8100: Donor Wafer

8102:施主晶圓面 8102: Donor Wafer Side

8104:氧化物 8104:Oxide

8106:氧化物表面 8106: oxide surface

8124:金屬條 8124: metal strip

8128:直通穿孔 8128: Straight through hole

8130:STI(淺溝槽隔離)隔離 8130: STI (shallow trench isolation) isolation

8136:氧化物 8136:Oxide

8140:觸點 8140: contact

8150:金屬線 8150: metal wire

8160:柵極氧化物 8160: gate oxide

8162:柵極材料 8162: gate material

8170:完全耗盡SOI電晶體結 8170: Fully depleted SOI transistor junction

8171:完全耗盡SOI電晶體結 8171: Fully depleted SOI transistor junction

8202:虛擬柵極電晶體 8202: dummy gate transistor

8206:第一片施主晶圓 8206:First donor wafer

8208:解理線 8208: cleavage line

8216:植入 8216:Implanted

8218:第二條解理線 8218: The second cleavage line

8226:第二片施主晶圓 8226: Second donor wafer

8232:表面 8232: surface

8246:植入 8246:Implanted

8300:施主晶圓 8300: Donor Wafer

8301:掩埋氧化物(BOX) 8301: buried oxide (BOX)

8302:薄矽層 8302: thin silicon layer

8303:電晶體間隔離 8303: Isolation between transistors

8304:多晶矽 8304: polysilicon

8305:柵極氧化物 8305: gate oxide

8306:NMOS源極和漏極 8306: NMOS source and drain

8307:NMOS電晶體溝道 8307: NMOS transistor channel

8308:NMOS層間電介質(ILD) 8308: NMOS Interlayer Dielectric (ILD)

8310:原子類植入 8310:Atomic Class Implantation

8312:解理面 8312: cleavage surface

8314:施主晶圓表面 8314: Donor Wafer Surface

8316:氧化層 8316: oxide layer

8320:載體晶圓 8320: carrier wafer

8321:解理面 8321: cleavage surface

8322:表面 8322: surface

8333:電晶體間隔離 8333: Isolation between transistors

8334:多晶矽 8334: polysilicon

8335:柵極氧化物 8335: gate oxide

8336:PMOS源極和漏極 8336: PMOS source and drain

8337:PMOS電晶體溝道 8337: PMOS transistor channel

8338:PMOS層間電介質(ILD) 8338: PMOS Interlayer Dielectric (ILD)

8339:電介質層 8339: dielectric layer

8340:原子類植入 8340:Atomic class implantation

8341:PMOS特定工作功能金屬柵極 8341: PMOS specific work function metal gate

8342:鋁充填 8342: aluminum filling

8343:柵極觸點和金屬化 8343: Gate Contacts and Metallization

8344:源極和漏極觸點和金屬化 8344: Source and drain contacts and metallization

8347:PMOS層至NMOS層穿孔 8347: PMOS layer to NMOS layer through hole

8348:氧化層 8348: oxide layer

8350:金屬著陸條 8350:Metal landing strip

8360:NMOS高-k柵極電介質 8360: NMOS High-k Gate Dielectric

8361:NMOS特定工作工程金屬柵極 8361: NMOS Job Specific Engineered Metal Gate

8362:鋁充填 8362: aluminum filling

8363:柵極觸點和金屬化 8363: Gate Contacts and Metallization

8364:源極和漏極觸點和金屬化 8364: Source and Drain Contacts and Metallization

8367:NMOS層至PMOS層穿孔 8367: NMOS layer to PMOS layer through hole

8369:電介質層 8369: dielectric layer

8370:電介質層 8370: dielectric layer

8372:層到層直通穿孔 8372: Layer-to-layer through hole

83L00:重複通用單元 83L00: Duplicate common units

83L04:NMOS電晶體 83L04: NMOS transistor

83L05:共用擴散 83L05: Shared Diffusion

83L02:PMOS電晶體 83L02: PMOS transistor

83L10:電晶體柵極 83L10: Transistor gate

83L12,83L20:穿孔 83L12, 83L20: Perforation

83L06:Vdd電源線 83L06: Vdd power line

83L08:擴散連接 83L08: Diffusion connection

83L17:朝下通用金屬結構 83L17: General purpose metal construction facing down

83L14,83L16,83L18:通孔 83L14, 83L16, 83L18: through hole

83L22,83L24:NMOS電晶體觸點 83L22, 83L24: NMOS transistor contacts

83L26:客戶金屬 83L26: Customer metal

83L25:Vss電源線 83L25: Vss power line

8402:重複邏輯圖案 8402: repeat logic pattern

8404:街區 8404: block

8420:SRAM單元 8420:SRAM cell

8422,8438,8452:字線 8422, 8438, 8452: word line

8424,8426,8436,8462:位線 8424,8426,8436,8462: bit lines

8430:連續陣列 8430: continuous array

8432:存儲模組 8432: storage module

8434:蝕刻單元 8434: etching unit

8450,8460:邏輯結構 8450,8460: logical structure

8468:讀取感應電路 8468: read sensing circuit

8502:柵極氧化物 8502: gate oxide

8504:柵極材料 8504: gate material

8506:柵極堆疊 8506: gate stack

8508:電介質 8508: Dielectric

8510:本地觸點 8510: local contact

8512:層到層觸點 8512: layer to layer contacts

8516:金屬化 8516: metallization

8520:氧化層 8520: oxide layer

8522:觸點 8522: contact

8536:金屬線 8536: metal wire

8550:頂部電晶體 8550: top transistor

8552:頂部電晶體 8552: top transistor

8602:邏輯層 8602: logic layer

8612:邏輯層 8612: logic layer

8622:邏輯層 8622: logic layer

8632:修復邏輯層 8632: Fix logic layer

86C02:基底天線 86C02: Base Antenna

86C04:RF至DC轉換電路 86C04: RF to DC conversion circuit

86C06:電源裝置 86C06: power supply unit

86C08:三維積體電路 86C08: Three-dimensional integrated circuits

86C10:太陽能電池 86C10: solar cell

86C12:微控制單元 86C12: Micro control unit

86C14:無線電模組 86C14: Radio Module

8702:觸發器 8702: Trigger

8704:正常輸出 8704: normal output

8706:分支 8706: branch

8708:修復輸入 8708: Fix input

8710:控制 8710: control

8712:正常輸入 8712: normal input

8714:複用器 8714: multiplexer

8801:P-型晶圓 8801:P-type wafer

8802:N+層 8802: N+ layers

8803:氫面 8803: hydrogen surface

8804:臨時載體 8804: temporary carrier

8805:氧化物 8805:Oxide

8806:週邊電路 8806: peripheral circuit

8807:表面 8807: surface

8808:柵電極 8808: Gate electrode

8809:柵極電介質 8809: Gate Dielectric

8810:氧化層 8810: oxide layer

8811:第一RCAT層 8811: The first RCAT layer

8812:第二RCAT層 8812: The second RCAT layer

8813:高摻雜多晶矽 8813:Highly doped polysilicon

8814:源極線 8814: source line

8815:位線 8815: bit line

8816:柵極 8816:Gate

8817:P-層 8817:P-layer

8818:P-層 8818:P-layer

8902:位線(BL) 8902: bit line (BL)

8903:源極線(SL) 8903: Source line (SL)

8904:字線(WL) 8904: word line (WL)

8905:氧化物隔離區 8905: oxide isolation area

8906:p-層 8906: p-layer

8907:WL 8907:WL

8908:WL接線 8908: WL Wiring

8909:SL接線8909 8909: SL Wiring 8909

8910:BL接線 8910: BL wiring

9001:P-型晶圓 9001:P-type wafer

9002:n+外延層 9002: n+ epitaxial layer

9003:p-外延層 9003:p-Epitaxial layer

9004:氧化層 9004: oxide layer

9005:氫面 9005: hydrogen surface

9006:週邊電路 9006: peripheral circuit

9007:氧化物 9007:Oxide

9008:柵電極 9008: Gate electrode

9009:柵極電介質 9009: Gate dielectric

9010:氧化層 9010: oxide layer

9011:第一RCAT層 9011: The first RCAT layer

9012:第二RCAT層 9012: The second RCAT layer

9013:高摻雜多晶矽 9013: Highly doped polysilicon

9014:源極線 9014: source line

9015:位線 9015: bit line

9016:柵電極 9016: Gate electrode

9101:SOI p-晶圓 9101:SOI p-wafer

9102:淺溝槽隔離區 9102: shallow trench isolation

9103:柵極溝槽 9103: gate trench

9104:柵電極 9104: Gate electrode

9105:柵極電介質層 9105: gate dielectric layer

9106:源極和漏極n+區 9106: source and drain n+ regions

9107:層間電介質 9107: interlayer dielectric

9108:P-型晶圓 9108:P-type wafer

9109:氧化物 9109:Oxide

9110:氫面 9110: hydrogen surface

9113:RCAT層 9113: RCAT layer

9114:RCAT層 9114: RCAT layer

9115:通孔 9115: Through hole

9116:位線BLs 9116: bit line BLs

9117:源極線SLs 9117: source line SLs

9118:週邊電路 9118: peripheral circuit

9119:掩埋氧化層 9119: buried oxide layer

9201:P-型晶圓 9201:P-type wafer

9202:氧化層 9202: oxide layer

9203:氫面 9203: hydrogen surface

9204:週邊電路 9204: peripheral circuit

9205:柵電極 9205: gate electrode

9206:氧化層 9206: oxide layer

9207:柵極電介質 9207: gate dielectric

9208:源極/漏極區 9208: source/drain region

9209:第二PD-SOI電晶體層 9209: Second PD-SOI transistor layer

9210:穿孔 9210: perforation

9211:位線 9211: bit line

9212:源極線 9212: source line

9213:電晶體柵極 9213: Transistor gate

9302:第一片晶圓 9302: first wafer

9303:電路 9303: circuit

9304:第二片晶圓 9304: Second wafer

9305:電路 9305: circuit

9306:薄晶圓 9306: thin wafer

9310:解理面 9310: cleavage surface

9312:薄層 9312: thin layer

9322:鍵合結構 9322: Bonding structure

9402:金屬著陸條 9402: Metal landing strip

9403:附加金屬條的未用可能房間 9403: Unused possible room for additional metal bars

9406:長度 9406: Length

9412:著陸帶 9412:Landing strip

9413:著陸帶 9413:Landing strip

9432:A行穿孔 9432: A row perforation

9433:B行穿孔 9433: B line perforation

9436:通孔 9436: Through hole

9438:金屬條 9438: metal strip

9500:P-襯底 9500:P-substrate

9501:氧化物 9501: oxide

9502:氧化物 9502: oxide

9503:N+摻雜晶圓大小層 9503: N+ doped wafer size layer

9503':N+層 9503': N+ layers

9504:P-摻雜晶圓大小層 9504: P-doped wafer size layer

9506:P+摻雜晶圓大小層 9506: P+ doped wafer size layer

9507:氫植入 9507: Hydrogen Implantation

9508:N-摻雜晶圓大小層 9508: N-doped wafer size layer

9510:受主晶圓 9510: acceptor wafer

9511:柵極氧化物 9511: Gate Oxide

9512:柵極氧化物 9512: gate oxide

9513:N+摻雜區 9513: N+ doped area

9514:P-摻雜區 9514:P-doped region

9516:P+摻雜區 9516: P+ doping area

9518:N-摻雜區 9518: N-doped region

9520:電晶體隔離區 9520: Transistor isolation area

9526:P+源極和漏極區 9526:P+ source and drain regions

9528:N-電晶體溝道區 9528: N-transistor channel region

9533:N+源極和漏極區 9533: N+ source and drain regions

9534:P-電晶體溝道區 9534: P-transistor channel region

9542:p-RCAT凹陷溝道 9542: p-RCAT recessed channel

9544:n-RCAT凹陷溝道 9544: n-RCAT recessed channel

9550:氧化物 9550: oxide

9552:氧化物 9552:Oxide

9554':p-RCAT柵電極 9554': p-RCAT gate electrode

9556':n-RCAT柵電極 9556': n-RCAT gate electrode

9562:n-RCAT源極觸點 9562: n-RCAT source contact

9564:n-RCAT柵極觸點 9564: n-RCAT gate contact

9566:n-RCAT漏極觸點 9566: n-RCAT drain contact

9572:p-RCAT源極觸點 9572: p-RCAT source contact

9574:p-RCAT柵極觸點 9574: p-RCAT gate contact

9576:p-RCAT漏極觸點 9576:p-RCAT Drain Contact

9599:層轉移劃分面 9599:Layer transfer division plane

9600:施主晶圓 9600: Donor Wafer

9602:N+摻雜矽層 9602: N+ doped silicon layer

9604:n+SiGe層 9604: n+SiGe layer

9606:N+摻雜矽層 9606: N+ doped silicon layer

9608:n+SiGe層 9608: n+SiGe layer

9610:受主晶圓 9610: acceptor wafer

9611:柵極電介質 9611: Gate Dielectric

9612:柵極材料 9612: Gate material

9613:氧化物 9613:Oxide

9614:氧化物 9614:Oxide

9616:n+SiGe區 9616:n+SiGe area

9618:N+矽區 9618: N+ silicon area

9620:氧化物 9620: oxide

9622:氧化物 9622:Oxide

9630:共同柵極區 9630: common gate area

9636:電晶體柵極溝道 9636: Transistor gate channel

9699:層轉移劃分面 9699: layer transfer divide plane

9702:多餘孔 9702: extra holes

9704:源極 9704: source

9706:柵極 9706:Gate

9708:漏極 9708: drain

9710:源極 9710: source

9712:柵極 9712:Gate

9714:漏極 9714: drain

9716:掩埋氧化物 9716: buried oxide

9718:掩埋氧化物 9718: buried oxide

9720:浮體區 9720: Floating body area

9730:電流差動 9730: current differential

9734:漏極電流 9734: Drain current

9736:柵極電壓 9736: Gate voltage

9800:P-襯底 9800:P-substrate

9801:氧化物 9801:Oxide

9802:氧化物 9802:Oxide

9804:P-層 9804:P-layer

9804':剩餘P-摻雜層 9804': remaining P-doped layer

9807:氫植入 9807: Hydrogen Implantation

9810:受主晶圓 9810: acceptor wafer

9820:電晶體源極和漏極 9820: Transistor source and drain

9824:柵極堆疊 9824: gate stack

9828:NMOS電晶體溝道 9828: NMOS transistor channel

9830:第二層 9830: second floor

9834:柵極堆疊 9834:Gate stack

9840:位線(BL)觸點 9840: Bit Line (BL) Contacts

9842:源極線(SL)觸點 9842: Source Line (SL) Contacts

9846:源極線(SL)接線 9846: Source Line (SL) Wiring

9848:位線(BL)接線 9848: Bit line (BL) wiring

9850:氧化物 9850:Oxide

9852:電晶體源極側的N+區 9852: N+ region on the source side of the transistor

9854:電晶體漏極側的N+區 9854: N+ region on the drain side of the transistor

9864:WL接線 9864: WL Wiring

9865:SL接線 9865: SL Wiring

9866:BL接線 9866: BL Wiring

9899:層轉移劃分面 9899:Layer transfer division plane

9902:週邊電路襯底 9902: Peripheral circuit substrate

9904:氧化物 9904:Oxide

9906:P-襯底 9906:P-substrate

9906':剩餘P-層 9906': remaining P-layer

9908:氧化物 9908:Oxide

9910:層轉移劃分面 9910: layer transfer division plane

9912:施主晶圓 9912: Donor Wafer

9914:受主晶圓 9914: acceptor wafer

9916:N+矽區 9916: N+ silicon area

9916':N+矽區 9916': N+ silicon area

9918:p-矽區 9918:p-silicon region

9918':p-矽區 9918': p-silicon region

9920:氧化層 9920: oxide layer

9922:第一Si/SiO2層 9922: The first Si/SiO2 layer

9924:第二矽/二氧化矽層 9924: Second silicon/silicon dioxide layer

9926:第三Si/SiO2層 9926: The third Si/SiO2 layer

9928:柵極電介質區 9928: Gate Dielectric Region

9929:氧化層 9929: oxide layer

9930:柵電極 9930: Gate electrode

9932:氧化物 9932:Oxide

9934:位線(BL)觸點 9934: Bit Line (BL) Contacts

9936:BL金屬線 9936: BL metal wire

9950:字線區(WL) 9950: word line area (WL)

9952:源極線區(SL) 9952: Source line area (SL)

10002:週邊電路襯底 10002: Peripheral circuit substrate

10004:氧化物 10004:Oxide

10006:P-襯底 10006:P-substrate

10006':剩餘P-層 10006': remaining P-layer

10008:氧化物 10008:Oxide

10010:層轉移劃分面 10010: layer transfer division surface

10012:施主晶圓 10012: Donor Wafer

10014:受主晶圓 10014: acceptor wafer

10016:p-矽區 10016:p-silicon area

10017:p-矽區 10017:p-silicon area

10020:氧化層 10020: oxide layer

10022:氧化物 10022: oxide

10023:第一Si/SiO2層 10023: first Si/SiO2 layer

10025:第二矽/二氧化矽層 10025: Second silicon/silicon dioxide layer

10026:N+矽區 10026: N+ silicon area

10027:第三Si/SiO2層 10027: The third Si/SiO2 layer

10028:柵極電介質區 10028: Gate Dielectric Region

10029:氧化層 10029: oxide layer

10030:柵電極 10030: Gate electrode

10032:氧化物 10032:Oxide

10034:位線(BL)觸點 10034: bit line (BL) contact

10036:BL金屬線 10036:BL metal wire

10050:字線區(WL) 10050: word line area (WL)

10052:源極線區(SL) 10052: Source line area (SL)

10102:週邊電路襯底 10102: Peripheral circuit substrate

10104,10122,10132:氧化物 10104, 10122, 10132: Oxide

10114:受主晶圓 10114: acceptor wafer

10112:施主晶圓 10112: Donor Wafer

10106:N+襯底 10106: N+ substrate

10110:層轉移劃分面 10110: layer transfer division plane

10106':剩餘N+層 10106': remaining N+ layers

10108,10120,10129:氧化層 10108, 10120, 10129: oxide layer

10123:第一Si/SiO2層 10123: first Si/SiO2 layer

10125:第二矽/二氧化矽層 10125: Second silicon/silicon dioxide layer

10127:第三Si/SiO2層 10127: The third Si/SiO2 layer

10126:N+矽區 10126: N+ silicon area

10128:柵極電介質區 10128: gate dielectric region

10130:柵電極 10130: Gate electrode

10150:字線區(WL) 10150: word line area (WL)

10152:源極線區(SL) 10152: Source line area (SL)

10134:位線(BL)觸點 10134: Bit line (BL) contact

10138:電阻改變型記憶體材料 10138: resistance change memory material

10136:BL金屬線 10136:BL metal wire

10202:週邊電路襯底 10202: Peripheral circuit substrate

10204:氧化物 10204: oxide

10206:P-襯底 10206:P-substrate

10206':P-層 10206': P-layer

10208:氧化物 10208: oxide

10210:層轉移劃分面 10210: layer transfer division surface

10212:施主晶圓 10212: Donor Wafer

10214:受主晶圓 10214: acceptor wafer

10216:p-矽區 10216:p-silicon region

10217:p-矽區 10217:p-silicon region

10220:氧化層 10220: oxide layer

10222:氧化區 10222: oxidation zone

10223:第一Si/SiO2層 10223: the first Si/SiO2 layer

10225:第二矽/二氧化矽層 10225: Second silicon/silicon dioxide layer

10226:N+矽區 10226: N+ silicon area

10227:第三Si/SiO2層 10227: The third Si/SiO2 layer

10228:柵極電介質區 10228: gate dielectric region

10229:氧化層 10229: oxide layer

10230:柵電極 10230: gate electrode

10232:氧化物 10232: oxide

10234:位線(BL)觸點 10234: Bit line (BL) contact

10236:BL金屬線 10236:BL metal wire

10238:電阻改變材料 10238: resistance change material

10250:字線區(WL) 10250: word line area (WL)

10252:源極線區(SL) 10252: Source line area (SL)

10302:週邊電路襯底 10302: Peripheral circuit substrate

10304:氧化物 10304: oxide

10306:P-襯底 10306:P-substrate

10306':P-層 10306': P-layer

10308:氧化物 10308: oxide

10310:層轉移劃分面 10310: layer transfer division plane

10312:施主晶圓 10312: Donor Wafer

10314:受主晶圓 10314: acceptor wafer

10316:N+矽區 10316: N+ silicon area

10316':N+矽區 10316': N+ silicon area

10318:p-矽區 10318:p-silicon region

10318':p-矽區 10318':p-silicon region

10320:氧化層 10320: oxide layer

10322:氧化區 10322: oxidation zone

10323:第一Si/SiO2層 10323: first Si/SiO2 layer

10325:第二矽/二氧化矽層 10325: Second silicon/silicon dioxide layer

10326:N+矽區 10326: N+ silicon area

10327:第三Si/SiO2層 10327: The third Si/SiO2 layer

10328:柵極電介質區 10328: gate dielectric region

10329:氧化層 10329: oxide layer

10330:柵電極 10330: gate electrode

10332:氧化物 10332:Oxide

10334:位線(BL)觸點 10334: Bit line (BL) contact

10336:BL金屬線 10336: BL metal wire

10338:電阻改變材料 10338: resistance change material

10350:字線區(WL) 10350: word line area (WL)

10352:源極線區(SL) 10352: source line area (SL)

10400:施主晶圓 10400: Donor Wafer

10401:氧化物 10401: oxide

10402:氧化物 10402: oxide

10404:P-層 10404:P-layer

10404':P-摻雜層 10404': P-doped layer

10407:氫植入 10407: Hydrogen Implantation

10410:受主晶圓 10410: acceptor wafer

10420:電晶體源極和漏極 10420: Transistor source and drain

10424:柵極堆疊 10424: gate stack

10428:P-矽NMOS電晶體溝道 10428: P-silicon NMOS transistor channel

10430:存儲電晶體第二層 10430: The second layer of storage transistor

10434:源極線(SL)觸點 10434: Source Line (SL) Contact

10440:位線(BL)觸點 10440: Bit line (BL) contact

10442:電阻改變型記憶體材料 10442: resistance change memory material

10446:源極線(SL)接線 10446: Source Line (SL) Wiring

10448:位線(BL)接線 10448: Bit line (BL) wiring

10450:氧化物 10450: oxide

10452:電晶體源極側的N+區 10452: N+ region on the source side of the transistor

10454:電晶體漏極側的N+區 10454: N+ region on the drain side of the transistor

10499:層轉移劃分面 10499: layer transfer division plane

10500:施主晶圓 10500: Donor Wafer

10501:氧化物 10501: oxide

10502:氧化物 10502: oxide

10504:P-摻雜層 10504: P-doped layer

10504':P-摻雜層 10504': P-doped layer

10507:氫植入 10507: Hydrogen implantation

10510:受主晶圓 10510: acceptor wafer

10520:P-摻雜區 10520:P-doped region

10522:電荷捕捉柵極電介質 10522: Charge Trapping Gate Dielectric

10524:柵極金屬材料 10524: gate metal material

10528:柵極堆疊 10528: gate stack

10530:NAND串源極和漏極終端 10530: NAND string source and drain termination

10534:電晶體間源極和漏極 10534: source and drain between transistors

10542:存儲電晶體第一層 10542: The first layer of storage transistor

10544:存儲電晶體第二層 10544: The second layer of storage transistor

10548:源極線(SL)接地觸點 10548: Source Line (SL) Ground Contact

10549:位線觸點 10549: bit line contact

10550:氧化物 10550: oxide

10599:層轉移劃分面 10599: layer transfer division surface

10602:週邊電路襯底 10602: Peripheral circuit substrate

10604:氧化物 10604: oxide

10606:N+襯底 10606: N+ substrate

10606':N+層 10606': N+ layers

10608:氧化物 10608:Oxide

10610:層轉移劃分面 10610: layer transfer division surface

10612:施主晶圓 10612: Donor Wafer

10614:受主晶圓 10614: acceptor wafer

10620:氧化層 10620: oxide layer

10622:氧化區 10622: oxidation zone

10623:第一Si/SiO2層 10623: first Si/SiO2 layer

10625:第二矽/二氧化矽層 10625: Second silicon/silicon dioxide layer

10626:N+矽區 10626: N+ silicon area

10627:第三Si/SiO2層 10627: The third Si/SiO2 layer

10628:柵極電介質區 10628: gate dielectric region

10629:氧化物 10629:Oxide

10630:柵極金屬電極區 10630:Gate metal electrode area

10632:氧化物 10632:Oxide

10634:選擇柵極觸點 10634: select gate contact

10636:NAND串區 10636: NAND serial area

10638:選擇柵極區 10638: select gate area

10644:源極區 10644: source area

10646:選擇金屬線 10646: Select metal wire

10652:位線區(BL) 10652: bit line area (BL)

10700:施主晶圓 10700: Donor Wafer

10701:氧化物 10701: oxide

10702:氧化物 10702: oxide

10704:P-摻雜層 10704: P-doped layer

10704':P-摻雜層 10704': P-doped layer

10707:氫植入 10707: Hydrogen Implantation

10710:受主晶圓 10710: acceptor wafer

10720:P-摻雜區 10720:P-doped region

10722:隧道氧化物 10722: tunnel oxide

10722':隧道氧化物區 10722': tunnel oxide region

10724:FG柵極金屬材料 10724: FG gate metal material

10724':FG柵極金屬區 10724': FG gate metal area

10725:多晶矽間氧化物層 10725: interpolysilicon oxide layer

10725':多晶矽間氧化物區 10725': Inter-poly oxide region

10726:控制柵極(CG)柵極金屬材料 10726: Control gate (CG) gate metal material

10726':CG柵極金屬區 10726': CG gate metal area

10728:柵極堆疊 10728: gate stack

10730:NAND串源極和漏極終端 10730: NAND string source and drain termination

10734:電晶體間源極和漏極 10734: source and drain between transistors

10742:存儲電晶體第一層 10742: The first layer of storage transistor

10744:存儲電晶體第二層 10744: The second layer of storage transistor

10748:源極線(SL)接地觸點 10748: Source Line (SL) Ground Contact

10749:位線觸點 10749: bit line contact

10750:氧化物 10750: oxide

10799:層轉移劃分面 10799: layer transfer division surface

10802:週邊電路襯底 10802: Peripheral circuit substrate

10804:氧化物 10804:Oxide

10806:N+襯底 10806: N+ substrate

10806':N+層 10806': N+ layers

10808:氧化物 10808:Oxide

10810:層轉移劃分面 10810: layer transfer division surface

10812:施主晶圓 10812: Donor Wafer

10814:受主晶圓 10814: acceptor wafer

10816:N+區 10816: N+ area

10818:隧道電介質 10818: tunnel dielectric

10823:第一存儲層 10823: The first storage layer

10825:第二存儲層 10825: Second storage layer

10828:FG區 10828: FG area

10829:氧化層 10829: oxide layer

10829':薄氧化物層 10829': thin oxide layer

10838:FG區 10838: FG area

10850:多晶矽間氧化物層 10850: interpolysilicon oxide layer

10852:控制柵極(CG)柵極材料 10852: Control Gate (CG) Gate Material

10902:週邊電路襯底 10902: Peripheral circuit substrate

10904:氧化物 10904: oxide

10906:N+摻雜多晶矽或非晶層 10906: N+ doped polysilicon or amorphous layer

10908:氧化層 10908: oxide layer

10916:結晶N+矽層 10916: Crystalline N+ silicon layer

10920:氧化矽層 10920: silicon oxide layer

10922:氧化區 10922: oxidation zone

10923:第一Si/SiO2層 10923: first Si/SiO2 layer

10925:第二矽/二氧化矽層 10925: Second silicon/silicon dioxide layer

10926:結晶N+矽區 10926: Crystalline N+ silicon region

10927:第三Si/SiO2層 10927: The third Si/SiO2 layer

10928:柵極電介質區 10928: Gate Dielectric Region

10929:氧化物 10929:Oxide

10930:柵電極 10930: Gate electrode

10932:氧化物 10932:Oxide

10934:位線(BL)觸點 10934: Bit Line (BL) Contacts

10936:BL金屬線 10936:BL metal wire

10938:電阻改變型記憶體材料 10938: resistance change memory material

10950:字線區(WL) 10950: word line area (WL)

10952:源極線區(SL) 10952: source line area (SL)

11002:矽襯底 11002: Silicon substrate

11004:氧化層 11004: oxide layer

11006:N+摻雜非晶矽或多晶矽層 11006: N+ doped amorphous silicon or polysilicon layer

11016:結晶N+矽層 11016: Crystalline N+ silicon layer

11020:氧化層 11020: oxide layer

11022:氧化區 11022: oxidation zone

11023:第一Si/SiO2層 11023: the first Si/SiO2 layer

11025:第二矽/二氧化矽層 11025: Second silicon/silicon dioxide layer

11026:結晶N+矽區 11026: Crystalline N+ silicon region

11027:第三Si/SiO2層 11027: The third Si/SiO2 layer

11028:柵極電介質區 11028: gate dielectric region

11029:氧化層 11029: oxide layer

11030:柵電極 11030: gate electrode

11032:氧化物 11032: oxide

11034:位線(BL)觸點 11034: Bit line (BL) contact

11036:BL金屬線 11036:BL metal wire

11038:電阻改變型記憶體材料 11038: resistance change memory material

11050:字線區(WL) 11050: word line area (WL)

11052:源極線區(SL) 11052: Source line area (SL)

11078:週邊電路 11078: peripheral circuit

11100:施主晶圓 11100: Donor Wafer

11100':施主晶圓部分 11100': Donor Wafer Section

11101:鍵合表面 11101: bonding surface

11102:層 11102: layer

11110:受主晶圓 11110: acceptor wafer

11111:鍵合表面 11111: bonding surface

11130:對準視窗 11130: Align the window

11130':對準視窗 11130': alignment window

11131:對準視窗區 11131: Align the window area

11150:施主晶圓設備結構 11150: Donor Wafer Device Structure

11160:直通層穿孔(TLVs) 11160: Through Layer Vias (TLVs)

11180:金屬連接晶片或條 11180: metal connection chip or strip

11190:受主晶圓對準標記 11190: Acceptor Wafer Alignment Mark

11199:層轉移劃分面 11199: layer transfer division surface

11201:互連金屬化層 11201: Interconnect metallization layer

11202:基底 11202: base

11203:薄二氧化矽層 11203: thin silicon dioxide layer

11204:氧化層 11204: oxide layer

11205:均熱片層 11205: Evening layer

11206:施主晶圓襯底 11206: Donor Wafer Substrate

11206':剩餘轉移層 11206': remaining transfer layer

11207:遮罩氧化物 11207: mask oxide

11212:施主晶圓 11212: Donor Wafer

11214:受主晶圓 11214: acceptor wafer

11299:層轉移劃分面 11299: layer transfer division plane

11300:印刷接線板 11300: printed wiring board

11302:電晶體底層 11302: The bottom layer of the transistor

11304:直通層電源和接地穿孔 11304: Thru layer power and ground vias

11305:不導電均熱片層 11305: Non-conductive heat spreader

11306:電晶體頂層電源和接地網 11306: Transistor top layer power supply and ground grid

11307:電晶體底層電源和接地網 11307: Transistor bottom power supply and ground grid

11310:鍵合氧化物 11310: bonded oxide

11312:電晶體頂層 11312: Transistor top layer

11325:包裝均熱片 11325: Packaging soaker

11330:散熱器 11330: Radiator

11360:側壁熱導體 11360: side wall heat conductor

11401:邏輯層 11401: logic layer

11402:邏輯層 11402: logic layer

11405:垂直連接 11405: vertical connection

11406:垂直連接 11406: vertical connection

11411:邏輯錐 11411: logic cone

11412:邏輯錐 11412: logic cone

11421:觸發器 11421: Trigger

11422:觸發器 11422: Trigger

11431:複用器 11431: multiplexer

11432:複用器 11432: multiplexer

11441:控制點 11441: Control point

11442:控制點 11442:Control point

11451:BIST控制器/檢測器 11451: BIST Controller/Detector

11452:BIST控制器/檢測器 11452: BIST Controller/Detector

11501:層 11501: layer

11502:層 11502: layer

11503:層 11503: layer

11511-1:邏輯錐 11511-1: Logic Cone

11511-2:邏輯錐 11511-2: Logic Cone

11511-3:邏輯錐 11511-3: Logic Cone

11521-1:觸發器 11521-1: Trigger

11521-2:觸發器 11521-2: Trigger

11521-3:觸發器 11521-3: Trigger

11531:多數表決電路 11531: Majority Voting Circuit

11541-1:最終容錯FF輸出 11541-1: Final fault tolerant FF output

11541-2:最終容錯FF輸出 11541-2: Final fault tolerant FF output

11541-3:最終容錯FF輸出 11541-3: Final fault tolerant FF output

11551:本地FF輸出 11551: Local FF output

11552:FF輸出值 11552: FF output value

11553:FF輸出值 11553: FF output value

11600:二維積體電路ASIC 11600: Two-dimensional integrated circuit ASIC

11610:掃描測試控制器 11610: Scan Test Controller

11612:多個觸發器 11612: Multiple triggers

11614:多個觸發器 11614: Multiple triggers

11616:多個觸發器 11616: Multiple triggers

11620:邏輯雲 11620: logic cloud

11622:邏輯雲 11622: logic cloud

11624:邏輯雲 11624: logic cloud

11626:邏輯雲 11626: logic cloud

11630:輸入晶片 11630: input chip

11640:輸出晶片 11640: output chip

11700:ASIC 11700:ASIC

11710:在邏輯功能模組內 11710: In the logic function module

11720:輸入/輸出單元 11720: Input/Output Unit

11722:鍵合晶片 11722: bonded wafer

11724:輸入緩衝器 11724: input buffer

11726:三種狀態輸出緩衝器 11726: Three state output buffer

11730:掃描測試控制模組 11730: Scan test control module

11732:邊界掃描寄存器鏈 11732: Boundary scan register chain

11734:邊界掃描寄存器鏈 11734: Boundary scan register chain

11800:邏輯模組 11800: logic module

11810:芯塊功能 11810: Pellet function

11812:輸入值 11812: Enter value

11814:輸出值 11814: output value

11820:BIST控制器 11820: BIST controller

11822:線性回饋移位暫存器(LFSR) 11822: Linear Feedback Shift Register (LFSR)

11824:循環冗餘核對電路 11824: Cyclic redundancy check circuit

11900:三維積體電路 11900: Three-dimensional integrated circuits

11910:控制邏輯 11910: control logic

11911:掃描觸發器 11911: scan trigger

11912:掃描觸發器 11912: scan trigger

11913:掃描觸發器 11913: scan trigger

11914:組合邏輯雲 11914: Combinational Logic Cloud

11915:組合邏輯雲 11915: Combinational Logic Cloud

11920:控制邏輯 11920: control logic

11921:掃描觸發器 11921: scan trigger

11922:掃描觸發器 11922: scan trigger

11923:掃描觸發器 11923: scan trigger

11924:邏輯雲 11924: logic cloud

11925:邏輯雲 11925: logic cloud

12000:掃描觸發器 12000: scan trigger

12002:D型觸發器 12002:D type flip flop

12004:複用器 12004: multiplexer

12006:複用器 12006: multiplexer

12100:三維積體電路 12100: Three-dimensional integrated circuits

12110:第1層邏輯錐 12110: Layer 1 Logic Cone

12112:掃描觸發器 12112: scan trigger

12114:XOR柵極 12114:XOR gate

12120:第2層邏輯錐 12120: Layer 2 logic cone

12122:掃描觸發器 12122: scan trigger

12124:XOR柵極 12124:XOR gate

12170:LAYER_SEL門閂 12170: LAYER_SEL latch

12172:ERROR2線 12172:ERROR2 line

12174:COL_ADDR線 12174: COL_ADDR line

12176:ROW_ADDR線 12176: ROW_ADDR line

12178:COL_BIT線 12178: COL_BIT line

12182:N型溝道電晶體 12182:N-type channel transistor

12184:N型溝道電晶體 12184:N-type channel transistor

12186:N型溝道電晶體 12186:N-type channel transistor

12188:線 12188: line

12190:P型溝道電晶體 12190: P-type channel transistor

12192:P型溝道電晶體 12192: P-type channel transistor

12200:邏輯功能模組(LFB) 12200: Logic function module (LFB)

12202:輸入 12202: input

12204:輸出 12204: output

12210:較小邏輯功能模組 12210: Smaller logic function module

12212:線性回饋移位暫存器電路 12212: Linear Feedback Shift Register Circuit

12214:循環冗餘核對電路 12214: Cyclic redundancy check circuit

12216:邏輯功能 12216: logic function

12220:較小邏輯功能模組 12220: Smaller logic function module

12230:線性回饋移位暫存器(LFSR)電路 12230: Linear Feedback Shift Register (LFSR) Circuit

12232:循環冗餘核對電路 12232: Cyclic redundancy check circuit

12300:三維積體電路 12300: Three-dimensional integrated circuits

12310:控制邏輯模組 12310: Control Logic Module

12311:掃描觸發器 12311: scan trigger

12312:掃描觸發器 12312: scan trigger

12313:複用器 12313: multiplexer

12314:複用器 12314: multiplexer

12315:邏輯錐 12315: logic cone

12320:控制邏輯模組 12320: Control Logic Module

12321:掃描觸發器 12321: scan trigger

12322:掃描觸發器 12322: scan trigger

12323:複用器 12323: multiplexer

12324:複用器 12324: multiplexer

12325:邏輯錐 12325: logic cone

12400:三維積體電路 12400: Three-dimensional integrated circuits

12410:第1層邏輯錐 12410: tier 1 logic cone

12412:掃描觸發器 12412: scan trigger

12414:複用器 12414: multiplexer

12416:XOR柵極 12416:XOR gate

12420:第2層邏輯錐 12420: Layer 2 logic cone

12422:掃描觸發器 12422: scan trigger

12424:複用器 12424: multiplexer

12426:XOR柵極 12426:XOR gate

12500:三維積體電路 12500: Three-dimensional integrated circuits

12510,12520:邏輯功能模組(LFB) 12510, 12520: logic function module (LFB)

12522,12524:複用器 12522, 12524: multiplexer

12530:電源選擇複用器 12530: Power Select Multiplexer

12600:三維積體電路 12600: Three-dimensional integrated circuits

12610:互連線 12610: interconnection wire

12612:互連線 12612: Interconnection wire

12620:第2層邏輯錐 12620: Layer 2 logic cone

12622:掃描觸發器 12622: scan trigger

12624:複用器 12624: multiplexer

12626:XOR柵極 12626:XOR gate

12628:RS觸發器 12628:RS trigger

12630:第2層復位線 12630: layer 2 reset line

12632:或柵極 12632: or gate

12634:第2層OR-鏈輸入線 12634: Layer 2 OR-chain input line

12636:第2層OR-鏈輸出線 12636: Layer 2 OR-chain output line

12638:N型溝道電晶體 12638:N-type channel transistor

12640:N型溝道電晶體 12640:N-type channel transistor

12642:N型溝道電晶體 12642: N-type channel transistor

12644:感應 12644: induction

12646:和柵極 12646: and gate

12648:TEST_EN線 12648: TEST_EN line

12700:三維積體電路 12700: Three-dimensional integrated circuits

12710:第1層邏輯錐 12710: tier 1 logic cone

12714:觸發器 12714: Trigger

12716:三者取多數(MAJ3)柵極 12716: The majority of the three (MAJ3) gate

12720:第2層邏輯錐 12720: Layer 2 logic cone

12724:觸發器 12724: Trigger

12726:三者取多數(MAJ3)柵極 12726: The majority of the three (MAJ3) gate

12730:第3層邏輯錐 12730: Layer 3 Logic Cone

12734:觸發器 12734: Trigger

12736:三者取多數(MAJ3)柵極 12736: The majority of the three (MAJ3) gate

12800:三維積體電路 12800: Three-dimensional integrated circuits

12810:第1層邏輯錐 12810: tier 1 logic cone

12812:三者取多數(MAJ3)柵極 12812: The majority of the three (MAJ3) gate

12814:觸發器 12814: Trigger

12820:第2層邏輯錐 12820: Layer 2 logic cone

12822:三者取多數(MAJ3)柵極 12822: The majority of the three (MAJ3) gate

12824:觸發器 12824: Trigger

12830:第3層邏輯錐 12830: Layer 3 Logic Cone

12832:三者取多數(MAJ3)柵極 12832: The majority of the three (MAJ3) gate

12834:觸發器 12834: Trigger

12900:三維積體電路 12900: Three-dimensional integrated circuits

12910:第1層邏輯錐 12910: Tier 1 Logic Cone

12912:三者取多數(MAJ3)柵極 12912: The majority of the three (MAJ3) gate

12914:觸發器 12914: Trigger

12916:三者取多數(MAJ3)柵極 12916: The majority of the three (MAJ3) gate

12920:第2層邏輯錐 12920: Layer 2 Logic Cone

12922:三者取多數(MAJ3)柵極 12922: The majority of the three (MAJ3) gate

12924:觸發器 12924: Trigger

12926:三者取多數(MAJ3)柵極 12926: The majority of three (MAJ3) gate

12930:第3層邏輯錐 12930: Layer 3 Logic Cone

12932:三者取多數(MAJ3)柵極 12932: The majority of the three (MAJ3) gate

12934:觸發器 12934: Trigger

12936:三者取多數(MAJ3)柵極 12936: The majority of three (MAJ3) gate

13000:穿孔圖案 13000: perforation pattern

13002:穿孔金屬重疊晶片 13002: perforated metal overlay wafer

13004:穿孔金屬重疊晶片 13004: perforated metal overlay wafer

13006:穿孔金屬重疊晶片 13006: perforated metal overlay wafer

13008:穿孔金屬重疊晶片 13008: perforated metal overlay wafer

13010:穿孔圖案 13010: perforated pattern

13012:穿孔金屬重疊晶片 13012: perforated metal overlay wafer

13014:穿孔金屬重疊晶片 13014: perforated metal overlay wafer

13016:穿孔金屬重疊晶片 13016: perforated metal overlay wafer

13018:穿孔金屬重疊晶片 13018: perforated metal overlay wafer

13020:三維積體電路 13020: Three-dimensional integrated circuits

13030:層 13030: layer

13031:電晶體 13031: Transistor

13032:觸點 13032: contact

13033:金屬1 13033: metal 1

13034:穿孔1 13034: perforation 1

13035:金屬2 13035: metal 2

13036:穿孔2 13036: Perforation 2

13037:金屬3 13037: metal 3

13040:直通矽晶穿孔 13040: TSV

13100:穿孔圖案 13100: perforation pattern

13102:穿孔金屬重疊晶片 13102: Perforated Metal Overlay Wafer

13104:穿孔金屬重疊晶片 13104: Perforated Metal Overlay Wafer

13106:穿孔金屬重疊晶片 13106: Perforated Metal Overlay Wafer

13110:穿孔圖案 13110: perforated pattern

13112:穿孔金屬重疊晶片 13112: Perforated Metal Overlay Wafer

13114:穿孔金屬重疊晶片 13114: Perforated Metal Overlay Wafer

13116:穿孔金屬重疊晶片 13116: Perforated Metal Overlay Wafer

13200:穿孔圖案 13200: perforated pattern

13202:穿孔金屬重疊晶片 13202: Perforated Metal Overlay Wafer

13204:穿孔金屬重疊晶片 13204: perforated metal overlay wafer

13206:穿孔金屬重疊晶片 13206: Perforated Metal Overlay Wafer

13208:穿孔金屬重疊晶片 13208: perforated metal overlay wafer

13210:穿孔金屬重疊晶片 13210: perforated metal overlay wafer

13212:穿孔金屬重疊晶片 13212: perforated metal overlay wafer

13214:穿孔金屬重疊晶片 13214: perforated metal overlay wafer

13216:穿孔金屬重疊晶片 13216: Perforated Metal Overlay Wafer

13218:穿孔金屬重疊晶片 13218: Perforated Metal Overlay Wafer

13220:三維積體電路 13220: Three-dimensional integrated circuits

13230:互連層 13230: interconnect layer

13232:互連層 13232: Interconnect layer

13240:互連層 13240: interconnect layer

13242:互連層 13242: interconnect layer

13250:互連層 13250: interconnect layer

13252:互連層 13252: interconnect layer

13301:P-摻雜層 13301: P-doped layer

13302:P-襯底施主晶圓 13302: P-Substrate Donor Wafer

13304:N+摻雜層 13304: N+ doped layer

13306:金屬矽化物層 13306: metal silicide layer

13308:氧化層 13308: oxide layer

13310:受主襯底或晶圓 13310: acceptor substrate or wafer

13312:載子或載體襯底 13312: carrier or carrier substrate

13314:粘結層 13314: bonding layer

13316:P-層 13316:P-layer

13318:氧化層 13318: oxide layer

13322:電晶體隔離區 13322: Transistor isolation area

13323:凹陷溝道 13323: Recessed channel

13324:氧化區 13324: oxidation zone

13326:金屬矽化物源極和漏極區 13326: metal silicide source and drain regions

13328:N+源極和漏極區 13328: N+ source and drain regions

13330:P型溝道區 13330: P-type channel region

13332:柵極電介質 13332: gate dielectric

13334:柵電極 13334: Gate electrode

13336:源極和漏極觸點 13336: Source and drain contacts

13338:厚氧化物 13338: thick oxide

13342:柵極觸點 13342: Gate contact

13399:層轉移劃分面 13399: layer transfer divide plane

13400:受主晶圓 13400: acceptor wafer

13400A:帶通道電晶體的受主襯底 13400A: Acceptor Substrate with Channel Transistor

13400B:帶通道電晶體和記憶元件的受主襯底 13400B: Acceptor substrate with channel transistor and memory element

13402:施主晶圓 13402: Donor Wafer

13402':通道電晶體層 13402': channel transistor layer

13404:記憶元件施主晶圓 13404: Memory element donor wafer

13404':記憶元件層 13404': memory element layer

13410:直通層穿孔(TLVs) 13410:Through Layer Vias (TLVs)

13410A:直通層穿孔 13410A: Straight through layer perforation

13410B:直通層穿孔 13410B: Straight through layer perforation

13420:存儲至開關直通層穿孔 13420: store to switch passthrough layer punch

13430:存儲至受主直通層穿孔 13430: Store-to-acceptor passthrough layer puncture

13440:記憶元件 13440: memory element

13442:通道電晶體柵極 13442: Channel Transistor Gate

13444:通道電晶體源極 13444: channel transistor source

13445:通道電晶體漏極 13445: channel transistor drain

13446:FPGA配置網路金屬線 13446: FPGA configuration network metal line

13447:FPGA配置網路金屬線 13447: FPGA configuration network metal line

13500:受主晶圓 13500: acceptor wafer

13500A:帶通道電晶體和記憶元件的受主襯底 13500A: Acceptor substrate with channel transistor and memory element

13502:施主晶圓 13502: Donor Wafer

13502':通道電晶體和存儲層 13502': channel transistor and memory layer

13510:直通層穿孔(TLVs) 13510: Through Layer Vias (TLVs)

13510A:直通層穿孔 13510A: Straight through layer perforation

13510B:直通層穿孔 13510B: Straight through layer perforation

13525:通道電晶體和存儲層互連金屬化 13525: Channel Transistor and Storage Layer Interconnect Metallization

13540:記憶元件 13540: memory element

13542:通道電晶體柵極 13542: Channel Transistor Gate

13544:通道電晶體源極 13544: Channel transistor source

13545:通道電晶體漏極 13545: channel transistor drain

13546:FPGA配置網路金屬線 13546: FPGA configuration network metal line

13547:FPGA配置網路金屬線 13547: FPGA configuration network metal line

13602:控制柵 13602: Control grid

13604:浮動柵 13604: floating gate

13610:開關電晶體溝道 13610: switch transistor channel

13612:開關電晶體源極 13612: switching transistor source

13614:開關電晶體漏極 13614: switching transistor drain

13620:感應電晶體溝道 13620: sense transistor channel

13622:感應電晶體源極 13622: Sense Transistor Source

13624:感應電晶體漏極 13624: sense transistor drain

13700:施主晶圓 13700: Donor Wafer

13701:遮罩氧化物 13701: mask oxide

13702:氧化物 13702:Oxide

13704:N+摻雜層 13704: N+ doped layer

13704':剩餘高摻雜層 13704': remaining highly doped layer

13706:P-摻雜層 13706: P-doped layer

13707:氫植入 13707: Hydrogen Implantation

13710:受主晶圓 13710: acceptor wafer

13711:隧道電介質 13711: tunnel dielectric

13714:隧道電介質 13714: tunnel dielectric

13715:未來東南電晶體區高N+摻雜 13715: High N+ doping in the southeast transistor area in the future

13716:西南電晶體溝道區 13716: Southwest Transistor Channel Area

13717:東南電晶體溝道區 13717: Southeast Transistor Channel Area

13720:電晶體隔離區 13720: Transistor isolation area

13721:西南到東南隔離區 13721: Southwest to Southeast Quarantine

13724:西南源極和漏極區 13724: SW source and drain regions

13725:東南源極和漏極區 13725: SE source and drain regions

13741:多晶矽層間電介質體 13741: polysilicon interlayer dielectric body

13742:西南凹陷溝道 13742: Southwest depression channel

13743:東南凹陷溝道 13743: southeast depression channel

13752:浮動柵 13752: floating gate

13754:控制柵 13754: Control Grid

13799:層轉移劃分面 13799: layer transfer partition plane

結合圖片和下文之詳細說明,讀者可以更為深入透徹之理解本項發明中之不同案例。 Combining the pictures and the detailed description below, readers can have a more in-depth understanding of different cases in this invention.

圖1為現有技術之電路示意圖。 FIG. 1 is a schematic circuit diagram of the prior art.

圖2為圖1中現有技術電路圖之部分剖視圖。 FIG. 2 is a partial cross-sectional view of the prior art circuit diagram in FIG. 1 .

圖3A為可編程互聯電路結構之示意圖。 FIG. 3A is a schematic diagram of a programmable interconnection circuit structure.

圖3B為可編程互聯電路結構之示意圖; 3B is a schematic diagram of a programmable interconnection circuit structure;

圖4A為可編程互聯電路板之示意圖; FIG. 4A is a schematic diagram of a programmable interconnection circuit board;

圖4B為2x2可編程互聯電路板之示意圖; 4B is a schematic diagram of a 2x2 programmable interconnect circuit board;

圖5A為逆變器邏輯晶片之示意圖; 5A is a schematic diagram of an inverter logic chip;

圖5B為緩衝器邏輯晶片之示意圖; 5B is a schematic diagram of a buffer logic chip;

圖5C為可設定強度之緩衝器邏輯晶片示意圖; FIG. 5C is a schematic diagram of a buffer logic chip whose strength can be set;

圖5D為D-觸發器邏輯晶片之示意圖; 5D is a schematic diagram of a D-flip-flop logic chip;

圖6為LUT4邏輯晶片之示意圖; 6 is a schematic diagram of a LUT4 logic chip;

圖6A為PLA邏輯晶片之示意圖; 6A is a schematic diagram of a PLA logic chip;

圖7為可編程晶片之示意圖; 7 is a schematic diagram of a programmable chip;

圖8為可編程組件層結構之示意圖; FIG. 8 is a schematic diagram of a layer structure of a programmable component;

圖8A為可編程組件多層結構之示意圖; FIG. 8A is a schematic diagram of a multi-layer structure of a programmable device;

圖8B-8I為預加工晶圓和各層以及通用層切除; Figures 8B-8I are pre-processed wafers and layers and common layer cuts;

圖9A-9C為一個使用現有矽片直穿過孔(TSV)技術之IC系統。 9A-9C illustrate an IC system using existing through-silicon via (TSV) technology.

圖10A為現有技術製造之連續陣列晶圓示意圖。 FIG. 10A is a schematic diagram of a continuous array wafer manufactured in the prior art.

圖10B為現有技術製造之連續陣列晶圓之部分示意圖。 FIG. 10B is a partial schematic diagram of a continuous array wafer manufactured in the prior art.

圖10C為現有技術製造之連續陣列晶圓之部分示意圖。 FIG. 10C is a partial schematic diagram of a continuous array wafer fabricated in the prior art.

圖11A-11F為一個晶圓上之實際掩模示意圖。 11A-11F are schematic diagrams of actual masks on a wafer.

圖12A-12E為可設定系統之示意圖; 12A-12E are schematic diagrams of a settable system;

圖13為3D邏輯分區流程之示意圖; 13 is a schematic diagram of a 3D logical partition process;

圖14為層切除流程之示意圖; Fig. 14 is a schematic diagram of a layer excision process;

圖15為底層編程電路之示意圖; Fig. 15 is the schematic diagram of bottom programming circuit;

圖16為底層隔離電晶體電路之示意圖; FIG. 16 is a schematic diagram of a bottom isolation transistor circuit;

圖17A為底層反偏壓電路之拓撲示意圖; 17A is a topological schematic diagram of the bottom reverse bias circuit;

圖17B為底層反偏壓電路之示意圖; 17B is a schematic diagram of the bottom reverse bias circuit;

圖17C為電源控制電路之示意圖; 17C is a schematic diagram of a power control circuit;

圖17D為探針電路之示意圖; 17D is a schematic diagram of a probe circuit;

圖18為底層SRAM之示意圖; Figure 18 is a schematic diagram of the bottom SRAM;

圖19A為底層I/O之示意圖; FIG. 19A is a schematic diagram of bottom I/O;

圖19B為邊“切”示意圖; Fig. 19B is a schematic diagram of edge "cutting";

圖19C為一個3D IC系統之示意圖; 19C is a schematic diagram of a 3D IC system;

圖19D為3D IC處理器和DRAM系統之示意圖; FIG. 19D is a schematic diagram of a 3D IC processor and DRAM system;

圖19E為3D IC處理器和DRAM系統之示意圖; 19E is a schematic diagram of a 3D IC processor and a DRAM system;

圖19F為使用定制SOI晶圓構建矽片直穿連接之示意 圖。 Figure 19F is a schematic diagram of using a custom SOI wafer to construct a TSIC picture.

圖19G為使用現有技術製造矽片直穿過孔(TSV)之示意圖。 FIG. 19G is a schematic diagram of manufacturing straight through-silicon vias (TSVs) using the prior art.

圖19H為製造定制SOI晶圓之流程示意圖; FIG. 19H is a schematic diagram of the process of manufacturing a custom SOI wafer;

圖19I為一個處理器-DRAM堆之示意圖; Figure 19I is a schematic diagram of a processor-DRAM stack;

圖19J為製造定制SOI晶圓之流程示意圖; FIG. 19J is a schematic diagram of the process of manufacturing a custom SOI wafer;

圖20為層切除流程之示意圖; FIG. 20 is a schematic diagram of a layer excision process;

圖21A為使用預處理晶圓進行層切除之示意圖; 21A is a schematic diagram of layer excision using a preprocessed wafer;

圖21B為可以進行層切除之預處理晶圓示意圖; FIG. 21B is a schematic diagram of a preprocessed wafer capable of layer excision;

圖22A-22H為表層平面電晶體成型示意圖; 22A-22H are schematic diagrams of forming surface planar transistors;

圖23A、23B為使用預處理晶圓進行層切除之示意圖; 23A and 23B are schematic diagrams of layer excision using preprocessed wafers;

圖24A-24F為表層平面電晶體成型示意圖; 24A-24F are schematic diagrams of surface planar transistor formation;

圖25A、25B為使用預處理晶圓進行層切除之示意圖; 25A and 25B are schematic diagrams of layer excision using preprocessed wafers;

圖26A-26E為表層平面電晶體成型示意圖; 26A-26E are schematic diagrams of forming surface planar transistors;

圖27A、27B為使用預處理晶圓進行層切除之示意圖; 27A and 27B are schematic diagrams of layer excision using preprocessed wafers;

圖28A-28E為表層電晶體成型示意圖; 28A-28E are schematic diagrams of forming surface transistors;

圖29A-29G為表層平面電晶體成型示意圖; 29A-29G are schematic diagrams of forming surface planar transistors;

圖30為電子供給晶圓之示意圖; 30 is a schematic diagram of an electron supply wafer;

圖31為主晶園上之切除層示意圖; Figure 31 is a schematic diagram of the excision layer on the master wafer;

圖32為測量對齊偏差之示意圖; Figure 32 is a schematic diagram of measuring alignment deviation;

圖33A、33B為連接帶之示意圖; Fig. 33A, 33B are the schematic diagrams of connection belt;

圖34A-34E為多個預處理晶圓進行層切除之示意圖; 34A-34E are schematic diagrams of layer removal performed on multiple pre-processed wafers;

圖35A-35G為表層平面電晶體成型示意圖; 35A-35G are schematic diagrams of forming surface planar transistors;

圖36為板陣列晶圓之示意圖; 36 is a schematic diagram of a plate array wafer;

圖37為可編程終端組件之示意圖; Figure 37 is a schematic diagram of a programmable terminal assembly;

圖38為調整後之JTAG連接示意圖; Figure 38 is a schematic diagram of the adjusted JTAG connection;

圖39A-39C為用於製造垂直電晶體之預處理晶圓示意圖; 39A-39C are schematic diagrams of pre-processed wafers used to manufacture vertical transistors;

圖40A-40I為垂直n-MOSFET表層電晶體之示意圖; 40A-40I are schematic diagrams of vertical n-MOSFET surface transistors;

圖41為帶有冗餘之3D IC系統示意圖; FIG. 41 is a schematic diagram of a 3D IC system with redundancy;

圖42為逆變器晶片之示意圖; Figure 42 is a schematic diagram of an inverter chip;

圖43A-C為3D晶片成型準備步驟之示意圖; 43A-C are schematic diagrams of preparation steps for 3D wafer molding;

圖44A-F為3D晶片成型步驟之示意圖; 44A-F are schematic diagrams of 3D wafer forming steps;

圖45A-G為3D晶片成型步驟之示意圖; 45A-G are schematic diagrams of 3D wafer forming steps;

圖46A-C為一層3D逆變器晶片之截面示意圖; 46A-C are schematic cross-sectional views of a layer of 3D inverter chips;

圖47為2個輸入之NOR晶片示意圖; Figure 47 is a schematic diagram of two input NOR chips;

圖48A-C為一層3D 2-輸入NOR晶片之截面示意圖; 48A-C are schematic cross-sectional views of a layer of 3D 2-input NOR chips;

圖49A-C為2-輸入之NOR 3D晶片示意圖; Figure 49A-C is a schematic diagram of a 2-input NOR 3D chip;

圖50A-D為3D CMOS傳輸晶片示意圖; 50A-D are schematic diagrams of a 3D CMOS transmission chip;

圖51A-D為3D CMOS SRAM晶片示意圖; 51A-D are schematic diagrams of a 3D CMOS SRAM chip;

圖52A、52B為無接頭電晶體之組件模擬圖; 52A, 52B are the component simulation diagrams of the junctionless transistor;

圖53A-E為3D CAM晶片之示意圖; 53A-E are schematic diagrams of a 3D CAM chip;

圖54A-C為無接頭電晶體之成型示意圖; 54A-C are schematic diagrams of forming a junctionless transistor;

圖55A-I為無接頭電晶體之成型示意圖; 55A-I are schematic diagrams of forming a junctionless transistor;

圖56A-M為無接頭電晶體之成型示意圖; 56A-M are schematic diagrams of forming a junctionless transistor;

圖57A-G為無接頭電晶體之成型示意圖; 57A-G are schematic diagrams of forming a junctionless transistor;

圖58A-G為無接頭電晶體之成型示意圖; 58A-G are schematic diagrams of forming a junctionless transistor;

圖59為現有技術之金屬互聯堆示意圖; Fig. 59 is a schematic diagram of a metal interconnect stack in the prior art;

圖60為金屬互聯堆示意圖; Figure 60 is a schematic diagram of a metal interconnect stack;

圖61A-I為無接頭電晶體之示意圖; 61A-I are schematic diagrams of junctionless transistors;

圖62A-D為3D NAND2晶片之示意圖; 62A-D are schematic diagrams of 3D NAND2 chips;

圖63A-G為3D NAND8晶片之示意圖; 63A-G are schematic diagrams of 3D NAND8 chips;

圖64A-G為3D NOR8晶片之示意圖; 64A-G are schematic diagrams of 3D NOR8 chips;

圖65A-C為無接頭電晶體之成型示意圖; 65A-C are schematic diagrams of forming a junctionless transistor;

圖66為凹槽通道陣列電晶體之示意圖; Fig. 66 is a schematic diagram of a trench channel array transistor;

圖67A-F為凹槽通道陣列電晶體之成型示意圖; 67A-F are schematic diagrams of forming grooved channel array transistors;

圖68A-F為球型凹槽通道陣列電晶體之成型示意圖; 68A-F are schematic diagrams of forming a spherical groove channel array transistor;

圖69為電子供給晶圓之示意圖; Figure 69 is a schematic diagram of an electron supply wafer;

圖70A、B、B-1和C-H為表層平面電晶體成型示意圖; Fig. 70A, B, B-1 and C-H are the schematic diagrams of surface plane transistor formation;

圖71為電子供給晶圓之示意圖; 71 is a schematic diagram of an electron supply wafer;

圖72A-F為表層平面電晶體成型示意圖; 72A-F are schematic diagrams of surface planar transistor formation;

圖73為電子供給晶圓之示意圖; 73 is a schematic diagram of an electron supply wafer;

圖74為測量對齊偏差之示意圖; Figure 74 is a schematic diagram of measuring alignment deviation;

圖75為連接帶之示意圖; Fig. 75 is the schematic diagram of connection belt;

圖76為電子供給晶圓之示意圖; 76 is a schematic diagram of an electron supply wafer;

圖77為連接帶之示意圖; Fig. 77 is the schematic diagram of connection belt;

圖78A、78B、78C為一層電子供給晶圓之示意圖; 78A, 78B, and 78C are schematic diagrams of a layer of electron supply wafers;

圖79為連接帶之示意圖; Fig. 79 is the schematic diagram of connection belt;

圖80為連接帶陣列結構之示意圖; Fig. 80 is the schematic diagram of connecting strip array structure;

圖81A-81F-2為表層平面電晶體成型示意圖; Figures 81A-81F-2 are schematic diagrams of forming surface plane transistors;

圖82A-G為表層平面電晶體成型示意圖; 82A-G are schematic diagrams of surface planar transistor formation;

圖83A-L為表層平面電晶體成型示意圖; Figure 83A-L is a schematic diagram of forming a surface planar transistor;

圖83L1-L4為表層平面電晶體成型示意圖; Figure 83L1-L4 is a schematic diagram of surface plane transistor formation;

圖84A-G為連續電晶體陣列之示意圖; 84A-G are schematic diagrams of sequential transistor arrays;

圖85A-E為表層平面電晶體成型示意圖; Figure 85A-E is a schematic diagram of forming a surface plane transistor;

圖86A為3D邏輯IC可供維修結構之示意圖; FIG. 86A is a schematic diagram of a repairable structure of a 3D logic IC;

圖86B為單層掃描鏈3D IC示意圖; FIG. 86B is a schematic diagram of a single-layer scan chain 3D IC;

圖86C為無接觸測試示意圖; Figure 86C is a schematic diagram of non-contact testing;

圖87為可維修3D IC邏輯器之觸發器示意圖; FIG. 87 is a schematic diagram of a flip-flop of a repairable 3D IC logic device;

圖88A-F為3D DRAM之成型示意圖; 88A-F are schematic diagrams of forming 3D DRAM;

圖89A-D為3D DRAM之成型示意圖; 89A-D are schematic diagrams of forming 3D DRAM;

圖90A-F為3D DRAM之成型示意圖; 90A-F are schematic diagrams of forming a 3D DRAM;

圖91A-L為3D DRAM之成型示意圖; 91A-L are schematic diagrams of forming 3D DRAM;

圖92A-F為3D DRAM之成型示意圖; 92A-F are schematic diagrams of forming 3D DRAM;

圖93A-D為先進TSV流程之示意圖; 93A-D are schematic diagrams of advanced TSV flows;

圖94A-C為先進多連接TSV流程之示意圖; 94A-C are schematic diagrams of advanced multi-connection TSV flow;

圖95A-J為CMOS凹槽通道陣列電晶體之成型示意圖; 95A-J are schematic diagrams of forming CMOS trench channel array transistors;

圖96A-J為無接頭電晶體之成型示意圖; Figure 96A-J is a schematic diagram of forming a junctionless transistor;

圖97為基本浮體DRAM之示意圖; Figure 97 is a schematic diagram of a basic floating body DRAM;

圖98A-H為浮體DRAM電晶體之成型示意圖; 98A-H are schematic diagrams of forming floating body DRAM transistors;

圖99A-M為浮體DRAM電晶體之成型示意圖; 99A-M are schematic diagrams of forming floating body DRAM transistors;

圖100A-L為浮體DRAM電晶體之成型示意圖; 100A-L are schematic diagrams of forming floating body DRAM transistors;

圖101A-K為電阻性儲存電晶體之成型示意圖; 101A-K are schematic diagrams of forming resistive storage transistors;

圖102A-L為電阻性儲存電晶體之成型示意圖; 102A-L are schematic diagrams of forming resistive storage transistors;

圖103A-M為電阻性儲存電晶體之成型示意圖; 103A-M are schematic diagrams of forming resistive storage transistors;

圖104A-F為電阻性儲存電晶體之成型示意圖; 104A-F are schematic diagrams of formation of resistive storage transistors;

圖105A-G為電荷俘獲型電晶體之成型示意圖; 105A-G are schematic diagrams of forming charge-trapping transistors;

圖106A-G為電荷俘獲型電晶體之成型示意圖; 106A-G are schematic diagrams of forming charge-trapping transistors;

圖107A-G為浮柵儲存電晶體之成型示意圖; 107A-G are schematic diagrams of forming floating gate storage transistors;

圖108A-H為浮柵儲存電晶體之成型示意圖; 108A-H are schematic diagrams of forming floating gate storage transistors;

圖109A-K為電阻性儲存電晶體之成型示意圖; 109A-K are schematic diagrams of forming resistive storage transistors;

圖110A-J為帶有上邊緣之電阻性儲存電晶體之成型示意圖; 110A-J are schematic diagrams of forming a resistive storage transistor with an upper edge;

圖111A-D為通用層切除流程及對其視窗之案例示意圖; 111A-D are schematic diagrams of the general layer removal process and its window;

圖112為帶有散熱器之3D IC系統示意圖; FIG. 112 is a schematic diagram of a 3D IC system with a radiator;

圖113A-B為集成热量排出裝置之3D-IC示意圖; 113A-B are schematic diagrams of 3D-IC with integrated heat removal device;

圖114為現場可維修3D IC系統之示意圖; Figure 114 is a schematic diagram of a field repairable 3D IC system;

圖115為3模態冗餘3D IC系統之示意圖; 115 is a schematic diagram of a 3-mode redundant 3D IC system;

圖116為現有技術之組掃描架構示意圖; FIG. 116 is a schematic diagram of a group scanning architecture in the prior art;

圖117為現有技術之邊界掃描架構示意圖; FIG. 117 is a schematic diagram of a boundary scan architecture in the prior art;

圖118為現有技術之BIST架構示意圖; FIG. 118 is a schematic diagram of the BIST architecture of the prior art;

圖119為另外一個現場可維修3D IC系統之示意圖; FIG. 119 is a schematic diagram of another field repairable 3D IC system;

圖120為可用於圖119所示3D IC之掃描觸發器之示意圖; FIG. 120 is a schematic diagram of a scan flip-flop that can be used in the 3D IC shown in FIG. 119;

圖121A為第三個現場可維修3D IC系統之示意圖; Figure 121A is a schematic diagram of a third field repairable 3D IC system;

圖121B為圖121A中現場可維修3D IC系統之另一面; Figure 121B is another side of the field repairable 3D IC system of Figure 121A;

圖122為第四個現場可維修3D IC系統之示意圖; Figure 122 is a schematic diagram of a fourth field repairable 3D IC system;

圖123為第五個現場可維修3D IC系統之示意圖; Figure 123 is a schematic diagram of a fifth field repairable 3D IC system;

圖124為第六個現場可維修3D IC系統之示意圖; Figure 124 is a schematic diagram of a sixth field repairable 3D IC system;

圖125A為第七個現場可維修3D IC系統之示意圖; Figure 125A is a schematic diagram of a seventh field repairable 3D IC system;

圖125B為圖125A中現場可維修3D IC系統之另一面; Figure 125B is another side of the field repairable 3D IC system of Figure 125A;

圖126為第八個現場可維修3D IC系統之示意圖; Figure 126 is a schematic diagram of an eighth field repairable 3D IC system;

圖127為第二個3模態冗餘3D IC系統之示意圖; 127 is a schematic diagram of a second 3-mode redundant 3D IC system;

圖128為第三個3模態冗餘3D IC系統之示意圖; 128 is a schematic diagram of a third 3-mode redundant 3D IC system;

圖129為第四個3模態冗餘3D IC系統之示意圖; 129 is a schematic diagram of a fourth 3-mode redundant 3D IC system;

圖130A為第一個過孔技術重疊方式之示意圖; FIG. 130A is a schematic diagram of the first overlapping method of via technology;

圖130B為第二個過孔技術重疊方式之示意圖; FIG. 130B is a schematic diagram of the second via technology overlapping method;

圖130C為圖130A和130B中現場可維修3D IC之過孔技術重疊方式之對齊示意圖; FIG. 130C is a schematic diagram of the alignment of the via technology overlap method of the field repairable 3D IC in FIGS. 130A and 130B;

圖130D為圖130C中結構之側視圖; Figure 130D is a side view of the structure in Figure 130C;

圖131A為第三個過孔技術重疊方式之示意圖; FIG. 131A is a schematic diagram of a third via technology overlapping method;

圖131B為第四個過孔技術重疊方式之示意圖; FIG. 131B is a schematic diagram of the fourth overlapping method of via technology;

圖131C為圖131A、131B和131C中過孔技術重疊方式之對齊示意圖; FIG. 131C is a schematic diagram of the alignment of via technology overlapping methods in FIGS. 131A, 131B and 131C;

圖132A為第五個過孔技術重疊方式之示意圖; FIG. 132A is a schematic diagram of the fifth via technology overlapping method;

圖132B為圖132A中3D IC過孔金屬重疊方式之對齊示意圖; FIG. 132B is a schematic diagram of the alignment of the 3D IC via metal overlapping method in FIG. 132A;

圖133A-I為帶有源極和汲極矽化物之凹槽通道陣列電晶體之成型示意圖; 133A-I are schematic diagrams of forming grooved channel array transistors with source and drain silicides;

圖134A-F為3D IC FPGA處理器之流程示意圖; 134A-F are schematic flow charts of a 3D IC FPGA processor;

圖135A-D為3D IC FPGA處理器之替代方案流程示意圖; 135A-D are schematic flow charts of alternative solutions for 3D IC FPGA processors;

圖136為NVM FPGA設定晶片之示意圖; Figure 136 is a schematic diagram of an NVM FPGA setting chip;

圖137A-G為3D IC NVM FPGA設定晶片處理流程之示意圖。 137A-G are schematic diagrams of 3D IC NVM FPGA setting wafer processing flow.

以下將參照圖紙對本項發明的案例進行說明。通常對於該領域僅有基礎知識的人們會希望說明和圖紙能夠解釋該項發明而非限制對本項發明的理解,並且圖紙無需放大到更清晰。同時,人們也會意識到透過應用本項發明之原理,能夠製造出更多之案例,而這些案例均將屬於本項發明專利保護之範疇,附件專利權聲明中另有說明的除外。 Hereinafter, examples of the present invention will be described with reference to the drawings. Usually a person with only basic knowledge in the field would like the description and drawings to explain the invention rather than limit the understanding of the invention, and the drawings need not be enlarged for greater clarity. At the same time, people will also realize that by applying the principles of this invention, more cases can be created, and these cases will all belong to the scope of protection of this invention patent, unless otherwise stated in the attached patent statement.

圖1為現有技術之電路示意圖,例如860-1至860-4均為可編程電晶體,用於對850-1,1編程。 FIG. 1 is a schematic circuit diagram of the prior art. For example, 860-1 to 860-4 are programmable transistors for programming 850-1, 1.

圖2為圖1中現有技術電路圖之局部剖視圖,編程電晶體860-1作為矽基片之一部分內置。 FIG. 2 is a partial cross-sectional view of the prior art circuit diagram in FIG. 1. The programming transistor 860-1 is embedded as part of the silicon substrate.

圖3A為可編程連接板之示意圖。310-1是4個水平金屬帶之一,構成平行帶。如今,一般的IC都有多個金屬層。在一個典型的可編程組件中,前兩個或前三個金屬層都可以用來建設邏輯組件。在它們之上方,金屬層4-金屬層7用來建設邏輯組件之佈線電路。在一個FPGA組件中,邏輯組件是可編程的,邏輯組件之間之佈線電路也是。在本 發明之可設定佈線電路從第4金屬層或之上開始建設。例如,金屬層4和5可以作為長插接條,金屬層6和7可以構成短插接條。通常,插接條構成了可編程佈線電路,具有相同之長高度和延伸方向,就像310-1、310-2、310-3、310-4一樣,構成平行之插接條。通常一個能帶包含10-40個插接條。通常,後續層之插接條會向垂直方向延伸,如圖3A中所示,金屬層6之插接條310和金屬層7之插接條308(即為垂直關係)。在本例中,金屬層6和金屬層7之間之絕緣體,在金屬層6和7之間之插接條交叉處,構成抗熔儲存之位置。板300包括16個這樣之抗熔存儲。312-1就是位於插接條310-4和308-4交叉位置之抗熔儲存。開啟後,它可以插接條310-4和插接條308-4。圖3A為簡化圖,通常,板之每一層包含10-40個插接條,並有多個這樣之板,包含抗熔儲存可設定佈線電路結構。 FIG. 3A is a schematic diagram of a programmable connection board. 310-1 is one of 4 horizontal metal strips that make up the parallel strips. Today, typical ICs have multiple metal layers. In a typical programmable component, the first two or three metal layers can be used to build the logic component. On top of them, metal layers 4-7 are used to build the routing circuits for logic components. In an FPGA device, the logic elements are programmable, as are the wiring circuits between the logic elements. in this Invented configurable wiring circuits are built from the 4th metal layer or above. For example, metal layers 4 and 5 can be used as long splice bars, and metal layers 6 and 7 can be used as short splice bars. Usually, the plug strips constitute a programmable wiring circuit, have the same long height and extension direction, just like 310-1, 310-2, 310-3, 310-4, constitute parallel plug strips. Usually a band contains 10-40 splice strips. Usually, the plug bars of the subsequent layers extend vertically, as shown in FIG. 3A , the plug bars 310 of the metal layer 6 and the plug bars 308 of the metal layer 7 (that is, vertical relationship). In this example, the insulator between the metal layer 6 and the metal layer 7 constitutes the location of the antifuse storage at the intersection of the straps between the metal layers 6 and 7 . Board 300 includes 16 such antifuse stores. 312-1 is the antifuse storage located at the crossing position of the plug strips 310-4 and 308-4. When turned on, it can be plugged into strip 310-4 and plugged into strip 308-4. FIG. 3A is a simplified diagram. Usually, each layer of the board contains 10-40 plug strips, and there are multiple such boards, including antifuse memory programmable wiring circuit structure.

304是與插接條310-1相連之Y可編程電晶體。318是一個與插接條308-4相連之X可編程電晶體。302是Y選擇邏輯器,在編程階段允許對一個Y編程電晶體進行選擇。316是X選擇邏輯器,在編程階段允許對一個X編程電晶體進行選擇。一旦304和318被選定,就會在插接條310-1上產生編程電壓306,同時插接條308-4接地,使得抗熔儲存312-4被開啟。 304 is a Y programmable transistor connected to the plug strip 310-1. 318 is an X programmable transistor connected to strip 308-4. 302 is a Y selection logic which allows selection of a Y programming transistor during the programming phase. 316 is an X selection logic which allows selection of an X programming transistor during the programming phase. Once 304 and 318 are selected, programming voltage 306 is generated on strip 310-1 while strip 308-4 is grounded, causing antifuse 312-4 to be turned on.

圖3B為可編程連接結構300B之示意圖;300B是300A之變體,能帶之部分插接條具有不同之長度。在該變體中,沒有插接條308-4,只有兩個較短之插接條308-4B1和 308-4B2。這可能對可編程佈線電路結構300B之訊號輸入和輸出有益,為了減少一個板中插接條之數目,這些短插接條可用於佈線電路結構中訊號之輸入和輸出,而不同於之前透過插接條來進行路徑選擇。在該變體中,編程電路需要放大來支援對抗熔存儲312-4B和312-4B的編程。 FIG. 3B is a schematic diagram of a programmable connection structure 300B; 300B is a variation of 300A, and some plug strips of the energy band have different lengths. In this variant, there is no splice strip 308-4, only two shorter splice strips 308-4B1 and 308-4B2. This may be beneficial for the signal input and output of the programmable wiring circuit structure 300B. In order to reduce the number of plug strips in a board, these short plug strips can be used for the input and output of signals in the wiring circuit structure, instead of using the previous plug-in strips. to select the path. In this variation, the programming circuit needs to be amplified to support the programming of antifuse storage 312-4B and 312-4B.

與現有技術不同,本項發明中之各種案例建議不在矽基片擴散層建設可編程電晶體,而是在可設定抗熔存儲佈線之的工作電壓。這也是抗熔存儲結構設定之一部分,使得抗熔存儲不會輕易被開啟。另外,需要注意的是,可能需要進行設定,並添加矽源極來確保編程過程不損壞工作電路。因此,在矽基片上包含抗熔存儲可編程電晶體時,需要額外之矽片區域和非常小心。 Different from the prior art, various cases in this invention suggest not constructing the programmable transistor in the diffusion layer of the silicon substrate, but setting the working voltage in the antifuse wiring. This is also part of the antifuse structure setting, so that the antifuse will not be easily opened. Also, be aware that it may be necessary to set and add a silicon source to ensure that the programming process does not damage the working circuit. Therefore, additional silicon area and great care are required when including antifuse programmable transistors on a silicon substrate.

為了滿足高速組件之性能要求,工作中之電晶體之最大要求是速度,而編程電路可以相對以較低速度工作。所以編程電路可以使用薄膜電晶體,可以很好地滿足功能,並能減少對矽片面積之要求。 In order to meet the performance requirements of high-speed components, the maximum requirement of the working transistor is speed, and the programming circuit can work relatively at a lower speed. Therefore, the programming circuit can use thin film transistors, which can satisfy the function well and reduce the requirement on the silicon chip area.

還有其他類型之電晶體,如真空FET、雙極管等,也可用於可編程電路,也可不佈置在矽基上,而是佈置在抗熔存儲可設定佈線電路之上層或下層。 There are other types of transistors, such as vacuum FETs, bipolar transistors, etc., which can also be used in programmable circuits, and can also be arranged not on the silicon base, but on the upper or lower layer of the antifuse memory programmable wiring circuit.

但是,在另一替代方案中,可編程電晶體和可編程電路可在SOI晶圓上製造,然後將晶圓黏結到可設定邏輯器晶圓上,並使用矽片直穿過孔(TSV)或穿層過孔(TLV)相連。使用SOI晶圓實現抗熔存儲編程功能之優勢在於,在該晶圓上建設之 However, in another alternative, programmable transistors and programmable circuits can be fabricated on SOI wafers, and the wafers can be bonded to programmable logic wafers using through-silicon vias (TSVs) Or connected through layer vias (TLV). The advantage of using SOI wafers for antifuse programming is that the

高電壓電晶體非常高效,並且可用於編程電路及支援功能,例如編程控制器功能。另外還有一個變體,可編程電路可以在以前之SOI晶圓工藝上製造,進一步減小成本。也可以在全球其他工藝技術中/或製造地點使用。 High voltage transistors are very efficient and can be used to program circuits and support functions such as programming controller functions. In addition, there is a variant in which programmable circuits can be fabricated on the previous SOI wafer process, further reducing costs. It can also be used in other process technologies and/or manufacturing locations around the world.

還有其他可在抗熔存儲可設定佈線電路上整合矽片或其他半導體層之處理技術,實現抗熔存儲可編程電路之建設。有一個例子,最近有一種技術,提出使用電漿槍噴灑半導體級矽,形成半導體結構,包括如p-n節。噴灑矽所形成的相應半導體類型是可以預測的。另外,還有越來越多之技術使用石墨烯和碳納米管(CNT)來實現半導體功能。基於本項發明,我們將使用片語“薄膜電晶體”作為以上技術之總稱,也包括所有已知或未知之類似技術。 There are also other processing technologies that can integrate silicon chips or other semiconductor layers on the antifuse programmable wiring circuit to realize the construction of the antifuse programmable circuit. As an example, there is a recent technique that proposes the use of plasma guns to spray semiconductor-grade silicon to form semiconductor structures, including, for example, p-n junctions. The corresponding semiconductor type formed by spraying silicon is predictable. In addition, there are more and more technologies using graphene and carbon nanotubes (CNTs) to realize semiconductor functions. Based on this invention, we will use the phrase "thin film transistor" as a general term for the above technologies, including all known or unknown similar technologies.

總之,一個共同之目標就是不進行重新設定,在最小之掩膜附設成本下,減小大批量生產之成本。使用薄膜電晶體,作為可編程電晶體,能夠實現相對簡單和直接之批量成本節約。不需要在隔離層嵌入抗熔存儲,定制掩膜可以用來定義最終所有位置之過孔,儘管之前這些過孔各自有單獨之開啟抗熔存儲。另外,之前需要進行編程的,這之間之相同連接可以透過固定之過孔相連。這樣就可能節約製造抗熔存儲編程層和編程電路相關之成本。需要注意的是,在抗熔存儲電阻和掩膜定義之過孔電阻之間可能存在區別。常規之處理方式是製作兩種選擇方案之類比模型,由設定師對在兩種情況下之設定是否都可行進行驗證。 In summary, a common goal is to reduce the cost of mass production with minimal mask setup cost without resetting. Using thin film transistors, as programmable transistors, enables relatively simple and straightforward volume cost savings. Instead of embedding the antifuse in the isolation layer, a custom mask can be used to define the vias in all the final locations, although previously these vias each had a separate open antifuse. In addition, those that need to be programmed before, the same connections between them can be connected through fixed vias. This may save costs associated with fabricating the antifuse programming layer and programming circuitry. Note that there may be a distinction between antifuse resistors and mask-defined via resistors. The conventional approach is to make analog models of the two alternatives, and the setter will verify whether the settings in both cases are feasible.

在抗熔存儲層之上建設編程電路之另外一個目的在於實現更高之電路密度。為了將編程電晶體與各自之金屬插接條連接起來,可能會需要很多連接。如果這些連接向上,則可能不阻斷下層連接之佈線電路路徑,從而減少上方之電路。 Another purpose of building programming circuits on top of the antifuse layer is to achieve higher circuit density. Many connections may be required to connect the programming transistors to their respective metal straps. If these connections go up, it is possible not to block the wiring circuit path for the connections on the lower layers, thereby reducing the circuitry above.

如圖3A所示為一個4x4插接條之佈線電路結構,通常之佈線電路結構可能包含多條20x30插接條。對於一個20x30之板,大約需要20+30=50個編程電晶體。20x30板區域大約為30hpx30vp,“hp”標識水平間距,“vp”標識垂直間距。這樣就可能造成可編程電晶體之面積相對較大,大約在12hp x vp(20hpx30vp/50=12hpxvp)。另外,需要處理:在可編程層之間,每個連接之可用面積,以及可編程佈線電路結構。並且,其中1-2個再分佈層可能需要重新分佈可用面積內之連接,然後將這些連接向下建設,最好是對準,使得在向可編程佈線電路結構之下層插接條310連接之過程中造成之阻礙最小。 FIG. 3A shows a wiring circuit structure of a 4x4 plug strip, and a common wiring circuit structure may include multiple 20x30 plug strips. For a 20x30 board, about 20+30=50 programming transistors are needed. A 20x30 board area is about 30hpx30vp, "hp" indicates the horizontal spacing, and "vp" indicates the vertical spacing. In this way, the area of the programmable transistor may be relatively large, about 12hp x vp (20hpx30vp/50=12hpxvp). In addition, you need to deal with: between programmable layers, the available area for each connection, and the programmable wiring circuit structure. Also, 1-2 of the redistribution layers may need to redistribute the connections within the available area, and then build these connections down, preferably aligned, so that before connecting to the lower layer patch strip 310 of the programmable routing circuit structure The process causes minimal hindrance.

圖4A為可編程連接板300和另外一個可編程連接板320之示意圖。由於矽密度更高,能夠以最緊湊之方式在該板上建設可設定佈線電路。圖4B為2x2可編程佈線電路板之意圖;包括棋盤格形狀之板300和板320,板320是板300旋轉90度之變體。當一個訊號從南到北傳輸時,需要使用抗熔存儲,如406來連接南-北插接條。406和410均為抗熔存儲,位於一個插接條之末端,將該插接條與相同方向之其他插接條連接。訊號從南到北從金屬層6傳輸到金屬層7。 如果需要改變方向,則使用類似312-1之抗熔存儲。 FIG. 4A is a schematic diagram of a programmable connection board 300 and another programmable connection board 320 . Due to the higher silicon density, configurable routing circuits can be built on this board in the most compact way. Figure 4B is a schematic of a 2x2 programmable wiring circuit board; including a tessellated board 300 and a board 320, which is a variation of board 300 rotated 90 degrees. When a signal is transmitted from south to north, it is necessary to use antifuse memory, such as 406, to connect the south-north splice strip. Both 406 and 410 are antifuse, located at the end of a strip that is connected to other strips in the same orientation. Signals travel from metal layer 6 to metal layer 7 from south to north. If a change of direction is required, use an antifuse like 312-1.

可設定佈線電路結構可能包括:將輸出邏輯晶片和輸入邏輯晶片連接起來,建設所需之部分定制邏輯器。邏輯晶片本身透過前幾個金屬層與矽基片上之電晶體建設。通常金屬層1和金屬層2用來建設邏輯晶片。有時,使用金屬層3或層3的一部分也很有效。 The configurable routing circuit structure may include: connecting the output logic chip to the input logic chip, and constructing the required part of the custom logic. The logic chip itself is built with the first few metal layers and transistors on the silicon substrate. Usually metal layer 1 and metal layer 2 are used to build logic chips. Sometimes it is also effective to use metal layer 3 or part of layer 3.

圖5A為逆變器504及其輸入502和輸出506之示意圖。逆變器是最簡單之邏輯晶片。輸入502和輸出506可以透過可設定佈線結構上之插接條相連。 FIG. 5A is a schematic diagram of an inverter 504 and its input 502 and output 506 . An inverter is the simplest logic chip. The input 502 and the output 506 can be connected through a plug strip on a configurable wiring structure.

圖5B為緩衝器514及其輸入512和輸出516之示意圖。輸入512和輸出516可以透過可設定佈線結構上之插接條相連。 FIG. 5B is a schematic diagram of buffer 514 and its input 512 and output 516 . The input 512 and the output 516 can be connected through a plug strip on a configurable wiring structure.

圖5C為可設定強度緩衝器524及其輸入522和輸出526之示意圖。輸入522和輸出526可以透過可設定佈線結構上之插接條相連。524可以透過抗熔存儲528-1、528-2和528-3設定,上述抗熔存儲構成了一個抗熔存儲可設定驅動晶片。 FIG. 5C is a schematic diagram of a settable strength buffer 524 and its input 522 and output 526 . The input 522 and the output 526 can be connected through a plug strip on a configurable wiring structure. 524 is programmable through antifuse 528-1, 528-2 and 528-3 which constitute an antifuse programmable drive chip.

圖5D是D-觸發器534及其輸入532-2和輸出536之示意圖,包括控制輸入532-1、532-3、532-4和532-5。控制訊號可與可設定佈線電路或本地或全局控制訊號相連。 5D is a schematic diagram of D-flip-flop 534 and its input 532-2 and output 536, including control inputs 532-1, 532-3, 532-4, and 532-5. Control signals can be connected to configurable wiring circuits or local or global control signals.

圖6為LUT4之示意圖。LUT4 604是FPGA技術中常見之邏輯組件,叫做16位查找表或LUT4。該組件具有四個輸入602-1、602-2、602-3、和602-4。一個輸出606。通常一個LUT4可以編程實現任何需要小於等於4個輸入之邏輯 功能。圖6中之LUT功能可透過32抗熔存儲如608來實現。604-5是一個2-1多路轉換器。在FPGA中,最常見之LUT4實施方法就是使用16位SRAM晶片或15路多工器。圖6顯示了一個透過32位抗熔存儲和7路多工器之LUT4抗熔存儲可設定查表實施方法。圖6中之可編程晶片包括額外之輸入602-6、602-7,每個輸入附設有8位抗熔存儲,允許實現LUT4之外之功能。 FIG. 6 is a schematic diagram of LUT4. LUT4 604 is a common logic element in FPGA technology called a 16-bit look-up table or LUT4. The component has four inputs 602-1, 602-2, 602-3, and 602-4. One outputs 606. Usually a LUT4 can be programmed to implement any logic that requires less than or equal to 4 inputs Function. The LUT function in FIG. 6 can be realized through 32 antifuse memory such as 608 . 604-5 is a 2-1 multiplexer. In FPGA, the most common way to implement LUT4 is to use 16-bit SRAM chips or 15-way multiplexers. Figure 6 shows a LUT4 antifuse configurable look-up table implementation via 32-bit antifuse and 7-way multiplexers. The programmable chip in FIG. 6 includes additional inputs 602-6, 602-7, each with 8-bit antifuse attached, allowing functions other than LUT4 to be implemented.

圖6A是一個PLA邏輯器晶片6A00之示意圖。在LUT邏輯器成為主流之前,該晶片用於大多數常用可編程邏輯器。其他此類邏輯器之縮寫還有PLD和PAL。6A01是抗熔存儲之一種,允許對多路輸入AND6A14之輸入訊號進行選擇。在該圖中,所有垂直和水平線交叉處都包含有一個抗熔存儲,使得能夠依照所需之最終功能實現連接。大的AND晶片6A14構成了乘積項,實現6A02或逆向副本之輸入選擇AND功能。一個多輸入或6A15在乘積項之選擇基礎上實現OR功能,構成一個輸出6A06。圖6A顯示了一個抗熔存儲可設定PLA邏輯器。 FIG. 6A is a schematic diagram of a PLA logic chip 6A00. This die was used in most commonly used programmable logic devices before LUT logic became mainstream. Other acronyms for such logic devices include PLD and PAL. 6A01 is a kind of antifuse memory, which allows to select the input signal of multi-channel input AND6A14. In this diagram, an antifuse is included at all intersections of vertical and horizontal lines, enabling connections according to the desired end function. The large AND chip 6A14 constitutes the product term and realizes the input selection AND function of 6A02 or the inverse copy. A multi-input OR 6A15 implements an OR function based on the selection of the product term to form an output 6A06. Figure 6A shows an antifuse programmable PLA logic.

圖5、6和6A中之邏輯晶片僅為代表。可編程邏輯器結構之建設存在很多種不同方式,包括附設邏輯晶片,如AND、MUX和其他晶片,以及上述晶片之變形。另外,邏輯晶片之建設中,也可能由於輸入和輸出連接所使用之可設定佈線電路結構或使用直接非可設定方式連接而存在形式不同。 The logic chips in Figures 5, 6 and 6A are representative only. There are many different ways of building programmable logic logic structures, including attached logic chips, such as AND, MUX and other chips, and variations of the above chips. In addition, in the construction of the logic chip, there may also be different forms due to the configurable wiring circuit structure used for the input and output connections or the use of direct non-configurable connections.

圖7為可編程晶片700之示意圖。透過平鋪上述晶片即 可建設可編程結構。相同晶片之平鋪可以使用重複之方式,形成同質結構。另外,不同晶片之混合可以形成非均勻結構。邏輯晶片700可能是圖5和圖6中之任意一種,上述之混合搭配,以及它們之前身。邏輯晶片710、輸入702和輸出706均透過輸入和輸出插接條708及相連之抗熔存儲701與可設定佈線結構720相連。較短之佈線電路722包括金屬插接條,長度與板相同,包括水平插接條722H,位於一個金屬層,垂直插接條722V,位於另一個金屬層,抗熔存儲701HV位於它們之交叉處,使得可以對水平插接條和垂直插接條和連接進行選擇。水平插接條與另外一個水平插接條之連接透過抗熔存儲701HH實現,功能與圖4中之抗熔存儲410相同。垂直插接條與另外一個垂直插接條之連接透過抗熔存儲701VV實現,功能與圖4中之抗熔存儲406相同。長水平插接條724用來連接長距離訊號,通常其長度為8個板或更多。通常一個長距離插接條都帶有一個可選連接,透過抗熔存儲724LH來縮短行程,而垂直長距離插接條則用724。圖7為可編程晶片700之二維示意圖。在實際使用時,700為三維結構,邏輯晶片710使用矽基、金屬層1、2、3。可編程佈線結構包括相連之抗熔存儲,抗熔存儲位於其表面。 FIG. 7 is a schematic diagram of a programmable chip 700 . By tiling the above wafers, the Programmable structures can be built. Tiling of the same wafer can be repeated to form a homogeneous structure. Additionally, mixing of different wafers can form non-uniform structures. The logic chip 700 may be any one of FIGS. 5 and 6 , a mix and match of the above, and their predecessors. Logic chip 710 , input 702 and output 706 are all connected to configurable wiring structure 720 through input and output strip 708 and connected antifuse memory 701 . The shorter wiring circuit 722 includes metal plug strips, the same length as the board, including horizontal plug strips 722H on one metal layer, vertical plug strips 722V on the other metal layer, and antifuse memory 701HV at their intersections , allowing selection of horizontal and vertical strips and connections. The connection between the horizontal plug strip and another horizontal plug strip is realized through the antifuse memory 701HH, which has the same function as the antifuse memory 410 in FIG. 4 . The connection between the vertical plug strip and another vertical plug strip is realized through the antifuse memory 701VV, which has the same function as the antifuse memory 406 in FIG. 4 . Long horizontal strips 724 are used to connect long distance signals, usually 8 boards or more in length. Usually a long-distance strip has an optional connection to shorten the travel through antifuse 724LH, and a vertical long-distance strip with 724. FIG. 7 is a two-dimensional schematic diagram of a programmable chip 700 . In actual use, 700 is a three-dimensional structure, and the logic chip 710 uses a silicon base and metal layers 1, 2, and 3. The programmable wiring structure includes connected antifuse on its surface.

圖8為可編程組件層結構之示意圖,為本發明之一個替代方案。在該方案中,抗熔存儲由兩層結構。第一層用於設定邏輯器區,並在某些情況下設定邏輯時鐘分配。第一抗熔存儲層也可用於管理某些功率分配,透過斷開未使 用電路之供電來節約功率。該層也可用於連接某些長距離傳輸通路和/或連接邏輯晶片之輸入和輸出。 FIG. 8 is a schematic diagram of a programmable component layer structure, which is an alternative solution of the present invention. In this scheme, the antifuse memory consists of two layers. The first level is used to set the logic region and in some cases the logic clock distribution. The first antifuse layer can also be used to manage some power distribution by disconnecting unused Use the power supply of the circuit to save power. This layer can also be used to connect certain long-distance transmission paths and/or to connect the inputs and outputs of logic chips.

組件之製造如圖8所示,從包含邏輯器晶片電晶體之半導體基片802開始,基片還包括第一抗熔存儲層可編程電晶體。接下來是804層,包括金屬層1、絕緣體、金屬層2,有時還包括金屬層3。這些層用來建設邏輯晶片,I/O和其他類比晶片。在該替代方案中,第一對抗熔存儲包含在隔離層,在金屬層1和金屬層2之間,或者包含在金屬層2和金屬層3之間之隔離層,編程電晶體可以內嵌在位於第一抗熔存儲之下之矽基片802中。第一抗熔存儲可用來對邏輯晶片編程,如520、600、700,也可用來連接各個晶片,實現更大之邏輯功能。第一抗熔存儲也可用來編輯邏輯器時鐘分配。第一抗熔存儲層也可用於管理某些功率分配,透過斷開未使用電路之供電來節約功率。該層也可用於連接某些長距離傳輸通路和/或連接這些晶片之輸入和輸出。 Fabrication of the Components As shown in Figure 8, starting with a semiconductor substrate 802 containing logic chip transistors, the substrate also includes first antifuse layer programmable transistors. Next comes 804 layers, including metal 1, insulator, metal 2, and sometimes metal 3. These layers are used to build logic chips, I/O and other analog chips. In this alternative, the first antifuse memory is contained in the isolation layer, between metal layer 1 and metal layer 2, or in the isolation layer between metal layer 2 and metal layer 3, and the programming transistor can be embedded in the It is located in the silicon substrate 802 under the first antifuse memory. The first antifuse memory can be used to program logic chips, such as 520, 600, 700, and can also be used to connect each chip to achieve greater logic functions. The first antifuse can also be used to program the logic clock distribution. The first antifuse layer can also be used to manage some power distribution, saving power by disconnecting power from unused circuits. This layer can also be used to connect certain long-distance transmission paths and/or to connect the inputs and outputs of these chips.

以下幾層806,可構成長距離佈線通道,用於全部或部分之功率分配和時鐘網路,形成對前幾層804中結構之補充。 The following layers 806 can form long-distance wiring channels for all or part of the power distribution and clock networks, forming a supplement to the structures in the previous layers 804 .

以下基層807可包含抗熔存儲可設定佈線結構。也可稱之為短距離佈線結構。如果金屬層6和7用於該可設定佈線結構的插接條,第二抗熔存儲則可內嵌在層6和層7之間的絕緣層中。 The underlying base layer 807 may include an antifuse programmable wiring structure. It can also be called a short-distance wiring structure. If metal layers 6 and 7 are used for the plug strips of the configurable wiring structure, the second antifuse can be embedded in the insulating layer between layers 6 and 7 .

編程電晶體和編程電路之其他部分可用於後續製造, 在可設定佈線結構810之上。編程組件可以是薄膜電晶體或前述之其他過氧化物電晶體。此時,抗熔存儲編程電晶體佈置在抗熔層上方,為可設定佈線電路808或804之實現提供可能。需要注意的是,在某些情況下,在基層802和804上建設第二抗熔存儲編程電路之控制邏輯器是有益的。 The programming transistors and other parts of the programming circuit can be used in subsequent manufacturing, above the configurable wiring structure 810 . The programming element can be a thin film transistor or other peroxide transistors mentioned above. At this time, the antifuse memory programming transistor is disposed above the antifuse layer, which makes it possible to implement the configurable wiring circuit 808 or 804 . It should be noted that in some cases it may be beneficial to build the control logic of the second antifuse programming circuit on the base layers 802 and 804 .

最後一步是與外部812之連接。可以使用焊點進行絲焊、也可使用焊球連接倒裝晶片、光電或其他連接結構,例如TSV連接。 The final step is the connection to the external 812. Solder joints can be used for wire bonding, and solder balls can be used for flip-chip, optoelectronic or other connection structures such as TSV connections.

在本項發明之另一替代方案中,抗熔存儲可編程佈線結構可用來設定多種用途。相同之結構可以作為佈線結構之一部分,或者PLA邏輯晶片之一部分,也可以作為唯讀存儲(ROM)功能之一部分。在FPGA產品中,可能需要一個組件能夠用於多個用途。配備多功能之系統資源可以增加FPGA組件之實用性。 In another alternative of the present invention, the antifuse programmable wiring structure can be used for multiple purposes. The same structure can be used as part of the wiring structure, or as a part of the PLA logic chip, or as a part of the read-only memory (ROM) function. In FPGA products, it may be necessary for a component to be able to serve multiple purposes. Equipping system resources with multiple functions can increase the utility of FPGA components.

圖8A為可編程組件層結構之示意圖,為本發明之另一個替代方案。在該替代方案中,有一個附設之電路814,與816接觸連接,至第一抗熔層804。由下方的組件提供第一抗熔存儲層804的編程電晶體。這樣,可編程組件之擴散層816就不用承擔第一抗熔層804編程電晶體之成本。相應的,第一抗熔層804之編程連接就可以直接向下與下方編程組件804相連,同時與第二抗熔層807之編程連接則可以直接向上與編程電路810相連。這樣就可以在電路內部之佈線路徑上減少擁堵。 FIG. 8A is a schematic diagram of a programmable component layer structure, which is another alternative solution of the present invention. In this alternative, there is an attached circuit 814 contacting 816 to the first antifuse layer 804 . The programming transistors of the first antifuse layer 804 are provided by the underlying components. In this way, the diffusion layer 816 of the programmable device does not need to bear the cost of the programming transistor of the first antifuse layer 804 . Correspondingly, the programming connection of the first antifuse layer 804 can be directly connected downward to the lower programming component 804 , while the programming connection to the second antifuse layer 807 can be directly connected upward to the programming circuit 810 . This reduces congestion on the wiring paths inside the circuit.

後續圖中之編號808可以是各種預處理晶圓或層之組合,晶圓或層包含多個本項發明所述之傳輸層(組合)。片語“預處理晶圓或層”為泛指;當在圖紙中使用編號808來說明本項發明之案例時,編號808可代表多個不同之預處理晶圓或層類型,包括但不限於下層預製造層、下層佈線絲線、基層、基片層、外殼晶圓、目標晶圓、預處理電路、預處理電路接受器晶圓、基片晶圓層、底層、底層主晶圓、基礎層、頂層、或廠晶圓。 Reference number 808 in subsequent figures may be a combination of various pre-processed wafers or layers, and the wafers or layers include multiple transport layers (combinations) described in this invention. The phrase "preprocessed wafer or layer" is generic; when reference number 808 is used in the drawings to illustrate examples of the invention, reference number 808 may represent a number of different preprocessed wafer or layer types, including but not limited to Lower prefab layer, lower wiring filaments, base layer, substrate layer, housing wafer, target wafer, pre-processing circuit, pre-processing circuit receiver wafer, substrate wafer layer, bottom layer, bottom master wafer, base layer , top layer, or fab wafer.

圖8B為通用預處理晶圓或808層。晶圓或808層可能含有預處理電路,例如,邏輯電路、微型處理器、包含各種電晶體之電路、其他類型數位或類比電路,包括且不限於本發明中之各種案例。預處理晶圓或808層可能含有預處理金屬佈線電路,可能由銅或鋁製成。預處理金屬佈線電路可能用於層傳輸之設定或製造,還包括從預處理晶圓或808層至該層或傳輸層之電氣連接。 Figure 8B is a generic preprocessed wafer or layer 808. The wafer or 808 layer may contain pre-processing circuits, such as logic circuits, microprocessors, circuits including various transistors, other types of digital or analog circuits, including but not limited to various cases in the present invention. The preprocessed wafer or 808 layer may contain preprocessed metal wiring circuits, possibly made of copper or aluminum. Preprocessed metal wiring circuits may be used for layer transport setup or fabrication, including electrical connections from the preprocessed wafer or layer 808 to that layer or transport layer.

圖8C為通用傳輸層809在加工到預處理晶圓或808層之前之示意圖。傳輸層809在層切過程中可以加工到載體晶圓或基片晶圓上。預處理晶圓或808層可以成為目標晶圓、接受器基片或接受器晶圓。接受器晶圓可以含有接受器晶圓金屬連接焊點或插接條,設定製造用於與傳輸層809之電氣連接。傳輸層809在層切過程中可以加工到載體晶圓或基片晶圓上。傳輸層809可以含有金屬佈線電路,設定製造用於與預處理晶圓或808層之間的層傳輸或電氣連接。從傳輸層809到預處理晶圓或808層之間之電氣連接 可以使用穿層過孔(TLV)連接。傳輸層809可以包含單晶矽、結晶矽、或可預測結晶矽單層或多層、其他半導體、金屬和絕緣體材料、層等;或者多個單晶矽區域、可預測單晶矽、或其他半導體、金屬、或絕緣體材料。 FIG. 8C is a schematic diagram of the universal transport layer 809 before being processed into the preprocessed wafer or layer 808 . The transfer layer 809 may be processed onto a carrier wafer or a substrate wafer during a layer dicing process. The preprocessed wafer or layer 808 can become the target wafer, receptor substrate or receptor wafer. The susceptor wafer may contain susceptor wafer metal connection pads or straps configured to make electrical connections to the transport layer 809 . The transfer layer 809 may be processed onto a carrier wafer or a substrate wafer during a layer dicing process. The transfer layer 809 may contain metal wiring circuits configured to be fabricated for layer transfer or electrical connection to the pre-processed wafer or to the 808 layer. Electrical connections from transport layer 809 to preprocessed wafer or between layers 808 Through Layer Via (TLV) connections may be used. Transport layer 809 may comprise monocrystalline silicon, crystalline silicon, or predictable crystalline silicon single or multiple layers, other semiconductor, metal and insulator materials, layers, etc.; or multiple regions of monocrystalline silicon, predictable monocrystalline silicon, or other semiconductor , metal, or insulator materials.

圖8D為預處理晶圓或808層由上方的傳輸層809經過層切形成之示意圖。預處理晶圓或808層之上方,可以進一步加工出預處理金屬佈線電路可能用於層傳輸之設定製造,還包括從預處理晶圓或808層至該層或傳輸層之電氣連接。 FIG. 8D is a schematic diagram of a preprocessed wafer or layer 808 formed by layer dicing from an upper transport layer 809 . Above the pre-processed wafer or layer 808, pre-processed metal wiring circuits may be further processed for the setting and manufacture of layer transfer, including electrical connections from the pre-processed wafer or layer 808 to this layer or transfer layer.

圖8E為通用傳輸層809A在加工到預處理晶圓或808A層之前之示意圖。傳輸層809A在層切過程中可以加工到載體晶圓或基片晶圓上。傳輸層809A可以含有金屬佈線電路,設定製造用於與預處理晶圓或808A層之間之層傳輸或電氣連接。 FIG. 8E is a schematic diagram of the universal transport layer 809A prior to processing into a preprocessed wafer or layer 808A. The transfer layer 809A may be processed onto a carrier wafer or a substrate wafer during a layer dicing process. The transfer layer 809A may contain metal wiring circuits designed to be fabricated for layer transfer or electrical connection to the preprocessed wafer or to the layer 808A.

圖8F為預處理晶圓或808B層由上方之傳輸層809A經過預處理晶圓或層808A之層切形成。預處理晶圓或808B層之上方,可以進一步加工出預處理金屬佈線電路可能用於層傳輸之設定製造,還包括從預處理晶圓或808B層至該層或傳輸層之電氣連接。 FIG. 8F shows a pre-processed wafer or layer 808B formed from the upper transfer layer 809A by layer dicing of the pre-processed wafer or layer 808A. Above the pre-processed wafer or 808B layer, pre-processed metal wiring circuits may be further processed for the setting and manufacture of layer transfer, including electrical connections from the pre-processed wafer or 808B layer to this layer or transfer layer.

圖8G為通用傳輸層809B在加工到預處理晶圓或808B層之前之示意圖。傳輸層809B在層切過程中可以加工到載體晶圓或基片晶圓上。傳輸層809B可以含有金屬佈線電路,設定製造用於與預處理晶圓或808B層之間之層傳輸或電氣連接。 FIG. 8G is a schematic diagram of the generic transport layer 809B prior to processing into a preprocessed wafer or layer 808B. The transfer layer 809B may be processed onto a carrier wafer or a substrate wafer during a layer dicing process. The transport layer 809B may contain metal wiring circuits designed to be fabricated for layer transport or electrical connection between the pre-processed wafer or the 808B layer.

圖8H為預處理晶圓或808C層由上方之傳輸層809B經過預處理晶圓或層808B的層切形成。預處理晶圓或808C層之上方,可以進一步加工出預處理金屬佈線電路可能用於層傳輸之設定製造,還包括從預處理晶圓或808C層至該層或傳輸層之電氣連接。 FIG. 8H shows a pre-processed wafer or layer 808C formed from the upper transfer layer 809B through layer dicing of the pre-processed wafer or layer 808B. Above the pre-processed wafer or 808C layer, pre-processed metal wiring circuits may be further processed for the setting and manufacture of layer transfer, including electrical connections from the pre-processed wafer or 808C layer to this layer or transfer layer.

圖8I為預處理晶圓或808C層,一個3D IC堆,可包含經過切除之層809A和809B,位於預處理晶圓或層808之上。切出層809A和809B以及初始之預處理晶圓或808層中之一層或多層可能包含一種或多種類型之電晶體,金屬噴鍍,如一層或多層包含銅或鋁,層間上下佈線電路,以及層內佈線電路。層與層之間,一層之內之電晶體可以是不同之類型。電晶體之佈置也可有多種方式。電晶體之佈置可以是重複佈置或帶狀佈置。電晶體可以在傳輸層內之多層進行佈置。電晶體之佈置可以是無極電晶體或凹槽通路電晶體。切出層809A和809B,以及預處理晶圓或808層還可以包含半導體組件,例如電阻、電容、電感,一個或多個可編程佈線電路,儲存結構和組件、感測器、微波組件、與微波收發器相連之光電佈線電路名詞“載體晶圓”或“載體基片”也可成為“支撐晶圓”或“支撐基片”。 FIG. 8I shows a pre-processed wafer or layer 808C, a 3D IC stack, which may include ablated layers 809A and 809B, on top of the pre-processed wafer or layer 808. One or more layers of cut-out layers 809A and 809B and the initial pre-processed wafer or layer 808 may include one or more types of transistors, metallization, such as one or more layers including copper or aluminum, upper and lower wiring circuits between layers, and In-layer wiring circuits. The transistors within a layer can be of different types between layers. Transistors can also be arranged in various ways. The arrangement of transistors can be a repeat arrangement or a strip arrangement. Transistors can be arranged in multiple layers within the transport layer. The arrangement of transistors can be electrodeless transistors or trench via transistors. Cut out layers 809A and 809B, and preprocessed wafer or layer 808 may also contain semiconductor components such as resistors, capacitors, inductors, one or more programmable wiring circuits, storage structures and components, sensors, microwave components, and The photoelectric wiring circuit term "carrier wafer" or "carrier substrate" connected to the microwave transceiver can also be called "support wafer" or "support substrate".

層切工藝可以重複使用多次,從而生產出包含多個切出層之預處理晶圓,這些晶圓組合起來還可以作為預處理晶圓或層繼續進行層切。層切工藝具有足夠之靈活性,使得預處理晶圓和傳輸層在適當之製造插接條件下,可以翻轉並在任意一面切割,依照設定選擇在任何方向上繼續進 行切割。 The layer-slicing process can be reused multiple times to produce pre-processed wafers containing multiple cut-out layers that can be combined as pre-processed wafers or layers for further layer-slicing. The layer-slicing process is flexible enough that the pre-processed wafer and transfer layer can be turned over and cut on any side under appropriate manufacturing insertion conditions, and continue in any direction according to the set selection line cutting.

僅具有基礎知識之人員將會很容易理解圖8-圖8I中之舉例說明(並未放大)。同時,人們也會進一步意識到,以預處理晶圓或808層作為基礎或基片層,或是以作為預處理或部分預處理電路接受器晶圓,使用晶圓切除流程,可以產生更多之變形。人們在讀完本說明之後,將會意識到本項發明範圍將會囊括非常多之修改變形。因此,本項發明並非僅限於附件中之專利權聲明。 Those with only basic knowledge will easily understand the illustrations in Figures 8-8I (not enlarged). At the same time, there will be further realization that more of deformation. After reading this description, people will realize that the scope of the present invention will include many modifications and variations. Therefore, this invention is not limited to the patent statement in the appendix.

這種下層電路之替代技術是“SmartCut”智慧切割工藝。“SmartCut”智慧切割工藝廣泛應用於製造SOI晶圓。智慧切割工藝,加上晶圓黏結技術,使得“層切”能夠從一個又一個之晶圓上製造出一薄層單晶矽晶圓。“層切”可以在400攝氏度以下完成,生產出之切出層可以小於100nm厚。具有多個變形和名稱之工藝已經用於商用之公司有兩個,即Soitec(Crolles,法國)和SiGen-Silicon Genesis公司(聖何塞,加州)。室溫下之矽片黏結流程使用粒子束在真空下處理矽表面,最近已由三菱重工集團(日本,東京)壟斷。該工藝能夠在室溫下切割矽片層。 The alternative technology for this underlying circuit is the "SmartCut" intelligent cutting process. The "SmartCut" intelligent cutting process is widely used in the manufacture of SOI wafers. The smart dicing process, coupled with wafer bonding technology, enables "layer dicing" to produce a thin layer of monocrystalline silicon wafers from one wafer after another. "Layer cutting" can be completed below 400 degrees Celsius, and the cut layer produced can be less than 100nm thick. Two companies, Soitec (Crolles, France) and SiGen-Silicon Genesis (San Jose, CA), have commercialized the process with several variants and names. The silicon wafer bonding process at room temperature, which uses a particle beam to treat the silicon surface under vacuum, has recently been monopolized by Mitsubishi Heavy Industries (Tokyo, Japan). The process is able to cut silicon wafer layers at room temperature.

另外,使用中還包括其他技術。例如,其他技術也可用於層切,例如IBM層切工藝,如IEDM2005,A.W.Topol等所述。IMB之層切工藝使用了一個SOI技術和玻璃基片晶圓。供電電路可以在SOI晶圓上經過高溫處理,臨時黏結到硼矽玻璃基片晶圓上,使用化學機械打磨將背面打薄,然後將埋入氧化物(BOX)蝕刻掉。此時,對打薄之 供電晶圓進行對準,低溫氧化物黏結至接受晶圓表面。然後將打薄供電晶圓從玻璃基片晶圓上分離,加工穿層過孔連接。另外,累晶移植(ELO)技術,如P.Demeester等所述,由IMEC在半導體科學技術1993年期中發佈,也可以用於層切。ELO將基片和待切層之間非常薄之犧牲層有選擇性之去除。GaAs或矽待切層可以使用黏性圓柱“滾”起來,或使用柔性載體從基片上去除,例如黑蠟,將待切層結構提起,這一過程與選擇性蝕刻同時發生,蝕刻可以使用稀釋之氫氟(HF)酸、將表面需要脫離之層清除掉,脫離層可以是SOI或AlAs之矽氧化物。在累晶移植之後,切出層就與所需之接受基片或晶圓對準並黏結。ELO工藝在多層層切使用中之生產能力由J.Yoon等進行了改進,J.Yoon來自伊利諾伊大學的香檳分校,文章發表在2010年5月20日之自然雜誌上。Canon開發了一種層切技術,稱之為ELTRAN-多孔矽晶膜層切。也可使用ELTRAN。依照電化學協會會議摘要No.438,2000年,和2001年7月的JSAP國際論文顯示,經過HF/乙醇溶液氧化之種子晶圓能夠在矽之表層產生氣孔,氣孔可以使用低溫氧化進行處理,然後使用高溫下之氫還原來密封氣孔。然後可以將矽晶膜放置在多孔矽上,氧化形成SOI BOX。種子晶圓可以與基片晶圓黏結,並使用高壓水對準多孔矽層,將種子晶圓分裂。多孔矽然後可以進行選擇性蝕刻,形成緻密之矽層。 Additionally, there are other techniques in use. For example, other techniques can also be used for layer dicing, such as the IBM layer dicing process, as described in IEDM2005, A.W. Topol et al. IMB's layer dicing process uses an SOI technology and a glass substrate wafer. The power supply circuit can be processed at high temperature on the SOI wafer, temporarily bonded to the borosilicate glass substrate wafer, chemical mechanical polishing is used to thin the backside, and the buried oxide (BOX) is etched away. At this time, against the thin The power supply wafer is aligned and the low temperature oxide is bonded to the surface of the receiving wafer. The thinned power supply wafer is then separated from the glass substrate wafer, and through-layer via connections are processed. In addition, the ELO technique, as described by P. Demeester et al., published by IMEC in Semiconductor Science and Technology 1993, can also be used for layer dicing. ELO selectively removes the very thin sacrificial layer between the substrate and the layer to be cut. The GaAs or Si to-be-cut layer can be "rolled" with an adhesive cylinder, or removed from the substrate using a flexible carrier, such as black wax, to lift the to-be-cut layer structure. This process occurs at the same time as selective etching, which can be dilute Hydrofluoric (HF) acid to remove the layer that needs to be released from the surface. The release layer can be silicon oxide of SOI or AlAs. After stack transfer, the cutout layer is aligned and bonded to the desired receiving substrate or wafer. The productivity of the ELO process in multilayer slicing was improved by J. Yoon et al., J. Yoon from the University of Illinois at Urbana-Champaign. The article was published in Nature on May 20, 2010. Canon has developed a layer cutting technology called ELTRAN-porous silicon film layer cutting. ELTRAN can also be used. According to the Electrochemical Society Conference Abstract No.438, 2000, and JSAP International Papers in July 2001, the seed wafer oxidized by HF/ethanol solution can generate pores on the surface of silicon, and the pores can be treated by low temperature oxidation. The pores are then sealed using hydrogen reduction at high temperature. Then silicon crystal film can be placed on the porous silicon and oxidized to form SOI BOX. The seed wafer can be bonded to the substrate wafer, and the seed wafer can be split by aligning the porous silicon layer with high pressure water. The porous silicon can then be selectively etched to form a dense silicon layer.

圖14為層切流程之示意圖。在該項發明的另外一個替代方案中,“層切”被用於構造下層電路814。1402是一個 經過處理,用於構造底層電路之晶圓。晶圓1402可以用於大多數先進工藝,或最近幾代之工藝。它可以含有編程電路814,以及其他有用之結構,並能作為預處理CMOS矽晶圓,或部分處理CMOS,或其他製造用矽或半導體基片。晶圓1402也可以稱之為接受基片或目標晶圓。隨後,一個氧化層1412將被佈置在晶圓1402上,進行打磨,達到更好之正平和表面等級。然後將供電晶圓1406黏結到1402上。供電晶圓1406和晶圓1402之表面都使用各種表面處理方式進行了預處理,可用於低溫黏結,表面處理包括RCA預清理,其中可能包含稀釋之氫氧化銨或氫氯酸,也可能包括電漿表面處理,以降低黏結能量並提高晶圓-晶圓之黏結強度。供電晶圓1406經過粒子植入之智慧切割作為預處理,原子類型可能包括H+離子,所需之深度依照智慧切割1408之刻線而定。智慧切割刻線1408可以成為層切劃分平面,如虛線所示。智慧切割刻線1408或層切劃分平面可以在供電晶圓1406之處理之前或之後形成。供電晶圓1406可以黏結到晶圓1402上,透過將供電晶圓1406之表面與晶圓1402之表面接觸,然後施加機械力和/或退火還原來強化氧化物-氧化物之鍵。供電晶圓1406與晶圓1402之對準可以在晶圓黏結之後馬上進行。包括退火黏結循環在內,可以接受之鍵強度大約不能超過400℃。在黏結兩個晶圓之後,進行智慧切割,沿切割層1408來切開並清除供電晶圓1406之頂部1414。切開可以使用各種能量方式,切至智慧切割線1408或層切劃分平面,包括小刀之機械切割,水 流衝擊、空氣切割,或現場鐳射退火或其他適宜之方式。得到一個3D晶圓1410,包含晶圓1402和單晶矽(或是多層材料之)附設層1404。層1404可以透過化學或機械之方法打磨,達到適宜之表面品質,供後續加工。層1404可以非常薄,大約在50-200nm之間。上述所需之流程稱之為“層切”。層切通常在SOI製造過程中使用,SIO即絕緣矽晶片。對於SOI晶圓,上表面已經氧化,使得在“層切”之後,獲得埋入氧化物-BOX,將頂層薄單晶矽層和晶片主體隔離。使用植入原子,例如氫或氦或氫氦混合物,能夠產生上述切割平面,在本檔中也做“離子-切割”,是層切方法之優選方案。 Fig. 14 is a schematic diagram of the layer cutting process. In another alternative of the invention, "layer cuts" are used to construct the underlying circuitry 814. 1402 is a After processing, the wafer used to construct the underlying circuit. Wafer 1402 can be used for most advanced processes, or recent generations of processes. It can contain programming circuitry 814, among other useful structures, and can serve as a pre-processed CMOS silicon wafer, or partially processed CMOS, or other silicon or semiconductor substrate for fabrication. Wafer 1402 may also be referred to as a receiver substrate or target wafer. Subsequently, an oxide layer 1412 will be placed on the wafer 1402 and polished to achieve a better planarity and surface grade. Power supply die 1406 is then bonded to 1402 . The surfaces of power supply wafer 1406 and wafer 1402 are pre-treated with various surface treatments for low temperature bonding, including RCA pre-cleaning, which may include diluted ammonium hydroxide or hydrochloric acid, and may include electrical Slurry surface treatment to reduce bonding energy and improve wafer-to-wafer bonding strength. The power supply wafer 1406 is preprocessed by smart dicing of particle implantation. The atomic type may include H+ ions, and the required depth depends on the scribe line of the smart dicing 1408 . The smart cutting line 1408 can become a layer cutting dividing plane, as shown by the dotted line. The smart dicing scribe lines 1408 or layer cut dividing planes can be formed before or after the power supply wafer 1406 is processed. The power wafer 1406 can be bonded to the wafer 1402 by contacting the surface of the power wafer 1406 with the surface of the wafer 1402, followed by mechanical force and/or annealing to strengthen the oxide-oxide bond. Alignment of power wafer 1406 to wafer 1402 may be performed immediately after wafer bonding. Including the annealing bond cycle, the acceptable bond strength should not exceed approximately 400°C. After bonding the two wafers, smart dicing is performed to cut and remove the top 1414 of the power supply wafer 1406 along the dicing layer 1408 . Cutting can use various energy methods, cutting to the intelligent cutting line 1408 or layer cutting division plane, including mechanical cutting with knife, water flow impact, air cutting, or on-site laser annealing or other suitable methods. A 3D wafer 1410 is obtained, including a wafer 1402 and a monocrystalline silicon (or multi-layer material) additional layer 1404 . The layer 1404 can be polished by chemical or mechanical methods to achieve a suitable surface quality for subsequent processing. Layer 1404 can be very thin, on the order of 50-200 nm. The process required above is called "layer cutting". Layer dicing is commonly used in the SOI manufacturing process, SIO stands for silicon-on-insulator wafer. For SOI wafers, the top surface has been oxidized such that after "layer dicing" a buried oxide-BOX is obtained, isolating the top thin monocrystalline silicon layer from the body of the wafer. The use of implanted atoms, such as hydrogen or helium or a mixture of hydrogen and helium, can produce the above-mentioned cutting planes, also referred to as "ion-cutting" in this document, which is the preferred version of the layer cutting method.

僅具有基礎知識之人們也會很容易理解圖14-圖中之舉例說明(並未放大)。一般情況下,人們可以進一步認識到,例如深度摻雜(大於le20原子/cm3)之硼層或矽鍺(SiGe)層可用作蝕刻止點,用於離子-切割工藝流程中,層切割劃分平面可以置於蝕刻中止層或置於基片材料以下,或者可以在無植入切割流程時蝕刻中止層,或者施主晶圓可優先蝕刻,直到達到蝕刻中止層。人們還可以進一步認識到,SOI或GeOI施主晶圓中之氧化物可用作蝕刻中止層。人們在讀完本說明之後,將會意識到本項發明範圍將會囊括非常多之修改變化。因此,本項發明並非僅限於附件中之專利權聲明。 People with only basic knowledge will also easily understand Figure 14 - the illustration in the diagram (not enlarged). In general, one can further realize that, for example, a deeply doped (greater than le20 atoms/cm3) boron layer or silicon germanium (SiGe) layer can be used as an etch stop for ion-dicing process flow, layer cutting division The plane can be placed on the etch stop layer or below the substrate material, or the etch stop layer can be used in a non-implant dicing process, or the donor wafer can be preferentially etched until the etch stop layer is reached. It is further recognized that oxides in SOI or GeOI donor wafers can be used as etch stop layers. After reading this description, people will realize that the scope of the present invention will include many modifications and changes. Therefore, this invention is not limited to the patent statement in the appendix.

因此,“層切”工藝可以用來在預處理晶圓1402上黏結一個薄單晶矽層1404,一個標準流程即可確保構件如圖8A 所示所需電路之剩餘部分,從切出層1404上之層802開始。印刷步驟會使用晶圓1402上之對準標記,使得電路802和816等能夠與下層電路814對應相連。需要注意之一個因素就是高溫,在處理電路802之過程中可能會需要高溫環境。晶圓1402上之預處理電路需要承受高溫,高溫用於開啟在層1404上構造之半導體電晶體802。晶圓1402上之電路將包含電晶體和多晶矽局部佈線電路(多晶矽或多聚物)以及一些其他類型可以承受高溫之電路,如鎢(電路)。處理過之晶圓可以在高溫下支撐後面加工之電晶體,該晶圓可稱為“基礎”或基片、基礎層、基礎電路。使用層切建設下層電路之優勢在於可以將層切後之1404做之非常薄,使得穿矽過孔連接816、或穿層過孔(TLV)具有低高寬比,並能更接近正常觸點,因此可以做非常之小,將開支面積降至最低。較薄之切出層還能使用傳統直接穿層對準技術,可以增加矽過孔連接816之密度。 Therefore, the "layer cut" process can be used to bond a thin single crystal silicon layer 1404 on the preprocessed wafer 1402, a standard process can ensure that the components shown in Figure 8A The remainder of the required circuitry is shown starting with layer 802 above cut-out layer 1404 . The printing step uses the alignment marks on the wafer 1402 so that the circuits 802 , 816 , etc. can be connected to the underlying circuit 814 . One factor to be aware of is high temperature, which may be required during processing of circuit 802 . The preprocessing circuits on wafer 1402 need to withstand the high temperatures used to turn on semiconductor transistors 802 built on layer 1404 . The circuits on wafer 1402 will include transistors and polysilicon local wiring circuits (polysilicon or poly) and some other type of circuits that can withstand high temperatures, such as tungsten (circuits). The processed wafer can support the transistors processed later at high temperature, and the wafer can be called "base" or substrate, base layer, base circuit. The advantage of using layer cutting to build the underlying circuit is that the layer cutting 1404 can be made very thin, so that the through-silicon via connection 816, or the through-layer via (TLV) has a low aspect ratio and can be closer to the normal contact. , so it can be made very small to minimize the area of expenditure. The thinner cut-out layer can also use the conventional direct through-layer alignment technique, which can increase the density of the via connection 816 .

圖15為底層編程電路之示意圖。變成電晶體1501和1502均在基片1402上預製,然後再在切出層1404上加工出可編程邏輯電路和抗熔存儲1504。編程連接1506、1508利用穿過層1404的接觸孔與編程電晶體相連,如圖8A中816所示。變成電晶體設定承受抗熔存儲1504編程時之較高編程電壓。 Figure 15 is a schematic diagram of the underlying programming circuit. Both the transistors 1501 and 1502 are prefabricated on the substrate 1402 , and then the programmable logic circuit and the antifuse memory 1504 are processed on the cut-out layer 1404 . Programming connections 1506, 1508 are connected to programming transistors using contact holes through layer 1404, as shown at 816 in FIG. 8A. The transistor is set to withstand a higher programming voltage when the antifuse 1504 is programmed.

圖16為底層隔離電晶體電路之示意圖。將抗熔存儲1604變成之高電壓可能損害邏輯電晶體1606、1608。為了保護這些邏輯電路,隔離電晶體1601、1602,所以設定電 晶體能夠承受較高電壓。較高之編程電壓僅在編程階段使用,同時隔離電晶體透過控制電路1603關閉。下層晶圓1402可以用來建設隔離電晶體。由於基片1402上之編程電晶體和隔離電晶體較大,使得可以更好之利用初晶矽802(1404)。通常初晶矽都在前期工藝中製造,以得到高密度和性能。基片可以在稍後之工藝步驟中製造,可減少成本並支撐高電壓電晶體。也可以不與CMOS電晶體一起加工,例如與雙重擴散金屬氧化物半導體(DMOS)或雙極節電晶體一起加工,這樣做有利於變成和隔離功能。在大多數情況下,柵極輸入均需要保護二極體,稱為天線。這樣之保護澱積可以有效之將隔離電晶體的輸入整合至基片中。另外,隔離電晶體1601、1602也可提供天線效應之保護,無需額外之二極體。 FIG. 16 is a schematic diagram of the bottom isolation transistor circuit. Bringing the antifuse 1604 to a high voltage may damage the logic transistors 1606,1608. In order to protect these logic circuits, the transistors 1601, 1602 are isolated, so setting the voltage Crystals can withstand higher voltages. The higher programming voltage is only used during the programming phase, while the isolation transistor is turned off by the control circuit 1603 . The lower wafer 1402 can be used to build isolation transistors. Since the programming transistors and isolation transistors on the substrate 1402 are larger, better utilization of the primary silicon 802 (1404) is possible. Usually primary silicon is manufactured in the front-end process to obtain high density and performance. The substrate can be fabricated in a later process step, reducing cost and supporting high voltage transistors. It can also be processed without CMOS transistors, such as double-diffused metal oxide semiconductor (DMOS) or bipolar transistors, which is beneficial to switching and isolation functions. In most cases, the gate input requires a protective diode, called an antenna. Such a protective deposition can effectively integrate the input of the isolation transistor into the substrate. In addition, the isolation transistors 1601, 1602 can also provide antenna effect protection without additional diodes.

本項發明之另一個替代方案案例是將基礎層1402進行預處理,加工出一對逆偏壓發生器。先進半導體邏輯組件之一個主要挑戰是晶片-晶片和晶片內之參數偏差。由於摻雜物等原因,晶片之各個部分可能具有不同之導電特性。這些參數中對偏差影響最大的是電晶體的闕值電壓。晶片內闕電壓之差異主要由於溝道摻雜物、柵極絕緣體、關鍵尺寸差異造成。這些差異對於次45nm工藝節點組件之影響是巨大的。通常之處理思路是,設定時應考量最壞情況,造成較大之性能開支。另外,目前正在提出全新之設定思路,來解決偏差問題造成之產能和成本的巨大不確定性。可能的方案包括使用局部逆偏壓,來提高最壞區域 之性能,在消耗最小額外功率的前提下提升整體性能。基礎-局部逆偏壓也可用來減少由於工藝偏差造成之漏電。 Another alternative example of the present invention is to preprocess the base layer 1402 to produce a pair of reverse bias voltage generators. One of the major challenges of advanced semiconductor logic devices is die-to-die and intra-die parametric variation. Parts of the wafer may have different conductive properties due to dopants and the like. The most influential of these parameters on bias is the threshold voltage of the transistor. The difference in gate voltage within the wafer is mainly caused by differences in channel dopants, gate insulators, and critical dimensions. The impact of these differences on sub-45nm process node components is enormous. The usual solution is to consider the worst case when setting, resulting in a large performance cost. In addition, a new setting idea is currently being proposed to solve the huge uncertainty of production capacity and cost caused by the deviation problem. Possibilities include using localized reverse bias to increase the worst-case The performance can improve the overall performance under the premise of consuming the minimum extra power. Base-local reverse bias can also be used to reduce leakage due to process variations.

圖17A為逆偏壓電路之拓撲示意圖。基板1402承載逆偏壓電路1711,能夠提高初晶組件部分區域1710之性能,否則這些區域之性能將維持較低水準。 FIG. 17A is a topological schematic diagram of a reverse bias circuit. The substrate 1402 carries a reverse bias circuit 1711, which can improve the performance of some regions 1710 of the primary crystal device, which would otherwise maintain a lower level of performance.

圖17B為逆偏壓電路之示意圖;逆偏壓控制電路1720控制振盪器1727和1729,從而驅動逆偏壓發生器1721。負逆偏壓發生器1725將產生所需之負偏壓,透過連接1723,與主電路相連,向初晶矽1404上之N-溝道金屬氧化物半導體(NMOS)電晶體1732提供逆偏壓。正逆偏壓發生器1726將產生所需之負偏壓,透過連接1724,與主電路相連,向初晶矽1404上之P-溝道金屬氧化物半導體(PMOS)電晶體1724提供逆偏壓。相應逆偏壓之大小依照所在區域在初始化階段設定。可以使用外部測試器和控制器設定,也可以使用片載自測試電路完成。通常,使用永久性儲存來保存各區域之逆偏壓大小,使得組件在開啟時就能夠正常初始化。另外,可以使用動態計劃來給不同運行模式之組件設定所需之逆偏壓大小。在基板中設定逆偏壓電路可以更好利用初晶組件之矽片資源,使得主片組件之邏輯運行失真更少。 17B is a schematic diagram of a reverse bias circuit; a reverse bias control circuit 1720 controls oscillators 1727 and 1729 to drive a reverse bias generator 1721 . Negative reverse bias voltage generator 1725 will generate the required negative bias voltage, connect to the main circuit through connection 1723, and provide reverse bias voltage to N-channel metal oxide semiconductor (NMOS) transistor 1732 on primary silicon 1404 . The forward and reverse bias voltage generator 1726 will generate the required negative bias voltage, connect with the main circuit through the connection 1724, and provide reverse bias voltage to the P-channel metal oxide semiconductor (PMOS) transistor 1724 on the primary crystal silicon 1404 . The size of the corresponding reverse bias voltage is set in the initialization phase according to the region. It can be programmed using an external tester and controller, or it can be done using the on-chip self-test circuit. Usually, non-volatile storage is used to save the reverse bias voltage of each region, so that the device can be initialized normally when it is turned on. In addition, dynamic planning can be used to set the required reverse bias voltage for devices in different operating modes. Setting the reverse bias circuit in the substrate can make better use of the silicon chip resources of the primary device, making the logic operation of the main chip device less distorted.

圖17C為替代方案電路功能,也可用於“基礎”。在很多IC設定中,需要整合功率控制,減少對組件部分磁區之供電,或者當這些磁區完全處於“睡眠”狀態時,將相應的供電切斷。通常,這些供電控制最好使用高電壓電晶 體來完成。因此,基板上可能需要建設一個功率控制電路晶片17C02。功率控制17C02可使用自身之高電壓供電和控制或調整主片組件上17C10和17C08磁區之供電電壓。控制可以透過主片組件17C16出發,由基板上之17C04管理。 Figure 17C is an alternative circuit function that can also be used for "basics". In many IC configurations, it is necessary to integrate power control to reduce the power supply to some magnetic regions of the component, or to cut off the corresponding power supply when these magnetic regions are completely in the "sleep" state. Usually, these supply controls are best used with high voltage transistor body to complete. Therefore, a power control circuit chip 17C02 may need to be built on the substrate. The power control 17C02 can use its own high voltage power supply and control or adjust the power supply voltage of the 17C10 and 17C08 magnetic areas on the main chip assembly. Control can be initiated through the main chip component 17C16 and managed by 17C04 on the base board.

圖17D為替代方案電路功能,也可用於“基礎”。在很多IC設定中,需要整合探頭輔助系統,使得在調試階段能夠很容易探測組件,並支持生產測試。探頭電路在現有技術中也有使用,使用與主電路相同之電晶體。圖17D顯示了在基板上初晶層有源電路之下建設之探頭電路。圖17D顯示了與連續有源電路組件17D02之連接。連接透過互聯電路17D06與基板相連,高阻探頭電路17D08用於檢測後續組件之輸出。選擇電路17D12允許一個或多個輸出透過一個或以上緩衝器17D16傳出,緩衝器可由初晶電路上之訊號控制,從而驅動順序輸出訊號至探頭訊號輸出17D14,以便調試或測試。人們通常能夠理解,例如多個探頭電路17D08組、多個探頭輸出訊號17D14、以及訊號不從主電路上輸出之控制緩衝器17D16,均為可能之配置。 Figure 17D is an alternative circuit function that can also be used for "basics". In many IC setups, it is necessary to integrate probing assistance systems to enable easy probing of components during the debug phase and to support production testing. Probe circuits are also used in the prior art, using the same transistors as the main circuit. Figure 17D shows the probe circuit built under the primary layer active circuit on the substrate. Figure 17D shows the connections to the continuous active circuit component 17D02. The connection is connected to the substrate through the interconnection circuit 17D06, and the high-impedance probe circuit 17D08 is used to detect the output of subsequent components. Selection circuit 17D12 allows one or more outputs to be routed through one or more buffers 17D16 that can be controlled by signals on the primary circuit to drive sequential output signals to probe signal output 17D14 for debugging or testing. People can generally understand that, for example, multiple probe circuits 17D08 groups, multiple probe output signals 17D14, and a control buffer 17D16 whose signals are not output from the main circuit are all possible configurations.

在另外一個方案中,基板1402可以搭載SRAM晶片,如圖18所示。SRAM晶片1802在底層基板1402上預製,可以連接1812至1404上之主邏輯電路1806、1808。如上文所述,在1404上建設之各層可以與底層基板1402上之預製結構對準,使得邏輯晶片能夠與相應的底層RAM晶片相連。 In another solution, the substrate 1402 may carry an SRAM chip, as shown in FIG. 18 . The SRAM chip 1802 is pre-fabricated on the bottom substrate 1402 and can be connected to the main logic circuits 1806, 1808 on 1812-1404. As described above, the layers built on 1404 can be aligned with the pre-fabricated structures on the underlying substrate 1402 to enable logic chips to be connected to corresponding underlying RAM chips.

圖19A為底層I/O之示意圖。基板1402可以透過預處理搭載I/O電路,或部分I/O,例如輸出驅動1912相對較大之電晶體。另外基板上之TSV也可用來將I/O連接1914一路導回到基板背面。圖19B為依照本項發明案例之集成組件之邊“切”。輸出驅動如PMOS和NMOS輸出電晶體19B06所示,兩個電晶體透過TSV 19B10向列,並與背面焊點或球型焊點19B08相連。基板1402中連接之材料可以進行選擇,承受整個1404上組件後續工藝製造過程中之高溫,如圖8A-802、804、806、807、810、812所示,可以是鎢。基板也可以搭載輸入保護電路1916,將焊點19B08連接至主電路之輸入邏輯器1920上。 Figure 19A is a schematic diagram of bottom I/O. The substrate 1402 can be pre-processed to carry I/O circuits, or part of the I/Os, such as output drive 1912 relatively large transistors. Alternatively TSVs on the substrate can also be used to route I/O connections 1914 all the way back to the back of the substrate. Figure 19B is a side "cut" of an integrated component according to an example of the present invention. The output drive is shown as PMOS and NMOS output transistor 19B06, and the two transistors are aligned through TSV 19B10, and connected to the back solder joint or ball solder joint 19B08. The material connected in the substrate 1402 can be selected to withstand the high temperature in the subsequent manufacturing process of the components on the entire 1404, as shown in Fig. 8A-802, 804, 806, 807, 810, 812, it can be tungsten. The substrate can also be equipped with an input protection circuit 1916 to connect the pad 19B08 to the input logic 1920 of the main circuit.

本項發明之另外一個案例是在基板上使用TSV,如TSV19B10,將晶片連接起來,構成3D集成系統。通常,每個TSV都需要較大之面積,一般幾個平方微米。當需要使用很多TSV時,就會排除所占面積使用高密度電晶體,使得所有TSV之面積開支很大。在施主晶圓上,使用先前之流程進行預處理加工這些TSV,可以顯著降低3D TSV連接之有效成本。到初晶矽電路1920之連接1924,可以使用最小之接觸面積實現,大約零點幾個平方納米,比TSV所需之幾個平方微米之面積小兩個數量級。僅具有基礎知識之人員將會很容易理解圖19B中之舉例說明(並未放大)。人們通常很容易理解,使用圖19B所述之發明原則,可以建設出很多其他實力和部件佈置,圖19B僅供參考。 Another example of this invention is to use TSV on the substrate, such as TSV19B10, to connect chips to form a 3D integrated system. Typically, each TSV requires a relatively large area, typically several square microns. When many TSVs need to be used, the area occupied by high-density transistors will be excluded, making the area of all TSVs very expensive. On the donor wafer, pre-processing these TSVs using the previous flow can significantly reduce the effective cost of 3D TSV connection. Connections 1924 to pristine silicon circuits 1920 can be made using the smallest contact area, on the order of a fraction of a square nanometer, which is two orders of magnitude smaller than the several square micrometers required for TSVs. The illustration in Figure 19B (not enlarged) will be readily understood by persons with only basic knowledge. It is generally well understood that many other strengths and component arrangements can be constructed using the inventive principles described in Figure 19B, which is provided for reference only.

圖19C為一個3D系統,包含3個相連之晶片(19C10、19C20、19C30)和TSV(19C12、19C22、19C32),以TSV19B10和圖19A類似之方式進行說明。3個晶片之堆使用基板上之TSV(19C12、19C22、19C32)建設3D互聯電路,使得初晶矽19C14、19C24、19C34與各自之基板透過最小尺寸之過孔相連,影響和矽片面積損失最小。三個晶片堆可以使用球焊19C40與PC主板相連,19C40與晶片TSV19C32之背面相連。僅具有基礎知識之人員將會很容易理解圖19C中之舉例說明(並未放大)。人們通常很容易理解,使用圖19C所述之發明原則,可以建設出很多其他實力和部件佈置,圖19C僅供參考。例如,一個晶片堆可以使用倒裝晶片黏結佈置在封裝內,也可以使用球焊19C40代替黏結焊點,將該部分倒裝並和焊線一起黏結在傳統封裝內。 Fig. 19C is a 3D system including 3 connected chips (19C10, 19C20, 19C30) and TSVs (19C12, 19C22, 19C32), illustrated in a similar manner to TSV19B10 and Fig. 19A. The stack of 3 chips uses TSV (19C12, 19C22, 19C32) on the substrate to build a 3D interconnection circuit, so that the primary silicon 19C14, 19C24, 19C34 are connected to their respective substrates through via holes of the smallest size, and the impact and loss of silicon chip area are minimal . The stack of three chips can be connected to the PC motherboard using ball bond 19C40, which is connected to the back side of chip TSV19C32. The illustration in Figure 19C (not enlarged) will be readily understood by persons with only basic knowledge. It is generally well understood that many other strengths and component arrangements can be constructed using the inventive principles described in Figure 19C, which is provided for reference only. For example, a die stack can be placed in a package using flip-chip bonding, or ball bonds 19C40 can be used instead of bond pads, and the part can be flipped and bonded in a conventional package with wire bonds.

圖19D為3D IC處理器和DRAM系統之示意圖;電腦行業所面臨之廣為人知之問題是“記憶體牆“和處理器訪問DRAM之速度有關。現有技術給出之解決方案是使用直接佈置在處理器以上之TSV連接DRAM堆,並將散熱器撞到處理器背面,來給處理器散熱。但是,這樣做就需要有一個特殊之過孔,穿過DRAM,使得處理器I/O和電流能夠透過。過多處理器“穿DRAM過孔”則會導致一些嚴重之缺陷。首先,會降低DRAM之可用矽面積,高達幾個百分點。然後,會增加上方透過之電流,增幅亦為幾個百分點。另外,會要求DRAM之設定與處理器之設定進行協 調,這在商業上是個挑戰。圖19D之案例給出了一個解決方案,可以減小上述問題:使用如19B和19C所示之具有TSV之基板。使用基板和初晶矽結構可以使得與處理器之連接無需穿過DRAM。 Figure 19D is a schematic diagram of a 3D IC processor and DRAM system; a well-known problem facing the computer industry is the "memory wall" related to the speed with which the processor can access the DRAM. The solution given by the prior art is to use TSVs directly arranged above the processor to connect to the DRAM stack, and bump the heat sink to the back of the processor to dissipate heat for the processor. However, doing so requires a special via through the DRAM to allow processor I/O and current to pass through. Too many processor "vias through DRAM" can lead to some serious drawbacks. First, it will reduce the available silicon area of DRAM by as much as several percent. Then, the current passing through the top will be increased by several percentage points. In addition, it will require DRAM settings to coordinate with processor settings. Tune, this is a commercial challenge. The example of Figure 19D presents a solution that can reduce the above-mentioned problems: use a substrate with TSVs as shown in Figures 19B and 19C. Using a substrate and pristine silicon structure allows the connection to the processor without going through the DRAM.

圖19D中,處理器I/O和電壓可以透過朝下之微處理器有源區域19D14連接-初晶矽層,透過過孔19D08穿過散熱器基板19D04與底板材料19D06相連。散熱器19D12,散熱器底板19D04、散熱槽19D02都用來帶走處理器有源區域19D14產生之熱量。穿過底板19D16之TSV(19D22)用來連接DRAM堆19D24。DRAM對包含多個透過TSV 19D20相互連接之薄型DRAM 19D18。因此,DRAM堆不需要穿過處理器I/O和電壓平面,並且可以無需考量處理器設定和佈置進行獨立設定製造。DRAM晶片19D18與基板19D16最近,可以設定用來連接基板TSV 19D22,或者也可以在之間加入一個單獨的重新分佈層(或RDL,未畫出),或者基板19D16可以用作預處理高溫佈線層,如前述之鎢。另外一個處理器有源區域並未包含TSV,與基板19D16不同。 In Fig. 19D, the processor I/O and voltage can be connected through the down-facing microprocessor active area 19D14 - the primary silicon layer, through the heat sink substrate 19D04 and the base material 19D06 through vias 19D08. The heat sink 19D12, the bottom plate of the heat sink 19D04, and the cooling groove 19D02 are all used to take away the heat generated by the active area 19D14 of the processor. The TSVs (19D22) passing through the backplane 19D16 are used to connect to the DRAM stack 19D24. A DRAM pair includes a plurality of thin DRAMs 19D18 interconnected by TSVs 19D20. Therefore, the DRAM stack does not need to pass through processor I/O and voltage planes, and can be fabricated independently of processor settings and placement. The DRAM chip 19D18 is closest to the substrate 19D16 and can be set to connect to the substrate TSV 19D22, or a separate redistribution layer (or RDL, not shown) can be added between, or the substrate 19D16 can be used as a pre-processing high-temperature wiring layer , such as the aforementioned tungsten. Another processor active area does not contain TSVs, unlike substrate 19D16.

另外,基板過孔19D22可以用來穿過處理器I/O和功率,連接基板19D04和基板材料19D06,同時DRAM堆可以直接與處理器有源區域19D14相連。人們可以很容易之理解在本項發明之範圍內,可以用更多不同之組合。 In addition, substrate vias 19D22 can be used to pass through the processor I/O and power, connecting the substrate 19D04 and substrate material 19D06, while the DRAM stack can be directly connected to the processor active area 19D14. It can be easily understood that many different combinations can be used within the scope of the present invention.

圖19E為本項發明之另一個案例,DRAM堆19D24可以透過焊線19E24與一個RDL(重新分佈層)19E26相連, RDL將DRAM與基板過孔19D22連接起來,然後將它們與朝下之處理器19D14相連。 Fig. 19E is another case of the present invention, the DRAM pile 19D24 can be connected with a RDL (redistribution layer) 19E26 through the bonding wire 19E24, The RDL connects the DRAM to the substrate vias 19D22 and then connects them to the processor facing down 19D14.

在另外一個案例中,定制之SOI晶圓可以在晶圓廠加工NuVias 19F00中。NuVias 19F00可以使用傳統之TSV,直徑大約在1微米以上,也由SOI晶圓供應商加工。如圖19F所示,處理晶圓19F02和買入氧化物BOX 19F01。處理晶圓19F02通常有好幾百個微米厚,BOX 19F01同差有好幾百個納米厚。集成組件製造商(IDM)或鑄造廠隨後加工NuContacts 19F03,與NuVias 19F00相連。NuContact可以是常規尺寸之觸點,同時在薄SOI矽片之19F05和BOX 19F01上蝕刻然後填充金屬得到。NuContact之尺寸DnuContact 19F04,如圖19F所示,可以加工至納米級。現有技術如圖19G所示,在大塊之矽晶圓19G00上進行建設,通常具有一個TSV直徑、DTSV_prior_art 19G02,尺寸在微米級。NuContact DnuContact 19F04,如圖19F所示,縮減後之尺寸可能對於半導體設定者而言具有重要意義。對於穿矽連接而言,使用NuContact可以提供縮小的晶片尺寸開支,更小的超薄矽晶圓加工,和更小的設定複雜程度。在傳統SOI晶圓上,TSV之佈置是基於高產能集成組件製造商(IDM)或鑄造廠之要求,或者依照公認之行業標準進行。 In another case, custom SOI wafers can be processed in the NuVias 19F00 in the fab. NuVias 19F00 can use traditional TSVs with a diameter of about 1 micron or more, which are also processed by SOI wafer suppliers. As shown in FIG. 19F, wafer 19F02 and buy-in oxide BOX 19F01 are processed. Process wafer 19F02 is typically hundreds of microns thick, and BOX 19F01 is typically hundreds of nanometers thick. The Integrated Component Manufacturer (IDM) or foundry then processes the NuContacts 19F03 to interface with the NuVias 19F00. NuContact can be a contact of a conventional size, which is obtained by etching on the thin SOI silicon wafer 19F05 and BOX 19F01 and then filling it with metal. The size of NuContact DnuContact 19F04, as shown in Figure 19F, can be processed to the nanoscale. Prior Art As shown in Figure 19G, construction is done on bulk silicon wafers 19G00, typically with one TSV diameter, DTSV_prior_art 19G02, in the micron range. NuContact DnuContact 19F04, shown in Figure 19F, the reduced size may be of great significance to semiconductor planners. For through-silicon connections, the use of NuContact can provide reduced die size spending, smaller ultra-thin silicon wafer processing, and less setup complexity. On traditional SOI wafers, TSV placement is based on the requirements of high-volume integrated device manufacturers (IDMs) or foundries, or in accordance with recognized industry standards.

如圖19H所示之流程圖可以用來製造傳統SOI晶圓。晶圓供應商就可能使用類似流程。採用矽施主晶圓19H04,表面19H05可以被氧化。然後將一種原子,例如 氦,植入到(摻雜)一定之深度19H06。在其他案例中所述之氧化物-氧化物黏結,可以用來將該晶圓與接受晶圓19H08黏結到一起,19H08具有預處理之NuVias 19H07過孔。NuVias 19H07可以使用導電材料建設,例如鎢或者摻雜矽,使之可以承受後續加工中之高溫。也可以使用絕緣屏障,例如矽氧化物,來將NuVia 19H07與接受晶圓19H08上之矽隔開。另外,晶圓供應商可以使用矽氧化物建設NuVias 19H07。集成組件製造商或鑄造廠可以在高溫(大於400度)電晶體製造完成後對氧化物進行蝕刻,並可以使用金屬,銅或鋁,來替代該氧化物。該流程允許較低之熔點,但是會用到高導電性金屬,例如銅或鋁。在黏結之後,施主晶圓19H04之一部分19H10可以在19H06處進行切割,然後可以用其他案例中所述之化學/機械打磨進行處理。 The flowchart shown in FIG. 19H can be used to fabricate conventional SOI wafers. Wafer suppliers may use a similar process. With silicon donor wafer 19H04, the surface 19H05 can be oxidized. Then an atom such as Helium, implanted (doped) to a certain depth 19H06. Oxide-oxide bonding, as described in other cases, can be used to bond this wafer to a receiver wafer 19H08 with preprocessed NuVias 19H07 vias. NuVias 19H07 can be constructed using conductive materials, such as tungsten or doped silicon, so that it can withstand high temperatures in subsequent processing. An insulating barrier, such as silicon oxide, can also be used to separate the NuVia 19H07 from the silicon on the receiver wafer 19H08. Alternatively, wafer suppliers can build NuVias 19H07 using silicon oxide. An integrated component manufacturer or foundry can etch the oxide after high temperature (greater than 400 degrees) transistor fabrication and can use metal, copper or aluminum, instead of the oxide. This process allows for lower melting points, but uses highly conductive metals such as copper or aluminum. After bonding, a portion 19H10 of the donor wafer 19H04 can be diced at 19H06 and can then be treated with chemical/mechanical polishing as described in other cases.

圖19J給出了製造傳統SOI晶圓之另外一項技術。可以使用一個標準的SOI晶圓,及基板19J01、BOX 19F01,和表層矽19J02,NuVias 19F00可以按照從背面到氧化層之順序進行加工。該項技術可能比標準之SOI工藝生產出更厚之埋入氧化物19F01。 Figure 19J shows another technique for fabricating conventional SOI wafers. A standard SOI wafer can be used, and the substrate 19J01, BOX 19F01, and surface silicon 19J02, NuVias 19F00 can be processed in order from the backside to the oxide layer. This technology may produce thicker buried oxide 19F01 than standard SOI process.

圖19I說明了如何使用定制SOI晶圓進行處理器19I09和一個DRAM19I10之3D堆加工。在上述配置中,一個處理器之功率分配和I/O連接都從底板19I12,經過DRAM 19I10,然後與處理器19I09相連。圖19F中之上述技術可以使得DRAM有源矽片之接觸面積較小,對預處理器- DRAM堆之應用而言十分方便。在DRAM晶片上,由於加工穿晶片連接19I13和19I14損失之電晶體面積,由於有源DRAM矽片上NuContact 19I13之直徑(10幾個納米),會變得非常小。當大型穿矽連接位於DRAM之中間時,佔用之較大面積將提高設定難度。較小尺寸之穿矽連接可以應付這個問題。人們可以很容易想到,使用這項技術可以建設處理器-SRAM堆,處理器-快閃記憶體堆、處理器-圖形儲存堆,和上述晶片之組合,或其他任何類型之與積體電路有關之組合,例如SRAM可編程邏輯組件,和相關之設定ROM/PROM/EPROM/EEPROM組件,ASIC和功率穩壓器,微型控制器和類比功能電路等。另外,絕緣矽(SOI)可以是在絕緣體上之多晶矽、GaAs、GaN等。人們會很容易想到,NuVia和NuContact技術適用非常廣,本項發明之範圍並非僅限於附件中之權利聲明。 Figure 19I illustrates how a 3D stack of a processor 19I09 and a DRAM 19I10 is processed using a custom SOI wafer. In the above configuration, the power distribution and I/O connections of a processor are all from the backplane 19I12, through the DRAM 19I10, and then connected to the processor 19I09. The above-mentioned technique in Fig. 19F can make the contact area of the DRAM active silicon chip smaller, and the preprocessor- It is very convenient for the application of DRAM stack. On the DRAM chip, the transistor area lost due to processing through-chip connections 19I13 and 19I14 will become very small due to the diameter of NuContact 19I13 on the active DRAM chip (a few nanometers). When the large through-silicon connection is located in the middle of the DRAM, the larger area occupied will increase the difficulty of setting. Smaller size through-silicon connections can cope with this problem. One can easily imagine using this technology to build processor-SRAM stacks, processor-flash memory stacks, processor-graphics storage stacks, combinations of the above, or any other type of integrated circuit Combinations, such as SRAM programmable logic components, and related setting ROM/PROM/EPROM/EEPROM components, ASIC and power regulators, microcontrollers and analog function circuits, etc. In addition, silicon-on-insulator (SOI) can be polysilicon-on-insulator, GaAs, GaN, etc. It is easy to imagine that the NuVia and NuContact technologies are widely applicable, and the scope of this invention is not limited to the rights statement in the appendix.

本項發明之另外一個案例就是基板1402可以額外搭載重新驅動晶片(通常稱為緩衝器)。重新驅動晶片在行業中通常用於路徑相對較長之訊號傳輸。由於路徑具有較大之阻值和容量損耗,沿傳輸路徑插入一個重新驅動電路有助於避免訊號時序和形狀之嚴重衰減。在基板1402上搭載重新驅動之優勢在於重新驅動能夠使用電晶體建設,因而能夠承受較大之編程電壓。另外,隔離電晶體,如1601和1602,或者其他隔離方案也可用於邏輯晶片之輸入和輸出。 Another example of the present invention is that the substrate 1402 can additionally carry a re-drive chip (commonly called a buffer). Redriver chips are commonly used in the industry for signal transmission with relatively long paths. Inserting a re-driver circuit along the transmission path helps avoid severe degradation of signal timing and shape due to the high resistance and capacity loss of the path. An advantage of having the redriver on the substrate 1402 is that the redriver can be built using transistors and thus can withstand larger programming voltages. In addition, isolation transistors, such as 1601 and 1602, or other isolation schemes can also be used for the input and output of the logic chip.

圖8A為可編程組件多層結構之結構示意圖,有兩個抗 熔存儲層。用作第一層804之可編程電晶體,可以在814上預製,然後,使用智慧切割,加工出單晶矽層1404,之後再添加主編程邏輯器802與先進邏輯電晶體和其他電路。隨後,在多金屬層加工時還包含了一個下層抗熔存儲804,佈線層806、第二抗熔存儲層和可設定互聯電路807。對於第二抗熔存儲,編程電晶體810也可以使用第二次只能切割層加工。 Figure 8A is a schematic diagram of the multi-layer structure of programmable components, there are two anti- molten storage layer. The programmable transistors used for the first layer 804 can be prefabricated on 814, and then, using smart dicing, the monocrystalline silicon layer 1404 is processed, after which the main programming logic 802 and advanced logic transistors and other circuits are added. Subsequently, a lower layer antifuse memory 804 , a wiring layer 806 , a second antifuse memory layer and a configurable interconnection circuit 807 are also included during multi-metal layer processing. For the second antifuse, the programming transistor 810 can also be processed using the second cut-only layer.

圖20為第二層之層切流程示意圖。初加工晶圓2002包含所有先前之層814、802、804、806和807。隨後,一個氧化層2012將被佈置在晶圓2002上,進行打磨,達到更好之正平和表面等級。然後將供電晶圓2006(或是可切除晶圓,如圖標注所示)黏結到2002上。施主晶圓2006之預加工包含半導體層2019,隨後可以用來建設編程電晶體810之表層,作為TFT電晶體之替代方案。供電晶圓2006也可以經過粒子植入之智慧切割作為預處理,原子類型可能包含H+離子,所需之深度依照智慧切割2008之刻線而定。在黏結兩個晶圓之後,進行智慧切割,沿切割層2014來移除供電晶圓2006之頂層2008。這樣,施主晶圓現在也可以用來處理和重新加工更多層。得到的是一個3D晶圓2010,包含晶圓2002和單晶矽(或是多層材料的)附加層2004。切出之層2004可以非常薄,大約在10-200nm之間。使用智慧切割能夠在預處理晶圓上製成單晶半導體層,而無需退火預處理晶圓至4000攝氏度以上。 Fig. 20 is a schematic diagram of the layer cutting process of the second layer. Raw wafer 2002 contains all previous layers 814 , 802 , 804 , 806 and 807 . Subsequently, an oxide layer 2012 will be placed on the wafer 2002 and polished to achieve a better planarity and surface grade. A power supply wafer 2006 (or a cutable wafer, as marked) is then bonded to 2002 . Prefabrication of the donor wafer 2006 to include the semiconductor layer 2019 can then be used to build the top layer of the programming transistor 810 as an alternative to TFT transistors. The power supply wafer 2006 can also be pretreated by smart dicing of particle implantation. The atomic type may include H+ ions, and the required depth depends on the scribe line of smart dicing 2008. After bonding the two wafers, smart dicing is performed to remove the top layer 2008 of the power supply wafer 2006 along the dicing layer 2014 . In this way, the donor wafer can now also be used to process and reprocess further layers. The result is a 3D wafer 2010 comprising a wafer 2002 and an additional layer 2004 of monocrystalline silicon (or multilayer material). The cut out layer 2004 can be very thin, approximately between 10-200nm. The use of smart dicing enables the fabrication of monocrystalline semiconductor layers on preprocessed wafers without annealing the preprocessed wafers to temperatures above 4000°C.

使用智慧切割層切並不超過下層預處理結構之溫度上 限,可以有多種替代方法來建設表層電晶體,並與下面之預處理層準確對準,如預處理晶圓或層808。由於切出之層厚小於200nm,以上定義之電晶體,按照需要,可以準確地與預處理晶圓或808層之表面金屬層對準,這些電晶體之對準誤差小於40nm。 The use of intelligent cutting layer cutting does not exceed the temperature of the lower pretreatment structure However, there are many alternative ways to build the surface transistors and align them accurately with the underlying pre-processed layer, such as the pre-processed wafer or layer 808. Since the thickness of the cut out layer is less than 200nm, the above-defined transistor can be accurately aligned with the surface metal layer of the preprocessed wafer or layer 808 as required, and the alignment error of these transistors is less than 40nm.

一個替代方法是使用一個較薄之單晶矽切出層,用於外緣Ge晶之生長,使用該切出層作為鍺之晶種。另外一個方法是使用較薄之單晶矽切出層用作外緣GexSil-x之生長。這些層中Ge/Si百分比由電路電晶體規範指定。現有技術提供的方法是,使用矽基板在氧化物表面透過氧化物孔來結晶鍺,從底層矽晶中生長晶體或格狀晶種。然而,在多個佈線層表面,這樣做就十分困難。透過層切,我們可以在表面獲得單晶層矽晶,並使得播種和結晶相對簡化,獲得一個疊加之鍺層。在300攝氏度下,使用CVD可以讓無定型鍺規則地分佈,並且與底層之圖案對準,底層可以是預處理晶圓或層808,然後使用低溫氧化物封裝。一個較短之秒級熱脈衝將鍺層融化,同時將下方結構之溫度保持在400攝氏度以下。Ge/Si連接處將開始結晶或格狀累晶生長,結晶成鍺,或者形成Ge X Sil-x層。然後,摻雜形成Ge電晶體,透過鐳射脈衝開啟,不會損壞下層結構,同時利用鍺中雜質之低活化溫度。 An alternative approach is to use a thinner cutout of monocrystalline silicon for the growth of the outer Ge crystals, using the cutout as a germanium seed. Another method is to use a thinner monocrystalline silicon cut-out layer for the growth of the outer edge GexSil-x. The Ge/Si percentages in these layers are specified by circuit transistor specifications. The method provided by the prior art is to use a silicon substrate to crystallize germanium through oxide holes on the oxide surface, and grow crystals or lattice seeds from the underlying silicon crystal. However, this is very difficult to do on the surface of multiple wiring layers. Through layer cutting, we can obtain a single crystal layer of silicon on the surface, and make the seeding and crystallization relatively simple, and obtain a superimposed germanium layer. Using CVD at 300 degrees Celsius, the amorphous germanium can be regularly distributed and aligned with the pattern of the underlying layer, which can be a pre-processed wafer or layer 808, and then packaged using low temperature oxide. A short heat pulse on the order of seconds melts the germanium layer while keeping the temperature of the underlying structure below 400 degrees Celsius. The Ge/Si junction will start to crystallize or lattice accumulative growth, crystallizing into germanium, or forming a Ge x Sil-x layer. Then, Ge transistors are formed by doping, which can be turned on by laser pulses without damaging the underlying structure, while taking advantage of the low activation temperature of impurities in germanium.

另外一個方法是使用預處理晶圓進行層切,如圖21所示。圖21A為使用預處理晶進行層切之示意圖;輕度摻雜之P型晶圓(P-晶圓)2101可以加工出一個高度摻雜之N型 矽(N+)“埋入”層,透過摻雜和開啟實現,也可透過P-累晶生長2106之後之淺層N+摻雜和擴散實現。另外,如果電晶體之性能需要使用一個基板觸點,則可另外摻雜並開啟一個淺P+層2108。圖21B為一個預處理晶圓,經過摻雜原子後可以用於層切,摻雜原子可以是H+,在下部之N+區域可製備用於智慧切割之“切出平面”2110,並且經過氧化物澱積或生長2112後,可生成用於氧化物黏結之氧化層。現在可以執行層切流程,來加工預處理單晶P-矽和N+層,該層位於預處理晶圓或層808之上。預處理晶圓或808層可以進行黏結,使用氧化物沉積和/或表面處理實現。人們通常可以預見,使用上述方法僅為參考,基於本項發明之原則可以推出其他案例和應用範圍,發明之範圍不受附錄之權利聲明限制。 Another method is to use pre-processed wafers for layer dicing, as shown in Figure 21. Figure 21A is a schematic diagram of layer dicing using a preprocessed wafer; a lightly doped P-type wafer (P-wafer) 2101 can be processed into a highly doped N-type The silicon (N+) "buried" layer is achieved by doping and opening, and can also be achieved by shallow N+ doping and diffusion after P-cumulative growth 2106. Alternatively, a shallow P+ layer 2108 can be additionally doped and turned on if the performance of the transistor requires the use of a substrate contact. Figure 21B is a pre-processed wafer, which can be used for layer cutting after doping atoms. The doping atoms can be H+, and the "cut-out plane" 2110 for smart cutting can be prepared in the lower N+ region, and the oxide After deposition or growth 2112, an oxide layer for oxide bonding may be generated. The layer dicing process can now be performed to process the pre-processed single crystal P-silicon and N+ layers on top of the pre-processed wafer or layer 808 . Pre-processed wafers or 808 layers can be bonded using oxide deposition and/or surface treatment. It is generally foreseeable that the above methods are used for reference only, and other cases and application scopes can be deduced based on the principles of this invention, and the scope of the invention is not limited by the rights statement in the appendix.

圖22A-22H為上部平面源極擴展電晶體之成型示意圖。圖22A為預處理晶圓或808層上部之切出層,在智能切割之後,N+2104位於表面。表面電晶體源極22B04和汲極22B06透過將柵極22B02指定區域之N+蝕刻掉形成,留下一薄層更為清的摻雜N+層,作為後續源極和汲極之擴展,及電晶體22B08之隔離層。利用額外之掩膜層,隔離區域22B)8,透過向預處理晶圓或808層表面蝕刻獲得,在電晶體或電晶體組之間形成隔離。將電晶體之間之N+層蝕刻掉有助於N+層之導通。該步驟與預處理晶圓或808層之表面對準,使得所形成之電晶體可以與預處理晶圓或808層之金屬層形成良好連接。然後,一個高度等效之低 溫氧化物22C02(或氧化物/氮堆)透過積澱和蝕刻獲得,形成圖22C所示之結構。圖22D為自對齊蝕刻準備步驟後之結構,此次蝕刻用於加工柵極22D02,然後形成源極和汲極擴展22D04。圖22E為低溫微波氧化技術後得到之結構,該技術可以是TEL SPA(豐田電子有限公司之槽平面天線)氧氣自由基電漿,從而生長出或積澱出一個低溫柵極絕緣體22E02,用作MOSFET柵極氧化物,或者也可以使用原子層積澱(ALD)技術。另外,柵極結構也可以使用如下高K-金屬柵極流程得到。在一個工業標準HF/SC1/SC2清理之後,形成一個原子級光滑之表面,然後沉積出一個高k絕緣層22E02。半導體行業選擇了Hafnium基絕緣層作為取代SiO2和矽氮氧化物之首選材料。Hafnium基族絕緣體包含hafnium氧化物和hafnium矽酸鹽/hafnium矽氮氧化物。Hafnium氧化物,HfO2,具有大約是hafnium矽酸鹽/hafnium矽氮氧化物2倍左右之絕緣常數。(HfSiO/HfSiON k~15)金屬之選擇是組件正常工作之關鍵。代替N+多聚物之金屬用作柵極之電極,需要大約4.2eV之工作闕值,來保證組件在正常闕值電壓下正常工作。另外,代替P+多聚物之金屬用作柵極之電極,需要大約5.2eV逸出功,來保證正常工作。TiAl和TiAlN基之金屬族,可以用來將金屬之逸出功從4.2eV提高到5.2eV。 22A-22H are schematic diagrams of forming the upper planar source extension transistor. FIG. 22A is a preprocessed wafer or cut out layer on top of layer 808, after smart dicing, N+2 104 is on the surface. The surface transistor source 22B04 and the drain 22B06 are formed by etching away the N+ in the designated area of the gate 22B02, leaving a thinner and clearer doped N+ layer as the extension of the subsequent source and drain, and the transistor The isolation layer of 22B08. Using an additional masking layer, isolation regions 22B) 8 are obtained by etching into the surface of the preprocessed wafer or layer 808 to form isolation between transistors or groups of transistors. Etching away the N+ layer between the transistors helps to conduct the N+ layer. This step is aligned with the surface of the pre-processed wafer or layer 808, so that the formed transistors can form a good connection with the metal layer of the pre-processed wafer or layer 808. Then, a height equivalent to a low Warm oxide 22C02 (or oxide/nitrogen stack) is obtained by deposition and etching to form the structure shown in Figure 22C. Figure 22D shows the structure after the preparatory step of the self-aligned etch for gate 22D02 followed by source and drain extensions 22D04. Figure 22E is the structure obtained after low-temperature microwave oxidation technology, which can be TEL SPA (Toyota Electronics Co., Ltd. slot planar antenna) oxygen radical plasma, so as to grow or deposit a low-temperature gate insulator 22E02 for MOSFET gate oxide, or atomic layer deposition (ALD) techniques can be used. In addition, the gate structure can also be obtained using the following high-K-metal gate process. After an industry standard HF/SC1/SC2 clean to form an atomically smooth surface, a high-k insulating layer 22E02 is deposited. The semiconductor industry has chosen Hafnium-based insulating layers as the material of choice to replace SiO2 and silicon oxynitride. Hafnium-based group insulators include hafnium oxide and hafnium silicate/hafnium silicon oxynitride. Hafnium oxide, HfO2, has a dielectric constant about twice that of hafnium silicate/hafnium silicon oxynitride. (HfSiO/HfSiON k~15) The choice of metal is the key to the normal operation of the device. The metal that replaces the N+ polymer is used as the electrode of the gate, and a working threshold of about 4.2eV is required to ensure the normal operation of the device under the normal threshold voltage. In addition, the metal that replaces the P+ polymer is used as the electrode of the gate, and the work function of about 5.2eV is required to ensure normal operation. TiAl and TiAlN-based metal groups can be used to increase the work function of metals from 4.2eV to 5.2eV.

圖22F為積澱、研磨和蝕刻之後之金屬柵極22F02。另外,為了提高電晶體之性能,可以使用一個目標壓力層來誘導更高之溝道應力。可以在低溫下積澱出一個拉伸氮化 物層,來提高圖22中NMOS組件之溝道應力。PMOS電晶體可以透過上述流程來建設,只需改變初始之P-晶圓或2104N+層上之外緣成型P-,為N-晶圓或P+外緣層上之N-晶圓;並且將N+層2104改為一個P+層。然後,在金屬柵極成型之後,可以積澱一個壓應力氮化物薄膜,來提高PMOS電晶體之性能。 Figure 22F is the metal gate 22F02 after deposition, grinding and etching. Additionally, to improve transistor performance, a target stress layer can be used to induce higher channel stress. A tensile nitride can be deposited at low temperature layer, to increase the channel stress of the NMOS device in Figure 22. PMOS transistors can be constructed through the above process, only need to change the initial P-wafer or 2104N+ layer on the outer edge of the P-, N-wafer or N-wafer on the P+ outer layer; and the N+ Layer 2104 was changed to a P+ layer. Then, after forming the metal gate, a compressive nitride film can be deposited to improve the performance of the PMOS transistor.

最終積澱出一個厚之氧化物層22G02,並使用掩膜和蝕刻處理觸點之開口,準備與電晶體連接,如圖22G所示。本檔中之較厚氧化物或者低溫氧化物,可以透過化學氣相澱積(CVD)、屋裏氣相澱積(PVD)或電漿擴大化學氣相澱積(PECVD)技術來加工。該流程能夠形成單晶表層MOS電晶體,能夠與下層多金屬層半導體組件相連,無需將下層組件和互聯電路金屬裸露在高溫中。這些電晶體可以用作層807之抗熔存儲編程電晶體,與預處理晶圓或808層相連構成單片3D電路堆,或者用作3D積體電路之其他功能。這些電晶體可以當作“平面MOSFET電晶體”,即電晶體溝道中之電流始終是在水平方向。上述電晶體,包含本檔中其他電晶體,可以成為水平電晶體,水平方向,或橫向電晶體。這一流程之另外一個優勢在於,智慧切割H+,或者其他原子之摻雜步驟在MOS電晶體柵極成型之前完成,能夠避免損害柵極功能。如有需要,預處理晶圓或808層之表層可以包含一個“背面柵極”22F02-1,柵極22F02可以直接從上方與背面柵極22F02-1對準,如圖22H所示。背面柵極22F02-1可以從預處理晶圓 或808層之表面金屬層加工獲得,也可以在金屬層表面進行氧化物層澱積將晶圓貼合(晶圓未畫出)來作為背面柵極之柵極氧化物。 Finally a thick oxide layer 22G02 is deposited and the contact openings are masked and etched ready for connection to the transistors as shown in Figure 22G. The thicker oxides or low temperature oxides in this document can be processed by chemical vapor deposition (CVD), indoor vapor deposition (PVD) or plasma enhanced chemical vapor deposition (PECVD) techniques. This process can form a single-crystal surface MOS transistor, which can be connected to the underlying multi-metal layer semiconductor components without exposing the underlying components and interconnection circuit metals to high temperatures. These transistors can be used as antifuse programming transistors of layer 807, connected with pre-processed wafer or layer 808 to form a monolithic 3D circuit stack, or used for other functions of 3D integrated circuits. These transistors can be regarded as "planar MOSFET transistors", that is, the current in the transistor channel is always in the horizontal direction. The above-mentioned transistors, including other transistors in this file, can be horizontal transistors, horizontal direction, or lateral transistors. Another advantage of this process is that the intelligent cutting H+, or other atomic doping steps are completed before the gate of the MOS transistor is formed, which can avoid damaging the gate function. If desired, the surface layer of the preprocessed wafer or layer 808 may include a "back gate" 22F02-1, and the gate 22F02 may be directly aligned with the back gate 22F02-1 from above, as shown in FIG. 22H. Backside gate 22F02-1 can be obtained from preprocessed wafer Or the metal layer on the surface of the 808 layer is processed, and the oxide layer can also be deposited on the surface of the metal layer to bond the wafers (the wafer is not shown) as the gate oxide of the back gate.

依照本項發明之部分案例,在組件層之正常製造過程中,如圖8所示,每個新的層都必須使用之前加工出之對準標記與下一層對準。有時,一層之對準可以用來對準上方之多個層,有時一個新層也必須有對準標記,用來與後續製造步驟中與上方其他層對準。所以層804必須與層802對準,層806必須與層804對準,依次類推。上述流程之另一個優勢是,可以使得切出層足夠薄,在後續畫圖步驟中(畫圖步驟如圖22B所述),切出層可以與預處理晶圓或808層之對準標記對準,也可以與以下任何一層,如806、804、802,或其他層對準,來製造3D IC。因此,“背面柵極”22F02-1,為預處理晶圓或808層之表面金屬層之一部分,可以準確地從下方對齊22F02,因為所有層之標記都是逐層對準的。在本文中,對準精度很大程度上依賴於做標記之設備。對於45nm及以下制程,覆蓋對準之精度通常要比5nm更小。對準要求會隨著按比例縮小之使用越來越高,現代之步進電機可以做到比2nm更精確。對準要求之更小數量級可以在基於3D IC系統之TSV中實現,如圖12及下文所述,要達到0.5微米之覆蓋對準精度是非常困難的。表層柵極和背面柵極之連接可以透過表層過孔或TLV實現。這樣就可以進一步減小柵極22F02和背面柵極22F02-1之漏電流,兩個柵極都可以連接起來,更好地切 斷電晶體22G20。同時,透過動態改變表層柵極電晶體之闕值電壓-透過獨立改變背面柵極22F02-1之偏壓實現-也可以設定出一個睡眠模式、一個正常睡眠模式、一個快速睡眠模式。另外,透過上述流程來建設一個積累模式(全空乏)MOSFET電晶體,只需改變初始P-晶圓2102,或將2104N+層上之外緣成型P-2106,變為N-晶圓或N+外緣層上之N-晶圓。 During the normal manufacturing process of the component layers according to some examples of the present invention, each new layer must be aligned with the next layer using previously machined alignment marks as shown in FIG. 8 . Sometimes, the alignment of one layer can be used to align multiple layers above, and sometimes a new layer must also have alignment marks, which are used to align with other layers above in subsequent manufacturing steps. So layer 804 must be aligned with layer 802, layer 806 must be aligned with layer 804, and so on. Another advantage of the above process is that the cut-out layer can be made thin enough. In the subsequent drawing step (the drawing step is described in FIG. 22B ), the cut-out layer can be aligned with the alignment mark of the pre-processed wafer or layer 808, It can also be aligned with any of the following layers, such as 806, 804, 802, or other layers to make a 3D IC. Therefore, the "back gate" 22F02-1, which is part of the surface metal layer of the pre-processed wafer or layer 808, can be accurately aligned with 22F02 from below because the marks of all layers are aligned layer by layer. In this paper, the alignment accuracy is largely dependent on the marking equipment. For 45nm and below processes, the accuracy of overlay alignment is usually smaller than that of 5nm. Alignment requirements will become higher and higher with the use of scaling, and modern stepper motors can be more accurate than 2nm. Order of magnitude smaller alignment requirements can be achieved in TSV based 3D IC systems, as shown in Figure 12 and below, it is very difficult to achieve 0.5 micron overlay alignment accuracy. The connection between the surface gate and the back gate can be realized through surface vias or TLVs. In this way, the leakage current of the gate 22F02 and the back gate 22F02-1 can be further reduced, and the two gates can be connected to better cut Power down crystal 22G20. At the same time, by dynamically changing the threshold voltage of the surface gate transistor—by independently changing the bias voltage of the back gate 22F02-1—it is also possible to set a sleep mode, a normal sleep mode, and a fast sleep mode. In addition, to build an accumulation mode (full depletion) MOSFET transistor through the above process, it is only necessary to change the initial P-wafer 2102, or to form P-2106 on the outer edge of the 2104N+ layer into an N-wafer or N+ outer N-wafer on edge layer.

使用該項技術生產表層電晶體之另外一個因素是過孔或TLV之尺寸,過孔或TLV用來將表層電晶體22G20連接至預處理晶圓之金屬層和下方808層。通常可靠之經驗方法是過孔之尺寸大於所穿過層厚度之1/10。由於結構之層厚如圖12所示,通常大於50微米,則該結構上之TSV通常大於10微米。圖22A中切出層之厚度小於100nm,所以相應連接表層電晶體22G20至下方預處理晶圓和808層中金屬層之過孔尺寸應小於50nm。由於對制程進行縮小,切出層之厚度和相應連接下方結構之過孔之尺寸也可以縮小。對於某些先進制程,切出層之端厚度可以做到低於10nm。 Another factor in producing surface transistors using this technology is the size of the vias or TLVs used to connect the surface transistors 22G20 to the metal layer and the underlying 808 layer of the pre-processed wafer. A generally reliable rule of thumb is that the size of the via hole is greater than 1/10 of the thickness of the layer it passes through. Since the layer thickness of the structure, as shown in Figure 12, is typically greater than 50 microns, the TSVs on the structure are typically greater than 10 microns. The thickness of the cut-out layer in FIG. 22A is less than 100nm, so the size of the via hole connecting the surface layer transistor 22G20 to the lower preprocessed wafer and the metal layer in the 808 layer should be less than 50nm. Due to the shrinking of the manufacturing process, the thickness of the cut-out layer and the size of the corresponding via hole connecting the underlying structure can also be reduced. For some advanced processes, the end thickness of the cut layer can be less than 10nm.

另外一個源極和汲極擴展之平面表層電晶體成型方案是對圖21B中之加工晶圓進行處理,如圖29A-29G所示。圖29A為預處理晶圓或808層上部之切出層,在智能切割之後,N+2104、P-2106和P+2108位於表面。由於輔助黏結晶圓之氧化層未畫出。基板P+源29B04之觸點開口和電晶體隔離29B02經過掩膜和蝕刻,如圖29B所示。利用額外 之掩膜層,隔離區域29B02,透過向預處理晶圓或808層表面蝕刻獲得,在電晶體或電晶體組之間形成隔離,如圖29C所示。將電晶體之間之P+層蝕刻掉有助於P+層之導通。然後澱積低溫氧化物29C04並使用化學機械方法打磨。然後,一個薄打磨中止層29C06,可以是低溫氮化矽澱積而成,形成如圖29C所示結構。源極29D02、汲極29D04、和自對準柵極29D06,可以透過在薄打磨中止層29C06上掩膜和蝕刻,然後進行N+斜面蝕刻得到,如圖29D所示。斜面(30-90度,圖示45度)蝕刻或雙斜面蝕刻可以使用濕化學或電漿蝕刻技術實現。該流程可以形成有角度之源極和汲極擴展29D08。如圖29E所示,後續之低溫柵極絕緣體29E02之澱積和增密,或者低溫微波電漿矽表面氧化物,或原子層澱積(ALD)柵極絕緣體之澱積和增密,可以用作MOSFET柵極氧化物,然後進行柵極材料29E04之澱積,如鋁或鎢。 Another scheme for forming planar surface transistors with source and drain extensions is to process the processed wafer in FIG. 21B , as shown in FIGS. 29A-29G . FIG. 29A is the sliced layer on top of the preprocessed wafer or layer 808. After smart dicing, N+ 2104, P- 2106 and P+ 2108 are on the surface. The oxide layer of the auxiliary bonding wafer is not shown. The contact openings of the substrate P+ source 29B04 and the transistor isolation 29B02 are masked and etched as shown in Figure 29B. take advantage of extra The mask layer, the isolation region 29B02, is obtained by etching the surface of the pre-processed wafer or layer 808 to form isolation between transistors or transistor groups, as shown in FIG. 29C. Etching away the P+ layer between the transistors helps to conduct the P+ layer. A low temperature oxide 29C04 is then deposited and polished using chemical mechanical methods. Then, a thin grinding stop layer 29C06, which may be low temperature silicon nitride, is deposited to form the structure shown in FIG. 29C. The source 29D02, the drain 29D04, and the self-aligned gate 29D06 can be obtained by masking and etching on the thin grinding stop layer 29C06, followed by N+ bevel etching, as shown in FIG. 29D. Bevel (30-90 degrees, 45 degrees shown) or dual bevel etch can be achieved using wet chemical or plasma etch techniques. This process can form angled source and drain extensions 29D08. As shown in FIG. 29E, the deposition and densification of the subsequent low-temperature gate insulator 29E02, or the deposition and densification of the low-temperature microwave plasma silicon surface oxide, or the deposition and densification of the gate insulator by atomic layer deposition (ALD) can be performed using Make MOSFET gate oxide, then proceed with deposition of gate material 29E04, such as aluminum or tungsten.

另外,高K金屬柵極結構也可以使用如下流程得到。在一個工業標準HF/SC1/SC2清理之後,形成一個原子級光滑之表面,然後沉積出一個高k絕緣層29E02。半導體行業選擇了Hafnium基絕緣層作為取代SiO2和矽氮氧化物之首選材料。Hafnium基族絕緣體包含hafnium氧化物和hafnium矽酸鹽/hafnium矽氮氧化物。Hafnium氧化物,HfO2,具有大約是hafnium矽酸鹽/hafnium矽氮氧化物2倍左右之絕緣常數。(HfSiO/HfSiON k~15)金屬之選擇是組件正常工作之關鍵。代替N+多聚物之金屬用作柵極之 電極,需要大約4.2eV之工作闕值,來保證組件在正常之闕值電壓下正常工作。另外,代替P+多聚物之金屬用作柵極之電極,需要大約5.2eV之工作闕值,來保證正常工作。TiAl和TiAlN基之金屬族,可以用來將金屬之逸出功從4.2eV提高到5.2eV。 In addition, the high-K metal gate structure can also be obtained using the following process. After an industry standard HF/SC1/SC2 clean to form an atomically smooth surface, a high-k insulating layer 29E02 is deposited. The semiconductor industry has chosen Hafnium-based insulating layers as the material of choice to replace SiO2 and silicon oxynitride. Hafnium-based group insulators include hafnium oxide and hafnium silicate/hafnium silicon oxynitride. Hafnium oxide, HfO2, has a dielectric constant about twice that of hafnium silicate/hafnium silicon oxynitride. (HfSiO/HfSiON k~15) The choice of metal is the key to the normal operation of the device. Metals instead of N+ polymers are used as gates The electrode requires a working threshold of about 4.2eV to ensure that the component works normally at a normal threshold voltage. In addition, the metal used as the gate electrode instead of the P+ polymer requires a working threshold of about 5.2eV to ensure normal operation. TiAl and TiAlN-based metal groups can be used to increase the work function of metals from 4.2eV to 5.2eV.

如圖29F所示,在使用化學機械打磨金屬柵極29E04之後,利用氮化物打磨中止層29C06得到之結構。PMOS電晶體可以透過上述流程來建設,只需改變初始之P-晶圓或2104N+層上之外緣成型P-,為N-晶圓或P+外緣層上之N-晶圓;並且將N+層2104改為一個P+層。類似的,如果將P+改為N+,在基板觸點被使用之情況下,層2108也會改變。 As shown in FIG. 29F , after the metal gate 29E04 is chemically mechanically polished, the stop layer 29C06 is polished with nitride to obtain the structure. PMOS transistors can be constructed through the above process, only need to change the initial P-wafer or 2104N+ layer on the outer edge of the P-, N-wafer or N-wafer on the P+ outer layer; and the N+ Layer 2104 was changed to a P+ layer. Similarly, if P+ is changed to N+, layer 2108 will also change in the event that substrate contacts are used.

最終積澱出一個厚之氧化物層29G02,並使用掩膜和蝕刻處理觸點之開口,準備與電晶體連接,如圖29G所示。該圖還給出了,層切矽過孔29G04,掩膜和蝕刻加工後,為表面電晶體線路至底層808互聯電路29G06提供連接。該流程能夠形成單晶表層MOS電晶體,能夠與下層多金屬層半導體組件相連,無需將下層組件和互聯電路金屬裸露在高溫中。這些電晶體可以用作層807之抗熔存儲編程電晶體,與預處理晶圓或808層相連構成單片3D IC,或者用作3D積體電路之其他功能。這些電晶體可以當作平面揗OSFET電晶體,即電晶體溝道中之電流是水平方向的。上述電晶體,包含本檔中之其他電晶體,可以成為水平電晶體,水平方向,或橫向電晶體。這一流程之另外一個優 勢在於,智慧切割H+,或者其他原子之摻雜步驟在MOS電晶體柵極成型之前完成,能夠避免損害柵極功能。另外,透過上述流程來建設一個積累模式(全空乏)MOSFET電晶體,只需改變初始之P-晶圓,或將2104N+層上之外緣成型P-,變為N-晶圓或N+外緣層上之N-晶圓。另外,也可使用類似於圖22H之背面柵極。 Finally a thick oxide layer 29G02 is deposited and the contact openings are masked and etched ready for connection to the transistors as shown in Figure 29G. The figure also shows that the layer-cut silicon via hole 29G04, after masking and etching process, provides connection for the surface transistor circuit to the bottom layer 808 interconnection circuit 29G06. This process can form a single-crystal surface MOS transistor, which can be connected to the underlying multi-metal layer semiconductor components without exposing the underlying components and interconnection circuit metals to high temperatures. These transistors can be used as antifuse programming transistors of layer 807, connected with pre-processed wafer or layer 808 to form a monolithic 3D IC, or used for other functions of 3D integrated circuits. These transistors can be regarded as planar OSFET transistors, that is, the current in the transistor channel is horizontal. The above transistors, including other transistors in this document, can be horizontal transistors, horizontal orientation, or lateral transistors. Another advantage of this process The advantage is that smart cutting H+, or other atomic doping steps are completed before the gate of the MOS transistor is formed, so as to avoid damage to the gate function. In addition, to build an accumulation mode (full depletion) MOSFET transistor through the above process, it only needs to change the initial P-wafer, or form P- on the outer edge of the 2104N+ layer to become an N-wafer or N+ outer edge N-wafer on layer. Alternatively, a back gate similar to that of FIG. 22H can be used.

另外一個方法是使用預處理晶圓進行層切,如圖23所示。圖23A為使用預處理晶進行層切之示意圖;N-晶圓2302可以加工出一個埋入層N+2304,透過摻雜和開啟實現,也可透過N-累晶生長之後之淺層N+摻雜和擴散實現。圖23B為一個預處理晶圓,經過澱積或氧化物2308之生長後可以用於層切,經過摻雜原子,例如H+後,可以在N+區域之下部準備好智慧切割之切出平面2306。現在可以執行層切流程,來加工預處理單晶N-矽和N+層,該層位於預處理晶圓或層808之上。 Another method is to use pre-processed wafers for layer dicing, as shown in Figure 23. Figure 23A is a schematic diagram of layer dicing using pre-processed crystals; N-wafer 2302 can process a buried layer N+ 2304, which can be realized through doping and opening, and can also be achieved through shallow N+ doping after N-cumulative crystal growth. Complexity and diffusion are realized. FIG. 23B is a pre-processed wafer, which can be used for layer cutting after deposition or growth of oxide 2308. After doping atoms, such as H+, a cutting plane 2306 for smart cutting can be prepared under the N+ region. The layer dicing process can now be performed to process the preprocessed single crystal N- silicon and N+ layers, which are located on the preprocessed wafer or layer 808 .

圖24A-24F為上部結柵場效應(JFET)平面電晶體成型示意圖。圖24A為預處理晶圓或808層上部在層切之後形成之結構。因此,在智慧切割之後,N+ 2304就出現在表面,現標記為24A04。表面電晶體源極24B04和汲極24B06透過將柵極24B02及電晶體22B08之隔離層。指定區域之N+蝕刻掉形成。該步驟與預處理晶圓或808層之表面對準,使得所形成之電晶體可以與預處理晶圓或808層之下層形成良好連接。然後執行額外之掩膜和蝕刻步驟,去除電晶體之間之N-層,如圖24C02所示,由此得到圖24C所 示更好的電晶體隔離層。圖24D為P+區域24D02之可選成型方法,用於加工JFET柵極。在該方法中,可能需要使用鐳射或其他光學緩冷方法來開啟P+。圖24E為如何在預處理晶圓或808層上部進行鐳射退火,減小熱傳遞。在較厚氧化物澱積24E02之後,將在反光層添加一層鋁24D04或其他反光材料。在反光層之開口24D08掩膜和蝕刻加工之後,鐳射24D06能夠退火P+ 24D02摻雜區域,並將鐳射能量24D06之大部分從預處理晶圓或808層之上反射出去。通常,開口區域24D08之面積小於整個晶圓面積之10%。另外,可以將一層銅24D10,或者一層反光率,或其他反光材料,加工到預處理晶圓或808層之上,使得能夠將不需要之鐳射能量24D06反射開,而不會讓熱量傳遞到預處理晶圓或808層上。當成型組件和電路工作時,層24D10也可以用作接地平面或導電背柵極。當然,層24D10也可以加工出開口,用來建設後續連接第二表面切出層和預處理晶圓或808層之過孔。相同之反光鐳射退火或其他光學退火技術可以用來退火上述任何結構,使得在第二層切出流程中可以對電晶體柵極進行摻雜開啟。另外,吸油材料,和/或其他發光材料,可以用在上述鐳射或其他光學退火方法中。如圖24E-1所示,光能吸收層24E04,可以是無定型碳,可以在低溫下澱積或噴射到需要鐳射退火之區域,然後相應進行掩膜和蝕刻加工。這樣,就可以使用最少之鐳射或其他光學能量來有效退火該區域,開啟摻雜材料,並將反光層24D04 & 24D10、預處理晶圓或808層之熱應力降 至最低。鐳射退火可以對整個晶圓表面使用,也可以對柵極電路所在區域使用,以便進一步減小總熱量並保證不會對下層造成傷害。 24A-24F are schematic diagrams of forming the top junction field effect (JFET) planar transistor. Figure 24A shows the structure formed after layer dicing on the pre-processed wafer or layer 808. So after the Wisdom Cut, N+ 2304 appeared on the surface, now labeled 24A04. The surface transistor source 24B04 and the drain 24B06 pass through the isolation layer connecting the gate 24B02 and the transistor 22B08. The N+ in the specified area is etched away to form. This step is aligned with the surface of the pre-processed wafer or layer 808 so that the formed transistors can form good connections with the pre-processed wafer or layers below the 808 layer. Additional masking and etching steps are then performed to remove the N-layer between the transistors, as shown in Figure 24C02, thereby obtaining the Indicates a better transistor isolation layer. Figure 24D is an alternative shaping method for P+ region 24D02 for processing JFET gates. In this approach, it may be necessary to turn on P+ using laser or other optical slow cooling methods. FIG. 24E shows how to perform laser annealing on the preprocessed wafer or the upper part of the 808 layer to reduce heat transfer. After the thicker oxide deposition 24E02, a layer of aluminum 24D04 or other reflective material will be added to the reflective layer. Laser 24D06 anneals the P+ 24D02 doped regions after masking and etching the openings 24D08 of the reflective layer and reflects most of the laser energy 24D06 away from the preprocessed wafer or above the 808 layer. Typically, the area of the open region 24D08 is less than 10% of the entire wafer area. In addition, a layer of copper 24D10, or a layer of reflectivity, or other reflective material, can be processed onto the pre-processed wafer or 808 layer, so that the unwanted laser energy can be reflected away from the 24D06 without heat transfer to the pre-processed wafer. processing on wafer or 808 layer. Layer 24D10 can also be used as a ground plane or a conductive back gate when molding components and circuits. Of course, the layer 24D10 can also be processed with openings, which can be used to build subsequent vias connecting the second surface cut-out layer and the pre-processed wafer or the 808 layer. The same reflective laser annealing or other optical annealing techniques can be used to anneal any of the above structures so that the gate of the transistor can be doped and turned on during the second layer cutting process. Additionally, oil absorbing materials, and/or other luminescent materials, may be used in the laser or other optical annealing methods described above. As shown in FIG. 24E-1, the light energy absorbing layer 24E04 can be amorphous carbon, which can be deposited or sprayed at low temperature to the area requiring laser annealing, and then masked and etched accordingly. In this way, the minimum amount of laser or other optical energy can be used to effectively anneal the area, turn on the dopant material, and reduce the thermal stress of the reflective layer 24D04 & 24D10, the pre-processed wafer or the 808 layer. to minimum. Laser annealing can be used on the entire wafer surface, or on the area where the gate circuit is located, in order to further reduce the total heat and ensure that it will not cause damage to the underlying layer.

圖24F所示之結構,在下述加工程式之後得到,鐳射反光層24D04蝕刻,澱積,掩膜,蝕刻厚氧化物層24F04得到開口觸點24F06和24F02,澱積和部分蝕刻(或者化學機械打磨(CMP))鋁(或其他金屬,在24F02處得到一個Schottky或Ohmic觸點)形成24F06觸點和柵極24F02。必要時,N+觸點24F06和柵極觸點24F02可以分開進行掩膜和蝕刻處理,使得之上可以澱積不同之金屬,以便在柵極24F02上得到Schottky或Ohmic觸點,在N+觸點24F06上得到ohmic連接。厚氧化物層24F04為非導電絕緣材料,也填充至表層電晶體之間之蝕刻空隙24B08和24B09,並可以使用其他隔離材料,例如矽氮化物。表層電晶體最後會被隔離絕緣材料包圍,與傳統整塊積體電路電晶體不同,傳統電晶體在一個單晶矽晶圓上加工,僅被非導電絕緣材料包圍。該流程能夠形成單晶表層JFET電晶體,能夠與下層多金屬層半導體組件相連,無需將下層組件裸露在高溫中。 The structure shown in FIG. 24F is obtained after the following processing formula, laser reflective layer 24D04 etching, deposition, masking, etching thick oxide layer 24F04 to obtain opening contacts 24F06 and 24F02, deposition and partial etching (or chemical mechanical polishing) (CMP)) Aluminum (or other metal to get a Schottky or Ohmic contact at 24F02) forms the 24F06 contact and gate 24F02. If necessary, the N+ contact 24F06 and the gate contact 24F02 can be masked and etched separately, so that different metals can be deposited on it to obtain a Schottky or Ohmic contact on the gate 24F02, and the N+ contact 24F06 to get an ohmic connection. The thick oxide layer 24F04 is a non-conductive insulating material that also fills the etched gaps 24B08 and 24B09 between the surface transistors, and other isolation materials such as silicon nitride may be used. Surface transistors are finally surrounded by isolating insulating materials. Unlike traditional bulk integrated circuit transistors, traditional transistors are processed on a single-crystal silicon wafer and surrounded only by non-conductive insulating materials. This process can form a single crystal surface JFET transistor, which can be connected to the underlying multi-metal layer semiconductor component without exposing the underlying component to high temperature.

在上述流程之另一個方案中,可以使用電晶體技術-偽MOSFET,利用但分子層,該層透過共價鍵嫁接到汲極和源極之間之溝道區域。這一工藝流程可以在相對較低之溫度下進行(低於400攝氏度)。 In another version of the above flow, transistor technology - pseudo-MOSFET, can be used, using a molecular layer that is covalently grafted to the channel region between the drain and source. This process can be carried out at relatively low temperatures (less than 400 degrees Celsius).

另外一個方法是使用預處理晶圓進行層切,如圖25所 示。圖25A為使用預處理晶進行層切之示意圖;N-晶圓2502可以加工出一個埋入層N+2304,透過摻雜和開啟實現,也可透過N-累晶生長2508之後之淺層N+摻雜和擴散實現。表面額外加工一個P+層2510。P+層2510可以再次使用摻雜和開啟,或者P+累晶生長進行加工。圖25B為一個預處理晶圓,經過澱積或氧化物2512之生長後可以用於層切,經過摻雜原子,例如H+後,可以在N+區域2504之下部準備好智慧切割之切出平面2506。現在可以執行層切流程,來加工預處理單晶矽,摻雜有N-和N+之層,該層位於預處理晶圓或層808之上。 Another method is to use pre-processed wafers for layer dicing, as shown in Figure 25 Show. Figure 25A is a schematic diagram of layer dicing using pre-processed crystals; N-wafer 2502 can process a buried layer N+ 2304, which can be realized through doping and opening, and can also be achieved through the shallow N+ layer after N-cumulative crystal growth 2508 Doping and diffusion are achieved. A P+ layer 2510 is additionally processed on the surface. The P+ layer 2510 can again be processed using doping and turning on, or P+ cumulative growth. 25B is a pre-processed wafer, which can be used for layer cutting after deposition or growth of oxide 2512. After doping atoms, such as H+, a cutting plane 2506 for intelligent cutting can be prepared under the N+ region 2504. . The layer slicing process can now be performed to process the preprocessed monocrystalline silicon, doped with N- and N+ layers, on top of the preprocessed wafer or layer 808 .

圖26A-24E為上部結柵場效應(JFET)平面電晶體(帶有逆偏壓閘或雙閘)之成型示意圖。圖26A為預處理晶圓或808層上部之切出層,在智能切割之後,N+ 2504位於表面。表面電晶體源極26B04和汲極26B06透過將柵極26B02及電晶體26B08之隔離層。指定區域之N+蝕刻掉形成。該步驟與預處理晶圓或808層之表面對準,使得所形成之電晶體可以與預處理晶圓或808層之下層形成良好連接。之後,經過掩膜和蝕刻加工,除去電晶體26C12之間之N-,使之與現在之埋入P+層2510接觸。然後執行另一個掩膜和蝕刻步驟,去除電晶體之間之P+層2510,由此得到圖26C所示之完全隔離。圖26D為淺層P+區域26D02之備選成型方法,用於構造柵極。在該方法中,可能需要使用鐳射退火來開啟P+。圖26E所示結構,透過以下步驟得到,厚氧化物層26E04之澱積和蝕刻/CMP,澱積和回蝕鋁(或 其他金屬,在26E02處獲得最佳Schottky或ohmic觸點),獲得觸點26E06、26E12和柵極26E02。必要時,N+觸點26E06和柵極觸點26E02可以分開進行掩膜和蝕刻處理,使得其上可以澱積不同之金屬,以便在柵極26E02上得到Schottky或Ohmic觸點,在N+觸點26E06 & 26E12上得到ohmic連接。厚氧化物層26E04為非導電絕緣材料,也填充至表層電晶體之間之蝕刻空隙26B08和26B09,並可以使用其他隔離材料,例如矽氮化物。觸點26E12允許添加電晶體背柵,或可以與柵極26E02相連,構成雙柵極JFET。另外,背柵之連接可以包含在預處理晶圓或808層之中,從下方連接層2510。該流程能夠形成單晶表層超薄體JFET電晶體,帶有背柵或雙柵極功能,能夠與下層多金屬層半導體組件相連,無需將下層組件裸露在高溫中。 26A-24E are schematic diagrams of the formation of the upper junction field effect (JFET) planar transistor (with reverse bias gate or double gate). Figure 26A is a pre-processed wafer or cut out layer on top of layer 808, after smart dicing, N+ 2504 is on the surface. The surface transistor source 26B04 and the drain 26B06 pass through the isolation layer connecting the gate 26B02 and the transistor 26B08. The N+ in the specified area is etched away to form. This step is aligned with the surface of the pre-processed wafer or layer 808 so that the formed transistors can form good connections with the pre-processed wafer or layers below the 808 layer. Afterwards, through masking and etching, the N- between the transistors 26C12 is removed to make it contact with the buried P+ layer 2510 now. Another masking and etching step is then performed to remove the P+ layer 2510 between the transistors, thereby obtaining complete isolation as shown in Figure 26C. Figure 26D is an alternative shaping method of the shallow P+ region 26D02 for constructing the gate. In this approach, laser annealing may be required to turn on P+. The structure shown in Figure 26E is obtained by the following steps, deposition and etch/CMP of thick oxide layer 26E04, deposition and etch back of Al (or Other metals, get the best Schottky or ohmic contacts at 26E02), get contacts 26E06, 26E12 and gate 26E02. If necessary, the N+ contact 26E06 and the gate contact 26E02 can be masked and etched separately, so that different metals can be deposited thereon to obtain a Schottky or Ohmic contact on the gate 26E02, and the N+ contact 26E06 & ohmic connection on 26E12. The thick oxide layer 26E04 is a non-conductive insulating material that also fills the etched gaps 26B08 and 26B09 between the surface transistors, and other isolation materials such as silicon nitride may be used. Contact 26E12 allows the addition of a transistor back gate, or can be connected to gate 26E02 to form a dual gate JFET. Alternatively, back gate connections may be included in the preprocessed wafer or layer 808, connecting layer 2510 from below. This process can form a single crystal surface ultra-thin body JFET transistor with back gate or double gate function, which can be connected to the underlying multi-metal layer semiconductor components without exposing the underlying components to high temperature.

另外一個方法是使用預處理晶圓進行層切,如圖27所示。圖27A為使用預處理晶進行層切之示意圖;一個N+晶圓2702處理後具有埋入層,透過離子注入和開啟退火實現,也可以透過擴散來建設一個垂直結構,之上建設NPN塊(或PNP塊)雙極電晶體。累晶生長之層可以用來建設摻雜多層結構。從P層2704開始,然後是N-層2708,最後是N+層2710,最後透過退火至較高之開啟溫度將上述層開啟。圖27B為一個預處理晶圓,經過澱積或氧化物2712之生長後可以用於層切,經過摻雜原子,例如H+後,可以在N+區域之準備好智慧切割之切出平面2706。現在可以執行層切流程,來加工預處理層,該層位於預處理晶圓 或層808之上。 Another method is to use pre-processed wafers for layer dicing, as shown in Figure 27. FIG. 27A is a schematic diagram of layer dicing using preprocessed crystals; an N+ wafer 2702 is processed with a buried layer, which is realized by ion implantation and open annealing, and can also be constructed by diffusion to build a vertical structure, and NPN blocks (or PNP block) bipolar transistor. Cumulatively grown layers can be used to build doped multilayer structures. Starting with the P layer 2704, then the N- layer 2708, and finally the N+ layer 2710, which are finally turned on by annealing to a higher turn-on temperature. FIG. 27B is a pre-processed wafer, which can be used for layer cutting after deposition or growth of oxide 2712. After doping atoms, such as H+, it can be cut out in the N+ region ready for smart dicing 2706. The layer slicing process can now be performed to process the pre-processed layer, which is located on the pre-processed wafer or layer 808 above.

圖28A-E為表層雙極電晶體之成型示意圖。圖28A為預處理晶圓或808層上部之切出層,在智能切割之後,N+28A02(2702之一部分)位於表面。通常在這點上,有一個巨型電晶體覆蓋在整個晶圓上。以下為多個蝕刻步驟,如圖28B-28D所示,巨型電晶體切割並按需要劃分後,與底層預處理晶圓或808層對準。蝕刻步驟還使得包含雙極電晶體之不同層露出來,實現發射極2806、基極2802和集電極2808之接觸,然後一直蝕刻至預處理晶圓或808層之表面氧化物層,將圖28D中之電晶體隔離。表層N+摻雜層28A02可以按如圖28B所示進行掩膜和蝕刻加工,形成發射極2806。然後,P 2704和N-2706摻雜層可以按如圖28C所示進行掩膜和蝕刻加工,形成基極2802。隨後,集電極層2710進行掩膜和蝕刻,直至預處理晶圓或808層之表面氧化物層,實現圖28D中之電晶體隔離2809。全部結構可以使用低溫氧化物2804覆蓋,氧化物使用CMP整平,然後進行掩膜和蝕刻,實現圖28E所示之發射極2806、基極2802和集電極2808之接觸。厚氧化物層2804為非導電絕緣材料,填充至表層電晶體之間之蝕刻空隙2809,並可以使用其他隔離材料,例如矽氮化物。該流程能夠形成單晶表層雙極電晶體,能夠與下層多金屬層半導體組件相連,無需將下層組件裸露在高溫中。 28A-E are schematic diagrams showing the formation of surface bipolar transistors. FIG. 28A is the sliced layer on top of the preprocessed wafer or layer 808. After smart dicing, N+28A02 (part of 2702) is on the surface. Usually at this point, there is one giant transistor covering the entire wafer. The following are multiple etching steps, as shown in FIGS. 28B-28D , after the giant transistor is cut and divided as required, it is aligned with the underlying pre-processed wafer or layer 808. The etch step also exposes the different layers comprising the bipolar transistor, making contact with the emitter 2806, base 2802, and collector 2808, and then etch down to the surface oxide layer of the pre-processed wafer or layer 808, Figure 28D Transistor isolation. The surface N+ doped layer 28A02 can be masked and etched as shown in FIG. 28B to form an emitter 2806 . Then, the P 2704 and N-2706 doped layers can be masked and etched as shown in FIG. 28C to form the base 2802 . Subsequently, the collector layer 2710 is masked and etched until the surface oxide layer of the pre-processed wafer or layer 808 to achieve transistor isolation 2809 in FIG. 28D. The entire structure can be covered with a low temperature oxide 2804, the oxide is leveled using CMP, then masked and etched to achieve the contacts of the emitter 2806, base 2802 and collector 2808 shown in Figure 28E. The thick oxide layer 2804 is a non-conductive insulating material that fills the etched gaps 2809 between the surface transistors, and other isolation materials such as silicon nitride can be used. The process enables the formation of single-crystal surface bipolar transistors that can be connected to underlying multi-metal semiconductor components without exposing the underlying components to high temperatures.

圖27和圖28所示得到之雙極電晶體可以用來構成類比或數位BiCMOS電路,CMOS電晶體位於基板初晶層802和 預處理晶圓或808層,雙極電晶體可以佈置在切出之表層。 The obtained bipolar transistors shown in Fig. 27 and Fig. 28 can be used to form analog or digital BiCMOS circuits, and the CMOS transistors are located in the substrate primary layer 802 and For pre-processed wafers or 808 layers, bipolar transistors can be placed on the cut surface.

另外一類組件可以在層切至帶有金屬互聯電路之基板之前,在高溫下構造,然後在層切至無結電晶體(JLT)後,在低溫下完成。例如,在深度次微米工藝中,使用了銅噴鍍,因此,可以達到大約400攝氏度以上之高溫,低溫則在400攝氏度及以下。無結電晶體之結構避免了在矽技術放縮時所需之尖銳分層之結點,並能夠建設較厚之柵極氧化層,具有與傳統MOSFET電晶體相當之性能。無結電晶體也稱為無結納米線電晶體,或者柵極選電阻,或者納米線電晶體,見《自然》納米技術2010年2月21日,由Jean-Pierre Colinge等發表。建設無結電晶體時,電晶體溝道可以是一個薄固體片,均勻重度摻雜之單晶矽。溝道之摻雜濃度可以與源極和汲極相同。需要考量的是,納米線溝道必須足夠薄足夠窄,使得當組件關閉時能夠完全利用載流子,並且溝道之摻雜必須足夠高,使得當組件打開後能夠產生所需之電流。這些考量可能導致工藝變化之餘地很小,限制了溝道厚度、寬度、柵極獲得逸出功所需之摻雜濃度,和柵極氧化層厚度。 Another type of device can be constructed at high temperature before layer dicing to the substrate with metal interconnect circuits, and then finished at low temperature after layer dicing to junction-less transistor (JLT). For example, in the deep sub-micron process, copper plating is used, so high temperatures above about 400 degrees Celsius can be achieved, and low temperatures are at and below 400 degrees Celsius. The structure of the junctionless transistor avoids the sharp layered junctions required in the scaling of silicon technology, and can build a thicker gate oxide layer, which has performance comparable to that of traditional MOSFET transistors. Junctionless transistors are also known as junctionless nanowire transistors, or gate selection resistors, or nanowire transistors, see Nature Nanotechnology, 21 February 2010, published by Jean-Pierre Colinge et al. When building a junctionless transistor, the transistor channel can be a thin solid sheet of uniformly heavily doped single crystal silicon. The channel can be doped at the same concentration as the source and drain. The considerations are that the nanowire channel must be thin enough and narrow enough to fully utilize the carriers when the device is off, and the channel must be doped high enough to generate the required current when the device is on. These considerations can lead to little room for process variation, limiting channel thickness, width, dopant concentration required for gate work function, and gate oxide thickness.

無結電晶體組件挑戰之一就是在柵極偏壓為0時,關閉溝道之漏電最小。為了提高柵極對電晶體溝道之控制,溝道可以非均勻摻雜,濃度最高之摻雜離柵極最近,並且溝道之摻雜比柵極電極要輕要遠。例如,2、3、或4個柵極之無結電晶體溝道之中間要比邊緣摻雜濃度輕。這樣就 是之柵極之逸出功之洩漏電流較低,並且實現控制。如圖52A和52B所示,分別在對數和線形縮放下,模擬汲極至模擬源極之電流I,作為柵極電壓V之函數,來表示出不同無結電晶體溝道之摻雜,其中n-溝道之總厚度為20nm。每個圖形之4插接條曲線中,有2個對應於均勻摻雜20nm溝道至1E17和1E18 atoms/cm3濃度。剩下之2插接條曲線表示之類比結果為,20nm溝道分別由2層10nm厚之摻雜層。剩下2插接條曲線之圖例解釋中,第一個數字對應於10nm層最接近柵極電極之部分。例如,曲線D=1I18/1I17,表示模擬結果10nm溝道摻雜濃度在1E18之部分,離柵極電極最近,而10nm溝道中,摻雜為1E17濃度之部分離柵極電極較遠。圖52A中,曲線5202和5204分別對應於摻雜圖形之D=1I18/1E17。依照圖52A,在V=0v時,摻雜區域,D=1E18/1E17之漏電電流大比相反摻雜區域D=1E17/1E18低50倍。類似的,圖52B中,曲線5206和5208分別對應於摻雜圖形之D=1I18/1E17。圖52B中,V=1v時,兩個摻雜區域之I均只相差幾個百分點。 One of the challenges of junctionless transistor devices is to minimize the leakage of the closed channel when the gate bias is zero. In order to improve the control of the gate to the transistor channel, the channel can be non-uniformly doped, the doping with the highest concentration is closest to the gate, and the doping of the channel is lighter and farther than the gate electrode. For example, junctionless transistor channels with 2, 3, or 4 gates are doped more lightly in the middle than at the edges. so that Therefore, the leakage current of the work function of the gate is low and controlled. As shown in Figures 52A and 52B, under logarithmic and linear scaling, respectively, the simulated drain to simulated source current I, as a function of the gate voltage V, to represent the doping of different junctionless transistor channels, where The total thickness of the n-channel is 20 nm. Of the 4 bar curves in each graph, 2 correspond to uniformly doped 20nm channels to concentrations of 1E17 and 1E18 atoms/cm3. The analog results shown by the remaining 2 plug-in curves are that the 20nm channel consists of two 10nm-thick doped layers respectively. In the legend for the remaining 2 bar curves, the first number corresponds to the portion of the 10nm layer closest to the gate electrode. For example, the curve D=1I18/1I17 indicates that the part of the 10nm channel doped with a concentration of 1E18 is the closest to the gate electrode, while the part doped with a concentration of 1E17 in the 10nm channel is farther away from the gate electrode. In FIG. 52A, curves 5202 and 5204 correspond to D=1I18/1E17 of the doping pattern, respectively. According to FIG. 52A, when V=0v, the leakage current of the doped region D=1E18/1E17 is 50 times lower than that of the opposite doped region D=1E17/1E18. Similarly, in FIG. 52B, curves 5206 and 5208 correspond to D=1I18/1E17 of the doping pattern, respectively. In Fig. 52B, when V=1v, the I of the two doped regions differ only by a few percentage points.

無結電晶體溝道之摻雜可以均勻進行、分層進行,或隔層進行。電晶體溝道也可以不適用摻雜單晶矽建設,例如多晶矽、其他半導體、絕緣、或導電材料,例如石墨或其他石墨材料,或者使用與其他層類似或不同材料之組合。例如,溝道之中心可以包含一層氧化物,或者輕度摻雜之矽,邊緣可以是重度摻雜之單晶矽。這樣就可以提高電阻之柵極在斷電狀態下之控制效果,由於溝道內其他層 之應變效應,還可能增加通路電流。應變技術還可用於覆蓋和上下層絕緣材料,以及周圍之電晶體溝道和柵極。晶格修飾也可用於拉伸矽,例如嵌入之SiGe摻雜和退火。電晶體溝道之介面可以是矩形、原型、或橢圓形,以便提高柵極對溝道之控制。另外,為了是P-溝道無結電晶體在3D層切加工時之行動性達到最佳狀態,在黏結之前,施主晶圓可以相對於受主晶圓旋轉90度,以有利於<110>矽平面方向上P-溝道之形成。 The doping of the junctionless transistor channel can be done uniformly, in layers, or in separate layers. Transistor channels may also be constructed without doped monocrystalline silicon, such as polysilicon, other semiconducting, insulating, or conducting materials, such as graphite or other graphitic materials, or using combinations of similar or different materials from other layers. For example, the center of the channel can consist of a layer of oxide, or lightly doped silicon, and the edges can be heavily doped single crystal silicon. In this way, the control effect of the gate of the resistor in the off state can be improved, because other layers in the channel The strain effect may also increase the channel current. Straining techniques can also be used for capping and upper and lower insulating materials, as well as surrounding transistor channels and gates. Lattice modification can also be used to stretch silicon, such as embedded SiGe doping and annealing. The interface of the transistor channel can be rectangular, circular, or elliptical in order to improve gate-to-channel control. In addition, in order to achieve the best mobility of P-channel non-junction transistors during 3D layer cutting, before bonding, the donor wafer can be rotated 90 degrees relative to the acceptor wafer, which is beneficial to <110> Formation of P-channels in the silicon plane direction.

為了建設一個n型4面柵控無結電晶體,需要對矽晶圓進行預處理,然後如圖56A-56G所示,進行層切。這些流程可能需要在高於400攝氏度之插接條件下進行,因為尚未完成層切至具有金屬互聯電路之基板。如圖56A所示,N-晶圓可以加工出一個層N+ 5604A,透過摻雜和開啟實現,也可透過N+累晶生長,或透過在重度N+摻雜之多晶矽形成澱積層實現。柵極氧化物5602A可以在摻雜之前或之後生長,厚度大約為所需最終表層柵極氧化物厚度之一半。圖56B為一個預處理晶圓,可用於層切,經過摻雜原子5606,例如H+後,可以在基板之N-區域5600A中準備好切出平面5608,然後經過電漿或其他表面處理,形成晶圓氧化層之氧化物表面,供氧化物進行黏結。另外一個晶圓按照如上方式加工,但是未使用H+進行摻雜,然後如圖56C所示,將兩個晶圓黏結,用於層切出預處理單晶矽N-和N+層和半柵極氧化層,在類似之預處理,但是切出層未摻雜之N-晶圓5600及N+層5604和氧化層5602。表面晶 圓進行層切,並與下方晶圓分離。這樣,表面晶圓也可以用來處理和重新加工更多層,用以建設電阻層。剩下之表面晶圓N-和N+層,使用化學機械打磨,直至得到非常薄之N+矽晶層5610,如圖56D所示。這一薄N+摻雜矽晶層5610之厚度在5-40nm之間,並最終構成電阻,電阻在4個方向上具有柵控。兩個“半”柵極氧化層5602、5602A,現在可以鍵合到一起,形成柵極氧化層5612,該層最終加工成無結型電晶體之表面柵極氧化層,如圖56E所示。可以使用高溫退火來去除殘餘之氧化物或表面電荷。 In order to build an n-type 4-sided gate-controlled junctionless transistor, the silicon wafer needs to be pretreated, and then layered as shown in FIGS. 56A-56G . These processes may need to be performed at temperatures above 400°C for mating because the layers have not yet been cut to the substrate with the metal interconnect circuitry. As shown in Figure 56A, an N- wafer can be processed with a layer N+ 5604A, which can be achieved by doping and turning on, or by N+ cumulative growth, or by forming a deposited layer on heavily N+ doped polysilicon. Gate oxide 5602A can be grown before or after doping to a thickness approximately half of the desired final surface gate oxide thickness. Figure 56B is a pre-processed wafer, which can be used for layer cutting. After doping atoms 5606, such as H+, a plane 5608 can be prepared in the N-region 5600A of the substrate, and then undergo plasma or other surface treatment to form The oxide surface of the wafer oxide layer is used for bonding of oxides. Another wafer is processed as above, but not doped with H+, and then as shown in Figure 56C, the two wafers are bonded for layer cutting out of pre-processed single crystal silicon N- and N+ layers and half gates Oxide layer, in a similar pre-treatment, but cut out layers undoped N- wafer 5600 and N+ layer 5604 and oxide layer 5602. surface crystal The circle is sliced and separated from the underlying wafer. In this way, the surface wafer can also be used to process and rework more layers to build the resistive layer. The remaining surface wafer N- and N+ layers are chemically mechanically polished until a very thin N+ silicon layer 5610 is obtained, as shown in FIG. 56D . This thin N+ doped silicon layer 5610 has a thickness between 5-40nm and finally forms a resistor with gate control in 4 directions. The two "half" gate oxides 5602, 5602A can now be bonded together to form the gate oxide 5612, which is ultimately processed into the surface gate oxide of the junctionless transistor, as shown in Figure 56E. A high temperature anneal can be used to remove residual oxide or surface charge.

或者,將構造出圖56C中之底部晶圓,N+層5604可以用來建設重度摻雜之多晶矽,並且半柵極氧化層5602在層切之前澱積或生長。底部晶圓N+矽晶或多晶層5604將最終成為無結型電晶體之上層柵極。 Alternatively, to construct the bottom wafer in Figure 56C, the N+ layer 5604 can be used to build heavily doped polysilicon, and the half gate oxide 5602 deposited or grown prior to layer dicing. The bottom wafer N+ silicon or poly layer 5604 will eventually become the upper gate of the junctionless transistor.

如圖56E-56G所示,晶圓進行常規加工,溫度需高於400攝氏度,製備出可以層切為無結型電晶體結構之加工“外殼”晶圓808。可以生長一薄層氧化物,用來保護較薄之電阻矽層5610之表面,然後就可以掩模蝕刻出薄電阻層上具有重複間距之平行導線5614,如圖56E所示,然後清理光刻膠。該薄氧化層,如有,可以在稀釋之氫氟酸(HF)溶液中脫去,然後生長出常規氧化層5616和多晶矽層5618,可以摻雜也可以不摻雜,進行澱積,如圖56F所示。對多晶矽進行化學和機械打磨(CMP)平整,並生長或澱積出薄氧化層5620,以便在下一步進行低溫氧化物-氧化物晶圓黏結。多晶矽5618可以進行額外之摻雜, 在CMP之前或之後。多晶矽最終加工成無結型電晶體之底部和側面柵極。圖56G為一個預處理晶圓,可用於層切,經過摻雜原子5606,例如H+,可以在基板之N-區域5600中準備好“切出平面”5608G,然後經過電漿或其他表面處理,形成晶圓氧化層之氧化物表面,供氧化物進行黏結。受主晶圓808具有邏輯電晶體和金屬互聯電路,進行預處理後,可用於低溫氧化物-氧化物晶圓黏結,及表層氧化物表面處理,黏結如圖56H所示。表層施主晶圓層切之後,與下方受主晶圓808分離,表層N-基板透過CMP清除。外殼808中之金屬佈線帶5622如圖56H所示。 As shown in FIGS. 56E-56G , the wafer is conventionally processed, and the temperature needs to be higher than 400 degrees Celsius to prepare a processed "shell" wafer 808 that can be sliced into a junctionless transistor structure. A thin layer of oxide can be grown to protect the surface of the thin resistive silicon layer 5610, and then the parallel conductive lines 5614 with repeated spacing on the thin resistive layer can be mask-etched, as shown in FIG. 56E, and then the photolithography is cleaned. glue. This thin oxide layer, if any, can be removed in a diluted hydrofluoric acid (HF) solution, and then a conventional oxide layer 5616 and a polysilicon layer 5618, which can be doped or undoped, can be deposited, as shown in the figure 56F. Perform chemical and mechanical polishing (CMP) to planarize the polysilicon, and grow or deposit a thin oxide layer 5620 for low temperature oxide-oxide wafer bonding in the next step. Polysilicon 5618 can be additionally doped, before or after CMP. Polysilicon is finally processed into the bottom and side gates of junctionless transistors. Figure 56G is a pre-processed wafer, which can be used for layer cutting. After doping atoms 5606, such as H+, a "cut out plane" 5608G can be prepared in the N- region 5600 of the substrate, and then undergo plasma or other surface treatment, Form the oxide surface of the wafer oxide layer for bonding of oxides. The acceptor wafer 808 has logic transistors and metal interconnection circuits. After pretreatment, it can be used for low-temperature oxide-oxide wafer bonding and surface oxide surface treatment. The bonding is shown in FIG. 56H. After the surface donor wafer is sliced, it is separated from the lower acceptor wafer 808, and the surface N-substrate is removed by CMP. Metal wiring straps 5622 in housing 808 are shown in Figure 56H.

圖56I為晶圓之俯視圖,與56H步驟相同,並有2個剖視圖I和II。N+層5604,最終構成電阻之頂柵,和頂柵氧化層5612將控制電阻線5614之一側,底部和側面柵極氧化層5616和多晶層底部及側面柵極5618控制電阻5614之其他三個側面。邏輯器外殼晶圓808具有上氧化層5624,將頂部金屬佈線插接條5622包裹起來,如俯視圖中外部虛線所示。 Figure 56I is a top view of the wafer, which is the same as step 56H, and has two cross-sectional views I and II. N+ layer 5604, which ultimately forms the top gate of the resistor, and top gate oxide 5612 will control one side of resistor line 5614, bottom and side gate oxide 5616 and poly bottom and side gate 5618 control the other three sides of resistor 5614 side. The logic housing wafer 808 has an upper oxide layer 5624 that wraps the top metal routing strips 5622, as indicated by the outer dashed lines in the top view.

在圖56J中,打磨中止層5626可以使用氧化物或矽氮化物等材料,在晶圓之表層進行澱積,隔離開孔5628經過掩模和蝕刻至外殼808氧化層5624之深度,使得能夠完全隔離電晶體。隔離開孔5628完全使用低溫填充氧化物,然後經過化學和機械打磨(CMP)打磨平整。頂柵5630之掩模和蝕刻如圖56K所示,然後蝕刻開孔5629使用低溫填充氧化物澱積進行填充,經過化學和機械(CMP)打磨平 整,然後澱積另外一層氧化物,實現佈線金屬層之隔離。 In FIG. 56J, the grinding stop layer 5626 can be deposited on the surface layer of the wafer using materials such as oxide or silicon nitride, and the isolation opening 5628 is masked and etched to the depth of the oxide layer 5624 of the shell 808, so that it can be completely isolated transistor. The isolation opening 5628 is completely filled with low temperature oxide, and then polished flat by chemical and mechanical polishing (CMP). Top gate 5630 is masked and etched as shown in Figure 56K, then etched opening 5629 is filled using low temperature fill oxide deposition, chemically and mechanically (CMP) polished After that, another layer of oxide is deposited to realize the isolation of the wiring metal layer.

觸點之掩模和蝕刻如圖56L所示。柵極觸點5632經過掩模和蝕刻,使得觸點一直蝕刻穿過頂柵層5630,在金屬層開孔掩模和蝕刻過程中,柵極氧化物也被蝕刻,使得頂柵5630和底部5618柵極得以連接。連接電阻層5614兩個電極之觸點5634也被掩模和蝕刻。然後,至外殼晶圓808和金屬佈線插接條5622之穿層過孔5636進行掩模蝕刻加工。 Contacts are masked and etched as shown in Figure 56L. The gate contact 5632 is masked and etched such that the contact is etched all the way through the top gate layer 5630. During the metal layer opening masking and etching, the gate oxide is also etched such that the top gate 5630 and bottom 5618 The gate is connected. Contacts 5634 connecting the two electrodes of the resistive layer 5614 are also masked and etched. Then, the through-layer vias 5636 to the housing wafer 808 and the metal wiring strips 5622 are masked and etched.

如圖56M所示,金屬線5640由掩模定義並進行蝕刻,使用阻隔金屬和銅互聯電路填充,經過CMP和常規金屬互聯電路方案進行加工,完成觸點過孔5632與表層5630和底層5618柵極之同時連接,電阻5614之兩個電極5634之連接,以及與外殼晶圓808金屬互聯電路插接條5622之連接。該流程能夠形成單晶4面柵極無結電晶體,能夠與下層多金屬層半導體組件相連,無需將下層組件裸露在高溫中。 As shown in Figure 56M, the metal line 5640 is defined by a mask and etched, filled with barrier metal and copper interconnection circuit, processed by CMP and conventional metal interconnection circuit scheme, and completes contact via hole 5632 and surface layer 5630 and bottom layer 5618 gate Simultaneous connection, the connection of the two electrodes 5634 of the resistor 5614, and the connection with the metal interconnection circuit inserting strip 5622 of the shell wafer 808. This process can form a single crystal 4-sided gate junctionless transistor, which can be connected to the underlying multi-metal layer semiconductor component without exposing the underlying component to high temperature.

另外,如圖96A-96J所示,一個N-溝道4面柵控無結電晶體(JLT)可以在相應之3D IC製造過程中建設。4面柵控JL也可以成為全柵控JLT,或者矽納米線JLT。 Alternatively, as shown in FIGS. 96A-96J , an N-channel 4-sided gated junction-less transistor (JLT) can be constructed during the corresponding 3D IC fabrication process. The 4-sided gated JL can also become a fully gated JLT, or a silicon nanowire JLT.

如圖96A所示,一個P-或N-基板施主晶圓9600,可以加工成包含晶圓尺寸之N+摻雜矽晶層9602和9606,以及晶圓尺寸之N+SiGe9604和9608層。層9602、9604、9608可以進行累晶生長,然後依照厚度和化學計量學進行小心加工,以保持由於Si和下方SiGe之晶格不匹配導致之缺陷密度。SiGe之化學計量可能因層不同,將會導致不同之蝕 刻速率,下文詳述。部分實現不同蝕刻速率之技術包含:保持SiGe層之厚度低於形成缺陷之關鍵厚度。施主晶圓9600之表面可以進行氧化層9613澱積,從而可以進行氧化物晶圓黏結。這些流程可能需要在高於400攝氏度之插接條件下進行,因為尚未完成層切至具有金屬互聯電路之基板。個晶圓大小之層能夠提供一連續層之材料或材料組合,橫跨整個晶圓,直至晶圓之邊緣,並可能具有大約一致之厚度。如果晶圓大小之層包含摻雜物,則摻雜之濃度大體上會在x和y向上保持一致,但是可能在z向上(垂直晶圓表面)出現不同。 As shown in FIG. 96A, a P- or N-substrate donor wafer 9600 can be processed to include wafer-sized N+ doped silicon layers 9602 and 9606, and wafer-sized N+ SiGe layers 9604 and 9608. Layers 9602, 9604, 9608 can be cumulatively grown and then carefully processed in terms of thickness and stoichiometry to maintain defect density due to lattice mismatch between Si and underlying SiGe. The stoichiometry of SiGe may vary from layer to layer, resulting in different eclipses Tick rate, detailed below. Some techniques for achieving different etch rates include keeping the thickness of the SiGe layer below the critical thickness for defect formation. An oxide layer 9613 can be deposited on the surface of the donor wafer 9600, so that oxide wafer bonding can be performed. These processes may need to be performed at temperatures above 400°C for mating because the layers have not yet been cut to the substrate with the metal interconnect circuitry. A wafer-sized layer can provide a continuous layer of material or combination of materials across the entire wafer to the edge of the wafer, possibly with approximately uniform thickness. If a wafer-sized layer contains dopants, the dopant concentration will generally be consistent in the x and y directions, but may vary in the z direction (perpendicular to the wafer surface).

如圖96B所示,層切劃分平面9699(如虛線所示),可能在施主晶圓9600上,透過摻雜氦或其他前述方法實現。 As shown in FIG. 96B , the layer-slicing dividing plane 9699 (shown as a dotted line) may be implemented on the donor wafer 9600 by helium doping or other aforementioned methods.

如圖96C所示,施主晶圓9600和受主晶圓9610之表層都可以加工進行晶圓黏結,然後將施主晶圓9600反轉,與受主晶圓9610上之對準標記(未畫出)進行對準,然後在低溫下(大約低於400攝氏度)進行黏結。施主晶圓和受主晶圓9610表面之氧化層9613隨之進行原子鍵合,如圖示9614所示。 As shown in FIG. 96C , both the surface layers of the donor wafer 9600 and the acceptor wafer 9610 can be processed for wafer bonding, and then the donor wafer 9600 is reversed to align with the alignment marks on the acceptor wafer 9610 (not shown). ) for alignment and bonding at low temperatures (approximately below 400 degrees Celsius). The oxide layer 9613 on the surface of the donor wafer and the acceptor wafer 9610 are then atomically bonded, as shown in diagram 9614 .

如圖96D所示,P-施主晶圓基板9600之一部分,該晶圓位於層切劃分平面9699之上,可以透過切割和打磨、蝕刻或其他前述之低溫方法去除。CMP工藝可以用來去除剩餘之P-層,直至達到N+矽晶層9602。然後使用離子注入原子,如氦,之工藝,形成層切劃分平面,之後進行切割或 打薄,或可稱為“離子切割”。受主晶圓9610也可以使用類似於晶圓808之方法進行加工,晶圓808之加工參見圖8。 As shown in FIG. 96D, the portion of the P-donor wafer substrate 9600 that lies above the layer-slicing demarcation plane 9699 can be removed by dicing and grinding, etching, or other low temperature methods as previously described. The CMP process can be used to remove the remaining P- layer until the N+ silicon layer 9602 is reached. Then use the process of ion implantation of atoms, such as helium, to form the layer cutting division plane, and then cut or Thinning, or can be called "ion cutting". The acceptor wafer 9610 can also be processed using a method similar to that of the wafer 808, see FIG. 8 for the processing of the wafer 808.

如圖96E所示,N+矽堆和N+SiGe層可以加工成電晶體或溝道,然後柵極部分可以透過印刷劃線和N+矽層9602 & 9606及N+SiGe層9604&9608之電漿/RIE蝕刻獲得。結果可以得到N+SiGe9616堆和N+矽9618層。堆之間之隔離可以完全使用低溫填充氧化物9620填充,然後經過化學物理打磨(CMP)打磨平整。這樣就將各個電晶體完全隔開。堆之端部都在圖中畫出,以便理解。 As shown in Figure 96E, the N+ silicon stack and the N+ SiGe layer can be processed into transistors or channels, and then the gate part can be printed and scribed and the plasma/RIE of the N+ silicon layers 9602 & 9606 and the N+ SiGe layers 9604 & 9608 obtained by etching. As a result, N+SiGe9616 stacks and N+SiGe9618 layers can be obtained. The isolation between the stacks can be completely filled with low temperature fill oxide 9620, and then smoothed by chemical physical polishing (CMP). This completely separates the individual transistors. The ends of the pile are drawn in the figure for ease of understanding.

如圖96F所示,最終成群之或共同之柵極部分9630可以使用印刷劃線和氧化物蝕刻獲得。這樣就將電晶體溝道和柵極區域堆之側面露出來,由交替之N+矽9618和N+SiGe9616層組成,最終構成成群之或共同之柵極區9630。堆之端部都在圖中畫出,以便理解。 As shown in Figure 96F, the final grouped or common gate portion 9630 can be obtained using printed scribe and oxide etch. This exposes the sides of the transistor channel and gate region stack, consisting of alternating layers of N+Si 9618 and N+SiGe 9616, ultimately forming grouped or common gate regions 9630. The ends of the pile are drawn in the figure for ease of understanding.

如圖96G所示,露出之N+SiGe層9616可以透過選擇性蝕刻配方清除,而不會損害到N+矽層9618。這樣就在最終成群或共同之柵極區9630中形成了有空隙之N+矽區域9618。上述蝕刻配方在“高溫5nm半徑雙矽納米線MOSFET(TSNWFET):在Si晶圓堆上之製造、特徵及依賴性”,由S.D.Suk等編寫之Proc.IEDM Tech中,717-720頁,2005年出版。離頂部邊緣最遠之N+SiGe層可以按化學計量進行構造,使得該層(區域)(如N+SiGe層9608)獲得稍快之蝕刻速率,相對於其他離頂部較近之層 (如,N+SiGe層9604),並且能夠使得最終兩個堆電晶體之柵極長度相同。堆之端部都在圖中畫出,以便理解。 As shown in FIG. 96G, the exposed N+SiGe layer 9616 can be removed by a selective etch recipe without damaging the N+Si layer 9618. This forms a voided N+ silicon region 9618 in the final grouped or common gate region 9630 . The above etching recipe is in "High Temperature 5nm Radius Twin Silicon Nanowire MOSFET (TSNWFET): Fabrication, Characteristics and Dependencies on a Si Wafer Stack", Proc.IEDM Tech by S.D.Suk et al., pp. 717-720, 2005 published in the year. The N+SiGe layer furthest from the top edge can be structured stoichiometrically so that this layer (region) (eg, N+SiGe layer 9608) achieves a slightly faster etch rate relative to other layers closer to the top (eg, N+SiGe layer 9604), and can make the gate lengths of the final two stack transistors the same. The ends of the pile are drawn in the figure for ease of understanding.

如圖96H所示,有一個可選步驟,可以減小表面除草度、圓整邊緣,並打薄N+矽晶區域9618之直徑,上述區域裸露在成群或公共柵極區域,利用低溫進行氧化,然後用HF蝕刻去除氧化層。這一步可以重複多次。對於裸露之N+矽晶表面,也可以在氧化過程中加入氦,或者使用電漿處理進行鍵合。這樣就可以得到圓整之矽似納米線結構,形成最終之電晶體柵控溝道9636。堆之端部都在圖中畫出,以便理解。 As shown in Figure 96H, there is an optional step to reduce the surface weeding, round the edges, and thin the diameter of the N+ silicon region 9618, which is exposed in the cluster or common gate area, and use low temperature oxidation , and then etched with HF to remove the oxide layer. This step can be repeated multiple times. For bare N+ silicon surfaces, helium can also be added during oxidation, or bonded using plasma treatment. In this way, a round silicon-like nanowire structure can be obtained to form the final gate-controlled channel 9636 of the transistor. The ends of the pile are drawn in the figure for ease of understanding.

如圖96I所示,可以將基於低溫之柵極絕緣體澱積並加密化,用作無結型電晶體之柵極氧化物。另外,可以使用低溫微波離子束氧化處理最終電晶體之柵控溝道9636之矽晶表面,作為JLT柵極氧化物或使用原子層澱積(ALD)技術構成HKMG柵極氧化物。也可以進行低溫柵極材料9612澱積,例如P+摻雜無定型矽。另外,高K金屬柵極結構也可以使用如下流程得到。對柵極材料澱積進行CMP處理。堆之端部都在圖中畫出,以便理解。 As shown in Figure 96I, a low temperature based gate insulator can be deposited and densified for use as the gate oxide for junctionless transistors. In addition, the silicon surface of the gate control channel 9636 of the final transistor can be oxidized by low-temperature microwave ion beam as JLT gate oxide or HKMG gate oxide can be formed by atomic layer deposition (ALD) technology. Low temperature gate material 9612 deposition, such as P+ doped amorphous silicon, can also be performed. In addition, the high-K metal gate structure can also be obtained using the following process. A CMP process is performed on the gate material deposition. The ends of the pile are drawn in the figure for ease of understanding.

圖96J給出了,在圖96I中形成之完整JLT電晶體堆,為了清晰起见,未畫出氧化層,還包含圖96I中之橫截面切割I。柵極9612包圍了電晶體柵控溝道9636,每個成群之電晶體矽都被氧化物9622與其他堆隔離。電晶體堆源極和汲極之連接可以移至N+矽9618和N+SiGe9616區域,該區域未被柵極9612覆蓋。 Figure 96J shows the complete JLT transistor stack formed in Figure 96I, without the oxide layer for clarity, and also includes the cross-sectional cut I in Figure 96I. The gate 9612 surrounds the transistor gated channel 9636, and each group of transistor silicon is isolated from the other stacks by an oxide 9622. The source and drain connections of the transistor stack can be moved to the N+ Si 9618 and N+ SiGe 9616 regions, which are not covered by the gate 9612.

與四面柵控JLT源極、汲極和柵極之觸點可以使用傳統之後端工藝(BEOL)加工,將成型之JLT與受主晶圓之連接可以透過穿層過孔(TLV)連接到受主晶圓金屬互聯電路焊盤上。該流程能夠形成單晶矽溝道4面柵極無結電晶體,能夠與下層多金屬層半導體組件相連,無需將下層組件裸露在高溫中。 The contacts with the source, drain and gate of the four-sided gate-controlled JLT can be processed using traditional back-end process (BEOL), and the connection between the formed JLT and the receiver wafer can be connected to the receiver through the through-layer via (TLV). On the main wafer metal interconnection circuit pad. This process can form a single-crystal silicon channel 4-sided gate junctionless transistor, which can be connected to the underlying multi-metal layer semiconductor component without exposing the underlying component to high temperature.

P溝道4面柵控JLT可以使用上述N+矽層9602和9608作為P+摻雜材料進行建設,柵極金屬9612之逸出功能夠在柵極電壓為0時相應關閉P-溝道。 The P-channel 4-sided gate-controlled JLT can be constructed using the above-mentioned N+ silicon layers 9602 and 9608 as P+ doped materials, and the work function of the gate metal 9612 can correspondingly close the P-channel when the gate voltage is 0.

工藝流程如圖96A-J所示,關鍵步驟包含4面柵控JLT及3D堆部件之成型,本行業資深人員不難想見,可以在此基礎上改進該流程。例如,可以增加步驟和額外之材料/區域來增加對JLT之應力。或者N+SiGe層9604和9608可以包含P+SiGe或未摻雜之SiGe,以及選擇性磨蝕溶液配方。另外,可以在3D堆上添加多於2層之晶片或電路。同時,也可以使用多種方法來建設矽納米線電晶體。上述內容在《高性能和高一致性全柵控矽納米線MOSFET及按比例縮小》中之1-4頁和7-9頁有所說明,該書為“電子元組件會議(IEDM)”2009年,IEEE,由Bangsaruntip.S,GM;Majundar.A、等與2009年12月編寫。(書原名:High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling)(“Bangsaruntip”)和上述高性能_5nm半徑雙矽納米線MOSFET(TSNWFET):在Si晶圓堆上之製造、特徵及依 賴性,由D.Suk、S.-Y.Lee,S.-M.Kim,(“Suk”)等編寫之Proc.IEDM Tech中,717-720頁,2005年出版。上述公開之內容均在本檔中引用,作為參考。上述公開中之技術可以用來製造四面柵控JLT。 The process flow is shown in Figure 96A-J. The key steps include the molding of 4-sided gate-controlled JLT and 3D stack components. It is not difficult for senior personnel in this industry to imagine that the process can be improved on this basis. For example, steps and additional material/areas can be added to increase the stress on the JLT. Alternatively N+SiGe layers 9604 and 9608 may comprise P+SiGe or undoped SiGe, and a selective abrasive solution formulation. Additionally, more than 2 layers of chips or circuits can be added on the 3D stack. At the same time, silicon nanowire transistors can also be constructed using a variety of methods. The above content is explained on pages 1-4 and pages 7-9 of "High Performance and High Consistency Fully Gate-Controlled Silicon Nanowire MOSFET and Scaling Down", the book is "Electronic Components Conference (IEDM)" 2009 2009, IEEE, by Bangsaruntip.S, GM; Majundar.A, et al., December 2009. (Book original title: High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling) (“Bangsaruntip”) and the above-mentioned high-performance_5nm radius double silicon nanowire MOSFET (TSNWFET): on Si wafer stack manufacture, characteristics and Lai Xing, Proc.IEDM Tech by D.Suk, S.-Y.Lee, S.-M.Kim, (“Suk”) et al., pp. 717-720, published in 2005. The contents of the above disclosures are quoted in this document as a reference. The techniques in the above publications can be used to fabricate four-sided gated JLTs.

另外,如圖57A-57G所示,一個N-溝道3面柵控無結電晶體(JLT)可以在相應之3D IC製造過程中建設。如圖57A和57B所示,經過預處理之矽晶圓可以進行層切。這些流程可能需要在高於400攝氏度之插接條件下進行,因為尚未完成層切至具有金屬互聯電路之基板。如圖57A所示,N-晶圓5700可以加工出一個層N+ 5704,透過摻雜和開啟實現,也可透過N+累晶生長,或透過在重度N+摻雜之多晶矽形成澱積層實現。屏障氧化物502可以在摻雜之前生長,從而能在摻雜過程中保護矽片,並能為後續之晶圓-晶圓黏結提供氧化層。圖57B為一個預處理晶圓,可用於層切,經過摻雜5707原子,例如H+後,可以在基板之N-區域5700A中準備好切出平面5708,然後經過電漿或其他表面處理,形成晶圓氧化層之氧化物表面,供氧化物進行黏結。受主晶圓或外殼晶圓808具有邏輯電晶體和金屬互聯電路,進行預處理後,可用於低溫氧化物-氧化物晶圓黏結,及表層氧化物表面處理,黏結如圖57C所示。表層施主晶圓層切之後,與下方受主晶圓808分離,表層N-基板透過CMP處理至N+層5704,形成無結型電晶體表層柵極層。受主晶圓或外殼808中之金屬佈線帶5706如圖57C所示。為簡單清晰起見,圖示中之施主晶圓氧化層5702與 受主晶圓或外殼808氧化層未分別畫出,如圖57D-57G所示。 Alternatively, as shown in Figures 57A-57G, an N-channel 3-side gated junction-less transistor (JLT) can be constructed during the corresponding 3D IC fabrication process. As shown in Figures 57A and 57B, the preprocessed silicon wafer can be sliced. These processes may need to be performed at temperatures above 400°C for mating because the layers have not yet been cut to the substrate with the metal interconnect circuitry. As shown in FIG. 57A, an N- wafer 5700 can be processed with a layer N+ 5704 by doping and turning on, or by N+ cumulative growth, or by forming a deposited layer on heavily N+ doped polysilicon. Barrier oxide 502 can be grown before doping to protect the silicon wafer during doping and provide an oxide layer for subsequent wafer-to-wafer bonding. Figure 57B is a pre-processed wafer that can be used for layer cutting. After doping 5707 atoms, such as H+, it can be prepared to cut out a plane 5708 in the N- region 5700A of the substrate, and then undergo plasma or other surface treatment to form The oxide surface of the wafer oxide layer is used for bonding of oxides. The acceptor wafer or shell wafer 808 has logic transistors and metal interconnection circuits. After pretreatment, it can be used for low temperature oxide-oxide wafer bonding and surface oxide surface treatment. The bonding is shown in Figure 57C. After the surface donor wafer is diced, it is separated from the lower acceptor wafer 808, and the surface N- substrate is processed through CMP to the N+ layer 5704 to form a junction-free transistor surface gate layer. The metal wiring strips 5706 in the acceptor wafer or housing 808 are shown in Figure 57C. For simplicity and clarity, the donor wafer oxide layer 5702 and The acceptor wafer or housing 808 oxide layer is not shown respectively, as shown in Figures 57D-57G.

可以生長一薄層氧化物,用來保護較薄之電晶體矽層5704之表面,然後就可以掩模蝕刻出薄電晶體溝道組件5708,如圖57D所示,然後清理光刻膠。在薄氧化層經過稀釋之HF溶液洗去後,可以將基於低溫之柵極絕緣體澱積並加密化,用作無結型電晶體之柵極氧化層5710。另外,可以使用低溫微波離子束氧化處理對矽晶表面進行氧化,形成無結型電晶體之柵極氧化層5710,或使用原子層澱積(ALD)技術構成HKMG柵極氧化物。 A thin layer of oxide can be grown to protect the surface of the thinner transistor silicon layer 5704, then the thin transistor channel element 5708 can be mask etched, as shown in Figure 57D, and the photoresist can then be cleaned. After the thin oxide layer is washed away with dilute HF solution, a gate insulator based on low temperature can be deposited and densified to be used as the gate oxide layer 5710 of the junctionless transistor. In addition, low-temperature microwave ion beam oxidation can be used to oxidize the surface of the silicon crystal to form the gate oxide layer 5710 of the junctionless transistor, or the HKMG gate oxide can be formed using atomic layer deposition (ALD) technology.

也可以進行低溫柵極材料5712澱積,例如P+摻雜無定型矽,如圖57E所示。另外,高K金屬門結構也可以使用上述流程得到。之後,柵極材料5712經過掩模和蝕刻交叉加工到電晶體溝道組件5708之表面和側面柵極5714上,交叉通常為垂直相交,如圖57F所示。 Low temperature gate material 5712 deposition, such as P+ doped amorphous silicon, can also be performed, as shown in FIG. 57E. In addition, the high-K metal gate structure can also be obtained using the above-mentioned process. Afterwards, the gate material 5712 is cross-processed on the surface of the transistor channel component 5708 and the side gate 5714 through masking and etching, and the crossing is usually vertical, as shown in FIG. 57F .

之後,整個結構使用低溫氧化層5716覆蓋,氧化層使用化學和機械打磨平整,並掩模和蝕刻出觸點和金屬互聯電路,如圖57G所示。柵極觸點5720用於連接柵極5714。兩個電晶體溝道之電極觸點5722分別連接兩側之電晶體組件5708和柵極5714。穿層過孔5724連接電晶體金屬層和互聯電路5706處之受主晶圓或外殼晶圓808。該流程能夠形成單晶矽4面柵控無結電晶體,能夠與下層多金屬層半導體組件相連,無需將下層組件裸露在高溫中。 Afterwards, the entire structure is covered with a low temperature oxide layer 5716, the oxide layer is chemically and mechanically polished, and contacts and metal interconnection circuits are masked and etched, as shown in FIG. 57G. A gate contact 5720 is used to connect to the gate 5714 . The electrode contacts 5722 of the two transistor channels are respectively connected to the transistor element 5708 and the gate 5714 on both sides. Through-layer vias 5724 connect the transistor metal layer to the acceptor wafer or housing wafer 808 at the interconnect circuit 5706 . This process can form single-crystal silicon 4-sided gate-controlled junctionless transistors, which can be connected to the underlying multi-metal layer semiconductor components without exposing the underlying components to high temperatures.

另外,如圖58A-58G所示,一個N-溝道3面柵控薄面 向上之無結電晶體(JLT)可以在相應之3D IC製造過程中建設。薄面向上之無結型電晶體在溝道橫截面向上(水平放置)時具有最薄尺寸,橫截面與矽基板表面平行。上下文中所述之薄面向上之無結型電晶體,也可以在溝道橫截面向上(垂直放置)時具有最薄尺寸,橫截面與矽基板表面垂直。如圖58A和58B所示,經過預處理之矽晶圓可以進行層切。這些流程可能需要在高於400攝氏度之插接條件下進行,因為尚未完成層切至具有金屬互聯電路之基板。如圖58A所示,N-晶圓5800可以加工出一個層N+ 5804,透過摻雜和開啟實現,也可透過N+累晶生長,或透過在重度N+摻雜之多晶矽形成澱積層實現。屏障氧化物5802可以在摻雜之前生長,從而能在摻雜過程中保護矽片,並能為後續之晶圓-晶圓黏結提供氧化層。圖58B為一個預處理晶圓,可用於層切,經過摻雜5802原子,例如H+,可以在基板之N-區域5800中準備好切出平面5806,然後經過電漿或其他表面處理,形成晶圓氧化層之氧化物表面,供氧化物進行黏結。受主晶圓808具有邏輯電晶體和金屬互聯電路,進行預處理後,可用於低溫氧化物-氧化物晶圓黏結,及表層氧化物表面處理,黏結如圖58C所示。表層施主晶圓層切之後,與下方受主晶圓808分離,表層N-基板透過CMP處理至N+層5804,形成無結型電晶體溝道層。圖58C為CMP和電漿蝕刻中止層5805之澱積,例如氧化物表面之低溫SiN,位於N+層5804表面。受主晶圓或外殼808中之金屬佈線層5806如圖58C所示。為簡單清 晰起見,圖示中之施主晶圓氧化層5802與受主晶圓或外殼808氧化層未分別畫出,如圖58D-58G所示。 In addition, as shown in Figures 58A-58G, an N-channel 3-side gated thin-side Upward junction-less transistors (JLTs) can be built in the corresponding 3D IC fabrication process. The junctionless transistor with the thin side up has the thinnest dimension when the channel cross-section is up (horizontally placed), and the cross-section is parallel to the surface of the silicon substrate. The thin-side-up junctionless transistor described above and below may also have the thinnest dimension when the channel cross-section is facing up (vertically placed), the cross-section being perpendicular to the surface of the silicon substrate. As shown in Figures 58A and 58B, the preprocessed silicon wafer can be sliced. These processes may need to be performed at temperatures above 400°C for mating because the layers have not yet been cut to the substrate with the metal interconnect circuitry. As shown in FIG. 58A, an N- wafer 5800 can be processed with a layer N+ 5804 by doping and turning on, or by N+ cumulative growth, or by forming a deposited layer on heavily N+ doped polysilicon. Barrier oxide 5802 can be grown prior to doping to protect the silicon wafer during doping and provide an oxide layer for subsequent wafer-to-wafer bonding. FIG. 58B is a pre-processed wafer, which can be used for layer cutting. After doping 5802 atoms, such as H+, it can be prepared to cut out a plane 5806 in the N- region 5800 of the substrate, and then undergo plasma or other surface treatment to form a wafer. The oxide surface of the circular oxide layer is used for bonding of oxides. The acceptor wafer 808 has logic transistors and metal interconnection circuits. After pretreatment, it can be used for low-temperature oxide-oxide wafer bonding and surface oxide surface treatment. The bonding is shown in FIG. 58C. After the surface donor wafer is sliced, it is separated from the lower acceptor wafer 808, and the surface N- substrate is processed to the N+ layer 5804 by CMP to form a junctionless transistor channel layer. Figure 58C shows the deposition of a CMP and plasma etch stop layer 5805, such as low temperature SiN on the oxide surface, on the surface of the N+ layer 5804. The metal wiring layer 5806 in the acceptor wafer or housing 808 is shown in Figure 58C. for simplicity For the sake of clarity, the donor wafer oxide layer 5802 and the acceptor wafer or shell 808 oxide layer are not drawn separately, as shown in FIGS. 58D-58G .

電晶體溝道組件5808經過如圖58D所示之掩模和蝕刻加工之後,將光刻膠清除。如圖48E所示,基於低溫之柵極絕緣體經過澱積和密化,作為無結型電晶體之柵極氧化層5810。另外,可以使用低溫微波離子束氧化處理對矽晶表面進行氧化,形成無結型電晶體之柵極氧化層5810,或使用原子層澱積(ALD)技術構成HKMG柵極氧化物。也可以進行低溫柵極材料5812澱積,例如P+摻雜無定型矽。另外,高K金屬門結構也可以使用上述流程得到。之後,柵極材料5812經過掩模和蝕刻加工到電晶體溝道組件5808之表面和側面柵極5814上。如圖58G所示,整個結構使用低溫氧化層5816覆蓋,氧化層使用化學和機械打磨平整,並掩模和蝕刻出觸點和金屬互聯電路。柵極觸點5820連接電阻柵極5814(例如從其他組件之前後平面連接,如圖58G)。兩個電晶體溝道之電極觸點5822分別連接兩側之電晶體溝道組件5808和柵極5814。穿層過孔5824連接電晶體金屬層和互聯電路5806處之受主晶圓或外殼晶圓808。該流程能夠形成單晶矽3面薄面朝上之柵控無結電晶體,能夠與下層多金屬層半導體組件相連,無需將下層組件裸露在高溫中。僅具有基礎知識之人員將會很容易理解圖57A-圖57G,以及圖58A-58G中之舉例說明(並未放大)。人們也很容易進一步想到,由此可以產生多種變形,例如,結合體57A-57G之上述工藝可以用來製造一種 無結型電晶體,該電晶體溝道之高度大於寬度,或者結合58A-58G所述之工藝可以用來製造一種寬度大於高度之無結型電晶體。技術嫺熟人員在讀完本說明之後,將會意識到本項發明範圍將會囊括非常多之修改變形。因此,本項發明並非僅限於附件中之專利權聲明。 After the transistor channel element 5808 has been masked and etched as shown in Figure 58D, the photoresist is removed. As shown in FIG. 48E, a low temperature based gate insulator is deposited and densified as the gate oxide layer 5810 of the junctionless transistor. In addition, low-temperature microwave ion beam oxidation can be used to oxidize the surface of the silicon crystal to form the gate oxide layer 5810 of the junctionless transistor, or the HKMG gate oxide can be formed using atomic layer deposition (ALD) technology. Low temperature gate material 5812 deposition, such as P+ doped amorphous silicon, may also be performed. In addition, the high-K metal gate structure can also be obtained using the above-mentioned process. Gate material 5812 is then masked and etched onto the surface of transistor channel element 5808 and side gate 5814. As shown in Figure 58G, the entire structure is covered with a low temperature oxide layer 5816, which is chemically and mechanically polished to level, and contacts and metal interconnects are masked and etched. A gate contact 5820 connects to the resistive gate 5814 (eg, front-to-back plane connection from other components, as in FIG. 58G ). The electrode contacts 5822 of the two transistor channels are respectively connected to the transistor channel element 5808 and the gate 5814 on both sides. Through-layer vias 5824 connect the transistor metal layer to the acceptor wafer or housing wafer 808 at the interconnect circuit 5806 . This process can form gate-controlled junction-free transistors with three thin sides of single-crystal silicon facing up, which can be connected to the underlying multi-metal layer semiconductor components without exposing the underlying components to high temperatures. Persons with only basic knowledge will easily understand the illustrations in Figures 57A-57G, and Figures 58A-58G (not enlarged). It is also easy for people to further imagine that multiple deformations can be produced thereby, for example, the above-mentioned process of the combination body 57A-57G can be used to manufacture a A junctionless transistor in which the channel is taller than it is wide, or the process described in conjunction with 58A-58G can be used to make a junctionless transistor wider than it is tall. After reading this description, those skilled in the art will realize that the scope of the invention encompasses many modifications and variations. Therefore, this invention is not limited to the patent statement in the appendix.

另外,如圖61A-61I所示,一個雙層N-溝道3面柵控無結電晶體(JLT)可以在相應之3D IC製造過程中建設。該結構可以提高源極和汲極電阻,透過在觸點表面進行比溝道更高濃度之摻雜實現。並且,該結構可以用來建設一個2層溝道,距離柵極較近之溝道摻雜濃度更高。如圖61A和61B所示,經過預處理之矽晶圓可以進行層切。這些預處理流程可能需要在高於400攝氏度之插接條件下進行,因為尚未完成層切至具有金屬互聯電路之基板。如圖61A所示,N-晶圓6100可以加工出雙層N+,表層6104之摻雜濃度低於底層N+層6103,透過摻雜和開啟實現,也可透過N+累晶生長,或組合方法實現。也可以使用一次或多次就地摻雜無定型矽之澱積來建設垂直摻雜層或梯度。屏障氧化物6102可以在摻雜之前生長,從而能在摻雜過程中保護矽片,並能為後續之晶圓-晶圓黏結提供氧化層。圖61B為一個預處理晶圓,可用於層切,經過摻雜6107原子,例如H+後,可以在基板之N-區域6100A中準備好“切出平面”6109,然後經過電漿或其他表面處理,形成晶圓氧化層之氧化物表面,供氧化物進行黏結。 Alternatively, as shown in Figures 61A-61I, a double-layer N-channel 3-side gated junction-less transistor (JLT) can be constructed in the corresponding 3D IC fabrication process. This structure increases the source and drain resistance by doping the contact surface at a higher concentration than the channel. Moreover, this structure can be used to build a 2-layer channel, and the channel closer to the gate has a higher doping concentration. As shown in Figures 61A and 61B, the preprocessed silicon wafer can be sliced. These pre-processing processes may need to be carried out at higher than 400 degrees Celsius for insertion, because the layer cutting has not yet been completed to the substrate with metal interconnection circuits. As shown in Figure 61A, N-wafer 6100 can be processed with double-layer N+. The doping concentration of the surface layer 6104 is lower than that of the bottom N+ layer 6103. This can be achieved through doping and opening, or through N+ cumulative growth, or a combination of methods. . Vertically doped layers or gradients can also be built using one or more depositions of in-situ doped amorphous silicon. Barrier oxide 6102 can be grown prior to doping to protect the wafer during doping and provide an oxide layer for subsequent wafer-to-wafer bonding. Figure 61B is a pre-processed wafer, which can be used for layer cutting. After doping 6107 atoms, such as H+, a "cut-out plane" 6109 can be prepared in the N- region 6100A of the substrate, and then undergo plasma or other surface treatment , forming the oxide surface of the wafer oxide layer for bonding of oxides.

受主晶圓或外殼晶圓808具有邏輯電晶體和金屬互聯 電路,進行預處理後,可用於低溫氧化物-氧化物晶圓黏結,及表層氧化物表面處理,黏結如圖61C所示。表層施主晶圓層切之後,與下方受主晶圓808分離,表層N-基板透過CMP處理至N+層6103,形成更高摻雜濃度之N+層6103。可以在6103之表面使用低溫矽氮化物6105澱積出一個蝕刻硬膜,包含一薄層氧化物應力緩衝層。受主晶圓或外殼808中之金屬互聯電路焊點或帶5706如圖61C所示。為簡單清晰起見,圖示中之施主晶圓氧化層6102與受主晶圓或外殼808氧化層未分別畫出,如圖61D-61I所示。 The acceptor wafer or housing wafer 808 has logic transistors and metal interconnects The circuit, after pretreatment, can be used for low-temperature oxide-oxide wafer bonding and surface oxide surface treatment. The bonding is shown in Figure 61C. After the surface donor wafer is sliced, it is separated from the lower acceptor wafer 808, and the surface N- substrate is processed to the N+ layer 6103 by CMP to form an N+ layer 6103 with a higher doping concentration. An etched hard film can be deposited on the surface of 6103 using low temperature silicon nitride 6105, including a thin oxide stress buffer layer. Metal interconnect circuit pads or straps 5706 in the acceptor wafer or housing 808 are shown in Figure 61C. For the sake of simplicity and clarity, the donor wafer oxide layer 6102 and the acceptor wafer or shell 808 oxide layer are not drawn separately, as shown in FIGS. 61D-61I .

源極和汲極之連接區域可以進行掩模,將矽氮化物6105蝕刻掉,然後去除光刻膠。可以進行部分或全部矽電漿蝕刻,或者低溫氧化後使用HF酸蝕刻氧化物,直至薄層6103。如圖61D所示,雙層溝道,前文結合52A和52B進行了說明和模擬,經過上述蝕刻工藝形成之薄層6103幾乎被完全去除,生下之部分6103在6104之表面,然後就是6105之下方保留了完整之6103層。可以將表面溝道之6103層完全去除。這一蝕刻過程將用來調整剩餘施主晶圓層之晶圓-晶圓CMP變形,例如6100和6103,在層切除厚度變化更小之溝道之後進行。 The connection area of the source and the drain can be masked, the silicon nitride 6105 is etched away, and then the photoresist is removed. Partial or full silicon plasma etching can be performed, or the oxide can be etched with HF acid after low temperature oxidation, down to the thin layer 6103. As shown in Figure 61D, the double-layer channel was described and simulated in conjunction with 52A and 52B above. The thin layer 6103 formed by the above etching process is almost completely removed, and the resulting part 6103 is on the surface of 6104, and then on the surface of 6105. The complete layer 6103 is preserved below. The 6103 layer of the surface trench can be completely removed. This etch process will be used to adjust the wafer-to-wafer CMP deformation of the remaining donor wafer layers, eg 6100 and 6103, after layer removal of trenches with smaller thickness variations.

圖61E中,光刻膠6150定義了無結型電晶體之源極6151(一個完整厚度之6103區域),汲極6152(另一個完整厚度之6104)區域,溝道5153(部分厚度之6130和完整厚度之6104)。 In FIG. 61E, photoresist 6150 defines the source 6151 (6103 region of one full thickness), drain 6152 (6104 of another full thickness) region of the junctionless transistor, channel 5153 (6130 and 6130 of partial thickness) 6104 of the full thickness).

層6104上外露之矽晶,如圖61F所示,可以用電漿蝕 刻,並將光刻膠6159清除。該過程將形成組件間之隔離,並定義無結型電晶體溝道6108之溝道寬度。 The exposed silicon crystals on layer 6104, as shown in Figure 61F, can be etched by plasma engraved, and remove the photoresist 6159. This process will form the isolation between the devices and define the channel width of the junctionless transistor channel 6108.

如圖61G所示,基於低溫之柵極絕緣體經過澱積和密化,作為無結型電晶體之柵極氧化層6110。另外,可以使用低溫微波離子束氧化處理對矽晶表面進行氧化,形成無結型電晶體之柵極氧化層6110,或使用原子層澱積(ALD)技術構成HKMG柵極氧化物。也可以進行低溫柵極材料6112澱積,例如摻雜無定型矽,如圖61G所示。另外,高K金屬門結構也可以使用上述流程得到。 As shown in FIG. 61G, a low temperature based gate insulator is deposited and densified as the gate oxide layer 6110 of the junctionless transistor. In addition, low-temperature microwave ion beam oxidation can be used to oxidize the surface of the silicon crystal to form the gate oxide layer 6110 of the junction-free transistor, or the HKMG gate oxide can be formed using atomic layer deposition (ALD) technology. Low temperature gate material 6112 deposition, such as doped amorphous silicon, can also be performed, as shown in FIG. 61G. In addition, the high-K metal gate structure can also be obtained using the above-mentioned process.

之後,柵極材料6112經過掩模和蝕刻交叉加工到電晶體溝道組件6108之表面和側面柵極6114上,交叉通常為垂直相交,如圖61H所示。完成後,可用低溫氧化物6116覆蓋整個結構,低溫氧化物可以透過CMP加工平整。 Afterwards, the gate material 6112 is cross-processed on the surface of the transistor channel component 6108 and the side gate 6114 through masking and etching, and the crossing is usually vertical, as shown in FIG. 61H . After completion, the entire structure can be covered with low-temperature oxide 6116, which can be flattened by CMP.

之後,按如圖61I所示,進行觸點和金屬互聯電路之掩模和蝕刻。柵極觸點6120用於連接柵極6114。兩個電晶體之源極/汲極之電極觸點6122分別連接兩側之重度摻雜層6103,然後再與電晶體溝道組件6108和柵極6114相連。穿層過孔6124連接無結型電晶體金屬層和互聯電路6106處之受主晶圓或外殼晶圓808。過孔6124可以分別掩模和蝕刻,為其他觸點6122和6120提供加工餘量。該流程能夠形成單晶矽雙層3面柵控無結電晶體,能夠與下層之多個金屬層半導體組件相連,無需將下層組件裸露在高溫中。 Thereafter, masking and etching of contacts and metal interconnection circuits are performed as shown in FIG. 61I. A gate contact 6120 is used to connect to the gate 6114 . The source/drain electrode contacts 6122 of the two transistors are respectively connected to the heavily doped layers 6103 on both sides, and then connected to the transistor channel element 6108 and the gate 6114 . Through layer vias 6124 connect the junctionless transistor metal layer and the acceptor wafer or housing wafer 808 at the interconnect circuit 6106 . The vias 6124 can be masked and etched separately to provide machining allowances for the other contacts 6122 and 6120 . This process can form single-crystal silicon double-layer 3-side gate-controlled junctionless transistors, which can be connected to multiple metal layer semiconductor components in the lower layer without exposing the lower layer components to high temperature.

另外,如圖65A-C所示,一個1面柵控無結電晶體(JLT)可以在相應之3D IC製造過程中建設。一薄層重度 摻雜之矽晶層6503,可以透過在受主晶圓或外殼晶圓808之表面層切得到,使用前述之層切技術,使得施主晶圓之氧化層6501可以用來與受主晶圓或外殼晶圓808進行氧化層黏合。切出之摻雜層6503可以使用N+摻雜,作為N-構造無結型電晶體,或P+摻雜,用作P-構造無結新電晶體。如圖65B所示,氧化層隔離6506可以透過在N+層6503上掩模和蝕刻得到,後續之低溫氧化物澱積則可進行化學機械打磨,直至溝道矽晶6503之厚度。溝道厚度6504可以在這一步進行調整。低溫柵極絕緣層6504和柵極金屬層6505可以透過簽署之澱積或生長得到,然後進行光刻印刷和蝕刻。如圖65C所示,隨後可以澱積得到低溫氧化層6508,該層也可以提供溝道所需之機械應力,以提高載流子之活性。隨後可以加工觸點開口6510,用作無結電晶體之能夠電極。普通技術人員可以預見,使用上述方法僅為參考,基於本項發明之原則可以推出其他案例和應用範圍,發明之範圍不受附錄之權利聲明限制。 Alternatively, as shown in Figures 65A-C, a 1-side gated junction-less transistor (JLT) can be built in the corresponding 3D IC fabrication process. a thin layer of heavy The doped silicon layer 6503 can be obtained by slicing the surface of the acceptor wafer or the shell wafer 808. Using the aforementioned layer slicing technique, the oxide layer 6501 of the donor wafer can be used for bonding with the acceptor wafer or the outer shell wafer 808. The housing wafer 808 is oxide bonded. The doped layer 6503 cut out can be doped with N+, used as an N-structure junctionless transistor, or P+ doped, used as a P-structure junctionless transistor. As shown in FIG. 65B , the oxide layer isolation 6506 can be obtained by masking and etching on the N+ layer 6503 , and the subsequent low-temperature oxide deposition can be chemical-mechanical polished to the thickness of the channel silicon 6503 . Channel thickness 6504 can be adjusted at this step. The low temperature gate insulating layer 6504 and the gate metal layer 6505 can be deposited or grown by signing, followed by photolithographic printing and etching. As shown in FIG. 65C, a low temperature oxide layer 6508 can be deposited subsequently, which can also provide the mechanical stress required by the channel to increase the activity of carriers. Contact openings 6510 can then be machined for use as enabling electrodes for junctionless transistors. Those of ordinary skill can foresee that the use of the above methods is for reference only, and other cases and application scopes can be deduced based on the principles of this invention, and the scope of the invention is not limited by the rights statement in the appendix.

由於之前,已經將表層電晶體與下層與製造受主晶圓或外殼晶圓808對齊,此時可以進行垂直組件族之加工。垂直組件可以透過在電晶體之單晶矽層上摻雜和退火加工,使用“智慧切割”層切工藝,其中溫度上限不得超過下層預製造結構之限值。例如,垂直型MOSFET電晶體,浮柵快閃記憶體電晶體,附體DRAM,晶閘管、雙極和Schottky柵控JFET電晶體,以及記憶體組件等。無結型電晶體也可以使用類似方法建設。垂直電晶體或電阻之柵極 可以透過記憶體或邏輯組件進行控制,如MOSFET、DRAM、SRAM、浮動山村、抗熔存儲、浮體組件等,上述組件位於垂直嵌件之上下層或同一層。例如,垂直全柵控N-MOSFET電晶體,就可以按如下方法建設。 Since the surface transistors have been previously aligned with the underlying fabrication acceptor or housing wafer 808, processing of the vertical family of devices can now proceed. Vertical components can be processed by doping and annealing the monocrystalline silicon layer of the transistor, using the "smart dicing" layer cutting process, in which the upper temperature limit must not exceed the limit of the underlying prefabricated structure. For example, vertical MOSFET transistors, floating gate flash memory transistors, attached DRAMs, thyristors, bipolar and Schottky gate JFET transistors, and memory components. Junctionless transistors can also be constructed using a similar approach. Gate of vertical transistor or resistor It can be controlled through memory or logic components, such as MOSFET, DRAM, SRAM, floating village, antifuse memory, floating body components, etc., and the above components are located on the upper and lower layers or on the same layer of the vertical insert. For example, a vertical fully gate-controlled N-MOSFET transistor can be constructed as follows.

施主晶圓經過如圖39所示之通用層層切工藝作為預處理。得到一個P-晶圓3902可以加工出一個“埋入”層N+3904,透過摻雜和開啟實現,也可透過淺層N+摻雜和擴散實現。該工藝之後,是澱積一個P-累晶生長層3906,並最終在表面加工出另一個N+層3908。該N+層2510可以再次使用摻雜和開啟,或者N+累晶生長進行加工。 The donor wafer is pre-processed through the general layer dicing process shown in FIG. 39 . Obtaining a P-wafer 3902 can process a "buried" layer N+ 3904 by doping and turning on, or by shallow N+ doping and diffusion. After this process, a P-accumulated crystal growth layer 3906 is deposited, and finally another N+ layer 3908 is processed on the surface. The N+ layer 2510 can again be processed using doping and turning on, or N+ cumulative growth.

圖39B為一個可進行導電黏結層切之預處理晶圓,經過在N+層3908表面澱積出一個導電阻隔層3910,如TiN或TaN,然後摻雜原子,例如H+,之後,可以在N+區域3904之下部準備好智慧切割之切出平面3912。 Figure 39B is a pre-processed wafer that can be cut into a conductive adhesive layer. After depositing a conductive barrier layer 3910 on the surface of the N+ layer 3908, such as TiN or TaN, and then doping atoms, such as H+, after that, it can be formed in the N+ region The lower part of 3904 is ready for cutting out plane 3912 of wisdom cutting.

如圖39C所示,受主晶圓可以使用氧化層預清理加工並澱積出一個導電阻隔層3916和Al-Ge層3914。Al-Ge共晶層3914可以與導電阻隔層3910一起構成Al-Ge共晶黏結,在退火加壓之晶圓黏結工藝中實現,屬於層切流程之一部分,之後,將預處理單晶矽之N+和P-層進行層切。從而,能夠在外殼808表面金屬層3920上得到一個導電通路,連接切出之施主晶圓之底部N+層3908。另外,Al-Ge共晶層3914可以使用銅加工,從而獲得銅-銅或銅-阻隔層退火加壓黏結層。類似的,可以透過將外殼晶圓金屬線3920(由銅和阻隔金屬)與銅層3910直接退火加壓黏結獲得連接施 主晶圓之導電通路,其中大部分黏結表面為施主晶圓之銅與外殼晶圓之氧化層,其餘之表面為施主晶圓之銅與外殼晶圓808之銅和阻礙金屬之黏結層。 As shown in Figure 39C, the acceptor wafer may be processed with an oxide pre-clean and deposited with a conductive barrier layer 3916 and Al-Ge layer 3914. The Al-Ge eutectic layer 3914 can form an Al-Ge eutectic bond together with the conductive barrier layer 3910, which is realized in the wafer bonding process of annealing and pressure, which is part of the layer dicing process. After that, the single crystal silicon is pretreated. The N+ and P- layers are sliced. Thus, a conductive path can be obtained on the surface metal layer 3920 of the housing 808 to connect to the bottom N+ layer 3908 of the diced donor wafer. Alternatively, the Al-Ge eutectic layer 3914 can be processed using copper to obtain a copper-copper or copper-barrier annealed pressure bond. Similarly, connections can be achieved by direct annealing and pressure bonding the housing wafer metal lines 3920 (made of copper and barrier metal) to the copper layer 3910. The conductive paths of the master wafer, most of the bonding surfaces are the copper of the donor wafer and the oxide layer of the shell wafer, and the rest of the surface is the bonding layer of the copper of the donor wafer, the copper of the shell wafer 808 and the barrier metal.

圖40A-40I為垂直全柵控n-MOSFET表層電晶體之成型示意圖。圖40A為第一步。在上述導電通路層切完成之後,為一個CMP和電漿蝕刻中止層4002之澱積,如低溫SiN,透過在N+層3904表面澱積實現。簡化起見,導電阻隔之覆蓋Al-Ge共晶層3910、3914和3916由導電層4004表示,如圖40A所示。 40A-40I are schematic diagrams of forming the surface layer transistors of the vertical fully gate-controlled n-MOSFET. Figure 40A is the first step. After the above-mentioned conductive path layer cutting is completed, a CMP and plasma etching stop layer 4002 is deposited, such as low-temperature SiN, by depositing on the surface of the N+ layer 3904 . For simplicity, the conductively isolated overlying Al-Ge eutectic layers 3910, 3914, and 3916 are represented by conductive layer 4004, as shown in Figure 40A.

圖40B-H為垂直投影(如,水平和垂直介面之俯視圖),表示部分流程和垂直關係。俯視時,電晶體為正方形,但可以構造成長方形,以獲得不同之寬度和柵極控制效果。另外,俯視時,正方形之電晶體可以有意構造成圓形,形成一個垂直之圓柱體,或者可以在後續之加工過程中得到該形狀,最後成為垂直之塔狀。見圖40B,垂直電晶體塔4006經過掩膜畫線,和電漿/反應離子蝕刻(RIE)蝕刻至化學機械打磨(CMP)中止層4004、N+層3904和3908、以及P-層3906、導電金屬黏結層4004、一直到外殼晶圓808之氧化層、隨後去除光刻膠,如圖40B所示。這一定義和蝕刻則可以建設N-P-N堆,使得底部N+層3908與外殼晶圓金屬層3920透過導電層4004相連。 Figures 40B-H are vertical projections (eg, top views of horizontal and vertical interfaces) showing partial flow and vertical relationships. Transistors are square when viewed from above, but can be configured as rectangles for different widths and gate control effects. In addition, when viewed from above, the square transistor can be intentionally rounded to form a vertical cylinder, or the shape can be obtained in the subsequent processing process, and finally become a vertical tower. See FIG. 40B, the vertical transistor tower 4006 is mask drawn, and plasma/reactive ion etching (RIE) etched to the chemical mechanical polishing (CMP) stop layer 4004, N+ layers 3904 and 3908, and P- layer 3906, conductive The metal bonding layer 4004, up to the oxide layer of the housing wafer 808, and then the photoresist is removed, as shown in FIG. 40B. This definition and etching can then build up the N-P-N stack such that the bottom N+ layer 3908 is connected to the shell wafer metal layer 3920 through the conductive layer 4004 .

塔與塔之間之面積部分由氧化物4010透過一個旋塗式玻璃發(SPG)進行旋轉、凝固,並回蝕,如圖40C所示。另外,可以澱積出一個低溫CVD空隙填充氧化層,然 後使用CMP打磨平整,然後選擇性回蝕,構成如圖40C所示之相同氧化層形狀4010。氧化層4010之高度,可以依照如下確定:底部N+塔層3908之小部分未被氧化層覆蓋。另外,這一步也可以透過一個等效之低溫氧化物CVD澱積和回蝕工序得到,構成底部N+塔層3908之隔離輪廓覆蓋。 The area between the towers is partially made of oxide 4010 through a spin-on-glass hair (SPG) that is spun, solidified, and etched back, as shown in Figure 40C. Alternatively, a low-temperature CVD void-fill oxide can be deposited and then Then use CMP to polish and smooth, and then selectively etch back to form the same oxide layer shape 4010 as shown in FIG. 40C. The height of the oxide layer 4010 can be determined as follows: a small portion of the bottom N+ tower layer 3908 is not covered by the oxide layer. In addition, this step can also be obtained through an equivalent low temperature oxide CVD deposition and etch back process to form the isolation profile coverage of the bottom N+ tower layer 3908 .

另外,側面柵極氧化物4014透過低溫微波氧化技術建設,例如TEL SPA(Tokyo Electron Limited Slot Plane Antenna)氧氣自由電漿,使用含水化合物,如稀釋過的HF,來去除,然後按圖40D所示重新生長4014。 In addition, the side gate oxide 4014 is constructed by low-temperature microwave oxidation technology, such as TEL SPA (Tokyo Electron Limited Slot Plane Antenna) oxygen free plasma, using aqueous compounds, such as diluted HF, to remove, and then as shown in Figure 40D Re-grow 4014.

之後澱積柵極,例如等效之摻雜無定型矽層4018,如圖40E所示。之後,畫出柵極掩模光刻膠4020。 A gate is then deposited, such as an equivalent doped amorphous silicon layer 4018, as shown in FIG. 40E. After that, a gate mask photoresist 4020 is drawn.

如圖40F所示,柵極層4018之蝕刻應保證,隔離輪廓柵極4022保留在區域中,未被光刻膠4020覆蓋。柵極層4018之全部厚度應在被電阻4020覆蓋處全部保留,並且柵極層4020應從塔之間完全清除。最後,將光刻膠4020去除。該方法可以將柵極之汲極之覆蓋降至最低,並最終獲得與柵極之潔淨觸點連接。 The etching of the gate layer 4018 should ensure that the isolation contour gate 4022 remains in the area not covered by the photoresist 4020 as shown in FIG. 40F. The full thickness of the gate layer 4018 should remain where it is covered by the resistor 4020, and the gate layer 4020 should be completely removed from between the towers. Finally, the photoresist 4020 is removed. This approach minimizes drain coverage of the gate and ultimately results in a clean contact connection to the gate.

如圖40G所示,塔之間之空隙被填滿,塔被氧化層4030透過低溫間隙填充澱積和CMP覆蓋。 As shown in Figure 40G, the gaps between the towers are filled and the towers are covered with an oxide layer 4030 by low temperature gap fill deposition and CMP.

在圖40H中,與塔N+層3904連接之過孔觸點4034透過掩模和蝕刻得到,然後是掩模並蝕刻與柵極多晶矽4024相連之過孔觸點4036。 In FIG. 40H , via contact 4034 to tower N+ layer 3904 is masked and etched, followed by masking and etching via contact 4036 to gate polysilicon 4024 .

金屬線4040由掩模和蝕刻得到,由隔離金屬和銅互連 電路填充,並使用正常之互聯電路方案進行CMP打磨,從而完成與塔N+3904和柵極4024之觸點過孔連接,如圖40I所示。 Metal lines 4040 are masked and etched, interconnected by isolation metal and copper The circuit is filled, and the normal interconnection circuit scheme is used for CMP polishing, so as to complete the contact via connection with the tower N+ 3904 and the gate 4024, as shown in FIG. 40I.

該流程能夠形成單晶矽表層MOS電晶體,能夠與下層多金屬層半導體組件相連,無需將下層組件和互聯電路金屬裸露在高溫中。這些電晶體可以用作層807之抗熔存儲編程電晶體,與晶圓金屬層或808層相連構成單片3D IC,作為晶圓或層808上之傳輸電晶體,或該用戶FPGA,或者用於其他3D半導體組件。 This process can form a MOS transistor on the surface of single crystal silicon, which can be connected to the underlying multi-metal layer semiconductor components, without exposing the underlying components and interconnection circuit metal to high temperature. These transistors can be used as the antifuse programming transistors of layer 807, connected with the wafer metal layer or layer 808 to form a monolithic 3D IC, as the transfer transistors on the wafer or layer 808, or the user FPGA, or with for other 3D semiconductor components.

另外,垂直全柵控無結型電晶體也可按圖54和55進行建設。圖54A為使用預處理晶進行層切除之示意圖;一個N-晶圓5402可以加工出一個N+層5404,透過離子注入和開啟實現,也可透過N+累晶生長實現。圖54B為一個可進行導電黏結層切之預處理晶圓,經過在N+層5410表面澱積出一個導電阻隔層5410,如TiN或TaN,然後摻雜原子,例如H+,之後,可以在N+區域5404之下部準備好智慧切割之切出平面5412。 In addition, the vertical fully gate-controlled junctionless transistor can also be constructed according to Figures 54 and 55. FIG. 54A is a schematic diagram of layer ablation using pre-processed crystals; an N- wafer 5402 can be processed into an N+ layer 5404 through ion implantation and turn-on, and can also be realized through N+ accumulated crystal growth. Figure 54B is a pre-processed wafer that can be cut into a conductive adhesive layer. After depositing a conductive barrier layer 5410 on the surface of the N+ layer 5410, such as TiN or TaN, and then doping atoms, such as H+, after that, it can be in the N+ region The lower part of 5404 is ready for cutting out plane 5412 of wisdom cutting.

受主晶圓或外殼晶圓808也可以透過氧化物預清理和澱積導電隔離層5416和AL和Ge層進行加工,形成Ge-Al共晶黏結層5414,這一過程在退火加壓晶圓黏結中完成,屬於層切流程之一部分,然後在受主晶圓或外殼晶圓808之表面,將圖54B所示之預處理單晶矽層和一個N+層5404進行層切,如圖54C所示。N+層5405可以透過打磨來去除層切工序留下之刮痕。從而,能夠在受主晶圓或外殼808表 面金屬層5420上得到一個導電通路,連接切出之施主晶圓之N+層5404。另外,Al-Ge共晶層5414可以使用銅加工,從而獲得銅-銅或銅-阻隔層退火加壓黏結層。類似的,可以透過將施主晶圓或外殼晶圓金屬線5420(由銅和阻隔金屬)與銅層5410直接退火加壓黏結獲得連接施主晶圓之導電通路,其中大部分黏結表面為施主晶圓之銅與外殼晶圓之氧化層,其餘之表面為施主晶圓之銅與施主晶圓或外殼晶圓808之銅和阻礙金屬之黏結層。 The acceptor or housing wafer 808 can also be processed by oxide pre-cleaning and depositing a conductive spacer layer 5416 and layers of Al and Ge to form a Ge-Al eutectic bonding layer 5414. It is completed in bonding, which is a part of the layer cutting process, and then on the surface of the acceptor wafer or the shell wafer 808, the preprocessed single crystal silicon layer and an N+ layer 5404 shown in Figure 54B are layer cut, as shown in Figure 54C Show. The N+ layer 5405 can be polished to remove scratches left by the layer cutting process. Thus, it is possible to express A conductive path is obtained on the surface metal layer 5420 to connect to the N+ layer 5404 of the diced donor wafer. Alternatively, the Al-Ge eutectic layer 5414 can be processed using copper to obtain a copper-copper or copper-barrier annealed pressure bond. Similarly, conductive pathways to the donor wafer can be obtained by direct annealing and pressure bonding of the donor wafer or housing wafer metal lines 5420 (made of copper and barrier metal) to the copper layer 5410, where the majority of the bonded surface is the donor wafer The oxide layer of the copper and the shell wafer, and the remaining surface is the bonding layer between the copper of the donor wafer and the copper of the donor wafer or the shell wafer 808 and the barrier metal.

圖55A-55I為,圖54C中之預處理受主晶圓或外殼808上方,垂直全柵控無結型電晶體之成型示意圖。圖55A為CMP和電漿蝕刻中止層5502之澱積,例如低溫SiN,位於N+層5504表面。簡化起見,圖54C中阻隔之覆蓋Al-Ge共晶層5410、5414和5416由導電層5500表示。 55A-55I are schematic diagrams of the formation of vertical fully-gated junction-free transistors above the preprocessed acceptor wafer or housing 808 in FIG. 54C. 55A shows the deposition of a CMP and plasma etch stop layer 5502, such as low temperature SiN, on the surface of the N+ layer 5504. For simplicity, the blocked overlying Al-Ge eutectic layers 5410, 5414, and 5416 are represented by conductive layer 5500 in FIG. 54C.

類似的,圖55B-H為垂直投影,表示部分流程和垂直關係。俯視時,無結型電晶體為正方形,但可以構造成長方形,以獲得不同之溝道厚度、寬度和柵極控制效果。另外,俯視時,正方形之電晶體可以有意構造成圓形,形成一個垂直之圓柱體,或者可以在後續之加工過程中得到該形狀,最後成為垂直之塔狀。垂直電晶體塔5506經過掩模畫線,和電漿/反應離子蝕刻(RIE)蝕刻至化學機械打磨(CMP)中止層5502、N+層5504和3908、導電金屬黏結層5500、一直到外殼晶圓808之氧化層、隨後去除光刻膠,如圖55B所示。這一定義和蝕刻則可以建設N+電晶體溝道堆,堆之相互之間隔離,但是N+層5404之底部與外 殼晶圓金屬層5420導通。 Similarly, Figures 55B-H are vertical projections showing partial flow and vertical relationships. When viewed from above, the junctionless transistor is square, but it can be configured as a rectangle to obtain different channel thicknesses, widths and gate control effects. In addition, when viewed from above, the square transistor can be intentionally rounded to form a vertical cylinder, or the shape can be obtained in the subsequent processing process, and finally become a vertical tower. Vertical transistor towers 5506 are mask drawn, and plasma/reactive ion etch (RIE) etched to chemical mechanical polish (CMP) stop layer 5502, N+ layers 5504 and 3908, conductive metal bonding layer 5500, all the way to the housing wafer 808 of the oxide layer, followed by removal of the photoresist, as shown in Figure 55B. This definition and etching can build N+ transistor channel stacks, the stacks are isolated from each other, but the bottom of the N+ layer 5404 is separated from the outer Shell wafer metal layer 5420 conducts.

塔與塔之間之面積部分由氧化物5510透過一個旋塗式玻璃發(SPG)進行旋轉、低溫凝固,並回蝕,如圖55C所示。另外,可以澱積出一個低溫CVD空隙填充氧化層,然後CMP打磨平整,接下來選擇性回蝕,構成如圖55C所示之相同形狀5510。另外,這一步也可以透過一個等效之低溫氧化物CVD澱積和回蝕工序得到,構成N+電阻塔層5504之隔離輪廓覆蓋。 The area between the towers is partially made of oxide 5510 through a spin-on glass (SPG) that is spun, cryogenically solidified, and etched back, as shown in Figure 55C. Alternatively, a low temperature CVD void filling oxide layer can be deposited, then CMP polished, followed by selective etch back to form the same shape 5510 as shown in Figure 55C. In addition, this step can also be obtained through an equivalent low-temperature oxide CVD deposition and etch-back process to form the isolation contour coverage of the N+ resistor tower layer 5504 .

另外,側面柵極氧化物5514透過低溫微波氧化技術建設,例如TEL SPA(Tokyo Electron Limited Slot Plane Antenna)氧氣自由電漿,使用含水化合物,如稀釋過的HF,去除,然後按圖55D所示重新生長5514。 In addition, the side gate oxide 5514 is constructed by low-temperature microwave oxidation technology, such as TEL SPA (Tokyo Electron Limited Slot Plane Antenna) oxygen free plasma, using hydrated compounds, such as diluted HF, to remove, and then reapply as shown in Figure 55D Grow 5514.

隨後澱積得到柵極,如P+摻雜無定型矽晶層5518,然後是化學機械打磨,打磨平整,然後進行選擇性回蝕,得到圖55E所示之形狀5518,然後進行柵極掩模光刻膠5520之畫線,如圖55E所示。 Then deposit the gate, such as the P+ doped amorphous silicon layer 5518, then chemical mechanical polishing, polishing, and then selectively etch back to obtain the shape 5518 shown in FIG. 55E, and then perform gate masking. The line drawing of the resist 5520 is shown in FIG. 55E.

柵極層5518透過蝕刻,使得柵極層從塔之間完全清楚,然後按圖55F所示,清除光刻膠。 The gate layer 5518 is etched through such that the gate layer is completely clear from between the towers, and then the photoresist is removed as shown in FIG. 55F.

如圖55G所示,塔之間之空隙被填滿,塔被氧化層5530透過低溫間隙填充澱積,然後進行CMP加工,和另一次之氧化物澱積,如圖55G所示。 As shown in Figure 55G, the gaps between the towers are filled, the towers are covered with oxide layer 5530 deposited by low temperature gap fill, followed by CMP processing, and another oxide deposition, as shown in Figure 55G.

在圖55H中,與電晶體塔N+層5504連接之觸點5534透過掩模和蝕刻得到,然後是掩模並蝕刻與柵極多晶矽5518相連之觸點5518。金屬線5540由掩模和蝕刻得到,由隔離 金屬和銅互連電路填充,並使用正常之雙鑲嵌互聯電路方案進行CMP打磨,從而完成與電晶體溝道塔N+5504和柵極5518之觸點過孔連接,如圖55I所示。 In FIG. 55H, contacts 5534 to the N+ layer 5504 of the transistor tower are masked and etched, followed by masking and etching of contacts 5518 to the gate polysilicon 5518. Metal lines 5540 are obtained by masking and etching, isolated by Metal and copper interconnection circuits are filled and polished by CMP using the normal dual damascene interconnection circuit scheme to complete contact via connections with transistor channel tower N+ 5504 and gate 5518, as shown in Figure 55I.

該流程能夠形成單晶矽表層垂直無結型電晶體,能夠與下層多金屬層半導體組件相連,無需將下層組件和互聯電路金屬裸露在高溫中。這些無結型電晶體可以用作受主晶圓或外殼晶圓808上之可編程電晶體,或者邏輯組件之傳輸電晶體,或用於FPG,或用於其他3D半導體組件。 This process can form a vertical junction-free transistor on the surface of monocrystalline silicon, which can be connected to the underlying multi-metal layer semiconductor components without exposing the underlying components and interconnection circuit metals to high temperatures. These junctionless transistors can be used as programmable transistors on the acceptor wafer or housing wafer 808, or transfer transistors for logic devices, or for FPGs, or for other 3D semiconductor devices.

凹槽陣列電晶體(RCAT)可以用另外一個電晶體族,以便能夠利用層切和蝕刻定義來建設低溫整體3D IC。圖66中給出了兩種類型之RCAT組件結構。由J.Kim等在2003-2005年之VLSI技術論壇進行了說明。注意到Kim等說明之這些背景技術,屬於單層電晶體,並未使用任何層切技術。他們工作中也使用高溫工藝,例如源極-汲極開啟退火,所使用之溫度達到400攝氏度以上。不同之處是,本項發明之案例中使用了一個二維平面中之電晶體族。所有電晶體(無結型、凹槽型或耗盡型等),均在同一個二維平面上具有源極和汲極,可以認為是平面電晶體。 Recessed Array Transistor (RCAT) can be used as another family of transistors to enable the construction of low temperature monolithic 3D ICs using layer cut and etch definitions. Two types of RCAT component structures are shown in Figure 66. It was explained by J.Kim et al. in the 2003-2005 VLSI Technology Forum. Note that the background technologies described by Kim et al. belong to single-layer transistors and do not use any layer cutting technology. They also use high-temperature processes in their work, such as source-drain open annealing, at temperatures above 400 degrees Celsius. The difference is that in the case of the present invention a family of transistors in a two-dimensional plane is used. All transistors (junctionless, grooved or depleted, etc.) have sources and drains on the same two-dimensional plane, and can be considered as planar transistors.

圖67A-F所示,層堆疊方法被用於建設3D積體電路和標準RCAT。對於一個N-槽型MOSFET,可以使用一個P-矽晶圓6700作為加工起點。N+Si埋入層6702可以進行摻雜,如圖67A所示,得到一個P-層6703,位於施主晶圓表面。另外一個方法就是進行淺層N+Si摻雜,然後外緣澱積 一個P-Si層6703。為了開啟N+層6702之摻雜材料,晶圓可以進行退火,使用標準之退火程式,例如氣體退火、尖端退火或鐳射退火。 As shown in Figure 67A-F, the layer stacking method is used to build 3D ICs and standard RCAT. For an N-groove MOSFET, a P-silicon wafer 6700 can be used as the starting point for processing. The N+Si buried layer 6702 can be doped, as shown in Figure 67A, resulting in a P- layer 6703 on the surface of the donor wafer. Another method is to perform shallow N+Si doping, and then deposit the outer edge A P-Si layer 6703. To turn on the dopant material of the N+ layer 6702, the wafer can be annealed using standard annealing procedures such as gas annealing, tip annealing or laser annealing.

然後可以按圖67B所示,生長或澱積得到一個氧化物層6701。氮氣可以摻雜到晶圓6704中,然後進行智慧切割加工,如圖67B所示。 An oxide layer 6701 may then be grown or deposited as shown in FIG. 67B. Nitrogen can be doped into the wafer 6704, and then the smart dicing process is performed, as shown in FIG. 67B.

然後可以進行層切,將圖67B所示之晶圓黏接到一個預處理電路受主晶圓808上,如圖67C所示。摻雜氦層6704可以用來切割晶圓6700之剩餘部分。 Layer dicing can then be performed to bond the wafer shown in Figure 67B onto a pre-processing circuit acceptor wafer 808, as shown in Figure 67C. The helium doped layer 6704 may be used to dice the remainder of the wafer 6700.

切割之後,可以進行化學機械打磨(CMP)。可以加工出氧化層隔離區域6705,並進行蝕刻,形成如圖67D所示之凹槽6706。這一蝕刻過程可以進一步調整,以便尖角都被打磨平整,避免高點。 After dicing, chemical mechanical polishing (CMP) may be performed. An oxide layer isolation region 6705 can be processed and etched to form a groove 6706 as shown in FIG. 67D. This etching process can be further tuned so that sharp corners are smoothed and high spots are avoided.

然後可以澱積得到門絕緣層6707,透過上述原子層澱積或透過低溫氧化物成型工藝實現。然後可以澱積得到金屬門6708,填充凹槽,再進行CMP和柵極畫線,如圖67E所示。 A gate insulating layer 6707 may then be deposited, either through the aforementioned atomic layer deposition or through a low temperature oxide forming process. Metal gates 6708 can then be deposited to fill the grooves, followed by CMP and gate drawing, as shown in Figure 67E.

然後可以澱積出低溫氧化層6709,並使用CMP進行平整化。之後加工出觸點6710,連接電晶體之所有電極,如圖67F所示。該流程能夠在預處理電路808表面形成完整之低溫RCAT。然後可以使用模擬工藝加工P-槽MOSFET。P和N槽RCAT可以用來形成整塊3D CMOS電路組件庫。 A low temperature oxide layer 6709 may then be deposited and planarized using CMP. Contacts 6710 are then machined to connect all electrodes of the transistor, as shown in Figure 67F. This process can form a complete low-temperature RCAT on the surface of the pre-processing circuit 808 . The P-groove MOSFETs can then be fabricated using the analog process. P and N slot RCATs can be used to form a library of monolithic 3D CMOS circuit components.

圖68A-F所示,層堆疊方法被用於建設3D積體電路和標準RCAT。對於一個N-槽型MOSFET,可以使用一個P- 矽晶圓6800作為加工起點。N+Si埋入層6802可以進行摻雜,如圖68A所示,得到一個P-層6803,位於施主晶圓表面。另外一個方法就是進行淺層N+Si摻雜,然後外緣澱積一個P-Si層6803。開啟N+層6802之摻雜材料,晶圓可以進行退火,使用標準之退火程式,例如氣體退火、尖端退火或鐳射退火。 As shown in Figure 68A-F, the layer stacking method is used to build 3D ICs and standard RCAT. For an N-slot MOSFET, use a P- Silicon wafer 6800 is used as the starting point for processing. The N+Si buried layer 6802 can be doped, as shown in Figure 68A, resulting in a P- layer 6803 on the surface of the donor wafer. Another method is to perform shallow N+Si doping, and then deposit a P-Si layer 6803 on the outer edge. With the doped material of the N+ layer 6802 turned on, the wafer can be annealed using standard annealing procedures such as gas annealing, tip annealing or laser annealing.

然後可以按圖68B所示,生長或澱積得到一個氧化物層6801。氫氣可以摻雜到晶圓6804中,然後進行智慧切割加工,如圖68B所示。 An oxide layer 6801 may then be grown or deposited as shown in FIG. 68B. Hydrogen can be doped into the wafer 6804, and then the smart dicing process is performed, as shown in FIG. 68B.

然後可以進行層切,將圖68B所示之晶圓黏接到一個預處理電路受主晶圓808上,如圖68C所示。摻雜氦層6804可以用來切割晶圓6800之剩餘部分。切割之後,可以進行化學機械打磨(CMP)。 Layer dicing can then be performed to bond the wafer shown in Figure 68B onto a pre-processing circuit acceptor wafer 808, as shown in Figure 68C. The helium doped layer 6804 may be used to dice the remainder of the wafer 6800. After dicing, chemical mechanical polishing (CMP) may be performed.

氧化物隔離區域6805可以如圖68D所示加工得到。最終之柵極凹槽可以透過掩模和部分蝕刻得到,然後可以進行間隔澱積6806使用等效之低溫澱積,如矽氧化層或矽氮化物或上述之組合。 Oxide isolation regions 6805 may be processed as shown in Figure 68D. The final gate recess can be obtained through masking and partial etching, and then spacer deposition 6806 can be performed using an equivalent low temperature deposition, such as silicon oxide or silicon nitride or a combination of the above.

可以對間隔使用各向異性蝕刻,使得間隔材料僅在凹槽柵極開口之垂直側面得以保留。然後可以進行均勻矽晶蝕刻,形成球型凹槽6807,如圖68E所示。側邊之間隔可以使用選擇性蝕刻清除。 An anisotropic etch can be used for the spacers such that spacer material remains only on the vertical sides of the recessed gate opening. Uniform silicon etching can then be performed to form spherical grooves 6807, as shown in FIG. 68E. The spacers between the sides can be removed using a selective etch.

然後可以澱積得到門絕緣層6808,透過上述原子層澱積或透過低溫氧化物成型工藝實現。然後可以澱積得到金屬門6809,填充凹槽,再進行CMP和柵極畫線,如圖68F 所示。柵極材料也可以進行摻雜,使用無定型矽或逸出功合適之低溫導體。然後可以澱積出低溫氧化層6810,並使用CMP進行平整化。之後加工出觸點6811,連接電晶體之所有電極,如圖68F所示。 A gate insulating layer 6808 may then be deposited, either through the aforementioned atomic layer deposition or through a low temperature oxide formation process. Then metal gate 6809 can be deposited, fill the groove, and then perform CMP and gate drawing, as shown in Figure 68F shown. The gate material can also be doped, using amorphous silicon or a low temperature conductor with a suitable work function. A low temperature oxide layer 6810 may then be deposited and planarized using CMP. Contacts 6811 are then machined to connect all electrodes of the transistor, as shown in Figure 68F.

該流程能夠在預處理電路808表面形成完整之低溫S-RCAT。然後可以使用模擬工藝加工P-槽MOSFET。P和N槽S-RCAT可以用來形成整塊3D CMOS電路組件庫。另外,使用RCAT建設之SRAM電路可能具有與邏輯電路不同之槽深。RCAT和S-RCAT組件可以用來建設BiCMOS逆變器和其他混合電路,只需外殼808層具有常規雙極結型電晶體,並且可以使用層切來建設整塊RCAT組件。 This process can form a complete low-temperature S-RCAT on the surface of the preprocessing circuit 808 . The P-groove MOSFETs can then be fabricated using the analog process. P and N slot S-RCAT can be used to form a library of monolithic 3D CMOS circuit components. In addition, SRAM circuits built using RCAT may have different trench depths than logic circuits. RCAT and S-RCAT components can be used to build BiCMOS inverters and other hybrid circuits, only need to have conventional bipolar junction transistors in the 808 layers of the casing, and layer cutting can be used to build the whole RCAT component.

3D組件結構可以在單晶矽層中建設,並且利用預處理施主晶圓之優勢,透過建設晶圓大小之不同材料層,無需受到溫度之限制,然後層切預處理施主晶圓至受主晶圓,之後可選擇不同加工步驟進行處理,然後重複上述過程多次,並使用低溫(低於400攝氏度)或高溫(高於400攝氏度)進行處理,在最後之層切之後,在一個或多個互相對齊之切出層上建設記憶體件結構,例如電晶體,各層可與受主晶圓連通。 The 3D component structure can be built in a single crystal silicon layer, and by taking advantage of the pre-processed donor wafer, through the construction of different material layers of the wafer size, without being limited by temperature, and then layer-cut the pre-processed donor wafer to the acceptor wafer Round, after which different processing steps can be selected for processing, and then the above process can be repeated many times, and processed with low temperature (below 400 degrees Celsius) or high temperature (higher than 400 degrees Celsius), after the final layer cutting, in one or more Memory device structures, such as transistors, are built on the cut-out layers that are aligned with each other, and each layer can be connected to the acceptor wafer.

新型之整塊3D動態訪問儲存(DRAM)可以用上述方法建設。本項發明之部分案例即為浮體DRAM型。 A new type of monolithic 3D dynamic access memory (DRAM) can be constructed using the method described above. Some examples of this invention are the floating body DRAM type.

浮體DRAM是新一代DRAM,目前有多家公司在對DRAM進行研發,如Innovative Silicon,Synix,和Toshiba。浮體DRAM將資料保存為一個SOI MOSFET之電 荷,或一個多柵極MOSFET之電荷。浮體DRAM之細節和工作類型可以在下列美國專利和其他檔中找到:7541616, 7514748, 7499358, 7499352, 7492632, 7486563, 7477540, 7476939。整塊3D集成DRAM可以使用浮體電晶體建設。用於建設整塊3D DRAM之現有技術使用平面電晶體,結晶矽層使用選擇性epi技術或鐳射重結晶技術成型。選擇性epi技術和鐳射重結晶技術不能夠製造完美之單晶矽,並通常具有很高之熱能支出。該工藝之說明可以在書《Integrated Interconnect Technologies for 3D Nanoelectronic System》中找到,作者Bakir和Meindl。 Floating body DRAM is a new generation of DRAM, and many companies are currently developing DRAM, such as Innovative Silicon, Synix, and Toshiba. Floating-body DRAM stores data as a power supply of an SOI MOSFET charge, or the charge of a multi-gate MOSFET. Details and types of operation of floating body DRAMs can be found in the following US patents and others: 7541616, 7514748, 7499358, 7499352, 7492632, 7486563, 7477540, 7476939. A monolithic 3D integrated DRAM can be built using floating body transistors. Existing technologies for building monolithic 3D DRAMs use planar transistors, and the crystalline silicon layer is formed using selective epi or laser recrystallization. Selective epi technology and laser recrystallization technology cannot produce perfect single crystal silicon, and usually have high thermal energy expenditure. A description of this process can be found in the book "Integrated Interconnect Technologies for 3D Nanoelectronic System" by Bakir and Meindl.

如圖97所示,下文將對工作中之浮體DRAM之基本要素進行說明。為了儲存“1”位元組,可能需要浮體區域9720中存在多餘空穴9702,並改變存儲晶片電晶體之闕值電壓,電晶體包含源極9704、柵極9706、浮體9720、埋入氧化層(BOX)9718。如圖97a所示。為了儲存0位元組,可能需要浮體區域9720中存在多餘空穴9710,並改變存儲晶片電晶體之闕值電壓,電晶體包含源極9712、柵極9714、浮體9720、埋入氧化層(BOX)9716。如圖97b所示。圖97a和97b中存儲晶片電晶體闕值電壓之不同使得電晶體在汲極電流9734中處於不同之工作狀態,此時電晶體柵極電壓9736為指定值。如圖97c所示。電流之差別9730可以被讀出放大器電路辨別處理,分別作為“0”和“1”之狀態,並儲存在晶片中。 As shown in FIG. 97, the basic elements of the floating body DRAM in operation will be described below. In order to store a "1" byte, it may be necessary to have redundant holes 9702 in the floating body region 9720, and to change the threshold voltage of the storage chip transistor, which includes a source 9704, a gate 9706, a floating body 9720, a buried Oxide layer (BOX) 9718. As shown in Figure 97a. In order to store 0 bytes, it may be necessary to have redundant holes 9710 in the floating body region 9720, and to change the threshold voltage of the memory chip transistor, which includes a source 9712, a gate 9714, a floating body 9720, and a buried oxide layer (BOX) 9716. As shown in Figure 97b. The difference in the threshold voltage of the storage chip transistor in Figure 97a and 97b causes the transistor to be in different working states in the drain current 9734, and the gate voltage 9736 of the transistor is a specified value at this time. As shown in Figure 97c. The current difference 9730 can be discriminated and processed by the sense amplifier circuit as the states of "0" and "1", respectively, and stored in the chip.

如圖98A-H所示,水平佈置之整塊3D DRAM之每個存 儲層使用兩個掩模步驟,可以使用合適之3D IC製造流程建設。 As shown in Figure 98A-H, each memory of the monolithic 3D DRAM arranged horizontally The reservoir uses two masking steps and can be constructed using a suitable 3D IC fabrication flow.

如圖98A所示,一個P-基板施主晶圓9800,可以加工成包含晶圓大小之p-摻雜矽晶層9804。P-層9804可以和P-基板9800具有相同或不同之摻雜濃度。P-摻雜層9804可以透過離子注入或退火退火製造。屏障氧化層9801可以在摻雜之前生長,用來保護矽晶不被摻雜,同時為後續之氧化層晶圓黏結提供氧化層。 As shown in FIG. 98A, a p-substrate donor wafer 9800 can be processed to include a wafer-sized p-doped silicon layer 9804. The P-layer 9804 can have the same or different doping concentration as the P-substrate 9800 . P-doped layer 9804 can be fabricated by ion implantation or annealing. The barrier oxide layer 9801 can be grown before doping to protect the silicon from doping and provide an oxide layer for subsequent oxide wafer bonding.

如圖98B所示,施主晶圓9800之表面,可以透過澱積一個氧化層9802或退火氧化一個P-層9804用於氧化層晶圓黏結,或者使用摻雜屏障氧化層9801進行重新氧化。層切劃分平面9899(如虛線所示),可能在施主晶圓9800上或P-層9804(如圖),透過摻雜氦9807或其他前述方法實現。施主晶圓9800和受主晶圓9810均可以加工用於晶圓黏結,如前所述,黏結時最好使用低溫(小於400攝氏度)來減小應力。P-施主晶圓基板9804之一部分,以及P-施主晶圓基板9800之一部分,位於層切劃分平面9899之上,可以透過切割和打磨、或其他前述之方法去除,例如離子切割等。 As shown in FIG. 98B , the surface of the donor wafer 9800 can be re-oxidized by depositing an oxide layer 9802 or annealing a P- layer 9804 for oxide wafer bonding, or using a doped barrier oxide layer 9801 . Layer-slicing dividing planes 9899 (shown in dashed lines), possibly on the donor wafer 9800 or P-layer 9804 (shown), are achieved by doping helium 9807 or other methods as previously described. Both the donor wafer 9800 and the acceptor wafer 9810 can be processed for wafer bonding. As mentioned above, it is best to use low temperature (less than 400 degrees Celsius) to reduce stress during bonding. A portion of the P-donor wafer substrate 9804, as well as a portion of the P-donor wafer substrate 9800, located above the layer-cut dividing plane 9899, can be removed by dicing and grinding, or other aforementioned methods, such as ion dicing.

如圖98C所示,剩餘之P-摻雜層9804’,和氧化層9802經過層切至受主晶圓9810。受主晶圓9810可以包含週邊電路,使之能夠承受附加之快速熱退火(RTA)之溫度,並能保持工作能力和較好之性能。因此,週邊電路之構造最好不使用RTA開啟摻雜物,或使用弱RTA。而且,週邊電 路可以使用一種耐高溫金屬,例如鎢,使之能夠承受大於400攝氏度之高溫。P-摻雜層9804’之表面可以使用化學和機械打磨之方法打磨平整。而今,可以構造電晶體並與受主晶圓9810之對準標記(未畫出)對齊。 The remaining P-doped layer 9804', and oxide layer 9802 are layer diced to the acceptor wafer 9810 as shown in FIG. 98C. The acceptor wafer 9810 may contain peripheral circuits that can withstand additional rapid thermal annealing (RTA) temperatures and maintain operational capability and better performance. Therefore, it is better to construct peripheral circuits without RTA turn-on dopant, or use weak RTA. Moreover, the peripheral The road can use a high-temperature resistant metal, such as tungsten, so that it can withstand high temperatures greater than 400 degrees Celsius. The surface of the P-doped layer 9804' can be smoothed by chemical and mechanical polishing. Now, the transistors can be constructed and aligned with the alignment marks (not shown) of the acceptor wafer 9810 .

如圖98D所示,淺槽隔離(STI)氧化區域(未畫出)可以使用印刷畫線和電漿/RIE蝕刻,至至少氧化層9802之表層,去除P-單晶矽層9804’區域。間隙填充氧化物可以透過澱積和CMP打磨平整,形成STI氧化物區域,並使用P-摻雜單晶矽區域(未畫出)建設電晶體。此時可以選擇是否進行闕值調整摻雜。柵極堆9824可以使用柵極絕緣體建設,例如退火氧化層,和柵極金屬材料,例如多晶矽。另外,柵極氧化物可以是原子層摻雜(ALD)柵極絕緣層,其逸出功與指定柵極金屬對應,依照行業標準,為一個高K金屬柵極處理方案。或者,柵極氧化物可以使用快速退火氧化(RTO)成型,進行低溫氧化層澱積,或矽表面低溫微波電漿氧化,然後點擊柵極材料,例如鎢或鋁。柵極堆對準LDD(輕度摻雜汲極),然後可以進行環形重度穿層摻雜,用以調整結和電晶體擊穿特性。也可以使用氧化物和/或氮化物間隙澱積,並透過後續回蝕在柵極堆9824上建設摻雜偏移間隙(未畫出)。可以進行能夠自身對準之N+源極和汲極摻雜,建設電晶體源極和汲極9820以及剩下之P-矽晶NMOS電晶體溝道9828。此時可以選擇是否進行高溫退火步驟,來開啟摻雜物和設定初始結深。最後,可用低溫氧化物9850覆蓋整個間隙填充氧化物 9850,並透過CMP加工平整。氧化物表面可以加工作為矽晶黏結氧化物,如前文所述。 As shown in Figure 98D, shallow trench isolation (STI) oxide regions (not shown) can be etched using scribe and plasma/RIE, down to at least the surface layer of oxide layer 9802, to remove regions of p-single crystal silicon layer 9804'. Gapfill oxide can be deposited and planarized by CMP to form STI oxide regions and use P-doped monocrystalline silicon regions (not shown) to build transistors. At this point, you can choose whether to perform threshold adjustment doping. The gate stack 9824 can be constructed using a gate insulator, such as annealed oxide, and a gate metal material, such as polysilicon. In addition, the gate oxide can be an atomic layer doped (ALD) gate insulating layer, whose work function corresponds to a specified gate metal, which is a high-K metal gate treatment scheme according to industry standards. Alternatively, the gate oxide can be formed using Rapid Anneal Oxidation (RTO), low-temperature oxide deposition, or low-temperature microwave plasma oxidation of the silicon surface, and then tap the gate material, such as tungsten or aluminum. The gate stack is aligned with the LDD (lightly doped drain), and then the annular heavy penetration doping can be performed to adjust the junction and transistor breakdown characteristics. Oxide and/or nitride gap deposition can also be used, followed by etch back to create a doped offset gap (not shown) on the gate stack 9824 . Self-aligning N+ source and drain can be doped to build transistor source and drain 9820 and the remaining P- silicon NMOS transistor channel 9828. At this time, you can choose whether to perform a high-temperature annealing step to turn on the dopant and set the initial junction depth. Finally, the entire gapfill oxide can be covered with low temperature oxide 9850 9850, and processed by CMP. The oxide surface can be processed as a silicon bond oxide, as described previously.

如圖98E所示,電晶體層之成型,黏結至受主晶圓9810之氧化層9850,以及後續圖98A-D之電晶體成型,可以重複進行,建設存儲電晶體之第二層9830。在所有之存儲層建設完成後,可以採用快速退火退火(RTA)開啟所有存儲層之摻雜材料,以及受體基板9810中之週邊電路。另外,也可採用光學退火,例如鐳射退火等。 As shown in Figure 98E, the formation of the transistor layer, bonding to the oxide layer 9850 of the acceptor wafer 9810, and the subsequent formation of the transistors of Figures 98A-D can be repeated to build the second layer 9830 of storage transistors. After the construction of all the storage layers is completed, rapid annealing (RTA) can be used to open the doping materials of all the storage layers and the peripheral circuits in the acceptor substrate 9810 . In addition, optical annealing, such as laser annealing, can also be used.

如圖98F所示,觸點和金屬互聯電路可以透過印刷和電漿/RIE蝕刻加工。位元線(BL)觸點9840與存儲層之電晶體N+區域連通,該區域位於電晶體汲極層9854,而且源極線觸點9842與存儲層電晶體N+區域相連,該區域位於電晶體源極側9852。位線(BL)連線9848和源極線(SL)連線9846分別與位線觸點9840和源極線觸點9842相連。柵極堆,如9834,可以與觸點和金屬層(未畫出)相連,構成字線(WL)。穿層過孔9860(未畫出)可以與BL、SL、WL之金屬層連通,並與受體基板9810之週邊電路,透過受主晶圓金屬連接焊點1980(未畫出)相連。 As shown in Figure 98F, contacts and metal interconnection circuits can be processed by printing and plasma/RIE etching. A bit line (BL) contact 9840 is connected to the storage layer transistor N+ region, which is located in the transistor drain layer 9854, and a source line contact 9842 is connected to the storage layer transistor N+ region, which is located in the transistor drain layer 9854. Source side 9852. Bit line (BL) connection 9848 and source line (SL) connection 9846 are connected to bit line contact 9840 and source line contact 9842, respectively. Gate stacks, such as 9834, can be connected to contacts and metal layers (not shown) to form word lines (WL). Through-layer vias 9860 (not shown) can communicate with the metal layers of BL, SL, and WL, and connect with peripheral circuits of the acceptor substrate 9810 through acceptor wafer metal connection pads 1980 (not shown).

如圖98G所示,為存儲陣列表面之一個俯視剖面圖,WL連線9864和SL連線9865可與BL連線9866垂直佈置。 As shown in FIG. 98G , which is a cross-sectional top view of the surface of the memory array, the WL line 9864 and the SL line 9865 can be arranged perpendicular to the BL line 9866 .

如圖98H所示,單個層之DRAM陣列之方案中,WL、BL和SL在每個陣列層之連接。陣列之多層結構共用BL、SL觸點,但是每個層有自己之WL連接組,並能實現每個位元組之單獨訪問。 As shown in FIG. 98H , in the scheme of a single-layer DRAM array, WL, BL and SL are connected at each array layer. The multi-layer structure of the array shares BL and SL contacts, but each layer has its own WL connection group, and can realize the independent visit of each byte.

該流程能夠形成水平佈置之整塊3D DRAM陣列,利用對每個存儲陣列進行兩次掩膜加工,透過對晶圓大小之摻雜單晶矽層進行層切,然後該3D DRAM陣列就可以與底層多金屬層半導體組件相連,底層組件可能包含/不包含週邊電路,用來控制DRAM之讀寫功能。 This process can form a horizontally arranged monolithic 3D DRAM array. By performing two mask processing on each memory array, the 3D DRAM array can be combined with the wafer-sized doped single crystal silicon layer. The underlying multi-metal layer semiconductor components are connected, and the underlying components may or may not contain peripheral circuits, which are used to control the read and write functions of the DRAM.

僅具有基礎知識之人員將會很容易理解圖98A-圖98H中之舉例說明(並未放大)。技術熟練人員很容易進一步想到,可以在此基礎上衍生出很多之變形,例如電晶體可以為其他類型如RCAT或無結型。或者,觸點也可以使用摻雜多晶矽,或其他導電材料。或者,成堆存儲層可以與上方之週邊電路相連。技術熟練人員在讀完本說明之後,將會意識到本項發明範圍將會囊括非常多之修改變形。因此,本項發明並非僅限於附件中之專利權聲明。 The illustrations in Figures 98A-98H (not enlarged) will be readily understood by persons with only basic knowledge. Those skilled in the art can easily think further, and many deformations can be derived on this basis. For example, the transistor can be of other types such as RCAT or junctionless. Alternatively, the contacts can also use doped polysilicon, or other conductive materials. Alternatively, stacked memory layers may be connected to peripheral circuits above. After reading this description, those skilled in the art will realize that the scope of the present invention encompasses many modifications and variations. Therefore, this invention is not limited to the patent statement in the appendix.

如圖99A-99M所示,水平佈置之整塊3D DRAM之每個存儲層使用兩個掩模步驟,可以使用合適之3D IC製造流程建設。 As shown in Figures 99A-99M, horizontally arranged monolithic 3D DRAMs using two masking steps per memory layer can be constructed using a suitable 3D IC fabrication flow.

如圖99A所示,具有週邊電路9902之矽基版可以使用耐高溫(高於400攝氏度)佈線,例如鎢。週邊電路基板9902可以包含存儲控制電路,以及其他功能和類型之電路,例如類比、數位、微波(RF)或儲存功能。週邊電路基板9902可以包含週邊電路,週邊電路能夠承受附加之快速退火退火(RTA)之溫度,並能保持工作能力和較好之性能。因此,週邊電路之構造最好不使用RTA開啟摻雜物,或使用弱RTA進行開啟。施主晶圓9902之表面可以進 行氧化層9904澱積,從而可以進行氧化物晶圓黏結,構成受主晶圓2414。 As shown in FIG. 99A , the silicon substrate with the peripheral circuit 9902 can use high temperature resistant (higher than 400 degrees Celsius) wiring, such as tungsten. The peripheral circuit substrate 9902 may contain memory control circuits, as well as other functions and types of circuits, such as analog, digital, microwave (RF), or memory functions. The peripheral circuit substrate 9902 may include peripheral circuits that can withstand the additional rapid annealing (RTA) temperature and maintain workability and better performance. Therefore, it is better to construct peripheral circuits without RTA turn-on dopant, or use weak RTA to turn on. The surface of the donor wafer 9902 can be processed An oxide layer 9904 is deposited so that the oxide wafers can be bonded to form the acceptor wafer 2414 .

如圖99B所示,一個P-基板施主晶圓9912,可以加工成包含晶圓大小之p-摻雜矽晶層9906(未畫出),該層可以之摻雜濃度可以與P-基板9906不同。P-摻雜層可以透過離子注入或退火退火製造。屏障氧化層9908可以在摻雜之前生長或澱積得到,用來保護矽晶不被摻雜,同時為後續之氧化層晶圓黏結提供氧化成。層切劃分平面9910(如虛線所示),可以在P-基板9906之施主晶圓9912上或P-摻雜層上,透過摻雜或其他前述方法實現。施主晶圓9912和受主晶圓9914均可以加工用於晶圓黏結,如前所述,並在表面進行氧化層9904和氧化層9908黏結,黏結時最好使用低溫(小於400攝氏度)來減小應力,或者使用中等溫度(小於900攝氏度)。 As shown in FIG. 99B, a P-substrate donor wafer 9912 can be processed to include a wafer-sized p-doped silicon layer 9906 (not shown) that can be doped at a concentration comparable to that of the P-substrate 9906. different. P-doped layers can be fabricated by ion implantation or annealing. The barrier oxide layer 9908 can be grown or deposited before doping to protect the silicon crystal from doping and provide oxidation for subsequent wafer bonding of the oxide layer. Layer-cut dividing planes 9910 (shown by dotted lines) can be implemented on the donor wafer 9912 of the P-substrate 9906 or on the P-doped layer by doping or other aforementioned methods. Both the donor wafer 9912 and the acceptor wafer 9914 can be processed for wafer bonding. As mentioned above, the oxide layer 9904 and the oxide layer 9908 are bonded on the surface. It is best to use low temperature (less than 400 degrees Celsius) to reduce the Light stress, or use moderate temperatures (less than 900°C).

如圖99C所示,P-施主晶圓基板9906之一部分,以及位於層切劃分平面9910之上之P-晶圓基板9906,可以透過切割和打磨、或其他前述之方法去除,例如離子切割等,從而建設單晶矽P-層9906。剩下之P-層9906’和氧化層9908則可以層切至受主晶圓9914。P-層9906’之表面可以使用化學和機械打磨之方法打磨平整。然後,可以構造電晶體或部分電晶體並與受主晶圓9914之對準標記(未畫出)對齊。 As shown in FIG. 99C, a part of the P-donor wafer substrate 9906, and the P-wafer substrate 9906 above the dicing plane 9910 can be removed by dicing and grinding, or other aforementioned methods, such as ion cutting, etc. , thereby constructing the monocrystalline silicon P-layer 9906. The remaining p-layer 9906' and oxide layer 9908 can be layer diced to the acceptor wafer 9914. The surface of the P-layer 9906' can be smoothed by chemical and mechanical polishing. Transistors or portions of transistors may then be constructed and aligned with alignment marks (not shown) of the acceptor wafer 9914 .

如圖99D所示,N+矽晶區域9916可以透過印刷畫線確定,N型,例如砷,可以使用離子植入到P-矽晶層9906’。 這樣也可以建設剩餘之P-矽晶區域9918。 As shown in FIG. 99D, the N+ silicon region 9916 can be defined by printed lines, and the N-type, such as arsenic, can be ion-implanted into the P- silicon layer 9906'. This also enables the construction of the remaining P-silicon region 9918.

如圖99E所示,氧化層9920可能會澱積,以便為後期之氧化物與氧化物之間之黏結準備好必要之表面,這樣就形成了第一層Si/SiO2層9922。Si/SiO2層包含二氧化矽層9920、N+矽區域9916和P-矽區域9918。 As shown in Figure 99E, an oxide layer 9920 may be deposited to prepare the surface necessary for later oxide-to-oxide bonding, thus forming a first Si/SiO2 layer 9922. The Si/SiO2 layer includes a silicon dioxide layer 9920 , N+ silicon regions 9916 and P− silicon regions 9918 .

如圖99F所示,可能會額外形成圖99A至圖99E所示之Si/SiO2層,比如第二層Si/SiO2層9924和第三層Si/SiO2層9926。氧化層9929可能會澱積。所有預期之存儲層都建設好之後,可進行快速高熱退火(RTA),以便從根本上開啟所有存儲層9922、9924和9926和週邊電路9902中之摻雜物。或者,可進行光學退火,例如鐳射退火。 As shown in FIG. 99F, the Si/SiO2 layers shown in FIGS. 99A to 99E may be additionally formed, such as a second Si/SiO2 layer 9924 and a third Si/SiO2 layer 9926. An oxide layer 9929 may be deposited. After all desired memory layers are built, a rapid thermal anneal (RTA) can be performed to essentially turn on dopants in all memory layers 9922, 9924 and 9926 and peripheral circuitry 9902. Alternatively, optical annealing, such as laser annealing, can be performed.

如圖99G所示,氧化層9929、第三層Si/SiO2層9926、第二層Si/SiO2層9924和第一層Si/SiO2層9922可進行光刻和電漿體/反應式離子蝕刻,形成存儲晶片結構之一部分。蝕刻可能會形成P-矽區9918(該區形成浮體電晶體溝槽)和N+矽區9916(形成源極、汲極和本地源極線路)。 As shown in FIG. 99G, the oxide layer 9929, the third Si/SiO2 layer 9926, the second Si/SiO2 layer 9924 and the first Si/SiO2 layer 9922 can be subjected to photolithography and plasma/reactive ion etching, Forms part of a memory wafer structure. Etching may form P- silicon regions 9918 (which form the floating body transistor trenches) and N+ silicon regions 9916 (which form source, drain and local source lines).

如圖99H所示,柵極電介質和柵電極材料可能會澱積,可透過化學-機械打磨(CMP)使其平面化,然後可進行光刻和電漿體/反應式離子蝕刻,以形成柵極電介質9928。柵極電介質9928可能與柵電極9930(如圖所示)自對齊,並被柵電極9930覆蓋,或者可能充分地覆蓋住整個矽/氧化物多層結構。柵電極9930和柵極電介質9928柵極堆疊層之尺寸和對齊方式應確保可充分徹底地覆蓋住P-矽 區9918’。柵極堆疊層(包含柵電極9930和柵極電介質9928)由柵極電介質(例如高熱氧化層)和柵電極材料(如多晶矽)組成。或者,柵極電介質可選擇與具體之柵極金屬之功函數相匹配之原子層澱積(ALD)材料,符合前文所述之高-k金屬柵極工藝方案之行業標準。此外,柵極電介質可透過快速高熱氧化(RTO)形成。快速高熱氧化是矽表面之一種低溫氧化澱積或低溫微波電漿體氧化之過程,最終可澱積成柵電極,例如鎢電極或鋁電極。 As shown in Figure 99H, gate dielectric and gate electrode material may be deposited, planarized by chemical-mechanical polishing (CMP), and then photolithography and plasma/reactive ion etching may be performed to form the gate electrode. pole dielectric 9928. The gate dielectric 9928 may be self-aligned with and covered by the gate electrode 9930 (as shown), or may substantially cover the entire silicon/oxide multilayer structure. The size and alignment of the gate electrode 9930 and gate dielectric 9928 gate stack should ensure adequate and complete coverage of the P-silicon District 9918'. The gate stack layer (comprising gate electrode 9930 and gate dielectric 9928) consists of a gate dielectric (eg, high thermal oxide) and a gate electrode material (eg, polysilicon). Alternatively, the gate dielectric can be selected from an atomic layer deposition (ALD) material that matches the work function of the specific gate metal, in line with the industry standard for high-k metal gate process solutions described above. In addition, the gate dielectric can be formed by rapid thermal oxidation (RTO). Rapid high thermal oxidation is a process of low-temperature oxidation deposition or low-temperature microwave plasma oxidation on the surface of silicon, which can eventually be deposited as a gate electrode, such as a tungsten electrode or an aluminum electrode.

如圖99I所示,間隙填充氧化層9932可徹底覆蓋整個結構,可透過化學-機械打磨(CMP)使其平面化。為清晰起見,圖中氧化層9932顯示為透明層。除此之外,還有文字線區(WL)9950、柵電極9930、源極線路區(SL)9952和所示之N+矽區9916’。 As shown in FIG. 99I, the gap-fill oxide layer 9932 can completely cover the entire structure, which can be planarized by chemical-mechanical polishing (CMP). For clarity, the oxide layer 9932 is shown as a transparent layer in the figure. In addition, there are word line regions (WL) 9950, gate electrodes 9930, source line regions (SL) 9952 and N+ silicon regions 9916' as shown.

如圖99J所示,位線(BL)接點9934可進行光刻和電漿體/反應式離子蝕刻,並透過光阻去除之方法進行處理。隨後,金屬(如銅、鋁或鎢)可發生澱積,對接點進行填充,然後蝕刻或打磨至氧化層9932之頂部。每個BL接點9934可充分與所有之存儲層共用,如圖99J中所示之三層存儲層。可能會形成穿層過孔9960(未顯示),透過受主晶圓金屬連接焊盤9980(未顯示)使BL、SL和WL之金屬化區域與受主基板9914週邊電路發生電耦合。 As shown in FIG. 99J, the bit line (BL) contact 9934 can be photolithographically and plasma/reactive ion etched and processed by photoresist stripping. Subsequently, a metal such as copper, aluminum or tungsten may be deposited to fill the contacts and then etched or polished to the top of the oxide layer 9932. Each BL contact 9934 can be fully shared with all memory layers, such as the three memory layers shown in Figure 99J. Through-layer vias 9960 (not shown) may be formed to electrically couple the metallized areas of BL, SL, and WL to peripheral circuitry of the acceptor substrate 9914 through acceptor wafer metal connection pads 9980 (not shown).

如圖99K所示,可形成BL金屬線9936,並與相關之BL接點9934連接在一起。在存儲陣列邊緣可形成WL和SL之接點和相關之金屬佈線(未顯示)。可利用《具有沖孔和 填塞工藝之適用于超高密度快閃式記憶體之三維晶片層疊技術》(《2007年IEEE超大規模集成技術研討會》;卷號:無;頁碼:14-15、12-14;2007年六月刊;作者:Tanaka,H.、Kido,M.、Yahashi,K.和Oomura,M.等人)中描述之技術將SL接點製成階梯狀結構。 As shown in FIG. 99K , BL metal lines 9936 may be formed and connected together with associated BL contacts 9934 . Contacts for WL and SL and associated metal wiring (not shown) may be formed at the edge of the memory array. Available with "Punched and Three-dimensional chip stacking technology suitable for ultra-high-density flash memory by filling process" ("2007 IEEE Symposium on Very Large-Scale Integration Technology"; Volume: None; Page: 14-15, 12-14; June 2007 Monthly; Authors: Tanaka, H., Kido, M., Yahashi, K., and Oomura, M. et al.) make SL contacts into a stepped structure.

如圖99L、99L1和99L2所示,圖99L之橫截面剖視圖二見圖99L1,圖99L之橫截面剖視圖三見圖99L2。BL金屬線9936、氧化層9932、BL接點9934、WL區9950、柵極電介質9928、P-矽區9918’和週邊電路基板9902見圖99L1。BL接點9934連接浮體電晶體三個水平面之其中一側。浮體電晶體包含每個水平面之兩個N+矽區9916’以及相應之P-矽區9918’。BL金屬線9936、氧化層9932、柵電極9930、柵極電介質9928、P-矽區9918’、夾層氧化區(OX)和週邊電路基板9902見圖99L2。柵電極9930在六個P-矽區9918’中都很常見,它們形成了六個雙面柵控浮體電晶體。 As shown in Figures 99L, 99L1 and 99L2, the second cross-sectional view of Figure 99L is shown in Figure 99L1, and the third cross-sectional view of Figure 99L is shown in Figure 99L2. BL metal line 9936, oxide layer 9932, BL contact 9934, WL region 9950, gate dielectric 9928, P-silicon region 9918' and peripheral circuit substrate 9902 are shown in FIG. 99L1. The BL contact 9934 connects one of the three horizontal planes of the floating body transistor. The floating body transistor includes two N+ silicon regions 9916' for each horizontal plane and corresponding P- silicon regions 9918'. BL metal line 9936, oxide layer 9932, gate electrode 9930, gate dielectric 9928, P-silicon region 9918', interlayer oxide region (OX) and peripheral circuit substrate 9902 are shown in FIG. 99L2. Gate electrodes 9930 are common to the six P-silicon regions 9918', which form six double-sided gated floating body transistors.

如圖99M所示,在第一層Si/SiO2層9922上雙柵極典型之浮體電晶體可能包含P-矽區9918’(起到浮體電晶體溝槽之作用)、N+矽區9916’(起到源極和汲極之作用)和兩個柵電極9930(帶相應之柵極電介質9928)。電晶體藉由氧化層9908可與下方絕緣。 As shown in FIG. 99M, a typical floating body transistor with double gates on the first Si/SiO2 layer 9922 may include a P-silicon region 9918' (acting as a floating body transistor trench), an N+ silicon region 9916 ' (acting as source and drain) and two gate electrodes 9930 (with corresponding gate dielectric 9928). The transistors are insulated from below by the oxide layer 9908 .

該流程可形成水平方向單塊3D DRAM。在透過逐一轉移晶圓大小之單晶摻雜矽層而形成之記憶體中,該DRAM使用一個掩蔽工序。同時,該3D DRAM與下方之多 金屬層半導體設備連接起來。 This process can form a monolithic 3D DRAM in the horizontal direction. The DRAM uses a masking process in memory formed by transferring wafer-sized single-crystal doped silicon layers one by one. At the same time, the 3D DRAM is as much Metal layer semiconductor devices are connected.

具有一般技藝之人可將圖99A至圖99M中提到之例子僅作為典型範例看待,並非按比例縮小。技藝高超之人可考量更多之變化情況。比如,可採用其他類型之電晶體,比如RCAT等,或採用更少之接頭。或者接點可使用摻雜多晶矽或其他之導電材料。或者堆疊式記憶體層可與存儲堆疊層上方之週邊電路連接起來。或者,只要利用鐳射退火系統完成相關之注入程式,Si/SiO2層9922、9924和9926可逐層退火。透過閱讀本說明書,可使技藝高超之人想起如何在本發明範圍內對其他地方進行修改。因此,本發明僅受限於附加之權利要求。 Those of ordinary skill may consider the examples mentioned in FIGS. 99A-99M to be representative examples only and not scaled down. A skilled person can take into account more changes. For example, other types of transistors, such as RCAT, etc., can be used, or fewer contacts can be used. Alternatively, doped polysilicon or other conductive materials can be used for the contacts. Alternatively, the stacked memory layer can be connected to peripheral circuits above the memory stack layer. Alternatively, the Si/SiO2 layers 9922, 9924 and 9926 can be annealed layer by layer as long as the relevant implantation procedures are completed by using a laser annealing system. A reading of this specification will allow the skilled person to recall how to make modifications elsewhere within the scope of the invention. Accordingly, the invention is limited only by the appended claims.

如圖100A至100L所示,可建設水平方向之3D DRAM。在徹底將所有層轉移之後,這種記憶體在每個存儲層透過共用掩蔽工序之方法不使用附加掩蔽工序。3D DRAM適用於生產3D IC。 As shown in FIGS. 100A to 100L, a horizontally oriented 3D DRAM can be constructed. After all layers have been completely transferred, this method of memory passes through a common masking process for each memory layer without using an additional masking process. 3D DRAM is suitable for producing 3D ICs.

如圖100A所示,帶週邊電路10002之矽基板可使用耐高溫(超過400℃)配線,例如鎢絲。週邊電路基板10002可包含記憶體控制電路以及其他用途之各種電路,例如用於類比、數位、射頻或存儲。週邊電路基板10002可包含週邊電路。這種週邊電路即便在經過附加快速高熱退火(RTA)後仍然可以繼續運行,保持良好之性能。為此,在組建週邊電路時應考量選擇那些只需要輕微RTA或無需RTA之即可開啟摻雜物之週邊電路。週邊電路基板10002之最上面一層可用於將氧化物晶圓和二氧化矽10004之澱 積層黏結起來,從而形成受主晶圓10014。 As shown in FIG. 100A , the silicon substrate with the peripheral circuit 10002 can use high temperature (over 400° C.) wiring, such as tungsten wire. The peripheral circuit substrate 10002 may include memory control circuits and various circuits for other purposes, such as analog, digital, radio frequency or storage. The peripheral circuit substrate 10002 may include peripheral circuits. This peripheral circuit can continue to operate even after additional rapid thermal annealing (RTA), maintaining good performance. For this reason, when constructing peripheral circuits, it should be considered to select those peripheral circuits that can turn on the dopant only with a slight RTA or without RTA. The uppermost layer of the peripheral circuit substrate 10002 can be used to deposit oxide wafer and silicon dioxide 10004 The buildup is bonded to form the acceptor wafer 10014.

如圖100B所示,單晶矽施主晶圓10012可包含晶圓大小之P-摻雜層(未顯示),其中之摻雜物濃度可能與P-基板1006不同。P-摻雜層可透過離子注入和高熱退火方式形成。可在注入之前生長或澱積遮罩氧化層10008,以確保在注入過程中矽免受污染,並為後期晶圓之間之黏結提供氧化層。透過氫離子注入或前文所描述之其他方法可在P-基板10006或P-摻雜層(未顯示)中之施主晶圓10012中形成層轉移分界平面10010(圖中虛線部分)。如前文所述,施主晶圓10012和受主晶圓10014均用於晶圓黏結,並在氧化層10004和氧化層10008之表面黏結在一起。因低溫時應力最低,黏結操作最好在低溫(低於400℃)或中溫(不超過900℃)下進行。 As shown in FIG. 100B , single crystal silicon donor wafer 10012 may include a wafer-sized P-doped layer (not shown), which may have a different dopant concentration than P-substrate 1006 . The P-doped layer can be formed by ion implantation and high temperature annealing. A mask oxide layer 10008 may be grown or deposited prior to implantation to ensure that silicon is free from contamination during implantation and to provide an oxide layer for later wafer-to-wafer bonding. A layer transfer boundary plane 10010 (dotted line in the figure) can be formed in the donor wafer 10012 in the P-substrate 10006 or in the P-doped layer (not shown) by hydrogen ion implantation or other methods described above. As previously mentioned, both the donor wafer 10012 and the acceptor wafer 10014 are used for wafer bonding, and are bonded together on the surfaces of the oxide layer 10004 and the oxide layer 10008 . Because the stress is lowest at low temperature, the bonding operation is best carried out at low temperature (below 400°C) or medium temperature (not exceeding 900°C).

如圖100C所示,可透過切割或打磨或前文所述之工序(例如離子切割或其他之方法)將層轉移分界平面10010上方之P-層部分(未顯示)和P-晶圓基板10006移除,從而形成剩餘之單晶矽P-層10006’。剩餘之P-層10006’和氧化層10008被層切到受主晶圓10014上。可透過化學或機械方式將P-層10006’之最上面一層打磨光滑、平坦。現在電晶體已全部或部分形成,並與受主晶圓10014之對準標誌(未顯示)對齊。氧化層10020可能會澱積,為後期氧化物之間之黏結提供表面。此時,第一層Si/SiO2層10023已形成,包含二氧化矽層10020、P-矽層10006’和氧化層10008。 As shown in FIG. 100C, the portion of the P-layer (not shown) above the layer-transfer interface plane 10010 and the P-wafer substrate 10006 can be removed by dicing or grinding or the processes described above (such as ion cutting or other methods). removal, thereby forming the remaining single crystal silicon P-layer 10006'. The remaining P-layer 10006' and oxide layer 10008 are layer diced onto the acceptor wafer 10014. The topmost layer of the P-layer 10006' can be polished smooth and flat by chemical or mechanical means. The transistors are now fully or partially formed and aligned with the alignment marks (not shown) of the acceptor wafer 10014 . An oxide layer 10020 may be deposited to provide a surface for later bonding between oxides. At this point, the first Si/SiO2 layer 10023 has been formed, including the silicon dioxide layer 10020, the P-silicon layer 10006' and the oxide layer 10008.

如圖100D所示,可能會額外形成圖100A至圖100C所示之Si/SiO2層,比如第二層Si/SiO2層10025和第三層Si/SiO2層10027。氧化層10029可能會澱積,實現與頂部矽層之間之絕緣。 As shown in FIG. 100D, Si/SiO2 layers shown in FIGS. 100A to 100C may be additionally formed, such as a second Si/SiO2 layer 10025 and a third Si/SiO2 layer 10027. An oxide layer 10029 may be deposited to provide isolation from the top silicon layer.

如圖100E所示,氧化層10029、第三層Si/SiO2層10027、第二層Si/SiO2層10025和第一層Si/SiO2層10023可進行光刻和電漿體/反應式離子蝕刻,形成存儲晶片結構之一部分。存儲晶片結構現在已包含P-矽區10016和氧化層區10022。 As shown in Figure 100E, the oxide layer 10029, the third Si/SiO2 layer 10027, the second Si/SiO2 layer 10025 and the first Si/SiO2 layer 10023 can be photolithographically and plasma/reactive ion etched, Forms part of a memory wafer structure. The memory chip structure now includes P-silicon region 10016 and oxide layer region 10022 .

如圖100F所示,柵極電介質和柵電極材料可能會澱積,可透過化學-機械打磨(CMP)使其平面化,然後可進行光刻和電漿體/反應式離子蝕刻,以形成柵極電介質10028。柵極電介質10028可能與柵電極10030(如圖所示)自對齊,並被柵電極10030覆蓋,或者可能充分地覆蓋住整個矽/氧化物多層結構。柵極堆疊層(包含柵電極10030和柵極電介質10028)由柵極電介質(例如高熱氧化層)和柵電極材料(如多晶矽)組成。或者,柵極電介質可選擇與具體之柵極金屬之功函數相匹配之原子層澱積(ALD)材料,符合前文所述之高-k金屬柵極工藝方案之行業標準。此外,柵極電介質可透過快速高熱氧化(RTO)形成。快速高熱氧化是矽表面之一種低溫氧化澱積或低溫微波電漿體氧化之過程,最終可澱積成柵電極,例如鎢電極或鋁電極。 As shown in Figure 100F, gate dielectric and gate electrode material may be deposited, planarized by chemical-mechanical polishing (CMP), and then photolithography and plasma/reactive ion etching may be performed to form the gate electrode. pole dielectric 10028. The gate dielectric 10028 may be self-aligned with and covered by the gate electrode 10030 (as shown), or may substantially cover the entire silicon/oxide multilayer structure. The gate stack layer (comprising gate electrode 10030 and gate dielectric 10028) consists of a gate dielectric (eg, high thermal oxide) and a gate electrode material (eg, polysilicon). Alternatively, the gate dielectric can be selected from an atomic layer deposition (ALD) material that matches the work function of the specific gate metal, in line with the industry standard for high-k metal gate process solutions described above. In addition, the gate dielectric can be formed by rapid thermal oxidation (RTO). Rapid high thermal oxidation is a process of low-temperature oxidation deposition or low-temperature microwave plasma oxidation on the surface of silicon, which can eventually be deposited as a gate electrode, such as a tungsten electrode or an aluminum electrode.

如圖100G所示,可透過向P-矽區10016中注入N型離 子之方法(例如砷)使N+矽區10026與柵電極10030實現自對齊。P-矽區10016不受到柵電極10030之阻隔。這樣就在柵電極10030阻隔之區域形成了其餘之P-矽區10017(未顯示)。在將N型離子置入每層P-矽區10016中時可採用不同之注入能量或角度或注入倍數。在多步注入過程中可使用柵側壁(未顯示),不同堆疊層中出現之矽層使用之柵側壁寬度可能也不同,用以說明N型離子注入之不同橫向擴散。底層(例如10023)可能比頂層(例如10027)所需之柵側壁更寬。同樣,可使用帶基板旋轉功能之角度離子注入補償不同之注入擴散。頂層注入可能具有一定之傾斜角,與晶圓表面並不垂直,銀耳它將離子置於柵電極10030之邊緣之稍下方,與垂直度更好之較低層之離子注入密切配合。因到達將底層所需之注入能量較高,從而產生擴散效應,較低層之離子注入可將離子置入柵電極10030之稍下方。可進行快速高熱退火(RTA),以便從根本上開啟所有存儲層10023、10025和10027和週邊電路10002中之摻雜物。或者,可進行光學退火,例如鐳射退火。 As shown in Figure 100G, the N-type ion can be implanted into the P-silicon region 10016 The N+ silicon region 10026 and the gate electrode 10030 are self-aligned by a sub-method (such as arsenic). The P-silicon region 10016 is not blocked by the gate electrode 10030 . This forms the rest of the P-silicon region 10017 (not shown) in the region blocked by the gate electrode 10030. When implanting N-type ions into each layer of P-silicon region 10016, different implantation energies or angles or implantation multiples can be used. Gate sidewalls (not shown) may be used in a multi-step implantation process, and different gate sidewall widths may be used for silicon layers present in different stacks to account for the different lateral diffusion of N-type ion implantation. The bottom layer (eg, 10023) may have wider gate sidewalls than the top layer (eg, 10027) requires. Likewise, angular ion implantation with substrate rotation can be used to compensate for different implant spreads. The top layer implant may have a certain tilt angle, which is not perpendicular to the wafer surface, and it places the ions slightly below the edge of the gate electrode 10030, which is closely coordinated with the ion implantation of the lower layer with better perpendicularity. Ion implantation of the lower layers can place ions slightly below the gate electrode 10030 due to the higher implant energy required to reach the bottom layer, resulting in a diffusion effect. A rapid thermal anneal (RTA) may be performed to essentially turn on dopants in all memory layers 10023, 10025 and 10027 and peripheral circuitry 10002. Alternatively, optical annealing, such as laser annealing, can be performed.

如圖100H所示,間隙填充氧化層10032可覆蓋整個結構,可透過化學-機械打磨(CMP)使其平面化。為清晰起見,圖中氧化層10032顯示為透明層。除此之外,還有文字線區(WL)10050、柵電極10030、源極線路區(SL)10052和所示之N+矽區10026。 As shown in Figure 100H, a gap-fill oxide layer 10032 may cover the entire structure, which may be planarized by chemical-mechanical polishing (CMP). For clarity, the oxide layer 10032 is shown as a transparent layer in the figure. In addition, there are word line region (WL) 10050, gate electrode 10030, source line region (SL) 10052 and N+ silicon region 10026 as shown.

如圖100I所示,位線(BL)接點10034可進行光刻和 電漿體/反應式離子蝕刻,並透過光阻去除之方法進行處理。隨後,金屬(如銅、鋁或鎢)可發生澱積,對接點進行填充,然後蝕刻或打磨至氧化層10032之頂部。每個BL接點10034可充分與所有存儲層共用,如圖100I中所示之三層存儲層。可能會形成穿層過孔10060(未顯示),透過受主晶圓金屬連接焊盤10014(未顯示)使BL、SL和WL之金屬化區域與受主基板10080週邊電路發生電耦合。 As shown in Figure 100I, the bit line (BL) contacts 10034 can be photolithographically and Plasma/Reactive Ion Etching and processing by photoresist removal. Subsequently, a metal such as copper, aluminum or tungsten may be deposited to fill the contacts and then etched or polished to the top of the oxide layer 10032. Each BL contact 10034 can be fully shared with all storage layers, such as the three storage layers shown in Figure 100I. Through-layer vias 10060 (not shown) may be formed to electrically couple the metallized areas of BL, SL and WL to peripheral circuitry of the acceptor substrate 10080 through acceptor wafer metal connection pads 10014 (not shown).

如圖100J所示,可形成BL金屬線10036,並與相關之BL接點10034連接在一起。在存儲陣列邊緣可形成WL和SL之接點和相關之金屬佈線(未顯示)。 As shown in Figure 100J, BL metal lines 10036 may be formed and connected together with associated BL contacts 10034. Contacts for WL and SL and associated metal wiring (not shown) may be formed at the edge of the memory array.

圖100K之橫截面剖視圖二見圖100K1,圖100K之橫截面剖視圖三見圖100K2。BL金屬線10036、氧化層10032、BL接點10034、WL區10050、柵極電介質10028、N+矽區10026、P-矽區10017和週邊電路基板10002見圖100K1。BL接點10034連接浮體電晶體三個水平面之其中一側。浮體電晶體包含每個水平面之兩個N+矽區10026以及相應之P-矽區10017。BL金屬線10036、氧化層10032、柵電極10030、柵極電介質10028、P-矽區10017、夾層氧化區(OX)和週邊電路基板10002見圖100K2。柵電極10030在六個P-矽區10017中都很常見,它們形成了六個雙面柵控浮體電晶體。 The second cross-sectional view of FIG. 100K is shown in FIG. 100K1, and the third cross-sectional view of FIG. 100K is shown in FIG. 100K2. BL metal line 10036, oxide layer 10032, BL contact 10034, WL region 10050, gate dielectric 10028, N+ silicon region 10026, P- silicon region 10017 and peripheral circuit substrate 10002 are shown in FIG. 100K1. The BL contact 10034 connects one of the three horizontal planes of the floating body transistor. The floating body transistor comprises two N+ silicon regions 10026 and corresponding P- silicon regions 10017 per horizontal plane. BL metal line 10036, oxide layer 10032, gate electrode 10030, gate dielectric 10028, P-silicon region 10017, interlayer oxide region (OX) and peripheral circuit substrate 10002 are shown in FIG. 100K2. Gate electrodes 10030 are common in the six P-silicon regions 10017, which form six double-sided gated floating body transistors.

如圖100M所示,在第一層Si/SiO2層10023上雙柵極典型之浮體電晶體可能包含P-矽區10017(起到浮體電晶體溝槽之作用)、N+矽區10026(起到源極和汲極之作用) 和兩個柵電極10030(帶相應之柵極電介質10028)。電晶體藉由氧化層10008可與下方絕緣。 As shown in FIG. 100M, a typical floating body transistor with double gates on the first Si/SiO2 layer 10023 may include a P-silicon region 10017 (acting as a floating body transistor trench), an N+ silicon region 10026 ( function as source and sink) and two gate electrodes 10030 (with corresponding gate dielectrics 10028). The transistors are insulated from below by the oxide layer 10008 .

該流程可形成水平方向單塊3D DRAM。在透過逐一轉移晶圓大小之單晶摻雜矽層而形成之記憶體中,該3D DRAM不使用掩蔽工序。同時,該DRAM與下方之多金屬層半導體設備連接起來。 This process can form a monolithic 3D DRAM in the horizontal direction. The 3D DRAM does not use a masking process in a memory formed by transferring wafer-sized single-crystal doped silicon layers one by one. At the same time, the DRAM is connected to the underlying MLS device.

具有一般技藝之人可將圖100A至圖100L中提到之例子僅作為典型範例看待,並非按比例縮小。技藝高超之人可考量更多之變化情況。比如,可採用其他類型之電晶體,比如RCAT等,或採用更少接頭。或者接點可使用摻雜多晶矽或其他導電材料。或者堆疊式記憶體層可與存儲堆疊層上方之週邊電路連接起來。此外,雙柵極3D DRAM之每個柵極可獨立控制,以更好地控制存儲晶片。透過閱讀本說明書,可使技藝高超之人想起如何在本發明範圍內對其他地方進行修改。因此,本發明僅受限於附加之權利要求。 One of ordinary skill would consider the examples mentioned in FIGS. 100A-100L to be representative examples only and not to scale. A skilled person can take into account more changes. For example, other types of transistors can be used, such as RCAT, etc., or fewer contacts can be used. Alternatively, doped polysilicon or other conductive materials can be used for the contacts. Alternatively, the stacked memory layer can be connected to peripheral circuits above the memory stack layer. In addition, each gate of dual-gate 3D DRAM can be independently controlled to better control the memory chip. A reading of this specification will allow the skilled person to recall how to make modifications elsewhere within the scope of the invention. Accordingly, the invention is limited only by the appended claims.

利用材料電阻變化特徵之新型單塊3D存儲技術可採用類似之方式。有很多種電阻性記憶體,包含相變記憶體、金屬氧化物記憶體、電阻性隨機記憶體(RRAM)、憶阻器、固體電介質式記憶體、鐵電隨機記憶體和磁性隨機記憶體等。這些電阻性記憶體類型之背景資訊見《儲存等級之記憶體候選設備技術概述》(《IBM公司研究與研發雜誌》;卷號:52;編號4.5;頁碼:449-464;2008年七月刊;作者:G.W.等人)。本說明書中加入了本檔之相關內 容,以供參考。 New monolithic 3D memory technologies that take advantage of the material's resistance-changing characteristics could be used in a similar fashion. There are many types of resistive memory, including phase change memory, metal oxide memory, resistive random access memory (RRAM), memristor, solid dielectric memory, ferroelectric random access memory and magnetic random access memory, etc. . For background information on these resistive memory types, see "Storage Class Memory Candidate Technology Overview" (IBM Corporate Research and Development Journal; Vol. 52; No. 4.5; Pages: 449-464; July 2008; Author: G.W. et al). The relevant content of this document is added to this manual content for reference.

如圖101A至101K所示,可利用電阻性無附加掩蔽工序在每個存儲層建設3D記憶體。3D記憶體適用於生產3D IC。該3D記憶體使用無結型電晶體,擁有電阻性記憶組件,與選擇電晶體或存取電晶體串聯。 As shown in Figures 101A to 101K, 3D memory can be built using a resistive no additional masking process at each memory layer. 3D memory is suitable for producing 3D IC. The 3D memory uses junctionless transistors with resistive memory components connected in series with select transistors or access transistors.

如圖101A所示,帶週邊電路10102之矽基板可使用耐高溫(超過400℃左右)配線,例如鎢絲。週邊電路基板10102可包含記憶體控制電路以及其他用途之各種電路,例如用於類比、數位、射頻或存儲。週邊電路基板10102可包含週邊電路。這種週邊電路即便在經過附加快速高熱退火(RTA)後仍然可以繼續運行,保持良好之性能。為此,在組建週邊電路時應考量選擇那些只需要輕微RTA或無需RTA之即可開啟摻雜物之週邊電路。週邊電路基板10102之最上面一層可用於將氧化物晶圓和二氧化矽10104之澱積層黏結起來,從而形成受主晶圓10114。 As shown in FIG. 101A , the silicon substrate with the peripheral circuit 10102 can use high temperature (over 400° C.) wiring, such as tungsten wire. The peripheral circuit substrate 10102 may include memory control circuits and various circuits for other purposes, such as analog, digital, radio frequency or storage. The peripheral circuit substrate 10102 may include peripheral circuits. This peripheral circuit can continue to operate even after additional rapid thermal annealing (RTA), maintaining good performance. For this reason, when constructing peripheral circuits, it should be considered to select those peripheral circuits that can turn on the dopant only with a slight RTA or without RTA. The uppermost layer of the peripheral circuit substrate 10102 can be used to bond the oxide wafer and the deposited layer of silicon dioxide 10104 to form the acceptor wafer 10114 .

如圖101B所示,單晶矽施主晶圓10112可選擇性地包含晶圓大小之N+摻雜層(未顯示),其中之摻雜物濃度可能與N+基板10106不同。N+摻雜層可透過離子注入和高熱退火方式形成。可在注入之前生長或澱積遮罩氧化層10108,以確保在注入過程中矽免受污染,並為後期晶圓之間之黏結提供氧化層。透過氫離子注入或前文所描述之其他方法可在N+基板10106或N+摻雜層(未顯示)中之施主晶圓10112中形成層轉移分界平面10110(圖中虛線部分)。如前文所述,施主晶圓10112和受主晶圓10114均用 於晶圓黏結,並在氧化層10104和氧化層10108之表面黏結在一起。因低溫時應力最低,黏結操作最好在低溫(低於400℃)或中溫(不超過900℃)下進行。 As shown in FIG. 101B , single crystal silicon donor wafer 10112 may optionally include a wafer-sized N+ doped layer (not shown), which may have a different dopant concentration than N+ substrate 10106 . The N+ doped layer can be formed by ion implantation and high thermal annealing. A mask oxide layer 10108 may be grown or deposited prior to implantation to ensure that the silicon is free from contamination during implantation and to provide an oxide layer for later wafer-to-wafer bonding. A layer transfer boundary plane 10110 (dotted line in the figure) can be formed in the N+ substrate 10106 or the donor wafer 10112 in the N+ doped layer (not shown) by hydrogen ion implantation or other methods described above. As previously mentioned, the donor wafer 10112 and the acceptor wafer 10114 are both Bonded to the wafer and bonded together on the surfaces of the oxide layer 10104 and the oxide layer 10108. Because the stress is lowest at low temperature, the bonding operation is best carried out at low temperature (below 400°C) or medium temperature (not exceeding 900°C).

如圖101C所示,可透過切割或打磨或前文所述之工序(例如離子切割或其他之方法)將層轉移分界平面10110上方之N+層部分(未顯示)和N+晶圓基板10106移除,從而形成剩餘之單晶矽N+層10106。剩餘之N+層10106’和氧化層10108被層切到受主晶圓10114上。可透過化學或機械方式將N+層10106’之最上面一層打磨光滑、平坦。現在電晶體已全部或部分形成,並與受主晶圓10114之對準標誌(未顯示)對齊。氧化層10120可能會澱積,為後期氧化物之間之黏結提供表面。此時,第一層Si/SiO2層10023已形成,包含二氧化矽層10120、N+矽層10106’和氧化層10108。 As shown in FIG. 101C, the N+ layer portion (not shown) above the layer transfer interface plane 10110 and the N+ wafer substrate 10106 can be removed by dicing or grinding or the processes described above (such as ion cutting or other methods), Thus, the remaining monocrystalline silicon N+ layer 10106 is formed. The remaining N+ layer 10106' and oxide layer 10108 are layer diced onto the acceptor wafer 10114. The uppermost layer of the N+ layer 10106' can be polished smooth and flat by chemical or mechanical means. The transistors are now fully or partially formed and aligned with the alignment marks (not shown) of the acceptor wafer 10114. An oxide layer 10120 may be deposited to provide a surface for later bonding between oxides. At this point, the first Si/SiO2 layer 10023 has been formed, including the silicon dioxide layer 10120, the N+ silicon layer 10106' and the oxide layer 10108.

如圖101D所示,可能會額外形成圖101A至圖101C所示之Si/SiO2層,比如第二層Si/SiO2層10125和第三層Si/SiO2層10127。氧化層10129可能會澱積,實現與頂部N+矽層之間之絕緣。 As shown in FIG. 101D, Si/SiO2 layers shown in FIGS. 101A to 101C may be additionally formed, such as a second Si/SiO2 layer 10125 and a third Si/SiO2 layer 10127. An oxide layer 10129 may be deposited to provide isolation from the top N+ silicon layer.

如圖101E所示,氧化層10129、第三層Si/SiO2層10127、第二層Si/SiO2層10125和第一層Si/SiO2層10123可進行光刻和電漿體/反應式離子蝕刻,形成存儲晶片結構之一部分。存儲晶片結構現在已包含N+矽區10126和氧化層區10122。 As shown in Figure 101E, the oxide layer 10129, the third Si/SiO2 layer 10127, the second Si/SiO2 layer 10125 and the first Si/SiO2 layer 10123 can be photolithographically and plasma/reactive ion etched, Forms part of a memory wafer structure. The memory wafer structure now includes N+ silicon region 10126 and oxide layer region 10122 .

如圖101F所示,柵極電介質和柵電極材料可能會澱 積,可透過化學-機械打磨(CMP)使其平面化,然後可進行光刻和電漿體/反應式離子蝕刻,以形成柵極電介質10128。柵極電介質10128可能與柵電極10130(如圖所示)自對齊,並被柵電極10130覆蓋,或者可能充分地覆蓋住整個N+矽區10126和氧化層區10122多層結構。柵極堆疊層(包含柵電極10130和柵極電介質10128)由柵極電介質(例如高熱氧化層)和柵電極材料(如多晶矽)組成。或者,柵極電介質可選擇與具體之柵極金屬之功函數相匹配之原子層澱積(ALD)材料,符合前文所述之高-k金屬柵極工藝方案之行業標準。此外,柵極電介質可透過快速高熱氧化(RTO)形成。快速熱氧化是矽表面之一種低溫氧化澱積或低溫微波電漿體氧化之過程,最終可澱積成柵電極,例如鎢電極或鋁電極。 As shown in Figure 101F, the gate dielectric and gate electrode material may deposit The area can be planarized by chemical-mechanical polishing (CMP), and then photolithography and plasma/reactive ion etching can be performed to form the gate dielectric 10128. The gate dielectric 10128 may be self-aligned with and covered by the gate electrode 10130 (as shown), or may substantially cover the entire N+ silicon region 10126 and oxide region 10122 multilayer structure. The gate stack layer (comprising gate electrode 10130 and gate dielectric 10128) consists of a gate dielectric (eg, high thermal oxide) and a gate electrode material (eg, polysilicon). Alternatively, the gate dielectric can be selected from an atomic layer deposition (ALD) material that matches the work function of the specific gate metal, in line with the industry standard for high-k metal gate process solutions described above. In addition, the gate dielectric can be formed by rapid thermal oxidation (RTO). Rapid thermal oxidation is a process of low-temperature oxidation deposition or low-temperature microwave plasma oxidation on the surface of silicon, which can eventually be deposited as a gate electrode, such as a tungsten electrode or an aluminum electrode.

如圖101G所示,間隙填充氧化層10132可覆蓋整個結構,可透過化學-機械打磨(CMP)使其平面化。為清晰起見,圖中氧化層10132顯示為透明層。除此之外,還有文字線區(WL)10150、柵電極10130、源極線路區(SL)10152和所示之N+矽區10126。 As shown in FIG. 101G, a gap-fill oxide layer 10132 may cover the entire structure, which may be planarized by chemical-mechanical polishing (CMP). For clarity, the oxide layer 10132 is shown as a transparent layer in the figure. In addition, there are word line region (WL) 10150, gate electrode 10130, source line region (SL) 10152 and N+ silicon region 10126 as shown.

如圖101H所示,位線(BL)接點10134可透過氧化層10132、三個N+矽區10126和相關之氧化層垂直絕緣區進行光刻和電漿體/反應式離子蝕刻,以便與所有之存儲層垂直連接。BL接點10134透過光阻去除之方法進行處理。阻變記憶體材料10138,比如二氧化鉿,接下來可能會澱積,最好為原子層澱積(ALD)。阻變記憶體組件之電極 接下來可能會被ALD澱積,形成電極/BL接點10134。應對多餘之澱積材料進行打磨,使之與氧化層10132頂部或頂部下方處於同一表面。每個帶有阻變材料10138之BL接點10034可充分與所有存儲層共用,如圖101H中所示之三層存儲層。 As shown in Figure 101H, the bit line (BL) contact 10134 can be photolithographically and plasma/reactive ion etched through the oxide layer 10132, the three N+ silicon regions 10126 and the associated oxide layer vertical isolation regions, so as to communicate with all The storage layer is connected vertically. BL contact 10134 is processed by photoresist stripping. The resistive memory material 10138, such as hafnium dioxide, may then be deposited, preferably by atomic layer deposition (ALD). Electrodes of resistive memory components This may then be deposited by ALD to form electrode/BL contact 10134 . Excess deposited material should be polished so that it is on the same surface as or below the top of the oxide layer 10132. Each BL contact 10034 with resistive material 10138 can be fully shared with all storage layers, such as the three storage layers shown in FIG. 101H.

如圖101I所示,可形成BL金屬線10136,並與相關之帶有阻變材料10138之BL接點10134連接在一起。在存儲陣列邊緣可形成WL和SL之接點和相關之金屬佈線(未顯示)。可能會形成穿層過孔10160(未顯示),透過受主晶圓金屬連接焊盤10114(未顯示)使BL、SL和WL之金屬化區域與受主基板10180週邊電路發生電耦合。 As shown in FIG. 101I , a BL metal line 10136 can be formed and connected to a related BL contact 10134 with a resistive material 10138 . Contacts for WL and SL and associated metal wiring (not shown) may be formed at the edge of the memory array. Through-layer vias 10160 (not shown) may be formed to electrically couple the metallized areas of BL, SL and WL to peripheral circuitry of the acceptor substrate 10180 through acceptor wafer metal connection pads 10114 (not shown).

圖101J之橫截面剖視圖二見圖101J1,圖101J之橫截面剖視圖三見圖101J2。圖101J1顯示了BL金屬線10136、氧化層10132、BL接點/電極10134、阻變材料10138、WL區10150、柵極電介質10128、N+矽區10126和週邊電路基板10102。BL接點/電極10134與阻變材料10138之三個水平面之其中一個邊相連。阻變材料10138之另外一邊與N+區10126相連。BL金屬線10136、氧化層10132、柵電極10130、柵極電介質10128、N+矽區10126、夾層氧化區(OX)和週邊電路基板10102見圖101J2。柵電極10130在六個N+矽區10126中都很常見,它們形成了六個雙面柵控無結型電晶體,作為記憶體選擇電晶體。 The second cross-sectional view of Fig. 101J is shown in Fig. 101J1, and the third cross-sectional view of Fig. 101J is shown in Fig. 101J2. Figure 101J1 shows BL metal line 10136, oxide layer 10132, BL contact/electrode 10134, resistive switch material 10138, WL region 10150, gate dielectric 10128, N+ silicon region 10126 and peripheral circuit substrate 10102. The BL contact/electrode 10134 is connected to one of the three horizontal planes of the resistive material 10138 . The other side of the resistive material 10138 is connected to the N+ region 10126 . BL metal line 10136, oxide layer 10132, gate electrode 10130, gate dielectric 10128, N+ silicon region 10126, interlayer oxide region (OX) and peripheral circuit substrate 10102 are shown in FIG. 101J2. The gate electrodes 10130 are common in the six N+ silicon regions 10126, and they form six double-sided gate-controlled junctionless transistors as memory selection transistors.

如圖101K所示,在第一層Si/SiO2層10123上雙柵極無結型典型之電晶體可能包含N+矽區10126(起到源極、汲 極和電晶體溝槽之作用)和兩個柵電極10130(帶相應之柵極電介質10128)。電晶體藉由氧化層10108可與下方絕緣。 As shown in FIG. 101K, a typical double gate junctionless transistor on the first Si/SiO2 layer 10123 may include an N+ silicon region 10126 (serving as source, drain electrodes and transistor trenches) and two gate electrodes 10130 (with corresponding gate dielectrics 10128). The transistors are insulated from below by the oxide layer 10108 .

該流程可形成電阻性多層或3D存儲陣列,每個存儲層不使用附加掩蔽工序。該存儲層使用無結型電晶體,其電阻性記憶組件與選擇電晶體串聯。透過層切晶圓大小之摻雜單晶矽層之方式建設存儲陣列。同時,該3D存儲陣列與下方之多金屬層半導體設備連接起來。 The process can form resistive multilayer or 3D memory arrays without additional masking steps for each memory layer. The storage layer uses a junctionless transistor, and its resistive memory component is connected in series with the selection transistor. The memory array is constructed by layering and dicing doped monocrystalline silicon layers of wafer size. At the same time, the 3D memory array is connected to the underlying multi-metal layer semiconductor device.

具有一般技藝之人可將圖101A至圖101K中提到之例子僅作為典型範例看待,並非按比例縮小。技藝高超之人可考量更多之變化情況。比如,可採用其他類型之電晶體,比如RCAT等。此外,在補償互連電阻時,N+層之摻雜物可能會略微有所不同。或者堆疊式記憶體層可與存儲堆疊層上方之週邊電路連接起來。此外,雙柵極3D電阻性記憶體之每個柵極可獨立控制,以更好地控制存儲晶片。透過閱讀本說明書,可使技藝高超之人想起如何在本發明範圍內對其他地方進行修改。因此,本發明僅受限於附加之權利要求。 Those of ordinary skill may regard the examples mentioned in FIGS. 101A-101K as typical examples only and not to scale. A skilled person can take into account more changes. For example, other types of transistors, such as RCAT, can be used. In addition, the dopant of the N+ layer may vary slightly when compensating for interconnect resistance. Alternatively, the stacked memory layer can be connected to peripheral circuits above the memory stack layer. In addition, each gate of dual-gate 3D resistive memory can be independently controlled to better control the memory chip. A reading of this specification will allow the skilled person to recall how to make modifications elsewhere within the scope of the invention. Accordingly, the invention is limited only by the appended claims.

如圖102A至102L所示,可利用電阻性無附加掩蔽工序在每個存儲層建設3D記憶體。3D記憶體適用於生產3D IC。該3D記憶體使用雙柵控金屬-氧化物半導體場效應電晶體(MOSFET),擁有電阻性記憶組件,與選擇電晶體串聯。 As shown in Figures 102A to 102L, 3D memory can be built in each memory layer using a resistive no additional masking process. 3D memory is suitable for producing 3D IC. The 3D memory uses dual-gated metal-oxide-semiconductor field-effect transistors (MOSFETs) with resistive memory elements in series with select transistors.

如圖102A所示,帶週邊電路10202之矽基板可使用耐 高溫(超過400℃)配線,例如鎢絲。週邊電路基板10202可包含記憶體控制電路以及其他用途之各種電路,例如用於類比、數位、射頻或存儲。週邊電路基板10202可包含週邊電路。這種週邊電路即便在經過附加快速高熱退火(RTA)後仍然可以繼續運行,保持良好之性能。為此,在組建週邊電路時應考量選擇那些只需要輕微RTA或無需RTA之即可開啟摻雜物之週邊電路。週邊電路基板10202之最上面一層可用於將氧化物晶圓和二氧化矽10204之澱積層黏結起來,從而形成受主晶圓10214。 As shown in Figure 102A, the silicon substrate with peripheral circuit 10202 can use High temperature (over 400°C) wiring, such as tungsten wire. The peripheral circuit substrate 10202 may include memory control circuits and various circuits for other purposes, such as for analog, digital, radio frequency or storage. The peripheral circuit substrate 10202 may include peripheral circuits. This peripheral circuit can continue to operate even after additional rapid thermal annealing (RTA), maintaining good performance. For this reason, when constructing peripheral circuits, it should be considered to select those peripheral circuits that can turn on the dopant only with a slight RTA or without RTA. The uppermost layer of the peripheral circuit substrate 10202 can be used to bond the oxide wafer and the deposited layer of silicon dioxide 10204 to form the acceptor wafer 10214 .

如圖102B所示,單晶矽施主晶圓10212可包含晶圓大小之P-摻雜層(未顯示),其中之摻雜物濃度可能與P-基板10206不同。P-摻雜層可透過離子注入和高熱退火方式形成。可在注入之前生長或澱積遮罩氧化層10208,以確保在注入過程中矽免受污染,並為後期晶圓之間之黏結提供氧化層。透過氫離子注入或前文所描述之其他方法可在P-基板10206或P-摻雜層(未顯示)中之施主晶圓10212中形成層轉移分界平面10210(圖中虛線部分)。如前文所述,施主晶圓10212和受主晶圓10214均用於晶圓黏結,在低溫(最好低於400℃,此時應力最低)或中溫(不超過900℃)下在氧化層10204和氧化層10208之表面黏結在一起。 As shown in FIG. 102B , a single crystal silicon donor wafer 10212 may include a wafer-sized P-doped layer (not shown), which may have a different dopant concentration than the P-substrate 10206 . The P-doped layer can be formed by ion implantation and high temperature annealing. A mask oxide layer 10208 may be grown or deposited prior to implantation to ensure silicon contamination during implantation and to provide an oxide layer for later wafer-to-wafer bonding. A layer transfer boundary plane 10210 (dotted line in the figure) can be formed in the donor wafer 10212 in the P-substrate 10206 or in the P-doped layer (not shown) by hydrogen ion implantation or other methods described above. As mentioned above, both the donor wafer 10212 and the acceptor wafer 10214 are used for wafer bonding. 10204 and the surfaces of the oxide layer 10208 are bonded together.

如圖102C所示,可透過切割或打磨或前文所述之工序(例如離子切割或其他方法)將層切分界平面10210上方之P-層部分(未顯示)和P-晶圓基板10206移除,從而形 成剩餘之單晶矽P-層10206。剩餘之P-層10206’和氧化層10208被層切到受主晶圓10214上。可透過化學或機械方式將P-層10206’之最上面一層打磨光滑、平坦。現在電晶體已全部或部分形成,並與受主晶圓10214之對準標誌(未顯示)對齊。氧化層10220可能會澱積,為後期氧化物之間之黏結提供表面。此時,第一層Si/SiO2層10223已形成,包含二氧化矽層10220、P-矽層10206’和氧化層10208。 As shown in FIG. 102C, the portion of the P-layer (not shown) above the dicing interface plane 10210 and the P-wafer substrate 10206 can be removed by dicing or grinding or the processes described above (such as ion cutting or other methods). , thus forming The remaining monocrystalline silicon P-layer 10206 is formed. The remaining P-layer 10206' and oxide layer 10208 are layer diced onto the acceptor wafer 10214. The topmost layer of the P-layer 10206' can be polished smooth and flat by chemical or mechanical means. The transistors are now fully or partially formed and aligned with the alignment marks (not shown) of the acceptor wafer 10214. An oxide layer 10220 may be deposited to provide a surface for later bonding between oxides. At this point, the first Si/SiO2 layer 10223 has been formed, including the silicon dioxide layer 10220, the P-silicon layer 10206' and the oxide layer 10208.

如圖102D所示,可能會額外形成圖102A至圖102C所示之Si/SiO2層,比如第二層Si/SiO2層10225和第三層Si/SiO2層10227。氧化層10229可能會澱積,實現與頂部矽層之間之絕緣。 As shown in FIG. 102D, Si/SiO2 layers shown in FIGS. 102A to 102C may be additionally formed, such as a second Si/SiO2 layer 10225 and a third Si/SiO2 layer 10227. An oxide layer 10229 may be deposited to provide isolation from the top silicon layer.

如圖102E所示,氧化層10229、第三層Si/SiO2層10227、第二層Si/SiO2層10225和第一層Si/SiO2層10223可進行光刻和電漿體/反應式離子蝕刻,形成存儲晶片結構之一部分。存儲晶片結構現在已包含P-矽區10216和氧化層區10222。 As shown in FIG. 102E, the oxide layer 10229, the third Si/SiO2 layer 10227, the second Si/SiO2 layer 10225 and the first Si/SiO2 layer 10223 can be subjected to photolithography and plasma/reactive ion etching, Forms part of a memory wafer structure. The memory chip structure now includes P-silicon region 10216 and oxide layer region 10222 .

如圖102F所示,柵極電介質和柵電極材料可能會澱積,可透過化學-機械打磨(CMP)使其平面化,然後可進行光刻和電漿體/反應式離子蝕刻,以形成柵極電介質10228。柵極電介質10228可能與柵電極10230(如圖所示)自對齊,並被柵電極10230覆蓋,或者可能充分地覆蓋住整個矽/氧化物多層結構。柵極堆疊層(包含柵電極10230和柵極電介質10228)由柵極電介質(例如高熱氧化 層)和柵電極材料(如多晶矽)組成。或者,柵極電介質可選擇與具體之柵極金屬之功函數相匹配之原子層澱積(ALD)材料,符合前文所述之高-k金屬柵極工藝方案之行業標準。此外,柵極電介質可透過快速高熱氧化(RTO)形成。快速熱氧化是矽表面之一種低溫氧化澱積或低溫微波電漿體氧化之過程,最終可澱積成柵電極,例如鎢電極或鋁電極。 As shown in Figure 102F, the gate dielectric and gate electrode material may be deposited, planarized by chemical-mechanical polishing (CMP), and then photolithography and plasma/reactive ion etching may be performed to form the gate electrode. pole dielectric 10228. The gate dielectric 10228 may be self-aligned with and covered by the gate electrode 10230 (as shown), or may substantially cover the entire silicon/oxide multilayer structure. The gate stack layer (comprising gate electrode 10230 and gate dielectric 10228) is made of gate dielectric (e.g. high thermal oxide layer) and gate electrode material (such as polysilicon). Alternatively, the gate dielectric can be selected from an atomic layer deposition (ALD) material that matches the work function of the specific gate metal, in line with the industry standard for high-k metal gate process solutions described above. In addition, the gate dielectric can be formed by rapid thermal oxidation (RTO). Rapid thermal oxidation is a process of low-temperature oxidation deposition or low-temperature microwave plasma oxidation on the surface of silicon, which can eventually be deposited as a gate electrode, such as a tungsten electrode or an aluminum electrode.

如圖102G所示,可透過向P-矽區10216中注入N型離子之方法(例如砷)使N+矽區10226與柵電極10230實現自對齊。P-矽區10216不受到柵電極10230之阻隔。這樣就在柵電極10230阻隔之區域形成了其餘之P-矽區10217(未顯示)。在將N型離子置入每層P-矽區10216中時可採用不同之注入能量或角度或注入倍數。在多步注入過程中可使用柵側壁(未顯示),不同堆疊層中出現之矽層使用之柵側壁寬度可能也不同,用以說明N型離子注入之不同橫向擴散。底層(例如10223)可能比頂層(例如10027)所需之柵側壁更寬。同樣,可使用帶基板旋轉功能之角度離子注入補償不同之注入擴散。頂層注入可能具有一定之傾斜角,與晶圓表面並不垂直,銀耳它將離子置於柵電極10230之邊緣之稍下方,與垂直度更好之較低層之離子注入密切配合。因到達將底層所需之注入能量較高,從而產生擴散效應,較低層之離子注入可將離子置入柵電極10230之稍下方。可進行快速高熱退火(RTA),以便從根本上開啟所有存儲層10223、10225和10227和週邊電路 10202中之摻雜物。或者,可進行光學退火,例如鐳射退火。 As shown in FIG. 102G , the N+ silicon region 10226 and the gate electrode 10230 can be self-aligned by implanting N-type ions (such as arsenic) into the P- silicon region 10216 . The P-silicon region 10216 is not blocked by the gate electrode 10230 . This forms the rest of the P-silicon region 10217 (not shown) in the region blocked by the gate electrode 10230. When implanting N-type ions into each layer of P-silicon region 10216, different implantation energies or angles or implantation multiples can be used. Gate sidewalls (not shown) may be used in a multi-step implantation process, and different gate sidewall widths may be used for silicon layers present in different stacks to account for the different lateral diffusion of N-type ion implantation. The bottom layer (eg, 10223) may have wider gate sidewalls than the top layer (eg, 10027) requires. Likewise, angular ion implantation with substrate rotation can be used to compensate for different implant spreads. The top layer implant may have a certain tilt angle, which is not perpendicular to the wafer surface, and it places the ions slightly below the edge of the gate electrode 10230, which is closely coordinated with the ion implantation of the lower layer with better perpendicularity. Ion implantation of the lower layers can place ions just below the gate electrode 10230 due to the higher implant energy required to reach the lower layers, resulting in a diffusion effect. Rapid thermal anneal (RTA) can be performed to essentially turn on all memory layers 10223, 10225 and 10227 and peripheral circuitry Adulteration in 10202. Alternatively, optical annealing, such as laser annealing, can be performed.

如圖102H所示,間隙填充氧化層10232可覆蓋整個結構,可透過化學-機械打磨(CMP)使其平面化。為清晰起見,圖中氧化層10232顯示為透明層。除此之外,還有文字線區(WL)10250、柵電極10230、源極線路區(SL)10252和所示之N+矽區10226。 As shown in FIG. 102H, a gap-fill oxide layer 10232 may cover the entire structure, which may be planarized by chemical-mechanical polishing (CMP). For clarity, the oxide layer 10232 is shown as a transparent layer in the figure. In addition, there are word line region (WL) 10250, gate electrode 10230, source line region (SL) 10252 and N+ silicon region 10226 as shown.

如圖102I所示,位線(BL)接點10234可透過氧化層10232、三個N+矽區10226和相關之氧化層垂直絕緣區進行光刻和電漿體/反應式離子蝕刻,以便充分與所有之存儲層垂直連接,隨後進行光阻去除。阻變記憶體材料10238,比如二氧化鉿,接下來可能會澱積,最好為原子層澱積(ALD)。阻變記憶體組件之電極接下來可能會被ALD澱積,形成電極/BL接點10234。應對多餘之澱積材料進行打磨,使之與氧化層10232頂部或頂部下方處於同一表面。每個帶有阻變材料10238之BL接點10234可充分與所有存儲層共用,如圖102I中所示之三層存儲層。 As shown in FIG. 102I, the bit line (BL) contact 10234 can be photolithographically and plasma/reactive ion etched through the oxide layer 10232, the three N+ silicon regions 10226 and the associated oxide layer vertical isolation regions in order to fully communicate with the All memory layers are connected vertically, followed by photoresist removal. The resistive memory material 10238, such as hafnium dioxide, may then be deposited, preferably by atomic layer deposition (ALD). The electrodes of the RRAM device may then be deposited by ALD to form the electrode/BL contact 10234 . Excess deposited material should be polished so that it is on the same surface as or below the top of the oxide layer 10232 . Each BL contact 10234 with resistive material 10238 can be fully shared with all storage layers, such as the three storage layers shown in FIG. 102I.

如圖102J所示,可形成BL金屬線10236,並與相關之帶有阻變材料10238之BL接點10234連接在一起。在存儲陣列邊緣可形成WL和SL之接點和相關之金屬佈線(未顯示)。可能會形成穿層過孔10260(未顯示),透過受主晶圓金屬連接焊盤10214(未顯示)使BL、SL和WL之金屬化區域與受主基板10280週邊電路發生電耦合。 As shown in FIG. 102J , a BL metal line 10236 can be formed and connected to a related BL contact 10234 with a resistive material 10238 . Contacts for WL and SL and associated metal wiring (not shown) may be formed at the edge of the memory array. Through-layer vias 10260 (not shown) may be formed to electrically couple the metallized areas of BL, SL and WL to peripheral circuitry of the acceptor substrate 10280 through acceptor wafer metal connection pads 10214 (not shown).

圖102K之橫截面剖視圖二見圖102K1,圖102K之橫截 面剖視圖三見圖102K2。圖102K1顯示了BL金屬線10236、氧化層10232、BL接點/電極10234、阻變材料10238、WL區10250、柵極電介質10228、P-矽區10217、N+矽區10226和週邊電路基板10202。BL接點/電極10234與阻變材料10238之三個水平面之其中一個邊相連。阻變材料10238之另外一邊與N+矽區10226相連。如圖102K2所示,P-區10217和每個邊上之相應N+區10226形成了選擇電晶體之源極、汲極和溝槽。BL金屬線10236、氧化層10232、柵電極10230、柵極電介質10228、P-矽區10217、夾層氧化區(OX)和週邊電路基板10202見圖102K2。柵電極10230在六個P-矽區10217中都很常見,它們控制著六個雙柵控MOSFET選擇電晶體。 The second cross-sectional view of Figure 102K is shown in Figure 102K1, the cross-section of Figure 102K Section 3 is shown in Figure 102K2. Figure 102K1 shows BL metal line 10236, oxide layer 10232, BL contact/electrode 10234, resistive switch material 10238, WL region 10250, gate dielectric 10228, P- silicon region 10217, N+ silicon region 10226 and peripheral circuit substrate 10202. The BL contact/electrode 10234 is connected to one of the three horizontal planes of the resistive material 10238 . The other side of the resistive material 10238 is connected to the N+ silicon region 10226 . As shown in Figure 102K2, the P- region 10217 and the corresponding N+ region 10226 on each side form the source, drain and trench of the select transistor. BL metal line 10236, oxide layer 10232, gate electrode 10230, gate dielectric 10228, P-silicon region 10217, interlayer oxide region (OX) and peripheral circuit substrate 10202 are shown in FIG. 102K2. Gate electrodes 10230 are common to the six P-silicon regions 10217, and they control the six dual-gated MOSFET select transistors.

如圖102L所示,在第一層Si/SiO2層10223上典型之雙柵控MOSFET選擇電晶體可能包含P-矽區10217(起到電晶體溝槽之作用)、N+矽區10226(起到源極和汲極之作用)和兩個柵電極10230(帶相應之柵極電介質10228)。電晶體藉由氧化層10208可與下方絕緣。 As shown in FIG. 102L, a typical dual-gated MOSFET selection transistor on the first Si/SiO2 layer 10223 may include a P-silicon region 10217 (acting as a transistor trench), an N+ silicon region 10226 (acting as source and drain) and two gate electrodes 10230 (with corresponding gate dielectrics 10228). The transistors are insulated from below by the oxide layer 10208 .

該流程可形成電阻性3D記憶體,每個存儲層不使用附加掩蔽工序。透過層切晶圓大小之摻雜單晶矽層之方式建設3D記憶體。同時,該3D記憶體與下方之多金屬層半導體設備連接起來。 The process forms resistive 3D memory without additional masking steps for each memory layer. 3D memory is constructed by layering wafer-sized doped monocrystalline silicon layers. At the same time, the 3D memory is connected to the underlying multi-metal layer semiconductor device.

具有一般技藝之人可將圖102A至圖102L中提到之例子僅作為典型範例看待,並非按比例縮小。技藝高超之人可考量更多變化情況。比如,可採用其他類型之電晶體, 比如RCAT等。MOSFET選擇組件在溝槽工程中可利用略微摻雜之汲極和halo注入法。或者接點可使用摻雜多晶矽或其他導電材料。或者堆疊式記憶體層可與存儲堆疊層上方之週邊電路連接起來。此外,雙柵極3D DRAM之每個柵極可獨立控制,以更好地控制存儲晶片。透過閱讀本說明書,可使技藝高超之人想起如何在本發明範圍內對其他地方進行修改。因此,本發明僅受限於附加之權利要求。 One of ordinary skill would consider the examples mentioned in FIGS. 102A-102L to be representative examples only and not to scale. A skilled person can consider many more variations. For example, other types of transistors can be used, Such as RCAT and so on. MOSFET option devices can utilize lightly doped drain and halo implants in trench engineering. Alternatively, doped polysilicon or other conductive materials can be used for the contacts. Alternatively, the stacked memory layer can be connected to peripheral circuits above the memory stack layer. In addition, each gate of dual-gate 3D DRAM can be independently controlled to better control the memory chip. A reading of this specification will allow the skilled person to recall how to make modifications elsewhere within the scope of the invention. Accordingly, the invention is limited only by the appended claims.

如圖103A至103M所示,可利用電阻性在每個存儲層建設帶一個附加掩蔽工序3D記憶體。3D記憶體適用於生產3D IC。該3D記憶體使用雙柵控MOSFET選擇電晶體,擁有電阻性記憶組件,與選擇電晶體串聯。 As shown in FIGS. 103A to 103M , resistivity can be used to build 3D memory with an additional masking process at each memory layer. 3D memory is suitable for producing 3D IC. The 3D memory uses a dual-gate MOSFET selection transistor with a resistive memory element connected in series with the selection transistor.

如圖103A所示,帶週邊電路10302之矽基板可使用耐高溫(超過400℃)配線,例如鎢絲。週邊電路基板10302可包含記憶體控制電路以及其他用途之各種電路,例如用於類比、數位、射頻或存儲。週邊電路基板10302可包含電路。這種電路即便在經過附加快速高熱退火(RTA)後仍然可以繼續運行,保持良好之性能。為此,在組建週邊電路時應考量選擇那些只需要輕微RTA或無需RTA之即可開啟摻雜物之週邊電路。週邊電路基板10302之最上面一層可用於將氧化物晶圓和二氧化矽10304之澱積層黏結起來,從而形成受主晶圓2414。 As shown in FIG. 103A , the silicon substrate with the peripheral circuit 10302 can use high temperature resistant (over 400° C.) wiring, such as tungsten wire. The peripheral circuit substrate 10302 may include memory control circuits and various circuits for other purposes, such as for analog, digital, radio frequency or storage. The peripheral circuit substrate 10302 may contain circuits. This circuit can continue to operate and maintain good performance even after additional rapid thermal annealing (RTA). For this reason, when constructing peripheral circuits, it should be considered to select those peripheral circuits that can turn on the dopant only with a slight RTA or without RTA. The uppermost layer of the peripheral circuit substrate 10302 can be used to bond the oxide wafer and the deposited layer of silicon dioxide 10304 to form the acceptor wafer 2414 .

如圖103B所示,單晶矽施主晶圓10312可包含晶圓大小之P-摻雜層(未顯示),其中之摻雜物濃度可能與P-基板10306不同。P-摻雜層可透過離子注入和高熱退火方式 形成。可在注入之前生長或澱積遮罩氧化層10308,以確保在注入過程中矽免受污染,並為後期晶圓之間之黏結提供氧化層。透過氫離子注入或前文所描述之其他方法可在P-基板10310或P-摻雜層(未顯示)中之施主晶圓10312中形成層轉移分界平面10306(圖中虛線部分)。如前文所述,施主晶圓10312和受主晶圓10314均用於晶圓黏結,在低溫(最好低於400℃,此時應力最低)或中溫(不超過900℃)下在氧化層10304和氧化層10308之表面黏結在一起。 As shown in FIG. 103B , a single crystal silicon donor wafer 10312 may include a wafer-sized P-doped layer (not shown), which may have a different dopant concentration than the P-substrate 10306 . P-doped layer can be through ion implantation and high temperature annealing method form. A mask oxide layer 10308 may be grown or deposited prior to implantation to ensure that the silicon is free from contamination during the implantation process and to provide an oxide layer for later wafer-to-wafer bonding. A layer transfer boundary plane 10306 (dotted line in the figure) can be formed in the donor wafer 10312 in the P-substrate 10310 or P-doped layer (not shown) by hydrogen ion implantation or other methods described above. As mentioned above, both the donor wafer 10312 and the acceptor wafer 10314 are used for wafer bonding. 10304 and the surfaces of the oxide layer 10308 are bonded together.

如圖103C所示,可透過切割或打磨或前文所述之工序(例如離子切割或其他之方法)將層切分界平面10310上方之P-層部分(未顯示)和P-晶圓基板10306移除,從而形成剩餘之單晶矽P-層10306。剩餘之P-層10306’和氧化層10308被層切到受主晶圓10314上。可透過化學或機械方式將P-層10306’之最上面一層打磨光滑、平坦。現在電晶體已全部或部分形成,並與受主晶圓10314之對準標誌(未顯示)對齊。 As shown in FIG. 103C, the portion of the P-layer (not shown) above the dicing interface plane 10310 and the P-wafer substrate 10306 can be removed by dicing or grinding or the processes described above (such as ion cutting or other methods). removal, thereby forming the remaining single crystal silicon P-layer 10306. The remaining P-layer 10306' and oxide layer 10308 are layer diced onto the acceptor wafer 10314. The topmost layer of the P-layer 10306' can be polished smooth and flat by chemical or mechanical means. The transistors are now fully or partially formed and aligned with the alignment marks (not shown) of the acceptor wafer 10314.

如圖103D所示,N+矽區10316可進行光刻該次注入還可以形成其餘之P-矽區10318。 As shown in FIG. 103D, the N+ silicon region 10316 can be photolithographically implanted and the rest of the P- silicon region 10318 can be formed.

如圖103E所示,氧化層10320可能會澱積,以便為後期之氧化物與氧化物之間之黏結準備好必要之表面,這樣就形成了第一層Si/SiO2層10323。Si/SiO2層包含二氧化矽層10320、N+矽區域10316和P-矽區域10318。 As shown in Figure 103E, an oxide layer 10320 may be deposited to prepare the necessary surface for later oxide-to-oxide bonding, thus forming a first Si/SiO2 layer 10323. The Si/SiO2 layer includes a silicon dioxide layer 10320 , an N+ silicon region 10316 and a P− silicon region 10318 .

如圖103F所示,可能會額外形成圖103A至圖103E所 示之Si/SiO2層,比如第二層Si/SiO2層10325和第三層Si/SiO2層10327。氧化層10329可能會澱積。所有預期之存儲層都建設好之後,可進行快速高熱退火(RTA),以便從根本上開啟所有存儲層10323、10325和10327和週邊電路10302中之摻雜物。或者,可進行光學退火,例如鐳射退火。 As shown in Figure 103F, it may additionally form the Si/SiO2 layers are shown, such as the second Si/SiO2 layer 10325 and the third Si/SiO2 layer 10327. An oxide layer 10329 may be deposited. After all desired memory layers are built, a rapid thermal anneal (RTA) can be performed to essentially turn on dopants in all memory layers 10323, 10325, and 10327 and peripheral circuitry 10302. Alternatively, optical annealing, such as laser annealing, can be performed.

如圖103G所示,氧化層10329、第三層Si/SiO2層10327、第二層Si/SiO2層10325和第一層Si/SiO2層10323可進行光刻和電漿體/反應式離子蝕刻,形成存儲晶片結構之一部分。蝕刻可能會形成P-矽區10318’(該區形成電晶體溝槽)和N+矽區10316’(形成源極、汲極和本地源極線路)。 As shown in Figure 103G, the oxide layer 10329, the third Si/SiO2 layer 10327, the second Si/SiO2 layer 10325 and the first Si/SiO2 layer 10323 can be photolithographically and plasma/reactive ion etched, Forms part of a memory wafer structure. Etching may form P- silicon regions 10318' (which form the transistor trenches) and N+ silicon regions 10316' (which form source, drain and local source lines).

如圖103H所示,柵極電介質和柵電極材料可能會澱積,可透過化學-機械打磨(CMP)使其平面化,然後可進行光刻和電漿體/反應式離子蝕刻,以形成柵極電介質10328。柵極電介質10328可能與柵電極10330(如圖所示)自對齊,並被柵電極10330覆蓋,或者可能充分地覆蓋住整個矽/氧化物多層結構。柵電極10330和柵極電介質10328柵極堆疊層之尺寸和對齊方式應確保可充分徹底地覆蓋住P-矽區10318’。柵極堆疊層(包含柵電極10330和柵極電介質10328)由柵極電介質(例如高熱氧化層)和柵電極材料(如多晶矽)組成。或者,柵極電介質可選擇與具體之柵極金屬之功函數相匹配之原子層澱積(ALD)材料,符合前文所述之高-k金屬柵極工藝方案之行業標 準。此外,柵極電介質可透過快速高熱氧化(RTO)形成。快速高熱氧化是矽表面之一種低溫氧化澱積或低溫微波電漿體氧化之過程,最終可澱積成柵電極,例如鎢電極或鋁電極。 As shown in Figure 103H, the gate dielectric and gate electrode material may be deposited, planarized by chemical-mechanical polishing (CMP), and then photolithography and plasma/reactive ion etching may be performed to form the gate electrode. pole dielectric 10328. The gate dielectric 10328 may be self-aligned with and covered by the gate electrode 10330 (as shown), or may substantially cover the entire silicon/oxide multilayer structure. The size and alignment of the gate electrode 10330 and the gate dielectric 10328 gate stack layer should ensure sufficient and complete coverage of the P-silicon region 10318'. The gate stack layer (comprising gate electrode 10330 and gate dielectric 10328) consists of a gate dielectric (eg, high thermal oxide) and a gate electrode material (eg, polysilicon). Alternatively, the gate dielectric can be selected from an atomic layer deposition (ALD) material that matches the work function of the specific gate metal, which is in line with the industry standard for the high-k metal gate process scheme mentioned above. allow. In addition, the gate dielectric can be formed by rapid thermal oxidation (RTO). Rapid high thermal oxidation is a process of low-temperature oxidation deposition or low-temperature microwave plasma oxidation on the surface of silicon, which can eventually be deposited as a gate electrode, such as a tungsten electrode or an aluminum electrode.

如圖103I所示,間隙填充氧化層10332可覆蓋整個結構,可透過化學-機械打磨(CMP)使其平面化。為清晰起見,圖中氧化層10332顯示為透明層。除此之外,還有文字線區(WL)10350、柵電極10330、源極線路區(SL)10352和所示之N+矽區10316。 As shown in Figure 103I, a gap-fill oxide layer 10332 may cover the entire structure, which may be planarized by chemical-mechanical polishing (CMP). For clarity, the oxide layer 10332 is shown as a transparent layer in the figure. In addition, there are word line region (WL) 10350, gate electrode 10330, source line region (SL) 10352 and N+ silicon region 10316 as shown.

如圖103J所示,位線(BL)接點10334可透過氧化層10332、三個N+矽區10316’和相關之氧化層垂直絕緣區進行光刻和電漿體/反應式離子蝕刻,以便與所有之存儲層垂直連接。BL接點10334透過光阻去除之方法進行處理。阻變記憶體材料10338,比如二氧化鉿,接下來可能會澱積,最好為原子層澱積(ALD)。阻變記憶體組件之電極接下來可能會被ALD澱積,形成電極/BL接點10334。應對多餘之澱積材料進行打磨,使之與氧化層10332頂部或頂部下方處於同一表面。每個帶有阻變材料10338之BL接點/電極10334可充分與所有之存儲層共用,如圖103J中所示之三層存儲層。 As shown in FIG. 103J, the bit line (BL) contact 10334 can be photolithographically and plasma/reactive ion etched through the oxide layer 10332, the three N+ silicon regions 10316' and the associated oxide layer vertical isolation regions in order to communicate with All storage layers are connected vertically. BL contact 10334 is processed by photoresist stripping. The resistive memory material 10338, such as hafnium dioxide, may then be deposited, preferably by atomic layer deposition (ALD). The electrodes of the RRAM device may then be deposited by ALD to form electrode/BL contacts 10334 . Excess deposited material should be polished so that it is on the same surface as or below the top of the oxide layer 10332. Each BL contact/electrode 10334 with resistive material 10338 can be fully shared with all storage layers, such as the three storage layers shown in FIG. 103J.

如圖103K所示,可形成BL金屬線10336,並與相關之帶有阻變材料10338之BL接點10334連接在一起。在存儲陣列邊緣可形成WL和SL之接點和相關之金屬佈線(未顯示)。可能會形成穿層過孔10360(未顯示),透過受主 晶圓金屬連接焊盤10380(未顯示)使BL、SL和WL之金屬化區域與受主基板10314週邊電路發生電耦合。 As shown in FIG. 103K, a BL metal line 10336 can be formed and connected to the associated BL contact 10334 with a resistive material 10338. Contacts for WL and SL and associated metal wiring (not shown) may be formed at the edge of the memory array. Through-layer vias 10360 (not shown) may be formed through the acceptor Wafer metal connection pads 10380 (not shown) electrically couple the metallized areas of BL, SL, and WL to the receiver substrate 10314 peripheral circuitry.

圖103L之橫截面剖視圖二見圖103L1,圖103L之橫截面剖視圖三見圖103L2。圖103L2顯示了BL金屬線10336、氧化層10332、BL接點/電極10334、阻變材料10338、WL區10350、柵極電介質10328、P-矽區10318’、N+矽區10316’和週邊電路基板10302。BL接點/電極10334與阻變材料10338之三個水平面之其中一個邊相連。阻變材料10338之另外一邊與N+矽區10316’相連。如圖103L2所示,P-區10318’和每個邊上之相應N+區10316’形成了選擇電晶體之源極、汲極和溝槽。BL金屬線10336、氧化層10332、柵電極10330、柵極電介質10328、P-矽區10318’、夾層氧化區(OX)和週邊電路基板10302見圖103L2。柵電極10330在六個P-矽區10318’中都很常見,它們控制著六個雙柵控MOSFET選擇電晶體。 The second cross-sectional view of Figure 103L is shown in Figure 103L1, and the third cross-sectional view of Figure 103L is shown in Figure 103L2. Figure 103L2 shows BL metal line 10336, oxide layer 10332, BL contact/electrode 10334, resistive switch material 10338, WL region 10350, gate dielectric 10328, P- silicon region 10318', N+ silicon region 10316' and surrounding circuit substrate 10302. The BL contact/electrode 10334 is connected to one of the three horizontal planes of the resistive material 10338 . The other side of the resistive material 10338 is connected to the N+ silicon region 10316'. As shown in Figure 103L2, the P- region 10318' and the corresponding N+ region 10316' on each side form the source, drain and trench of the select transistor. BL metal line 10336, oxide layer 10332, gate electrode 10330, gate dielectric 10328, P-silicon region 10318', interlayer oxide region (OX) and peripheral circuit substrate 10302 are shown in Figure 103L2. Gate electrodes 10330 are common to the six P-silicon regions 10318', which control the six dual-gated MOSFET select transistors.

如圖103L所示,在第一層Si/SiO2層10323上典型之雙柵控MOSFET選擇電晶體可能包含P-矽區10318(起到電晶體溝槽之作用)、N+矽區10316(起到源極和汲極之作用)和兩個柵電極10330(帶相應之柵極電介質10328)。電晶體藉由氧化層10308可與下方絕緣。 As shown in FIG. 103L, a typical dual-gated MOSFET select transistor on the first Si/SiO2 layer 10323 may include a P-silicon region 10318 (acting as a transistor trench), an N+ silicon region 10316 (acting as source and drain) and two gate electrodes 10330 (with corresponding gate dielectrics 10328). The transistors are insulated from below by the oxide layer 10308 .

該流程可形成電阻性3D記憶體,每個存儲層使用一個附加掩蔽工序。透過層切晶圓大小之摻雜單晶矽層之方式建設電阻性3D記憶體。同時,該3D記憶體與下方之多金屬層半導體設備連接起來。 The process forms resistive 3D memory, using an additional masking process for each memory layer. Resistive 3D memory is built by layering wafer-sized doped single-crystal silicon layers. At the same time, the 3D memory is connected to the underlying multi-metal layer semiconductor device.

具有一般技藝之人可將圖103A至圖103M中提到之例子僅作為典型範例看待,並非按比例縮小。技藝高超之人可考量更多變化情況。比如,可採用其他類型之電晶體,比如RCAT等。或者接點可使用摻雜多晶矽或其他導電材料。或者堆疊式記憶體層可與存儲堆疊層上方之週邊電路連接起來。或者,只要利用鐳射退火系統完成相關之注入程式,Si/SiO2層10322、10324和10326可逐層退火。透過閱讀本說明書,可使技藝高超之人想起如何在本發明範圍內對其他地方進行修改。因此,本發明僅受限於附加之權利要求。 Those of ordinary skill may consider the examples mentioned in FIGS. 103A-103M to be representative examples only and not to scale. A skilled person can consider more variations. For example, other types of transistors, such as RCAT, can be used. Alternatively, doped polysilicon or other conductive materials can be used for the contacts. Alternatively, the stacked memory layer can be connected to peripheral circuits above the memory stack layer. Alternatively, the Si/SiO2 layers 10322, 10324 and 10326 can be annealed layer by layer as long as the relevant implantation procedures are completed by using a laser annealing system. A reading of this specification will allow the skilled person to recall how to make modifications elsewhere within the scope of the invention. Accordingly, the invention is limited only by the appended claims.

如圖104A至104F所示,可建設在每個存儲層帶兩個附加掩蔽工序電阻性3D記憶體。3D記憶體適用於生產3D IC。該3D記憶體使用單柵極MOSFET選擇電晶體,擁有電阻性記憶組件,與選擇電晶體串聯。 As shown in Figures 104A to 104F, resistive 3D memories can be built with two additional masking steps per memory layer. 3D memory is suitable for producing 3D IC. The 3D memory uses a single-gate MOSFET select transistor with a resistive memory element in series with the select transistor.

如圖104A所示,P-基板施主晶圓10400經加工可包含晶圓大小之P-摻雜層10404。P-摻雜層10404之摻雜物濃度可能與P-基板10400相同,也有可能不同。P-摻雜層10404可透過離子注入和高熱退火之方式形成。可在注入之前生長遮罩氧化層10401,以確保在注入過程中矽免受污染,並為後期晶圓之間之黏結提供氧化層。 As shown in Figure 104A, a P-substrate donor wafer 10400 is processed to include a wafer-sized P-doped layer 10404. The dopant concentration of the P-doped layer 10404 may be the same as that of the P-substrate 10400, or it may be different. The P-doped layer 10404 can be formed by ion implantation and high thermal annealing. A mask oxide layer 10401 can be grown prior to implantation to ensure that the silicon is free from contamination during implantation and to provide an oxide layer for later wafer-to-wafer bonding.

如圖104B所示,施主晶圓10400之頂層可用於將氧化物晶圓和氧化層10402之澱積層黏結起來,或透過P-層10404之高熱氧化,或注入遮罩氧化層10401之二次氧化形成氧化層10402。透過氫離子注入10407或前文所描述之其 他方法可在施主晶圓10400或P-層10404(如圖所示)中形成層轉移分界平面10499(圖中虛線部分)。如前文所述,施主晶圓10400和受主晶圓10410均可用作晶圓之間之黏結,然後二者再黏結起來。上述黏結最好在低溫(不超過400℃)下進行,以將應力控制在最低平。可透過切割或打磨或前文所述之工序(例如離子切割或其他之方法)將層轉移分界平面10499上方之P-層部分和P-施主晶圓基板10400移除。 As shown in Figure 104B, the top layer of the donor wafer 10400 can be used to bond the oxide wafer to the deposited layer of the oxide layer 10402, either through high thermal oxidation of the P- layer 10404, or secondary oxidation of the implanted mask oxide layer 10401 An oxide layer 10402 is formed. By implanting hydrogen ions into 10407 or other Other methods can form a layer transfer boundary plane 10499 (dotted line in the figure) in the donor wafer 10400 or the P-layer 10404 (as shown). As previously described, both the donor wafer 10400 and the acceptor wafer 10410 can be used as a bond between the wafers, and then the two are bonded together. The above-mentioned bonding is best carried out at low temperature (not exceeding 400°C) to keep the stress at the lowest level. Portions of the P-layer above the layer-transfer interface plane 10499 and the P-donor wafer substrate 10400 may be removed by dicing or grinding or the processes described above, such as ion dicing or other methods.

如圖104C所示,剩餘之P-摻雜10404’和氧化層10402已被層切到受主晶圓10410上。受主晶圓10410可包含電路。這種電路即便在經過附加快速高熱退火(RTA)後仍然可以繼續運行,保持良好性能。為此,在組建週邊電路時應考量選擇那些只需要輕微RTA或無需RTA之即可開啟摻雜物之週邊電路。另外,週邊電路可使用耐火金屬,例如耐高溫能力超過400℃之鎢。可透過化學或機械方式將P-摻雜層10404’之最上面一層打磨光滑、平坦。現在電晶體已形成,並與受主晶圓10410之對準標誌(未顯示)對齊。 The remaining P-doping 10404&apos; and oxide layer 10402 have been layered onto the acceptor wafer 10410 as shown in Figure 104C. The acceptor wafer 10410 may contain circuitry. This circuit can continue to operate and maintain good performance even after additional rapid thermal annealing (RTA). For this reason, when constructing peripheral circuits, it should be considered to select those peripheral circuits that can turn on the dopant only with a slight RTA or without RTA. In addition, the peripheral circuits can use refractory metals, such as tungsten with high temperature resistance over 400°C. The uppermost layer of the P-doped layer 10404' can be polished smooth and flat by chemical or mechanical means. The transistors are now formed and aligned with the alignment marks (not shown) of the acceptor wafer 10410 .

如圖104D所示,淺槽絕緣層(STI)氧化區(未顯示)可進行光刻和電漿體/反應式離子蝕刻,直至氧化層10402之頂層,從而移除P-單晶矽層區10404。間隙填充氧化層可能會澱積並透過化學-機械打磨(CMP)之方式使之平坦化,形成傳統之STI氧化區和P-摻雜單晶矽區(未顯示),從而形成電晶體。也可以同時進行或不進行閾值 調整注入。柵極堆疊層由柵極電介質(例如高熱氧化層)和柵電極材料(如多晶矽)組成。或者,柵極氧化層可選擇與具體之柵極金屬之功函數相匹配之原子層澱積(ALD)柵極電介質,符合前文所述之高-k金屬柵極工藝方案之行業標準。此外,柵極氧化區可透過快速高熱氧化(RTO)形成。快速熱氧化是矽表面之一種低溫氧化澱積或低溫微波電漿體氧化之過程,最終可澱積成柵極材料,例如鎢或鋁。此時可進行柵極堆疊層自對齊LDD(輕摻雜汲極)和halo擊穿注入,以調整接頭和電晶體之擊穿特徵。可進行氧化物和氮化物之傳統柵側壁澱積並接著進行深蝕刻,以在柵極堆疊層10424上形成注入便宜柵側壁(未顯示)。接著可進行自對齊N+源極和汲極注入,以產生電晶體源極和汲極10420和其餘之P-矽NMOS(N溝道金屬-氧化物-半導體)電晶體溝槽10428。此時,要開啟注入離子、設定初始接頭深度,是否進行高溫退火均可。最後,間隙填充氧化層10450可覆蓋整個結構,可透過化學-機械打磨(CMP)使其平面化。如前文所述,氧化表面可用於氧化物與氧化晶圓之間之黏結。 As shown in Figure 104D, the shallow trench insulator (STI) oxide region (not shown) can be subjected to photolithography and plasma/reactive ion etching up to the top layer of the oxide layer 10402 to remove the P-monocrystalline silicon layer region 10404. A gap-fill oxide may be deposited and planarized by chemical-mechanical polishing (CMP) to form conventional STI oxide regions and P-doped monocrystalline silicon regions (not shown) to form transistors. Also with or without thresholding Adjust injection. The gate stack consists of a gate dielectric (such as a high thermal oxide layer) and a gate electrode material (such as polysilicon). Alternatively, the gate oxide layer can be an atomic layer deposition (ALD) gate dielectric that matches the work function of the specific gate metal, which is in line with the industry standard for high-k metal gate process solutions described above. In addition, gate oxide can be formed by rapid thermal oxidation (RTO). Rapid thermal oxidation is a low-temperature oxidation deposition or low-temperature microwave plasma oxidation process on the silicon surface, and finally gate materials such as tungsten or aluminum can be deposited. At this time, gate stack self-alignment LDD (Lightly Doped Drain) and halo breakdown implantation can be performed to adjust the breakdown characteristics of contacts and transistors. Conventional gate sidewall deposition of oxide and nitride followed by etch back can be performed to form implanted inexpensive gate sidewalls (not shown) on the gate stack layer 10424 . Self-aligned N+ source and drain implants can then be performed to create transistor source and drain 10420 and remaining P-silicon NMOS (N-channel metal-oxide-semiconductor) transistor trenches 10428 . At this time, it is necessary to start implanting ions, set the initial joint depth, and whether to perform high-temperature annealing. Finally, a gap-fill oxide layer 10450 may cover the entire structure, which may be planarized by chemical-mechanical polishing (CMP). As mentioned above, the oxide surface can be used for bonding between the oxide and the oxide wafer.

如圖104E所示,重複圖104A至104D中描述之電晶體層形成、受主晶圓10410與氧化層10450黏結以及隨後之電晶體形成過程,可形成記憶體電晶體第二層10430。所有預期之存儲層都建設好之後,可進行快速高熱退火(RTA),以便從根本上開啟所有存儲層和受主基板10410週邊電路中之摻雜物。或者,可進行光學退火,例 如鐳射退火。 As shown in FIG. 104E , repeating the transistor layer formation described in FIGS. 104A to 104D , the bonding of the acceptor wafer 10410 and the oxide layer 10450 , and the subsequent transistor formation process, can form the memory transistor second layer 10430 . After all desired memory layers are built, a rapid thermal anneal (RTA) can be performed to essentially turn on all memory layers and dopants in peripheral circuits of the acceptor substrate 10410. Alternatively, optical annealing can be performed, e.g. Such as laser annealing.

如圖104F,可透過光刻和電漿體/反應式離子蝕刻可形成接點和金屬佈線。位元線(BL)接點10440透過電力方式與電晶體汲極側10454上之存儲層電晶體N+區連接起來,而源極線路接點10442與電晶體源極側10452上之存儲層電晶體N+區發生電耦合。位線(BL)配線10448和源極線路(SL)配線10446分別與位線10440和源極線路接點10442發生電耦合。柵極堆疊層,例如10434,可與接點和金屬化區域(未顯示)連接起來,形成文字線區(WL)。可能會形成穿層過孔10460(未顯示),透過受主晶圓金屬連接焊盤1980(未顯示)使BL、SL和WL之金屬化區域與受主基板10410週邊電路發生電耦合。 Contacts and metal wiring can be formed by photolithography and plasma/reactive ion etching as shown in FIG. 104F. The bit line (BL) contact 10440 is electrically connected to the N+ region of the storage layer transistor on the drain side 10454 of the transistor, and the source line contact 10442 is connected to the storage layer transistor on the source side 10452 of the transistor The N+ region is electrically coupled. Bit line (BL) wiring 10448 and source line (SL) wiring 10446 are electrically coupled to bit line 10440 and source line contact 10442 , respectively. A gate stack layer, such as 10434, may be connected with contacts and metallization regions (not shown) to form word line regions (WL). Through-layer vias 10460 (not shown) may be formed to electrically couple the metallized areas of BL, SL and WL to peripheral circuitry of the acceptor substrate 10410 through acceptor wafer metal connection pads 1980 (not shown).

如圖104F所示,源極線路(SL)接點10434可透過每個存儲層之氧化層10450、N+矽區10420和相關之氧化層垂直絕緣區進行光刻和電漿體/反應式離子蝕刻,以便與所有之存儲層垂直連接。SL接點可透過光阻去除之方法進行處理。阻變記憶體材料10442,比如二氧化鉿,接下來可能會澱積,最好為原子層澱積(ALD)。阻變記憶體組件之電極接下來可能會被ALD澱積,形成SL電極/接點10434。應對多餘之澱積材料進行打磨,使之與氧化層10450頂部或頂部下方處於同一表面。每個帶有阻變材料10442之SL接點/電極10434可充分與所有之存儲層共用,如圖104F中所示之三層存儲層。SL接點10434與電晶體源極側10452上之存儲層電晶體N+區發生電耦合。可形成SL 金屬線10446,並利用阻變材料10442將其與相關之SL接點10434連接起來。氧化層10452可能會澱積,並被平面化。位元線(BL)接點10440可透過每個存儲層之氧化層10450、N+矽區10420和相關之氧化層垂直絕緣區進行光刻和電漿體/反應式離子蝕刻,以便充分與所有之存儲層垂直連接。BL接點10440透過光阻去除之方法進行處理。BL接點10440與電晶體汲極側10454上之存儲層電晶體N+區發生電耦合。可形成BL金屬線路10448,並將其與相關之BL接點10440連接起來。柵極堆疊層,例如10424,可與接點和金屬化區域(未顯示)連接起來,形成文字線區(WL)。可能會形成穿層過孔10460(未顯示),透過受主晶圓金屬連接焊盤10480(未顯示)使BL、SL和WL之金屬化區域與受主基板10410週邊電路發生電耦合。 As shown in Figure 104F, source line (SL) contact 10434 can be photolithographically and plasma/reactive ion etched through the oxide layer 10450, N+ silicon region 10420 and associated oxide vertical isolation regions of each storage layer , so as to be vertically connected to all storage layers. SL contacts can be processed by photoresist removal. The resistive memory material 10442, such as hafnium dioxide, may then be deposited, preferably by atomic layer deposition (ALD). The electrodes of the RRAM device may then be deposited by ALD to form SL electrodes/contacts 10434 . Excess deposited material should be polished so that it is on the same surface as or below the top of the oxide layer 10450. Each SL contact/electrode 10434 with resistive switching material 10442 can be fully shared with all memory layers, such as the three memory layers shown in FIG. 104F. The SL contact 10434 is electrically coupled to the storage layer transistor N+ region on the source side 10452 of the transistor. can form SL The metal wire 10446 is connected with the relevant SL contact 10434 by using the resistive material 10442. An oxide layer 10452 may be deposited and planarized. Bit line (BL) contacts 10440 can be photolithographically and plasma/reactive ion etched through the oxide layer 10450, N+ silicon region 10420 and associated oxide layer vertical isolation regions of each memory layer to fully communicate with all The storage layer is connected vertically. BL contact 10440 is processed by photoresist stripping. The BL contact 10440 is electrically coupled to the N+ region of the storage layer transistor on the drain side 10454 of the transistor. BL metal lines 10448 can be formed and connected to associated BL contacts 10440 . A gate stack layer, such as 10424, may be connected with contacts and metallization regions (not shown) to form word line regions (WL). Through-layer vias 10460 (not shown) may be formed to electrically couple the metallized areas of BL, SL and WL to peripheral circuitry of the acceptor substrate 10410 through acceptor wafer metal connection pads 10480 (not shown).

該流程可形成電阻性3D記憶體,每個存儲層使用兩個附加掩蔽工序。透過層切晶圓大小之摻雜單晶矽層之方式建設3D記憶體。同時,該3D記憶體與下方之多金屬層半導體設備連接起來。 The process forms resistive 3D memory using two additional masking steps per memory layer. 3D memory is constructed by layering wafer-sized doped monocrystalline silicon layers. At the same time, the 3D memory is connected to the underlying multi-metal layer semiconductor device.

具有一般技藝之人可將圖104A至圖104F中提到之例子僅作為典型範例看待,並非按比例縮小。技藝高超之人可考量更多變化情況。比如,可採用其他類型之電晶體,比如PMOS(P溝道金屬氧化物半導體)或RCAT等。或者堆疊式記憶體層可與存儲堆疊層上方之週邊電路連接起來。此外,每層存儲層可配置略微不同之施主晶圓P-層摻雜分佈圖。另外,記憶體可以採取不同佈局方式,例如 BL和SL互換,或者在埋設配線之地方,存儲陣列之配線可置於存儲層下方、週邊電路上方。透過閱讀本說明書,可使技藝高超之人想起如何在本發明範圍內對其他地方進行修改。因此,本發明僅受限於附加之權利要求。 One of ordinary skill would consider the examples mentioned in FIGS. 104A-104F to be representative examples only and not to scale. A skilled person can consider more variations. For example, other types of transistors, such as PMOS (P-channel Metal Oxide Semiconductor) or RCAT, can be used. Alternatively, the stacked memory layer can be connected to peripheral circuits above the memory stack layer. In addition, each storage layer can be configured with a slightly different doping profile for the P-layer of the donor wafer. In addition, the memory can be arranged in different ways, such as BL and SL are interchangeable, or where wiring is buried, the wiring of the memory array can be placed below the storage layer and above the peripheral circuit. A reading of this specification will allow the skilled person to recall how to make modifications elsewhere within the scope of the invention. Accordingly, the invention is limited only by the appended claims.

電荷俘獲型NAND(反及閘)存儲設備是另外一種常見之商用非易失性記憶體。電荷俘獲型設備將其電荷存儲在電荷俘獲層中。該電荷俘獲層會進而影響電晶體溝槽。有關電荷俘獲型記憶體之背景資訊可查閱《3D納米電子系統集成互連技術》(阿勒泰克出版社;2009年;作者:Bakir和Meindl一下文簡稱Bakir)、《一種使用無結型埋置溝道BE-SONOS設備之高度可擴展8層3D垂直柵極(VG)TFT NAND快閃記憶體》(有關VLSI技術之座談會;2010年;作者:Hang-Ting Lue等)和《快閃記憶體概述》(Proc.IEEE91;第489至502頁(2003);作者:Bez等)。Bakir描述之設備使用選擇性類晶生長、鐳射再結晶或多晶矽形成電晶體溝槽,導致電晶體性能不十分理想。任意一種電荷俘獲型記憶體都用到圖105和106中顯示之結構。 Charge-trapping NAND (NAND) memory devices are another common commercially available non-volatile memory. A charge-trapping device stores its charge in a charge-trapping layer. The charge trapping layer in turn affects the transistor trench. For background information on charge-trapping memory, please refer to "Integrated Interconnection Technology for 3D Nanoelectronic Systems" (Altek Press; 2009; Authors: Bakir and Meindl, hereinafter referred to as Bakir), "A Method of Using Junctionless Buried Ditch Highly Scalable 8-Layer 3D Vertical Gate (VG) TFT NAND Flash Memory for BE-SONOS Devices" (Symposium on VLSI Technology; 2010; Authors: Hang-Ting Lue et al.) and "Flash Memory Overview" (Proc. IEEE91; pp. 489-502 (2003); Author: Bez et al.). The device described by Bakir uses selective crystal growth, laser recrystallization, or polysilicon to form transistor trenches, resulting in suboptimal transistor performance. Any kind of charge trap memory can be used with the structures shown in Figs. 105 and 106 .

如圖105A至104G所示,可建設在每個存儲層帶兩個附加掩蔽工序電荷俘獲型3D記憶體。3D記憶體適用於生產3D IC。該3D記憶體使用建設在單晶矽中之電荷俘獲型電晶體之NAND串。 As shown in Figures 105A to 104G, a charge-trapping 3D memory can be constructed with two additional masking steps per memory layer. 3D memory is suitable for producing 3D IC. The 3D memory uses NAND strings of charge-trapping transistors built in single-crystal silicon.

如圖105A所示,P-基板施主晶圓10500經加工可包含晶圓大小之P-摻雜層10504。P-摻雜層10504之摻雜物濃度 可能與P-基板10500相同,也有可能不同。P-摻雜層10504可能具有垂直摻雜梯度。P-摻雜層10504可透過離子注入和高熱退火之方式形成。可在注入之前生長遮罩氧化層10501,以確保在注入過程中矽免受污染,並為後期晶圓之間之黏結提供氧化層。 As shown in Figure 105A, a P-substrate donor wafer 10500 is processed to include a wafer-sized P-doped layer 10504. Dopant concentration of P-doped layer 10504 May or may not be the same as P-substrate 10500. P-doped layer 10504 may have a vertical doping gradient. The P-doped layer 10504 can be formed by ion implantation and high thermal annealing. A mask oxide layer 10501 may be grown prior to implantation to ensure that the silicon is free from contamination during the implantation process and to provide an oxide layer for later wafer-to-wafer bonding.

如圖105B所示,施主晶圓10500之頂層可用於將氧化物晶圓和氧化層10502之澱積層黏結起來,或透過P-摻雜層10504之高熱氧化,或注入遮罩氧化層10501之二次氧化形成氧化層10502。透過氫離子注入10507或前文所描述之其他方法可在施主晶圓10500或P-層10504(如圖所示)中形成層轉移分界平面10599(圖中虛線部分)。如前文所述,施主晶圓10500和受主晶圓10510均可用作晶圓之間之黏結,然後二者再黏結起來。上述黏結最好在低溫(不超過400℃)下進行,以將應力控制在最低平。可透過切割或打磨或前文所述之工序(例如離子切割或其他之方法)將層轉移分界平面10599上方之P-層部分10504和P-施主晶圓基板10500移除。 As shown in FIG. 105B, the top layer of the donor wafer 10500 can be used to bond the oxide wafer to the deposited layer of the oxide layer 10502, or through high thermal oxidation of the P-doped layer 10504, or implant the second layer of the mask oxide layer 10501. The secondary oxidation forms an oxide layer 10502. A layer transfer interface plane 10599 (dotted line in the figure) can be formed in the donor wafer 10500 or the P-layer 10504 (as shown) by hydrogen ion implantation 10507 or other methods described above. As previously described, both the donor wafer 10500 and the acceptor wafer 10510 can be used as a bond between the wafers, and then the two are bonded together. The above-mentioned bonding is best carried out at low temperature (not exceeding 400°C) to keep the stress at the lowest level. The P-layer portion 10504 above the layer transfer interface plane 10599 and the P-donor wafer substrate 10500 may be removed by dicing or grinding or a process as previously described (eg, ion dicing or other methods).

如圖105C所示,剩餘之P-摻雜10504’和氧化層10502已被層切到受主晶圓10510上。受主晶圓10510可包含電路。這種電路即便在經過附加快速高熱退火(RTA)後仍然可以繼續運行,保持良好之性能。為此,在組建週邊電路時應考量選擇那些只需要輕微RTA或無需RTA之即可開啟摻雜物之週邊電路。另外,週邊電路可使用耐火金屬,例如耐高溫能力超過400℃之鎢。可透過化學或機械方式 將P-摻雜層10504’之最上面一層打磨光滑、平坦。現在電晶體已形成,並與受主晶圓10510之對準標誌(未顯示)對齊。 The remaining P-doping 10504' and oxide layer 10502 have been layer diced onto the acceptor wafer 10510 as shown in Figure 105C. The acceptor wafer 10510 may contain circuitry. This circuit can continue to operate and maintain good performance even after additional rapid thermal annealing (RTA). For this reason, when constructing peripheral circuits, it should be considered to select those peripheral circuits that can turn on the dopant only with a slight RTA or without RTA. In addition, the peripheral circuits can use refractory metals, such as tungsten with high temperature resistance over 400°C. chemically or mechanically The uppermost layer of the P-doped layer 10504' is ground smooth and flat. The transistors are now formed and aligned with the alignment marks (not shown) of the acceptor wafer 10510 .

如圖105D所示,淺槽絕緣層(STI)氧化區(未顯示)可進行光刻和電漿體/反應式離子蝕刻,直至氧化層10502之頂層,從而移除P-單晶矽層區10504’,並形成P-摻雜區10520。間隙填充氧化層可能會澱積並透過化學-機械打磨(CMP)之方式使之平坦化,形成傳統之STI氧化區和P-摻雜單晶矽區(未顯示),從而形成電晶體。也可以同時進行或不進行閾值調整注入。透過生長或電荷俘獲型柵極電介質10522(例如高熱氧化層和氮化矽層-ONO:氧化物-氮化物-氧化物)和柵極金屬材料10524(例如摻雜或無摻雜多晶矽)澱積可形成柵極堆疊層。同樣,電荷俘獲型柵極電介質可包含封裝在氧化物中之矽或III-V納米晶體。 As shown in Figure 105D, the shallow trench insulator (STI) oxide region (not shown) can be subjected to photolithography and plasma/reactive ion etching up to the top layer of the oxide layer 10502 to remove the P-monocrystalline silicon layer region 10504', and form a P-doped region 10520. A gap-fill oxide may be deposited and planarized by chemical-mechanical polishing (CMP) to form conventional STI oxide regions and P-doped monocrystalline silicon regions (not shown) to form transistors. Simultaneous injection with or without threshold adjustment can also be performed. By growth or charge-trapping gate dielectric 10522 (e.g. high thermal oxide layer and silicon nitride layer - ONO: Oxide-Nitride-Oxide) and gate metal material 10524 (e.g. doped or undoped polysilicon) deposition A gate stack layer may be formed. Likewise, the charge-trapping gate dielectric may comprise silicon or III-V nanocrystals encapsulated in oxide.

如圖105E所示,柵極堆疊層10528可進行光刻和電漿體/反應式離子蝕刻,從而移除柵極金屬材料區10524和電荷俘獲柵極電介質10522。可進行自對齊N+源極和汲極注入,以形成電晶體間源極和汲極10534和NAND串源極和汲極之末端10530。最後,間隙填充氧化層10550和氧化層可覆蓋整個結構,可透過化學-機械打磨(CMP)使其平面化。如前文所述,氧化表面可用於氧化物與氧化晶圓之間之黏結。現在已形成第一層存儲電晶體10542,包含二氧化矽層10550,柵極堆疊層10528,電晶體間源極和汲極 10534、NAND串源極和柵極末端10530、P-矽區10520和氧化層10502。 As shown in FIG. 105E , the gate stack layer 10528 can be subjected to photolithography and plasma/reactive ion etching to remove the gate metal material region 10524 and the charge trapping gate dielectric 10522 . Self-aligned N+ source and drain implants can be performed to form the inter-transistor source and drain 10534 and the ends 10530 of the NAND string source and drain. Finally, a gap-fill oxide layer 10550 and an oxide layer can cover the entire structure, which can be planarized by chemical-mechanical polishing (CMP). As mentioned above, the oxide surface can be used for bonding between the oxide and the oxide wafer. The first layer of storage transistors 10542 is now formed, comprising silicon dioxide layer 10550, gate stack layer 10528, source and drain between transistors 10534, NAND string source and gate terminals 10530, P-silicon region 10520 and oxide layer 10502.

如圖105F所示,重複圖105A至105D中描述之電晶體層成型、受主晶圓10510與氧化層10550黏結以及隨後之電晶體成型過程,可在存儲電晶體10542之第一層頂部形成記憶體電晶體第二層10544。所有預期之存儲層都建設好之後,可進行快速高熱退火(RTA),以便從根本上開啟所有存儲層和受主基板10510週邊電路中之摻雜物。或者,可進行光學退火,例如鐳射退火。 As shown in FIG. 105F, repeating the formation of the transistor layer described in FIGS. 105A to 105D, the bonding of the acceptor wafer 10510 and the oxide layer 10550, and the subsequent formation of the transistor can form a memory on top of the first layer of the storage transistor 10542. Bulk transistor second layer 10544. After all desired memory layers are built, a rapid thermal anneal (RTA) can be performed to essentially turn on dopants in all memory layers and peripheral circuitry of the acceptor substrate 10510. Alternatively, optical annealing, such as laser annealing, can be performed.

如圖105G所示,源極線路(SL)接點10548和位線接點10549可透過每個存儲層之氧化層10550、NAND串源極和汲極末端10530、P-區10520和相關之氧化層垂直絕緣區進行光刻和電漿體/反應式離子蝕刻,以便與所有之存儲層垂直連接。然後,SL接地接點和位線接點可透過光阻去除之方法進行處理。可使用金屬或重摻雜多晶矽填充接點和金屬化區域,以形成BL和SL配線區(未顯示)。柵極堆疊層,例如10528,可與接點和金屬化區域連接起來,形成文字線區(WL)和WL配線區(未顯示)。可能會形成穿層過孔10560(未顯示),透過受主晶圓金屬連接焊盤10580(未顯示)使BL、SL和WL之金屬化區域與受主基板10510週邊電路發生電耦合。 As shown in Figure 105G, source line (SL) contacts 10548 and bit line contacts 10549 are permeable through the oxide layer 10550 of each storage layer, NAND string source and drain terminals 10530, P-region 10520 and associated oxide Layer vertical isolation regions are subjected to photolithography and plasma/reactive ion etching to connect vertically to all memory layers. Then, the SL ground contacts and bit line contacts can be processed by photoresist removal. Contacts and metallization areas can be filled with metal or heavily doped polysilicon to form BL and SL wiring regions (not shown). A gate stack layer, such as 10528, can be connected with contacts and metallization areas to form word line regions (WL) and WL wiring regions (not shown). Through-layer vias 10560 (not shown) may be formed to electrically couple the metallized areas of BL, SL and WL to peripheral circuitry of the acceptor substrate 10510 through acceptor wafer metal connection pads 10580 (not shown).

該流程可形成電荷俘獲型3D記憶體,每個存儲層使用兩個附加掩蔽工序。透過層切晶圓大小之摻雜單晶矽層之方式建設3D記憶體。同時,該3D記憶體與下方之多金屬 層半導體設備連接起來。 The process creates charge-trapping 3D memory using two additional masking steps per memory layer. 3D memory is constructed by layering wafer-sized doped monocrystalline silicon layers. At the same time, the 3D memory and the underlying multi-metal Layer semiconductor devices are connected.

具有一般技藝之人可將圖105A至圖105G中提到之例子僅作為典型範例看待,並非按比例縮小。技術高超之人可考量更多變化情況,比如,可透過該流程建設BL或SL選擇電晶體。或者堆疊式記憶體層可與存儲堆疊層上方之週邊電路連接起來。此外,每層存儲層可配置略微不同之施主晶圓P-層摻雜分佈圖。另外,記憶體可以採取不同佈局方式,例如BL和SL互換,或者將這些結構修改成NOR快快閃記憶體儲格式,或者在埋設配線之地方,存儲陣列之配線可置於存儲層下方、週邊電路上方。此外,層切前電荷俘獲型絕緣層和柵極層可能會澱積,並臨時與載子或晶圓保持器或基板黏結起來,然後再利用週邊電路轉移到受主基板上。透過閱讀本說明書,可使技藝高超之人想起如何在本發明範圍內對其他地方進行修改。因此,本發明僅受限於附加之權利要求。 Those of ordinary skill may regard the examples mentioned in FIGS. 105A-105G as typical examples only and not to scale. Skilled people can consider more changes, for example, BL or SL selection transistors can be built through this process. Alternatively, the stacked memory layer can be connected to peripheral circuits above the memory stack layer. In addition, each storage layer can be configured with a slightly different doping profile for the P-layer of the donor wafer. In addition, the memory can adopt different layout methods, such as BL and SL interchange, or modify these structures into NOR flash memory storage format, or in the place where wiring is buried, the wiring of the storage array can be placed under the storage layer, around the above the circuit. In addition, charge-trapping insulating layers and gate layers may be deposited and temporarily bonded to carriers or wafer holders or substrates before layer dicing, and then transferred to the acceptor substrate using peripheral circuits. A reading of this specification will allow the skilled person to recall how to make modifications elsewhere within the scope of the invention. Accordingly, the invention is limited only by the appended claims.

如圖106A至106G所示,可建設在每個存儲層不帶附加掩蔽工序電荷俘獲型3D記憶體。3D記憶體適用於生產3D IC。該3D記憶體使用電荷俘獲型無結型電晶體之NAND串,帶有建設在單晶矽中之無結型選擇電晶體。 As shown in FIGS. 106A to 106G, a charge-trapping 3D memory can be constructed without an additional masking process in each memory layer. 3D memory is suitable for producing 3D IC. The 3D memory uses NAND strings of charge-trapping junctionless transistors with junctionless select transistors built in single crystal silicon.

如圖106A所示,帶週邊電路10602之矽基板可使用耐高溫(超過400℃)配線,例如鎢絲。週邊電路基板10602可包含記憶體控制電路以及其他用途之各種電路,例如用於類比、數位、射頻或存儲。週邊電路基板10602可包含週邊電路。這種週邊電路即便在經過附加快速高熱退火 (RTA)後仍然可以繼續運行,保持良好之性能。為此,在組建週邊電路時應考量選擇那些只需要輕微RTA或無需RTA之即可開啟摻雜物之週邊電路。週邊電路基板10602之最上面一層可用於將氧化物晶圓和二氧化矽10604之澱積層黏結起來,從而形成受主晶圓10614。 As shown in FIG. 106A , the silicon substrate with the peripheral circuit 10602 can use high temperature resistant (over 400° C.) wiring, such as tungsten wire. The peripheral circuit substrate 10602 may include memory control circuits and various circuits for other purposes, such as for analog, digital, radio frequency or storage. The peripheral circuit substrate 10602 may include peripheral circuits. This peripheral circuit even after additional rapid high thermal annealing (RTA) can still continue to run and maintain good performance. For this reason, when constructing peripheral circuits, it should be considered to select those peripheral circuits that can turn on the dopant only with a slight RTA or without RTA. The uppermost layer of the peripheral circuit substrate 10602 can be used to bond the oxide wafer and the deposited layer of silicon dioxide 10604 to form the acceptor wafer 10614 .

如圖106B所示,單晶矽施主晶圓10612可包含晶圓大小之N+摻雜層(未顯示),其中之摻雜物濃度可能與N+基板10606不同。N+摻雜層可透過離子注入和高熱退火方式形成。可在注入之前生長或澱積遮罩氧化層10608,以確保在注入過程中矽免受污染,並為後期晶圓之間之黏結提供氧化層。透過氫離子注入或前文所描述之其他方法可在N+基板10606或N+摻雜層(未顯示)中之施主晶圓10612中形成層轉移分界平面10610(圖中虛線部分)。如前文所述,施主晶圓10612和受主晶圓10614均用於晶圓黏結,並在氧化層10604和氧化層10608之表面黏結在一起。因低溫時應力最低,黏結操作最好在低溫(低於400℃)或中溫(不超過900℃)下進行。 As shown in FIG. 106B , a single crystal silicon donor wafer 10612 may include a wafer-sized N+ doped layer (not shown), which may have a different dopant concentration than the N+ substrate 10606 . The N+ doped layer can be formed by ion implantation and high thermal annealing. A mask oxide layer 10608 can be grown or deposited prior to implantation to ensure that the silicon is free from contamination during implantation and to provide an oxide layer for later wafer-to-wafer bonding. A layer transfer boundary plane 10610 (dotted line in the figure) can be formed in the N+ substrate 10606 or the donor wafer 10612 in the N+ doped layer (not shown) by hydrogen ion implantation or other methods described above. Both the donor wafer 10612 and the acceptor wafer 10614 are used for wafer bonding and are bonded together on the surfaces of the oxide layer 10604 and the oxide layer 10608 as previously described. Because the stress is lowest at low temperature, the bonding operation is best carried out at low temperature (below 400°C) or medium temperature (not exceeding 900°C).

如圖106C所示,可透過切割或打磨或前文所述之工序(例如離子切割或其他方法)將層轉移分界平面10610上方之N+層部分(未顯示)和N+晶圓基板10606移除,從而形成剩餘之單晶矽N+層10606。剩餘之N+層10606’和氧化層10608被層切到受主晶圓10614上。可透過化學或機械方式將N+層10606’之最上面一層打磨光滑、平坦。氧化層10620可能會澱積,為後期氧化物之間之黏結提供表面。 此時,第一層Si/SiO2層10623已形成,包含二氧化矽層10620、N+矽層10606’和氧化層10608。 As shown in FIG. 106C , the portion of the N+ layer (not shown) above the layer transfer interface plane 10610 and the N+ wafer substrate 10606 can be removed by dicing or grinding or the processes described above (such as ion cutting or other methods), thereby The remaining monocrystalline silicon N+ layer 10606 is formed. The remaining N+ layer 10606' and oxide layer 10608 are layer diced onto the acceptor wafer 10614. The uppermost layer of the N+ layer 10606' can be polished smooth and flat by chemical or mechanical means. An oxide layer 10620 may be deposited to provide a surface for later bonding between oxides. At this point, the first Si/SiO2 layer 10623 has been formed, including the silicon dioxide layer 10620, the N+ silicon layer 10606' and the oxide layer 10608.

如圖106D所示,可能會額外形成圖106A至圖106C所示之Si/SiO2層,比如第二層Si/SiO2層10625和第三層Si/SiO2層10627。氧化層10629可能會澱積,實現與頂部N+矽層之間之絕緣。 As shown in FIG. 106D, Si/SiO2 layers shown in FIGS. 106A to 106C may be additionally formed, such as a second Si/SiO2 layer 10625 and a third Si/SiO2 layer 10627. An oxide layer 10629 may be deposited to provide isolation from the top N+ silicon layer.

如圖106E所示,氧化層10629、第三層Si/SiO2層10627、第二層Si/SiO2層10625和第一層Si/SiO2層10623可進行光刻和電漿體/反應式離子蝕刻,形成存儲晶片結構之一部分。存儲晶片結構現在已包含N+矽區10626和氧化層區10622。 As shown in Figure 106E, the oxide layer 10629, the third Si/SiO2 layer 10627, the second Si/SiO2 layer 10625 and the first Si/SiO2 layer 10623 can be photolithographically and plasma/reactive ion etched, Forms part of a memory wafer structure. The memory wafer structure now includes N+ silicon region 10626 and oxide layer region 10622 .

如圖106F所示,透過生長或沉澱電荷俘獲型柵極電介質(例如高熱氧化層和氮化矽層-ONO:氧化物-氮化物-氧化物)和柵極金屬電極層(例如摻雜或無摻雜多晶矽)可形成柵極堆疊層。然後,可透過化學-機械打磨(CMP)使柵極金屬電極層平面化。同樣,電荷俘獲型柵極電介質可包含封裝在氧化物中之矽或III-V納米晶體。選擇柵極區10638可包含非電荷俘獲型絕緣層。NAND串區域10636和選擇電晶體區10638之柵極金屬電極區10630和柵極電介質區10628可進行光刻和電漿體/反應式離子蝕刻。 As shown in Figure 106F, by growing or depositing a charge-trapping gate dielectric (such as high thermal oxide layer and silicon nitride layer-ONO: Oxide-Nitride-Oxide) and a gate metal electrode layer (such as doped or Doped polysilicon) can form the gate stack layer. Then, the gate metal electrode layer can be planarized by chemical-mechanical polishing (CMP). Likewise, the charge-trapping gate dielectric may comprise silicon or III-V nanocrystals encapsulated in oxide. Select gate region 10638 may include a non-charge-trapping insulating layer. The gate metal electrode region 10630 and gate dielectric region 10628 of the NAND string region 10636 and select transistor region 10638 can be photolithographically and plasma/reactive ion etched.

如圖106G所示,間隙填充氧化層10632可覆蓋整個結構,可透過化學-機械打磨(CMP)使其平面化。為清晰起見,圖中氧化層10632顯示為透明層。可形成選擇金屬線10646,並與相關之選擇柵極接點10634連接在一起。在 存儲陣列邊緣可形成WL和SL之接點和相關之金屬佈線(未顯示)。文字線區(WL)10636、柵電極10630和位線區(BL)10652,包含所示之N+矽區10626如圖所示。透過接點蝕刻和填充可形成源極區10644,使之與NAND串10636源極末端之N+矽區黏結起來。可能會形成穿層過孔10660(未顯示),透過受主晶圓金屬連接焊盤10680(未顯示)使BL、SL和WL之金屬化區域與受主基板10614週邊電路發生電耦合。 As shown in FIG. 106G, a gap-fill oxide layer 10632 may cover the entire structure, which may be planarized by chemical-mechanical polishing (CMP). For clarity, the oxide layer 10632 is shown as a transparent layer in the figure. Select metal lines 10646 can be formed and connected together with associated select gate contacts 10634 . exist Contacts of WL and SL and associated metal routing (not shown) may be formed at the edge of the memory array. Word line region (WL) 10636, gate electrode 10630 and bit line region (BL) 10652, including N+ silicon region 10626 as shown. Source region 10644 is formed by contact etch and fill to bond to the N+ silicon region at the source end of NAND string 10636 . Through-layer vias 10660 (not shown) may be formed to electrically couple the metallized areas of BL, SL, and WL to peripheral circuitry of the acceptor substrate 10614 through acceptor wafer metal connection pads 10680 (not shown).

該流程可形成電荷俘獲型3D記憶體,每個存儲層不使用附加掩蔽工序。透過層切晶圓大小之摻雜單晶矽層之方式建設3D記憶體。同時,該3D記憶體與下方之多金屬層半導體設備連接起來。 The process can form charge-trapping 3D memory without additional masking steps for each memory layer. 3D memory is constructed by layering wafer-sized doped monocrystalline silicon layers. At the same time, the 3D memory is connected to the underlying multi-metal layer semiconductor device.

具有一般技藝之人可將圖106A至圖106G中提到之例子僅作為典型範例看待,並非按比例縮小。技藝高超之人可考量更多之變化情況,比如,可採取前文中描述之階梯方式建設BL或SL接點。或者堆疊式記憶體層可與存儲堆疊層上方之週邊電路連接起來。此外,每層存儲層可配置略微不同之施主晶圓N+層摻雜分佈圖。另外,記憶體可以採取不同之佈局方式,例如BL和SL互換,或者在埋設配線之地方,存儲陣列之配線可置於存儲層下方、週邊電路上方。透過單晶矽層切之方法還可以建設其他類型之3D電荷俘獲型記憶體,例如在《一種使用無結型埋置溝道BE-SONOS設備之高度可擴展8層3D垂直柵極(VG)TFT NAND快閃記憶體》(有關VLSI技術之座談會;2010年; 作者:Hang-Ting Lue等)和《一種克服了太比位元密度記憶體堆疊限制之多層垂直柵極NAND快閃記憶體》(有關VLSI技術之座談會;2009年;作者:W.Kim、S.Choi,等)中提到之記憶體。透過閱讀本說明書,可使技藝高超之人想起如何在本發明範圍內對其他地方進行修改。因此,本發明僅受限於附加之權利要求。 Those of ordinary skill may consider the examples mentioned in FIGS. 106A-106G to be representative examples only and not to scale. People with high skills can consider more changes. For example, the ladder method described above can be used to build BL or SL contacts. Alternatively, the stacked memory layer can be connected to peripheral circuits above the memory stack layer. In addition, each storage layer can be configured with a slightly different doping profile for the N+ layer of the donor wafer. In addition, the memory can adopt different layout methods, such as BL and SL are interchanged, or where the wiring is buried, the wiring of the memory array can be placed below the storage layer and above the peripheral circuit. Other types of 3D charge-trapping memories can also be constructed through the method of monocrystalline silicon layer dicing, for example, in "A highly scalable 8-layer 3D vertical gate (VG) using a junctionless buried channel BE-SONOS device TFT NAND Flash Memory" (symposium on VLSI technology; 2010; Authors: Hang-Ting Lue et al.) and "A Multilayer Vertical Gate NAND Flash Memory Overcomes the Stacking Limit of Terabit-Density Memory" (Symposium on VLSI Technology; 2009; Authors: W.Kim, S. Choi, et al.) mentioned memory. A reading of this specification will allow the skilled person to recall how to make modifications elsewhere within the scope of the invention. Accordingly, the invention is limited only by the appended claims.

浮柵(FG)存儲設備是另外一種常見之商用非易失性記憶體。浮柵設備將其電荷存儲在導電柵極(FG)中,而導電柵極名義上是與無意電場絕緣的。在這些電場中,FG上之電荷會反過來影響電晶體之溝槽。有關浮柵快速記憶體之背景資訊可查閱《快閃記憶體概述》(Proc.IEEE91;第489至502頁(2003);作者:R.Bez等)。任意一種浮柵記憶體都用到圖107和108中顯示之結構。 Floating gate (FG) memory devices are another common type of commercial non-volatile memory. A floating-gate device stores its charge in a conductive gate (FG), which is nominally insulated from unintentional electric fields. In these electric fields, the charge on FG will in turn affect the trench of the transistor. Background information on floating gate flash memory can be found in "Overview of Flash Memory" (Proc. IEEE91; pages 489 to 502 (2003); author: R. Bez et al.). Any kind of floating gate memory can use the structure shown in Figs. 107 and 108.

如圖107A至104G所示,可建設在每個存儲層帶兩個附加掩蔽工序浮柵3D記憶體。3D記憶體適用於生產3D IC。該3D記憶體使用建設在單晶矽中之浮柵電晶體之NAND串。 As shown in Figures 107A to 104G, a floating gate 3D memory can be built with two additional masking steps per memory layer. 3D memory is suitable for producing 3D IC. The 3D memory uses NAND strings of floating-gate transistors built in single-crystal silicon.

如圖107A所示,P-基板施主晶圓10700經加工可包含晶圓大小之P-摻雜層10704。P-摻雜層10704之摻雜物濃度可能與P-基板10700相同,也有可能不同。P-摻雜層10704可能具有垂直摻雜梯度。P-摻雜層10704可透過離子注入和高熱退火之方式形成。可在注入之前生長遮罩氧化層10701,以確保在注入過程中矽免受污染,並為後期晶圓之間之黏結提供氧化層。 As shown in Figure 107A, a P-substrate donor wafer 10700 is processed to include a wafer-sized P-doped layer 10704. The dopant concentration of the P-doped layer 10704 may be the same as that of the P-substrate 10700, or it may be different. P-doped layer 10704 may have a vertical doping gradient. The P-doped layer 10704 can be formed by ion implantation and high thermal annealing. A mask oxide layer 10701 can be grown prior to implantation to ensure silicon contamination during implantation and to provide an oxide layer for later wafer-to-wafer bonding.

如圖107B所示,施主晶圓10700之頂層可用於將氧化物晶圓和氧化層10702之澱積層黏結起來,或透過P-摻雜層10704之高熱氧化,或注入遮罩氧化層10701之二次氧化形成氧化層10702。透過氫離子注入10707或前文所描述之其他方法可在施主晶圓10700或P-層10704(如圖所示)中形成層轉移分界平面10799(圖中虛線部分)。如前文所述,施主晶圓10700和受主晶圓10710均可用作晶圓之間之黏結,然後二者再黏結起來。上述黏結最好在低溫(不超過400℃)下進行,以將應力控制在最低平。可透過切割或打磨或前文所述之工序(例如離子切割或其他方法)將層切分界平面10799上方之P-層部分10704和P-施主晶圓基板10700移除。 As shown in FIG. 107B, the top layer of the donor wafer 10700 can be used to bond the oxide wafer to the deposited layer of the oxide layer 10702, or through high thermal oxidation of the P-doped layer 10704, or implant the second layer of the mask oxide layer 10701. The secondary oxidation forms an oxide layer 10702 . A layer transfer interface plane 10799 (dotted line in the figure) can be formed in the donor wafer 10700 or the P-layer 10704 (as shown) by hydrogen ion implantation 10707 or other methods described above. As previously described, both the donor wafer 10700 and the acceptor wafer 10710 can be used as a bond between the wafers, and then the two are bonded together. The above-mentioned bonding is best carried out at low temperature (not exceeding 400°C) to keep the stress at the lowest level. The P-layer portion 10704 and the P-donor wafer substrate 10700 above the dicing interface plane 10799 may be removed by dicing or grinding or the processes described above, such as ion dicing or other methods.

如圖107C所示,剩餘之P-摻雜10704’和氧化層10702已被層切到受主晶圓10710上。受主晶圓10710可包含電路。這種電路即便在經過附加快速高熱退火(RTA)後仍然可以繼續運行,保持良好之性能。為此,在組建週邊電路時應考量選擇那些只需要輕微RTA或無需RTA之即可開啟摻雜物之週邊電路。另外,週邊電路可使用耐火金屬,例如耐高溫能力超過400℃之鎢。可透過化學或機械方式將P-摻雜層10704’之最上面一層打磨光滑、平坦。現在電晶體已形成,並與受主晶圓10710之對準標誌(未顯示)對齊。 The remaining P-doping 10704&apos; and oxide layer 10702 have been layered onto the acceptor wafer 10710 as shown in Figure 107C. The acceptor wafer 10710 may contain circuitry. This circuit can continue to operate and maintain good performance even after additional rapid thermal annealing (RTA). For this reason, when constructing peripheral circuits, it should be considered to select those peripheral circuits that can turn on the dopant only with a slight RTA or without RTA. In addition, the peripheral circuits can use refractory metals, such as tungsten with high temperature resistance over 400°C. The uppermost layer of the P-doped layer 10704' can be polished smooth and flat by chemical or mechanical means. The transistors are now formed and aligned with the alignment marks (not shown) of the acceptor wafer 10710 .

如圖107D所示,透過生長或澱積隧道氧化層10722(例如高熱氧化層)和FG柵極金屬材料10724(例如摻雜 或無摻雜多晶矽)可形成部分柵極堆疊層。同樣,電荷俘獲型柵極電介質可包含封裝在氧化物中之矽或III-V納米晶體。淺槽絕緣層(STI)氧化區(未顯示)可進行光刻和電漿體/反應式離子蝕刻,直至氧化層10702之頂層,從而移除P-單晶矽層區10704,並形成P-摻雜區10720。間隙填充氧化層可能會澱積並透過化學-機械打磨(CMP)之方式使之平坦化,形成傳統之STI氧化區(未顯示)。 As shown in FIG. 107D, by growing or depositing a tunnel oxide layer 10722 (such as a high thermal oxide layer) and an FG gate metal material 10724 (such as a doped or undoped polysilicon) can form part of the gate stack layer. Likewise, the charge-trapping gate dielectric may comprise silicon or III-V nanocrystals encapsulated in oxide. The shallow trench insulator (STI) oxide region (not shown) can be photolithographically and plasma/reactive ion etched down to the top layer of the oxide layer 10702 to remove the P- monocrystalline silicon layer region 10704 and form the P- Doped region 10720. A gap-fill oxide may be deposited and planarized by chemical-mechanical polishing (CMP), forming a conventional STI oxide (not shown).

如圖107E所示,多晶矽氧化層10725(例如二氧化矽層和氮化矽層-ONO:氧化物-氮化物-氧化物)和控制柵極(CG)柵極金屬材料10726(例如摻雜或無摻雜多晶矽)可能會澱積。柵極堆疊層10728可進行光刻和電漿體/反應式離子蝕刻,從而去除CG柵極金屬材料區10726、多晶矽氧化層10725、FG柵極金屬材料10724和隧道氧化層10722。去除操作可形成柵極堆疊層10728,包含CG柵極金屬區10726、多晶矽氧化區10725、FG柵極金屬區10724和隧道氧化層區10722。為清晰起見,只在區域層線條中標注了一個柵極堆疊層10728。可進行自對齊N+源極和汲極注入,以形成電晶體間源極和汲極10734和NAND串源極和汲極之末端10730。最後,間隙填充氧化層10750可覆蓋整個結構,可透過化學-機械打磨(CMP)使其平面化。如前文所述,氧化表面可用於氧化物與氧化晶圓之間之黏結。現在已形成第一層存儲電晶體10742,包含二氧化矽層10750,柵極堆疊層10728,電晶體間源極和汲極10734、NAND串源極和柵極末端10730、P-矽區10720和氧 化層10702。 As shown in FIG. 107E, a polysilicon oxide layer 10725 (such as a silicon dioxide layer and a silicon nitride layer—ONO: Oxide-Nitride-Oxide) and a control gate (CG) gate metal material 10726 (such as a doped or undoped polysilicon) may be deposited. The gate stack layer 10728 can be subjected to photolithography and plasma/reactive ion etching to remove the CG gate metal material region 10726 , the polysilicon oxide layer 10725 , the FG gate metal material 10724 and the tunnel oxide layer 10722 . The removal operation may form gate stack layer 10728 including CG gate metal region 10726 , polysilicon oxide region 10725 , FG gate metal region 10724 and tunnel oxide region 10722 . For clarity, only one gate stack layer 10728 is labeled in the area layer line. Self-aligned N+ source and drain implants can be performed to form inter-transistor source and drain 10734 and ends 10730 of NAND string source and drain. Finally, a gap-fill oxide layer 10750 may cover the entire structure, which may be planarized by chemical-mechanical polishing (CMP). As mentioned above, the oxide surface can be used for bonding between the oxide and the oxide wafer. The first layer of storage transistors 10742 is now formed, comprising silicon dioxide layer 10750, gate stack layer 10728, inter-transistor source and drain 10734, NAND string source and gate terminations 10730, P-silicon region 10720 and oxygen layer 10702.

如圖107F所示,重複圖107A至107D中描述之電晶體層成型、受主晶圓10710與氧化層10750黏結以及隨後之電晶體成型過程,可在存儲電晶體10742之第一層頂部形成記憶體電晶體第二層10744。所有預期之存儲層都建設好之後,可進行快速高熱退火(RTA),以便從根本上開啟所有存儲層和受主基板10710週邊電路中之摻雜物。或者,可進行光學退火,例如鐳射退火。 As shown in FIG. 107F, repeating the formation of the transistor layer described in FIGS. 107A to 107D, the bonding of the acceptor wafer 10710 and the oxide layer 10750, and the subsequent formation of the transistor can form a memory on top of the first layer of the storage transistor 10742. Bulk transistor second layer 10744. After all desired memory layers are built, a rapid thermal anneal (RTA) can be performed to essentially turn on all memory layers and dopants in the surrounding circuitry of the acceptor substrate 10710. Alternatively, optical annealing, such as laser annealing, can be performed.

如圖107G所示,源極線路(SL)接地接點10748和位線接點10749可透過每個存儲層之氧化層10750、NAND串源極和汲極末端10730、P-區10720和相關之氧化層垂直絕緣區進行光刻和電漿體/反應式離子蝕刻,以便與所有之存儲層垂直連接。然後,SL接地接點10748和位線接點10749可透過光阻去除之方法進行處理。可使用金屬或重摻雜多晶矽填充接點和金屬化區域,以形成BL和SL配線區(未顯示)。柵極堆疊層,例如10728,可與接點和金屬化區域連接起來,形成文字線區(WL)和WL配線區(未顯示)。可能會形成穿層過孔10760(未顯示),透過受主晶圓金屬連接焊盤10710(未顯示)使BL、SL和WL之金屬化區域與受主基板10780週邊電路發生電耦合。 As shown in FIG. 107G, source line (SL) ground contact 10748 and bit line contact 10749 are permeable through oxide layer 10750 of each storage layer, NAND string source and drain terminals 10730, P-region 10720 and associated Oxide vertical isolation regions are photolithographically and plasma/reactive ion etched for vertical connection to all memory layers. The SL ground contact 10748 and the bit line contact 10749 can then be processed by photoresist removal. Contacts and metallization areas can be filled with metal or heavily doped polysilicon to form BL and SL wiring regions (not shown). A gate stack layer, such as 10728, can be connected with contacts and metallization areas to form word line regions (WL) and WL wiring regions (not shown). Through-layer vias 10760 (not shown) may be formed to electrically couple the metallized areas of BL, SL and WL to peripheral circuitry of the acceptor substrate 10780 through acceptor wafer metal connection pads 10710 (not shown).

該流程可形成浮柵3D記憶體,每個存儲層使用兩個附加掩蔽工序。透過層切晶圓大小之摻雜單晶矽層之方式建設3D記憶體。同時,該3D記憶體與下方之多金屬層半導體設備連接起來。 The process creates floating-gate 3D memory using two additional masking steps per memory layer. 3D memory is constructed by layering wafer-sized doped monocrystalline silicon layers. At the same time, the 3D memory is connected to the underlying multi-metal layer semiconductor device.

具有一般技藝之人可將圖107A至圖107G中提到之例子僅作為典型範例看待,並非按比例縮小。技術高超之人可考量更多之變化情況,比如,可透過該流程建設BL或SL選擇電晶體。或者堆疊式記憶體層可與存儲堆疊層上方之週邊電路連接起來。此外,每層存儲層可配置略微不同之施主晶圓P-層摻雜分佈圖。另外,記憶體可以採取不同佈局方式,例如BL和SL互換,或者在埋設配線之地方,存儲陣列之配線可置於存儲層下方、週邊電路上方。透過閱讀本說明書,可使技藝高超之人想起如何在本發明範圍內對其他地方進行修改。因此,本發明僅受限於附加之權利要求。 Those of ordinary skill may consider the examples mentioned in FIGS. 107A-107G to be representative examples only and not to scale. Skilled people can consider more changes, for example, BL or SL selection transistors can be constructed through this process. Alternatively, the stacked memory layer can be connected to peripheral circuits above the memory stack layer. In addition, each storage layer can be configured with a slightly different doping profile for the P-layer of the donor wafer. In addition, the memory can adopt different layout methods, such as BL and SL are interchanged, or where the wiring is buried, the wiring of the memory array can be placed below the storage layer and above the peripheral circuit. A reading of this specification will allow the skilled person to recall how to make modifications elsewhere within the scope of the invention. Accordingly, the invention is limited only by the appended claims.

如圖108A至108H所示,可建設在每個存儲層帶一個附加掩蔽工序之浮柵3D記憶體。3D記憶體適用於生產3D IC。該3D記憶體使用建設在單晶矽中之3D浮柵無結型電晶體。 As shown in Figures 108A to 108H, a floating gate 3D memory can be constructed with an additional masking process at each memory layer. 3D memory is suitable for producing 3D IC. The 3D memory uses 3D floating gate junctionless transistors built in single crystal silicon.

如圖108A所示,帶週邊電路10802之矽基板可使用耐高溫(超過400℃)配線,例如鎢絲。週邊電路基板10802可包含記憶體控制電路以及其他用途之各種電路,例如用於類比、數位、射頻或存儲。周邊電路基板10802可包含周邊電路。這種周邊電路即便在經過附加快速高熱退火(RTA)後仍然可以繼續運行,保持良好之性能。為此,在組建週邊電路時應考量選擇那些只需要輕微RTA或無需RTA之即可開啟摻雜物之週邊電路。週邊電路基板10802之最上面一層可用於將氧化物晶圓和二氧化矽10804之澱 積層黏結起來,從而形成受主晶圓10814。 As shown in FIG. 108A , the silicon substrate with the peripheral circuit 10802 can use high temperature resistant (over 400° C.) wiring, such as tungsten wire. The peripheral circuit substrate 10802 may include memory control circuits and various circuits for other purposes, such as analog, digital, radio frequency or storage. The peripheral circuit substrate 10802 may include peripheral circuits. This peripheral circuit can continue to operate even after additional rapid thermal annealing (RTA), maintaining good performance. For this reason, when constructing peripheral circuits, it should be considered to select those peripheral circuits that can turn on the dopant only with a slight RTA or without RTA. The uppermost layer of the peripheral circuit substrate 10802 can be used to deposit the oxide wafer and silicon dioxide 10804 The buildup is bonded to form the acceptor wafer 10814.

如圖108B所示,單晶矽N+施主晶圓10812可包含晶圓大小之N+摻雜層(未顯示),其中之摻雜物濃度可能與N+基板10806不同。N+摻雜層可透過離子注入和高熱退火方式形成。可在注入之前生長或澱積遮罩氧化層10808,以確保在注入過程中矽免受污染,並為後期晶圓之間之黏結提供氧化層。透過氫離子注入或前文所描述之其他方法可在N+基板10806或N+摻雜層(未顯示)中之施主晶圓10812中形成層轉移分界平面10810(圖中虛線部分)。如前文所述,施主晶圓10812和受主晶圓10814均用於晶圓黏結,並在氧化層10804和氧化層10808之表面黏結在一起。因低溫時應力最低,黏結操作最好在低溫(低於400℃)或中溫(不超過900℃)下進行。 As shown in FIG. 108B , a single crystal silicon N+ donor wafer 10812 may include a wafer-sized N+ doped layer (not shown), which may have a different dopant concentration than the N+ substrate 10806 . The N+ doped layer can be formed by ion implantation and high thermal annealing. A mask oxide layer 10808 may be grown or deposited prior to implantation to ensure that the silicon is free from contamination during implantation and to provide an oxide layer for later wafer-to-wafer bonding. A layer transfer boundary plane 10810 (dotted line in the figure) can be formed in the N+ substrate 10806 or the donor wafer 10812 in the N+ doped layer (not shown) by hydrogen ion implantation or other methods described above. Both the donor wafer 10812 and the acceptor wafer 10814 are used for wafer bonding and are bonded together on the surfaces of the oxide layer 10804 and the oxide layer 10808 as described above. Because the stress is lowest at low temperature, the bonding operation is best carried out at low temperature (below 400°C) or medium temperature (not exceeding 900°C).

如圖108C所示,可透過切割或打磨或前文所述之工序(例如離子切割或其他方法)將層轉移分界平面10810上方之N+層部分(未顯示)和N+晶圓基板10806移除,從而形成剩餘之單晶矽N+層10806。剩餘之N+層10806’和氧化層10808被層切到受主晶圓10814上。可透過化學或機械方式將N+層10806之最上面一層打磨光滑、平坦。現在電晶體已全部或部分形成,並與受主晶圓10814之對準標誌(未顯示)對齊。 As shown in FIG. 108C , the portion of the N+ layer (not shown) above the layer transfer boundary plane 10810 and the N+ wafer substrate 10806 can be removed by dicing or grinding or the processes described above (such as ion cutting or other methods), thereby The remaining monocrystalline silicon N+ layer 10806 is formed. The remaining N+ layer 10806' and oxide layer 10808 are layer diced onto the acceptor wafer 10814. The uppermost layer of the N+ layer 10806 can be polished smooth and flat by chemical or mechanical means. The transistors are now fully or partially formed and aligned with the alignment marks (not shown) of the acceptor wafer 10814 .

如圖108D所示,N+區10816可進行光刻和電漿體/反應式離子蝕刻,從而移除N+層區域10806,並停留在氧化層10808上或部分停留在氧化層10808中。 As shown in FIG. 108D , the N+ region 10816 can be subjected to photolithography and plasma/reactive ion etching to remove the N+ layer region 10806 and reside on or partially in the oxide layer 10808 .

如圖108E所示,隧道電介質10818(比如高熱二氧化矽)可能會生長或澱積,浮柵(FG)材料10828(例如摻雜或無摻雜多晶矽)可能會澱積。可透過化學-機械打磨(CMP)方式使該結構大致與N+區10816位於同一平面上。如前文所述,該表面可用於氧化物與氧化晶圓之間之黏結,比如薄層氧化物之間之澱積。現在已形成了第一層存儲層10823,包含將來之FG區10828、隧道電介質10818、N+區10816和氧化層10808。 As shown in FIG. 108E , tunnel dielectric 10818 (such as high-temperature silicon dioxide) may be grown or deposited, and floating gate (FG) material 10828 (such as doped or undoped polysilicon) may be deposited. This structure may be substantially coplanar with the N+ region 10816 by chemical-mechanical polishing (CMP). As mentioned above, this surface can be used for bonding between oxide and oxide wafer, such as deposition between thin layers of oxide. The first storage layer 10823 has now been formed, including the future FG region 10828 , tunnel dielectric 10818 , N+ region 10816 and oxide layer 10808 .

如圖108F所示,重複圖108A至108E中描述之N+層成型、受主晶圓黏結以及隨後之存儲層成型過程,可在存儲層10823之第一層頂部形成記憶體第二層10825。然後,氧化層10829可能會澱積。 As shown in FIG. 108F , the second layer 10825 of memory can be formed on top of the first layer of the memory layer 10823 by repeating the N+ layer formation, acceptor wafer bonding, and subsequent formation of the memory layer described in FIGS. 108A to 108E . An oxide layer 10829 may then be deposited.

如圖108G所示,FG區10838可進行化學-機械打磨(CMP),從而移除第二層存儲層10825上之氧化層部分10829、將來的FG區10828和氧化層10808以及第一層存儲層10823上之將來的FG區10828,從而停留在第一層存儲層10823之氧化層10808上或部分停留在氧化層10808中。 As shown in Figure 108G, the FG region 10838 can be chemically mechanically polished (CMP) to remove the oxide layer portion 10829 on the second storage layer 10825, the future FG region 10828 and oxide layer 10808, and the first storage layer The future FG region 10828 on 10823 stays on the oxide layer 10808 of the first storage layer 10823 or partially stays in the oxide layer 10808 .

如圖108H所示,多晶矽氧化層10850(例如二氧化矽層和氮化矽層-ONO:氧化物-氮化物-氧化物)和控制柵極(CG)柵極材料10852(例如摻雜或無摻雜多晶矽)可能會澱積。透過化學-機械打磨(CMP)方式使該表面平面化,得到薄層氧化層10829’。如圖所示,這樣就得到了有關四個帶N+無結型電晶體之水平方向浮柵存儲晶片之資訊。可對形成眾所周知之記憶體出口/解碼電路之接點 和金屬配線進行處理,形成穿層過孔(TLV)。藉由受主晶圓金屬連接焊盤與記憶體出口發生電耦合,並對受主基板週邊電路進行解碼。 As shown in FIG. 108H, a polysilicon oxide layer 10850 (such as a silicon dioxide layer and a silicon nitride layer—ONO: Oxide-Nitride-Oxide) and a control gate (CG) gate material 10852 (such as doped or doped polysilicon) may be deposited. The surface is planarized by chemical-mechanical polishing (CMP), resulting in a thin oxide layer 10829'. This results in information about four horizontally oriented floating gate memory chips with N+ junctionless transistors, as shown. Contacts that form well-known memory export/decode circuits Process with metal wiring to form through-layer vias (TLVs). The metal connection pad of the acceptor wafer is electrically coupled with the outlet of the memory, and the peripheral circuit of the acceptor substrate is decoded.

該流程可形成浮柵3D記憶體,每個存儲層使用一個附加掩蔽工序。透過層切晶圓大小之摻雜單晶矽層之方式建設3D記憶體。同時,該3D記憶體與下方之多金屬層半導體設備連接起來。 The process creates floating-gate 3D memory, using an additional masking process for each memory layer. 3D memory is constructed by layering wafer-sized doped monocrystalline silicon layers. At the same time, the 3D memory is connected to the underlying multi-metal layer semiconductor device.

具有一般技藝之人可將圖108A至圖108H中提到之例子僅作為典型範例看待,並非按比例縮小。技術高超之人可考量更多變化情況,比如,可在不同之層(而非同一層)建設存儲晶片控制線。或者堆疊式記憶體層可與存儲堆疊層上方之週邊電路連接起來。此外,每層存儲層可配置略微不同之施主晶圓N+層摻雜分佈圖。另外,記憶體可以採取不同佈局方式,例如BL和SL互換,或者將這些結構修改成NOR快快閃記憶體儲格式,或者在埋設配線之地方,存儲陣列之配線可置於存儲層下方、週邊電路上方。透過閱讀本說明書,可使技藝高超之人想起如何在本發明範圍內對其他地方進行修改。 One of ordinary skill would consider the examples mentioned in FIGS. 108A-108H to be representative examples only and not to scale. Skilled people can consider more variations, for example, memory chip control lines can be built on different layers (rather than the same layer). Alternatively, the stacked memory layer can be connected to peripheral circuits above the memory stack layer. In addition, each storage layer can be configured with a slightly different doping profile for the N+ layer of the donor wafer. In addition, the memory can adopt different layout methods, such as BL and SL interchange, or modify these structures into NOR flash memory storage format, or in the place where wiring is buried, the wiring of the storage array can be placed under the storage layer, around the above the circuit. A reading of this specification will allow the skilled person to recall how to make modifications elsewhere within the scope of the invention.

本專利申請書中提到之單塊3D集成概念可引出基於多晶矽之存儲結構之新穎案例。在利用電阻性記憶體結構作為範例對下圖109和110中之概念進行解釋時,對該領域比較熟悉之人就可以很清楚地看到類似之概念可使用在NAND快速記憶體、電荷俘獲型記憶體、DRAM記憶體結構中以及本專利申請書前文所述之處理流程中。 The monolithic 3D integration concept mentioned in this patent application can lead to novel examples of polysilicon-based memory structures. When using the resistive memory structure as an example to explain the concepts in Figures 109 and 110 below, those familiar with the field can clearly see that similar concepts can be used in NAND flash memory, charge trapping memory, DRAM memory structure and the processing flow described above in this patent application.

如圖109A至109K所示,可建設在每個存儲層不帶附加掩蔽工序之電阻性3D記憶體,其方法適用於生產3D IC。該3D記憶體使用多晶矽無結型電晶體。這種電晶體使用正或副閾值電壓和電阻性記憶組件,與選擇電晶體或存取電晶體串聯。 As shown in Figures 109A to 109K, a resistive 3D memory can be built without additional masking process in each memory layer, and the method is suitable for the production of 3D IC. The 3D memory uses polysilicon junctionless transistors. This transistor uses a positive or secondary threshold voltage and a resistive memory component in series with a select or access transistor.

如圖109A所示,帶週邊電路10902之矽基板可使用耐高溫(超過400℃)配線,例如鎢絲。週邊電路基板10902可包含記憶體控制電路以及其他用途之各種電路,例如用於類比、數位、射頻或存儲。周邊電路基板10902可包含周邊電路。這種周邊電路即便在經過附加快速高熱退火(RTA)後仍然可以繼續運行,保持良好之性能。為此,在組建週邊電路時應考量選擇那些只需要局部或輕微RTA或無需RTA之即可開啟摻雜物之週邊電路。二氧化矽層10904在週邊電路基板之頂層澱積。 As shown in FIG. 109A , the silicon substrate with the peripheral circuit 10902 can use high temperature (over 400° C.) wiring, such as tungsten wire. The peripheral circuit substrate 10902 may include memory control circuits and various circuits for other purposes, such as for analog, digital, radio frequency or storage. The peripheral circuit substrate 10902 may include peripheral circuits. This peripheral circuit can continue to operate even after additional rapid thermal annealing (RTA), maintaining good performance. For this reason, when constructing peripheral circuits, it should be considered to select those peripheral circuits that only require partial or slight RTA or can turn on the dopant without RTA. A silicon dioxide layer 10904 is deposited on top of the peripheral circuit substrate.

如圖109B所示,N+摻雜多晶矽層或非晶矽層10906可能會澱積。可採用化學汽相澱積法(例如低壓化學氣相澱積--LPCVD或電漿體增強化學氣相澱積--PECVD或其他之工藝方法)使非晶矽層或多晶矽層10906澱積。在澱積時可摻雜N+摻雜物,例如砷或磷;也可在澱積時不摻雜,澱積後再進行摻雜,例如採用離子注入或PLAD(電漿體摻雜)技術。然後可使二氧化矽層10920澱積或生長。現在就形成了第一層Si/SiO2層10923,包含N+摻雜多晶矽層或非晶矽層10906和二氧化矽層10920。 As shown in Figure 109B, an N+ doped polysilicon layer or amorphous silicon layer 10906 may be deposited. The amorphous silicon layer or polysilicon layer 10906 can be deposited by chemical vapor deposition (such as low pressure chemical vapor deposition - LPCVD or plasma enhanced chemical vapor deposition - PECVD or other process methods). N+ dopant, such as arsenic or phosphorus, can be doped during deposition; it can also be undoped during deposition, and then doped after deposition, for example, using ion implantation or PLAD (plasma doping) technology. A silicon dioxide layer 10920 may then be deposited or grown. The first Si/SiO2 layer 10923 is now formed, comprising an N+ doped polysilicon layer or amorphous silicon layer 10906 and a silicon dioxide layer 10920 .

如圖109C所示,可能會額外形成圖109B中所示之 Si/SiO2層,比如第二層Si/SiO2層10925和第三層Si/SiO2層10927。氧化層10929可能會澱積,實現與頂部N+摻雜多晶矽或非晶矽層之間之絕緣。 As shown in Figure 109C, it may be additionally formed as shown in Figure 109B Si/SiO2 layers, such as the second Si/SiO2 layer 10925 and the third Si/SiO2 layer 10927. An oxide layer 10929 may be deposited to provide insulation from the top N+ doped polysilicon or amorphous silicon layer.

如圖109D所示,可進行快速高熱退火(RTA),使第一層Si/SiO2層10923、第二次Si/SiO2層10925和第三層Si/SiO2層10927之N+摻雜多晶矽層或非晶矽層10906晶化,形成晶化之N+矽層10916。在RTA過程中溫度可高達800℃。或者,也可單獨採取光學退火(比如鐳射退火),或者同時採取光學退火和RTA,或者採取其他之退火工藝。 As shown in Figure 109D, rapid high thermal annealing (RTA) can be performed to make the N+ doped polysilicon layer of the first Si/SiO2 layer 10923, the second Si/SiO2 layer 10925 and the third Si/SiO2 layer 10927 or non- The crystalline silicon layer 10906 is crystallized to form a crystallized N+ silicon layer 10916 . The temperature can be as high as 800°C during RTA. Alternatively, optical annealing (such as laser annealing) can be used alone, or optical annealing and RTA can be used at the same time, or other annealing processes can be used.

如圖109E所示,氧化層10929、第三層Si/SiO2層10927、第二層Si/SiO2層10925和第一層Si/SiO2層10923可進行光刻和電漿體/反應式離子蝕刻,形成存儲晶片結構之一部分。存儲晶片結構現在已包含多層晶化之N+矽區10926(前面晶化之N+矽層10916)和氧化層區10922。 As shown in Figure 109E, the oxide layer 10929, the third Si/SiO2 layer 10927, the second Si/SiO2 layer 10925 and the first Si/SiO2 layer 10923 can be subjected to photolithography and plasma/reactive ion etching, Forms part of a memory wafer structure. The memory chip structure now includes multilayer crystallized N+ silicon region 10926 (previously crystallized N+ silicon layer 10916 ) and oxide layer region 10922 .

如圖109F所示,柵極電介質和柵電極材料可能會澱積,可透過化學-機械打磨(CMP)使其平面化,然後可進行光刻和電漿體/反應式離子蝕刻,以形成柵極電介質區10928。柵極電介質區10928可能與柵電極10930(如圖所示)自對齊,並被柵電極10930覆蓋,或者可能充分地覆蓋住整個N+矽區10126和氧化層區10922多層結構。柵極堆疊層(包含柵電極10930和柵極電介質區10928)由柵極電介質區(例如高熱氧化層)和柵電極材料(如多晶矽)組成。或者,柵極電介質可選擇與具體之柵極金屬之 功函數相匹配之原子層澱積(ALD)材料,符合前文所述之高-k金屬柵極工藝方案之行業標準。此外,柵極電介質可透過快速高熱氧化(RTO)形成。快速熱氧化是矽表面之一種低溫氧化澱積或低溫微波電漿體氧化之過程,最終可澱積成柵極電極,例如鎢電極或鋁電極。 As shown in Figure 109F, gate dielectric and gate electrode material may be deposited, planarized by chemical-mechanical polishing (CMP), and then photolithography and plasma/reactive ion etching may be performed to form the gate electrode. Pole dielectric region 10928. Gate dielectric region 10928 may be self-aligned with and covered by gate electrode 10930 (as shown), or may substantially cover the entire N+ silicon region 10126 and oxide region 10922 multilayer structure. The gate stack layer (comprising gate electrode 10930 and gate dielectric region 10928) consists of a gate dielectric region (eg, high thermal oxide) and a gate electrode material (eg, polysilicon). Alternatively, the gate dielectric can be chosen to match the specific gate metal Atomic layer deposition (ALD) materials with work function matching that meet industry standards for high-k metal gate process solutions as described above. In addition, the gate dielectric can be formed by rapid thermal oxidation (RTO). Rapid thermal oxidation is a process of low-temperature oxidation deposition or low-temperature microwave plasma oxidation on the surface of silicon, which can eventually be deposited as a gate electrode, such as a tungsten electrode or an aluminum electrode.

如圖109G所示,間隙填充氧化層10932可覆蓋整個結構,可透過化學-機械打磨使其平面化。為清晰起見,圖中氧化層10932顯示為透明層。除此之外,還有文字線區(WL)10950、柵電極10930、源極線區(SL)10952和所示之晶化之N+矽區10926。 As shown in Figure 109G, a gap-fill oxide layer 10932 may cover the entire structure, which may be planarized by chemical-mechanical polishing. For clarity, the oxide layer 10932 is shown as a transparent layer in the figure. In addition, there are word line regions (WL) 10950, gate electrodes 10930, source line regions (SL) 10952 and crystallized N+ silicon regions 10926 as shown.

如圖109H所示,位線(BL)接點10934可透過氧化層10932、三個晶化之N+矽區10926和相關之氧化層垂直絕緣區進行光刻和電漿體/反應式離子蝕刻,以便充分與所有存儲層垂直連接,隨後進行光阻去除。阻變記憶體材料10938,比如二氧化鉿或氧化鈦,接下來可能會澱積,最好為原子層澱積(ALD)。阻變記憶體組件之電極接下來可能會被ALD澱積,形成電極/BL接點10934。應對多餘之澱積材料進行打磨,使之與氧化層10932頂部或頂部下方處於同一表面。每個帶有阻變材料10938之BL接點10934可充分與所有存儲層共用,如圖109H中所示之三層存儲層。 As shown in Figure 109H, the bit line (BL) contact 10934 can be photolithographically and plasma/reactive ion etched through the oxide layer 10932, the three crystallized N+ silicon regions 10926 and the associated oxide layer vertical isolation regions, In order to fully connect vertically to all memory layers, followed by photoresist removal. The resistive memory material 10938, such as hafnium dioxide or titanium oxide, may then be deposited, preferably by atomic layer deposition (ALD). The electrodes of the RRAM device may then be deposited by ALD to form electrode/BL contacts 10934 . Excess deposited material should be polished so that it is on the same surface as or below the top of the oxide layer 10932. Each BL contact 10934 with resistive material 10938 can be fully shared with all storage layers, such as the three storage layers shown in FIG. 109H.

如圖109I所示,可形成BL金屬線10936,並與相關之帶有阻變材料10938之BL接點10934連接在一起。在存儲陣列邊緣可形成WL和SL之接點和相關之金屬佈線(未顯 示)。可能會形成穿層過孔10960(未顯示),透過受主晶圓金屬連接焊盤10980(未顯示)使BL、SL和WL之金屬化區域與受主基板週邊電路發生電耦合。 As shown in FIG. 109I , BL metal lines 10936 can be formed and connected to the associated BL contacts 10934 with resistive material 10938 . Contacts of WL and SL and associated metal wiring (not shown) may be formed at the edge of the memory array. Show). Through-layer vias 10960 (not shown) may be formed to electrically couple the metallized areas of BL, SL and WL to the acceptor substrate peripheral circuitry through acceptor wafer metal connection pads 10980 (not shown).

圖109J之橫截面剖視圖二見圖109J1,圖109J之橫截面剖視圖三見圖109J2。圖101J1顯示了BL金屬線10936、氧化層10932、BL接點/電極10934、阻變材料10938、WL區10950、柵極電介質10928、晶化之N+矽區10926和週邊電路基板10902。BL接點/電極10934與阻變材料10938之三個水平面之其中一個邊相連。阻變材料10938之另外一邊與晶化之N+區10196相連。BL金屬線10936、氧化層10932、柵電極10930、柵極電介質10928、晶化之N+矽區10926、夾層氧化區(OX)和週邊電路基板10902見圖109J2。柵電極10930在六個晶化之N+矽區10926中都很常見,它們形成了六個雙面柵控無結型電晶體,作為記憶體選擇電晶體。 The second cross-sectional view of Figure 109J is shown in Figure 109J1, and the third cross-sectional view of Figure 109J is shown in Figure 109J2. Figure 101J1 shows BL metal line 10936, oxide layer 10932, BL contact/electrode 10934, resistive switch material 10938, WL region 10950, gate dielectric 10928, crystallized N+ silicon region 10926 and peripheral circuit substrate 10902. The BL contact/electrode 10934 is connected to one of the three horizontal planes of the resistive material 10938 . The other side of the resistive material 10938 is connected to the crystallized N+ region 10196 . BL metal line 10936, oxide layer 10932, gate electrode 10930, gate dielectric 10928, crystallized N+ silicon region 10926, interlayer oxide region (OX) and peripheral circuit substrate 10902 are shown in FIG. 109J2. Gate electrodes 10930 are common in the six crystallized N+ silicon regions 10926, which form six double-sided gate-controlled junctionless transistors as memory select transistors.

如圖109K所示,在第一層Si/SiO2層10923上之帶有典型之雙面柵控無結型電晶體可能包含晶化之N+矽區10926(起到源極、汲極和電晶體溝槽之作用)和雙柵電極10930(帶相應之柵極絕緣層10928)。電晶體藉由氧化層10908可與下方絕緣。 As shown in FIG. 109K, a typical double-sided gate-controlled junctionless transistor on the first Si/SiO2 layer 10923 may include crystallized N+ silicon regions 10926 (serving as source, drain and transistor trench) and double gate electrode 10930 (with corresponding gate insulating layer 10928). The transistors are insulated from below by the oxide layer 10908 .

該流程可形成電阻性多層或3D存儲陣列,每個存儲層不使用附加掩蔽工序。該存儲層使用無結型多晶矽電晶體,其電阻性記憶組件與選擇電晶體串聯。透過層切晶圓大小之摻雜多晶矽層之方式建設存儲陣列。同時,該3D存 儲陣列與下方之多金屬層半導體設備連接起來。 The process can form resistive multilayer or 3D memory arrays without additional masking steps for each memory layer. The storage layer uses a junctionless polysilicon transistor, and its resistive memory component is connected in series with the selection transistor. The memory array is constructed by layering wafer-sized doped polysilicon layers. At the same time, the 3D storage The storage array is connected to the underlying multi-metal layer semiconductor device.

具有一般技藝之人可將圖109A至圖109K中提到之例子僅作為典型範例看待,並非按比例縮小。技藝高超之人可考量更多變化情況。比如,在圖109C中之各層Si/SiO2層形成之後,可對圖109D中之N+摻雜多晶矽層或非晶矽層10906進行RTA和/或光學退火。此外,N+摻雜多晶矽層或非晶矽層10906可摻雜P+,或同時加入摻雜物和其他之多晶矽網路改性劑,以增強RTA或光學退火效果和隨後之晶化效果,降低N+矽層10916之電阻率。此外,在補償互連電阻時,晶化之N+層之摻雜物可能會略微有所不同。此外,雙柵控3D電阻性記憶體之每個柵極可獨立控制,以更好地控制存儲晶片。透過閱讀本說明書,可使技藝高超之人想起如何在本發明範圍內對其他地方進行修改。因此,本發明僅受限於附加之權利要求。 One of ordinary skill would consider the examples mentioned in FIGS. 109A-109K to be representative examples only, and not scaled down. A skilled person can consider more variations. For example, RTA and/or optical annealing can be performed on the N+ doped polysilicon layer or amorphous silicon layer 10906 in FIG. 109D after the formation of the Si/SiO2 layers in FIG. 109C. In addition, the N+ doped polysilicon layer or amorphous silicon layer 10906 can be doped with P+, or dopants and other polysilicon network modifiers can be added at the same time to enhance the RTA or optical annealing effect and subsequent crystallization effect, and reduce the N+ Resistivity of silicon layer 10916. In addition, the dopant of the crystallized N+ layer may vary slightly when compensating for interconnect resistance. In addition, each gate of dual-gated 3D resistive memory can be independently controlled to better control the memory chip. A reading of this specification will allow the skilled person to recall how to make modifications elsewhere within the scope of the invention. Accordingly, the invention is limited only by the appended claims.

如圖110A至110J所示,可建設在每個存儲層不帶附加掩蔽工序之電阻性3D記憶體之另一個案例,其方法適用於生產3D IC。該3D記憶體使用多晶矽無結型電晶體。這種電晶體使用正或副閾值電壓和電阻性記憶組件,與選擇電晶體或存取電晶體串聯。它有助於形成週邊電路層或者將電路層層切到3D存儲陣列之頂部。 As shown in Figures 110A to 110J, another example of a resistive 3D memory that can be built in each memory layer without additional masking process, the method is suitable for the production of 3D IC. The 3D memory uses polysilicon junctionless transistors. This transistor uses a positive or secondary threshold voltage and a resistive memory component in series with a select or access transistor. It facilitates the formation of peripheral circuit layers or layer cutting of circuit layers on top of 3D memory arrays.

如圖110A所示,二氧化矽層11004可能會在矽基板11002之頂部澱積或生長。 A silicon dioxide layer 11004 may be deposited or grown on top of the silicon substrate 11002 as shown in FIG. 110A .

如圖110B所示,N+摻雜多晶矽層或非晶矽層11006可能會澱積。可採用化學汽相澱積法(例如低壓化學氣相澱 積--LPCVD或電漿體增強化學氣相澱積--PECVD或其他之工藝方法)使非晶矽層或多晶矽層11006澱積。在澱積時可摻雜N+摻雜物,例如砷或磷;也可在澱積時不摻雜,澱積後再進行摻雜,例如採用離子注入或PLAD(電漿體摻雜)技術。然後可使二氧化矽層11020澱積或生長。現在就形成了第一層Si/SiO2層11023,包含N+摻雜多晶矽層或非晶矽層11006和二氧化矽層11020。 As shown in FIG. 110B, an N+ doped polysilicon layer or an amorphous silicon layer 11006 may be deposited. Chemical vapor deposition (e.g. low pressure chemical vapor deposition deposition - LPCVD or plasma enhanced chemical vapor deposition - PECVD or other process methods) to deposit the amorphous silicon layer or polysilicon layer 11006 . N+ dopant, such as arsenic or phosphorus, can be doped during deposition; it can also be undoped during deposition, and then doped after deposition, for example, using ion implantation or PLAD (plasma doping) technology. A silicon dioxide layer 11020 may then be deposited or grown. Now the first Si/SiO2 layer 11023 is formed, including N+ doped polysilicon layer or amorphous silicon layer 11006 and silicon dioxide layer 11020 .

如圖110C所示,可能會額外形成圖110B中所示之Si/SiO2層,比如第二層Si/SiO2層11025和第三層Si/SiO2層11027。氧化層11029可能會澱積,實現與頂部N+摻雜多晶矽或非晶矽層之間之絕緣。 As shown in FIG. 110C, Si/SiO2 layers shown in FIG. 110B may be additionally formed, such as a second Si/SiO2 layer 11025 and a third Si/SiO2 layer 11027. An oxide layer 11029 may be deposited to provide insulation from the top N+ doped polysilicon or amorphous silicon layer.

如圖110D所示,可進行快速高熱退火(RTA),使第一層Si/SiO2層11023、第二次Si/SiO2層11025和第三層Si/SiO2層11027之N+摻雜多晶矽層或非晶矽層11006晶化,形成晶化之N+矽層11016。或者,也可單獨採取光學退火(比如鐳射退火),或者同時採取光學退火和RTA,或者採取其他之退火工藝。在RTA過程中溫度可高達700℃,甚至可以達到1400℃。由於這些晶化之N+矽層下方沒有電路或金屬化層,在退火過程中可使用很高之溫度(比如1400℃),這樣就使得多晶矽之品質非常好,晶粒邊界很少,載子靠近單晶矽之靈活性更高。 As shown in Figure 110D, rapid high thermal annealing (RTA) can be performed to make the N+ doped polysilicon layer of the first Si/SiO2 layer 11023, the second Si/SiO2 layer 11025 and the third Si/SiO2 layer 11027 or non- The crystalline silicon layer 11006 is crystallized to form a crystallized N+ silicon layer 11016 . Alternatively, optical annealing (such as laser annealing) can be used alone, or optical annealing and RTA can be used at the same time, or other annealing processes can be used. During the RTA process the temperature can be as high as 700°C and can even reach 1400°C. Since there is no circuit or metallization layer under these crystallized N+ silicon layers, very high temperature (such as 1400°C) can be used in the annealing process, so that the quality of polysilicon is very good, there are few grain boundaries, and the carriers are close to each other. Monocrystalline silicon is more flexible.

如圖110E所示,氧化層11029、第三層Si/SiO2層11027、第二層Si/SiO2層11025和第一層Si/SiO2層11023可進行光刻和電漿體/反應式離子蝕刻,形成存儲晶片結構 之一部分。存儲晶片結構現在已包含多層晶化之N+矽區11026(前面晶化之N+矽層11016)和氧化層區11022。 As shown in Figure 110E, the oxide layer 11029, the third Si/SiO2 layer 11027, the second Si/SiO2 layer 11025 and the first Si/SiO2 layer 11023 can be subjected to photolithography and plasma/reactive ion etching, memory chip structure one part. The memory chip structure now includes multilayer crystallized N+ silicon region 11026 (previously crystallized N+ silicon layer 11016 ) and oxide layer region 11022 .

如圖110F所示,柵極電介質和柵電極材料可能會澱積,可透過化學-機械打磨(CMP)使其平面化,然後可進行光刻和電漿體/反應式離子蝕刻,以形成柵極電介質區11028。柵極電介質區11028可能與柵電極11030(如圖所示)自對齊,並被柵電極11030覆蓋,或者可能覆蓋住整個晶化之N+矽區11026和氧化層區11022多層結構。柵極堆疊層(包含柵電極11030和柵極電介質11028)由柵極電介質(例如高熱氧化層)和柵電極材料(如多晶矽)組成。或者,柵極電介質可選擇與具體之柵極金屬之功函數相匹配之原子層澱積(ALD)材料,符合前文所述之高-k金屬柵極工藝方案之行業標準。此外,柵極電介質可透過快速高熱氧化(RTO)形成。快速熱氧化是矽表面之一種低溫氧化澱積或低溫微波電漿體氧化之過程,最終可澱積成柵電極,例如鎢電極或鋁電極。 As shown in Figure 110F, the gate dielectric and gate electrode material may be deposited, planarized by chemical-mechanical polishing (CMP), and then photolithography and plasma/reactive ion etching may be performed to form the gate electrode. Pole dielectric region 11028. The gate dielectric region 11028 may be self-aligned with and covered by the gate electrode 11030 (as shown), or may cover the entire crystallized N+ silicon region 11026 and oxide region 11022 multilayer structure. The gate stack layer (comprising gate electrode 11030 and gate dielectric 11028) consists of a gate dielectric (eg, high thermal oxide) and a gate electrode material (eg, polysilicon). Alternatively, the gate dielectric can be selected from an atomic layer deposition (ALD) material that matches the work function of the specific gate metal, in line with the industry standard for high-k metal gate process solutions described above. In addition, the gate dielectric can be formed by rapid thermal oxidation (RTO). Rapid thermal oxidation is a process of low-temperature oxidation deposition or low-temperature microwave plasma oxidation on the surface of silicon, which can eventually be deposited as a gate electrode, such as a tungsten electrode or an aluminum electrode.

如圖110G所示,間隙填充氧化層11032可覆蓋整個結構,可透過化學-機械打磨使其平面化。為清晰起見,圖中氧化層11032顯示為透明層。除此之外,還有文字線區(WL)11050、柵電極11030、源極線區(SL)11052和所示之晶化之N+矽區11026。 As shown in FIG. 110G, a gap-fill oxide layer 11032 may cover the entire structure, which may be planarized by chemical-mechanical polishing. For clarity, the oxide layer 11032 is shown as a transparent layer in the figure. In addition, there are word line regions (WL) 11050, gate electrodes 11030, source line regions (SL) 11052 and crystallized N+ silicon regions 11026 as shown.

如圖110H所示,位線(BL)接點11034可透過氧化層11032、三個晶化之N+矽區11026和相關之氧化層垂直絕緣區進行光刻和電漿體/反應式離子蝕刻,以便與所有之 存儲層垂直連接。BL接點11034透過光阻去除之方法進行處理。阻變記憶體材料11038,比如二氧化鉿或氧化鈦,接下來可能會澱積,最好為原子層澱積(ALD)。阻變記憶體組件之電極接下來可能會被ALD澱積,形成電極/BL接點11034。應對多餘之澱積材料進行打磨,使之與氧化層11032頂部或頂部下方處於同一表面。每個帶有阻變材料11038之BL接點11034可充分與所有之存儲層共用,如圖110H中所示之三層存儲層。 As shown in Figure 110H, the bit line (BL) contact 11034 can be photolithographically and plasma/reactive ion etched through the oxide layer 11032, the three crystallized N+ silicon regions 11026 and the associated oxide layer vertical isolation regions, so as to be with all The storage layer is connected vertically. BL contact 11034 is processed by photoresist stripping. A resistive memory material 11038, such as hafnium dioxide or titanium oxide, may then be deposited, preferably by atomic layer deposition (ALD). The electrodes of the RRAM device may then be deposited by ALD to form electrode/BL contacts 11034 . Excess deposited material should be polished so that it is on the same surface as or below the top of the oxide layer 11032. Each BL contact 11034 with resistive material 11038 can be fully shared with all storage layers, such as the three storage layers shown in FIG. 110H.

如圖110I所示,可形成BL金屬線11036,並與相關之帶有阻變材料11038之BL接點11034連接在一起。在存儲陣列邊緣可形成WL和SL之接點和相關之金屬佈線(未顯示)。 As shown in FIG. 110I , a BL metal line 11036 can be formed and connected to a related BL contact 11034 with a resistive material 11038 . Contacts for WL and SL and associated metal wiring (not shown) may be formed at the edge of the memory array.

如圖110J所示,可先使用前文所述之方法(例如離子切割和取代柵極)建設週邊電路11078,接著再層切到存儲陣列,然後再形成穿層過孔(未顯示),以便使週邊電路與存儲陣列BL、WL、SL和其他之連接線發生電耦合,比如電源線和接地線。或者,可利用層切晶圓大小之摻雜層和隨後之處理過程(例如前文所述之無結型、凹道排列電晶體、V形槽或雙極性電晶體成型過程)建設週邊電路,並直接與存儲陣列和矽基板11002對齊。 As shown in FIG. 110J, the peripheral circuit 11078 can be constructed using the methods described above (such as ion dicing and replacing the gate), and then layer cut to the memory array, and then form through-layer vias (not shown), so that the The peripheral circuits are electrically coupled to the memory arrays BL, WL, SL and other connection lines, such as power lines and ground lines. Alternatively, peripheral circuits can be built using layer-cut wafer-sized doped layers and subsequent processing (such as junctionless, trench-arranged transistors, V-groove, or bipolar transistor molding processes as described above), and Align directly with memory array and silicon substrate 11002.

該流程可形成電阻性多層或3D存儲陣列,每個存儲層不使用附加掩蔽工序。該存儲層使用無結型多晶矽電晶體,其電阻性記憶組件與選擇電晶體串聯。透過層切晶圓大小之摻雜多晶矽層之方式建設存儲陣列。同時,該3D存 儲陣列與上方之多金屬層半導體設備或週邊電路連接起來。 The process can form resistive multilayer or 3D memory arrays without additional masking steps for each memory layer. The storage layer uses a junctionless polysilicon transistor, and its resistive memory component is connected in series with the selection transistor. The memory array is constructed by layering wafer-sized doped polysilicon layers. At the same time, the 3D storage The storage array is connected with the upper multi-metal layer semiconductor device or peripheral circuit.

具有一般技藝之人可將圖110A至圖110J中提到之例子僅作為典型範例看待,並非按比例縮小。技藝高超之人可考量更多變化情況。比如,在圖110C中之各層Si/SiO2層形成之後,可對圖110D中之N+摻雜多晶矽層或非晶矽層11006進行RTA和/或光學退火。此外,N+摻雜多晶矽層或非晶矽層11006可摻雜P+,或同時加入摻雜物和其他之多晶矽網路改性劑,以增強RTA或光學退火效果和隨後之晶化效果,降低N+矽層11016之電阻率。此外,在補償互連電阻時,晶化之N+層之摻雜物可能會略微有所不同。此外,雙柵控3D電阻性記憶體之每個柵極可獨立控制,以更好地控制存儲晶片。而且,透過選擇正確之存儲層電晶體和存儲層電線材料(比如使用鎢絲和在配線加工過程中能夠耐高溫之其他材料),可在高溫(超過700℃)下加工標準之CMOS電晶體,形成週邊電路11078。透過閱讀本說明書,可使技藝高超之人想起如何在本發明範圍內對其他地方進行修改。因此,本發明僅受限於附加之權利要求。 One of ordinary skill would consider the examples mentioned in FIGS. 110A-110J to be representative examples only and not to scale. A skilled person can consider more variations. For example, RTA and/or optical annealing can be performed on the N+ doped polysilicon layer or amorphous silicon layer 11006 in FIG. 110D after the formation of the Si/SiO2 layers in FIG. 110C. In addition, the N+ doped polysilicon layer or amorphous silicon layer 11006 can be doped with P+, or dopants and other polysilicon network modifiers can be added at the same time to enhance the RTA or optical annealing effect and subsequent crystallization effect, and reduce the N+ Resistivity of silicon layer 11016. In addition, the dopant of the crystallized N+ layer may vary slightly when compensating for interconnect resistance. In addition, each gate of dual-gated 3D resistive memory can be independently controlled to better control the memory chip. Moreover, standard CMOS transistors can be processed at high temperatures (over 700°C) by selecting the correct storage layer transistors and storage layer wire materials (such as using tungsten wire and other materials that can withstand high temperatures during wiring processing), A peripheral circuit 11078 is formed. A reading of this specification will allow the skilled person to recall how to make modifications elsewhere within the scope of the invention. Accordingly, the invention is limited only by the appended claims.

單塊3D DRAM是本發明之另外一種案例,我們稱之為NuDRAM。它可能使用本檔中提到之層切和切割法。這種方法可提供優質單晶矽,有效熱量變化較小,是現有技術之一次質之飛躍。 Monolithic 3D DRAM is another example of the present invention, which we call NuDRAM. It may use the layering and cutting methods mentioned in this document. This method can provide high-quality monocrystalline silicon with less change in effective heat, which is a qualitative leap in the existing technology.

採取圖88(A)至(F)中所示之流程可建設本發明之一個案例。圖88(A)描述了本工藝之第一個步驟。可 向p-晶圓8801中注入n型摻雜物,形成n+層8802,接下來可進行RTA。n+層8802也可以採取類晶生長之方法形成。 An example of the present invention can be constructed by taking the flow shown in Fig. 88(A) to (F). Figure 88(A) depicts the first step of the process. Can Implant n-type dopants into the p-wafer 8801 to form an n+ layer 8802, followed by RTA. The n+ layer 8802 can also be formed by the method of crystal-like growth.

圖88(B)顯示了本工藝之下一個步驟。可在p-區8801之一定深度處向晶圓中注入氫。氫之最終位置如虛線8803所示。 Figure 88(B) shows the next step in the process. Hydrogen can be implanted into the wafer at a certain depth in the p-region 8801 . The final position of the hydrogen is shown by dashed line 8803.

圖88(C)描述了本工藝之下一個步驟。使用黏合劑將晶圓黏貼到晶圓臨時載子8804上。例如,為了達到這個目的,我們可以使用杜邦公司生產之聚醯亞胺黏合劑將晶圓黏貼到玻璃做之晶圓臨時載子8804上。然後可採用本檔中所述之切割法在氫平面8803上對晶圓進行切割。切割之後,採取化學-機械打磨法對切割表面進行打磨,從而使氧化層8805在該表面上澱積。所有步驟都徹底完成之後之晶圓結構如圖88(C)所示。 Figure 88(C) depicts the next step in the process. The wafer is attached to the wafer temporary carrier 8804 using an adhesive. For this purpose, for example, we can bond the wafer to the wafer temporary carrier 8804 made of glass using a polyimide adhesive from DuPont. The wafer can then be diced on the hydrogen plane 8803 using the dicing method described in this document. After dicing, chemical-mechanical polishing is used to polish the cut surface so that an oxide layer 8805 is deposited on the surface. The wafer structure after all steps are fully completed is shown in FIG. 88(C).

圖88(D)顯示了本工藝之下一個步驟。現在可使用帶有DRAM週邊電路8806(例如讀出放大器、行解碼器等)之晶圓作為基極。在表面8807上使用氧化物-氧化物黏結之方式就可以將圖88(C)中之晶圓黏貼在該基極之頂部。現在可以將臨時載子8804移除了。然後,就可以進行掩膜、蝕刻和氧化操作了,以便確定好擴散行,被類似於圖89(B)中之8905氧化層絕緣。擴散行和絕緣行可與下方之週邊電路8806對齊。絕緣區成型後,可透過蝕刻、然後澱積柵極電介質8809和柵電極8808建設RCAT(凹道排列電晶體)。圖67之描述中進一步對該程式進行了解釋。柵電極掩膜可與下方之週邊電路8806對齊。氧化層 8810可能會澱積,並透過化學-機械打磨法進行打磨。 Figure 88(D) shows the next step in the process. A wafer with DRAM peripheral circuits 8806 (eg sense amplifiers, row decoders, etc.) can now be used as the base. The wafer in Figure 88(C) can be attached on top of the base using oxide-oxide bonding on surface 8807. The temporary carrier 8804 can now be removed. Masking, etching and oxidation operations can then be performed to define diffusion rows, insulated by an oxide layer similar to 8905 in Figure 89(B). The diffusion and isolation rows may be aligned with the underlying peripheral circuitry 8806 . After the insulating region is formed, RCAT (Recessed Array Transistor) can be constructed by etching and then depositing gate dielectric 8809 and gate electrode 8808 . This procedure is further explained in the description of Figure 67. The gate electrode mask can be aligned with the underlying peripheral circuitry 8806 . oxide layer 8810 may be deposited and polished by chemical-mechanical polishing.

圖88(E)顯示了本工藝之下一個步驟。採用圖88(A)-(D)中類似之步驟可在第一層RCAT層8811之頂部形成第二層RCAT層8812。多次重複上面之步驟,可得到理想之多層3D DRAM。 Figure 88(E) shows the next step in the process. A second RCAT layer 8812 can be formed on top of the first RCAT layer 8811 using steps similar to those in FIGS. 88(A)-(D). By repeating the above steps several times, an ideal multi-layer 3D DRAM can be obtained.

圖88(F)描述了本工藝之下一個步驟。可完全穿過所有之堆疊層將通孔蝕刻至源極8814和汲極8815。由於在與週邊電路8806對齊之過程中還要重複操作本步驟,需要設定一個蝕刻停蝕層,否則就不應當在指定之蝕刻位置下方放置易損壞組件。這就類似于傳統之DRAM陣列。在傳統之DRAM陣列中,多個RCAT電晶體之柵極8816透過垂直於圖88中平面之多晶矽導線或金屬線連接起來。連接柵電極可形成類似於圖89A-D中說明之文字線。版圖將展開多層DRAM結構之文字線,這樣每層上都有一個垂直接觸孔連線,使週邊電路8806可單獨控制每層之文字線。接著可使用重摻雜之多晶矽8813進行填充。可採用低溫(低於400℃)工藝(例如PECVD)建設重摻雜之多晶矽8813。重摻雜之多晶矽8813不僅能夠改良3D DRAM之多個源極、汲極和文字線之接點,而且能夠起到隔開相鄰p-層8817和8818之作用。或者,也可以使用氧化層進行隔離。接著可建設多層互聯層和通孔,形成位線8815和源極線8814,完成整個DRAM陣列。RCAT電晶體如圖88所示。還可利用類似於圖88A-F所示之工藝流程建設其他類型之低溫堆疊電晶體。例如,可建設V形槽電晶體和本發明中 其他案例中所描述的其他電晶體。 Figure 88(F) depicts the next step in the process. Vias may be etched completely through all stack layers to source 8814 and drain 8815. Since this step is repeated during alignment with the peripheral circuit 8806, an etch stop layer is required, otherwise fragile components should not be placed under the designated etch position. This is similar to a traditional DRAM array. In a conventional DRAM array, gates 8816 of multiple RCAT transistors are connected by polysilicon wires or metal lines perpendicular to the plane in FIG. 88 . Connecting the gate electrodes can form word lines similar to those illustrated in Figures 89A-D. The layout will expand the word lines of the multi-layer DRAM structure, so that there is a vertical contact hole connection on each layer, so that the peripheral circuit 8806 can individually control the word lines of each layer. Then it can be filled with heavily doped polysilicon 8813. The heavily doped polysilicon 8813 can be constructed by a low temperature (less than 400°C) process (such as PECVD). The heavily doped polysilicon 8813 can not only improve the contacts of multiple sources, drains and word lines of 3D DRAM, but also can separate adjacent p-layers 8817 and 8818. Alternatively, an oxide layer can also be used for isolation. Then, multi-layer interconnection layers and through holes can be built to form bit lines 8815 and source lines 8814 to complete the entire DRAM array. The RCAT transistor is shown in Figure 88. Other types of low temperature stacked transistors can also be constructed using a process flow similar to that shown in Figures 88A-F. For example, V-groove transistors can be constructed and in the present invention Other transistors described in other cases.

圖89(A)-(D)分別展示了圖88(A)-(F)中描述之NuDRAM陣列其中一部分之側視圖、佈局圖和示意圖。圖89(A)展示了NuDRAM陣列之一個特定之剖視圖。位線(BL)8902可在垂直於文字線(WL)8904和源極線(SL)8903之方向運行。 Figures 89(A)-(D) show a side view, layout and schematic diagram, respectively, of a portion of the NuDRAM array depicted in Figures 88(A)-(F). Figure 89(A) shows a specific cross-sectional view of a NuDRAM array. Bit lines (BL) 8902 may run in a direction perpendicular to word lines (WL) 8904 and source lines (SL) 8903 .

圖89(B)顯示了從虛線表示之平面上所看到之剖視圖。氧化絕緣區8905可將相鄰之電晶體之p-層8906隔開。本質上來說,WL8907可包含連接在一起之各個電晶體之柵電極。 Fig. 89(B) shows a cross-sectional view seen from a plane indicated by a dotted line. The oxide insulating region 8905 can separate the p-layer 8906 of adjacent transistors. Essentially, the WL8907 can consist of the gate electrodes of individual transistors connected together.

圖89(C)顯示了本陣列之佈局。WL配線8908和SL配線8909可能與BL配線8910垂直。NuDRAM陣列示意圖(圖89(D))揭示了WL、BL和SL在陣列層次上之連接情況。 Figure 89(C) shows the layout of this array. WL wiring 8908 and SL wiring 8909 may be perpendicular to BL wiring 8910. The schematic diagram of the NuDRAM array (Fig. 89(D)) reveals the connection of WL, BL and SL at the array level.

圖90(A)-(F)描述了本發明之另外一種案例。圖90(A)描述了本工藝之第一個步驟。p-晶圓9001包含n+類晶生長層9002和在n+類晶生長層上方生長之p-類晶生長層9003。另外,這些層也在透過注入之方式形成。氧化層9004也可能在晶圓上方生長或澱積。 Figure 90(A)-(F) depicts another example of the present invention. Figure 90(A) depicts the first step of the process. The p-wafer 9001 comprises an n+ quasi-like growth layer 9002 and a p- quasi-like growth layer 9003 grown over the n+ quasi-like growth layer. In addition, these layers are also formed by implantation. An oxide layer 9004 may also be grown or deposited over the wafer.

圖90(B)顯示了本工藝之下一個步驟。可在n+區9002之一定深度處向晶圓中注入氫H+或其他之原子種類。氫之最終位置如虛線9005所示。 Figure 90(B) shows the next step in the process. Hydrogen H+ or other atomic species can be implanted into the wafer at a certain depth in the n+ region 9002 . The final position of the hydrogen is shown by dashed line 9005.

圖90(C)描述了本工藝之下一個步驟。透過氧化物之間黏結之方式將晶圓翻轉並黏貼到帶DRAM週邊電路 9006之晶圓上。然後可採用本檔中所述之低溫(低於400℃)切割法在氫平面9005上對晶圓進行切割。切割之後,可採取化學-機械打磨之方式對切割之後之表面進行打磨。 Figure 90(C) describes the next step in the process. Flip the wafer and stick it to the peripheral circuit with DRAM by bonding between oxides 9006 on the wafer. The wafer can then be diced on the hydrogen plane 9005 using the low temperature (below 400°C) dicing method described in this document. After cutting, chemical-mechanical polishing can be used to polish the cut surface.

如圖90(D)所示,可以進行掩膜、蝕刻和低溫氧化層澱積操作了,以便確定好被上述氧化層絕緣之擴散行。上述擴散行和絕緣行可與下方之週邊電路9006對齊。絕緣區成型後,可透過掩膜、蝕刻、澱積柵極電介質9009和柵電極9008建設RCAT(凹道排列電晶體)。圖67之描述中進一步對該程式進行了解釋。上述柵極可與下方之週邊電路9006對齊。氧化層9010可能會澱積,並透過化學-機械打磨法進行打磨。 As shown in Fig. 90(D), masking, etching and low temperature oxide deposition operations can be performed to define the diffusion rows insulated by the above oxide layer. The aforementioned diffusion row and isolation row may be aligned with the peripheral circuit 9006 below. After the insulating region is formed, a RCAT (recessed array transistor) can be constructed through masking, etching, and depositing gate dielectric 9009 and gate electrode 9008 . This procedure is further explained in the description of Figure 67. The above-mentioned gates can be aligned with the peripheral circuit 9006 below. An oxide layer 9010 may be deposited and polished by chemical-mechanical polishing.

圖90(E)顯示了本工藝之下一個步驟。採用圖90(A)-(D)中類似之步驟可在第一層RCAT層9011之頂部形成第二層RCAT層9012。多次重複上面之步驟,可得到理想之多層3D DRAM。 Figure 90(E) shows the next step in the process. A second RCAT layer 9012 can be formed on top of the first RCAT layer 9011 using steps similar to those in FIGS. 90(A)-(D). By repeating the above steps several times, an ideal multi-layer 3D DRAM can be obtained.

圖90(F)描述了本工藝之下一個步驟。可完全穿過所有之堆疊層將通孔蝕刻至源極和汲極連接線。這就類似于傳統之DRAM陣列。在傳統之DRAM陣列中,多個RCAT電晶體之柵電極9016透過垂直於圖90中平面之多晶矽導線連接起來。連接柵電極可形成類似於文字線。版圖將展開多層DRAM結構之文字線,這樣每層上都有一個垂直孔,使週邊電路9006可單獨控制每層之文字線。接著可使用重摻雜之多晶矽9013進行填充。可採用低溫(低於400℃) 工藝(例如PECVD)建設重摻雜矽9013。接著可建設多層互聯層和通孔,形成位線9015和源極線9014,完成整個DRAM陣列。圖90中描述之NuDRAM之陣列結構類似於圖89中之陣列。RCAT電晶體如圖90所示。還可利用類似於圖90所示之工藝流程建設其他類型之低溫堆疊電晶體。例如,可建設V形槽電晶體和前文所描述之本發明中其他案例中其他電晶體。 Figure 90(F) depicts the next step in the process. Vias can be etched completely through all stacked layers to source and drain connection lines. This is similar to a traditional DRAM array. In a conventional DRAM array, gate electrodes 9016 of multiple RCAT transistors are connected by polysilicon wires perpendicular to the plane in FIG. 90 . Connecting the gate electrodes can be formed similar to word lines. The layout will expand the word lines of the multi-layer DRAM structure so that there is a vertical hole on each layer, so that the peripheral circuit 9006 can individually control the word lines of each layer. Then it can be filled with heavily doped polysilicon 9013 . Low temperature (less than 400°C) can be used process (eg PECVD) to build heavily doped silicon 9013. Then, multi-layer interconnection layers and through holes can be constructed to form bit lines 9015 and source lines 9014 to complete the entire DRAM array. The array structure of the NuDRAM depicted in FIG. 90 is similar to the array in FIG. 89 . The RCAT transistor is shown in Figure 90. Other types of low-temperature stacked transistors can also be constructed using a process flow similar to that shown in FIG. 90 . For example, V-groove transistors and other transistors in other instances of the invention described above can be constructed.

圖91A-L中還顯示了建設NuDRAM之其他工藝流程。從圖91A開始描述之工藝顯示了SOI p-晶圓9101中之成型淺槽絕緣層9102。埋設之氧化層標示為9119。 Other process flows for building NuDRAM are shown in Figures 91A-L. The process described beginning with FIG. 91A shows a shaped trench insulation layer 9102 in an SOI p-wafer 9101 . The buried oxide layer is marked as 9119.

隨後,如圖91B所示進行柵極溝槽蝕刻9103。圖91A顯示之是XZ平面上之NuDRAM之剖視圖,圖91B是YZ平面上之剖視圖(因此圖91B中並未標注淺槽絕緣層9102)。 Subsequently, gate trench etching 9103 is performed as shown in FIG. 91B. FIG. 91A shows a cross-sectional view of NuDRAM on the XZ plane, and FIG. 91B is a cross-sectional view on the YZ plane (so the shallow trench insulating layer 9102 is not marked in FIG. 91B ).

圖91C展示了本工藝之下一步驟。採用與圖67E類似之程式可形成柵極電介質層9105和RCAT柵電極9104。接下來可進行離子注入形成n+區9106之源極和汲極。 Figure 91C illustrates the next step in the process. A gate dielectric layer 9105 and RCAT gate electrode 9104 can be formed using a procedure similar to that of Figure 67E. Next, ion implantation can be performed to form the source and drain of the n+ region 9106 .

圖91D展示了層間電介質層9107之成型和打磨過程。 FIG. 91D shows the forming and grinding process of the interlayer dielectric layer 9107.

91E展示了本工藝之下一步驟。可取另外一個p-晶圓9108。氧化層9109在p-晶圓9108上生長。為達到切割目的,可在9110之一定深度處向晶圓9108中注入氫H+或其他之原子種類。 91E shows the next step in the process. Another p-wafer 9108 may be taken. An oxide layer 9109 is grown on the p-wafer 9108 . For the purpose of dicing, hydrogen H+ or other atomic species can be implanted into the wafer 9108 at a certain depth at 9110 .

接下來可透過氧化物之間黏結之方式將這層“較高之層”9108翻轉並黏貼到較低之晶圓9101上。然後可在氫平面9110上進行切割,接著再進行化學-機械打磨,得到圖 91F中所示之結構。 This "upper layer" 9108 can then be flipped over and attached to the lower wafer 9101 by way of oxide-to-oxide bonding. Cutting can then be performed on the hydrogen plane 9110, followed by chemical-mechanical polishing to obtain the pattern Structure shown in 91F.

圖91G顯示了本工藝之下一個步驟。可採取類似於圖91B-D所示之程式建設RCAT9113之另外一層。RCAT之這一層可與底部晶圓9101之部件對齊。 Figure 91G shows the next step in the process. Another layer of RCAT 9113 can be built using a procedure similar to that shown in Figures 91B-D. This layer of RCAT can be aligned with features of the bottom wafer 9101.

如圖91H所示,可採取類似於圖91B-D所示之程式建設一層或多層RCAT 9114。 As shown in Figure 91H, one or more layers of RCAT 9114 can be constructed using a procedure similar to that shown in Figures 91B-D.

圖91I展示了形成之通往不同之n+區和WL層之通孔9115。可使用重摻雜多晶矽建設這些通孔9115。 Figure 91I shows vias 9115 formed to different n+ regions and WL layers. These vias 9115 may be constructed using heavily doped polysilicon.

圖91J展示了本工藝之下一步驟。這一步驟可完成快速高熱退火(RTA),以開啟注入之摻雜物,使所有層之多晶矽區徹底晶化。 Figure 91J illustrates the next step in the process. This step allows rapid thermal annealing (RTA) to turn on the implanted dopants and fully crystallize the polysilicon regions in all layers.

圖91K展示了形成之位線BL 9116和源極線SL 9117。 Figure 91K shows bit line BL 9116 and source line SL 9117 formed.

BL 9116和SL 9117成型之後,圖91L展示了採用上文所述之程式形成DRAM週邊電路9118之電晶體和通孔新層之方法(例如,採用圖29A-G之方法形成V形槽MOSFET)。這些週邊電路9118可與下方之DRAM電晶體層對齊。本案例中之DRAM電晶體可採取任意一種類型(高溫(即超過400℃)加工或低溫(即低於400℃)加工之電晶體都可以);由於週邊電路將在鋁或銅配線層9116和9117之後建設,週邊電路可採用低溫加工之電晶體。圖91中之案例之陣列結構可與圖89中顯示之陣列結構類似。 After BL 9116 and SL 9117 are formed, Figure 91L shows the method of forming a new layer of transistors and vias for DRAM peripheral circuit 9118 using the procedure described above (for example, using the method of Figure 29A-G to form a V-groove MOSFET) . These peripheral circuits 9118 may be aligned with the underlying DRAM transistor layer. The DRAM transistor in this case can be of any type (transistors processed at high temperature (that is, over 400°C) or low temperature (that is, below 400°C) can be used); since the peripheral circuit will be in the aluminum or copper wiring layer 9116 and For construction after 9117, the peripheral circuit can use transistors processed at low temperature. The array structure for the case in FIG. 91 may be similar to the array structure shown in FIG. 89 .

可使用圖91A-L中所示之演變流程作為製作NuDRAM之備選流程。可在電晶體所有步驟都外城之後未進行RTA之前先建設週邊電路層。在這些週邊電路之本地佈線過程 中可使用一層或多層金屬鎢。之後,如圖91所示,可利用層切法建設多層RCAT,接著再進行RTA。接下來可增加高導電性銅或鋁線層,從而完成DRAM流程。透過共用高溫步驟RTA以及一次性徹底處理所有之晶化層之方法,這個流程降低了製作成本,同時也可在3D NuDRAM週邊電路中使用類似于傳統2D DRAM使用之設定。在這一工藝流程中,可採用任意類型之DRAM電晶體,並不局限於低溫光刻電晶體,例如RCAT或V形槽電晶體。 The evolution flow shown in Figures 91A-L can be used as an alternative flow for making NuDRAM. The peripheral circuit layer can be built before RTA after all steps of the transistor are completed. The local wiring process in these peripheral circuits One or more layers of metal tungsten can be used in the. Afterwards, as shown in Figure 91, the layer cutting method can be used to construct multi-layer RCAT, followed by RTA. Next, layers of highly conductive copper or aluminum lines can be added to complete the DRAM process. By sharing the high-temperature step RTA and thoroughly processing all the crystallization layers at one time, this process reduces the production cost, and can also be used in the peripheral circuits of 3D NuDRAM similar to the settings used in traditional 2D DRAM. In this process flow, any type of DRAM transistor can be used, not limited to low-temperature lithography transistors, such as RCAT or V-groove transistors.

圖92A-F展示了採用部分空乏型SOI電晶體建設之NuDRAM。圖99A描述了本工藝之第一個步驟。氧化層9202可能會在p-晶圓9201上生長。92B展示了本工藝之下一步驟。可在p-區9201之一定深度處向晶圓中注入氫。氫之最終位置如虛線9203所示。圖92C展示了本工藝之下一步驟。可製備帶DRAM週邊電路9204之晶圓。這個晶圓帶有未經過RTA處理之電晶體。另外,週邊電路還可以進行輕微或部分RTA。製備將9204中之電晶體連接在一起之多層鎢互聯層。透過氧化物之間黏結之方式將圖92B中之晶圓翻轉並黏貼到帶DRAM週邊電路9204之晶圓上。然後可採用本檔中所述之切割法在氫平面9203上對晶圓進行切割。切割之後,採取化學-機械打磨法對切割表面進行打磨。圖92D展示了本工藝之下一步驟。如圖92D所示,可以進行掩膜、蝕刻和低溫氧化層澱積操作了,以便確定好被上述氧化層絕緣之擴散行。上述擴散行和絕緣行可與下方之週邊電路9204對齊。絕緣區成型之後,建設部分空乏 型SOI(PD-SOI)電晶體,使柵極電介質9207和柵電極9205成型,然後對9207和9205進行繪製圖形和蝕刻,接下來就形成離子注入源極/汲極區9208。請注意在這一步驟中無需進行RTA開啟注入源極/汲極區9208。圖92D所示之掩膜可與下方之週邊電路9204對齊。氧化層9206可能會澱積,並透過化學-機械打磨法進行打磨。92E展示了本工藝之下一步驟。採取圖92A-D中類似之步驟可在第一層PD-SOI電晶體層之頂部形成第二層PD-SOI電晶體層9209。多次重複上面之步驟,可得到理想之多層3D DRAM。接下來可進行RTA,以開啟摻雜物,使所有電晶體層之多晶矽區徹底晶化。圖92F描述了本工藝之下一個步驟。可完全穿過所有之堆疊層將通孔9210遮蔽並蝕刻至文字線、源極和汲極連接線。請注意採取類似於圖89之方式將電晶體9213之柵極連接起來,形成文字線。接著可使用金屬(例如鎢)對通孔進行填充。或者也可以使用重摻雜之多晶矽。接著可建設多層互聯層和通孔,形成位線9211和源極線9212,完成整個DRAM陣列。圖92中描述之NuDRAM之陣列結構類似於圖89中之陣列。 Figures 92A-F show a NuDRAM constructed using partially depleted SOI transistors. Figure 99A depicts the first step of the process. An oxide layer 9202 may be grown on the p-wafer 9201. 92B shows the next step in the process. Hydrogen can be implanted into the wafer at a certain depth in p-region 9201 . The final position of the hydrogen is shown by dashed line 9203. Figure 92C illustrates the next step in the process. A wafer with DRAM peripheral circuits 9204 can be prepared. This wafer has transistors that have not been RTA processed. In addition, peripheral circuits can also perform slight or partial RTA. Fabricate the multilayer tungsten interconnects that connect the transistors in the 9204 together. The wafer in FIG. 92B is flipped over and pasted onto the wafer with DRAM peripheral circuits 9204 by means of oxide-to-oxide bonding. The wafer can then be diced on the hydrogen plane 9203 using the dicing method described in this document. After cutting, the cut surface is polished by chemical-mechanical polishing. Figure 92D illustrates the next step in the process. As shown in Figure 92D, masking, etching, and low temperature oxide deposition operations can be performed to define the diffusion rows insulated by the oxide. The aforementioned diffusion row and isolation row may be aligned with the peripheral circuit 9204 below. After the insulating area is formed, the building part is empty Type SOI (PD-SOI) transistor, shape the gate dielectric 9207 and gate electrode 9205, then pattern and etch the gate dielectric 9207 and 9205, and then form the ion implantation source/drain region 9208. Note that there is no need for RTA to turn on the implant source/drain regions 9208 in this step. The mask shown in Figure 92D can be aligned with the underlying peripheral circuitry 9204. An oxide layer 9206 may be deposited and polished by chemical-mechanical polishing. 92E shows the next step in the process. A second layer of PD-SOI transistors 9209 can be formed on top of the first layer of PD-SOI transistors by following steps similar to those in Figures 92A-D. By repeating the above steps several times, an ideal multi-layer 3D DRAM can be obtained. Next, RTA can be performed to turn on the dopant and completely crystallize the polysilicon regions of all transistor layers. Figure 92F depicts the next step in the process. Vias 9210 may be masked and etched completely through all stack layers to word lines, source and drain connection lines. Please note that the gates of transistors 9213 are connected in a manner similar to that shown in Figure 89 to form word lines. The vias may then be filled with a metal such as tungsten. Alternatively, heavily doped polysilicon can be used. Then, multi-layer interconnection layers and through holes can be constructed to form bit lines 9211 and source lines 9212 to complete the entire DRAM array. The array structure of the NuDRAM described in FIG. 92 is similar to the array in FIG. 89 .

對於編程用電晶體,使用一種類型之上層電晶體就足夠了。對於邏輯型電路,兩隻互補性之電晶體可能更有利於CMOS類型之邏輯器。因此,上述各種單體電晶體流程可執行兩次。首先徹底地執行所有步驟,以建設“n”型電晶體,接著再層切一次,在“n”型電晶體頂部再建設“p”型電晶體。 For programming transistors, it is sufficient to use one type of upper layer transistor. For logic type circuits, two complementary transistors may be more beneficial for CMOS type logic devices. Therefore, the various monolithic transistor processes described above can be performed twice. All steps are performed thoroughly first to build the "n" type transistor, followed by one more layer cut to build the "p" type transistor on top of the "n" type transistor.

另外一種方法是在同一層上建設“n”型電晶體和“p”型電晶體。難點在於如何使這些電晶體與下面的層808對齊。下文將藉由圖30至33對創新之解決方案進行說明。這種工藝適用於任何採取適用於晶圓傳送之方式建設之電晶體,包含但不限於水平或垂直MOSFET、JFET、水平和垂直無結型電晶體、RCAT和球形RCAT等。如圖30所示,主要不同點在於現在已對施主晶圓3000進行預加工,建設不止一種電晶體,而是兩種電晶體,包含施主晶圓3000上用於建設“n”型電晶體3004之行和建設“p”型電晶體之行之交替行。圖30還顯示了四個基本方向之指示符3040,圖33中藉由這些指示符進行解釋。n型行3004之寬度是Wn,p型行3006之寬度是Wp,二者之和W 3008等於之重複圖形之寬度。行自東向西重複排列,而交替行從北向南重複排列。施主晶圓行3004和3006自東向西沿長度方向延伸,延伸距離等於受主裸晶片寬度加上施主晶圓到受主晶圓未對準線之間之最大距離。或者也可以自東向西延伸整個施主晶圓之長度。事實上,可以將晶圓當作劃線投影區。在大多數情況下,這些投影區要包含圖像或場之多個裸晶片。在大多數情況下,設定用於進一步將晶圓切成單獨之裸晶片之劃片槽寬度可能會超過20微米。晶圓與晶圓未對準線之間之距離大約為1微米。因此,將圖形延伸至劃片槽可充分在裸晶片範圍內充分利用圖形,儘量不影響切割劃片槽。Wn和Wp可設定為相應電晶體之最小寬度加上其在選定之工藝節點中之隔離寬度。晶圓3000還具有 一條對準標誌3020,與作為n 3004和p 3006行之施主晶圓位於同一層。因此,為了將其他之圖像繪製和加工過程與上述n 3004和n 3006行相對齊,可稍後再使用晶圓3000。 Another approach is to build "n" type transistors and "p" type transistors on the same layer. The difficulty is how to align these transistors with the layer 808 below. The innovative solution will be described below with reference to FIGS. 30 to 33 . This process is applicable to any transistor built in a way suitable for wafer transfer, including but not limited to horizontal or vertical MOSFETs, JFETs, horizontal and vertical junctionless transistors, RCAT and spherical RCAT, etc. As shown in Figure 30, the main difference is that the donor wafer 3000 has now been pre-processed to build not just one type of transistor, but two types of transistors, including the "n" type transistor 3004 on the donor wafer 3000 Alternate between the trips and the trips to build "p"-type transistors. FIG. 30 also shows indicators 3040 of the four cardinal directions, which are explained in FIG. 33 . The width of the n-type row 3004 is Wn, the width of the p-type row 3006 is Wp, and the sum of the two, W 3008, is equal to the width of the repeated pattern. Rows repeat from east to west, and alternating rows repeat from north to south. Donor wafer rows 3004 and 3006 extend lengthwise from east to west for a distance equal to the width of the acceptor die plus the maximum distance between the donor wafer and the acceptor wafer misalignment. Alternatively, it can extend the entire length of the donor wafer from east to west. In fact, the wafer can be regarded as a scribe line projection area. In most cases, these projection areas will contain multiple dies of images or fields. In most cases, the width of the scribe line for further cutting the wafer into individual dies may exceed 20 microns. The wafer-to-wafer misalignment distance is approximately 1 micron. Therefore, extending the pattern to the scribing groove can make full use of the pattern within the range of the bare wafer without affecting the cutting of the scribing groove as much as possible. Wn and Wp can be set to the minimum width of the corresponding transistor plus its isolation width in the selected process node. Wafer 3000 also has A strip of alignment marks 3020, on the same layer as the donor wafer as rows n 3004 and p 3006. Therefore, wafer 3000 may be reused later in order to align other image rendering and processing with rows n 3004 and n 3006 described above.

如前所述,受主晶圓3000將被放置到主晶圓3100之頂部,完成層切。當前之技術發展平可以實現完美之黏結步驟之角對準,但要達到比1□m還完美之位置對準卻非常困難。 As mentioned above, the acceptor wafer 3000 will be placed on top of the master wafer 3100 for layer dicing. The current technological development can achieve perfect corner alignment of the bonding step, but it is very difficult to achieve a perfect position alignment than 1□m.

具有一般技藝之人會認為東南西北四個方向只起到說明用途,和真正之地理方向無關;並且會認為僅僅透過將晶圓旋轉90°就可以將南北方向變成東西方向(反之亦然);“n”型電晶體行3004和“p”型電晶體行3006也可以在南北方向上運行,主要取決於設定選擇以及對其餘之製作工藝進行相應之調整。技藝高超之人可在不同之設定選擇中考量為“n”型電晶體行3004和“p”行電晶體行選擇不同之結構。例如,“n”型電晶體行3004和“p”型電晶體行3006可各自包含單行並聯之電晶體、多行並聯之電晶體和多組不同規格、不同方向和不同類型之電晶體(單只電晶體或組合電晶體均可),並可為“n”型電晶體行3004和“p”型電晶體行3006選擇不同之電晶體尺寸或數量。因此,本發明之範圍受限於附加之權利要求。 People with ordinary skills will think that the four directions of east, west, north and south are only for illustrative purposes, and have nothing to do with the real geographical direction; and will think that the north-south direction can be changed to east-west direction (and vice versa) just by rotating the wafer 90°; The "n" type transistor row 3004 and the "p" type transistor row 3006 can also run in the north-south direction, depending on the setting choices and corresponding adjustments to the rest of the fabrication process. The skilled person may consider choosing different configurations for the "n" transistor row 3004 and the "p" transistor row in different setting options. For example, the "n" type transistor row 3004 and the "p" type transistor row 3006 may each include a single row of parallel transistors, multiple rows of parallel transistors, and multiple sets of transistors of different specifications, directions, and types (single Only transistors or combined transistors are acceptable), and different transistor sizes or numbers can be selected for the "n" type transistor row 3004 and the "p" type transistor row 3006. Accordingly, the scope of the present invention is limited by the appended claims.

圖31顯示了主晶圓3100(帶有對準標誌3120)以及施主晶圓3000(帶有對準標誌3020)之切出層3000L。東西方向之未對準線是DX 3124,南北方向之未對準線是DY 3122。為簡化下文中之說明,可假設已設定好對準標誌 3120和3020,這樣一來,不管是很圓滿地對準了對準標誌3020(在公差範圍內),還是採取近似之方式對準了對準標誌3120之南方,切出層3020之對準標誌將一直位於基板3120對準線之北方。此外,每個晶圓上只能在某些位置設定這些對準標誌,可設定在各個步驟場中、各個裸晶片中、各個重複圖形W中或者依照不同之設定選擇設定在其他之位置。 FIG. 31 shows a cut-out layer 3000L of a master wafer 3100 (with alignment marks 3120 ) and a donor wafer 3000 (with alignment marks 3020 ). The east-west misalignment is DX 3124, and the north-south misalignment is DY 3122. To simplify the description below, it can be assumed that the alignment mark has been set 3120 and 3020, in this way, whether the alignment mark 3020 is perfectly aligned (within the tolerance range), or the alignment mark 3120 is aligned to the south of the alignment mark 3120 in an approximate manner, the alignment mark of the layer 3020 is cut out Will always be north of the substrate 3120 alignment. In addition, these alignment marks can only be set at certain positions on each wafer, and can be set in each step field, in each bare wafer, in each repeated pattern W, or in other positions according to different settings.

在建設本文所述之單塊3D積體電路時,目標在於以808中各層之連接線相同之密度和精度將層3000L上之結構連接到下方之主晶圓3100和808層上之結構上。該過程中所需之對準精度大約為數十納米或更高。 In building the monolithic 3D ICs described herein, the goal is to connect structures on layer 3000L to structures on the master wafer 3100 below and on layers 808 with the same density and precision as the interconnects at each layer in 808. The alignment accuracy required in this process is on the order of tens of nanometers or more.

在東西方向上採用之方法可與圖21至29描述之方法相同。無論未對準線DX 3124是否相同,施主晶圓3000上之預製結構都相同。因此,和前面步驟一樣,可利用下方之對準標誌3120將預製結構對齊,透過蝕刻和單獨加工,形成“n”型電晶體行3004和“p”型電晶體行3006,無需考量DX。隨著圖形之改變,南北方向上之情況與此不同。然而,圖形重複每段距離W 3008之事實就顯示出了圖30所示之交替行南北方向上重複圖形之預期結構之優點。因此,由於南北方向上之圖形可保持重複每段W,有效對齊之不確定性就可降至W 3008。 The method used in the east-west direction can be the same as that described in FIGS. 21 to 29 . Whether or not the misalignment line DX 3124 is the same, the prefabricated structures on the donor wafer 3000 are the same. Therefore, as in the previous steps, the alignment mark 3120 below can be used to align the prefabricated structure, and the "n" type transistor row 3004 and the "p" type transistor row 3006 can be formed through etching and separate processing, without considering DX. As the figure changes, the situation in the north-south direction is different. However, the fact that the pattern repeats every distance W 3008 shows an advantage to the intended structure of repeating the pattern in the north-south direction of alternating rows shown in FIG. 30 . Therefore, since the pattern in the north-south direction can keep repeating every segment W, the uncertainty in the effective alignment can be reduced to W 3008.

因此,可採取圖32所示之方法計算有效對齊之不確定性,以確定DY 3122需要W之數量--完整之“n”行3004和“p”行3006組合之圖形,並計算殘餘Rdy 3202(DY模 量W之餘數,0<=Rdy<W)。因此,要與南北方向上最近之n 3004和p 3006準確對齊,一定要與下方之Rdy 3202偏移之對準標誌3120對齊。因此,應依照受主晶圓對準標誌3120和施主晶圓對準標誌3020之間之未對準線進行對齊,並考量重複距離W 3008,計算偏移Rdy 3202所需之合向量。使用紅外燈和光學組件時,可以看到在對齊過程中被晶圓3000L覆蓋之對準標誌3120,並可將其用於分節器或光刻工具對準系統。 Therefore, the method shown in Figure 32 can be used to calculate the uncertainty of the effective alignment to determine the amount of W required for DY 3122 - the complete pattern of "n" row 3004 and "p" row 3006 combinations, and calculate the residual Rdy 3202 (DY mode The remainder of the amount W, 0<=Rdy<W). Therefore, to accurately align with the nearest n 3004 and p 3006 in the north-south direction, it must be aligned with the offset alignment mark 3120 of the Rdy 3202 below. Therefore, alignment should be performed according to the misalignment line between the acceptor wafer alignment mark 3120 and the donor wafer alignment mark 3020 , and considering the repeat distance W 3008 , the resultant vector required for the offset Rdy 3202 is calculated. Alignment marks 3120 covered by wafer 3000L during the alignment process can be seen using infrared lamps and optical components and can be used for segmenter or lithography tool alignment systems.

或者,可如圖69所示使用施主晶圓上之多個對準標誌。可在南北方向上之每段W 6920上精確複製施主晶圓對準標誌3020,其距離以能夠完全覆蓋住施主晶圓和受主晶圓之間可能會出現之南北方向未對準線M 6922為宜。因此,殘餘Rdy 3202可能是最近之施主晶圓對準標誌6920C和受主晶圓對準標誌3120之間之南北方向之未對準線。因而,要與施主晶圓層最近之對準標誌9620C對齊,而不要與下方之Rdy 3202偏移之對準標誌3120對齊。所以,可採用選擇施主晶圓上最近之對準標誌6920C之方法依照受主晶圓對準標誌3120和施主晶圓對準標誌6920之間之未對準線進行對齊。 Alternatively, multiple alignment marks on the donor wafer may be used as shown in FIG. 69 . Donor wafer alignment marks 3020 can be accurately replicated on each segment W 6920 in the north-south direction at a distance sufficient to completely cover any north-south misalignment M 6922 that may occur between the donor wafer and the acceptor wafer It is appropriate. Therefore, residual Rdy 3202 may be a north-south misalignment between the nearest donor wafer alignment mark 6920C and acceptor wafer alignment mark 3120 . Thus, align with the alignment mark 9620C closest to the donor wafer layer, and not align with the alignment mark 3120 that is offset from the Rdy 3202 below. Therefore, the method of selecting the closest alignment mark 6920C on the donor wafer can be used to align according to the misalignment line between the acceptor wafer alignment mark 3120 and the donor wafer alignment mark 6920 .

藉由圖69中之插圖可簡化說明,實際應用中對準標誌可能要超過WxW之大小。在這種情況下,為避免對準標誌6920互相重疊,可使用偏移技術,以採取適當之標誌,實現理想之對齊效果。 The illustration is simplified by the inset in FIG. 69 , the alignment marks may exceed the size of WxW in practice. In this case, in order to prevent the alignment marks 6920 from overlapping each other, an offset technique can be used to adopt appropriate marks to achieve an ideal alignment effect.

將透過該流程加工之各個晶圓均具有特定之Rdy 3202,具體以實際未對準線DY 3122為准。不過,用於繪製各種圖形之掩膜需要預先進行設定、製作;所有晶圓(用於同一終端設備之晶圓)都要使用相同之掩膜,無需考量實際之未對準線情況。如圖33A所示,為改良切出層3000L上之結構與下方之主晶圓3100之間之連接情況,下方之晶圓3100設定有沿W 3008長度方向之南北向插接條接合焊盤33A04以及通孔設定規則所必須之擴展部分。滿足通孔設定規則之長度方向或寬度方向之接合焊盤擴展部分可包含補償因晶圓與晶圓之間之黏結而產生之角度失准,還包含未補償之施主晶圓彎曲和翹曲。步進電機重疊演算法並不補償角度失准。插接條33A04可成為基板3100之一部分,因此與其對準標誌3120對齊。自上而下之通孔33A02(成為頂層3000L圖形之一部分,與下方之帶有Rdy偏移之對準標誌3120對齊)將與接合焊盤33A04連接在一起。 Each wafer to be processed through this process has a specific Rdy 3202, the actual misalignment line DY 3122 shall prevail. However, the masks used to draw various graphics need to be set and fabricated in advance; all wafers (wafers used for the same terminal equipment) must use the same mask, without considering the actual misalignment situation. As shown in FIG. 33A , in order to improve the connection between the structure on the cut-out layer 3000L and the lower main wafer 3100, the lower wafer 3100 is provided with north-south insertion pads 33A04 along the length direction of W 3008 And the necessary extensions for the via setting rules. Lengthwise or widthwise bond pad extensions that meet via-setting rules can include compensation for angular misalignment due to wafer-to-wafer bonding, as well as uncompensated donor wafer bow and warpage. The stepper motor overlap algorithm does not compensate for angular misalignment. The plug strips 33A04 can be part of the substrate 3100 and thus aligned with the alignment marks 3120 . The top-down via 33A02 (becoming part of the top layer 3000L pattern, aligned with the underlying alignment mark 3120 with Rdy offset) will connect together with the bond pad 33A04.

或者,可在頂層3000L上製作南北方向之長度至少為W之接合插接條33B04,以及滿足通孔設定規則之延伸部分和上述其他之補償部分,並相應地域下方之帶有Rdy偏移之對準標誌3120對其,從而連接到通孔33B02上,成為下方之圖形之一部分(與下方之對準標誌3120對齊,無偏移)。 Alternatively, splicing strips 33B04 with a length of at least W in the north-south direction can be made on the top layer 3000L, as well as extensions that meet the through-hole setting rules and other compensation parts mentioned above, and pairs with Rdy offsets below the corresponding regions Alignment marks 3120 are aligned so as to be connected to via holes 33B02 and become part of the lower pattern (aligned with lower alignment marks 3120 without offset).

下文列舉了在用於CMOS邏輯之單獨切出層上產生互補電晶體之工藝流程之範例。首先,可首先對施主晶圓進行預加工,為層切工作做好準備。如圖34A所示,可專門 加工該互補施主晶圓,以產生p和n井之重複行3400,它們之總寬度是W 3008。重複行3400之長度可能等於受主裸晶片寬度加上施主晶圓與受主晶圓未對準線之間之最大距離;或者,重複行之長度可以與施主晶圓之總長度相等。依照四個基本方向之指示符所示,將圖34A相對於圖30旋轉90°,使圖34A與後面之圖34B至35G中之方向相同。 An example of a process flow for creating complementary transistors on a separate cut-out layer for CMOS logic is given below. First, the donor wafer can be pre-processed first in preparation for layer dicing. As shown in Figure 34A, the dedicated The complementary donor wafer is processed to produce repeating rows 3400 of p and n wells whose total width is W 3008 . The length of the repeating row 3400 may be equal to the width of the acceptor die plus the maximum distance between the donor wafer and the receiver wafer misalignment; alternatively, the length of the repeating row may be equal to the total length of the donor wafer. Rotate Fig. 34A by 90° relative to Fig. 30 as indicated by the indicators of the four cardinal directions, so that Fig. 34A is oriented in the same way as in subsequent Figs. 34B to 35G.

圖34B是預加工之用於層切之晶圓之剖視圖。透過不斷在寬度W 3008中掩膜、離子注入和開啟方式加工後之P-晶圓3402具有一層“埋設”N+層3404和一層P+層3406 Figure 34B is a cross-sectional view of a wafer preprocessed for layer dicing. The P- wafer 3402 processed by successive masking, ion implantation and opening in the width W 3008 has a "buried" N+ layer 3404 and a P+ layer 3406

接下來要進行的是圖34C中之P-類晶生長生長3408和N-區3410之掩膜、離子注入和退火。 Next to be performed are masking, ion implantation and annealing of P-like crystal growth 3408 and N-region 3410 in FIG. 34C.

下一步,如圖34D所示,透過掩膜、淺槽離子注入和RTA開啟形成淺槽P+ 3412和N+ 3414。 Next, as shown in FIG. 34D , shallow trenches P+ 3412 and N+ 3414 are formed through a mask, shallow trench ion implantation and RTA opening.

圖34E展示了透過原子種類(例如H+)之注入預加工之用於層切之晶圓圖紙,在較深之N+和P+區之底部區域形成了SmartCut“切割平面”3416。一薄層氧化層3418可能會澱積或生長,促進氧化物與層808之黏結。氧化層3418可在H+注入之前澱積或生長,包含不同厚度之P+ 3412和N+ 3414區,使H+注入範圍終止更均勻,促進注入平之提高和產生連續之SmartCut切割平面3416。可採取其他方式在必要時調整H+注入之深度,包含為P+ 3412和N+ 3414區設定不同之注入深度。 Figure 34E shows a wafer drawing preprocessed by implantation of atomic species (eg, H+) for layer dicing, forming a SmartCut "cut plane" 3416 in the bottom region of the deeper N+ and P+ regions. A thin oxide layer 3418 may be deposited or grown to promote adhesion of the oxide to layer 808 . Oxide layer 3418 can be deposited or grown before H+ implantation, including P+ 3412 and N+ 3414 regions with different thicknesses, making the termination of H+ implantation range more uniform, promoting the improvement of implantation level and producing continuous SmartCut cutting plane 3416. The depth of the H+ implant can be adjusted if necessary in other ways, including setting different implant depths for the P+ 3412 and N+ 3414 regions.

如圖20所示,現在可進行層切流程,以轉移圖35A所示之808頂部上之預加工之插接條多井式單晶矽晶圓。現 在可同時採取CMP和化學打磨手段將切割表面打磨光滑,也可不進行打磨。 As shown in FIG. 20, the layer dicing process can now be performed to transfer the prefabricated strap multi-well monocrystalline silicon wafer on top of 808 shown in FIG. 35A. now The cutting surface can be smoothed by CMP and chemical polishing at the same time, or not.

上述p & n井帶狀施主晶圓預處理過程也可改為在層切之前採取淺槽蝕刻、電介質填充和CMP之方法預先進行井隔離。 The above p & n well ribbon donor wafer pretreatment process can also be changed to pre-well isolation by means of shallow trench etching, dielectric filling and CMP before layer dicing.

圖35A至35G逐步介紹了位於互補施主晶圓(圖34所示)上之低溫成型之平面CMOS電晶體之側視圖。圖35A展示了在智慧切割3502之後轉移到晶圓或層808頂部之層;其中N+ 3404和P+ 3406位於最上面,依照基本方向3500之指示可判斷,它們東西向運行(即垂直於圖中之平面),而重複寬度為南北向。 35A to 35G are step-by-step side views of low temperature formed planar CMOS transistors on a complementary donor wafer (shown in FIG. 34). Figure 35A shows the layers transferred to the top of the wafer or layer 808 after smart dicing 3502; where N+ 3404 and P+ 3406 are uppermost, as indicated by cardinal direction 3500, running east-west (i.e., perpendicular to plane), and the repeat width is north-south.

接下來,如圖35B所示,可對基板P+ 35B06和N+ 35B08源極和808金屬層35B04檢查口以及電晶體隔離區35B02進行遮蔽和蝕刻。這一層接接下來所有之遮蔽層都會與圖30至32以及圖35B所示之層對齊,其中層對準標誌3020藉由偏移Rdy與基板層808之對準標誌3120對齊。 Next, as shown in FIG. 35B , the substrate P+ 35B06 and N+ 35B08 sources and 808 metal layer 35B04 inspection openings and the transistor isolation region 35B02 can be masked and etched. This layer and all subsequent masking layers will be aligned with the layers shown in FIGS. 30-32 and FIG. 35B , where layer alignment mark 3020 is aligned with alignment mark 3120 of substrate layer 808 by offset Rdy.

透過使用附加之掩蔽層,隔離區35C02充分地一直被蝕刻至預加工晶圓或層808之頂部,以便將圖35C所示之電晶體或電晶體組完全隔離。接下來低溫氧化層35C04被澱積,並採取化學-機械打磨之方式打磨。然後,一薄層打磨終止層35C06,例如低溫氮化矽,會澱積,生成如圖35C所示之結構。 By using an additional masking layer, isolation region 35C02 is etched sufficiently all the way to the top of prefabricated wafer or layer 808 to completely isolate the transistor or groups of transistors shown in FIG. 35C. Next, a low temperature oxide layer 35C04 is deposited and polished by chemical-mechanical polishing. Then, a thin grind stop layer 35C06, such as low temperature silicon nitride, is deposited, resulting in the structure shown in Figure 35C.

如圖35D所示,透過掩蔽和蝕刻一薄層打磨終止層35C06和傾斜之N+蝕刻層,可形成n-溝槽源極35D02、汲 極35D04和自對齊柵極35D06。在P+層上重複上述步驟可形成p-溝槽源極35D08、汲極35D10和自對齊柵極35D12,產生互補組件並形成補充金屬氧化半導體(CMOS)傾斜(35°至90°,圖中顯示為45°)蝕刻之後可採取濕式化學或電漿蝕刻技術。這步蝕刻操作可形成N+源極和汲極角度擴展35D12和P+源極和汲極角度擴展35D14。 As shown in FIG. 35D, by masking and etching a thin layer of grinding stop layer 35C06 and an inclined N+ etch layer, n-trench source 35D02, drain pole 35D04 and self-aligned gate 35D06. Repeating the above steps on the P+ layer can form p-trench source 35D08, drain 35D10 and self-aligned gate 35D12, creating complementary components and forming a complementary metal oxide semiconductor (CMOS) tilt (35° to 90°, shown in the figure For 45°) etching can be followed by wet chemical or plasma etching techniques. This etching operation forms N+ source and drain angle extensions 35D12 and P+ source and drain angle extensions 35D14.

圖35E展示了澱積和緻密化之後低溫柵極電介質35E02之結構,或者低溫微波電漿氧化之後矽表面(充當n & p MOSFET之柵極氧化層)之結構,接下來還展示了柵極材料35E04(例如鋁或鎢)之澱積情況。此外,還可採取下列方法形成高-k金屬柵極結構。採用符合行業標準HF/SC1/SC2之清洗方法,產生原子級平滑表面之後,高-k電介質35E02將會發生澱積。半導體行業已選擇鉿介電介質作為代替SiO2和氮氧化矽之主要材料。鉿介電介質系列包含二氧化鉿和矽酸鉿/氮氧化鉿矽。二氧化鉿(HfO2)之介電常數是矽酸鉿/氮氧化鉿矽(HfSiO/HfSiON k~15)之介電常數之兩倍。金屬材料之選擇對於組件正常運行起到至關重要之作用。代替N+多晶矽成為柵電極之金屬之功函數應達到大約4.2eV,這樣組件才能在正確之閾值電壓下正常運行。或者,代替P+多晶矽成為柵電極之金屬之功函數應達到大約5.2eV,這樣組件才能正常運行。舉例來說,TiAl和TiAlN金屬系列可用於將金屬之功函數從4.2eV調整為5.2eV。n和p溝槽組件中之柵極氧化層和柵極金屬可能會有所不同,可以選擇性地移除一種類型之柵極 氧化層和柵極金屬,代之以其他類型的。 Figure 35E shows the structure of the low temperature gate dielectric 35E02 after deposition and densification, or the structure of the silicon surface (serving as gate oxide for n & p MOSFETs) after low temperature microwave plasma oxidation, followed by the gate material Deposition of 35E04 (such as aluminum or tungsten). In addition, the following methods can also be used to form the high-k metal gate structure. High-k dielectric 35E02 will be deposited after an atomically smooth surface using industry standard HF/SC1/SC2 cleans. The semiconductor industry has chosen hafnium dielectric as the main material to replace SiO2 and silicon oxynitride. The hafnium dielectric family includes hafnium dioxide and hafnium silicate/hafnium silicon oxynitride. The dielectric constant of hafnium dioxide (HfO2) is twice that of hafnium silicate/hafnium oxynitride silicon (HfSiO/HfSiON k~15). The choice of metal material plays a critical role in the proper functioning of the component. The work function of the metal that replaces N+ polysilicon as the gate electrode should reach about 4.2eV so that the device can operate normally at the correct threshold voltage. Alternatively, the metal that replaces the P+ polysilicon as the gate electrode should have a work function of about 5.2eV for the device to function properly. For example, the TiAl and TiAlN metal series can be used to tune the work function of the metal from 4.2eV to 5.2eV. The gate oxide and gate metal may differ in n and p trench components, allowing one type of gate to be selectively removed Oxide layer and gate metal are replaced by other types.

圖35F展示了利用氮化物打磨停蝕層35C06進行化學-機械打磨之後之金屬柵極35E04之結構。最後,如圖35G所示,一厚層氧化層35G02發生了澱積,接點開口被掩蔽、蝕刻,準備好將要連接在一起之電晶體。圖35F還展示了層切矽通孔35G04。層切矽通孔將被掩蔽並蝕刻,以將上層電晶體佈線和底層808互連佈線35B04之間互相連接起來。這個流程可形成單晶頂層CMOS電晶體,並將金屬與高溫部件互相連接起來。這些電晶體與下方之多金屬半導體組件連接起來,不會裸露下方之組件。這些電晶體可用作層807上之抗熔存儲之編程電晶體或者可用於其他之功能,例如與預加工之晶圓之金屬層或層808進行電耦合之3D積體電路中之邏輯器或記憶體。該流程之另外一個優點在於SmartCut H+或其他原子種類之注入步驟在MOS電晶體柵極成型之前完成,避免對柵極功能造成潛在之損壞。 FIG. 35F shows the structure of metal gate 35E04 after chemical-mechanical polishing using nitride polishing stop layer 35C06. Finally, as shown in Figure 35G, a thick oxide layer 35G02 is deposited and the contact openings are masked and etched, ready for the transistors to be connected together. FIG. 35F also shows layer cut silicon via 35G04. The TSVs will be masked and etched to interconnect the upper transistor wiring and the bottom 808 interconnection wiring 35B04. This process forms the single-crystal top-layer CMOS transistors and interconnects metal and high-temperature components. These transistors are connected to the underlying multi-metal semiconductor components without exposing the underlying components. These transistors can be used as antifuse programming transistors on layer 807 or can be used for other functions such as logic or logic in 3D integrated circuits electrically coupled to the metal layer or layer 808 of the prefabricated wafer. Memory. Another advantage of this process is that the implantation of SmartCut H+ or other atomic species is completed before the gate of the MOS transistor is formed, avoiding potential damage to the gate function.

具有一般技藝之人會認為,為清晰起見,在解釋同時製作P-溝槽和N-溝槽電晶體之方法時,按照圖34A至圖35G製作之電晶體之導電溝槽為南北方向,而它們之柵電極為東西方向。實際上也可以採取其他方向和結構。技藝高超之人可進一步考量電晶體可繞著南北方向之柵電極旋轉90°。例如,技藝高超之人很容易瞭解到在東西方向上互相對齊之電晶體可利用低溫氧化層35C04互相絕緣,或者依照不同設定選擇共用源極區和汲極區及接點。技藝高 超之人還會意識到“n”型電晶體行3004可包含多個南北方向對齊之N-溝槽電晶體,“p”型電晶體行3006可包含多個南北方向對齊之P-溝槽電晶體,逐一形成了背對背之同於有效之邏輯佈局之P-溝槽和N-溝槽電晶體之子行。在邏輯佈局中,相同類型之子行共用電源線和連接線。在本發明範圍內還可以採取很多其他設定選擇,對技藝高超之人有啟發作用。因此,本僅受限於附加之權利要求。 Those of ordinary skill will recognize that, for clarity, in explaining the method of simultaneously fabricating P-groove and N-groove transistors, the conduction trenches of transistors fabricated in accordance with FIGS. 34A to 35G are oriented north-south, And their grid electrodes are in the east-west direction. In fact other orientations and configurations are also possible. Those skilled in the art can further consider that the transistor can be rotated 90° about the gate electrode in the north-south direction. For example, those skilled in the art can easily understand that transistors aligned in the east-west direction can be insulated from each other by using the low-temperature oxide layer 35C04, or choose to share source and drain regions and contacts according to different settings. high skill Superman will also realize that "n" type transistor row 3004 may contain a plurality of N-trench transistors aligned in a north-south direction, and "p" type transistor row 3006 may contain a plurality of P-trenches aligned in a north-south direction The transistors, one by one, form sub-rows of back-to-back P-channel and N-channel transistors with the same effective logic layout. In a logical layout, sub-rows of the same type share power and connection lines. Many other setting options can also be taken within the scope of the present invention, which is instructive to those skilled in the art. Accordingly, the invention is limited only by the appended claims.

或者,可使用晶圓大小之摻雜層之簡單層切之方式建設完整之CMOS組件。下文將以n-RCAT和p-RCAT為例對工藝流程進行描述,但該工藝不適用於上述之使用晶圓大小之轉移摻雜層建設之組件。 Alternatively, complete CMOS devices can be built using simple layer-cutting of wafer-sized doped layers. The following will take n-RCAT and p-RCAT as examples to describe the process flow, but this process is not applicable to the above-mentioned components using the transfer doping layer construction of the wafer size.

如圖95A至95I所示,可使用晶圓大小之摻雜層之簡單層切之方式建設n-RCAT和p-RCAT。其工藝流程也適用於生產3D IC。 As shown in Figures 95A to 95I, n-RCAT and p-RCAT can be constructed using simple layer-cutting of wafer-sized doped layers. Its process flow is also suitable for the production of 3D ICs.

如圖95A所示,P-基板施主晶圓9500可包含四個晶圓大小之層,它們分別是N+摻雜層9503、P-摻雜層9504、P+摻雜層9506和N-摻雜層9508。P-摻雜層9504之摻雜物濃度可能與P-基板9500相同,也有可能不同。可透過離子注入和高熱退火之方式形成四個摻雜層9503、9504、9506和9508。另外,可透過連續類晶生長澱積摻雜矽層或同時使用類晶生長、離子注入和高熱退火之方式形成堆疊層。P-層9504和N-層9508也可進行梯度摻雜,以解決電晶體之性能問題,例如短通到效應。可在注入之前生長或澱積遮罩氧化層9501,以確保在注入過程中矽免受污染,並為後期 晶圓之間之黏結提供氧化層。由於尚未利用金屬佈線移到已加工之基板上,這些步驟可在超過400℃之溫度下完成。 As shown in Figure 95A, a P-substrate donor wafer 9500 may contain four wafer-sized layers, which are N+ doped layer 9503, P-doped layer 9504, P+ doped layer 9506, and N-doped layer 9508. The dopant concentration of the P-doped layer 9504 may be the same as that of the P-substrate 9500, or it may be different. Four doped layers 9503, 9504, 9506 and 9508 can be formed by ion implantation and thermal annealing. In addition, doped silicon layers can be deposited by sequential morphological growth or stacked layers can be formed using morphological growth, ion implantation, and high thermal annealing simultaneously. P-layer 9504 and N-layer 9508 can also be graded doped to solve performance problems of transistors, such as short pass effect. A mask oxide layer 9501 can be grown or deposited prior to implantation to ensure that the silicon is protected from contamination during the implantation process and to provide The bonding between the wafers provides the oxide layer. These steps can be performed at temperatures in excess of 400° C. since the metal wiring has not yet been moved onto the processed substrate.

如圖95B所示,施主晶圓9500之頂層可用於將氧化物晶圓和氧化層9502之澱積層黏結起來,或透過N-層9508之高熱氧化,或注入遮罩氧化層9501之二次氧化形成氧化層9502。透過氫離子注入9507或前文所描述之其他方法可在施主晶圓9500或N+層9503(如圖所示)中形成層切分界平面9599(圖中虛線部分)。如前文所述,施主晶圓9500和受主晶圓9510均可用作晶圓之間之黏結,然後二者再在低溫(不超過400℃)黏結起來。可透過切割或打磨或前文所述之工序將層切分界平面9599上方之N+層部分9503和P-施主晶圓基板9500移除。透過離子注入原子類別,例如氫注入,形成層切分界平面,隨後再進行切割或修磨之方法可稱為“離子切割”。受主晶圓之意思類似于前文所述之晶圓808,詳情請參考圖8。 As shown in Figure 95B, the top layer of the donor wafer 9500 can be used to bond the oxide wafer to the deposited layer of the oxide layer 9502, either through high thermal oxidation of the N- layer 9508, or secondary oxidation of the implanted mask oxide layer 9501 An oxide layer 9502 is formed. Slicing boundary planes 9599 (dotted lines in the figure) can be formed in the donor wafer 9500 or the N+ layer 9503 (as shown) by hydrogen ion implantation 9507 or other methods described above. As mentioned above, both the donor wafer 9500 and the acceptor wafer 9510 can be used as bonding between the wafers, and then the two are bonded together at a low temperature (not exceeding 400° C.). The portion of the N+ layer 9503 above the layer cut interface plane 9599 and the P- donor wafer substrate 9500 can be removed by dicing or grinding or the processes described above. The method of forming a layer cutting boundary plane by ion implantation of atomic species, such as hydrogen implantation, followed by cutting or grinding can be called "ion cutting". The meaning of the acceptor wafer is similar to the wafer 808 mentioned above, please refer to FIG. 8 for details.

如圖95C所示,剩餘之N+層9503、P-摻雜層9504、P+摻雜層9506、N-摻雜層9508和氧化層9502已層切至受主晶圓9510上。可透過化學或機械方式將N+摻雜層9503’之最上面一層打磨光滑、平坦。現在已利用低溫(低於400℃)加工工藝形成多個電晶體,並將它們與受主晶圓9510對準標誌對齊(未顯示)。為便於說明,後面之圖紙將不再顯示用於促進晶圓與晶圓之間黏結之氧化層(例如9502)。 As shown in FIG. 95C , the remaining N+ layer 9503 , P-doped layer 9504 , P+ doped layer 9506 , N-doped layer 9508 and oxide layer 9502 have been layered onto the acceptor wafer 9510 . The uppermost layer of the N+ doped layer 9503' can be polished smooth and flat by chemical or mechanical means. Multiple transistors have now been formed using a low temperature (below 400°C) process and aligned with the acceptor wafer 9510 alignment marks (not shown). For ease of illustration, subsequent drawings will not show the oxide layer (eg, 9502) used to promote wafer-to-wafer bonding.

如圖95D所示,電晶體隔離區在成型時可首先進行光刻,接著再透過電漿體/反應式離子蝕刻,至少達到受主基板9510之頂部氧化層,以移除N+摻雜層部分9503、P-摻雜層9504、P+摻雜層9506和N-摻雜層9508。接著,低溫間隙填充氧化層可發生澱積,並透過化學-機械方式打磨,保留在電晶體隔離區9520中。這樣,已進一步形成了RCAT電晶體N+摻雜區9513、P-摻雜區9514、P+摻雜區9516和N-摻雜區9518。 As shown in Figure 95D, the transistor isolation region can be formed by photolithography first, and then through plasma/reactive ion etching, at least reaching the top oxide layer of the acceptor substrate 9510 to remove the N+ doped layer part 9503, P-doped layer 9504, P+ doped layer 9506 and N-doped layer 9508. Next, a low temperature gap-fill oxide layer may be deposited and chemical-mechanical polished to remain in the transistor isolation region 9520 . In this way, the N+ doped region 9513, the P-doped region 9514, the P+ doped region 9516 and the N-doped region 9518 of the RCAT transistor have been further formed.

如圖95E所示,晶圓之p-RCAT部分N+摻雜區9513和P-摻雜區9514可進行光刻,並透過電漿體/反應式離子蝕刻或選擇性濕式蝕刻法進行移除。接下來p-RCAT隱藏溝槽9542可進行掩膜處理和蝕刻。可採取濕式化學或電漿體/反應式離子蝕刻技術將隱藏溝槽表面和邊緣打磨光滑,減少強電場效應。這些工藝步驟就形成了P+源極和汲極區9526和N-電晶體溝槽區9528。 As shown in FIG. 95E, the p-RCAT portion of the wafer with N+ doped regions 9513 and P- doped regions 9514 can be photolithographically removed by plasma/reactive ion etching or selective wet etching. . Next, the p-RCAT hidden trench 9542 can be masked and etched. Wet chemical or plasma/reactive ion etching techniques can be used to smooth the surface and edges of hidden trenches to reduce the effect of strong electric fields. These process steps form the P+ source and drain regions 9526 and the N- transistor trench region 9528 .

如圖95F所示,可形成柵極氧化層9511,柵極金屬材料9554可能會發生澱積。柵極氧化層9511可選擇與具體之柵極金屬9554之功函數相匹配之原子層澱積(ALD)柵極電介質,符合前文所述之高-k金屬柵極工藝方案之行業標準,定位為p-溝槽RCAT用途。此外,柵極氧化區9511可透過低溫氧化澱積或矽表面之低溫微波電漿體氧化形成。接下來柵極材料(例如鉑或鋁)可能會澱積。接著可採取化學-機械方式對柵極材料9554進行打磨,採取掩膜和蝕刻之方法對p-RCAT柵電極9554’進行處理。 As shown in Figure 95F, a gate oxide layer 9511 may be formed and a gate metal material 9554 may be deposited. The gate oxide layer 9511 can choose an atomic layer deposition (ALD) gate dielectric that matches the work function of the specific gate metal 9554, which conforms to the industry standard of the high-k metal gate process mentioned above, and is positioned as p-groove RCAT use. In addition, the gate oxide region 9511 can be formed by low temperature oxide deposition or low temperature microwave plasma oxidation on the silicon surface. Next gate material such as platinum or aluminum may be deposited. Then, the gate material 9554 can be polished by a chemical-mechanical method, and the p-RCAT gate electrode 9554' can be processed by masking and etching.

如圖95G所示,低溫氧化層9550可發生澱積並平面化,覆蓋住已成型之p-RCAT。這樣一來就可開始加工並形成n-RCAT。 As shown in Figure 95G, a low temperature oxide layer 9550 can be deposited and planarized to cover the formed p-RCAT. This allows processing to begin and form n-RCAT.

如圖95H所示,n-RCAT隱藏溝槽9544可進行掩膜處理和蝕刻。可採取濕式化學或電漿體/反應式離子蝕刻技術將隱藏溝槽表面和邊緣打磨光滑,減少強電場效應。這些工藝步驟就形成了N+源極和汲極區9533和P-電晶體溝槽區9534。 As shown in Figure 95H, the n-RCAT hidden trench 9544 can be masked and etched. Wet chemical or plasma/reactive ion etching techniques can be used to smooth the surface and edges of hidden trenches to reduce the effect of strong electric fields. These process steps form the N+ source and drain regions 9533 and the P- transistor trench region 9534 .

如圖95I所示,可形成柵極氧化層9512,柵極金屬材料9556可能會發生澱積。柵極氧化層9512可選擇與具體之柵極金屬9556之功函數相匹配之原子層澱積(ALD)柵極電介質,符合前文所述之高-k金屬柵極工藝方案之行業標準,定位為n-溝槽RCAT。此外,柵極氧化區9512可透過低溫氧化澱積或矽表面之低溫微波電漿體氧化形成。接下來柵極材料(例如鎢或鋁)可能會澱積。接著可採取化學-機械方式對柵極材料9556進行打磨,採取掩膜和蝕刻之方法對柵電極9556’進行處理。 As shown in FIG. 95I, a gate oxide layer 9512 may be formed and a gate metal material 9556 may be deposited. The gate oxide layer 9512 can choose an atomic layer deposition (ALD) gate dielectric that matches the work function of the specific gate metal 9556, which conforms to the industry standard of the high-k metal gate process scheme mentioned above, and is positioned as n-groove RCAT. In addition, the gate oxide region 9512 can be formed by low temperature oxide deposition or low temperature microwave plasma oxidation on the silicon surface. Next gate material such as tungsten or aluminum may be deposited. Next, the gate material 9556 can be polished by a chemical-mechanical method, and the gate electrode 9556' can be processed by masking and etching.

如圖95J所示,低溫氧化層9552可覆蓋整個結構,可透過化學-機械打磨使其平面化。可透過光刻和電漿體/反應式離子蝕刻形成接點和金屬佈線。n-RCAT N+源極和汲極區9533、P-電晶體溝槽區9534、柵極電介質9512和柵電極9556’如圖所示。p-RCAT P+源極和汲極區9526、N-電晶體溝槽區9528、柵極電介質9511和柵電極9554’如圖所示。電晶體隔離區9520、氧化層9552、n-RCAT源極接點 9562、柵極接點9564和汲極接點9566如圖所示。p-RCAT源極接點9572、柵極接點9574和汲極接點9576如圖所示。n-RCAT源極接點9562和汲極接點9566與各自之N+區9533發生電耦合。n-RCAT柵極接點9564與柵電極9556’發生電耦合。p-RCAT源極接點9572和汲極接點9576與各自之N+區9526發生電耦合。n-RCAT柵極接點9574與柵電極9554’發生電耦合。P+摻雜區9516和N-摻雜區9518之接點(未顯示)可用於允許噪音抑制偏置和背柵/基板偏置。 As shown in Figure 95J, a low temperature oxide layer 9552 can cover the entire structure, which can be planarized by chemical-mechanical polishing. Contacts and metal wiring can be formed by photolithography and plasma/reactive ion etching. n-RCAT N+ source and drain regions 9533, P- transistor trench region 9534, gate dielectric 9512 and gate electrode 9556' are shown. The p-RCAT P+ source and drain regions 9526, N- transistor trench region 9528, gate dielectric 9511 and gate electrode 9554' are shown. Transistor isolation region 9520, oxide layer 9552, n-RCAT source contact 9562, gate contact 9564 and drain contact 9566 are shown. The p-RCAT source contact 9572, gate contact 9574 and drain contact 9576 are shown. The n-RCAT source contact 9562 and drain contact 9566 are electrically coupled to the respective N+ region 9533 . n-RCAT gate contact 9564 is electrically coupled to gate electrode 9556&apos;. The p-RCAT source contact 9572 and drain contact 9576 are electrically coupled to respective N+ regions 9526 . n-RCAT gate contact 9574 is electrically coupled to gate electrode 9554&apos;. Junctions (not shown) of P+ doped regions 9516 and N- doped regions 9518 may be used to allow noise suppression biasing and back gate/substrate biasing.

接下來可利用傳統方法形成佈線金屬化區。可能會形成穿層過孔9560(未顯示),在受主晶圓金屬連接焊盤9580(未顯示)使互補RCAT之金屬化區域與受主基板9510發生電耦合。這個過程可透過預製作晶圓大小之摻雜層之簡單層切形成單晶矽n-RCAT和p-RCAT。它們可與下方之多金屬層半導體組件連接起來,避免將下方之組件裸露在高溫下。 Next, wiring metallization can be formed using conventional methods. Through-layer vias 9560 (not shown) may be formed to electrically couple the metallized regions of the complementary RCAT to the acceptor substrate 9510 at acceptor wafer metal connection pads 9580 (not shown). This process enables single crystal silicon n-RCAT and p-RCAT to be formed by simple layer dicing of prefabricated wafer-sized doped layers. They can be connected with the underlying multi-metal layer semiconductor components to avoid exposing the underlying components to high temperature.

具有一般技藝之人可將圖95A至圖95J中提到之例子僅作為典型範例看待,並非按比例縮小。技藝高超之人可考量更多變化情況。比如,可在p-RCAT之前加工n-RCAT或者適用各種蝕刻硬膜。技藝高超之人可能會進一步考量對工藝流程稍作變化生成組件,而非互補RCAT,例如,雙極結型互補電晶體,或帶凸起源極和汲極擴展部分之互補電晶體,或無結型互補電晶體,或V形槽互補電晶體。透過閱讀本說明書,可使技藝高超之人想起如何在本發明範圍內對其他地方進行修改。因此,本發明僅受限於附加之 權利要求。 Those of ordinary skill may consider the examples mentioned in FIGS. 95A-95J to be representative examples only and not scaled down. A skilled person can consider more variations. For example, n-RCAT can be processed before p-RCAT or various etched hard films can be applied. A skilled person might further consider making a slight change to the process flow to generate components other than complementary RCATs, e.g. bipolar junction complementary transistors, or complementary transistors with raised source and drain extensions, or junctionless Type complementary transistor, or V-groove complementary transistor. A reading of this specification will allow the skilled person to recall how to make modifications elsewhere within the scope of the invention. Accordingly, the present invention is limited only by the additional Rights request.

在同一層上建設“n”型和“p”行電晶體之另外一種方法是先在施主晶圓上部分實施電晶體成形之第一個步驟(帶常規CMOS加工過程),包含“虛擬柵極”,這種工藝適用於後柵極電晶體。在本發明之這個案例中,單晶矽之層切操作可在完成虛擬柵極之後、替代柵極成型之前進行。層切之前之操作沒有溫度限制,層切過程中和層切之後之操作應在低溫下進行,通常應低於400℃。虛擬柵極和替代柵極可採用多種材料(例如矽和二氧化矽),或者金屬和低-k材料(例如TiAlN和HfO2)。另外一個例子是高-k金屬柵極(HKMG)CMOS電晶體,有45nm、32nm、22nm和其他代之CMOS英代爾(Intel)和臺灣積體電路製造股份有限公司(TSMC)已經證實了“後柵極”方法建設高性能HKMG CMOS電晶體之優點(C,Auth等人;VLSI2008;頁碼:128-129和C.H.Jan等人;2009 IEDM;頁碼:647)。 Another way to build "n" and "p" transistors on the same layer is to partially implement the first steps of transistor formation (with conventional CMOS processing) on the donor wafer, including the "dummy gate ", this process is suitable for gate-last transistors. In this case of the present invention, the layer cutting operation of the single crystal silicon can be performed after the completion of the dummy gate and before the formation of the replacement gate. There is no temperature limit for the operation before layer cutting, and the operation during and after layer cutting should be carried out at low temperature, usually lower than 400°C. Dummy gates and replacement gates can be made of various materials such as silicon and silicon dioxide, or metals and low-k materials such as TiAlN and HfO2. Another example is the high-k metal gate (HKMG) CMOS transistor, which has 45nm, 32nm, 22nm and other alternative CMOS Intel and Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC) have confirmed " Advantages of gate-last" approach to building high-performance HKMG CMOS transistors (C, Auth et al; VLSI2008; Pages: 128-129 and C.H.Jan et al; 2009 IEDM; Page: 647).

如圖70A所示,以HKMG“後柵極”之方式採用先進加工體矽施主晶圓7000,直至多晶矽虛擬柵極出現CMP裸露為止。圖70A展示了體矽施主晶圓7000之橫截面、電晶體之間之柵側壁7002、n-型和p-型CMOS虛擬柵極之多晶矽7004和柵極氧化層7005、它們相應的源極和汲極7006(NMOS)和7007(PMOS)以及層間電介質(ILD)7008。圖70A中這些結構就說明了電晶體成形過程之第一步驟之完成情況。如圖70B所示,在這一階段中,或者是 剛剛對層7008進行CMP以裸露多晶矽虛擬柵極,或者使氧化層7008平面化,不裸露虛擬柵極,注入原子種類7010(例如H+)可為適於層切之施主基板之體矽準備好切割平面7012。 As shown in FIG. 70A , the bulk silicon donor wafer 7000 is advanced processed by HKMG "gate last" until CMP exposure of the polysilicon dummy gate. Figure 70A shows a cross-section of a bulk silicon donor wafer 7000, gate sidewalls 7002 between transistors, polysilicon 7004 and gate oxide 7005 for n-type and p-type CMOS dummy gates, their corresponding source and Drains 7006 (NMOS) and 7007 (PMOS) and interlayer dielectric (ILD) 7008 . These structures in Figure 70A illustrate the completion of the first step in the transistor forming process. As shown in Figure 70B, at this stage, either Just after CMP of layer 7008 to expose polysilicon dummy gates, or planarize oxide layer 7008 without exposing dummy gates, implanted atomic species 7010 (eg, H+) can prepare the bulk silicon of the donor substrate suitable for layer dicing Plane 7012.

如圖70C所示,現在可使用低溫工藝(可促進低溫釋放)將施主晶圓7000和載子基板7014臨時黏結起來。載子基板7014可採用玻璃質基板,使受主晶圓之光學對準達到最先進平。載子基板7014與施主晶圓7000在介面7016之間之臨時黏結可使用聚合材料,例如聚醯亞胺杜邦HD3007。這種材料可透過鐳射燒蝕、紫外線輻照或熱分解之方法在接下來之步驟中釋放掉。或者,也可使用單極靜電或雙極靜電技術進行臨時黏結,例如Beam Services Inc公司生產之Apache工具。 As shown in Figure 70C, the donor wafer 7000 and the carrier substrate 7014 can now be temporarily bonded using a low temperature process (which facilitates low temperature release). The carrier substrate 7014 can be a glass substrate, so that the optical alignment of the acceptor wafer can reach the most advanced level. The temporary bonding between the carrier substrate 7014 and the donor wafer 7000 at the interface 7016 can use a polymeric material, such as polyimide DuPont HD3007. This material can be released in a subsequent step by means of laser ablation, UV irradiation or thermal decomposition. Alternatively, temporary bonding can be performed using unipolar electrostatic or bipolar electrostatic techniques, such as the Apache tool from Beam Services Inc.

如圖70D所示,接下來可在切割平面上切割施主晶圓7000,再採取化學-機械打磨(CMP)之方式使其變薄。如此一來,電晶體柵側壁7002可裸露在施主晶圓表面7018上。或者,CMP操作也可持續到接頭之底部,生成完全空乏之SOI層。 As shown in FIG. 70D , the donor wafer 7000 can then be diced on a dicing plane and thinned by chemical-mechanical polishing (CMP). As such, the transistor gate sidewalls 7002 may be exposed on the donor wafer surface 7018 . Alternatively, the CMP operation can be continued down to the bottom of the joint, resulting in a completely depleted SOI layer.

如圖70E所示,薄薄之單晶施主晶圓表面7018可用於藉由氧化層7020之低溫氧化或沉澱進行層切,以及電漿體或其他表面處理,以便為晶圓氧化物與氧化物之間之黏結準備好氧化表面7022。在為氧化物與氧化物之間之黏結準備表面時,也可在808受主晶圓上採取類似之表面處理方法。 As shown in FIG. 70E , the thin single crystal donor wafer surface 7018 can be used for layer dicing by low temperature oxidation or precipitation of an oxide layer 7020, as well as plasma or other surface treatments to clean the wafer from oxide to oxide. The bond between them is ready to oxidize the surface 7022. Similar surface treatments can also be used on 808 acceptor wafers when preparing the surface for oxide-to-oxide bonding.

如圖70E所示,可進行低溫(例如,低於400℃)層切,以便將變薄的、在第一步驟之電晶體成形預加工之HKMG矽層7001(附帶載子基板7014)轉移到受主晶圓808(頂部金屬化)上,包含金屬插接條7024,成為在切出層上形成之電路與下方電路一層808之間連接線之接合焊盤。 As shown in FIG. 70E , low temperature (eg, below 400° C.) layer dicing can be performed to transfer the thinned HKMG silicon layer 7001 (with carrier substrate 7014 ) pre-processed in the first step of transistor formation to On the acceptor wafer 808 (top metallization), include metal straps 7024 that serve as bonding pads for connection lines between circuits formed on the cut-out layer and the circuit layer 808 below.

如圖70F所示,接下來可採取低溫工藝(例如鐳射燒蝕)釋放載子基板7014。 As shown in FIG. 70F , the carrier substrate 7014 may be released by a low-temperature process (such as laser ablation) next.

黏結在一起之受主晶圓808和HKMG電晶體矽層7001現在已準備妥當,可用于先進之“後柵極”電晶體之成形了。如圖70G所示,可對層間電介質7008進行化學-機械打磨,以便露出多晶矽虛擬柵極之頂層。接下來可採取蝕刻方式將多晶矽虛擬柵極移除,高-k柵極電介質7026和PMOS特定功函數金屬柵極7028可發生澱積。PMOS功函數金屬柵極可從NMOS電晶體上移除,NMOS特定功函數金屬柵極7030可發生澱積。在NMOS和PMOS柵極上填充鋁7032,並對金屬進行化學-機械打磨操作。 The bonded acceptor wafer 808 and HKMG transistor silicon layer 7001 are now ready for advanced "gate last" transistor formation. As shown in FIG. 70G, the interlayer dielectric 7008 may be chemical-mechanical polished to expose the top layer of the polysilicon dummy gate. Next, the polysilicon dummy gate can be removed by etching, and the high-k gate dielectric 7026 and the PMOS specific work function metal gate 7028 can be deposited. The PMOS work function metal gate can be removed from the NMOS transistor and the NMOS specific work function metal gate 7030 can be deposited. Aluminum 7032 is filled on the NMOS and PMOS gates, and the metal is chemical-mechanical polished.

如圖70H所示,電介質層7032可能會發生澱積,現在可進行常規柵極7034和源極/汲極7036接點成形和金屬化操作,以便將單晶層上之電晶體連接起來,並透過通孔7040連接到受主晶圓808之頂部金屬化插接條7024上。如此一來,可穿過切出層將施主晶圓和受主晶圓連接起來。可形成頂部金屬層,成為受主晶圓接合插接條。重複上述工藝流程,以便將另外一個預加工之單晶兩步驟成形之電 晶體薄層定位好。還可利用上述流程建設其他類型之柵極,比如,熱氧化層上之摻雜多晶矽、氮氧化合物上之摻雜多晶矽、或其他金屬柵極配置。這些柵極可作為“虛擬柵極”,執行薄薄之單晶層之層切,替代柵電極和柵極養護曾,然後在進行低溫佈線加工。 As shown in Figure 70H, a dielectric layer 7032 may be deposited, and conventional gate 7034 and source/drain 7036 contact formation and metallization operations can now be performed to connect the transistors on the single crystal layer and Connect to the top metallization strap 7024 of the acceptor wafer 808 through vias 7040 . In this way, the donor wafer and the acceptor wafer can be connected through the cut-out layer. A top metal layer can be formed to become the acceptor wafer bonding strip. Repeat the above process to make another pre-processed single crystal two-step forming electrode The thin layer of crystals is well positioned. Other types of gates, such as doped polysilicon on thermal oxide, doped polysilicon on oxynitride, or other metal gate configurations, can also be constructed using the above process. These gates can be used as "dummy gates" to perform layer dicing of thin single crystal layers, replacing gate electrodes and gate maintenance, and then perform low-temperature wiring processing.

或者,可使用矽晶圓作為載子基板7014,使用紅外線和光學組件對準。圖82A至82G可用於說明載子晶圓之用途。圖82A說明了在第一個施主晶圓8206上準備帶虛擬柵極8202之電晶體之第一個步驟。第一個步驟可完成電晶體成形之第一個階段。 Alternatively, a silicon wafer can be used as the carrier substrate 7014, aligned using infrared and optical components. 82A to 82G can be used to illustrate the use of a carrier wafer. FIG. 82A illustrates the first steps in preparing transistors with dummy gates 8202 on a first donor wafer 8206. The first step completes the first stage of transistor shaping.

圖82B說明了透過注入原子粒子8216(例如H+)之方法形成切割線8208之方法。 FIG. 82B illustrates a method of forming dicing lines 8208 by implanting atomic particles 8216 (eg, H+).

圖82C說明了將第一個施主晶圓8206與第二個施主晶圓8226永久黏結起來之方法。如前文所述,永久黏結可能是氧化物與氧化物晶圓之間之黏結。 Figure 82C illustrates a method of permanently bonding a first donor wafer 8206 to a second donor wafer 8226. As mentioned earlier, the permanent bond may be an oxide-to-oxide wafer bond.

圖82D展示了第二個施主晶圓8226(在將第一個晶圓切割掉之後它成為載子晶圓),剩下一薄層8206,帶有已埋置之虛擬柵極電晶體8202。 Figure 82D shows a second donor wafer 8226 (which becomes the carrier wafer after the first wafer is diced), leaving a thin layer 8206 with embedded dummy gate transistors 8202.

圖82E說明了透過向第二個施主晶圓8226中注入原子類型8246(例如H+)之方式形成第二個切割線8218)。 FIG. 82E illustrates the formation of a second dicing line 8218 by implanting an atomic type 8246 (eg, H+) into a second donor wafer 8226 .

圖82F說明了層切之第二個步驟。透過這一步驟,可將已準備好之將要永久黏結之虛擬柵極電晶體8202帶入外殼808。為便於解釋,此處省略了有關用於各個黏結環節之表面層準備之步驟。 Figure 82F illustrates the second step of layer cutting. Through this step, the prepared dummy gate transistor 8202 to be permanently bonded is brought into the housing 808 . For the convenience of explanation, the steps related to the preparation of the surface layer for each bonding link are omitted here.

圖82G展示了外殼808,頂部帶有虛擬柵極電晶體8202。此時第二個施主晶圓已被切割掉,虛擬柵極電晶體頂部之層已被移除。這個流程現在可以開始了,以便用最終之柵極替代掉虛擬柵極,形成金屬互聯層,繼續3D製作過程。 Figure 82G shows housing 808 with dummy gate transistor 8202 on top. At this point the second donor wafer has been diced and the layer on top of the dummy gate transistors has been removed. The process can now begin to replace the dummy gates with the final gates, form the metal interconnect layer, and continue the 3D fabrication process.

採取載子晶圓流程時,還可以使用另外一種很有趣之方法。在這個過程中,我們可以使用已切出層之兩邊,在其中一邊建設NMOS,在另外一邊建設PMOS。正確記錄這個過程中替代柵極之時間能夠確保互相對齊之電晶體具有良好之性能。這個流程還可以建設壓縮3D模組庫晶片。 There is another interesting approach that can be used when taking the carrier wafer flow. In this process, we can use both sides of the cut-out layer to build NMOS on one side and PMOS on the other side. Properly timing the replacement gate during this process will ensure good performance of the transistors aligned with each other. This process can also build compressed 3D module library chip.

如圖83A所示,可使用諸如HKMG“後柵極”流程利用先進技術加工SOI(絕緣基板上之矽)施主晶圓8300,使用調整後之熱循環補償後期之熱處理,直至多晶矽虛擬柵極出現CMP裸露為止。或者,施主晶圓8300在開始時可作為體矽晶圓,利用氧離子注入和高熱退火之方式形成埋置氧化層,例如SIMOX工藝(即利用氧離子注入進行隔離)。圖83A展示了SOI施主晶圓基板8300之橫截面、埋置之氧化層(即BOX)8301、SOI晶圓之薄薄的氧化層8302、電晶體之間之柵側壁8303、n型CMOS虛擬柵極之多晶矽8304和柵極氧化層8305,以及NMOS相關之源極和汲極8306、NMOS電晶體溝槽8307和NMOS層間電介質(ILD)8308。或者,也可在這一階段建設PMOS組件或完整之CMOS組件。這個步驟可完成電晶體成形之第一個階段。 As shown in Figure 83A, an SOI (silicon on insulator) donor wafer 8300 can be processed using advanced techniques such as the HKMG "gate-last" process, using adjusted thermal cycling to compensate for later thermal processing until polysilicon dummy gates appear CMP until bare. Alternatively, the donor wafer 8300 can be initially used as a bulk silicon wafer, and a buried oxide layer is formed by oxygen ion implantation and high temperature annealing, such as the SIMOX process (ie isolation by oxygen ion implantation). FIG. 83A shows a cross-section of an SOI donor wafer substrate 8300, a buried oxide layer (i.e., BOX) 8301, a thin oxide layer 8302 of the SOI wafer, gate sidewalls 8303 between transistors, and n-type CMOS dummy gates. Pole polysilicon 8304 and gate oxide layer 8305, and NMOS related source and drain 8306, NMOS transistor trench 8307 and NMOS interlayer dielectric (ILD) 8308. Alternatively, PMOS components or complete CMOS components can also be built at this stage. This step completes the first stage of transistor shaping.

如圖83B所示,在這一階段中,或者是剛剛對層8308進行CMP以裸露多晶矽虛擬柵極,或者使氧化層8308平面化,不裸露偽柵極,注入原子種類8310(例如H+)可為適於層切之施主基板之體矽準備好切割平面8312。 As shown in FIG. 83B , at this stage, either layer 8308 has just been CMPed to expose polysilicon dummy gates, or oxide layer 8308 is planarized without exposing dummy gates, and implanted atomic species 8310 (eg, H+) can be A dicing plane 8312 is prepared for the bulk silicon of the donor substrate suitable for layer dicing.

如圖83C所示,SOI施主晶圓8300現在可永久性地與載子晶圓8320黏結起來。載子晶圓8320具有氧化層8316,可用於氧化物-氧化物與施主晶圓表面8314之間之黏結。 The SOI donor wafer 8300 can now be permanently bonded to the carrier wafer 8320 as shown in FIG. 83C . The carrier wafer 8320 has an oxide layer 8316 that can be used for oxide-oxide bonding to the donor wafer surface 8314 .

如圖83D所示,接下來可在切割平面8312上切割施主晶圓8300,再採取化學-機械打磨(CMP)之方式使其變薄,表面8322可用於電晶體成型。 As shown in FIG. 83D , the donor wafer 8300 can then be diced on the dicing plane 8312 and thinned by chemical-mechanical polishing (CMP). The surface 8322 can be used for transistor molding.

表面8322上之施主晶圓層8300可採用先進的“後柵極”加工方法進行加工,以形成帶虛擬柵極之PMOS電晶體。圖83A展示了PMOS組件成型之後埋置之氧化層(BOX)8301之橫截面、SOI基板之薄薄的矽層8300、電晶體之間之柵側壁8333、p型CMOS虛擬柵極之多晶矽8334和柵極氧化層8335,以及PMOS相關之源極和汲極8336、PMOS電晶體溝槽8337和PMOS層間電介質(ILD)8338。由於共用之基板8300具有相同之對準標誌,採用先進工藝可將PMOS電晶體與NMOS電晶體精確對齊。在這個步驟中,或者是剛剛對層8338進行CMP,這個加工流程可裸露PMOS多晶矽虛擬柵極或者使氧化層8338平面化,不裸露虛擬柵極。現在可將晶圓放入高溫退火爐中,以開啟NMOS和PMOS電晶體。 The donor wafer layer 8300 on the surface 8322 can be processed using advanced "gate last" processing methods to form PMOS transistors with dummy gates. Figure 83A shows the cross-section of the buried oxide layer (BOX) 8301 after the PMOS component is formed, the thin silicon layer 8300 of the SOI substrate, the gate sidewall 8333 between the transistors, the polysilicon 8334 of the p-type CMOS dummy gate and Gate oxide 8335 , and PMOS related source and drain 8336 , PMOS transistor trench 8337 and PMOS interlayer dielectric (ILD) 8338 . Since the common substrate 8300 has the same alignment mark, the PMOS transistor and the NMOS transistor can be precisely aligned using advanced technology. In this step, or just CMP layer 8338, this process can expose the PMOS polysilicon dummy gate or planarize the oxide layer 8338 without exposing the dummy gate. The wafer can now be placed in a high temperature annealing furnace to turn on the NMOS and PMOS transistors.

如圖83F所示,接下來可注入原子種類8340(例如 H+)可為適於層切之載子晶圓基板8320之體矽準備好切割平面8321。 As shown in FIG. 83F, atomic species 8340 (e.g., H+) The dicing plane 8321 may be prepared for bulk silicon of the carrier wafer substrate 8320 suitable for layer dicing.

PMOS電晶體現在已經準備好,可採用最先進工藝完成“後柵極”電晶體成型步驟了。如圖83G所示,可對層間電介質8338進行化學-機械打磨,以便露出多晶矽偽柵極之頂層。接下來可採取蝕刻方式將多晶矽虛擬柵極移除,PMOS高-k柵極電介質8340和PMOS特定功函數金屬柵極8341可發生澱積。在PMOS柵極上填充鋁8342,並對金屬進行化學-機械打磨操作。電介質層8339可發生澱積,常規柵極8343和源極/汲極8344接點可成型並被金屬化。如圖83G所示,可部分形成PMOS層至NMOS層通孔8347並發生金屬化,氧化層8348可發生澱積,為黏結做好準備。 The PMOS transistors are now ready for the "gate last" transistor forming step using state-of-the-art processes. As shown in Figure 83G, the interlayer dielectric 8338 may be chemical-mechanical polished to expose the top layer of the polysilicon dummy gate. Next, the polysilicon dummy gate can be removed by etching, and the PMOS high-k gate dielectric 8340 and the PMOS specific work function metal gate 8341 can be deposited. Aluminum 8342 is filled on the PMOS gate, and the metal is chemical-mechanical polished. A dielectric layer 8339 can be deposited and conventional gate 8343 and source/drain 8344 contacts can be formed and metallized. As shown in FIG. 83G, the PMOS layer to NMOS layer via hole 8347 can be partially formed and metallized, and an oxide layer 8348 can be deposited to prepare for bonding.

如圖83H所示,接下來載子晶圓和雙邊n/p層可進行對齊,並利用相關之接合插接條金屬8350永久與外殼受主晶圓808黏結起來。 As shown in FIG. 83H , the carrier wafer and the double-sided n/p layer can then be aligned and permanently bonded to the case acceptor wafer 808 with the associated bonding strap metal 8350 .

如圖83I所示,接下來可在切割平面8321上切割載子晶圓8320,再採取化學-機械打磨(CMP)之方式使其變薄至氧化層8316。 As shown in FIG. 83I , next, the carrier wafer 8320 can be diced on the dicing plane 8321 , and then the oxide layer 8316 can be thinned by chemical-mechanical polishing (CMP).

NMOS電晶體現在已經準備好,可採用最先進之工藝完成“後柵極”電晶體成型步驟了。如圖83J所示,可對NMOS層間電介質8308進行化學-機械打磨,以便露出NMOS多晶矽虛擬柵極之頂層。接下來可採取蝕刻方式將多晶矽虛擬柵極移除,NMOS高-k柵極電介質8360和NMOS特定功函數金屬柵極8361可發生澱積。在NMOS柵 極上填充鋁8362,並對金屬進行化學-機械打磨操作。電介質層8369可發生澱積,常規柵極8363和源極/汲極8364接點可成型並被金屬化。可在NMOS層至PMOS層之間形成連接8347之通孔8367,並使通孔發生金屬化。 The NMOS transistors are now ready for the "gate last" transistor forming step using state-of-the-art processes. As shown in Figure 83J, the NMOS interlayer dielectric 8308 can be chemical-mechanical polished to expose the top layer of the NMOS polysilicon dummy gate. Next, the polysilicon dummy gate can be removed by etching, and the NMOS high-k gate dielectric 8360 and the NMOS specific work function metal gate 8361 can be deposited. In NMOS gate The pole is filled with aluminum 8362, and the metal is chemical-mechanical polished. A dielectric layer 8369 can be deposited and conventional gate 8363 and source/drain 8364 contacts can be formed and metallized. Vias 8367 connecting 8347 between the NMOS layer and the PMOS layer can be formed and metallized.

如圖83K所示,電介質層8370可發生澱積。接下來可將層與層之間之通孔8372對齊、掩膜、蝕刻並金屬化,以便透過電力方式將其連接到受主晶圓808和金屬接合插接條8350。如圖83K所示,可形成最頂部金屬層,成為受主晶圓接合插接條。重複上述工藝流程,以便將另外一個預加工之單晶電晶體薄層定位好。具有一般技藝之人可將圖83A至圖83K中提到之例子僅作為典型範例看待,並非按比例縮小。技藝高超之人可考量更多變化情況。比如,BOX8301每一側之電晶體可完全使用CMOS;或者一側使用CMOS,另一側使用其他n型MOSFET電晶體;或者使用其他組合方式和其他類型之半導體組件。透過閱讀本說明書,可使技藝高超之人想起如何在本發明範圍內對其他地方進行修改。因此,本發明僅受限於附加之權利要求。 As shown in Figure 83K, a dielectric layer 8370 may be deposited. Layer-to-layer vias 8372 may then be aligned, masked, etched, and metalized to electrically connect them to the acceptor wafer 808 and metal bond bars 8350 . As shown in FIG. 83K, the topmost metal layer may be formed to become the acceptor wafer bonding strip. The above process flow is repeated to position another pre-processed single crystal transistor thin layer. Those of ordinary skill may consider the examples mentioned in FIGS. 83A-83K to be representative examples only and not to scale. A skilled person can consider more variations. For example, the transistors on each side of BOX8301 can completely use CMOS; or use CMOS on one side and other n-type MOSFET transistors on the other side; or use other combinations and other types of semiconductor components. A reading of this specification will allow the skilled person to recall how to make modifications elsewhere within the scope of the invention. Accordingly, the invention is limited only by the appended claims.

圖83L是重複晶片83L00(是形成柵極陣列之基礎晶片)和兩個NMOS電晶體83L04(帶共用擴散層83L05,“正面向下”)和兩個PMOS電晶體83L02(帶共用擴散層)之俯視圖NMOS電晶體柵極覆蓋住PMOS電晶體柵極83L10,覆蓋住之柵極透過通孔83L12互相連接在一起。VDD電源線83L06在運行過程中成為正面向下通用結構之一部分,透過通孔83L20與上方之層連接起來。擴散連接 83L08將會使用正面向下通用結構83L17,並透過通孔83L14、83L16和83L18將其帶上去。 Figure 83L is a repeating wafer 83L00 (which is the base wafer forming the gate array) and two NMOS transistors 83L04 (with a common diffusion layer 83L05, "face down") and two PMOS transistors 83L02 (with a common diffusion layer) In the plan view, the NMOS transistor gate covers the PMOS transistor gate 83L10, and the covered gates are connected to each other through the through hole 83L12. The VDD supply line 83L06 becomes part of the front-down common structure during operation, and is connected to the layer above through the via 83L20. diffuse connection The 83L08 will use the front down generic structure 83L17 and bring it up through vias 83L14, 83L16 and 83L18.

圖83L1展示了依照定制NMOS接點83L22、83L24和定制金屬83L26定制之通用晶片83L00,可形成雙逆變。Vss電源線83L25可在NMOS電晶體頂部運行。 Figure 83L1 shows a general-purpose chip 83L00 customized according to custom NMOS contacts 83L22, 83L24 and custom metal 83L26, which can form a double inverter. The Vss power line 83L25 can be run on top of an NMOS transistor.

圖83L2是用於定制NOR功能之通用晶片83L00之圖紙;圖83L3是用於定制NAND功能之通用晶片83L00之圖紙;圖83L3是用於定制多工器功能之通用晶片83L00之圖紙。因此,83L00可廣泛用於定制各種想要之邏輯功能。因此,使用晶片83L00之通用柵極陣列可使用定制接點通孔和金屬層定制任何邏輯功能。 FIG. 83L2 is a drawing of a general-purpose chip 83L00 for customizing NOR functions; FIG. 83L3 is a drawing of a general-purpose chip 83L00 for customizing NAND functions; FIG. 83L3 is a drawing of a general-purpose chip 83L00 for customizing multiplexer functions. Therefore, 83L00 can be widely used to customize various desired logic functions. Thus, any logic function can be customized using custom contact vias and metal layers using the generic gate array of chip 83L00.

另外一個辦法請參考圖70及其說明。圖70B-1詳細說明了這個方法。首先透過掩膜和蝕刻緻密材料之保護注入停蝕層7050(例如5000埃之鉭)可將注入原子類別7010(例如H+)從敏感柵極區7003上掩蔽,並與5000埃之光刻膠黏結起來。這樣可在施主晶圓和矽晶圓之體矽中生成分段切割平面7012。另外,可採取打磨之方式提供適合層切之光滑黏結表面。 For another method, please refer to Figure 70 and its description. Figure 70B-1 illustrates this method in detail. First, through the mask and etch the protective implant stop layer 7050 of dense material (such as tantalum of 5000 angstroms), the implanted atomic species 7010 (such as H+) can be masked from the sensitive gate region 7003, and bonded with the photoresist of 5000 angstroms stand up. This creates segmented cut planes 7012 in the bulk silicon of the donor wafer and the silicon wafer. In addition, grinding can be used to provide a smooth bonding surface suitable for layer cutting.

還可以使用另外一種是用SOI施主晶圓之方法在垂直方向隔離電晶體。例如,可在垂直堆疊之電晶體之間形成pn接頭,這些接頭可能會出現偏置。此外,可在垂直堆疊之電晶體之間注入氧離子,並進行退火,形成埋置之氧化層。同樣,還可在首次成型之虛擬電晶體上使用SRI技術,其中可選擇性地對SiGe層進行蝕刻,並重新填充氧化 物,產生絕緣矽島狀物。 Another approach that can be used is to use an SOI donor wafer to isolate the transistors in the vertical direction. For example, pn junctions can be formed between vertically stacked transistors, and these junctions can be biased. In addition, oxygen ions can be implanted between vertically stacked transistors and annealed to form a buried oxide layer. Likewise, SRI technology can also be used on first-time dummy transistors, where the SiGe layer is selectively etched and refilled with oxide Objects, resulting in insulating silicon islands.

上述工藝流程之另外一個案例請參考圖70,圖81A至81F對該案例進行了相吸描述,可在預先加工好之外殼基板頂部提供正面向下之CMOS平面電晶體層。從下文和圖70A和70B可以看出,可使用虛擬柵極製作CMOS平面電晶體並在施主晶圓中生成切割平面7012。依照前文描述和圖81A之相關內容,此時可將虛擬柵極移除掉了。 Please refer to FIG. 70 for another example of the above-mentioned process flow. FIGS. 81A to 81F describe the case of attraction, which can provide a face-down CMOS planar transistor layer on the top of the pre-processed housing substrate. As can be seen below and in Figures 70A and 70B, dummy gates can be used to fabricate CMOS planar transistors and create cut planes 7012 in the donor wafer. According to the foregoing description and the related content of FIG. 81A, the dummy gate can be removed at this time.

可如圖81B進行接點和金屬化步驟操作,以便在電晶體正面向下時將它們互相連接起來。 The contact and metallization steps can be performed as in Figure 81B to connect the transistors to each other when they are face down.

如圖81C所示,施主晶圓8100之正面8102可利用氧化物澱積8104、電漿體或其他表面處理進行黏結,以便為晶圓與晶圓直接和氧化物與氧化物之間之黏結準備好氧化表面8106。 As shown in Figure 81C, the front side 8102 of the donor wafer 8100 can be bonded using oxide deposition 8104, plasma or other surface treatment to prepare for wafer-to-wafer direct and oxide-to-oxide bonding Good oxidation surface 8106.

在為氧化物與氧化物之間之黏結準備表面時,也可在808受主晶圓上採取類似之表面處理方法。如圖81D所示,現在可進行低溫(不超過400℃)層切流程,將準備好之施主晶圓8100(帶頂部表面8106)轉移到受主晶圓808上。可使用電晶體線路和金屬佈線對受主晶圓808進行預加工。受主晶圓808可在頂部進行金屬化,包含金屬插接條8124,成為在切出層上形成之電路與下方外殼808中電路層之間連接線之接合焊盤。為便於說明,圖81D至81F中額外增添了STI(淺槽絕緣層)隔離區8130(無通孔7040)。 Similar surface treatments can also be used on 808 acceptor wafers when preparing the surface for oxide-to-oxide bonding. As shown in FIG. 81D , the low temperature (not exceeding 400° C.) layer dicing process can now be performed to transfer the prepared donor wafer 8100 (with top surface 8106 ) onto the acceptor wafer 808 . The acceptor wafer 808 may be pre-processed with transistor lines and metal wiring. The acceptor wafer 808 may be metallized on the top, including metal straps 8124 , which become bond pads for connections between circuits formed on the cut-out layer and circuit layers in the housing 808 below. For ease of illustration, an additional STI (Shallow Trench Insulation) isolation region 8130 (without via 7040 ) is added in FIGS. 81D to 81F .

如圖81E所示,接下來可在切割平面7012上切割施主 晶圓8100,再採取化學-機械打磨(CMP)之方式使其變薄。如此一來,電晶體柵側壁7002和8130可被裸露。或者,CMP操作也可持續到接頭之底部,生成完全空乏之SOI層。 The donor can then be cut on cutting plane 7012 as shown in FIG. 81E The wafer 8100 is thinned by chemical-mechanical polishing (CMP). In this way, the transistor gate sidewalls 7002 and 8130 are exposed. Alternatively, the CMP operation can be continued down to the bottom of the joint, resulting in a completely depleted SOI layer.

如圖81F所示,低溫氧化層或低-k電介質8136可發生澱積,並被平面化。對通往外殼808之通孔8128、受主晶圓接合插接條8124和接點8140和通孔7040進行蝕刻、金屬化並用金屬線8150進行連接,以實現施主晶圓電晶體和受主晶圓之間之電力連接。如圖32和圖33A所示,接合插接條8124之長度至少應達到重複寬度W加上滿足適當之通孔設定規則之邊緣之寬度。滿足通孔設定規則之接合焊盤插接條擴展部分可包含補償因晶圓與晶圓之間之黏結而產生之角度失准,還包含未補償之施主晶圓彎曲和翹曲。步進電機重疊演算法並不補償角度失准。 A low temperature oxide or low-k dielectric 8136 may be deposited and planarized as shown in FIG. 81F. Vias 8128 to housing 808, acceptor wafer bonding strips 8124 and contacts 8140 and vias 7040 are etched, metallized and connected with wires 8150 to implement donor wafer transistor and acceptor die Electrical connections between circles. As shown in Figures 32 and 33A, the length of the splice strip 8124 should be at least as long as the repeat width W plus the width of the edge that satisfies the proper via placement rules. Bond pad strip extensions that meet via set rules can include compensation for angular misalignment due to wafer-to-wafer bonding, as well as uncompensated donor wafer bow and warpage. The stepper motor overlap algorithm does not compensate for angular misalignment.

正面向下工藝具有一些優點。例如,可開啟雙柵極電晶體、反向偏電晶體或進入記憶體應用程式中之浮體。再例如,可如圖81E-1所示建設雙柵極電晶體之背柵極。如前文所述,帶柵極材料8162之低溫柵極氧化層8160可能會生長或澱積,並採取光刻和時刻工藝進行處理。 The face down process has some advantages. For example, double gate transistors can be turned on, reverse biased transistors or floating bodies into memory applications. For another example, the back gate of the double gate transistor can be constructed as shown in FIG. 81E-1. A low temperature gate oxide 8160 with gate material 8162 may be grown or deposited and processed using photolithography and timing processes as previously described.

如圖81F-1所示建設金屬接線圖。 Build the metal wiring diagram as shown in Figure 81F-1.

如圖81F-2所示,也可按照本流程之要求建設帶帶接頭8170和8171之完全空乏之SOI電晶體,並按照圖81E透過CMP使其變薄。 As shown in Figure 81F-2, a fully depleted SOI transistor with connectors 8170 and 8171 can also be constructed according to the requirements of this process and thinned by CMP as shown in Figure 81E.

圖85A至85E展示了上述雙柵極工藝流程之另外一個 案例,可在正面向上流程中提供背柵極,詳情可參考圖70。從下文和圖70A和70B可以看出,可使用虛擬柵極製作CMOS平面電晶體並在施主晶圓(體矽或SOI)中生成切割平面7012。從下文和圖70C中可以看出,施主晶圓可永久性地或暫時性地黏貼到載子基板上,接著再如圖70D所示進行切割和變薄至STI 7002。或者,CMP操作也可持續到接頭之底部,生成完全空乏之SOI層。 Figures 85A to 85E show another alternative to the above double gate process flow For example, a back gate can be provided in a front-up process, see Figure 70 for details. As can be seen below and in Figures 70A and 70B, dummy gates can be used to fabricate CMOS planar transistors and create cut planes 7012 in the donor wafer (bulk or SOI). As can be seen below and in Figure 70C, the donor wafer can be permanently or temporarily attached to the carrier substrate and then diced and thinned to STI 7002 as shown in Figure 70D. Alternatively, the CMP operation can be continued down to the bottom of the joint, resulting in a completely depleted SOI layer.

如圖85A所示,第二層柵極氧化層8502可發生生長或澱積,柵極材料8504可發生澱積。柵極氧化層8502和柵極材料8504可使用低溫(不超過400℃)材料和工藝形成,例如前文所述之TEL SPA柵極氧化物和非晶矽,ALD技術或高-k金屬柵極堆疊(HKMG);如果載子基板為永久性黏結,並且已對現有平面電晶體摻雜物運動進行說明,也可採取較高溫之柵極氧化物或氮氧化合物和摻雜多晶矽。 As shown in FIG. 85A, a second gate oxide layer 8502 may be grown or deposited, and gate material 8504 may be deposited. The gate oxide layer 8502 and the gate material 8504 can be formed using low temperature (not exceeding 400°C) materials and processes, such as the TEL SPA gate oxide and amorphous silicon mentioned above, ALD technology or high-k metal gate stack (HKMG); Higher temperature gate oxide or oxynitride and doped polysilicon can also be used if the carrier substrate is permanently bonded and the dopant movement of existing planar transistors has been described.

如圖85B所示,可勾畫出柵極堆疊層8506之輪廓,電介質8508可發生澱積並使其平面化,接下來可形成局部接點8510和層-層之間之接點8512和金屬化層8516。 As shown in Figure 85B, the gate stack layer 8506 can be outlined, a dielectric 8508 can be deposited and planarized, and then local contacts 8510 and layer-to-layer contacts 8512 and metallization can be formed. Layer 8516.

如圖85C所示,可採取前文所述之方法準備好用於層切之薄薄的單晶施主和載子基板堆疊層,包含氧化層8520。在為氧化物與氧化物之間之黏結準備表面時,也可在外殼808受主晶圓上採取類似之表面處理方法。如圖85C所示,可進行低溫(例如,低於400℃)層切,以便將變薄的、在第一階段之電晶體成形預加工之HKMG矽層7001和背柵極8506(附帶載子基板7014)轉移到受主晶圓808 (頂部金屬化)上,包含金屬插接條8124,成為在切出層上形成之電路與下方電路層808之間連接線之接合焊盤。 As shown in FIG. 85C , a thin stack of single crystal donor and carrier substrates, including oxide layer 8520 , can be prepared for layer dicing by the methods described above. A similar surface treatment can also be used on the housing 808 acceptor wafer in preparing the surface for oxide-to-oxide bonding. As shown in FIG. 85C, low temperature (eg, below 400°C) layer dicing can be performed to separate the thinned HKMG silicon layer 7001 and back gate 8506 (with carrier Substrate 7014) is transferred to the acceptor wafer 808 (Top metallization) includes metal plug strips 8124 that become bond pads for connection lines between circuits formed on the cut-out layer and the underlying circuit layer 808 .

如圖85D所示,如前文所述,接下來可在表面7016上將載子基板7014釋放。 As shown in FIG. 85D , the carrier substrate 7014 may then be released on the surface 7016 as previously described.

如圖85E所示,黏結在一起之受主晶圓808和HKMG電晶體矽層7001現在已準備妥當,可採取先進之技術使“後柵極”電晶體之成形了,並將受主晶圓外殼808透過層與通孔7040連接起來。將頂部柵極透過柵極接點7034與底部柵極、金屬線8536和接點8522連接起來,並透過層接點8512與施主晶圓層連接起來,從而使上層電晶體8550擁有背柵極。透過將金屬線8516與回饋偏壓電路連接起來使上層電晶體8552出現反向偏置。回饋偏壓電路可能出現在上層電晶體級或在外殼808中。 As shown in Figure 85E, the bonded acceptor wafer 808 and HKMG transistor silicon layer 7001 are now ready for advanced techniques to form the "gate-last" transistors and place the acceptor wafer The shell 808 is connected to the via 7040 through the layer. The top gate is connected to the bottom gate, metal line 8536 and contact 8522 through gate contact 7034 and to the donor wafer layer through layer contact 8512 so that the upper transistor 8550 has a back gate. The upper transistor 8552 is reverse biased by connecting the metal line 8516 to the back bias circuit. Back bias circuitry may be present at the upper transistor level or within housing 808 .

本發明克服了在形成與下方層808對齊之平面電晶體過程中遇到之難題,詳情請見圖71至圖79以及圖30至圖33。如前文所述,參考圖70A至70H可知,電晶體成型過程中可採取一般之流程。在其中一個案例中,可預先對施主晶圓3000進行加工,這樣一來,透過包含並聯之交替行,並非單單建設一種電晶體類型,而是兩種類型。交替行等於裸晶片寬度加上施主晶圓與受主晶圓未對準線之間之最大長度。此外,如圖30所示,在“n”型3004和“p”型3006電晶體成型之第一階段,也可將交替行做成與晶圓一樣長,圖30還顯示了四個基本方向之指示符3040,圖71至圖78藉由這些指示符進行解釋。如放大投影圖3002所 示,n型行3004之寬度是Wn,p型行3006之寬度是Wp,二者之和W 3008等於之重複圖形之寬度。行自東向西重複排列,而交替圖形穿過晶圓從北向南重複排列。Wn和Wp可設定為相應電晶體之最小寬度加上其在選定之工藝節點中之隔離寬度。晶圓3000還具有一條對準標誌3020,與作為n 3004和p 3006行之施主晶圓位於同一層。因此,為了將其他圖像繪製和加工過程與上述n 3004和n 3006行相對齊,可稍後再使用晶圓3000。 The present invention overcomes the difficulties encountered in forming planar transistors aligned with the underlying layer 808, see FIGS. 71-79 and 30-33 for details. As mentioned above, with reference to FIGS. 70A to 70H , it can be known that a general process can be adopted in the transistor forming process. In one case, the donor wafer 3000 can be pre-processed so that not just one transistor type is built, but two types, by including alternating rows in parallel. The alternating rows are equal to the width of the die plus the maximum length between the misalignment of the donor and acceptor wafers. In addition, as shown in Figure 30, in the first stage of "n" type 3004 and "p" type 3006 transistor formation, alternating rows can also be made as long as the wafer, and Figure 30 also shows the four basic directions The indicator 3040 of Figure 71 to Figure 78 is explained by these indicators. As shown in the enlarged projection diagram 3002 As shown, the width of the n-type row 3004 is Wn, the width of the p-type row 3006 is Wp, and the sum of the two, W 3008, is equal to the width of the repeated pattern. Rows repeat from east to west, while alternating patterns repeat from north to south across the wafer. Wn and Wp can be set to the minimum width of the corresponding transistor plus its isolation width in the selected process node. Wafer 3000 also has a strip of alignment marks 3020 on the same layer as the donor wafer as rows n 3004 and p 3006 . Therefore, wafer 3000 may be reused later in order to align other image rendering and processing with rows n 3004 and n 3006 described above.

如圖71所示,p型電晶體行之寬度重複Wp 7106可包含兩個電晶體絕緣區7110,每個寬度為2F;加上一個電晶體源極7112,寬度2.5F;一個PMOS柵極7113,寬度F和一個電晶體汲極7114,寬度2.5F。總寬度Wp可能等於10F,其中F是2×λ,最小設定規則。n型電晶體行之寬度重複Wn 7104可包含兩個電晶體絕緣區7110,每個寬度為2F;加上一個電晶體源極7116,寬度2.5F;一個NMOS柵極7117,寬度F和一個電晶體汲極7118,寬度2.5F。總寬度Wn可能等於10F,總重複寬度W 7108等於20F。 As shown in Figure 71, the width repetition Wp 7106 of the p-type transistor row may include two transistor isolation regions 7110, each with a width of 2F; plus a transistor source 7112, with a width of 2.5F; and a PMOS gate 7113 , width F and a transistor drain 7114, width 2.5F. The total width Wp may be equal to 10F, where F is 2 x λ, the minimum setting rule. The n-type transistor row width repeat Wn 7104 may comprise two transistor isolation regions 7110, each 2F wide; plus a transistor source 7116, 2.5F wide; an NMOS gate 7117, wide F and a transistor Crystal drain 7118, width 2.5F. The total width Wn may be equal to 10F, and the total repeat width W 7108 is equal to 20F.

如前文所述並參考圖70E,現在已經變薄之施主晶圓層3000L和第一階段電晶體成型預加工之HKMG矽層7001(帶隨附之載子基板7014)可置於圖31所示之受主晶圓3100之頂部。當前之技術發展平可以實現完美之黏結步驟之角對準,但要達到比1宾m還完美之位置對準卻非常困難。圖31顯示了受主晶圓3100(帶有相應之對準標誌3120)以及施主晶圓(帶有對準標誌3020)之切出層 3000L。東西方向之未對準線是DX 3124,南北方向之未對準線是DY 3122。每個晶圓上只能在某些位置設定這些對準標誌3120和3020,可設定在各個步驟場中、各個裸晶片中或各個重複圖形W中。如前文所述並參考圖32、33A和33B,對齊方法包含殘餘Rdy 3202和黏結區插接條33A04和33B04,可用于提高轉移施主晶圓層與受主晶圓之間電氣連接之密度和依賴性。 As previously described and with reference to FIG. 70E , the now thinned donor wafer layer 3000L and first stage transistor forming pre-processed HKMG silicon layer 7001 (with accompanying carrier substrate 7014 ) can be placed as shown in FIG. 31 The top of the acceptor wafer 3100. The current technological development can achieve perfect corner alignment of bonding steps, but it is very difficult to achieve perfect position alignment of more than 1 mm. Figure 31 shows cut out layers of a recipient wafer 3100 (with corresponding alignment marks 3120) and a donor wafer (with alignment marks 3020) 3000L. The east-west misalignment is DX 3124, and the north-south misalignment is DY 3122. These alignment marks 3120 and 3020 can only be set at certain positions on each wafer, and can be set in each step field, each bare wafer or each repeated pattern W. As previously described and with reference to Figures 32, 33A, and 33B, the alignment method, including residual Rdy 3202 and bond pad strips 33A04 and 33B04, can be used to increase the density and dependence of the electrical connection between the transferred donor wafer layer and the acceptor wafer. sex.

圖72A至72F展示了施主晶圓佈局(帶有與圖71所示之源極和汲極並聯之柵極)之低溫層切流程。 Figures 72A to 72F illustrate the low temperature layer dicing flow for a donor wafer layout with gates in parallel to the source and drain shown in Figure 71 .

圖72A展示了電晶體成型第一階段層切之後、薄薄的單晶預加工施主層被層切到受主晶圓並與其黏結之後以及圖70F(含)之前篇章中所述之將黏結結構從載子基板上移除之後晶圓之俯視圖和剖視圖。 Figure 72A shows the thin single crystal prefabricated donor layer sliced and bonded to the acceptor wafer after the first stage of transistor formation after layer dicing and the bonded structure described in the section preceding and including Figure 70F Top and cross-sectional views of the wafer after removal from the carrier substrate.

對層間電介質(ILD)7008進行化學-機械打磨,以裸露虛擬多晶矽之頂部;並如圖72B所示對層-層通孔7040進行蝕刻、金屬填充並採取化學-機械打磨之方法將其磨平。 Perform chemical-mechanical polishing on the interlayer dielectric (ILD) 7008 to expose the top of the dummy polysilicon; and etch, metal fill, and smooth the layer-to-layer via 7040 as shown in FIG. 72B .

如圖72C所示,可透過形成隔離區7202將預成型電晶體較長之行蝕刻至所需之長度或片段。可進行低溫氧化,已修復電晶體邊緣之受損部分;可向區域7202填充電介質,並採取化學-機械打磨之方法將其磨平,以將電電晶體段隔離開。 Longer rows of preformed transistors can be etched to desired lengths or segments by forming isolation regions 7202, as shown in FIG. 72C. Low temperature oxidation can be performed to repair the damaged portion of the transistor edge; the region 7202 can be filled with dielectric and smoothed by chemical-mechanical polishing to isolate the transistor segments.

或者,可選擇性地打開或填充PMOS和NMOS之區域7202,以全面改良電晶體溝槽或提高其張應力,有利於提 高載子遷移率。 Alternatively, the region 7202 of PMOS and NMOS can be selectively opened or filled to improve the overall transistor trench or increase its tensile stress, which is beneficial to improve High carrier mobility.

現在可對多晶矽7004和氧化物7005虛擬柵極進行蝕刻,以便在隔離區7202邊界和高-k電介質7026、PMOS金屬柵極7028和NMOS金屬柵極7030之普通取代柵極澱積提供一些柵極覆蓋層。此外,可進行鋁超填7032。如圖72D所示,可對鋁7032進行化學-機械打磨,使用於柵極輪廓勾畫之表面平面化。 The polysilicon 7004 and oxide 7005 dummy gates can now be etched to provide some gates at the boundaries of the isolation region 7202 and the normal replacement gate deposition of the high-k dielectric 7026, PMOS metal gate 7028 and NMOS metal gate 7030 overlay. In addition, aluminum overfill 7032 is available. As shown in Figure 72D, aluminum 7032 can be chemical-mechanical polished to planarize the surface for gate profiling.

如圖72E所示,可繪製取代柵極7215之圖形並進行蝕刻,並提供柵極接點接合焊盤7218。 As shown in FIG. 72E, the replacement gate 7215 can be patterned and etched, and a gate contact bonding pad 7218 can be provided.

層間電介質可能會澱積,並採取化學-機械打磨之方法使其平面化。如圖72F所示,可進行普通接點成型和金屬化步驟,以製造柵極7220、源極7222、汲極7224和層間通孔7240連接線。 An interlayer dielectric may be deposited and planarized by chemical-mechanical polishing. As shown in FIG. 72F, common contact forming and metallization steps may be performed to create gate 7220, source 7222, drain 7224, and interlayer via 7240 connection lines.

在另外一個案例中,可在電晶體成型之第一階段對施主晶圓7000進行預加工,以建設n和p型虛擬晶圓,包含兩個方向上之重複圖形。圖73、74和75還顯示了四個基本方向之指示符3040,可藉由這些指示符進行解釋。如圖73中之放大投影圖7302所示,寬度Wy 7304與重複圖形行一致。重複圖形行等於自東向西之受主裸晶片之寬度加上施主晶圓與受主晶圓未對準線之間之最大長度;或者等於施主晶圓自東向西之長度;重複圖形穿過晶圓從北向南重複排列。與此類似,Wx 7306所示與重複圖形行一致。重複圖形行等於自北向南之受主裸晶片之寬度加上施主晶圓與受主晶圓未對準線之間之最大長度;或者等於施主晶圓自 北向南之長度;重複圖形穿過晶圓從東向西重複排列。晶圓7000還具有一條對準標誌3020,與作為Wx 7306和Wy 7304衝突圖形行之施主晶圓位於同一層。因此,為了將其他之圖像繪製和加工過程與上述行相對齊,可稍後再使用對準標誌3020。 In another example, the donor wafer 7000 can be pre-processed in the first stage of transistor formation to create n- and p-type dummy wafers, including repeating patterns in both directions. Figures 73, 74 and 75 also show indicators 3040 of the four cardinal directions by which interpretation can be made. As shown in the enlarged projection view 7302 in FIG. 73, the width Wy 7304 coincides with the repeating pattern row. The repeating pattern row is equal to the width of the acceptor die from east to west plus the maximum length between the misalignment line of the donor wafer and the acceptor wafer; or equal to the length of the donor wafer from east to west; repeat pattern across the die The circles are repeated from north to south. Similarly, Wx 7306 is shown consistent with repeating graphic lines. The repeat pattern row is equal to the width of the acceptor die from north to south plus the maximum length between the donor wafer and the acceptor wafer misalignment line; Length from north to south; repeating pattern repeats across the wafer from east to west. Wafer 7000 also has a strip of alignment marks 3020 on the same layer as the donor wafer as the Wx 7306 and Wy 7304 conflicting pattern lines. Therefore, alignment marks 3020 may be used later in order to align other image rendering and processing with the above-mentioned rows.

如前文所述並參考圖70E,現在已經變薄之施主晶圓層3000L和第一階段電晶體成型預加工之HKMG矽層7001(帶隨附之載子基板7014)可置於圖31所示之受主晶圓3100之頂部。當前之技術發展平可以實現完美之黏結步驟之角對準,但要達到比1□m還完美之位置對準卻非常困難。圖31顯示了受主晶圓3100(帶有相應之對準標誌3120)以及施主晶圓(帶有對準標誌3020)之切出層3000L。東西方向之未對準線是DX 3124,南北方向之未對準線是DY 3122。每個晶圓上只能在某些位置設定這些對準標誌,可設定在各個步驟場中、各個裸晶片中或各個重複圖形W中。 As previously described and with reference to FIG. 70E , the now thinned donor wafer layer 3000L and first stage transistor forming pre-processed HKMG silicon layer 7001 (with accompanying carrier substrate 7014 ) can be placed as shown in FIG. 31 The top of the acceptor wafer 3100. The current technological development can achieve perfect corner alignment of the bonding step, but it is very difficult to achieve a perfect position alignment than 1□m. FIG. 31 shows a cut-out layer 3000L of a recipient wafer 3100 (with corresponding alignment marks 3120 ) and a donor wafer (with alignment marks 3020 ). The east-west misalignment is DX 3124, and the north-south misalignment is DY 3122. These alignment marks can only be set at certain positions on each wafer, and can be set in each step field, each bare wafer, or each repeated pattern W.

如圖74所示,擬議之結構包含並聯電晶體能帶交替行之南北方向和東西方向之重複圖形。擬議之結構之優點在於電晶體之加工工藝類似於受主晶圓之加工工藝,從而大大降低3D集成組件之研發成本。因此,有效對齊之不確定性可降低到Wy 7304(南北方向)和Wx 7306(東西方向)。相應地,可計算出在南北方向上之對齊殘餘Rdy 3202(DY模量Wy之餘數,0<=Rdy<Wy)。要與最近之Wy準確對齊,一定要與下方之Rdy 3202偏移之對準標誌3120 在南北方向上對齊。同樣地,東西方向上之有效對齊之不確定性可降低到Wx 7306。可採用與Rdy3202類似之方法計算東西方向上之對齊殘餘Rdx 3708(DX模量Wx之餘數,0<=Rdx<Wx)。同樣,要與最近之Wx準確對齊,一定要與下方之Rdx 7308偏移之對準標誌3120在東西方向上對齊。 As shown in Figure 74, the proposed structure consists of a repeating pattern of alternating rows of energy bands in parallel transistors in north-south and east-west directions. The advantage of the proposed structure is that the processing technology of the transistor is similar to the processing technology of the acceptor wafer, thereby greatly reducing the development cost of 3D integrated components. Therefore, the uncertainty in the effective alignment can be reduced to Wy 7304 (north-south direction) and Wx 7306 (east-east direction). Correspondingly, the alignment residual Rdy 3202 (the remainder of the DY modulus Wy, 0<=Rdy<Wy) in the north-south direction can be calculated. For accurate alignment with the nearest Wy, the alignment mark 3120 must be offset from the lower Rdy 3202 Align in north-south direction. Likewise, the uncertainty of effective alignment in the east-west direction can be reduced to Wx 7306. The alignment residual Rdx 3708 (the remainder of the DX modulus Wx, 0<=Rdx<Wx) in the east-west direction can be calculated using a method similar to Rdy3202. Likewise, for accurate alignment with the nearest Wx, it must be aligned with the alignment mark 3120 offset from the lower Rdx 7308 in the east-west direction.

按照本流程要加工之各個晶圓應至少擁有一個特定之Rdx 7308和Rdy 3202,它們都取決於實際之未對準線DX 3124和DY 3122以及Wx和Wy。不過,用於繪製各種圖形之掩膜需要預先進行設定、製作;所有晶圓(用於同一終端設備之晶圓)都要使用相同之掩膜,無需考量實際之晶圓與晶圓之間之未對準線情況。如圖75所示,為了確保施主晶圓7001上之結構與下方之施主晶圓808更好地連接,下方之晶圓808應設定有矩形接合焊盤7504,沿長度Wy 7304南北方向延伸,外加滿足通孔設定規則之延伸段;此外,該接合焊盤還應沿長度Wx 7306東西方向延伸,外加滿足通孔設定規則之延伸段。滿足通孔設定規則之接合焊盤矩形延伸段可包含補償因晶圓與晶圓之間之黏結而產生之角度失准,還包含未補償之施主晶圓彎曲和翹曲。步進電機重疊演算法並不補償角度失准。接合焊盤7504可成為受主晶圓808之一部分,因此與其對準標誌3120對齊。通孔7502為下降方向,是施主晶圓7001圖形之一部分。它分別透過偏移Rdx 7308和Rdy 3202與下方之對準標誌3120,使之與接合焊盤7504連接起來。 Each wafer to be processed according to this flow should have at least one specific Rdx 7308 and Rdy 3202, both of which depend on the actual misalignment lines DX 3124 and DY 3122 and Wx and Wy. However, the masks used to draw various graphics need to be set and fabricated in advance; all wafers (wafers used for the same terminal equipment) must use the same mask, regardless of the actual wafer-to-wafer Misalignment condition. As shown in FIG. 75 , in order to ensure that the structures on the donor wafer 7001 are better connected to the donor wafer 808 below, the lower wafer 808 should be provided with rectangular bonding pads 7504 extending along the length Wy 7304 in the north-south direction, plus The extension that satisfies the via design rules; in addition, the bond pad should also extend along the length Wx 7306 in the east-west direction, plus the extension that satisfies the via design rules. Rectangular extensions of bond pads that satisfy via-setting rules can include compensation for angular misalignment due to wafer-to-wafer bonding, as well as uncompensated donor wafer bow and warpage. The stepper motor overlap algorithm does not compensate for angular misalignment. The bond pads 7504 may become part of the acceptor wafer 808 and thus align with its alignment marks 3120 . Vias 7502 are in the descending direction and are part of the donor wafer 7001 pattern. It connects to the bond pad 7504 by offsetting Rdx 7308 and Rdy 3202 respectively from the alignment mark 3120 below.

如圖77所示,在另外一個案例中,受主基板808中之矩形接合焊盤7504可替代成受主晶圓中之接合插接條77A04和受主層中之垂直接合插接條77A06。通孔77A02為下降方向,是施主晶圓7001圖形之一部分。它分別透過偏移Rdx 7308和Rdy 3202與下方之對準標誌3120,使之與接合焊盤77A06連接起來。 As shown in FIG. 77 , in another example, the rectangular bonding pads 7504 in the acceptor substrate 808 can be replaced by bonding strips 77A04 in the acceptor wafer and vertical bonding strips 77A06 in the acceptor layer. The via hole 77A02 is in the descending direction and is part of the pattern of the donor wafer 7001 . It connects to bond pad 77A06 by offsetting Rdx 7308 and Rdy 3202 respectively from alignment mark 3120 below.

圖76分別從南北方向和東西方向展示了重複圖形。這個重複圖形可能是電晶體之重複圖形,其中每個電晶體都具有柵極7622,沿東西軸上形成電晶體能帶。南北方向之重複圖形可包含並聯之電晶體能帶,其中每個電晶體具有有源區7612或7614。電晶體可對其柵極7622進行充分定義。因此,重複Wx 7306可使結構可在東西方向重複排列。結構在南北方向上可重複各個Wy 7304。層與層之間之通孔溝槽7618之寬度Wv 7602為5F,n型電晶體行之寬度Wn 7604可包含兩個電晶體隔離區7610(寬度3F)、共用隔離區7616(寬度1F)以及電晶體有源區7614(寬度2.5F)。p型電晶體行之寬度Wp 7606可包含兩個電晶體隔離區7610(寬度3F)、共用隔離區7616(寬度1F)以及電晶體有源區7612(寬度2.5F)。總寬度Wy可能等於18F,是Wv+Wn+Wp之和,其中F是2×λ,最小設定規則。柵極7622之寬度為F,與東西方向上各個柵極之間之間隔為4F。東西重複寬度Wx 7306為5F。透過將中間柵極偏置至適當之斷開狀態,東西方向上相鄰電晶體之間可實現互相絕緣,例如用於NMOS之接地柵極和用於PMOS之Vdd柵 極。 Figure 76 shows repeating patterns from north-south and east-west directions, respectively. This repeating pattern may be a repeating pattern of transistors each having a gate 7622 forming the transistor energy bands along the east-west axis. The repeating pattern in the north-south direction can include transistor energy bands connected in parallel, where each transistor has an active region 7612 or 7614 . A transistor may have its gate 7622 fully defined. Thus, repeating Wx 7306 allows the structure to repeat in the east-west direction. The structure repeats each Wy 7304 in a north-south direction. The width Wv 7602 of the via trench 7618 between layers is 5F, and the width Wn 7604 of the n-type transistor row can include two transistor isolation regions 7610 (width 3F), a common isolation region 7616 (width 1F) and Transistor active area 7614 (width 2.5F). P-type transistor row width Wp 7606 may include two transistor isolation regions 7610 (width 3F), common isolation region 7616 (width 1F), and transistor active region 7612 (width 2.5F). The total width Wy may be equal to 18F, which is the sum of Wv+Wn+Wp, where F is 2×λ, the minimum setting rule. The width of the grid 7622 is F, and the distance between each grid in the east-west direction is 4F. The east-west repeat width Wx 7306 is 5F. By biasing the middle gate to an appropriate off state, the adjacent transistors in the east-west direction can be isolated from each other, such as the ground gate for NMOS and the Vdd gate for PMOS pole.

如前文所述並參考圖70E,現在已經變薄之施主晶圓層3000L和第一階段電晶體成型預加工之HKMG矽層7001(帶隨附之載子基板7014)可置於圖31所示之受主晶圓3100之頂部。如前文所述,可對DX 3124和DY 3122未對準線以及相關之Rdx 7308和Rdy 3202進行計算。如圖77A所示,為了確保施主晶圓7001上之結構與下方之晶圓808更好地連接,下方之晶圓808應設定有接合焊盤77A04,沿長度Wy 7304南北方向延伸,外加滿足通孔設定規則之延伸段。滿足通孔設定規則之接合焊盤延伸段可包含補償因晶圓與晶圓之間之黏結而產生之角度失准,還包含未補償之施主晶圓彎曲和翹曲。步進電機重疊演算法並不補償角度失准。插接條77A04可成為晶圓808之一部分,因此與其對準標誌3120對齊。接合插接條77A06可成為施主晶圓層之一部分,其方向與電晶體能帶平行,因此也是東西方向。接合插接條77A06可與帶有Rdx和Rdy偏置之主晶圓對準標誌3120對齊(也就是說,相當於與施主晶圓對準標誌3020對齊)。連接這兩個接合插接條77A04和77A06之通孔77A02可成為頂層7001圖形之一部分。通孔77A02可與東西方向之主晶圓808對準標誌對齊,也與南北方向之主晶圓對準標誌3120(帶Rdy偏置)對齊。 As previously described and with reference to FIG. 70E , the now thinned donor wafer layer 3000L and first stage transistor forming pre-processed HKMG silicon layer 7001 (with accompanying carrier substrate 7014 ) can be placed as shown in FIG. 31 The top of the acceptor wafer 3100. DX 3124 and DY 3122 misalignment and associated Rdx 7308 and Rdy 3202 can be calculated as previously described. As shown in FIG. 77A , in order to ensure that the structure on the donor wafer 7001 is better connected to the wafer 808 below, the wafer 808 below should be set with bonding pads 77A04 extending along the length Wy 7304 in the north-south direction, and additionally meet the requirements of the pass An extension of the hole setting rule. Bond pad extensions that meet via-setting rules can include compensation for angular misalignment due to wafer-to-wafer bonding, as well as uncompensated donor wafer bow and warpage. The stepper motor overlap algorithm does not compensate for angular misalignment. The strap 77A04 may become part of the wafer 808 and thus be aligned with its alignment mark 3120 . Bonding strips 77A06 can be part of the donor wafer layer and are oriented parallel to the transistor energy bands and thus also in an east-west direction. Bonding strip 77A06 can be aligned with master wafer alignment mark 3120 with Rdx and Rdy offsets (ie, equivalently aligned with donor wafer alignment mark 3020 ). The via 77A02 connecting the two bonded strips 77A04 and 77A06 can be part of the top layer 7001 pattern. The vias 77A02 can be aligned with the main wafer alignment marks 3120 (with Rdy offset) in the north-south direction.

或者,如圖78A所示,圖76中描述之柵極之連續擴散區之重複圖形可帶有放大之Wv 7802,用以放大接合插接條77A06之行。層與層之間之通孔溝槽7618之寬度Wv 7802等於10F,而南北方向圖形重複之總寬度Wy 7804等於23F。 Alternatively, as shown in FIG. 78A, the repeating pattern of continuous diffusion regions of the gate depicted in FIG. 76 may have enlarged Wv 7802 to enlarge the row of bonded bars 77A06. Width Wv of via trench 7618 between layers 7802 is equal to 10F, and the total width Wy 7804 of pattern repeats in the north-south direction is equal to 23F.

如圖77B所示,在另外一個案例中,柵極7622B可在東西方向重複,與附加之柵側壁重複7810配合。這個電晶體之重複圖形沿東西軸上形成電晶體能帶,其中每個電晶體都具有柵極7622B。南北方向之重複圖形可包含並聯之電晶體能帶,其中每個電晶體具有有源區7612或7614。東西方向圖形重複寬度Wx 7806為14F,施主晶圓接合插接條77A06之長度可設定為長度Wx 7806加上前文所述之滿足設定規則所必須之延伸部分之長度。施主晶圓接合插接條77A06之方向可與電晶體能帶平行,因此也是東西方向。 As shown in FIG. 77B , in another example, gate 7622B may repeat in an east-west direction, mating with additional gate sidewall repeat 7810 . This repeating pattern of transistors forms the energy bands of the transistors along the east-west axis, where each transistor has a gate 7622B. The repeating pattern in the north-south direction can include transistor energy bands connected in parallel, where each transistor has an active region 7612 or 7614 . The pattern repeat width Wx 7806 in the east-west direction is 14F, and the length of the donor wafer bonding strip 77A06 can be set as the length Wx 7806 plus the length of the extension necessary to meet the setting rules mentioned above. The orientation of the donor wafer bonding strips 77A06 may be parallel to the transistor energy bands, and thus is also east-west.

圖78C展示了帶重複電晶體晶片結構之柵極陣列部分之截面。該晶片類似於圖78B中之一個晶片,其中N電晶體柵極與P電晶體對應之柵極連接起來。圖78C展示了基本邏輯晶片之注入情況:Inv、NAND、NOR和MUX。 Figure 78C shows a cross-section of a portion of a gate array with a repeating transistor wafer structure. The die is similar to the one in Fig. 78B, where the gates of the N transistors are connected to the corresponding gates of the P transistors. Figure 78C shows the implantation of basic logic chips: Inv, NAND, NOR and MUX.

或者,如圖79所示,要增加施主晶圓層與層之間通孔中通層孔連接線之密度,將施主晶圓接合插接條77A06之長度設定為低於Wx 7306,方法為增加外殼77A04中接合插接條寬度中之7900並偏置通層孔77A02。如前文所述,將接合插接條77A04和77A06對齊。如前文所述,通孔77A02與南北方向之主晶圓對準標誌3120(帶Rdy偏置)對齊,在東西方向上與受主晶圓808之對準標誌3120對齊,稍微偏向東方。偏置尺寸等於施主晶圓接合插接條77A06之縮減量。 Or, as shown in FIG. 79, to increase the density of the through-hole connection lines in the through-holes between the layers of the donor wafer, set the length of the donor wafer bonding strip 77A06 to be lower than Wx 7306 by increasing Engage 7900 of the width of the strip in housing 77A04 and offset via hole 77A02. Align splice strips 77A04 and 77A06 as previously described. Vias 77A02 are aligned with master wafer alignment marks 3120 (with Rdy offset) in the north-south direction, and aligned with the alignment marks 3120 of acceptor wafer 808 in the east-west direction, slightly offset to the east, as previously described. The offset dimension is equal to the reduction of the donor wafer bonding strap 77A06.

在另外一個案例中,可使用前文所述之技術在施主晶圓和切出層上準備非重複圖形組件結構之功能塊。這個非重複圖形組件結構之施主晶圓可能是DRAM之存儲塊,或者輸入-輸出電路之功能塊,或者其他之功能塊。可使用一般之連接結構8002將施主晶圓非重複圖形組件結構8004連接到受主晶圓-外殼晶圓裸晶片8000上。 In another example, functional blocks of non-repeating patterned device structures can be prepared on the donor wafer and the diced layer using the techniques described above. The donor wafer of this non-repeating pattern device structure may be a memory block of a DRAM, or a functional block of an input-output circuit, or other functional blocks. The donor wafer non-repeating pattern device structure 8004 can be connected to the acceptor wafer-housing wafer bare die 8000 using conventional bonding structures 8002 .

外殼808晶圓裸晶片8000見圖80。連接結構8002可置於非重複結構8004之內部或外部。如前文所述,在層切過程中,Mx 8006等於施主晶圓至受主晶圓8000未對準線之間之東西方向上之最大距離加上滿足設定規則所必須之延伸部分;My 8008等於施主晶圓至受主晶圓未對準線之間之南北方向上之最大距離加上滿足設定規則所必須之延伸部分。Mx 8006和My 8008可包含因晶圓與晶圓之間之黏結而產生之增加之角度失准,還包含未補償之施主晶圓彎曲和翹曲。步進電機重疊演算法並不補償角度失准。受主晶圓南北方向上之接合插接條8010之長度等於My 8008,與受主晶圓對準標誌3120對齊。施主晶圓東西方向上之接合插接條8011之長度等於Mx 8006,與施主晶圓對準標誌3020對齊。連接它們之通層孔8012在東西方向上與受主晶圓對準標誌3120對齊,在南北方向上與施主晶圓對準標誌3020對齊。為便於解釋,施主晶圓較低之金屬接合插接條為東西方向,施主晶圓較高之金屬接合插接條為南北方向。接合插接條之方向可互換。 The shell 808 wafer bare chip 8000 is shown in FIG. 80 . The connection structure 8002 can be placed inside or outside the non-repeating structure 8004 . As mentioned above, during the layer cutting process, Mx 8006 is equal to the maximum distance in the east-west direction between the donor wafer and the acceptor wafer 8000 misalignment plus the extension necessary to meet the set rules; My 8008 is equal to The maximum distance in the north-south direction between the donor wafer and the acceptor wafer misalignment plus the extension necessary to satisfy the set rules. Mx 8006 and My 8008 may include increased angular misalignment due to wafer-to-wafer bonding, as well as uncompensated donor wafer bow and warp. The stepper motor overlap algorithm does not compensate for angular misalignment. The length of the bonding strip 8010 in the north-south direction of the acceptor wafer is equal to My 8008, aligned with the acceptor wafer alignment marks 3120. The length of the bonding strip 8011 in the east-west direction of the donor wafer is equal to Mx 8006 , aligned with the donor wafer alignment marks 3020 . The vias 8012 connecting them are aligned with the acceptor wafer alignment marks 3120 in the east-west direction and with the donor wafer alignment marks 3020 in the north-south direction. For ease of explanation, the lower metal bonding bars of the donor wafer are oriented east-west, and the higher metal bonding bars of the donor wafer are oriented north-south. The direction of engaging the strips is interchangeable.

施主晶圓可包含重複組件結構組件之部件(如圖76和 78B所示)以及非重複之組件結構組件。如前文所述,這兩個組件中一個是重複組件,另外一個是非重複組件,可單獨繪製圖形。原因在於非重複組件之圖形可與施主晶圓對準標誌3020對齊,而重複組件之圖形可與受主晶圓對準標誌3120(帶Rdx和Rdy偏置)對齊。因此,圖80中所示之一般連接結構可用於這兩個組件之間之連接。東西方向之接合插接條8011可與施主晶圓對準標誌3020和非重複組件對齊,而南北方向之接合插接條8010可與受主晶圓對準標誌3120(帶偏置)和重複組件圖形對齊。連接這些插接條之通孔8012需要在南北方向上與施主晶圓對準標誌3020對齊,在東西方向上與受主晶圓對準標誌3120(帶偏置)對齊。 The donor wafer can contain components of repeating assembly structures (as shown in Figure 76 and 78B) and non-repeating component structure components. As mentioned earlier, one of these two components is a repeating component, and the other is a non-repeating component that can draw graphics independently. The reason is that the pattern of non-repeating components can be aligned with the donor wafer alignment marks 3020, while the pattern of repeating components can be aligned with the acceptor wafer alignment marks 3120 (with Rdx and Rdy offsets). Therefore, the general connection structure shown in Fig. 80 can be used for the connection between these two components. East-west bonded strips 8011 can be aligned with donor wafer alignment marks 3020 and non-repeating components, while north-south bonded bars 8010 can be aligned with acceptor wafer alignment marks 3120 (with offset) and repeated components Graphical alignment. The vias 8012 connecting these straps need to be aligned with the donor wafer alignment marks 3020 in the north-south direction and the acceptor wafer alignment marks 3120 (with offset) in the east-west direction.

上述流程,不管是單一型電晶體施主晶圓還是互補型電晶體施主晶圓,在建設多層3D單塊集成系統時都可以重複多次。這些流程還可以以單塊3D之方式提供多種組件技術。舉例來說,組件I/O或類比電路(比如鎖相回路-PLL)、時鐘分佈或射頻電路可透過層切之方法集成到CMOS邏輯電路中;或者將雙極電路集成到CMOS邏輯電路中;或者將模擬組件集成到邏輯電路中,等等。先前之技術還提供了建設3D組件之其他技術。最常用之技術有,使用薄膜電晶體(TFT)建設單塊3D組件;或堆疊預製之晶圓,接著使用矽通孔(TSV)將預製之晶圓連接起來。由於3D層相對較寬之一側大約有60微米,連接它們之矽通孔之密度也相對較低,TFT方法取決於薄膜電晶體之性 能,而堆疊方法取決於TSV通孔之相對較大之一側之尺寸(大約等於數微米)。從本發明中以層切法建設3D IC之很多案例中可以看出,切出層通常是厚度不足0.4微米之薄層。從本發明之一些案例可以看出,帶切出層之3D IC與先前採用TSV技術建設之3D IC形成鮮明之比對。採用TSV技術時,TSV連接之層之厚度均超過5微米,在很多情況下要超過50微米。 The above process, whether it is a single type transistor donor wafer or a complementary type transistor donor wafer, can be repeated many times when building a multi-layer 3D monolithic integrated system. These processes can also provide multiple component technologies in a single 3D manner. For example, component I/O or analog circuits (such as phase-locked loop-PLL), clock distribution or radio frequency circuits can be integrated into CMOS logic circuits through the method of layer cutting; or bipolar circuits can be integrated into CMOS logic circuits; Or integrate analog components into logic circuits, etc. Prior art also provides other techniques for building 3D components. The most commonly used techniques are to use thin film transistors (TFT) to build a single 3D device; or to stack prefabricated wafers and then use through-silicon vias (TSVs) to connect the prefabricated wafers. Since the relatively wide side of the 3D layer is about 60 microns and the density of TSVs connecting them is relatively low, the TFT approach depends on the properties of thin film transistors. can, and the stacking method depends on the size of the relatively large side of the TSV via (on the order of a few microns). It can be seen from many cases of building 3D ICs by layer cutting in the present invention that the cut layer is usually a thin layer with a thickness less than 0.4 microns. From some cases of the present invention, it can be seen that the 3D IC with cut-out layer is in sharp contrast with the previous 3D IC constructed using TSV technology. When using TSV technology, the thickness of the layer connected by TSV exceeds 5 microns, and in many cases exceeds 50 microns.

圖20至圖35、圖40、圖54至圖61以及圖65至圖94中展示之其他工藝流程提供了真實之單塊3D積體電路。該流程可使用單晶矽電晶體層、互相對齊之層以及僅受到步進電機性能限制之層。單晶矽電晶體層應當能夠將上部電晶體和下方電路對齊。同樣,上部電晶體和下方電路之間之接點間隔應當與下方之層之接點間隔一致。而在使用最新之堆疊方法時,堆疊晶圓只有數微米厚。使用圖20至圖35、圖40、圖40至圖61以及圖65至圖94中提到之替代流程時,層非常薄,通常只有100納米;而最近之工件可證明層之厚度只有大約20納米。 The other process flows shown in FIGS. 20-35 , 40 , 54-61 , and 65-94 provide true monolithic 3D integrated circuits. The process can use single-crystal silicon transistor layers, layers aligned with each other, and layers limited only by the performance of stepper motors. The monocrystalline silicon transistor layer should be able to align the upper transistors with the underlying circuitry. Likewise, the contact spacing between the upper transistor and the underlying circuitry should match the contact spacing of the underlying layer. With the latest stacking methods, the stacked wafers are only a few microns thick. When using the alternative processes mentioned in Figures 20-35, 40, 40-61, and 65-94, the layers are very thin, typically only 100 nanometers; and recent workpieces have demonstrated layer thicknesses of only about 20 Nano.

因此,展示之替代流程可用于真正之單塊3D組件生產。這個單塊3D技術可允許全密度集成,以更嚴格之特徵測量,可與半導體行業同步。 Therefore, the alternative process shown can be used for true monolithic 3D component production. This monolithic 3D technology allows for full density integration with tighter feature measurements that can keep pace with the semiconductor industry.

另外,真正單塊3D組件可在有效之立體空間中生成各種子電路結構,其性能要優於同等2D結構。下文將舉例說明如何使用真正單塊3D方式建設3D晶片程式庫。 In addition, a true monolithic 3D device can generate various subcircuit structures in an effective three-dimensional space, and its performance is better than that of the equivalent 2D structure. The following will illustrate how to use the true monolithic 3D method to build a 3D chip library.

圖42展示了典型的2D CMOS倒相器佈局圖和示意圖, 其中NMOS電晶體4202和PMOS電晶體4204並排放在一起,處於摻雜程度不同之井中。NMOS源極4206採取一般方式接地,NMOS和PMOS汲極4208透過電力方式連接在一起,NMOS和PMOS柵極4210透過電力方式連接在一起,PMOS 4207源極連接到+Vdd上。下文中所述之3D結構將利用這些第三維之連接線。 Figure 42 shows a typical 2D CMOS inverter layout and schematic diagram, Wherein the NMOS transistor 4202 and the PMOS transistor 4204 are arranged side by side, in wells with different doping levels. The NMOS source 4206 is grounded normally, the NMOS and PMOS drains 4208 are electrically connected together, the NMOS and PMOS gates 4210 are electrically connected together, and the PMOS 4207 source is connected to +Vdd. The 3D structures described below will make use of these third-dimensional connecting lines.

受主晶圓之預加工方法見圖43A。可向重摻雜N單晶矽晶圓4300中注入大劑量N+型離子並進行退火,生成電阻係數更低之層4302。或者,可加入耐高溫金屬(例如鎢)作為低電阻互聯層,或者薄板層或者處理過之幾何金屬化層。氧化物4304會成長或澱積,準備好黏結之晶圓。如圖43B所示,對施主晶圓進行預加工,為層切工作做好準備。圖43B是預加工之用於層切之施主晶圓之圖紙。透過氧化物4312之澱積或生長、表面電漿體處理、原子類型注入(例如在準備SmartCut切割平面4314時要注入H+),P-晶圓4310可用於為層切工作做好準備。如圖43C所示,現在可開始層切流程了,將預先加工之單晶矽施主晶圓層切到受主晶圓之頂部。現在可同時採取CMP、化學拋光和類晶生長(EPI)打磨手段將切割表面4316打磨光滑,也可不進行打磨。 The preprocessing method of the acceptor wafer is shown in Fig. 43A. A large dose of N+ type ions can be implanted into the heavily doped N single crystal silicon wafer 4300 and annealed to form a layer 4302 with lower resistivity. Alternatively, high temperature resistant metals such as tungsten can be added as low resistance interconnect layers, or thin slab layers or treated geometry metallization layers. Oxide 4304 is grown or deposited, ready to bond the wafer. As shown in Figure 43B, the donor wafer is preprocessed in preparation for layer dicing. Figure 43B is a drawing of a pre-processed donor wafer for layer dicing. The P-wafer 4310 can be prepared for layer dicing by deposition or growth of oxide 4312, surface plasma treatment, atomic type implantation (such as H+ implantation in preparation of SmartCut cutting plane 4314). As shown in Figure 43C, the layer dicing process can now begin by layer dicing the pre-processed monocrystalline silicon donor wafer on top of the acceptor wafer. Now the cutting surface 4316 can be polished smooth by CMP, chemical polishing and epitaxial growth (EPI) polishing simultaneously, or not.

圖44A至圖44G展現了生成組件和佈線以及建設3D模組庫之工藝流程。如圖44A所示,打磨終止層4404(例如氮化矽或無定形碳)在保護氧化層4402之後可能會澱積。對NMOS源極-接地4406進行掩蔽和蝕刻,使之與作為接地 平面之重摻雜N+層4302相接觸。這步操作可在典型之接觸層尺寸和精度下進行。為清晰起見,兩層氧化層(受主晶圓氧化層4304和施主晶圓氧化層4312)被合併在一起,稱為4400。向NMOS源極-接地4406填充重摻雜多晶矽或非晶矽,或者高熔點金屬(例如鎢);然後如圖44B所示對其進行化學-機械打磨,直至達到能夠保護氧化層4404之程度。 44A to 44G show the process flow of generating components and wiring and building a 3D module library. As shown in FIG. 44A , a grind stop layer 4404 (eg, silicon nitride or amorphous carbon) may be deposited after the protective oxide layer 4402 . NMOS source-ground 4406 is masked and etched to match the ground The planar heavily doped N+ layer 4302 is in contact. This operation can be performed with typical contact dimensions and precision. For clarity, the two oxide layers (acceptor wafer oxide layer 4304 and donor wafer oxide layer 4312 ) are merged together and referred to as 4400 . Fill the NMOS source-ground 4406 with heavily doped polysilicon or amorphous silicon, or a high melting point metal (such as tungsten); then perform chemical-mechanical polishing as shown in FIG.

現在可開始標準之NMOS電晶體成型工藝流程了,但有兩種例外情況。第一種情況:在區分NMOS和PMOS組件之注入步驟中省略光刻掩膜程式,只形成了NMOS組件。第二種情況:在NMOS成型過程中採取或未採取高溫退火步驟,後文描述之有些或全部必要之退火程式只能在PMOS成型之後完成。如圖44C所示,透過掩膜、將未掩膜之P-層4301進行電漿體蝕刻至氧化層4400、剝除掩膜層、澱積間隙填充氧化層以及透過化學-機械打磨法將間隙填充氧化層磨平,在最後之NMOS電晶體中間形成典型之淺槽絕緣層(STI)區4410。也可以同時進行或不進行閾值調整注入。透過HF(氫氟酸)蝕刻之方式去除剩餘之氧化物,將矽表面清理乾淨。 The standard NMOS transistor formation process can now begin, with two exceptions. Case 1: In the implantation step for distinguishing NMOS and PMOS devices, the photolithographic masking process is omitted, and only NMOS devices are formed. The second case: the high-temperature annealing step is adopted or not taken during the NMOS forming process, and some or all of the necessary annealing procedures described later can only be completed after the PMOS forming. As shown in FIG. 44C, through the mask, the unmasked P-layer 4301 is plasma etched to the oxide layer 4400, the mask layer is stripped, a gap-fill oxide layer is deposited, and the gap is removed by chemical-mechanical polishing. The fill oxide is smoothed to form a typical shallow trench insulator (STI) region 4410 between the final NMOS transistors. Simultaneous injection with or without threshold adjustment can also be performed. The remaining oxide is removed by HF (hydrofluoric acid) etching, and the silicon surface is cleaned.

柵極氧化物4411會發生熱生長,摻雜多晶矽會澱積,形成柵極堆疊層。如圖44D所示,對柵極堆疊層進行光刻和蝕刻,形成NMOS柵極4412並在STI佈線4414上形成聚合物。或者,可在本階段利用高-k金屬柵極工藝步驟,形成柵極堆疊層4412並在STI 4414上方形成佈線。此時可進行 柵極堆疊層自對齊LDD(輕摻雜汲極)和halo擊穿注入,以調整接頭和電晶體之擊穿特徵。 Gate oxide 4411 is thermally grown and doped polysilicon is deposited to form the gate stack. Photolithography and etching are performed on the gate stack layer to form NMOS gate 4412 and polymer on STI wiring 4414 as shown in FIG. 44D . Alternatively, a high-k metal gate process step can be utilized at this stage to form the gate stack layer 4412 and form wiring over the STI 4414 . Available at this time Gate stack self-aligned LDD (Lightly Doped Drain) and halo breakdown implants to adjust breakdown characteristics of contacts and transistors.

圖44E展示了氧化物和氮化物之典型隔離片澱積以及後來之回蝕過程,在柵極堆疊層上形成注入偏置隔離片4416。接著進行自對齊N+源極和汲極注入,生成NMOS電晶體源極和汲極4418。此時,要開啟注入離子、設定初始接頭深度,是否進行高溫退火均可。接著可形成自對齊矽化物。另外,可使用標準之半導體生產工藝建設帶相應接點和通孔(未顯示)之一個或多個互聯層。使用諸如銅或鋁之類之金屬在低溫下建設金屬層,或者使用諸如鎢之類之難熔金屬建設,以便在超過400℃之高溫下正常使用。如圖44F所示,將厚氧化膜4420進行澱積,並採用化學-機械打磨(CMP)之方式使其變平坦。在對晶圓進行加工使其成為下一步層切操作之受主晶圓之過程中,晶圓表面4422採取電漿體活化之方式進行處理。 Figure 44E shows a typical spacer deposition of oxide and nitride followed by an etch back process to form implant bias spacers 4416 on the gate stack layer. Then perform self-aligned N+ source and drain implantation to generate NMOS transistor source and drain 4418 . At this time, it is necessary to start implanting ions, set the initial joint depth, and whether to perform high-temperature annealing. A self-aligned silicide may then be formed. Additionally, one or more interconnect layers with corresponding contacts and vias (not shown) can be constructed using standard semiconductor fabrication processes. Use metals such as copper or aluminum to build metal layers at low temperatures, or use refractory metals such as tungsten for normal use at high temperatures exceeding 400°C. As shown in Figure 44F, a thick oxide film 4420 is deposited and planarized by chemical-mechanical polishing (CMP). The wafer surface 4422 is treated by plasma activation during processing of the wafer to become a recipient wafer for the next layer dicing operation.

如圖45A所示,對產生PMOS之施主晶圓進行預加工,為層切工作做好準備。透過氧化物4504之澱積或生長、表面電漿體處理、原子類型注入(例如在準備SmartCut切割平面4506時要注入H+),N-晶圓4502可用於為層切工作做好準備。 As shown in Figure 45A, the donor wafer for PMOS generation is pre-processed in preparation for layer dicing. The N- wafer 4502 can be prepared for layer dicing by deposition or growth of oxide 4504, surface plasma treatment, atomic type implantation (eg H+ implantation in preparation of SmartCut cutting plane 4506).

如圖45B所示,現在可開始層切流程了,將預先加工之單晶矽施主晶圓層切到受主晶圓之頂部,並將受主晶圓氧化物4420層切到施主晶圓氧化物4504上。為優化PMOS之靈活性,可將施主晶圓旋轉90°,使受主晶圓成為黏結 過程之一部分,促進生成<110>矽平面方向上之PMOS溝槽。現在可同時採取CMP、化學拋光和類晶生長(EPI)打磨手段將切割表面4508打磨光滑,也可不進行打磨。 As shown in Figure 45B, the layer dicing process can now begin by layer dicing the pre-processed monocrystalline silicon donor wafer on top of the acceptor wafer and layer dicing the acceptor wafer oxide 4420 onto the donor wafer oxide Object 4504 on. In order to optimize the flexibility of PMOS, the donor wafer can be rotated 90° so that the acceptor wafer can be bonded Part of the process that facilitates the formation of PMOS trenches in the direction of the <110> silicon plane. Now the cutting surface 4508 can be polished smooth by CMP, chemical polishing and epitaxial growth (EPI) polishing at the same time, or not.

為清晰起見,兩層氧化層(受主晶圓氧化層4420和施主晶圓氧化層4504)被合併在一起,稱為4500。現在可開始標準之PMOS電晶體成型工藝流程了,但有一種例外情況。在區分NMOS和PMOS組件之注入步驟中省略光刻掩膜程式,只形成了PMOS組件。這種3D晶片結構之一個優點在於可獨立形成PMOS電晶體和NMOS電晶體。因此,可單獨對每個電晶體之成型過程進行優化。這個過程可透過單獨選擇晶體趨向以及各種應力材料和技術(例如摻雜分佈圖、材料厚度和成分、溫度循環等)來完成。 For clarity, the two oxide layers (acceptor wafer oxide layer 4420 and donor wafer oxide layer 4504 ) are merged together and referred to as 4500 . The standard PMOS transistor formation process can now begin, with one exception. The photolithographic masking process is omitted in the implantation step for distinguishing NMOS and PMOS devices, and only PMOS devices are formed. One advantage of this 3D wafer structure is that PMOS transistors and NMOS transistors can be formed independently. Therefore, the forming process of each transistor can be optimized individually. This process is accomplished through individual selection of crystal orientation and various stress materials and techniques (eg doping profiles, material thickness and composition, temperature cycling, etc.).

打磨終止層4404(例如氮化矽或無定形碳)在保護氧化層4510之後可能會澱積。如圖45C所示,透過光刻、電漿體蝕刻至氧化層4500、澱積間隙填充氧化層以及透過化學-機械打磨法將間隙填充氧化層磨平,在最後之PMOS電晶體之間形成典型之淺槽絕緣層(STI)區4512。也可以同時進行或不進行閾值調整注入。 A grind stop layer 4404 (eg, silicon nitride or amorphous carbon) may be deposited after the protective oxide layer 4510 . As shown in FIG. 45C, through photolithography, plasma etching to the oxide layer 4500, deposition of a gap-fill oxide layer, and smoothing of the gap-fill oxide layer through chemical-mechanical polishing, a typical PMOS transistor is formed between the final PMOS transistors. The shallow trench insulator (STI) region 4512. Simultaneous injection with or without threshold adjustment can also be performed.

透過HF(氫氟酸)蝕刻之方式去除剩餘之氧化物,將矽表面清理乾淨。柵極氧化物4514會發生熱生長,摻雜多晶矽會澱積,形成柵極堆疊層。如圖45D所示,對柵極堆疊層進行光刻和蝕刻,形成PMOS柵極4516並在STI佈線4518上形成聚合物。或者,可在本階段利用高-k金屬柵極工藝步驟,形成柵極堆疊層4516並在STI 4418上方形成佈 線。此時可進行柵極堆疊層自對齊LDD(輕摻雜汲極)和halo擊穿注入,以調整接頭和電晶體之擊穿特徵。 The remaining oxide is removed by HF (hydrofluoric acid) etching, and the silicon surface is cleaned. Gate oxide 4514 is thermally grown and doped polysilicon is deposited to form the gate stack. As shown in FIG. 45D , the gate stack layer is photolithographically and etched to form a PMOS gate 4516 and a polymer on the STI wiring 4518 . Alternatively, a high-k metal gate process step can be utilized at this stage to form the gate stack 4516 and form the wiring over the STI 4418. Wire. At this time, gate stack self-alignment LDD (Lightly Doped Drain) and halo breakdown implantation can be performed to adjust the breakdown characteristics of contacts and transistors.

圖45E展示了氧化物和氮化物之典型隔離片澱積以及後來之回蝕過程,在柵極堆疊層上形成注入偏置隔離片4520。接著進行自對齊P+源極和汲極注入,生成PMOS電晶體源極和汲極4422。採用RTA(快速高熱退火)或熔爐熱裸露方式在PMOS和NMOS組件中進行高熱退火,以開啟移植物並設定接頭。或者,可在NMOS和PMOS源極和汲極注入之後進行鐳射退火,以開啟移植物並設定接頭。如前文所示,可採取光學吸收和反射層對移植物進行退貨,並開啟接頭。 Figure 45E shows a typical spacer deposition of oxide and nitride followed by an etch back process to form implant bias spacers 4520 on the gate stack layer. Then perform self-aligned P+ source and drain implantation to generate PMOS transistor source and drain 4422 . Hyperthermic annealing in PMOS and NMOS components using RTA (rapid hyperthermic annealing) or furnace thermal exposure to open the graft and set the junction. Alternatively, laser annealing can be performed after the NMOS and PMOS source and drain implants to open the grafts and set the contacts. As previously indicated, the graft can be returned with an optically absorbing and reflective layer, and the joint opened.

如圖45F所示,將厚氧化膜4524進行澱積,並採用化學-機械打磨(CMP)之方式使其變平坦。 As shown in Figure 45F, a thick oxide film 4524 is deposited and planarized by chemical-mechanical polishing (CMP).

圖45G說明了三組八層層間接點之程式方法。蝕刻終止層和打磨終止層或層4530可發生澱積,例如氮化物或無定形碳。首先,在第一個接點步驟中對N+接地平面層4302之最深之接點4532,以及NMOS汲極唯一之接點4540和STI接點4546上之NMOS唯一柵極進行掩蔽和蝕刻。接著,在第二個接點步驟中對STI互連接點4542上之NMOS & PMOS柵極以及NMOS和PMOS汲極接點4544進行掩蔽和蝕刻。接著,對PMOS平接點進行掩蔽和蝕刻:第三個接點步驟中STI接點4550上之PMOS柵極佈線、PMOS唯一之源極觸點4552和PMOS唯一之汲極接點4554。或者,首先對最淺之接點進行掩蔽和蝕刻,接著加工中層接點,最後 是最深之接點。金屬線被掩蔽、蝕刻,並填充阻擋金屬,並採取普通之雙嵌入式互連方法進行CMP,從而完成八種接點連接。 Figure 45G illustrates the programming method for three sets of eight layers of interlayer nodes. Etch stop and grind stop layers or layers 4530 may be deposited, such as nitride or amorphous carbon. First, the deepest contact 4532 of the N+ ground plane layer 4302, and the NMOS only gate on the NMOS drain only contact 4540 and the STI contact 4546 are masked and etched in the first contact step. Next, the NMOS & PMOS gates and NMOS and PMOS drain contacts 4544 on the STI interconnect 4542 are masked and etched in a second contact step. Next, mask and etch the PMOS flat contacts: the PMOS gate wiring on the STI contact 4550 in the third contact step, the only PMOS source contact 4552 and the only PMOS drain contact 4554 . Alternatively, mask and etch the shallowest contacts first, then process the middle contacts, and finally It is the deepest point of contact. The metal lines are masked, etched, and filled with barrier metal, and CMP is performed by a common dual-embedded interconnection method to complete eight kinds of contact connections.

如圖46A至46C所示,關於圖42中所示之2D CMOS倒相器晶片佈局圖和示意圖,可利用上述工藝流程建設壓縮3D CMOS倒相器晶片範例。3D晶片之俯視圖見圖46A,其中NMOS和PMOS之淺槽絕緣層(STI)4600保持一致,PMOS處於NMOS頂部。 As shown in FIGS. 46A to 46C , with regard to the layout and schematic diagram of the 2D CMOS inverter chip shown in FIG. 42 , an example of a compressed 3D CMOS inverter chip can be constructed using the above process flow. The top view of the 3D chip is shown in FIG. 46A , where the STI 4600 of the NMOS and the PMOS are consistent, and the PMOS is on top of the NMOS.

X方向之剖視圖見圖46B,Y方向之剖視圖見圖46C。NMOS和PMOS柵極4602保持一致並堆疊,被STI上之一個NMOS柵極連接到STI接點4604上之PMOS柵極上。圖42A展示了倒相器輸入訊號A之連接方式。如圖42所示,圖46A &圖46C中之接地平面4606之N+源極接點(類似於圖44B之接點4406)將NMOS源極進行接地。如圖42所示,PMOS源極接點4608(類似於圖45G中之接點4552)將PMOS源極連接到+V 4207。如圖42所示,NMOS和PMOS汲極共用接點4610(類似於圖45G中之接點4544)將共用接點4208作為輸出Y。未顯示接地-接地平面接點(類似於圖45G中之接點4532)。並非在每個晶片中都需要這個接點,並可將其共用。 See Figure 46B for a cross-sectional view in the X direction, and Figure 46C for a cross-sectional view in the Y direction. The NMOS and PMOS gates 4602 are aligned and stacked, connected by an NMOS gate on the STI to a PMOS gate on the STI contact 4604 . Figure 42A shows how the inverter input signal A is connected. As shown in Figure 42, the N+ source contact (similar to contact 4406 of Figure 44B) of the ground plane 4606 in Figures 46A & 46C grounds the NMOS source. As shown in FIG. 42, PMOS source contact 4608 (similar to contact 4552 in FIG. 45G) connects the PMOS source to +V 4207. As shown in FIG. 42, NMOS and PMOS drain common junction 4610 (similar to junction 4544 in FIG. 45G) has common junction 4208 as output Y. The ground-to-ground plane contact (similar to contact 4532 in Figure 45G) is not shown. This contact is not required in every die and can be shared.

其他之3D邏輯器或存儲晶片可使用類似之方式建設。圖47展示了典型之2D雙輸入NOR晶片佈局圖和示意圖,其中NMOS電晶體4702和PMOS電晶體4704並排放在一起,處於摻雜程度不同之井中。NMOS源極4706採用一般方式 接地,兩個NMOS源極和其中一個PMOS汲極4708透過電力方式連接在一起,形成輸入Y。NMOS & PMOs柵極4710透過電力方式連接在一起,形成輸入A或輸出B。下文中所述之3D結構將利用第三維之這些連接線。 Other 3D logic or memory chips can be constructed in a similar manner. FIG. 47 shows a typical layout and schematic diagram of a 2D dual-input NOR chip, in which NMOS transistors 4702 and PMOS transistors 4704 are arranged side by side in wells with different doping levels. NMOS source 4706 in general way Grounded, two NMOS sources and one of the PMOS drains 4708 are electrically connected together to form an input Y. NMOS & PMOs gates 4710 are electrically connected together to form input A or output B. The 3D structures described below will make use of these connecting lines in the third dimension.

如圖44A至圖48C所示,可使用上述工藝流程建設壓縮3D雙輸入NOR晶片範例。3D晶片之俯視圖見圖48A,其中NMOS和PMOS之淺槽絕緣層(STI)4800在底部和側部保持一致,並不處於頂部矽層上,只有NMOS汲極被連接起來。晶片X方向之剖視圖見圖48B,Y方向之剖視圖見圖48C。 As shown in FIGS. 44A-48C , the process flow described above can be used to construct a compressed 3D dual-input NOR chip example. The top view of the 3D chip is shown in FIG. 48A , where the shallow trench insulator (STI) 4800 of NMOS and PMOS is consistent at the bottom and side, not on the top silicon layer, and only the NMOS drain is connected. The cross-sectional view of the wafer in the X direction is shown in FIG. 48B, and the cross-sectional view in the Y direction is shown in FIG. 48C.

NMOS和PMOS柵極4802保持一致並堆疊,每個柵極被STI上之一個NMOS柵極連接到STI接點4804上之PMOS柵極上(類似於圖45G中所示之接點4542)。圖47展示了輸入訊號A & B之連接方式。 The NMOS and PMOS gates 4802 are aligned and stacked, each gate being connected by an NMOS gate on the STI to a PMOS gate on the STI contact 4804 (similar to contact 4542 shown in Figure 45G). Figure 47 shows the connection of input signal A & B.

如圖47所示,圖48A和圖48C中之接地平面4806之N+源極接點將NMOS源極接地。如圖47所示,PMOS源極接點4808(類似於圖45G中之接點4552)將PMOS源極連接到+V 4707。如圖47所示,NMOS和PMOS汲極共用接點4810(類似於圖45G中之接點4544)將共用接點4708作為輸出Y。NMOS源極接點4812(類似於圖45中之接點4540)將NMOS連接到輸出Y。使用金屬將輸出Y連接到NMOS和PMOS汲極共用接點4810,形成圖47中之輸出Y。未顯示接地-接地平面接點(類似於圖45G中之接點4532)。並非在每個晶片中都需要這個接點,並可將其共 用。 As shown in Figure 47, the N+ source contact of ground plane 4806 in Figures 48A and 48C connects the NMOS source to ground. As shown in FIG. 47, PMOS source contact 4808 (similar to contact 4552 in FIG. 45G) connects the PMOS source to +V 4707. As shown in FIG. 47, NMOS and PMOS drain common junction 4810 (similar to junction 4544 in FIG. 45G) has common junction 4708 as output Y. NMOS source contact 4812 (similar to contact 4540 in FIG. 45) connects the NMOS to output Y. Output Y is connected to NMOS and PMOS drain common junction 4810 using metal to form output Y in FIG. 47 . The ground-to-ground plane contact (similar to contact 4532 in Figure 45G) is not shown. This contact is not required in every chip and can be shared use.

如圖49A至圖49C所示,可使用上述工藝流程建設備用壓縮3D雙輸入NOR晶片範例。3D晶片之俯視圖見圖49A,其中NMOS和PMOS之淺槽絕緣層(STI)4900在頂部和側部保持一致,並不處於頂部矽層上。這樣就在NMOS-A和NMOS-B電晶體之間形成絕緣,並將獨立之柵極連接起來。如圖47所示,帶有字母-A或-B之NMOS或PMOS電晶體標明了柵極連接之NMOS或PMOS電晶體,要麼是A輸入,要麼是B輸入。晶片X方向之剖視圖見圖49B,Y方向之剖視圖見圖49C。 As shown in FIGS. 49A-49C , an alternate compressed 3D dual-input NOR wafer paradigm can be constructed using the above-described process flow. The top view of the 3D wafer is shown in FIG. 49A , where the shallow trench insulation (STI) 4900 of NMOS and PMOS is consistent on the top and sides, and is not on the top silicon layer. This creates isolation between the NMOS-A and NMOS-B transistors and connects the separate gates. As shown in Figure 47, an NMOS or PMOS transistor with the letters -A or -B designates the NMOS or PMOS transistor to which the gate is connected, either the A input or the B input. The cross-sectional view of the wafer in the X direction is shown in FIG. 49B, and the cross-sectional view in the Y direction is shown in FIG. 49C.

PMOS-B柵極4902與虛擬柵極4904一直,並堆在該柵極上;PMOS-B柵極4902僅透過STI接點4908上之PMOS柵極與輸入B聯繫起來。NMOS-A柵極4910和NMOS-B柵極4912都處於PMOS-A柵極4906之下方。NMOS-A柵極4910和PMOS-A柵極4912被連接在一起,並被STI上之NMOS柵極與輸入A連接起來,接著與STI接點4914上之PMOS柵極連接起來(類似於圖45G中所示之接點4542)。NMOS-B柵極4912被STI接點4916上之NMOS唯一柵極連接到輸入B,類似於圖45中所示之接點4546。圖47展示了輸入訊號A & B 4710之連接方式。 PMOS-B gate 4902 is aligned with dummy gate 4904 and stacked on top of it; PMOS-B gate 4902 is only connected to input B through the PMOS gate on STI contact 4908. Both the NMOS-A gate 4910 and the NMOS-B gate 4912 are under the PMOS-A gate 4906 . The NMOS-A gate 4910 and the PMOS-A gate 4912 are connected together and connected by the NMOS gate on the STI to input A, which in turn is connected to the PMOS gate on the STI contact 4914 (similar to FIG. 45G The contact shown in 4542). NMOS-B gate 4912 is connected to input B by the NMOS only gate on STI contact 4916, similar to contact 4546 shown in FIG. Figure 47 shows how input signals A & B 4710 are connected.

如圖47B所示,圖49A和圖49C中之接地平面4918之N+源極接點將NMOS源極接地,類似於圖44B中之接地4406。如圖47所示,Vdd之PMOS-B源極接點4920(類似於圖45G中之接點4552)將PMOS源極連接到+V 4707。如 圖47所示,NMOS-A、NMOS-B和PMOS汲極共用接點4922(類似於圖45G中之接點4544)將共用接點4708作為輸出Y。未顯示接地-接地平面接點(類似於圖45G中之接點4532)。並非在每個晶片中都需要這個接點,並可將其共用。 As shown in Figure 47B, the N+ source contact of ground plane 4918 in Figures 49A and 49C grounds the NMOS source, similar to ground 4406 in Figure 44B. As shown in FIG. 47 , a PMOS-B source contact 4920 for Vdd (similar to contact 4552 in FIG. 45G ) connects the PMOS source to +V 4707 . like As shown in FIG. 47 , NMOS-A, NMOS-B and PMOS drains share a joint 4922 (similar to joint 4544 in FIG. 45G ) with common joint 4708 as output Y. The ground-to-ground plane contact (similar to contact 4532 in Figure 45G) is not shown. This contact is not required in every die and can be shared.

可使用上述工藝流程建設CMOS傳輸柵極。圖50A展示了一個典型之2D CMOS傳輸柵極之示意圖和佈局圖範例。NMOS電晶體5002和PMOS電晶體5004並排放在一起,處於摻雜程度不同之井中。控制訊號A(作為NMOS柵極輸入5006)及其補充Â(作為PMOS柵極輸入5008)允許輸入訊號在NMOS和PMOS電晶體均開啟時(A=1,Â=0)完全傳給輸出訊號,在NMOS和PMOS電晶體均關閉時(A=0,Â=1)不透過任何輸入訊號。NMOS和PMOS之源極5010透過電力方式連接在一起,並連接到輸出上;NMOS和PMOS之汲極5012透過電力方式連接在一起,產生輸出。下文中所述之3D結構將利用第三維之這些連接線。 CMOS transfer gates can be constructed using the process flow described above. Figure 50A shows an example schematic and layout of a typical 2D CMOS transfer gate. The NMOS transistor 5002 and the PMOS transistor 5004 are arranged side by side in wells with different doping levels. Control signal A (as NMOS gate input 5006) and its complement  (as PMOS gate input 5008) allows the input signal to be fully passed to the output signal when both NMOS and PMOS transistors are on (A=1, Â=0), When both NMOS and PMOS transistors are turned off (A=0, Â=1), no input signal is passed through. The sources 5010 of the NMOS and PMOS are electrically connected together and connected to an output; the drains 5012 of the NMOS and PMOS are connected together electrically to generate an output. The 3D structures described below will make use of these connecting lines in the third dimension.

如圖50B至圖50D所示,可使用上述工藝流程建設壓縮3D CMOS傳輸晶片範例。3D晶片之俯視圖見圖50B,其中NMOS和PMOS之淺槽絕緣層(STI)5000在頂部和側面保持一致。晶片X方向之剖視圖見圖50C,Y方向之剖視圖見圖50D。PMOS柵極5014與NMOS柵極5016保持一致,並堆疊。STI接點5018上之PMOS柵極將PMOS柵極5014與控制訊號Â 5008連接在一起。STI接點5020上之NMOS柵極將 NMOS柵極5016與控制訊號A 5006連接在一起。NMOS和PMOS源極共用接點5022將共用連接層5010與圖50A中之輸入連接起來。NMOS和PMOS汲極共用接點5024將共用連接層5012與圖50A中之輸出連接起來。 As shown in FIGS. 50B-50D , a compressed 3D CMOS transfer chip example can be built using the above process flow. The top view of the 3D wafer is shown in FIG. 50B , where the shallow trench insulation (STI) 5000 of NMOS and PMOS is consistent on the top and sides. The cross-sectional view of the wafer in the X direction is shown in FIG. 50C, and the cross-sectional view in the Y direction is shown in FIG. 50D. The PMOS gate 5014 is aligned with the NMOS gate 5016 and stacked. The PMOS gate on STI contact 5018 connects the PMOS gate 5014 to the control signal 5008. The NMOS gate on STI contact 5020 will The NMOS gate 5016 is connected together with the control signal A 5006 . NMOS and PMOS source common contact 5022 connects common connection layer 5010 to the input in FIG. 50A. NMOS and PMOS drain common contact 5024 connects common connection layer 5012 to the output in FIG. 50A.

可採取該3D工藝流程和方法建設其他之邏輯晶片和存儲晶片,例如雙輸入NAND柵極、傳輸柵極、NMOS驅動器、觸發器、6T SRAM、浮體DRAM、CAM(按位址定址記憶體)陣列等。 This 3D process flow and method can be used to build other logic chips and memory chips, such as dual-input NAND gates, transfer gates, NMOS drivers, flip-flops, 6T SRAM, floating body DRAM, CAM (addressable memory) array etc.

還可以建設更多類型之壓縮3D模組庫,從而使NMOS和PMOS組件之間存在一層或多層金屬佈線。這種方法可建設更多之壓縮晶片,尤其是複雜之晶片;然而,如前文所述,現在應當使用低溫層切和電晶體成型工藝建設頂部PMOS組件,除非NMOS和PMOS層之間之金屬採用耐火金屬,例如鎢。 It is also possible to build more types of compressed 3D module libraries, so that there is one or more layers of metal wiring between NMOS and PMOS components. This method can build more compact wafers, especially complex wafers; however, as mentioned earlier, low-temperature layer-slicing and transistor formation processes should now be used to build the top PMOS components, unless the metal between the NMOS and PMOS layers is used. Refractory metals such as tungsten.

因此,在圖43和圖44中可採取上述之模組庫工藝流程。如圖21、圖22、圖29、圖39和圖40所示,接下來,在NMOS組件之頂部建設一層或多層傳統金屬佈線層,接著那個晶圓就被視為受主晶圓或“外殼”晶圓808,對PMOS組件進行層切,並利用其中一個低溫流程進行建設。 Therefore, in FIG. 43 and FIG. 44, the above-mentioned process flow of the module library can be adopted. As shown in Figure 21, Figure 22, Figure 29, Figure 39 and Figure 40, next, one or more conventional metal wiring layers are built on top of the NMOS components, and then that wafer is regarded as the acceptor wafer or "enclosure". "Wafer 808, the PMOS components are layer sliced and built using one of the low temperature processes.

如圖51A至圖51D所示,可使用上述工藝流程建設壓縮3D CMOS 6-電晶體SRAM(靜態隨機存取記憶體)晶片。SRAM晶片之示意圖見圖51A。讀取該晶片受到文字行電晶體M5和M6之控制,其中M6被標記為5106。讀取電晶體控制著位線5122和位線杆型線5124之連接。用M1或 M2 5102將兩個交叉耦合之倒相器M1-M4拉高至Vdd 5108,再透過電晶體M3或M4 5104拉到接地5110上。 As shown in Figures 51A-51D, the process flow described above can be used to build compressed 3D CMOS 6-transistor SRAM (Static Random Access Memory) chips. A schematic diagram of a SRAM chip is shown in FIG. 51A. Reading the chip is controlled by word line transistors M5 and M6, where M6 is labeled 5106. The read transistor controls the connection of bitline 5122 and bitline barline 5124. with M1 or M2 5102 pulls the two cross-coupled inverters M1-M4 to Vdd 5108, and then pulls to ground 5110 through transistor M3 or M4 5104.

3D SRAM晶片之NMOS(未顯示金屬)之俯視圖見圖51B;SRAM晶片X方向之橫截面圖見圖51C;Y方向之橫截面圖見51D。NMOS文字線存取電晶體M6 5106被連接到位線杆型線5124(帶有NMOS金屬1之接點)上。NMOS下拉電晶體5104被NMOS金屬1之接點連接到接地線5110上,並連接到背板N+接地層上。NMOS金屬1中之位元線5122和電晶體絕緣氧化物5100如圖所示。Vdd電源5108被帶入PMOS金屬1上之晶片中,並透過P+接點連接到M2 5102上。STI上之PMOS多晶矽至STI接點5112上之NMOS多晶矽將M2 5102之柵極和M4 5104之柵極連接起來,說明3D交叉耦合之方法。透過PMOS P+至NMOS N+接點5114將M2和M4之普通汲極與位線讀取電晶體M6連接起來。 The top view of the NMOS (metal not shown) of the 3D SRAM chip is shown in Figure 51B; the cross-sectional view of the SRAM chip in the X direction is shown in Figure 51C; the cross-sectional view in the Y direction is shown in Figure 51D. NMOS word line access transistor M6 5106 is connected to bit line bar type line 5124 (contact with NMOS metal 1). The NMOS pull-down transistor 5104 is connected to the ground line 5110 by the contact of NMOS metal 1, and is connected to the N+ ground layer of the backplane. Bit line 5122 and TIO 5100 in NMOS metal 1 are shown. The Vdd supply 5108 is brought into the die on PMOS Metal 1 and connected to M2 5102 through the P+ contact. The PMOS polysilicon on the STI to the NMOS polysilicon on the STI contact 5112 connects the gate of M2 5102 and the gate of M4 5104, illustrating the method of 3D cross-coupling. The common drains of M2 and M4 are connected to bit line sense transistor M6 through PMOS P+ to NMOS N+ contact 5114 .

如圖62A至圖62D所示,可使用上述工藝流程建設壓縮3D CMOS雙輸入NAND晶片範例。NAND-2晶片之示意圖和2D佈局圖見圖62A。兩個PMOS電晶體6201源極6211被連接在一起,並連接到V+電源上。兩個PMOS汲極被連接在一起,其中一個連接到NMOS汲極6213,另外一個連接到輸出Y上。輸入A 6203被連接到一個PMOS柵極和一個NMOS柵極上。輸入B 6204被連接到另外PMOS和NMOS柵極上。NMOS A汲極將6220連接到NMOS B源極上,PMOS B汲極6212接地。下文中所述之3D結構將利用第三維之這些連接線。 As shown in FIGS. 62A-62D , the above-described process flow can be used to construct an example of a compressed 3D CMOS dual-input NAND chip. A schematic diagram and a 2D layout of a NAND-2 chip are shown in FIG. 62A. The sources 6211 of the two PMOS transistors 6201 are connected together and connected to the V+ power supply. Two PMOS drains are connected together, one of which is connected to the NMOS drain 6213 and the other is connected to the output Y. Input A 6203 is connected to one PMOS gate and one NMOS gate. Input B 6204 is connected to the other PMOS and NMOS gates. The NMOS A drain connects 6220 to the NMOS B source, and the PMOS B drain 6212 is grounded. The 3D structures described below will make use of these connecting lines in the third dimension.

3D NAND-2晶片(未顯示金屬)之俯視圖見圖62B;NAND-2晶片X方向之橫截面圖見圖62C;Y方向之橫截面圖見62D。兩個PMOS源極6211在PMOS矽層中被連接在一起,並在PMOS金屬1層中透過接點連接到V+電源金屬6216。NMOS A汲極和PMOS A汲極使用對穿P+將6213連接到N+接點,並連接到PMOS金屬2中之輸出Y金屬6217上,同時再透過PMOS金屬1 6215連接到PMOS B汲極接點上。PMOS金屬2 6214上之輸入A將6203連接到PMOS A柵極和NMOS A柵極上,NMOS A柵極透過STI上之PMOS柵極將其連接到STI接點上之NMOS柵極上。輸入B將6204連接到PMOS B柵極上,NMOS B利用STI上之P+柵極將其連接到STI接點上之NMOS柵極上。NMOS A源極和NMOS B汲極在NMOS矽層上被連接在一起6220。NMOS B源極6212被NMOS金屬1之接點連接到接地線6218上,並連接到背板N+接地層上。電晶體絕緣氧化物6200如圖所示。 A top view of a 3D NAND-2 chip (metal not shown) is shown in FIG. 62B; a cross-sectional view of a NAND-2 chip in the X direction is shown in FIG. 62C; a cross-sectional view in the Y direction is shown in FIG. 62D. The two PMOS sources 6211 are connected together in the PMOS silicon layer and connected to the V+ power metal 6216 through a contact in the PMOS metal 1 layer. The NMOS A drain and the PMOS A drain use the P+ to connect the 6213 to the N+ contact, and connect to the output Y metal 6217 in the PMOS metal 2, and then connect to the PMOS B drain contact through the PMOS metal 1 6215 superior. Input A on PMOS metal 2 6214 connects 6203 to PMOS A gate and NMOS A gate, NMOS A gate connects it to NMOS gate on STI contact through PMOS gate on STI. Input B connects the 6204 to the PMOS B gate, and NMOS B uses the P+ gate on the STI to connect it to the NMOS gate on the STI contact. The NMOS A source and the NMOS B drain are connected together 6220 on the NMOS silicon layer. The NMOS B source 6212 is connected to the ground line 6218 by the NMOS metal 1 contact, and is connected to the backplane N+ ground plane. Transistor insulating oxide 6200 is shown in the figure.

還可以建設其他類型之壓縮3D模組庫,從而使NMOS和PMOS組件層之間存在一層或多層金屬佈線。這種方法可建設更多之壓縮晶片結構,尤其是複雜之晶片;然而,如前文所述,現在應當使用低溫層切和電晶體成型工藝建設第一層NMOS層上方之組件。 Other types of compressed 3D libraries can also be built such that there is one or more layers of metal wiring between the NMOS and PMOS component layers. This method can build more compact wafer structures, especially complex wafers; however, as mentioned earlier, low-temperature layer-slicing and transistor formation processes should now be used to build devices above the first NMOS layer.

因此,在圖43和圖44中可採取上述之模組庫工藝流程。如圖21、圖22、圖29、圖39和圖40所示,接下來,在NMOS組件之頂部建設一層或多層傳統金屬佈線層,接著那個晶圓就被視為受主晶圓或“外殼”晶圓808,對PMOS 組件進行層切,並利用其中一個低溫流程進行建設。接著可重複操作這個低溫流程,形成另外一層PMOS或NMOS組件層,等等。 Therefore, in FIG. 43 and FIG. 44, the above-mentioned process flow of the module library can be adopted. As shown in Figure 21, Figure 22, Figure 29, Figure 39 and Figure 40, next, one or more conventional metal wiring layers are built on top of the NMOS components, and then that wafer is regarded as the acceptor wafer or "enclosure". ” Wafer 808, on PMOS Components are cut in layers and built using one of the cryogenic processes. This low-temperature process can then be repeated to form another layer of PMOS or NMOS components, and so on.

如圖53A至圖53E所示,可使用上述工藝流程建設壓縮3D CMOS按位址定址記憶體(CAM)陣列。CAM晶片之示意圖見圖53A。讀取SRAM晶片受到文字行電晶體M5和M6之控制,其中M6被標記為5332。讀取電晶體控制著位線5342和位線杆型線5340之連接。用M1或M2 5304將兩個交叉耦合之倒相器M1-M4拉高至Vdd 5334,再透過電晶體M3或M4 5306拉到接地5330上。匹配線5336將比較電路之符合或不符合狀態傳輸給匹配位址解碼器。檢測線5316和檢測小節線5318選擇用於位址檢索之比較電路晶片,並將下拉電晶體M8和M10 5326之柵極接地5322。SRAM狀態讀取電晶體M7和M9 5302柵極被連接到SRAM晶片節點n1和n2上,以將SRAM晶片之狀態讀入比較電路晶片。下文中所述之3D結構將利用第三維之這些連接線。 As shown in Figures 53A-53E, the process flow described above can be used to build a compressed 3D CMOS Addressable Memory (CAM) array. A schematic diagram of a CAM chip is shown in Figure 53A. The read SRAM chip is controlled by word row transistors M5 and M6, where M6 is marked as 5332. The read transistor controls the connection of bitline 5342 and bitline barline 5340. The two cross-coupled inverters M1-M4 are pulled up to Vdd 5334 by M1 or M2 5304, and then pulled to ground 5330 by transistor M3 or M4 5306. The match line 5336 transmits the matching or non-matching status of the comparing circuit to the matching address decoder. The sense line 5316 and the sense bar line 5318 select the comparison chip used for address retrieval and ground 5322 the gates of the pull-down transistors M8 and M10 5326 . The gates of the SRAM state read transistors M7 and M9 5302 are connected to the nodes n1 and n2 of the SRAM chip to read the state of the SRAM chip into the comparison circuit chip. The 3D structures described below will make use of these connecting lines in the third dimension.

3D CAM晶片(未顯示金屬)之上層NMOS俯視圖見圖53B;3D CAM晶片(顯示金屬)之上層NMOS俯視圖見圖53C;3D CAM晶片X方向之橫截面圖見圖53D;Y方向之橫截面圖見圖53E。NMOS文字線存取電晶體M6 5332被連接到位線杆型線5342(帶有NMOS金屬1之N+接點)上。NMOS下拉電晶體5306被NMOS金屬1之N+接點連接到接地線5330上,並連接到背板N+接地層上。NMOS金屬1中之位元線5340和電晶體絕緣氧化物5300如圖所示。接地 層5322被帶入上層NMOS金屬-2上之晶片中。Vdd電源5334被帶入PMOS金屬-1上之晶片中,並透過P+接點連接到M2 5304上。STI上之PMOS多晶矽至STI接點5314上之底部NMOS多晶矽將M2 5304之柵極和M4 5306之柵極連接起來,說明SRAM 3D交叉耦合之方法,並透過PMOS金屬-1 5312連接至比較晶片節點n1。透過PMOS P+至NMOS N+接點5320將M2和M4之普通汲極與位線讀取電晶體M6連接起來,透過PMOS金屬-1 5310將節點n2連接到M9柵極5302並透過金屬將其連接到STI接點5308上之柵極。上層NMOS比對晶片接地下拉電晶體M10柵極5326被連接到檢測線5316,並藉由NMOS金屬-2連接到STI接點上之柵極多晶矽。上層NMOS金屬-2中之檢測線5318將直通接點5324連接到上層NMOS層中之M8之柵極。上層NMOS金屬-2中之匹配線5336連接到M9和M7之汲極側。 The top view of the NMOS on the 3D CAM chip (not showing metal) is shown in Figure 53B; the top view of the NMOS on the 3D CAM chip (showing metal) is shown in Figure 53C; the cross-sectional view of the 3D CAM chip in the X direction is shown in Figure 53D; the cross-sectional view in the Y direction See Figure 53E. NMOS word line access transistor M6 5332 is connected to bit line bar 5342 (N+ contact with NMOS metal 1). The NMOS pull-down transistor 5306 is connected to the ground line 5330 by the N+ contact of the NMOS metal 1, and is connected to the N+ ground layer of the backplane. Bit line 5340 and TIO 5300 in NMOS metal 1 are shown. grounding Layer 5322 is brought into the wafer on top NMOS Metal-2. The Vdd supply 5334 is brought into the die on PMOS metal-1 and connected to M2 5304 through the P+ contact. PMOS polysilicon on STI to bottom NMOS polysilicon on STI contact 5314 connects the gate of M2 5304 to the gate of M4 5306, illustrates the method of SRAM 3D cross-coupling, and connects to the comparison chip node through PMOS metal-1 5312 n1. Connect common drains of M2 and M4 to bit line read transistor M6 through PMOS P+ to NMOS N+ contact 5320, node n2 to M9 gate 5302 through PMOS metal-1 5310 and metal to Gate on STI contact 5308. The gate 5326 of the upper NMOS comparison chip ground pull-down transistor M10 is connected to the detection line 5316, and is connected to the gate polysilicon on the STI contact through NMOS metal-2. A sense line 5318 in the upper NMOS metal-2 connects the thru contact 5324 to the gate of M8 in the upper NMOS layer. Match line 5336 in upper NMOS Metal-2 is connected to the drain side of M9 and M7.

還可以建設其他類型之壓縮3D模組庫,從而使NMOS和PMOS組件層之間存在一層或多層金屬佈線,並垂直建設一個或多個組件。 Other types of compressed 3D modules can also be built such that there is one or more layers of metal wiring between the NMOS and PMOS component layers and one or more components are built vertically.

如圖63A至63G所示建設壓縮3D CMOS八輸入NAND晶片。NAND-8晶片之示意圖和2D佈局圖見圖63A。八個PMOS電晶體6301源極6311被連接在一起,並連接到V+電源上。兩個PMOS汲極被連接在一起6313,其中一個連接到NMOS A汲極,另外一個連接到輸出Y上。輸入A至H被連接到一個PMOS柵極一個NMOS柵極上。輸入A被連接到PMOS A柵極和NMOS A柵極,輸入B被連接到PMOS B柵 極和NMOS B柵極。依次類推,輸入H被連接到PMOS H柵極和NMOS H柵極。輸出Y、PMOS汲極和接地層之間之八個NMOS電晶體採取串聯方式連接。下文中所述之3D結構將利用這些第三維之連接線。 Compressed 3D CMOS eight-input NAND chips were constructed as shown in Figures 63A to 63G. A schematic diagram and 2D layout of a NAND-8 chip is shown in FIG. 63A. The sources 6311 of the eight PMOS transistors 6301 are connected together and connected to the V+ supply. Two PMOS drains are connected together 6313, one of which is connected to the NMOS A drain and the other is connected to the output Y. Inputs A to H are connected to one PMOS gate and one NMOS gate. Input A is connected to PMOS A gate and NMOS A gate, input B is connected to PMOS B gate pole and NMOS B gate. By analogy, the input H is connected to the PMOS H gate and the NMOS H gate. The eight NMOS transistors between the output Y, the PMOS drain and the ground plane are connected in series. The 3D structures described below will make use of these third-dimensional connecting lines.

3D NAND-8晶片(未顯示金屬,帶水平NMOS和PMOS組件)之俯視圖見圖63B;晶片X方向之橫截面圖見圖63C;Y方向之橫截面圖見63D。帶垂直PMOS和水平NMOS組件之NAND-8之俯視圖見圖63E;X方向之橫截面圖見圖63F;Y方向之橫截面圖見63H。圖63B至63D以及圖63E至圖63G中所示之案例中之同功結構也可以使用相同之參考編號。八個PMOS源極6311在PMOS矽層中被連接在一起,並在PMOS金屬1層中透過金屬接點之P+連接到V+電源金屬6316。使用對穿P+將NMOS A汲極和PMOS A汲極6313被連接到N+接點,並連接到PMOS金屬2中之輸出Y電源金屬6315上,同時再透過PMOS金屬1 6215連接到PMOS汲極接點上。PMOS金屬2 6314上之輸入A將6303連接到PMOS A柵極和NMOS A柵極上,NMOS A柵極透過STI上之PMOS柵極將其連接到STI接點6314上之NMOS柵極上。其他所有之輸入均以類似之方式連接到P和N柵極上。NMOS A源極和NMOS B汲極在NMOS矽層上被連接在一起6320。NMOS H源極6232被NMOS金屬1之接點連接到接地線6318上,並連接到背板N+接地層上。電晶體絕緣氧化物6300如圖所示。 A top view of a 3D NAND-8 wafer (metal not shown, with horizontal NMOS and PMOS components) is shown in Figure 63B; a cross-sectional view of the wafer in the X direction is shown in Figure 63C; a cross-sectional view in the Y direction is shown in Figure 63D. A top view of NAND-8 with vertical PMOS and horizontal NMOS components is shown in Figure 63E; a cross-sectional view in the X direction is shown in Figure 63F; a cross-sectional view in the Y direction is shown in Figure 63H. The equivalent structures in the cases shown in Figures 63B to 63D and Figures 63E to 63G may also use the same reference numbers. The eight PMOS sources 6311 are connected together in the PMOS silicon layer and connected to the V+ power metal 6316 through the P+ of the metal contact in the PMOS metal 1 layer. The NMOS A drain and the PMOS A drain 6313 are connected to the N+ contact using the through P+, and connected to the output Y power metal 6315 in the PMOS metal 2, and then connected to the PMOS drain through the PMOS metal 1 6215 Point. Input A on PMOS metal 2 6314 connects 6303 to PMOS A gate and NMOS A gate, NMOS A gate connects it to NMOS gate on STI contact 6314 through PMOS gate on STI. All other inputs are similarly connected to the P and N gates. The NMOS A source and the NMOS B drain are connected together 6320 on the NMOS silicon layer. The NMOS H source 6232 is connected to the ground line 6318 by the NMOS metal 1 contact, and is connected to the backplane N+ ground plane. Transistor insulating oxide 6300 is shown.

如圖64A至64G所示建設壓縮3D CMOS八輸入NOR晶 片。NOR-8晶片之示意圖和2D佈局圖見圖64A。PMOS H電晶體源極6411被連接到V+電源。NMOS汲極被連接在一起6413,並連接到PMOS A之汲極和輸出Y上。輸入A至H被連接到一個PMOS柵極和一個NMOS柵極上。輸入A 6403被連接到PMOS A柵極和NMOS A柵極上。所有NMOS源極均接地6412。在柵極堆疊層、PMOS G中,PMOS H汲極連接6420到下一個PMOS源極,依次類推。下文中所述之3D結構將利用第三維之這些連接線。 Construction of compressed 3D CMOS eight-input NOR crystals as shown in Figures 64A to 64G piece. A schematic and 2D layout of a NOR-8 chip is shown in Figure 64A. The PMOS H transistor source 6411 is connected to the V+ supply. The NMOS drains are connected together 6413 and to the PMOS A drain and output Y. Inputs A to H are connected to a PMOS gate and an NMOS gate. Input A 6403 is connected to PMOS A gate and NMOS A gate. All NMOS sources are grounded 6412. In the gate stack layer, PMOS G, the PMOS H drain connects 6420 to the next PMOS source, and so on. The 3D structures described below will make use of these connecting lines in the third dimension.

3D NOR-8晶片(未顯示金屬,帶水平NMOS和PMOS組件)之俯視圖見圖64B;晶片X方向之橫截面圖見圖64C;Y方向之橫截面圖見64D。帶垂直PMOS和水平NMOS組件之NAND-8之俯視圖見圖64E;X方向之橫截面圖見圖64F;Y方向之橫截面圖見64G。PMOS H源極6411透過金屬接點之P+被連接到PMOS金屬1層中之V+電源金屬6416上。PMOS H汲極連接6420到PMOS矽層中之PMOS G源極。透過NMOS金屬-1接點之N+將NMOS源極6412全部接地,並且連接到N-基板金屬線6418上以及背板N+接地層上。利用STI上之柵極將PMOS金屬-2上之輸入A連接到PMOS和NMOS柵極6403,接著再連接到STI接點6414上之柵極上。利用NMOS金屬-2 6415將NMOS汲極全部連接到NMOS A汲極和PMOS A汲極6413,P+將其連接到N+、PMOS金屬-2接點6417(連接到輸出Y上)。圖64G講述了利用垂直PMOS電晶體將堆疊源極和汲極緊密地連接起來,並形成圖64E中所示之壓縮區晶片。電晶體絕緣氧化 物6400如圖所示。 See Figure 64B for a top view of a 3D NOR-8 wafer (metal not shown, with horizontal NMOS and PMOS components); see Figure 64C for a cross-sectional view of the wafer in the X direction; and 64D for a cross-sectional view in the Y direction. A top view of NAND-8 with vertical PMOS and horizontal NMOS components is shown in Figure 64E; a cross-sectional view in the X direction is shown in Figure 64F; a cross-sectional view in the Y direction is shown in Figure 64G. The PMOS H source 6411 is connected to the V+ power metal 6416 in the PMOS metal 1 layer through the P+ of the metal contact. The PMOS H drain connects 6420 to the PMOS G source in the PMOS silicon layer. The NMOS source 6412 is fully grounded through the N+ of the NMOS metal-1 contact, and is connected to the N- substrate metal line 6418 and the backplane N+ ground plane. The input A on PMOS metal-2 is connected to the PMOS and NMOS gate 6403 with the gate on the STI, which is then connected to the gate on the STI contact 6414. Use NMOS Metal-2 6415 to connect all NMOS Drains to NMOS A Drain and PMOS A Drain 6413, P+ to N+, PMOS Metal-2 contact 6417 (connected to output Y). Figure 64G illustrates the use of vertical PMOS transistors to closely connect stacked sources and drains and form the compressed region wafer shown in Figure 64E. Transistor Insulation Oxidation Object 6400 is shown in the figure.

從而可建設CMOS電路,其中在兩個矽層上建設各種電路晶片,使電路面積更小,電晶體佈線內部和之間距離更短。由於佈線成為功耗和速度之主導因素,面積越小之壓縮電路可使終端組件之功耗更低、速度更快。 This allows the construction of CMOS circuits, in which various circuit chips are constructed on two silicon layers, resulting in smaller circuit areas and shorter distances within and between transistor wiring. Since wiring becomes the dominant factor in power consumption and speed, smaller area compression circuits can lead to lower power consumption and faster speed of end components.

技藝一般之人會認為本檔中利用典型之邏輯柵極和記憶體晶片作為代表電路介紹了多個不同之工藝流程。技藝高超之人會進一步考量在各個設定中使用哪個流程。可能會產生模組庫,具備設定過程中所需之所有必要之邏輯功能,這樣不管是在單獨之設定中還是採取相同流程之其他設定中都可以很容易地再次使用這些晶片。技藝高超之人還會在既定之設定中採用多種不同之設定風格。例如,可採用高度相同之晶片(本行業中常說之標準晶片)建設邏輯晶片模組庫。或者,可生成在較長之連續電晶體插接條中使用之模組庫,這就是技術中常說之柵控陣列。在另外一個案例中,可建設晶片模組庫,在手工或自定義設定中使用,這種做法在本技術中也很常見。例如,在另外一個備用案例中,在特定之設定中可使用為設定方法量身之邏輯晶片模組庫,這是個設定選擇之問題。如果模組庫用在3D IC之相同層上,選擇之模組庫可使用同樣之工藝流程。3D IC之不同層次上可使用不同之工藝流程,在單獨之設定中可為各個層次選擇一個或多個晶片模組庫。 Those of ordinary skill will think that this document introduces several different process flows using typical logic gates and memory chips as representative circuits. A skilled person will further consider which process to use in each setting. It is possible to generate a library of modules with all the necessary logic functions required in the setup so that the chips can be easily reused, either in a single setup or in other setups following the same process. A highly skilled person will also use many different setting styles in a given setting. For example, chips of the same height (standard chips often referred to in this industry) can be used to build a library of logic chip modules. Alternatively, a library of modules can be generated for use in longer continuous strips of transistors, known in the art as gated arrays. In another case, a chip module library can be built for use in manual or custom settings, which is also common in this technology. For example, in another alternate case, a library of logic chip modules tailored to the method of implementation may be used in a particular configuration, and this is a matter of configuration choice. If the module library is used on the same layer of the 3D IC, the selected module library can use the same process flow. Different process flows can be used at different levels of 3D IC, and one or more chip module libraries can be selected for each level in a separate setting.

本技術中還常使用電腦程式產品。這些產品存儲在電腦可讀取介質上,在資料處理系統中使用,可使設定過程 自動化,通俗點說就是電腦輔助設定(CAD)軟體。技藝一般之人會考量採用與CAD軟體相容之方式設定晶片模組庫之優點。 Computer program products are also commonly used in the art. These products are stored on computer-readable media and used in data processing systems to enable the setting process Automation, in layman's terms, is computer-aided setting (CAD) software. People with average skills will consider the advantages of setting the chip module library in a way compatible with CAD software.

技藝一般之人會認識到在設定過程中使用之一種或多種工藝流程或生成I/O晶片之模組庫、模仿功能晶片、各種類型之完整存儲塊以及其他之電路,這些模組庫應與CAD軟體相容。閱讀本說明書之後,很多其他之用途和案例對技藝高超之人有啟發作用。因此,本僅受限於附加之權利要求。 Those of ordinary skill will recognize that one or more process flows or libraries of modules that generate I/O chips, analog function chips, complete memory blocks of various types, and other circuits used in the setup process should be used in conjunction with Compatible with CAD software. After reading this manual, many other uses and examples will inspire the skilled person. Accordingly, the invention is limited only by the appended claims.

此外,如上文所述,如果在一層或多層薄薄之矽層上建設了電路晶片,並且享有密集、垂直之直通矽互聯層,利用這種密集之3D技術之金屬化層之設定方案可進行完善,具體如下。圖59展示了矽積體電路金屬化設定方案之現有技術。傳統之電晶體矽層5902透過接點5904被連接到第一層金屬層5910上。這種互聯接點對和金屬線之尺寸通常處於該技術流程節點之光刻和蝕刻能力之最小線分辨力。它通常被稱為“1X”設定規則金屬層。一般情況下,下一層金屬層也遵循“1X”設定規則、金屬線5912、5905下方之通孔和5906上方之通孔(將金屬5912連接到5910或5914上都可以)。接著,接下來之幾層金屬層通常做成最小光刻和蝕刻能力之兩倍,被稱為“2X”金屬層。其金屬更厚,具有更高之載流能力。可採用圖59中之與通孔5907匹配之金屬線5914以及與通孔5908匹配之金屬線5916對此進行說明。因此,5918之金屬通孔(帶5909)和5920(帶 黏結焊盤開口5922)代表“4X”金屬化層,其中平面和厚度尺寸比2X和1X層更大、更厚。1X或2X或4X層之精確數量常常會變化,主要取決於互連層之需求和其他之要求;然而,一般之流程是金屬線、金屬間隔之尺寸越大,作為金屬層之通孔離矽電晶體越遠,越靠近黏結焊盤。 In addition, as mentioned above, if the circuit chip is built on one or more thin silicon layers, and has a dense, vertical through-silicon interconnection layer, the metallization layer configuration using this dense 3D technology can be carried out. perfect, as follows. Figure 59 shows a prior art silicon IC metallization setup scheme. The conventional transistor silicon layer 5902 is connected to the first metal layer 5910 through contacts 5904 . The dimensions of such interconnecting contact pairs and metal lines are typically at the minimum line resolution of the lithography and etch capabilities of the technology process node. It is often referred to as the "1X" set rule metal layer. In general, the next metal layer also follows the "1X" set rule, vias below metal lines 5912, 5905, and vias above 5906 (connecting metal 5912 to 5910 or 5914 is fine). Next, the next few metal layers are usually made twice the minimum lithography and etch capability, referred to as "2X" metal layers. The metal is thicker and has a higher current carrying capacity. This can be illustrated using the metal line 5914 matching the via 5907 and the metal line 5916 matching the via 5908 in FIG. 59 . Therefore, the 5918 metal through hole (with 5909) and 5920 (with Bond pad openings 5922) represent "4X" metallization layers, where the planar and thickness dimensions are larger and thicker than the 2X and 1X layers. The exact number of 1X or 2X or 4X layers often changes, mainly depending on the needs of the interconnection layer and other requirements; however, the general process is that the larger the size of the metal line and metal space, the via holes as the metal layer are separated from the silicon The farther away the transistor is, the closer it is to the bond pad.

如圖60所示,可對3D線路之金屬化層設定方案進行改良。第一個單晶矽或多晶矽組件層6024可被理解為上述3D模組庫晶片之NMOS矽電晶體層,也可理解為傳統之邏輯電晶體矽基板或層。採用接點6010將“1X”金屬層6020和6019連接到矽電晶體,採用通孔6008和6009使其互相連接或者連接到金屬線6018上。透過通孔6007將2X層與金屬6018相連,透過通孔6006將2X層與金屬6017相連。透過通孔6005將4X金屬層6016與同在4X層上之金屬6015相連。然而,現在通孔6004是依照2X設定規則建設的,使金屬線6014也處於2X層。金屬線6013和通孔6003也符合2X設定規則,滿足其厚度要求。通孔6002和6001與金屬線6012和6011相連,符合1X最低設定規則之尺寸和厚度要求。接下來,依照1X最低設定規則建設所述PMOS層切矽6022之矽通孔6000,並提供頂層之最高密度。1X或2X或4X層之精確數量常常會變化,主要取決於電路面積和載流金屬化設定規則和設定折衷。層切上層電晶體層6022可以採取本文說明之任意一種低溫組件。 As shown in FIG. 60 , the scheme for setting the metallization layer of the 3D circuit can be improved. The first single crystal silicon or polycrystalline silicon component layer 6024 can be understood as the NMOS silicon transistor layer of the above-mentioned 3D module library chip, and can also be understood as a traditional logic transistor silicon substrate or layer. The "1X" metal layers 6020 and 6019 are connected to the silicon transistor using contacts 6010 and connected to each other or to metal line 6018 using vias 6008 and 6009 . The 2X layer is connected to the metal 6018 through the via 6007 , and the 2X layer is connected to the metal 6017 through the via 6006 . Vias 6005 connect 4X metal layer 6016 to metal 6015 also on 4X layer. Now, however, via 6004 is built according to the 2X set rule, so that metal line 6014 is also at 2X layer. The metal line 6013 and the via hole 6003 also comply with the 2X setting rule and meet their thickness requirements. The via holes 6002 and 6001 are connected to the metal wires 6012 and 6011, which meet the size and thickness requirements of the 1X minimum setting rule. Next, construct the TSVs 6000 of the PMOS layer cut silicon 6022 according to the 1X minimum setting rule, and provide the highest density of the top layer. The exact number of 1X or 2X or 4X layers will often vary, depending primarily on circuit area and current-carrying metallization set rules and set tradeoffs. The layer-cut upper transistor layer 6022 can adopt any low-temperature device described herein.

如果切出層無法透過較短波長光,因此也就無法檢測到對準標誌以及分辨力為一納米或數十納米之圖像,原因 在於切出層或其載子或基板座之厚度。可使用紅外(IR)光學和成像技術進行對準。然而,其分辨力和對準能力可能不能令人滿意。在本案例中,在層切流程中生成了對準視窗,可以使用較短波長光進行對準。 If the cut-out layer cannot pass through shorter wavelength light, it is impossible to detect alignment marks and images with a resolution of one nanometer or tens of nanometers. It lies in the thickness of the cut-out layer or its carrier or substrate base. Alignment can be performed using infrared (IR) optics and imaging techniques. However, its resolution and alignment capabilities may not be satisfactory. In this case, an alignment window is created during the slice process, allowing alignment using shorter wavelength light.

如圖111A所示,在普通工藝流程開始要使用施主晶圓11100(使用透過澱積方式、離子注入和退火、氧化、類晶生長、同時使用上述方法、或者其他半導體加工步驟和方法形成之導電層11102、半導電材料或絕緣材料進行預加工)。在層11102成型之前或之後也可採取層切分界平面(例如,氫注入切割平面)對施主晶圓11100進行預加工,或者採取前文所述之方法使其變薄。首先對對準視窗11130進行光刻和電漿體/反應式離子蝕刻,然後再填充較短波長之透明材料(例如二氧化矽),並透過化學-機械打磨(CMP)使其平面化。或者,可採取化學-機械打磨(CMP)方法使施主晶圓進一步變薄。對準視窗11130之施主晶圓之尺寸和佈局取決於在將施主晶圓11100黏結到受主晶圓11110上時所使用之對準計畫之最大未對準公差,以及受主晶圓未對準標誌11190之佈局位置。可在層11102成型之前或之後對準視窗11130進行加工。受主晶圓11110可以為預加工之具有全功能電路之晶圓,或者是帶有預先切出層之晶圓,或者是空白載子或保持晶圓或者是其他類型之基板,也可以稱為目標晶圓。例如,受主晶圓11110和施主晶圓11100可以為單晶體矽晶圓或者絕緣襯底上之矽(SOI)晶圓或者絕緣上覆鍺(GeOI)晶圓。受主 晶圓11110金屬連接焊盤或插接條11180和受主晶圓對準標誌如圖所示。 As shown in FIG. 111A , a donor wafer 11100 is used at the beginning of the normal process flow (using a conductive wafer 11100 formed by deposition, ion implantation and annealing, oxidation, crystal-like growth, simultaneously using the above methods, or other semiconductor processing steps and methods. layer 11102, semiconducting material or insulating material for preprocessing). The donor wafer 11100 can also be pre-processed with a layer cut boundary plane (eg, a hydrogen implant cut plane) before or after the formation of the layer 11102 , or thinned by the methods described above. The alignment window 11130 is first subjected to photolithography and plasma/reactive ion etching, then filled with a shorter wavelength transparent material (such as silicon dioxide) and planarized by chemical-mechanical polishing (CMP). Alternatively, chemical-mechanical polishing (CMP) can be used to further thin the donor wafer. The size and layout of the donor wafer that aligns the window 11130 depends on the maximum misalignment tolerance of the alignment plan used when bonding the donor wafer 11100 to the recipient wafer 11110, and the misalignment of the recipient wafer. The layout position of quasi-mark 11190. The alignment window 11130 can be machined before or after layer 11102 is formed. The acceptor wafer 11110 can be a pre-processed wafer with fully functional circuits, or a wafer with pre-cut layers, or a blank carrier or holding wafer or other types of substrates, also known as target wafer. For example, the acceptor wafer 11110 and the donor wafer 11100 may be single crystal silicon wafers or silicon-on-insulator (SOI) wafers or germanium-on-insulator (GeOI) wafers. recipient Wafer 11110 metal connection pads or straps 11180 and acceptor wafer alignment marks are shown.

施主晶圓11100和受主晶圓11110黏結表面11101和11111可透過澱積、打磨、電漿體或濕式化學處理方法用於晶圓黏結,促進晶圓與晶圓之間黏結成功。 The bonding surfaces 11101 and 11111 of the donor wafer 11100 and the acceptor wafer 11110 can be used for wafer bonding through deposition, grinding, plasma or wet chemical treatment to promote successful bonding between wafers.

如圖111B所示,帶層11102之施主晶圓11100、對準視窗11130和層切分界平面11199接下來可翻過來,具有較高之分辨力,然後對準到受主晶圓對準標誌11190並黏結到受主晶圓11110上。 As shown in FIG. 111B , the donor wafer 11100 with layers 11102 , alignment windows 11130 and layer cut interface planes 11199 can then be flipped over, with higher resolution, and aligned to the acceptor wafer alignment marks 11190 And bonded to the acceptor wafer 11110.

如圖1111C所示,在層切分界平面對施主晶圓11100進行切割或者使其變薄到層切分界平面,使施主晶圓11100之部分、對準視窗11130和預加工層11102對齊並黏結到受主晶圓11110。 As shown in FIG. 1111C , the donor wafer 11100 is diced at or thinned to the layer-cut interface plane so that portions of the donor wafer 11100 , alignment window 11130 and pre-process layer 11102 are aligned and bonded to Acceptor Wafer 11110.

如圖111D所示,施主晶圓剩餘部分11100可透過打磨或蝕刻之方式移除;可對切出層11102進一步加工,生成施主晶圓組件結構11150。施主晶圓組件結構11150與受主晶圓對準標誌11190精確對齊。對準視窗11130’可進一步加工至對準視窗區11131。這些施主晶圓組件結構11150可使用穿層過孔(TLV)11160,以連理方式將施主晶圓組件結構11150連接到受主晶圓金屬連接焊盤或插接條11180上。由於切出層11102很薄,厚度大約為200nm或更薄,可以很容易地將TLV加工成普通之金屬和金屬之間之通孔。上述TLV之直徑達到最高技術平,例如幾納米或者數十納米。 As shown in FIG. 111D , the remaining portion 11100 of the donor wafer can be removed by grinding or etching; the cut-out layer 11102 can be further processed to generate the donor wafer assembly structure 11150 . The donor wafer assembly structure 11150 is precisely aligned with the recipient wafer alignment marks 11190 . The alignment window 11130' can be further processed into the alignment window area 11131. These donor wafer assembly structures 11150 may use through layer vias (TLVs) 11160 to connect the donor wafer assembly structures 11150 to the acceptor wafer metal connection pads or straps 11180 in a bonded manner. Since the cut-out layer 11102 is very thin, about 200nm or less in thickness, the TLV can be easily processed into common metal-to-metal vias. The diameter of the above-mentioned TLV reaches the highest technical level, such as several nanometers or tens of nanometers.

圖111D中高密度TLV 11160或本檔中該類TLV之另外一種用法是透過傳熱將有源電路產生之熱量從一層傳到TLV連接之另外一層,例如從施主層和裝置結構傳到受主晶圓或基板上。也可使用TLV 11160將傳熱到晶片上之熱電製冷器、散熱器或其他之放熱組件上。可主要利用3D IC上之TLV部分進行電耦合,也可將其主要用於傳熱。在很多情況下,TLV既可用於電耦合也可用於傳熱。 Another use of the high-density TLV 11160 in Figure 111D or in this document is to transfer the heat generated by the active circuit from one layer to another layer connected to the TLV through heat transfer, such as from the donor layer and device structure to the acceptor crystal. round or on a substrate. The TLV 11160 can also be used to transfer heat to a thermoelectric cooler, heat sink, or other heat sink on the wafer. The TLV part on the 3D IC can be mainly used for electrical coupling, or it can be mainly used for heat transfer. In many cases, TLVs are used for both electrical coupling and heat transfer.

由於層都堆在3D IC上,單位面積之功率密度會增加。單晶矽之傳熱功能在150W/m-K時最弱。二氧化矽(現代矽積體電路中最常見之電絕緣體)在1.4W/m-K時傳熱功能最弱。如果3D IC堆疊層上不放有散熱器,則底部晶片或層(離散熱器最遠)對那個散熱器之傳熱功能最差,原因是從底層散發出來之熱量必須穿過其上方晶片或層之二氧化矽和矽。 Since the layers are stacked on the 3D IC, the power density per unit area will increase. The heat transfer function of monocrystalline silicon is the weakest at 150W/m-K. Silicon dioxide (the most common electrical insulator in modern silicon integrated circuits) has the weakest heat transfer function at 1.4W/m-K. If no heat sink is placed on the layer of the 3D IC stack, the bottom die or layer (furthest from the heat sink) has the worst heat transfer function to that heat sink, because the heat emitted from the bottom layer must pass through the die or layer above it. Layers of silicon dioxide and silicon.

如圖112A所示,散熱層11205在薄薄之二氧化矽層11203頂層澱積,而二氧化矽層在基板11202之互聯金屬化層11201之頂部表面上澱積。散熱層11205可包含電漿體增強化學氣相沉積類金剛石碳(PECVD DLC),其傳熱性為1000W/m-K,或者其他之傳熱材料,例如化學氣相沉積(CVD)石墨烯(5000W/m-K)或銅(400W/m-K)。散熱層5015之厚度大約在20納米至1微米之間。最理想之厚度範圍是50納米至100納米,絕緣體是散熱層11205導電率最理想之配件,能夠確保直通層通孔滿足設定規則規定之最小直徑。如果散熱層可導電,需要將TLV之開口適當 放大,使得非導電覆蓋層在TLV之導電芯澱積之前在TLV壁上澱積。或者,如果散熱層11205可導電,可對其進行掩蔽並蝕刻,為直通層通孔提供接合焊盤,並在焊盤周圍提供較大之用於傳熱之柵極。散熱層還可用作其上方或下方電路之接地平面或電源中繼線和接地母線。氧化層11204可發生澱積(也可將其平面化,以填充傳熱層中之間隙),以便為晶圓與晶圓氧化物之間之黏結做好準備。受主基板11214可包含基板11202、互聯金屬化層11201、薄薄的二氧化矽層11203、散熱層11205和氧化層11204。如前文所述,層切之後,在準備電晶體和電路(例如,無結型、RCAT、V形槽和雙極)成型之過程中,可使用晶圓大小之摻雜層加工施主晶圓基板11206。如使用注入法,可在注入之前生長或澱積遮罩氧化層11207,以確保在注入過程中矽免受污染,並為後期晶圓之間之黏合提供氧化層。透過氫離子注入、“離子切割”或前文所描述之其他方法可在施主晶圓基板11206中形成層切分界平面11299(圖中虛線部分)。如前文所討論之內容,在為電晶體成型做準備之過程中,施主晶圓11212可包含施主基板11206、層切分界平面11299、遮罩氧化層11207和其他層(未顯示)。如前文所述,施主晶圓11212和受主晶圓11214均用於晶圓黏合,並在低溫(低於400℃)下在氧化層11204和氧化層11207之表面黏合在一起。可透過切割或打磨或前文所述之工序(例如離子切割或其他方法)將層切分界平面11299上方之施主晶圓部分11206移除,從而形 成剩餘之切出層11206’。或者,可使用前文所述之方法先建設施主晶圓11212,例如使用取代柵極(未顯示)進行離子切割,再層切出至受主基板11214上。現在電晶體已全部或部分形成,並與前面形成之受主晶圓對準標誌(未顯示)和直通層通孔對齊。這樣,帶有集成散熱層之3D IC就建設好了。 As shown in FIG. 112A , a heat sink layer 11205 is deposited on top of a thin silicon dioxide layer 11203 which is deposited on the top surface of the interconnect metallization layer 11201 of the substrate 11202 . The heat dissipation layer 11205 may comprise plasma-enhanced chemical vapor deposition diamond-like carbon (PECVD DLC), whose thermal conductivity is 1000W/m-K, or other heat transfer materials, such as chemical vapor deposition (CVD) graphene (5000W/m-K) m-K) or copper (400W/m-K). The thickness of the heat dissipation layer 5015 is approximately between 20 nanometers and 1 micron. The ideal thickness range is 50nm to 100nm. The insulator is the most ideal accessory for the conductivity of the heat dissipation layer 11205, which can ensure that the through-layer through hole meets the minimum diameter specified by the set rules. If the heat dissipation layer is conductive, the opening of the TLV needs to be properly Scale up so that a non-conductive capping layer is deposited on the TLV walls before the deposition of the conductive core of the TLV. Alternatively, if the heat sink layer 11205 is conductive, it can be masked and etched to provide a bond pad for the TLV and provide a larger grid around the pad for heat transfer. The heat sink can also be used as a ground plane or as a power trunk and ground bus for circuits above or below it. An oxide layer 11204 may be deposited (and also planarized to fill gaps in the thermal transfer layer) in preparation for wafer-to-wafer oxide bonding. The acceptor substrate 11214 may include a substrate 11202 , an interconnect metallization layer 11201 , a thin silicon dioxide layer 11203 , a heat dissipation layer 11205 and an oxide layer 11204 . As previously mentioned, after layer dicing, the donor wafer substrate can be processed with wafer-sized doped layers in preparation for molding of transistors and circuits (e.g., junctionless, RCAT, V-groove, and bipolar) 11206. If implantation is used, a mask oxide layer 11207 can be grown or deposited prior to implantation to ensure that the silicon is free from contamination during the implantation process and to provide an oxide layer for later wafer-to-wafer bonding. Slicing boundary planes 11299 (dashed lines in the figure) can be formed in the donor wafer substrate 11206 by hydrogen ion implantation, "ion dicing" or other methods described above. As previously discussed, in preparation for transistor formation, donor wafer 11212 may include donor substrate 11206, layer cut interface plane 11299, mask oxide layer 11207, and other layers (not shown). As mentioned above, both the donor wafer 11212 and the acceptor wafer 11214 are used for wafer bonding, and are bonded together on the surfaces of the oxide layer 11204 and the oxide layer 11207 at low temperature (less than 400° C.). The portion of the donor wafer 11206 above the dicing interface plane 11299 may be removed by dicing or grinding or a process as previously described (eg, ion dicing or other methods) to form Become the remaining cut-out layer 11206'. Alternatively, the host wafer 11212 can be first constructed using the method described above, for example, using a replacement gate (not shown) for ion dicing, and then layer-cut out onto the acceptor substrate 11214 . The transistors are now fully or partially formed and aligned with the previously formed acceptor wafer alignment marks (not shown) and through-layer vias. In this way, a 3D IC with an integrated heat dissipation layer is constructed.

如圖113所示,一組電源柵極和接地柵極(例如底部電晶體電源柵極和接地柵極11307和頂部電晶體電源柵極和接地柵極11306)可透過直通層電源通孔和接地通孔11304連接在一起,並透過熱耦合方式連接到非導電散熱層11305上。如果散熱層是導電體,要麼它只能用作接地平面,要麼利用電源板和接地片在TLV之接合焊盤之間形成圖形。對電源柵極和接地柵極之密度以及電源柵極和接地柵極之直通層通孔進行設定,以提高3D IC堆疊層中所有電路之某些傳熱總熱阻。黏結氧化物11310、印刷電路板11300、封裝散熱層11325、底部電晶體層11302、頂部電晶體層11321和散熱器如圖所示。這樣,帶有集成散熱器、散熱層以及電源柵極和接地柵極之直通層通孔之3D IC就建設好了。 As shown in Figure 113, a set of power and ground gates (e.g. bottom transistor power and ground gate 11307 and top transistor power and ground gate 11306) can pass through layer power vias and ground The vias 11304 are connected together and connected to the non-conductive heat dissipation layer 11305 through thermal coupling. If the heat sink is a conductor, either it can only be used as a ground plane, or it can be patterned between the bonding pads of the TLV using the power plane and the ground pad. The density of power and ground gates and the through-layer vias of power and ground gates are set to increase some of the total thermal resistance of heat transfer for all circuits in the layers of the 3D IC stack. Bond oxide 11310, printed circuit board 11300, package heat sink layer 11325, bottom transistor layer 11302, top transistor layer 11321 and heat sink are shown. In this way, a 3D IC with an integrated heat sink, heat dissipation layer, and through-layer vias for power and ground gates is constructed.

如圖113B所示,在圖113A之3D IC結構之側壁上可形成導熱材料(例如PECVD DLC),從而形成側壁熱導體11360,可用於側壁之熱量排除。底部電晶體層電源柵極和接地柵極11307、頂部電晶體層電源柵極和接地柵極11306、直通層電源通孔和接地通孔11304、撒熱層 11305、黏結氧化物11310、印刷電路11300、封裝散熱層11325、底部電晶體層11302、頂部電晶體層11312和散熱器11330如圖所示。 As shown in FIG. 113B , a thermally conductive material (such as PECVD DLC) can be formed on the sidewall of the 3D IC structure in FIG. 113A , thereby forming a sidewall thermal conductor 11360 for heat removal from the sidewall. Bottom Transistor Layer Power and Ground Gates 11307, Top Transistor Layer Power and Ground Gates 11306, Thru Layer Power and Ground Vias 11304, Heat Spreading Layer 11305, bonding oxide 11310, printed circuit 11300, package heat sink layer 11325, bottom transistor layer 11302, top transistor layer 11312 and heat sink 11330 as shown.

每個電晶體獨立城型也促使使用矽之外之其他材料建設電晶體。例如,可用過直接層切或澱積和使用緩衝複合物(GaAs和InAlAs,起到緩衝矽和III-V晶格失配之作用)之方式在上述之一層或多層3D層上使用薄薄的III-V複合量子井溝槽(例如InGaAs和InSb)。這樣就形成了高遷移率電晶體,能夠單獨優化p和n溝槽之電晶體,這就解決了在同一個基板上同時加入n和p III-V電晶體之集成難題,也解決了在同一個基板上將II-V電晶體與傳統矽電晶體集成之難題。例如,第一層矽電晶體和金屬化層通常不能裸露在高於400℃之高溫下。III-V複合物、緩衝層和摻雜物所需之加工溫度通常要超過400℃之界限。透過使用前文所述以及圖14、圖20至圖29以及圖43至圖45中介紹之預澱積、摻雜、退火層施主晶圓成型和隨後之施主至受主晶圓層切技術,可在矽電晶體和電路頂部建設III-V電晶體和電路,不會損壞下方之矽電晶體和電路。此外,即使在將要集成之異質材料(例如矽和III-V複合物)中存在應力失配現象,也可以透過垂直處於異質材料層之間之氧化層或特殊緩衝層緩和應力失配現象。此外,這種方法還可以集成光電組件、通信組件以及透過傳統矽邏輯電晶體、存儲電晶體和矽電路加工之資料通路。除了矽之外,還可以使用鍺單獨建設各個電晶體層。 The individual shape of each transistor also encourages the use of materials other than silicon to construct transistors. For example, one or more of the above-mentioned 3D layers can be applied with a thin III-V composite quantum well trenches (eg InGaAs and InSb). In this way, a high-mobility transistor is formed, and the p- and n-groove transistors can be optimized separately, which solves the integration problem of adding n and p III-V transistors on the same substrate at the same time, and also solves the problem of adding n and p III-V transistors on the same substrate. The challenge of integrating II-V transistors with traditional silicon transistors on one substrate. For example, the first layer of silicon transistors and metallization layers usually cannot be exposed to high temperatures above 400°C. The processing temperatures required for III-V composites, buffer layers, and dopants typically exceed the 400°C limit. By using the pre-deposition, doping, annealing layer donor wafer shaping and subsequent donor-to-acceptor wafer layer dicing techniques described above and illustrated in Figures 14, 20-29, and 43-45, Build III-V transistors and circuits on top of silicon transistors and circuits without damaging the silicon transistors and circuits below. Furthermore, even if there is a stress mismatch in the heterogeneous materials to be integrated (such as silicon and III-V composites), it can be mitigated by an oxide layer or a special buffer layer vertically between the heterogeneous material layers. In addition, this method can also integrate optoelectronic components, communication components, and data paths through traditional silicon logic transistors, memory transistors, and silicon circuit processing. In addition to silicon, germanium can also be used to build individual transistor layers individually.

應當注意到,可在很多應用中使用這項3D IC技術。透過使用圖21至圖35中所述之技術,圖15至圖19中展示之各種結構建設在“基礎”上,可能位於主層或第一層或外殼層之下方。這些結構同樣也可以在“頂層”上製造,可能位於主層或第一層或外殼層之上方。 It should be noted that this 3D IC technology can be used in many applications. By using the techniques described in Figures 21-35, the various structures shown in Figures 15-19 are built on a "foundation", possibly under the main or first or shell layer. These structures can also be fabricated on a "top layer", possibly above the main or first or outer skin layer.

還應注意的是3D可編程系統,其邏輯構造大小由切割平鋪陣列之晶片決定,如圖36所示,可利用與圖14有關關於‘基礎’之‘單片積體電路’3D技術,或透過圖21所示之適用的‘尖端的’35技術,添加IO晶片或記憶晶片,如圖11所示。所以很多情況下利用TSV構造3D可編程系統更可取,也有時候利用‘基礎’或‘尖端的’技術更好些。 It should also be noted that for a 3D programmable system, the size of its logic structure is determined by dicing the chip of the tiled array, as shown in Figure 36, and the "monolithic integrated circuit" 3D technology related to the "basic" in Figure 14 can be used. Or through the applicable 'cutting edge' 35 technology shown in Figure 21, add IO chips or memory chips, as shown in Figure 11. So in many cases it is preferable to use TSVs to construct 3D programmable systems, and sometimes it is better to use 'basic' or 'cutting-edge' technologies.

本文中,如果基板晶片,傳輸晶片或供體晶片透過開裂和化學機械拋光變薄,這裏還有其他方法可用來使晶片變薄。例如,可利用硼植入和退火在矽基板上創造一層表面,使之變薄,從而產生一層潮濕之化學刻蝕阻止平面。幹刻蝕,如鹵氣糰粒束,可用來使矽基板變薄,接著用氧氣團簇使矽基板變得光滑。這些變薄技術可因工藝流程需要,為滿足合適厚度和表面光滑度,或單獨使用或綜合利用。 Here, if the substrate wafer, transfer wafer, or donor wafer is thinned through cleavage and chemical mechanical polishing, there are other methods that can be used to thin the wafer. For example, boron implantation and annealing can be used to create a surface on a silicon substrate that is thinned to produce a wet chemical etch stop plane. Dry etching, such as a cluster beam of halogen gas, can be used to thin the silicon substrate, followed by smoothing the silicon substrate with oxygen clusters. These thinning technologies can be used alone or comprehensively to meet the needs of the process flow to meet the appropriate thickness and surface smoothness.

圖9A透過9C舉例說明了一種3維-3D複合模具整合建設IC系統及利用穿矽過孔構造方法。圖9A舉例說明透過所有模具來建設一個總體跨模連接,使穿矽過孔保持繼續垂直。 9A through 9C exemplify a 3D-3D composite mold integrated construction method for IC systems and utilizing through-silicon vias. FIG. 9A illustrates the construction of an overall cross-die connection through all dies so that TSVs remain vertical.

圖9B舉例說明了類似大小之模具建設3D系統。圖9B 表明,穿矽過孔404在所有模具構造標準介面中處於同樣之相對位置。 Figure 9B illustrates a similarly sized mold building 3D system. Figure 9B It is shown that the TSVs 404 are in the same relative position in the standard interface of all mold constructions.

圖9C圖解了不同尺寸模具之3D系統。圖9C還說明了利用引線黏合連接所有與外部鏈結之IC系統3模具(three dies)?。 Fig. 9C illustrates a 3D system of molds of different sizes. FIG. 9C also illustrates the use of wire bonding to connect all IC system 3 dies (three dies) with external links? .

圖10A是美國當前技術,即專利7,337,425連續陣列晶片之示意圖。磁泡102表示連續陣列之循環區塊,連線104表示水平和垂直之潛在切割線。區塊102可能按照帶潛在切割線104-1之圖10B102-1或帶平行轉換器嵌條106之圖10C來構造,平行轉換器嵌條106是區塊102-2和潛在切割線104-2之組成部分。 FIG. 10A is a schematic diagram of the current technology in the United States, that is, the continuous array chip of patent 7,337,425. Bubbles 102 represent a continuous array of recurring blocks, and lines 104 represent potential horizontal and vertical cutting lines. Block 102 may be constructed according to Figure 10B102-1 with potential cut line 104-1 or Figure 10C with parallel converter fillet 106 that is block 102-2 and potential cut line 104-2 the components.

通常邏輯組件包含各種各樣數量眾多之邏輯組件,記憶體和I/O晶片。當前技術之連續陣列允許在同樣晶片外界定模具大小,由此邏輯組件也會相應變化,但邏輯組件,I/O晶片和記憶體間之三向比率很難變化。此外,記憶體類型多樣,例如有靜態隨機記憶體(SARM),動態隨機存取記憶體(DRAM),快閃記憶體等,I/O晶片也是形式多樣,例如平行轉換器。一些應用程式可能仍需要其他功能,如處理程式,數位訊號處理,類比功能等。 Usually logic components include a large number of various logic components, memory and I/O chips. The continuous array of current technology allows the die size to be determined outside the same die, so that the logic components will also change accordingly, but the three-way ratio between logic components, I/O chips and memory is difficult to change. In addition, there are various types of memory, such as static random access memory (SARM), dynamic random access memory (DRAM), flash memory, etc., and I/O chips are also in various forms, such as parallel converters. Some applications may still require other functions, such as processing programs, digital signal processing, analog functions, etc.

依照本項發明之案例,它可以採用一種不同之方法。不是試圖把這些功能融合在一個可編程模具上,因為這需要大量昂貴之掩模組,而是利用穿矽過孔來構造可配置系統。這項“積體電路和垂直整合打包”技術已成為美國專利6,322,903,並於2001年11月27日頒發給Oleg Siniaguine 和Sergey Savastiouk。 In the case of this invention, it can take a different approach. Instead of trying to combine these functions on one programmable die, which would require a large number of expensive mask sets, configurable systems are built using through-silicon vias. This "Integrated Circuit and Vertical Integration Packaging" technique has become US Patent 6,322,903, issued to Oleg Siniaguine on November 27, 2001 and Sergey Savastiouk.

依照本項發明之案例,可建議利用區塊之連續排列集中某一項或幾項功能。接著,在3D積體電路系統透過整合每一種區塊之期望數值來建設終端系統。 According to the case of this invention, it can be suggested to use the continuous arrangement of blocks to concentrate one or several functions. Then, build the end system by integrating the desired value of each block in 3D IC.

圖11A為一個晶片上之實際掩模示意圖,晶片包含可編程邏輯1100A指示之現場可編輯閘陣列區塊。晶片為可編程邏輯之連續陣列。1102為潛在切割線,用以支持在一個掩模組上建設不同之模具和邏輯。這種模具可用作圖12所示3D系統中1202A,1202B,1202C或1202D之基礎。作為本發明之一種替代物,這些模具可用來傳送大多數邏輯,所期望之記憶體和I/O晶片也可透過其他模具獲得,模具間透過穿矽過孔連接。應注意很多情況下並沒有鋼線,甚至在切割線108中從未用過。這種情況下,起碼為了邏輯模具,可以用專用掩模,依照所希望模具大小,透過連接未用過之潛在切割線來連接單個區塊。實際之切割線也可稱為幹線。 FIG. 11A is a schematic diagram of the actual mask on a wafer containing FPGA blocks indicated by programmable logic 1100A. A chip is a contiguous array of programmable logic. 1102 is a potential dicing line to support building different molds and logic on one mask set. Such a mold can be used as the basis for 1202A, 1202B, 1202C or 1202D in the 3D system shown in FIG. 12 . As an alternative to the present invention, these dies can be used to carry most of the logic, and the desired memory and I/O chips can also be obtained through other dies connected by through-silicon vias. It should be noted that steel wire is not present in many cases, or even never used in cutting wire 108 . In this case, at least for logic dies, individual blocks can be connected by connecting unused potential dicing lines with a dedicated mask, depending on the desired die size. The actual cutting line can also be called the main line.

應注意的是,在通常情況下晶片上之蝕刻是透過反復投射完成的,投射以“高品質之電子分步重複”方式而被稱之為晶片上之掩模。在很多情況下,分別考量循環區塊102間之分離更為可取,循環區塊102處於掩模影像與區塊之比對下,與2個投射有關。簡單描述就是使用晶片,但很多情況下一個晶片僅用一個掩模于區塊上。 It should be noted that etching on a wafer is typically done by repeated projections in a "high-quality electronic step-and-repeat" manner known as a mask on the wafer. In many cases, it is preferable to consider separately the separation between the cyclic blocks 102, which are under the mask image-to-block comparison, related to the 2 projections. A simple description is to use a wafer, but in many cases a wafer only uses one mask on a block.

循環區塊102形式多樣。對現場可編程閘陣列應用程式而言,設定區塊1101在0.5毫米到1毫米之間較好,這樣 由於未用之潛在切割線1102之原因,在終端組件大小和可接受相對區域損耗間可以保持良好平衡。 The loop block 102 takes various forms. For field programmable gate array applications, it is better to set the block 1101 between 0.5mm and 1mm, so that Due to the unused potential dicing lines 1102, a good balance can be maintained between terminal component size and acceptable relative area loss.

圖11A之均勻循環區塊有很多優點,可編程組件可透過切割晶片至需要之組件大小來構造。它還有助於終端組件作為完整的合成組件而不僅僅是單個區塊1101之集合體。圖36表示一個帶有潛在切割線3602且承載3601區塊排列之晶片,沿著實際切割線3612被切割,從而構造一個3x3區塊之終端組件3611。終端組件3611受實際切割線3612制約。 The uniform cycle block of FIG. 11A has many advantages. Programmable devices can be constructed by dicing the wafer to the required device size. It also facilitates terminal components as complete composite components rather than just collections of individual blocks 1101 . Figure 36 shows a wafer with potential dicing lines 3602 carrying 3601 arrays of blocks, diced along actual dicing lines 3612 to construct a terminal assembly 3611 of 3x3 blocks. Termination assembly 3611 is constrained by actual cutting line 3612 .

圖37是終端組件3611之示意圖,3611包含9個3701區塊,例如3601。每個區塊3701含有一個很小之微控制晶片-MCU3702。此控制晶片有通用之架構,例如8051,有自己的程式記憶體和資料記憶體。每個區塊上之微控制晶片將憑藉其程式功能和組件正確操作所需之設定初值來寄存現場可編程閘陣列區塊3701。它們相互連接是為了按照優先順序由其區塊之西面或南面來控制。例如,MCU3702-11將由MCU 3702-01控制。MCU 3702-01之西面沒有MCU,因此由3702-00南面之MCU控制。相應的,位於西南角之MCU 3702-00沒有區塊MCU來控制它,它就是終端組件之主控制晶片。 FIG. 37 is a schematic diagram of a terminal component 3611, and 3611 includes nine blocks 3701, such as 3601. Each block 3701 contains a very small microcontroller chip - MCU3702. This control chip has a common architecture, such as 8051, with its own program memory and data memory. The microcontroller chip on each block will register the FPGA block 3701 with its programmed functions and initial settings required for the correct operation of the components. They are connected to each other in order to be controlled by the west or south of their blocks in order of preference. For example, MCU3702-11 will be controlled by MCU 3702-01. There is no MCU to the west of MCU 3702-01, so it is controlled by the MCU to the south of 3702-00. Correspondingly, the MCU 3702-00 located in the southwest corner has no block MCU to control it, it is the main control chip of the terminal components.

圖38說明了一個簡單之控制連接,它利用稍微改進之聯合測試行動組--基於MCU架構-支援這種區塊方式。每個MCU都有兩個時間延遲集成輸入口(TDI),組件上之TDI3816在西側,而MCU上之TDIb 3814在南側。只要西側 TDI3816之輸入是開啟的,它就是控制晶片,否則南側之TDIb 3814就是控制晶片。在本示意圖中,位於西南角之3800區塊將成為主控者,它所控制之輸入3802會用來控制終端組件,並透過MCU3800傳到其他區塊。在圖38之結構示意圖中,終端組件3611之輸出口由位於東北角3820區塊之MCU連接起來,3820位於3822之測試資料輸出處。這些MCU及其連接會用來寄存終端組件功能,進行初始化和測試,調試,制訂時刻,及其它所希望之功能等。一旦終端組件完成了其設定和其他控制或初始化功能如測試或調試等,這些MCU可作為用戶功能使用,成為終端組件操作之一部分。 Figure 38 illustrates a simple control connection that supports this block approach with a slightly modified joint test action set - based on the MCU architecture. Each MCU has two Time Delay Integrated Inputs (TDIs), the TDI3816 on the component is on the west side and the TDIb 3814 on the MCU is on the south side. as long as the west side The input of TDI3816 is open, it is the control chip, otherwise the TDIb 3814 on the south side is the control chip. In this schematic diagram, the block 3800 located in the southwest corner will be the master controller, and the input 3802 controlled by it will be used to control the terminal components and be transmitted to other blocks through the MCU3800. In the structural schematic diagram of FIG. 38 , the output port of the terminal component 3611 is connected with the MCU located in block 3820 in the northeast corner, and 3820 is located at the test data output of block 3822 . These MCUs and their connections will be used to register terminal component functions, perform initialization and testing, debugging, setting time, and other desired functions. Once the end unit has completed its setup and other control or initialization functions such as testing or debugging, these MCUs can be used as user functions as part of the end unit operation.

構造帶有MCUS之平鋪現場可編程閘陣列(FPGA)之另一個優點在於,它能構造帶有嵌入式可編程閘陣列功能之系統級晶片。一個單一區塊3601可利用穿矽過孔-TSV連接到一個系統級晶片上,因此產生了獨立之嵌入式可編程閘陣列功能。 Another advantage of building a tiled field programmable gate array (FPGA) with MCUS is that it enables building a system-on-chip with embedded programmable gate array functionality. A single block 3601 can be connected to a system-on-chip using through-silicon vias - TSVs, thus creating a standalone embedded programmable gate array function.

很明顯,同樣方案經改進後,用東/北(或其他正交方向組合)方向可用來有效地編寫相同之優先方案。 Obviously, the same scheme can be modified to use east/north (or other combination of orthogonal directions) directions to effectively program the same priority scheme.

圖11B是一個晶片上之掩模位置替代示意圖,晶片由結構化專用積體電路區塊(ASIC)1100B組成。這種晶片可能是一種可配置邏輯晶片之連續排列。1102是潛在之切割線,用來支援構造各種模具和邏輯晶片。這種模具可用作圖12中3D系統1202A,1202B,1202C或1202D之基礎。 FIG. 11B is an alternate schematic diagram of mask locations on a wafer consisting of structured application specific integrated circuit blocks (ASICs) 1100B. Such a chip may be a contiguous array of configurable logic chips. 1102 is a potential dicing line to support the construction of various dies and logic chips. Such molds can be used as the basis for 3D systems 1202A, 1202B, 1202C or 1202D in FIG. 12 .

圖11C是一個晶片上之另一掩模位置示意圖,晶片由 隨機存取記憶體(RAM)1100C區塊組成。晶片可能是一個呈連續陣列之記憶體。晶片之外之模具方塊可能是3D合成系統之存儲模具組件。它可能包含一個抗熔存儲層或其他形式之配置技術,從而起到可配置存儲模具之作用。它有可能透過多次記憶體連接而得以建設,即透過多次連接穿矽過孔到可配置模具,模具在可配置系統中可用來配置存儲模具之原始記憶體,以達到其預期功能。 Figure 11C is a schematic diagram of another mask position on a wafer formed by The random access memory (RAM) is composed of 1100C blocks. A chip may be a memory in a contiguous array. Mold blocks other than wafers may be storage mold components for 3D compositing systems. It may contain an antifuse memory layer or other form of configuration technology to act as a configurable memory die. It is possible to build through multiple memory connections, that is, through multiple connections through silicon vias to a configurable die, which can be used to configure the original memory of the storage die in a configurable system to achieve its intended function.

圖11D是一個晶片上之另一掩模位置示意圖,晶片由動態隨機記憶體1100D區塊組成。晶片可能是一個呈連續陣列之動態隨機記憶體。 FIG. 11D is a schematic diagram of another mask position on a wafer composed of DRAM 1100D blocks. The chip may be a continuous array of DRAM.

圖11E是一個晶片上之另一掩模位置示意圖,晶片由微處理器區塊或微控制器核心1100E組成。晶片可能是一個呈連續陣列之處理器。 FIG. 11E is a schematic diagram of another mask location on a wafer consisting of microprocessor blocks or microcontroller cores 1100E. A chip may be a contiguous array of processors.

圖11F是一個晶片上之另一掩模位置示意圖,晶片由I/O晶片區塊1100F組成,包含成組之平行轉換器(SerDes)。晶片可能是一個呈連續區塊狀之I/O晶片。晶片之外之模具方塊可能是3D合成系統之I/O晶片模具組件。它可能包含一個抗熔存儲層或其他形式之配置技術如靜態隨機記憶體,來設定可配置I/O模具之I/O晶片,從而發揮它們在可配置系統中之作用。它有可能透過多次I/O連接而得以建設,即透過多次連接穿矽過孔到可配置模具,模具在可配置系統中可用來配置I/O模具之原始I/O晶片,以達到其預期功能。 FIG. 11F is a schematic diagram of another mask location on a wafer consisting of I/O wafer blocks 1100F, including groups of parallel switches (SerDes). A chip may be a continuous block of I/O chips. The mold block other than the wafer may be the I/O wafer mold assembly of the 3D compositing system. It may contain an antifuse layer or other forms of configuration technology such as SRAM to configure the I/O chips of the configurable I/O dies so that they function in a configurable system. It is possible to build through multiple I/O connections, that is, through multiple connections through silicon vias to a configurable die, which in a configurable system can be used to configure the original I/O die of the I/O die to achieve its intended function.

I/O電路是很好的例子,它有利於利用舊版本開啟程 式。通常程式驅動器是靜態隨機記憶體和邏輯電路。它經常花很長時間才能發揮出與I/O電路,平行轉換器電路,鎖相環電路(PLL),及其它線性函數相關之類比功能。除此外,用更小之電晶體來發揮邏輯功能也有好處,I/O晶片可能需要更強之驅動和相對較大之電晶體。因此,採用老程式可能更划算,因為老程式晶片花費少而功能有效性不減。 The I/O circuit is a good example, it is beneficial to use the old version to open the program Mode. Usually program drivers are SRAM and logic circuits. It often takes a long time to perform analog functions related to I/O circuits, parallel converter circuits, phase-locked loop circuits (PLL), and other linear functions. In addition, there are benefits to using smaller transistors for logic functions. I/O chips may require stronger drivers and relatively larger transistors. Therefore, it may be more cost-effective to adopt the old code, because the chip of the old code costs less without reducing the functional effectiveness.

另外一項功能是它可能對在3D系統中取出可編程邏輯模具及進入其他模具有利,它透過穿矽過孔連接,可能是時鐘電路及其相關之鎖相環路(PLL),動態連接(DLL)電路和控制電路等。鎖相環路和分佈。這些電路經常在區域使用,也可能鑒於噪音產生而要求較高。在很多情況下它們可以利用舊程式而得以有效實施。時鐘樹和配電線路可能包含在I/O模具中。而透過穿矽過孔(TSVs)或光纖手段,時鐘訊號可以轉移到可編程模具上。模具之間透過光纖手段轉移資料之技術已作為美國專利6052498頒發給英代爾公司。 Another feature is that it may be beneficial to take out the programmable logic die and enter other dies in the 3D system. It is connected through silicon vias, which may be the clock circuit and its associated phase-locked loop (PLL). Dynamic connection ( DLL) circuit and control circuit, etc. PLL and distribution. These circuits are frequently used in areas and may also be demanding due to noise generation. In many cases they can be effectively implemented using legacy procedures. Clock trees and power distribution lines may be included on the I/O die. And through silicon vias (TSVs) or optical fiber means, the clock signal can be transferred to the programmable die. The technology of transferring data between molds through optical fiber has been issued to Intel Corporation as US Patent 6052498.

作為一種選擇,也能利用光纖時鐘分佈器。這裏有不少新技術可用來在矽或其他基板上構造光纖嚮導。光纖時鐘分佈器可用來使時鐘訊號分佈使用之能源最小化,降低數位系統之失真和雜訊。在同一模具上,與先前技術之帶有邏輯晶片之集成光纖時鐘分佈器相比,光纖時鐘可在不同模具上建設,可透過穿矽過孔或光纖手段與數位模具連接,使之非常實用。 As an option, fiber optic clock distributors can also be utilized. There are a number of new technologies available for fabricating fiber guides on silicon or other substrates. Fiber optic clock distributors can be used to minimize the energy used for clock signal distribution and reduce distortion and noise in digital systems. On the same mold, compared with the integrated optical fiber clock distributor with logic chips in the prior art, the optical fiber clock can be built on different molds, and can be connected to digital molds through silicon vias or optical fiber, making it very practical.

作為另一種選擇,光纖時鐘分配輔助線和一些潛在支援性電子設備,透過利用圖14和20描述之存儲層轉移和智慧切割法之集合,例如可以實現由光訊號到電子訊號之轉變。光纖時鐘分配輔助線和一些潛在之支援性電子設備可首先在晶片1402之“基礎”上建設,接著薄晶片1404利用“智慧切割”可實現轉變,因此所有以下初級電路之建設會接著進行。光纖時鐘分配輔助線和支援性電子設備能在存儲層1404電晶體之處理過程中經得起高溫。 Alternatively, fiber optic clock distribution auxiliary lines and potentially some supporting electronics, such as optical to electronic signal conversion, can be achieved by utilizing a combination of storage layer migration and smart slicing as described in FIGS. 14 and 20 . Fiber optic clock distribution auxiliary lines and some potential supporting electronics can first be built on the "base" of chip 1402, then the thin chip 1404 can be transformed using "smart dicing", so the construction of all the following primary circuits will follow. The fiber optic clock distribution auxiliary lines and supporting electronics can withstand high temperatures during the processing of the storage layer 1404 transistors.

與圖20有關的,光導和合適之半導體結構(稍後會在上面處理支援性電子設備)要在存儲層2019上提前設立。利用“智慧切割”流,它可以轉移到晶片808上做完全處理。為了“智慧切割”需要,光導應能經得起離子2008注入,而支援性電子設備在循環中會終結,這一情況與圖21到圖35,圖39到94相似。這意味著時鐘訊號之登陸目標需要容納約1微米之轉向存儲層2004之位移來做預加工-初級電路和上層808。在很多設定中這種位移是可以接受的。作為一種選擇,支援性電子設備之基座會在存儲層2019上預製,存儲層和支援性電子設備之最終循環一起轉移後,光導才得以建設,這一情況與圖21到圖35,圖39到94相似。另一種選擇是透過利用圖21到圖35,圖39到94相似之循環,在加工完晶片後組裝支援性電子設備。接著可利用支援性電子設備上之存儲層轉移在低溫下來建設光波導器。 In relation to FIG. 20 , light guides and suitable semiconductor structures (supporting electronics will be dealt with later on) are pre-established on storage layer 2019 . Using the "smart dicing" flow, it can be transferred to wafer 808 for full processing. For "smart cutting" needs, the light guide should be able to withstand ion 2008 implantation, while the supporting electronics will end up in the cycle, this situation is similar to Figs. 21 to 35, and Figs. 39 to 94. This means that the landing target of the clock signal needs to accommodate a shift of about 1 micron towards the memory layer 2004 for preprocessing - primary circuit and upper layer 808 . This displacement is acceptable in many settings. As an option, the base of the supporting electronics will be prefabricated on the storage layer 2019, and the storage layer and the final loop of the supporting electronics will be transferred before the light guide can be constructed. to 94 similar. Another option is to assemble the supporting electronics after the wafer has been processed by using a similar cycle of Figures 21 to 35, Figures 39 to 94. The optical waveguide can then be constructed at low temperature using the transfer of the memory layer on the supporting electronics.

正因為晶片之這些功能,才能支援大容量之非專利產 品生產。與樂高積木相似,很多不同之可配置系統可以用各種各樣之邏輯記憶體和I/O晶片來建設。除了圖11A展示之替代方案外,圖11F也有很多功能可以創建併合並到3D可配置系統中。如圖像感測器,類比,資料獲取功能,光電組件,非易失性記憶體等。 It is precisely because of these functions of the chip that it can support large-capacity non-patented products product production. Similar to Lego bricks, many different configurable systems can be built with a variety of logic memory and I/O chips. In addition to the alternatives shown in Fig. 11A, Fig. 11F also has many functions that can be created and incorporated into a 3D configurable system. Such as image sensor, analog, data acquisition function, optoelectronic components, non-volatile memory, etc.

3D系統採用穿矽過孔後之另一項功能是功率調節。在很多情況下,它可以關閉積體電路不運作狀態下之部分電源。當外部模具之電源電壓可能高時,利用穿矽過孔連接(TSVs)之外部模具之功率控制分佈器是有好處的,因為它使用了舊程式。電源電壓高可以使受控模具之功率分配更容易,更好控制。 Another function of the 3D system after adopting TSV is power regulation. In many cases, it can shut down part of the power of the integrated circuit when it is not in operation. When the power supply voltage of the external die may be high, it is beneficial to use the power control distributor of the external die with through-silicon vias (TSVs), because it uses the old formula. High power supply voltage can make the power distribution of the controlled mold easier and better controlled.

可配置系統之部件可由一個或多個供應商建設,供應商應就標準具體介面允許模具混合與匹配方面達成一致。 Components of a configurable system may be built by one or more suppliers, and the suppliers shall agree on standard specific interfaces that allow mixing and matching of molds.

可以為一般市場需求或顧客特別需要定做3D可編程系統。 3D programmable systems can be customized for general market needs or special needs of customers.

本專利案例之另外一個優點是它可以與不同之程式混合匹配。利用前沿技術程式之記憶體是有好處,但可以透過成熟技術(如上面討論之)之舊程式使用I/O晶片及類比功能模具。 Another advantage of this patent case is that it can be mixed and matched with different programs. There are advantages to using memory for leading-edge technology programs, but I/O chips and analog function dies can be used by older programs of mature technology (as discussed above).

圖12A至圖12E說明了積體電路系統,是3D系統內及模具圖形中積體電路系統或帶多種模具選擇之可配置系統之示意圖。圖12E側面展示了3D結構。少數幾個模具如1204E,1206E,1208E被放置在同一基礎1202E上,這使相對更小之模具可以放置在同一個母模上。如模具1204E可 能平行轉換器模具,而模具1206E可能是模擬資料獲取模具。在不同晶片上利用不同之程式組合這些模具比在一個系統上合成它們要好。模具相對較小時,要把它們並排放置(如圖12E)而不是一個摞一個地層疊(圖12A-D)放置。 Figures 12A-12E illustrate an integrated circuit system, which is a schematic view of an integrated circuit system in a 3D system and in die graphics or a configurable system with multiple die options. Figure 12E shows the 3D structure sideways. A small number of molds such as 1204E, 1206E, 1208E are placed on the same base 1202E, which allows relatively smaller molds to be placed on the same master mold. Such as mold 1204E can be Parallel converter dies can be used, and die 1206E may be an analog data acquisition die. Combining these dies with different programs on different wafers is better than synthesizing them on one system. When the molds are relatively small, they should be placed side by side (Fig. 12E) rather than stacked on top of each other (Fig. 12A-D).

穿矽過孔技術在不斷改進。在早期,過孔之直徑是10微米,現在已發展到不到直徑不到1微米。不過,利用這一技術在模具中水平連接之密度仍然比垂直連接之密度大很多。 Through silicon via technology is constantly improving. In the early days, the diameter of the via hole was 10 microns, but now it has been developed to less than 1 micron in diameter. However, the density of horizontal connections in the die using this technique is still much higher than the density of vertical connections.

本發明之另外一種用途是邏輯記憶體部分被分解為多個模具,模具大小相等,可集成到一個3D可配置系統中。同樣的,也可以把記憶體劃分為多個模具,其他功能也可如此。 Another application of the present invention is that the logical memory part is decomposed into multiple dies, the dies are equal in size, and can be integrated into a 3D configurable system. Likewise, memory can be divided into multiple dies, as can other functions.

關於3D合成之最新進展表明了,晶片結合及切割這些結合晶片之有效方式。這種組配方式會形成如圖12A或圖12D之模具結構。對3D組配技術來說,有不同大小之模具或許更好。而且,將邏輯功能分解到垂直合成之模具裏可用來降低重負荷電線之平均長度,如時鐘訊號,資料匯流排,轉而這些組件會提高性能。 Recent advances in 3D synthesis have demonstrated efficient ways of bonding wafers and dicing these bonded wafers. This combination will form a mold structure as shown in Figure 12A or Figure 12D. For 3D assembly technology, it may be better to have molds of different sizes. Also, decomposing logic functions into vertically synthesized dies can be used to reduce the average length of heavy-duty wires, such as clock signals, and data busses, which in turn will improve performance.

本項發明之另一變化是,連續陣列經改編後(件圖10和11),用於通用邏輯組件甚至3D積體電路系統。對此先進之組件設定來說,需考量蝕刻之局限性。因此,規則結構是合適之選擇,各存儲層可以最適宜之樣式建設,多數情況下是每次一個方位。除此外,高度垂直連接之3D積體 電路系統可透過分離邏輯記憶體和I/O晶片到專用存儲層來完成有效建設。對僅有邏輯存儲層而言,其結構如圖76和圖78所示,可以充分利用,如圖84所闡釋。這樣,循環邏輯模式8402可能會組合為完全之掩模。圖84A闡明了圖78B邏輯晶片之一個循環模式,此模式循環8x12次。圖84B闡明了統一邏輯循環更多次,至填滿一個掩模。用以建設邏輯範圍之多種面模可用以3D積體電路之多重邏輯存儲層及多重積體電路。這種循環結構可包含邏輯記憶體P和N電晶體,及其相應之接觸層,甚至是連接基礎層之著陸帶。緊接著這些邏輯範圍之互聯層,或依設定自定或部分自定,全憑設定方法。自定之金屬互聯可以使邏輯範圍在切割線區域保持不用。也可用一個切割線面模來蝕刻切割線8404中未用之電晶體,如圖84C所示。 Another variation of the present invention is that the serial array is adapted (FIGS. 10 and 11) for use in general logic components or even 3D ICs. For this advanced device setup, the limitations of etching need to be considered. Therefore, a regular structure is a suitable choice, and each storage layer can be constructed in the most suitable pattern, in most cases, one orientation at a time. In addition, highly vertically connected 3D volumes Circuitry can be efficiently built by separating logic memory and I/O chips into dedicated memory layers. For only logical storage layers, the structure shown in Figure 76 and Figure 78 can be fully utilized, as illustrated in Figure 84. Thus, the circular logic pattern 8402 may be combined into a complete mask. Figure 84A illustrates a cycle pattern for the logic die of Figure 78B, which cycled 8x12 times. Figure 84B illustrates that the unified logic loops more times to fill a mask. A variety of surface molds for building logic areas can be used for multiple logic storage layers and multiple integrated circuits of 3D integrated circuits. This loop structure can include logic memory P and N transistors, their corresponding contact layers, and even landing strips connecting the base layer. The interconnection layer next to these logical areas can be customized or partially customized according to the setting, depending on the setting method. Custom metal interconnects can keep the logic area unused in the cutting line area. A scribe line mask can also be used to etch the unused transistors in the scribe line 8404, as shown in Figure 84C.

連續邏輯範圍可用任何樣式電晶體,包含以前展示的。對以前提到之某些3D存儲層轉換技術來說,其另外一個優點是,可以為了減少3D定制積體電路製造成本,而選擇提前構造大容量之電晶體。 Continuous logic ranges can use any style of transistor, including those shown previously. Another advantage of some of the 3D storage layer conversion technologies mentioned above is that in order to reduce the manufacturing cost of 3D custom integrated circuits, high-capacity transistors can be constructed in advance.

同樣,一個記憶體範圍可作為一個完全附有掩模之連續循環記憶體結構而建設。多數記憶體之非循環組件可以是位址解碼器,有時是電流檢測線路。這些非循環組件可利用基礎存儲層或覆蓋存儲層上之邏輯電晶體來建設。 Likewise, a memory range can be constructed as a fully masked continuous loop memory structure. The acyclic components of most memories can be address decoders and sometimes current sense circuits. These acyclic devices can be built using logic transistors on the underlying memory layer or on the overlying memory layer.

圖84D-G是靜態隨機記憶體(SRAM)範圍之示意圖。它闡明了由字線(WL)8422和位線(BL.BLB)8424和8426控制之6個常規電晶體靜態隨機記憶體(SRAM)晶 片(cell)8420,通常靜態隨機記憶體位元線之設定很緊湊。 84D-G are schematic diagrams of static random access memory (SRAM) ranges. It illustrates six conventional transistor static random memory (SRAM) crystals controlled by word line (WL) 8422 and bit lines (BL.BLB) 8424 and 8426. Chip (cell) 8420, usually the setting of SRAM bit lines is very compact.

通用之連續陣列8430可以是靜態隨機記憶體(SRAM)位元晶片8420之掩模欄位範圍,其中電晶體存儲層甚至金屬1存儲層可基本上在所有設定中使用。圖84E闡明了連續陣列8430,其中4x4之記憶體區塊透過蝕刻8434周圍之晶片而確定。記憶體可透過定制金屬面模如金屬2和金屬3定做。為控制記憶體區塊,字線8438和位元線8436可透過邏輯範圍下面或上面之過孔來連接。 A generic contiguous array 8430 can be a range of mask fields for a static random access memory (SRAM) bit die 8420, where transistor memory layers and even metal 1 memory layers can be used in substantially all settings. Figure 84E illustrates a contiguous array 8430 where 4x4 memory blocks are defined by etching 8434 the surrounding die. The memory can be customized through custom metal face molds such as Metal 2 and Metal 3. To control memory blocks, wordlines 8438 and bitlines 8436 can be connected by vias below or above the logic range.

圖84F說明邏輯結構8450可以在邏輯範圍上建設,來驅動字線8452。圖84G說明邏輯結構8460可以在邏輯範圍上建設,來驅動字線8462。圖84G還說明讀取電流檢測線路8468可以從位線8462上,讀取記憶體內容。與之相似,其他記憶體結構可從未被授權之記憶體範圍上,利用未被授權之記憶體範圍來建設,記憶體範圍接近於預期記憶體結構。類似比對下,其他記憶體如快閃記憶體或動態隨機存取記憶體(DRAM)可包含記憶體範圍。而且,記憶體範圍可在投影模具邊緣被蝕刻以規定切割線,這一點與圖84C所示之邏輯範圍相似。 FIG. 84F illustrates that a logic structure 8450 can be built on a logic scale to drive a word line 8452. FIG. 84G illustrates that a logic structure 8460 can be built on a logic range to drive a word line 8462. FIG. 84G also illustrates that the read current sense circuit 8468 can read the contents of the memory from the bit line 8462. Similarly, other memory structures can be built on and from unlicensed memory ranges close to the intended memory structure. In a similar comparison, other memories such as flash memory or dynamic random access memory (DRAM) may include memory ranges. Also, memory areas can be etched at the edge of the projected mold to define cut lines, similar to the logic areas shown in Figure 84C.

如利用不同功能之多層存儲層建設3D積體電路,可以依照本項發明案例,透過利用存儲層轉移技術來組合3D存儲層,其預製組合之組件可由,行業標準穿矽過孔技術來連接。 If multi-layer storage layers with different functions are used to build 3D integrated circuits, the 3D storage layers can be combined by using the storage layer transfer technology according to this invention case, and the prefabricated components can be connected by the industry standard through-silicon via technology.

本發明之另一特點是,可以為任意邏輯提供成品修 補。這裏3D積體電路技術,能利用多層邏輯存儲層建設十分複雜之邏輯3D積體電路。在此積體電路中,修補積體電路製造中任意之常見缺陷可能使人很滿意。修補重複結構為人熟知,且常用於記憶體中,這一點請看圖41。另一點是修補任意邏輯為目前3D積體電路技術和直接寫取電子束技術特徵提供支援,如由日本愛德萬株式會社,富士通公司微電子和Vistec提供之技術。 Another feature of the present invention is that it can provide off-the-shelf repairs for arbitrary logic. repair. The 3D integrated circuit technology here can use multiple logic storage layers to construct very complex logical 3D integrated circuits. In such integrated circuits, it may be desirable to repair any common defect in the manufacture of integrated circuits. Patching repeated structures is well known and commonly used in memory, see Figure 41 for this. Another point is patching arbitrary logic to provide support for current 3D IC technology and direct-write e-beam technology features, such as those provided by Advantech, Fujitsu Microelectronics, and Vistec.

圖86A說明了待修補之3D邏輯積體電路。它包含3個邏輯存儲層8602,8612,8622和上存儲層要修補之8632。每個邏輯存儲層都有主要輸出,觸發電路可以傳遞給8632。8632最初包含一個未授權邏輯電晶體之循環結構,這一點與圖76和78所示相似。 Figure 86A illustrates a 3D logic IC to be repaired. It contains 3 logical storage layers 8602, 8612, 8622 and the upper storage layer 8632 to be patched. Each logic storage layer has a primary output, and the trigger circuit can be passed to the 8632. The 8632 originally contained a loop structure of unauthorized logic transistors, similar to that shown in Figures 76 and 78.

圖87說明了為可修理之3D積體電路邏輯設定之觸發電路。此觸發電路8702除包含正常之輸出8704外,還包含通往上存儲層之支路8706,修補邏輯存儲層8632。每個觸發電路,有兩條線源自8632,也就是修補輸入8708和控制8710。通向觸發電路8712之正常輸入可透過專門設定之多路轉換器8714來選擇正常輸入8712,只要頂層控制8710是浮動的。不過一旦頂層控制8710活性降低,多路轉換器8714可以選擇修補輸入8708。故障輸入之影響可能比主要輸入要大。修補會恢復所有所需邏輯以替代類似情況下之故障輸入。 Figure 87 illustrates the flip-flop circuit set for the repairable 3D IC logic. The trigger circuit 8702 includes, in addition to the normal output 8704, a branch 8706 leading to the upper storage layer, repairing the logic storage layer 8632. For each trigger circuit, there are two wires originating from the 8632, namely patch input 8708 and control 8710. The normal input to the flip-flop circuit 8712 can be selected through a specially programmed multiplexer 8714 as long as the top level control 8710 is floating. However, the multiplexer 8714 may choose to patch the input 8708 once the top level control 8710 becomes less active. Faulty inputs may have a greater impact than major inputs. Patching restores all required logic to replace faulty inputs in similar situations.

插入新輸入還有多種選擇,包含利用可編程性,如無需頂控制線8710,一次性可編程部件將原始輸入8712之多 路轉換器8714,切換至所需輸入8708。 There are many options for inserting new inputs, including taking advantage of programmability, such as eliminating the need for top control lines 8710, one-time programmable parts that convert the original input 8712 switch 8714 to the desired input 8708.

在建造方面,3D積體電路晶片可透過全掃描檢驗。如果檢測到有缺陷,可應用修補程式。利用設定資料庫,可將修補邏輯設立在上層存儲層8632。只要在頂層存儲層有效,修補邏輯可進入所有基本輸出。因此,那些需要修補之輸出可用於有缺陷之精確邏輯之重構。重構邏輯可增強某些功能,如驅動器變大或金屬線強度變大,以彌補長線之升降起伏。修補邏輯作為故障邏輯‘圓錐’之實際代替者,可利用頂層記憶體上之為授權電晶體來建設。帶有定制金屬層之頂層記憶體透過利用直接寫取電子光束定制,金屬層為晶片上之每個模具所確定。替代者訊號8708可以連接合適之觸發電路,並透過頂層控制訊號8710之活性降低而變得有活性。 In terms of fabrication, 3D IC chips can be inspected through full scan. If a defect is detected, a patch can be applied. Patching logic can be established in the upper storage layer 8632 using the configuration database. Patching logic can go to all base outputs as long as it is valid at the top storage layer. Thus, those outputs that need to be repaired can be used for reconstruction of flawed precise logic. Reconfiguration logic can enhance certain functions, such as larger drivers or stronger metal lines, to compensate for the ups and downs of long lines. Repair logic, the actual replacement for the 'cone' of faulty logic, can be built using the enabling transistors on the top memory. Top-level memory is customized by using direct write electron beams with a custom metal layer that is defined for each die on the wafer. The replacement signal 8708 can be connected to a suitable trigger circuit and made active by deactivating the top level control signal 8710 .

修補流程也可用于增強性能。如晶片測試包含測時,那麼一個表現緩慢之邏輯‘圓錐’可能以類似方式被替代為前面段落描述之故障邏輯‘圓錐’。 The patching process can also be used to enhance performance. If wafer testing includes timing, then a slow performing logical 'cone' may be replaced in a similar manner by a faulty logical 'cone' as described in the previous paragraph.

圖86B是3D積體電路之示意圖,在其中設定之掃描鏈使其僅限於一層存儲層。此限制使每層存儲層在建設時可以測試,在很多方面也有用。如電路層結束後接著測試表現糟糕,可移除晶片不再繼續建設糟糕基礎上之3D電路層。另外,可建設模組化設定,因而下面之轉移電路層包含基礎故障層之替代模組,與圖41之建議類似。 FIG. 86B is a schematic diagram of a 3D integrated circuit in which the scan chain is set so that it is limited to only one memory layer. This limitation makes each storage layer testable as it is being built, which is also useful in many ways. If the test performance is poor after the circuit layer is completed, the chip can be removed and no longer continue to build the 3D circuit layer on the poor foundation. In addition, a modular setup can be built so that the underlying transfer circuit layer contains replacement modules for the underlying fault layer, similar to the suggestion in FIG. 41 .

附圖86A和86B所涉及之發明元素,需要在製造階段進行晶圓檢測,如果檢測時探測到晶圓,對於與檢測晶圓 有體接觸之碎片有關聯。附圖86C是一個無接點自動自測之案例,示意圖。藉由環形天線86C02,RF到DC轉換電路86C04和電源裝置86C06,無接點電源收集組件就可收集相關電路上之電磁能,從而產生必要之電源電壓來運行自檢測電路以及待測之各種3D IC電路86C08。或者,使用一塊小型之光伏電池86C10將光束能量轉換成電流,再經由電源裝置86C06轉換成所需之電壓。一旦電路通電,微控制器86C12就能對所有現有電路86C08進行全掃描檢測。自測方式有兩種選擇:全掃描或BIST(內建自測)。檢測結果可透過無線電模組86C14傳輸到位於3D IC晶圓外部之基本裝置上。這種無接點晶圓檢測可用於附圖86A和附圖86B中引用之測試或其他應用,例如晶圓對晶圓或晶粒對晶圓之TSV接合。無接點檢測之替代運用,可應用到本發明之不同組合中。舉例子來說,載流子晶圓法可用來產生晶圓傳送層,而電晶體以及連接它們之金屬層卻構成了功能電子電路。這些功能電路透過無接點檢測開啟固有場(validate proper yield);若可能的話,完成修復動作或開啟內部冗餘。然後透過層轉移,經檢測之功能電路層就會轉移到另一加工晶圓808上,再利用之前介紹之一種方法進行連接。 The inventive elements involved in Figures 86A and 86B require wafer inspection during the manufacturing stage. If the wafer is detected during inspection, for the inspection wafer Fragments of physical contact are related. Accompanying drawing 86C is a case of non-contact automatic self-test, schematic diagram. With loop antenna 86C02, RF to DC conversion circuit 86C04 and power supply unit 86C06, the non-contact power collection component can collect the electromagnetic energy on the relevant circuit, thereby generating the necessary power supply voltage to run the self-test circuit and various 3D devices to be tested IC circuit 86C08. Alternatively, use a small photovoltaic cell 86C10 to convert the beam energy into current, and then convert it to the required voltage through the power supply unit 86C06. Once the circuit is powered on, the microcontroller 86C12 can perform a full scan of all existing circuits 86C08. There are two options for self-test: full scan or BIST (built-in self-test). The test results can be transmitted to the base device outside the 3D IC wafer through the radio module 86C14. This contactless wafer inspection can be used for testing referenced in Figures 86A and 86B or for other applications such as wafer-to-wafer or die-to-wafer TSV bonding. Alternative uses of contactless detection can be applied in different combinations of the present invention. For example, the carrier wafer method can be used to produce wafer transport layers, while the transistors and the metal layers connecting them form the functional electronic circuits. These functional circuits validate proper yield through contactless detection; if possible, perform repair actions or enable internal redundancy. Then through layer transfer, the tested functional circuit layer will be transferred to another processed wafer 808, and then connected by one of the methods introduced earlier.

依照成品率修復設定方法論,幾乎全部主要輸出訊號8706會增長,而幾乎全部主要輸入訊號8712會被來自頂端之8708訊號所代替。 According to the yield recovery setup methodology, almost all of the main output signal 8706 will grow, and almost all of the main input signal 8712 will be replaced by the 8708 signal from the top.

而成品率修復設定方法論之一個額外優勢在於:在一 個設定和另一個設定之間再利用邏輯層之能力。舉例來說,3D IC系統之某一層包含一個WiFi收發器,而這種電路正被完全不同之3D IC所需要。因此,在新設定中再用同樣之WiFi收發器是很有利的,只透過將接受器作為新的3D IC設定層之一來達到不用重新設定和節省掩膜等NRE(一次性費用)之目的。亦可在許多其他功能中應用再用原理,使得3D IC趨向于舊式之接合功能,即PC(印刷電路)板。為了保證該概念之順利實施,最理想之方式就是制定一個適用於連接上下線路之連通性標準。 An additional advantage of the Yield Repair Setup methodology is that: The ability to reuse layers of logic between one setting and another. For example, one layer of the 3D IC system contains a WiFi transceiver, and this circuit is being required by a completely different 3D IC. Therefore, it is very beneficial to reuse the same WiFi transceiver in the new configuration, only by using the receiver as one of the new 3D IC configuration layers to achieve the purpose of not having to reset and save NRE (one-time cost) such as masks . The principle of re-use can also be applied in many other functions, making 3D ICs trend towards the old-fashioned bonding function, ie PC (printed circuit) boards. In order to ensure the smooth implementation of this concept, the ideal way is to develop a connectivity standard suitable for connecting up and down lines.

這些概念之其他應用方式包含,使用上層調整實際裝置之時鐘及其不同製造組件來達到修改時鐘計時之目的。掃描電路可用來測量時鐘脈衝相位差並報備給一個外接設定工具。外接設定工具在時鐘修改電路施加下,可進行定時修改,再利用直讀式電子束形成電晶體和上層電路,從而透過時鐘修改,實現3D IC終端產品之較佳成品率和性能平。 Other applications of these concepts include using upper layers to adjust the clock of the actual device and its various manufacturing components for the purpose of modifying the timing of the clock. The scan circuit can be used to measure the clock skew and report it to an external setting tool. The external setting tool can perform timing modification under the application of the clock modification circuit, and then use the direct-reading electron beam to form the transistor and the upper circuit, so that through the clock modification, the better yield and performance level of 3D IC terminal products can be achieved.

藉由3D結構增加複雜系統成品率之另一方法,就是在上下疊加之兩層上複製同一設定,並使用與上述識別和更換異常邏輯錐方法一樣之BIST設定技術。這應證明,在生產階段使用一次性或難以逆轉之修復結構(例如反熔絲或直讀式專用電子束),即使成品率很低,也能非常有效之修復大量IC。透過下文附圖114中所述之基於記憶體之修復結構,相同之修復方法也可為,每一加電順序(加電次序)?下需要自我修復能力之系統提供幫助。 Another way to increase the yield of complex systems with 3D structures is to duplicate the same setup on two superimposed layers and use the same BIST setup technique as described above for identifying and replacing abnormal logic cones. This should demonstrate that the use of one-time or irreversible repair structures such as antifuse or direct-reading dedicated electron beams at the production stage can be very effective in repairing large numbers of ICs, even at low yields. With the memory-based repair structure described below in Figure 114, the same repair method is also available, per power-up sequence (power-up sequence)? Helping systems that need self-healing capabilities.

附圖114是對這個概念之可能案例之示意圖。兩個上下疊加之邏輯層11401和11402基本上採用一樣之設定。這個設定(所有層都一樣)基於掃描,而且直接或透過外接試驗器進行通訊之各層11451和11452都包含有BIST控制器/檢驗器。11421是一個具有代表性之第一層觸發器flip-flop(FF),在第2層上有一個相應的FF 11422,分別受饋於各自相同之邏輯錐(logic cones)11411和11412。觸發器11421之輸出透過垂直連接11406耦合到複用器11431之A輸入和複用器11432之B輸入,而觸發器11422之輸出則透過垂直連接11405耦合到複用器11432之A輸入和複用器11431之B輸入。每個輸出複用器各自從控制點11441和11442起受控,而複用器輸出則驅動各自每層之下個邏輯階段。因此,不管是邏輯錐11411和觸發器11421還是邏輯錐11412和觸發器11422,可編程地或選擇性地耦合到每層之下個邏輯階段。 Figure 114 is a schematic illustration of a possible example of this concept. The two logical layers 11401 and 11402 superimposed on top of each other basically adopt the same setting. This setup (the same for all layers) is based on scans, and each layer 11451 and 11452 that communicates directly or through an external tester contains a BIST controller/checker. 11421 is a representative flip-flop (FF) on the first layer, and there is a corresponding FF 11422 on the second layer, which are respectively fed by the same logic cones (logic cones) 11411 and 11412. The output of flip-flop 11421 is coupled to the A input of multiplexer 11431 and the B input of multiplexer 11432 via vertical connection 11406, while the output of flip-flop 11422 is coupled to the A input of multiplexer 11432 and multiplexed via vertical connection 11405. The B input of device 11431. Each output multiplexer is individually controlled from control points 11441 and 11442, and the multiplexer output drives the respective next logic stage below each layer. Therefore, whether it is the logic cone 11411 and the flip-flop 11421 or the logic cone 11412 and the flip-flop 11422, it is programmatically or selectively coupled to the next logic stage under each layer.

採用存儲晶片、反熔絲或任何其他定製件(比如直讀式電子束機器專做之金屬絲-Direct-Write e-Beam machine),實施複用器控制點11441和11442。若採用存儲晶片,那麼它的內容可存儲在ROM、快閃記憶體或其他非易失性存儲媒介中,或存儲在3D IC或在系統開啟、重定或系統維修請求時所分佈,並載入內容之系統中。 Multiplexer control points 11441 and 11442 are implemented using memory chips, antifuses or any other custom parts such as wires for Direct-Write e-Beam machines. If a memory chip is used, its contents can be stored in ROM, flash memory or other non-volatile storage media, or stored in 3D IC or distributed when the system is turned on, reset or system maintenance request, and loaded into the in the content system.

一旦開啟,BCC初始化所有複用器控制程式,來選擇輸入A並在每層設定上,運行診斷試驗。透過掃描和BIST技術確定每個邏輯層上之故障觸發器(FF),只要一對相 應的FF沒有同時出現故障,BCC就可以與彼此進行通訊(直接或透過一個外接試驗器)來確定哪個運行良好之FF使用,並設定複用器控制程式11441和11442。 Once turned on, the BCC initializes all multiplexer control programs to select input A and run diagnostic tests on each layer setting. Identify Fault Flip-Flops (FF) on each logic layer through scanning and BIST technology, as long as a pair of phase As long as the corresponding FFs do not fail simultaneously, the BCCs can communicate with each other (directly or through an external tester) to determine which FFs are well-behaved to use and program the multiplexer control programs 11441 and 11442.

如果複用器控制程式11441和11442藉由存儲晶片可重編程式,那麼測試和修復過程可在每次開啟或請求時發生,從而實現3D IC在電路中之自我修復。如果複用器控制程式只可以編程一次,那麼診斷和修復過程之實現則需藉由外接設備。請注意,上文附圖86C中所述之無接點測試和修復技術就可在這種情況下得到應用。 If the multiplexer control programs 11441 and 11442 are reprogrammable by the memory chip, then the test and repair process can occur every turn-on or request, thereby realizing the self-healing of the 3D IC in the circuit. If the multiplexer control program can only be programmed once, then the diagnosis and repair process needs to be realized through external equipment. Note that the no-contact test and repair technique described above in Figure 86C can be applied in this case.

這個概念之另一案例:在附圖87中描述之FF輸入處採用複用8714。在那種情況下,如果存在的話,就可同時使用FF之Q和反向Q。 Another example of this concept: Multiplexing 8714 is employed at the FF input depicted in FIG. 87 . In that case, both the Q of the FF and the reverse Q can be used, if present.

所屬技術領域之專業人員知悉,這種從兩個幾乎一模一樣並上下疊加之部件中二選一之修復法,可應用於除上述FF外之其他部件中。例子包含但不限於,模擬塊、I/O、記憶體和其他部件。在這種情況下,工作輸出之選擇需要專門之複用技術(多工技術),但該技術之本質保持不變。 Those skilled in the art know that this method of repairing one of two almost identical parts superimposed on top of each other can be applied to other parts except the above-mentioned FF. Examples include, but are not limited to, analog blocks, I/O, memory, and other components. In this case, the selection of the job output requires a special multiplexing technique (multiplexing technique), but the essence of the technique remains the same.

所屬技術領域之專業人員將同時知悉,一旦兩層之BIST診斷完整,那麼與用來確定複用器控制程式相同之機構,也可用於選擇性地切斷邏輯層未使用部分之電源,從而節約功耗。 Those skilled in the art will also appreciate that once the BIST diagnostics for both layers are complete, the same mechanism used to determine the multiplexer control program can also be used to selectively power down unused portions of the logic layer, thereby saving power consumption.

但本發明之另一不同之處在於:藉由三模(或更高)冗餘(“TMR”)等冗餘理念在飛速(快速)修復中採用 了垂直堆垛法。TMR在高依賴性行業是一個非常有名之理念,其中,每個電路各生產三份,它們之輸出部分則透過多數表決電路。只要TMR模組中不出現超過一個單個故障,那麼該TMR系統就可繼續無故障運行。設定TMR IC時之一個主要問題就是當電路增至三倍時,那麼互連會大大變長導致系統運行減慢,而且路線選擇也變得更加複雜,導致系統設定之進度減緩。TMR之另一個主要問題就是由於相比變大之設定尺寸導致設定工藝昂貴,而市場卻有限。 But another difference of the present invention is that it is adopted in rapid (rapid) repair by means of redundancy concepts such as triple-mode (or higher) redundancy ("TMR") vertical stacking method. TMR is a well-known concept in the high-dependency industry, where three copies of each circuit are produced and their outputs pass through the majority voting circuit. As long as no more than one single fault occurs in the TMR module, the TMR system continues to operate without faults. One of the main problems when setting up a TMR IC is that when the circuit is tripled, the interconnection becomes much longer which slows down the system operation, and the routing becomes more complicated, which slows down the progress of the system set-up. Another major problem with TMR is that the setting process is expensive due to the larger setting size, and the market is limited.

垂直堆垛法為複製每一頂部系統映射提供了一個自然解決方案。附圖115對含有三層11501 11502 11503之系統進行了說明,其中組合邏輯複製到邏輯錐11511-1、11511-2和11511-3中,而FF複製到11521-1、11521-2和11521-3。本段中之其中一層11501包含了多數表決電路11531,其在本地FF輸出11661和垂直堆垛之FF輸出11552和11553間進行了判決,從而產生一個需要分配到11541-1、11541-2和11541-3等所有邏輯層之最終容錯FF輸出。 Vertical stacking provides a natural solution for duplicating the mapping of each top system. Figure 115 illustrates a system with three layers 11501 11502 11503 where combinational logic is replicated in logic cones 11511-1, 11511-2 and 11511-3 and FF is replicated in 11521-1, 11521-2 and 11521- 3. One of the tiers 11501 in this section contains majority voting circuitry 11531 which decides between the local FF output 11661 and the vertically stacked FF outputs 11552 and 11553, resulting in an -3 etc. Final fault tolerant FF output for all logical layers.

所屬技術領域之專業人員會知悉,配置變化是可以實現的,比如將一個獨立層分配到表決電路,使得各層11501、11502和11503在邏輯上保持一致;將表決電路再定位到FF之輸入而不是輸出上;或將冗餘之複製範圍擴大到至少3次以上(和疊加層)。 Those skilled in the art will appreciate that configuration changes are possible, such as assigning an independent layer to the voting circuit so that the layers 11501, 11502, and 11503 are logically consistent; relocating the voting circuit to the input of the FF instead of on output; or extend redundant replication to at least 3 more times (and overlays).

上述設定三模冗餘(TMR)之方法都同時提到了所述缺點。第一,因為TMR之存在,基本上每一層中都沒有額 外之佈線擁擠,且每一層之設定可在單個映射而不是三重映射中優化實行。其次,透過三個原始映射之垂直堆垛及在附圖115中任一層、所有三層或一個獨立層上增加一個多數表決電路之方式,在非高依賴性市場實施之任何設定,可用最少之精力實現TMR之設定轉換。TMR電路可帶著已知現有錯誤(TMR冗餘掩蓋)從工廠發運或增加一個修復層來修復任何已知錯誤,從而保證更高之依賴性。 The above-mentioned methods for setting triple-mode redundancy (TMR) all mention the above-mentioned disadvantages at the same time. First, because of the existence of TMR, basically there is no additional In addition, the wiring is crowded, and the setting of each layer can be optimized in a single map instead of a triple map. Second, by vertically stacking the three original maps and adding a majority voting circuit on any, all three, or a separate layer in Figure 115, any setup implemented in a non-highly dependent market can be implemented with minimal Efforts to realize the setting conversion of TMR. TMR circuits can be shipped from the factory with known existing errors (TMR redundancy masking) or with the addition of a repair layer to repair any known errors, thus ensuring higher dependencies.

截至目前所討論之案例主要涉及,將3D IC發貨給客戶前之成品率提升以及工廠修復問題。本發明之另一方面則是當產品率中分佈3D IC時提供冗餘和自我修復。這是一個理想之產品特徵,因為即使在工廠中運行無誤,檢測產品中還是會出現缺陷。例如,缺陷原因可能為延遲之故障機構,如電晶體之故障柵極介質演變成柵極和底層電晶體源極、漏極或基極之間之短路問題。組裝完成後,電晶體在廠測試運行無誤,但隨著時間和施加之電壓和溫度,缺陷可演變成故障,可在隨後之現場測試中發現。很多其他之延誤故障機構已被世人所知。撇開延誤之缺陷性質來說,若它給3D IC中帶來了邏輯錯誤,則可採用依照本發明之隨後測試進行檢測並修復。 The cases discussed so far have mainly involved yield improvement and factory repair issues before shipping 3D ICs to customers. Another aspect of the present invention is to provide redundancy and self-healing when distributing 3D ICs in production rates. This is a desirable product feature because even if it works flawlessly in the factory, defects can still appear in inspected products. For example, the defect cause may be a delayed failure mechanism, such as a faulty gate dielectric of a transistor that evolves into a short circuit problem between the gate and the source, drain or base of the underlying transistor. After assembly, the transistors are tested to operate without error at the factory, but with time and applied voltage and temperature, defects can evolve into failures, which can be found in subsequent field tests. Many other delay failure mechanisms are known. Leaving aside the defective nature of the delay, if it introduces a logic error in the 3D IC, it can be detected and repaired using subsequent testing in accordance with the present invention.

依照本發明案例,附圖119對以11900表示之3D IC進行了說明。3D IC 11900包含兩層,分別以第1層和第2層表示,在附圖中以虛線區分開來。第1層和第2層可透過本技術已知之方法接合到一個3D IC中。第1層和第2層之間之訊號可透過矽通孔技術(TSV)或其他之間層技術實現 電耦合。第1層和第2層各自包含一個半導體裝置層,叫做電晶體層,而其相關之互連(在一個或多個物理金屬層中實現)則叫做互連層。一個電晶體層和一個或多個互連層稱為電路層。第1層和第2層各自可包含裝置和互連之一個或多個電路層,視設定方案而定。 According to the example of the present invention, accompanying drawing 119 illustrates the 3D IC indicated by 11900. The 3D IC 11900 includes two layers, respectively denoted as layer 1 and layer 2, which are distinguished by dotted lines in the drawings. Layer 1 and Layer 2 can be bonded into a 3D IC by methods known in the art. The signal between layer 1 and layer 2 can be realized through silicon via technology (TSV) or other interlayer technology electrical coupling. Layers 1 and 2 each contain a semiconductor device layer, called a transistor layer, and its associated interconnections (implemented in one or more physical metal layers) are called interconnect layers. A transistor layer and one or more interconnect layers are called circuit layers. Layer 1 and Layer 2 may each include one or more circuit layers of devices and interconnects, depending on the setup.

儘管在結構詳圖中有差異之處,3D IC 11900中之第1層和第2層大致上採用的是相同之邏輯功能。在一些案例中,第1層和第2層使用與所有層相同之掩模進行各自封裝,來降低生產成本。而在另外一些案例中,一個或多個掩模層還是存在微小之偏差。例如,針對在各層上產生不同邏輯訊號之一個邏輯層來說還是存在選擇的,這告訴第1層和第2層上之控制邏輯塊這樣一個事實,它們是各自重要情況下第1層和第2層之控制器。層間其他差異之處依設定情況而存在。 Although there are differences in the structural details, Layer 1 and Layer 2 in the 3D IC 11900 generally employ the same logic functions. In some cases, layer 1 and layer 2 are individually encapsulated using the same mask as all layers to reduce production costs. In other cases, however, one or more of the mask layers still has a slight deviation. For example, there is still a choice for one logic layer to generate different logic signals on each layer, which tells the control logic blocks on layers 1 and 2 of the fact that they are layers 1 and 2 in their respective importance. 2 layer controller. Other differences between layers exist depending on the setting.

第1層包含控制邏輯11910,代表性掃描觸發器11911、11912和11913及代表性組合邏輯雲11914和11915,而第2層包含控制邏輯11920,代表性掃描觸發器11921、11922和11923及代表性邏輯雲11924和11925。控制邏輯11910和掃描觸發器11911、11912和11913耦合到一塊形成了一條掃描鏈,以上述描述之方式來群組掃描測試組合邏輯雲11914和11915。而控制邏輯11920和掃描觸發器11921、11922和11923也耦合到一塊形成了一條掃描鏈,來群組掃描測試組合邏輯雲11924和11925。控制邏輯塊11910和11920耦合到一塊來協調在兩個層上進行之測 試。在一些案例中,控制邏輯塊11910和11920可測試自身或彼此。若其中一個壞了,另一個還可控制第1層和第2層上進行之測試。 Tier 1 contains control logic 11910, representative scan flops 11911, 11912, and 11913, and representative combinatorial logic clouds 11914 and 11915, while tier 2 contains control logic 11920, representative scan flops 11921, 11922, and 11923, and representative Logic Cloud 11924 and 11925. Control logic 11910 and scan flip-flops 11911, 11912 and 11913 are coupled together to form a scan chain to group scan test combinatorial logic clouds 11914 and 11915 in the manner described above. The control logic 11920 and the scan flip-flops 11921 , 11922 and 11923 are also coupled together to form a scan chain to group scan test combinatorial logic clouds 11924 and 11925 . Control logic blocks 11910 and 11920 are coupled together to coordinate measurements performed on the two layers try. In some cases, control logic blocks 11910 and 11920 may test themselves or each other. If one fails, the other can also control the tests performed on layers 1 and 2.

所屬技術領域之通常知識者將樂於看到,附圖119中掃描鏈之代表性特徵之前提是實際設定中數以百萬計之觸發器形成多個掃描鏈,而且本文公開之發明原理適用,不受設定之大小和範圍之影響。 Those of ordinary skill in the art will be pleased to see that the representative features of the scan chains in Figure 119 are based on the premise that millions of flip-flops form multiple scan chains in actual settings, and that the principles of the invention disclosed herein apply, Unaffected by the size and range set.

如前述案例,第1層和第2層掃描鏈可用於工廠不同測試用途。例如,第1層和第2層可各自有一個相關之修復層(附圖119中未體現),用來校正封裝過程中第一次出現在第1層或第2層上之缺陷邏輯錐或邏輯塊。或者,第1層和第2層共用一個修復層。 As in the previous case, the layer 1 and layer 2 scan chains can be used for different test purposes in the factory. For example, Layer 1 and Layer 2 may each have an associated repair layer (not shown in FIG. 119 ) for correcting defective logic cones or logic blocks. Alternatively, layers 1 and 2 share a restoration layer.

附圖120對適用于本發明一些案例之典型掃描觸發器12000(附圖中虛線框中部分)進行了解釋說明。掃描觸發器12000用於附圖119中之掃描觸發器11911、11912、11913、11921、11922和11923。附圖120中是D型觸發器12002,它有一個耦合到掃描觸發器12000 Q輸出之Q輸出以及一個耦合到複用器12004輸出之D輸入,以及一個耦合到CLK訊號之時鐘輸入。複用器12004也有耦合到複用器12006輸出之第一資料登錄,耦合到掃描觸發器12000 SI(掃描輸入)輸入,以及耦合到SE(掃描開啟)訊號之選擇輸入。複用器12006也有耦合到掃描觸發器12000之D0和D1輸入之第一和第二資料登錄,及一個耦合到LAYER_SEL訊號之選擇輸入。 Figure 120 illustrates a typical scan flip-flop 12000 (in the dashed box in the figure) suitable for some cases of the present invention. Scan flip-flop 12000 is used for scan flip-flops 11911, 11912, 11913, 11921, 11922, and 11923 in FIG. 119 . In Figure 120 is D flip-flop 12002 which has a Q output coupled to the Q output of scan flip-flop 12000 and a D input coupled to the output of multiplexer 12004, and a clock input coupled to the CLK signal. Multiplexer 12004 also has a first data entry coupled to the output of multiplexer 12006, a SI (scan in) input coupled to scan flip-flop 12000, and a select input coupled to the SE (scan on) signal. Multiplexer 12006 also has first and second data entries coupled to the D0 and D1 inputs of scan flip-flop 12000, and a select input coupled to the LAYER_SEL signal.

SE、LAYER_SEL和CLK訊號未顯示耦合到掃描觸發器12000之輸入端上以避免公開的過度複雜化-特別是像附圖119類似之圖紙,其中掃描觸發器12000之多個例子表明且明確佈線會轉移正表述理念之注意力。在實際設定中,所有三個訊號均典型地耦合到掃描觸發器12000每一相應的電路中。 The SE, LAYER_SEL and CLK signals are not shown coupled to the inputs of the scan flip-flop 12000 to avoid over-complicating the disclosure - especially a drawing like Figure 119 where multiple instances of the scan flip-flop 12000 show and clearly the wiring would To divert attention from the idea being expressed. In a practical setup, all three signals are typically coupled into each respective circuit of scan flip-flop 12000.

確定時,SE訊號將掃描觸發器12000處於掃描模式導致複用器12004柵極控制SI輸入到D型觸發器12002之D輸入。由於該訊號在掃描鏈中轉向所有之掃描觸發器12000,從而將它們連接到一塊組成一個移位寄存器,使得向量移入,測試結果移出。當SE不確定時,複用器12004選擇複用器12006之輸出到D型觸發器12002之D輸入。 When asserted, the SE signal puts the scan flip-flop 12000 in scan mode causing the gate of the multiplexer 12004 to control the SI input to the D input of the D-type flip-flop 12002 . Since this signal is diverted to all scan flip-flops 12000 in the scan chain, they are connected together to form a shift register, so that vectors are shifted in and test results are shifted out. The multiplexer 12004 selects the output of the multiplexer 12006 to the D input of the D flip-flop 12002 when SE is indeterminate.

CLK訊號作為一個“內部”訊號出現,因為它的起點會由於設定選擇之問題,各個案例都會不一樣。在實際設定中,一個時鐘訊號(或其變形體)經特殊佈線至其功能域中每個觸發器。在一些掃描測試總體結構中,函數運算時,第三個複用器(附圖120中未體現)會從域時鐘中選擇CLK;掃描測試時,則會從掃描時鐘中選擇。在這些情況下,SCAN_EN訊號將特殊耦合到第三個複用器之選擇輸入上,這樣D型觸發器12002就能同時在掃描和函數運算模式下正確計時。在其他掃描總體結構中,掃描時鐘處於測試模式時刻採用功能域時鐘,無需額外之複用器。所屬技術領域之通常知識者知悉,許多不同的掃描總體結構已 被人所熟知,並意識到任何給定案例中之特殊掃描總體結構,將視設定選擇而定,而不會限於本發明內容。 The CLK signal appears as an "internal" signal because its starting point will vary from case to case due to a matter of setting choice. In a practical setup, a clock signal (or variants thereof) is specially routed to each flip-flop in its functional domain. In some scan test general structures, the third multiplexer (not shown in FIG. 120 ) will select CLK from the domain clock during function operation; during scan test, it will select from the scan clock. In these cases, the SCAN_EN signal will be specifically coupled to the select input of the third multiplexer so that the D-type flip-flop 12002 can be clocked correctly in both scan and function modes. In other scan overall structures, the scan clock is in test mode using the functional domain clock without additional multiplexers. Those of ordinary skill in the art know that many different scanning general structures have been It is well known, and recognized, that the particular scan general structure in any given case will be a matter of setting choices, and not limiting of this disclosure.

LAYER_SEL訊號決定了,正常操作模式下掃描觸發器12000之資料源。如附圖119所示,輸入D1耦合到掃描觸發器12000所在某層(第1層或第2層)邏輯錐之輸出上,而輸入D0耦合到另一層相應邏輯錐之輸出上。LAYER_SEL之缺省值是邏輯值-1,選擇了同一層之輸出。每個掃描觸發器12000有其獨特之ALYER_SEL訊號。這使得一層上之缺陷邏輯錐接受其在另一層上對應錐之可編程或選擇性更換。在這種情況下,被更換之耦合到D1之訊號稱為故障訊號,而更換它之耦合到D0之訊號則稱為修復訊號。 The LAYER_SEL signal determines the data source of the scan flip-flop 12000 in normal operation mode. As shown in FIG. 119, the input D1 is coupled to the output of the logic cone of a certain level (level 1 or level 2) where the scan flip-flop 12000 is located, and the input D0 is coupled to the output of the corresponding logic cone of the other level. The default value of LAYER_SEL is logical value -1, which selects the output of the same layer. Each scan flip-flop 12000 has its unique ALYER_SEL signal. This enables a defective logic cone on one layer to undergo programmable or selective replacement of its corresponding cone on another layer. In this case, the signal coupled to D1 that is replaced is called the fault signal, and the signal coupled to D0 that replaces it is called the repair signal.

附圖121A對以12100表示之典型3D IC進行了說明。與附圖119案例一樣,3D IC 12000包含兩層,分別以第1層和第2層表示,在附圖中以虛線區分開來。第1層包含第1曾邏輯錐12110、掃描觸發器12112和XOR門12114,而第2層則包含第2層邏輯錐12120、掃描觸發器12122和XOR門12124。附圖120中之掃描觸發器12000可用於掃描觸發器12112和12122,儘管SI和其他內部連接未在附圖121A中得到體現。第1層邏輯錐12110之輸出(圖形中以DATA1表示)分別耦合到第1層掃描觸發器12112之D1輸入和第2層掃描觸發器12122之D0輸入。同樣地,第2層邏輯錐12120之輸出(圖形中以DATA2表示)分別耦合到第2層掃描觸發器12122之D1輸入和第1層掃描觸發器12112之D0輸入。 掃描觸發器12112和12122分別有各自之LAYER_SEL訊號(未體現在附圖121A中),以與附圖120中說明之相同方式在D0和D1輸入之間進行選擇。 FIG. 121A illustrates a typical 3D IC, indicated generally at 12100. Like the case in Figure 119, the 3D IC 12000 includes two layers, respectively denoted as layer 1 and layer 2, which are distinguished by dotted lines in the drawing. Layer 1 contains 1st logic cone 12110 , scan flip-flop 12112 and XOR gate 12114 , while layer 2 contains layer 2 logic cone 12120 , scan flip-flop 12122 and XOR gate 12124 . Scan flip-flop 12000 in FIG. 120 can be used for scan flip-flops 12112 and 12122, although SI and other internal connections are not shown in FIG. 121A. The output of the logic cone 12110 of the first layer (indicated by DATA1 in the figure) is respectively coupled to the D1 input of the first layer scan flip-flop 12112 and the D0 input of the second layer scan flip-flop 12122 . Similarly, the output of the logic cone 12120 of the layer 2 (indicated by DATA2 in the figure) is coupled to the D1 input of the layer 2 scan flip-flop 12122 and the D0 input of the layer 1 scan flip-flop 12112, respectively. Scan flip-flops 12112 and 12122 each have their own LAYER_SEL signal (not shown in FIG. 121A ) that selects between the D0 and D1 inputs in the same manner as illustrated in FIG. 120 .

XOR門12114有一耦合(first input coupled)到DATA1之輸入,第二個耦合到DATA2之輸入以及耦合到訊號ERROR1之輸出。同樣地,XOR門12124有一耦合到DATA2之輸入,第二個耦合到DATA1之輸入以及耦合到訊號ERROR2之輸出。如果DATA1和DATA2上訊號之邏輯值不同,ERROR1和ERROR2將取邏輯值-1,表示存在邏輯錯誤。如果DATA1和DATA2上訊號之邏輯值相同,ERROR1和ERROR2將取邏輯值-0,表示不存在邏輯錯誤。所屬技術領域之通常知識者知悉這裏所影射之假設是:邏輯錐12110和12120其中一個才會同時壞掉。既然第1層和第2層已經經過了工廠測試、驗證並在一些案例中進行了修復,那麼兩個在現場出現故障之邏輯錐之統計相似性,即使未經任何因數修復也是不可能的,從而證實了這個假設。 XOR gate 12114 has a first input coupled to DATA1, a second input coupled to DATA2 and an output coupled to signal ERROR1. Likewise, XOR gate 12124 has one input coupled to DATA2, a second input coupled to DATA1 and an output coupled to signal ERROR2. If the logic values of the signals on DATA1 and DATA2 are different, ERROR1 and ERROR2 will take logic value -1, indicating that there is a logic error. If the logic values of the signals on DATA1 and DATA2 are the same, ERROR1 and ERROR2 will take a logic value of -0, indicating that there is no logic error. Those skilled in the art know that the assumption implied here is that only one of the logic cones 12110 and 12120 will be broken at the same time. Now that Tier 1 and Tier 2 have been factory tested, validated and in some cases repaired, the statistical similarity of two logic cones that failed in the field, even without any factor repair, is impossible, thus confirming this hypothesis.

在3D IC 12100中,可視設定選擇需要以很多不同之方式進行測試。例如,時鐘突然中止,ERROR1和ERROR2訊號之狀態在系統維修階段以抽查方式進行監測。或者,中止運行並依照每個向量所做之比對運行掃描向量。在一些案例中,採用BIST測試方案中常用之線性回饋移位寄存器,來產生用於循環冗餘校驗之偽隨機向量。這些方法都涉及停止系統運行並進入測試模式。即時監測 可能錯誤情況之其他方法將在下文進行探討。 In 3D IC 12100, visual setting selection needs to be tested in many different ways. For example, the clock is stopped suddenly, and the status of the ERROR1 and ERROR2 signals is monitored in a spot check during the system maintenance phase. Alternatively, abort the run and run through the vectors according to the alignments made for each vector. In some cases, a linear feedback shift register commonly used in BIST test schemes is used to generate pseudo-random vectors for cyclic redundancy checks. These methods all involve stopping the system and entering test mode. real-time monitoring Other methods of possible error conditions are discussed below.

為了實現3D IC 12100之修復,專門做了2次測定:(1)錯誤邏輯錐之位置,和(2)兩個相應邏輯錐中之哪個在該位置運行無誤。因此,儘管還有其他方法,還是要用到ERROR1和ERROR2訊號之監測方法以及觸發器12112和12122LAYER_SEL訊號之控制方法。在一個實際案例中,需要LAYER_SEL訊號狀態之讀寫方法,用於工廠測試來證明第1層和第2層均運行無誤。 In order to achieve the repair of 3D IC 12100, two determinations were made: (1) the position of the faulty logic cone, and (2) which of the two corresponding logic cones worked correctly at that position. Therefore, although there are other methods, the monitoring method of the ERROR1 and ERROR2 signals and the control method of the trigger 12112 and 12122 LAYER_SEL signals are still used. In a practical case, the method of reading and writing the state of the LAYER_SEL signal is needed for factory testing to prove that both layer 1 and layer 2 are functioning correctly.

特別是,每個掃描觸發器之LAYER_SEL訊號可保存在可編程晶片中,例如易失性存儲電路猶如一個鎖存器存儲一比特二進位資料(未體現在附圖121A中)。在一些案例中,每個可編程晶片或鎖存器之正確值可在系統開啟、系統重定或請求時作為系統維修之常規內容進行測定。或者,每個可編程晶片或鎖存器之正確值,可在更早時候測定並儲存在快閃記憶體等非易失性媒介或透過3D IC 12100內部之可編程反熔絲進行保存,或者這些值也可以存儲在3D IC 12100分佈所在系統之其他地方。在那些案例中,存儲在非易失性媒介之資料可以某一方式從其存儲位置讀取並寫到LAYER_SEL鎖存器中。 In particular, the LAYER_SEL signal of each scan flip-flop can be stored in the programmable chip, for example, the volatile memory circuit is like a latch to store a bit of binary data (not shown in FIG. 121A ). In some cases, the correct value of each programmable chip or latch can be determined at system start-up, system reset or request as a routine part of system maintenance. Alternatively, the correct value of each programmable chip or latch can be determined earlier and stored in a non-volatile medium such as flash memory or saved through a programmable antifuse inside the 3D IC 12100, or These values may also be stored elsewhere in the system where the 3D IC 12100 is distributed. In those cases, the data stored on the non-volatile media can be read from its storage location and written to the LAYER_SEL latch in some way.

用不相同之ERROR1和ERROR2監測方法是可能的。例如,可透過每層上獨立之移位寄存器鏈(未體現在附圖121A中)來捕獲ERROR1和ERROR2值,儘管這會引起大面積損失。或者,ERROR1和ERROR2訊號可各自耦合到掃描觸發器12112和12122(未體現在附圖121A中),在測 試模式下捕獲後移出。這可能會減少掃描觸發器製造費用,但還是很昂貴。 It is possible to use different ERROR1 and ERROR2 monitoring methods. For example, ERROR1 and ERROR2 values could be captured by separate shift register chains (not shown in Figure 121A) on each layer, although this would incur a large area penalty. Alternatively, the ERROR1 and ERROR2 signals may be coupled to scan flip-flops 12112 and 12122 (not shown in FIG. Move out after capture in test mode. This may reduce scan flip flop manufacturing costs, but is still expensive.

如果匹配讀寫存儲LAYER_SEL資訊鎖存器必要之電路時,就可進一步降低ERROR1和ERROR2訊號之監測成本。在一些案例中,例如,LAYER_SEL鎖存器可耦合到相應之掃描觸發器12000並透過掃描鏈讀寫其數值。或者,邏輯錐、掃描觸發器、XOR門和LAYER_SEL鎖存器可透過使用同一定址電路進行編址。 If the necessary circuit for reading and writing the latch for storing the LAYER_SEL information is matched, the monitoring cost of the ERROR1 and ERROR2 signals can be further reduced. In some cases, for example, a LAYER_SEL latch can be coupled to a corresponding scan flip-flop 12000 and read and write its value through the scan chain. Alternatively, logic cones, scan flip-flops, XOR gates and LAYER_SEL latches can be addressed by using the same addressing circuit.

附圖121B是透過在3D IC 12100中編址監測ERROR2和控制其相關LAYER_SEL鎖存器之電路示意圖。附圖121B包含3D IC 12100,即附圖121A中討論之第2層電路之一部分,包含掃描觸發器12122和XOR門12124。第1層上包含一個大致相同之電路(未體現在附圖121B中),涉及掃描觸發器12112和XOR門12114。 FIG. 121B is a schematic circuit diagram of monitoring ERROR2 and controlling its related LAYER_SEL latch through addressing in 3D IC 12100. FIG. 121B includes 3D IC 12100 , a portion of the layer 2 circuitry discussed in FIG. 121A , including scan flip-flops 12122 and XOR gates 12124 . Level 1 contains substantially identical circuitry (not shown in FIG. 121B ) involving scan flip-flops 12112 and XOR gates 12114 .

附圖121B也包含LAYER_SEL鎖存器12170,其透過LAYER_SEL訊號耦合到掃描觸發器12122。存儲在鎖存器12170中之資料值決定了,掃描觸發器12122在正常運行下會採用哪個邏輯錐。鎖存器12170耦合到COL_ADDR線12174(列地址線)、ROW_ADDR線12176(行地址線)和COL_BIT線12178。這些線用與所屬領域已知之技術中任一SRAM電路相同之方式來讀寫鎖存器12170之內容。在一些案例中,會存在一條互補的帶反二進位資料之COL_BIT線(未體現在附圖121B中)。在邏輯設定中,不管採用的是全定制設定、半定制設定、閘陣列還是ASIC 設定或其他設定方法,掃描觸發器都不會像存儲晶片在存儲區採用之方式一樣,整齊地排成行列。在一些案例中,可藉由工具將掃描觸發器分配到,以編址為目的之虛行列中,然後不同之虛行列就會,以設定中任何其他訊號相同之方式進行佈線。 Figure 121B also includes LAYER_SEL latch 12170, which is coupled to scan flip-flop 12122 via the LAYER_SEL signal. The data value stored in latch 12170 determines which cone of logic will be used by scan flip flop 12122 during normal operation. Latch 12170 is coupled to COL_ADDR line 12174 (column address line), ROW_ADDR line 12176 (row address line) and COL_BIT line 12178 . These lines read and write the contents of latch 12170 in the same manner as any SRAM circuit known in the art. In some cases, there will be a complementary COL_BIT line with inverted binary data (not shown in Figure 121B). In the logic setting, whether it is a full-custom setting, a semi-custom setting, a gate array or an ASIC Setting or other setting methods, the scan flip-flops are not neatly arranged in rows like the way memory chips use in the memory area. In some cases, the scan flip flops can be assigned by the tool to dummy rows for addressing purposes, and then the different dummy rows will be routed in the same way as any other signal in the setup.

採用包含N型通路電晶體12182、12184、12186和P型通路電晶體12190和12192之電路,就可以在與鎖存器(latch)12170一樣之地址上讀取ERROR2線12172。N型通路電晶體12182包含一個耦合到ERROR2線12172之柵極端子、一個耦合到地面之源極端子和一個耦合到N型通路電晶體12184源極之漏極端子。N型通路電晶體12184包含一個耦合到COL_ADDR線12174之柵極端子、一個耦合到N型通路電晶體12182之源極端子和一個耦合到N型通路電晶體12186源極之漏極端子。N型通路電晶體12186包含一個耦合到ROW_ADDR線12176之柵極端子、一個耦合到N型通路電晶體12184漏極之源極端子和一個經由線12188耦合到P型通路電晶體12190漏極和P型通路電晶體12192柵極之漏極端子。P型通路電晶體12190包含一個耦合到地面之柵極端子、一個耦合到正電源之源極端子和一個耦合到線12188之漏極端子。P型通路電晶體12192包含一個耦合到線12188之柵極端子、一個耦合到正電源之源極端子和一個耦合到COL_BIT線12178之漏極端子。 Using a circuit comprising N-type pass transistors 12182, 12184, 12186 and P-type pass transistors 12190 and 12192, ERROR2 line 12172 can be read at the same address as latch 12170. N-type pass transistor 12182 includes a gate terminal coupled to ERROR2 line 12172 , a source terminal coupled to ground, and a drain terminal coupled to the source of N-type pass transistor 12184 . N-type pass transistor 12184 includes a gate terminal coupled to COL_ADDR line 12174 , a source terminal coupled to N-type pass transistor 12182 , and a drain terminal coupled to the source of N-type pass transistor 12186 . N-type pass transistor 12186 includes a gate terminal coupled to ROW_ADDR line 12176, a source terminal coupled to N-type pass transistor 12184 drain, and a P-type pass transistor 12190 drain and P Type pass transistor 12192 gate drain terminal. P-type pass transistor 12190 includes a gate terminal coupled to ground, a source terminal coupled to the positive power supply, and a drain terminal coupled to line 12188 . P-type pass transistor 12192 includes a gate terminal coupled to line 12188 , a source terminal coupled to the positive power supply, and a drain terminal coupled to COL_BIT line 12178 .

如果附圖121B中之ERROR2專線12172未編址(即,要麼COL_ADDR線12174等同於接地電壓電平(邏輯值- 0)),要麼ROW_ADDR線12176等同於接地電壓電源之電壓電平(邏輯值-0),那麼包含三個N型通路電晶體12182、12184和12186之電晶體疊層是不導電的。當N型通路電晶體疊層不導電時,那麼作為一個較弱之上拉組件,P型通路電晶體12190會起到將線12188上之電壓電平,拉到正電源電壓(邏輯值-1)之作用,從而使P型通路電晶體12192不導電,給COL_BIT線12178帶來高阻抗。 If the ERROR2 dedicated line 12172 among the accompanying drawings 121B is not addressed (that is, either the COL_ADDR line 12174 is equal to the ground voltage level (logic value- 0)), or the ROW_ADDR line 12176 is equal to the voltage level of the ground voltage supply (logic value -0), then the transistor stack comprising three N-type pass transistors 12182, 12184 and 12186 is non-conductive. When the N-type pass transistor stack is non-conductive, then as a weaker pull-up component, the P-type pass transistor 12190 will pull the voltage level on the line 12188 to the positive supply voltage (logic value -1 ), so that the P-type pass transistor 12192 is non-conductive and brings high impedance to the COL_BIT line 12178.

較弱之下拉組件(未體現在附圖121B中)耦合到COL_BIT線12178上。當耦合到COL_BIT線12178之所有存儲晶片,顯示高阻抗時,此下拉組件就會將電壓電平,拉至地面(邏輯值-0)。 A weaker pull-down component (not shown in FIG. 121B ) is coupled to COL_BIT line 12178 . When all memory chips coupled to the COL_BIT line 12178 exhibit high impedance, the pull-down component pulls the voltage level to ground (logic value -0).

如果附圖121B中之特定ERROR2線12172編址(即,COL_ADDR線12174和ROW_ADDR線12176位於正電源電壓電平(邏輯值-1)),那麼包含三個N型通路電晶體12182、12184和12186之電晶體疊層,在ERROR2之邏輯值為-0時不導電,在ERROR2邏輯值為-1時導電。這樣的話,ERROR2之邏輯值就能,透過P型通路電晶體12190和12192傳播到COL_BIT線12178上。 If the particular ERROR2 line 12172 in FIG. 121B is addressed (i.e., COL_ADDR line 12174 and ROW_ADDR line 12176 are at a positive supply voltage level (logic value -1)), then three N-type pass transistors 12182, 12184, and 12186 are included The transistor stack does not conduct when the logic value of ERROR2 is -0, and conducts when the logic value of ERROR2 is -1. In this way, the logic value of ERROR2 can be propagated to COL_BIT line 12178 through P-type pass transistors 12190 and 12192.

附圖63B之編址方案之一個優勢在於:透過對行和列之同步編址,以及所有列位線12178之監控,就能實現廣播就緒模式。當所有列位線12178為邏輯值-0時,所有ERROR2訊號為邏輯值-0,表示第2層上沒有壞掉之邏輯錐。隨著現場可校錯誤之相對變少,透過使用掃描觸發器方法,就能節省大量之錯誤定位時間。如果一條或多條位 線為邏輯值-1,那麼故障邏輯錐只會存在於那些列上,而行地址則會快速循環找到它們之準確地址。這個方案之另一優勢在於:在開啟或重定模式下,大量或所有LAYER_SEL鎖存器,可同時快速初始化到缺省值邏輯值-1。 One advantage of the addressing scheme of FIG. 63B is that by synchronous addressing of rows and columns, and monitoring of all column bit lines 12178, a broadcast ready mode can be achieved. When all column bit lines 12178 are logic-0, all ERROR2 signals are logic-0, indicating that there are no broken logic cones on layer 2. With relatively few field correctable errors, a large amount of error location time can be saved by using the scan flip-flop approach. If one or more bits If the line is logical value -1, then the fault logic cone will only exist on those columns, and the row address will quickly cycle to find their exact address. Another advantage of this scheme is that in enable or reset mode, a large number or all LAYER_SEL latches can be quickly initialized to the default value logic-1 at the same time.

在故障邏輯錐(若有的話)存在之每個位置,缺陷被隔離到一個特定層上,這樣的話,正確運行之邏輯錐就能被位於第1層和第2層上之相應掃描觸發器選擇。如果3D IC 12100或外部系統中有一個大的非易失性記憶體,那麼自動測試碼生成(ATPG)向量,就會以與工廠修復案例一樣之方式,得到應用。在這種情況下,掃描本身具有確定位置和正確運行層之能力。不幸的是,這個掃描需要大量之向量以及相當大的非易失性記憶體,而這種記憶體並不是在所有案例中都具備。 At each location where a faulty cone of logic (if any) exists, the defect is isolated to a specific layer so that a correctly functioning cone of logic can be triggered by the corresponding scan flip-flops located on layers 1 and 2 choose. If there is a large non-volatile memory in the 3D IC 12100 or in an external system, then automatic test pattern generation (ATPG) vectors are applied in the same way as in the factory repair case. In this case, the scan itself has the ability to determine the location and run the layers correctly. Unfortunately, this scan requires a large number of vectors and considerable non-volatile memory, which is not available in all cases.

採用某一形式之內建自測(BIST)方法之優勢在於內含於3D IC 12100中,而不需要存儲大量測試向量。不幸的是,BIST測試傾向於“合格”或“不合格”判斷,雖然知道有錯誤之存在,但卻不是特別擅長診斷故障之位置或性質。幸運的是,在上述錯誤訊號監測過程中結合BIST技術和相應之設定方法,就能快速確定LAYER_SEL鎖存器之正確值。 The advantage of using some form of built-in self-test (BIST) method is that it is embedded in the 3D IC 12100 without the need to store a large number of test vectors. Unfortunately, BIST testing tends to be a "pass" or "fail" judgment, knowing that an error exists but not being particularly good at diagnosing the location or nature of the failure. Fortunately, the correct value of the LAYER_SEL latch can be quickly determined by combining the BIST technology and the corresponding setting method in the above error signal monitoring process.

附圖122為3D IC中採用之例,參閱附圖119中之11900和附圖121A中之12100等邏輯設定典型部分之示意圖。邏輯設定可見帶有大體相同門級案例之第1層和第2層。最好 是設定中之所有觸發器(未體現在附圖122中),採用與附圖120中掃描觸發器12000相似或相同之掃描觸發器。最好每層上之所有掃描觸發器,與另一層上之相應掃描觸發器有一定互連性,結合附圖121A一同表述。最好每個掃描觸發器都配備一個相關之錯誤訊號生成器(比如XCR門),來檢測錯誤邏輯錐和LAYER_SEL寄存器之存在,從而控制哪個邏輯錐受饋于正常運行模式下之觸發器,結合附圖121A和121B一同表述。 Accompanying drawing 122 is an example adopted in 3D IC, refer to the schematic diagrams of typical logic settings such as 11900 in accompanying drawing 119 and 12100 in accompanying drawing 121A. Logical settings can be seen on Tier 1 and Tier 2 with roughly the same gate-level cases. most It is all flip-flops (not shown in accompanying drawing 122) in setting, adopt the scanning flip-flop similar or the same as scanning flip-flop 12000 in the accompanying drawing 120. Preferably, all scan flip-flops on each layer have a certain degree of interconnection with the corresponding scan flip-flops on another layer, which is described in conjunction with FIG. 121A. Preferably, each scan flip-flop is equipped with an associated error signal generator (such as an XCR gate) to detect the presence of an error logic cone and the LAYER_SEL register, thereby controlling which logic cone is fed to the flip-flop in normal operation mode, combined with Figures 121A and 121B are presented together.

附圖122中有一個典型之邏輯功能塊(LFB)12200。典型的是,LFB 12200有很多輸入,案例參考號為12202,以及很多輸出,案例參考號為12204。最好LFB 12200以層次結構方式設定,表明它具有特殊之較小邏輯功能塊,在文中以12210和12220具體說明。與視為處於層次結構較高級之LFB 12200頂層之電路相比,LFB 12210和12220之內部電路視為處於層次結構之較低級。LFB 12200僅為舉例用。很多其他配置也是可能的。而LFB 7500內部,至少(至多)會有兩個初始化之LFB。而且未體現在附圖122中之LFB 12200內部,也會有初始化之獨立邏輯門和其他電路,以避免公開之過度複雜化。LFB12210和12220具有內部初始化較小之模組,在層次結構中形成甚至更低之級別。同樣地,邏輯功能塊12200其自身,也可在另一LFB中以總體設定層次結構中甚至更高之平得到初始化。 An exemplary logic function block (LFB) 12200 is shown in Figure 122 . Typically, an LFB 12200 has many inputs, case ref 12202, and many outputs, case ref 12204. Preferably, the LFB 12200 is set in a hierarchical manner, indicating that it has specific smaller logic function blocks, specified as 12210 and 12220 in the text. The internal circuits of LFBs 12210 and 12220 are considered to be at lower levels of the hierarchy compared to the circuitry at the top level of LFB 12200 which is considered to be at a higher level of the hierarchy. LFB 12200 is for example only. Many other configurations are also possible. Inside the LFB 7500, there are at least (at most) two initialized LFBs. Also inside the LFB 12200 which is not shown in Figure 122, there will also be separate logic gates for initialization and other circuits to avoid over-complicating the disclosure. The LFB12210 and 12220 have internally initialized smaller modules that form even lower levels in the hierarchy. Likewise, the Logical Function Block 12200 itself may also be initialized in another LFB at an even higher level in the overall settings hierarchy.

LFB 12200中包含線性回饋移位寄存器(LFSR)電路12230,以所屬領域為人所熟知之技術方法,為LFB 12200 生成偽隨機輸入向量。在附圖122中,一比特LFSR 12230與LFB 12200之每個輸入12202相關。如果輸入12202直接耦合到一個觸發器上(最好與12000相似之掃描觸發器),那麼該掃描觸發器在更改後,就能具備額外之LFSR功能來生成偽隨機輸入向量。如果輸入12202直接耦合到組合邏輯上,它就會在測試模式下截取,而其值則由測試期間LFSR 12230中之一個相應比特確定並取代。或者,LFSR電路12230將在測試期間截取所有輸入訊號,而不考量其連接到內部LFB 12200之電路類型。 The LFB 12200 includes a linear feedback shift register (LFSR) circuit 12230, which is known in the art as the LFB 12200 Generate pseudorandom input vectors. In FIG. 122 , one bit LFSR 12230 is associated with each input 12202 of LFB 12200 . If the input 12202 is directly coupled to a flip-flop (preferably a scan flip-flop similar to the 12000), then the scan flip-flop can be modified to have the additional LFSR capability to generate pseudo-random input vectors. If input 12202 is directly coupled to combinational logic, it is intercepted in test mode and its value is determined and replaced by a corresponding bit in LFSR 12230 during test. Alternatively, the LFSR circuit 12230 will intercept all input signals during testing regardless of the type of circuit it is connected to the internal LFB 12200.

因此在BIST測試中,LFB 12200之所有輸入,可採用LSFR 12230生成之偽隨機輸入向量。依照此項技術所知,LSFR 12230可為單個LSFR或多個較小之LSFR,具體情況視設定選擇而定。LSFR 12230優選採用一個本原多項式,來生成一個最大長度序列之偽隨機向量。LSFR 12230需要播種到一個已知數值,這樣的話偽隨機向量之序列,就是確定性的。播種邏輯可採取LSFR 12230觸發器內部之價格便宜之方法,並透過回應重定訊號等方式進行初始化。 Therefore, in the BIST test, all inputs of LFB 12200 can use pseudo-random input vectors generated by LSFR 12230. As known in the art, LSFR 12230 can be a single LSFR or multiple smaller LSFRs, depending on the setting chosen. LSFR 12230 preferably uses a primitive polynomial to generate a pseudorandom vector of maximum length sequence. LSFR 12230 needs to be seeded to a known value so that the sequence of pseudorandom vectors is deterministic. The seeding logic can be cheaply implemented inside the LSFR 12230 flip-flop and initialized by responding to reset signals etc.

LFB 12200中還包含循環冗餘校驗(CRC)電路12232,來生成響應LFSR 12230,以此項技術中已被人熟知的方式,生成之偽隨機輸入向量而產生LFB 12200輸出之特徵。在附圖122中,一比特CRC 12232與LFB 12200之每個輸出12204相關。如果輸出12204直接耦合到一個觸發器(最好是與12000相似之掃描觸發器),那麼該掃描觸發器在更改後,就能具備額外之CRC功能來生成特徵。或 者,CRC之所有比特會消極監控輸出,不管LFB 12200內部之訊號來源。 LFB 12200 also includes cyclic redundancy check (CRC) circuitry 12232 to generate pseudo-random input vectors in response to LFSR 12230 , in a manner well known in the art, to generate characteristics of LFB 12200 output. In FIG. 122, a one-bit CRC 12232 is associated with each output 12204 of the LFB 12200. If the output 12204 is directly coupled to a flip-flop (preferably a scan flip-flop similar to the 12000), then the scan flip-flop can be modified to have the additional CRC function to generate the signature. or Alternatively, all bits of the CRC will passively monitor the output regardless of the signal source inside the LFB 12200.

因此在BIST測試中,LFB 12200之所有輸出可在分析後,確定回應LSFR 12230生成之偽隨機輸入,回應提供之刺激源之正確性。依照此項技術可知,CRC 12232可為單個CRC或多個較小之CRC,具體情況視設定選擇而定。依照此項技術可知,CRC電路為LSFR之特殊情況,它的附加電路能將觀察到之資料,併入基極LSFR生成之偽隨機碼序列中。CRC 12232優選採用一個本原多項式,來生成一個最大序列之偽隨機編碼。CRC 12232需要播種到一個已知數值,這樣的話偽隨機輸入向量生成之特徵,就是確定性的。播種邏輯可採取LSFR 12230觸發器內部之價格便宜之方法,並透過回應重定訊號等方式進行初始化。測試完成後,將CRC 12232中之數值與特徵已知值比對。如果CRC 12232中之所有比特都匹配,則識別有效,而且LFB 12200視為運行無誤。如果CRC 12232中之一個或多個比特不匹配,則識別無效,而且LFB 12200視為運行有誤。預期特徵之值可採取CRC 12232觸發器內部之價格便宜之做法,並與回應一個評價訊號之CRC 12232進行內部比較。 Therefore, in the BIST test, all the outputs of the LFB 12200 can be analyzed to determine the correctness of the stimulus generated in response to the pseudo-random input generated by the LSFR 12230. According to this technology, CRC 12232 can be a single CRC or multiple smaller CRCs, depending on the setting selection. According to this technology, the CRC circuit is a special case of LSFR, and its additional circuit can incorporate the observed data into the pseudo-random code sequence generated by the base LSFR. CRC 12232 preferably uses a primitive polynomial to generate a maximum sequence pseudo-random code. CRC 12232 needs to be seeded to a known value so that the characteristics of the pseudo-random input vector generation are deterministic. The seeding logic can be cheaply implemented inside the LSFR 12230 flip-flop and initialized by responding to reset signals etc. After the test is complete, compare the value in CRC 12232 with the known value of the characteristic. If all bits in the CRC 12232 match, the identification is valid and the LFB 12200 is considered to be operating without error. If one or more bits in the CRC 12232 do not match, the identification is invalid and the LFB 12200 is considered to be malfunctioning. The value of the expected characteristic can be taken cheaply inside the CRC 12232 flip-flop and compared internally with the CRC 12232 responding to an evaluation signal.

如附圖122所示,LFB 12210包含LFSR電路12212、CRC電路12214和邏輯功能12216。由於它的輸入/輸出結構與LFB 12200之輸入/輸出結構類似,則可採用相同方式更小之比例進行測試。如果12200初始化成一個具有相同輸入/輸出結構之更大塊,12200就可作為那個更大塊之一 部分進行測試或單獨測試,具體情況視設定選擇而定。如果沒有單獨測試之必要,那麼層次結構中之所有塊,也不一定非得具備輸入/輸出結構。有一個例子就是說明LFB 12220在LFB 12200中初始化,而LFB 12220在輸入上沒有LFSR電路,在輸出上沒有CRC電路,並且是與LFB 12200剩餘部分同時測試的。 As shown in FIG. 122 , LFB 12210 includes LFSR circuit 12212 , CRC circuit 12214 and logic function 12216 . Since its input/output structure is similar to that of LFB 12200, it can be tested in the same way with a smaller scale. If the 12200 is initialized as a larger block with the same input/output structure, the 12200 can be one of that larger block Partially or individually, depending on the setup selection. All blocks in the hierarchy do not necessarily have to have an input/output structure, if there is no need for individual testing. An example is where the LFB 12220 is initialized in the LFB 12200, and the LFB 12220 has no LFSR circuit on the input, no CRC circuit on the output, and is tested at the same time as the rest of the LFB 12200.

本技術領域之技術普通者知悉,其他BIST測試方法在此項技術中被人熟知,而且任意一種方法都能用來確定,LFB 12200運行良好或有故障。 Those of ordinary skill in the art will appreciate that other BIST testing methods are known in the art, and that either method can be used to determine whether the LFB 12200 is functioning properly or failing.

透過使用塊BIST方法,來修復像附圖121A中3D IC 12100之3D IC,將該部件放在測試模式下,比較第1層和第2層上各個掃描觸發器12000之DATA1和DATA2訊號,並對上述案例中描述之ERROR1和ERROR2合成訊號進行監控,或在可能之情況下採用其他方法進行監控。故障邏輯錐之位置,是依照它在邏輯設定層次結構中之位置而決定的。例如,如果故障邏輯錐位於LFB 12210內部,那麼只有那個塊之BIST程式,才可同時在第1層和第2層上運行。兩次測試之結果決定了,哪個塊(並暗示哪個邏輯錐)運行良好,哪個塊運行有障礙。然後相應掃描觸發器12000之LAYER_SEL鎖存器就可設定,這樣每個鎖存器都能接收到來自功能邏輯錐之修復訊號,而忽略故障訊號,從而在短期內無需昂貴ATPG測試之情況下,完成普通硬體成本之層測定。 To repair a 3D IC like 3D IC 12100 in Figure 121A by using the block BIST method, place the part in test mode, compare the DATA1 and DATA2 signals of each scan flip-flop 12000 on layer 1 and layer 2, and Monitor ERROR1 and ERROR2 composite signals as described in the case above, or use other methods where possible. The location of the failure logic cone is determined by its position in the logic setting hierarchy. For example, if the cone of fault logic is inside LFB 12210, then only the BIST program for that block can run on both layer 1 and layer 2. The results of the two tests determine which block (and, by implication, which cone of logic) is functioning well and which block is functioning with obstacles. Then the LAYER_SEL latch of the corresponding scan flip-flop 12000 can be set, so that each latch can receive the repair signal from the functional logic cone, and ignore the fault signal, so that in the short term without expensive ATPG test, Complete the layer determination of common hardware cost.

附圖123介紹了一個選擇性之案例,具備獨立邏輯錐 之現場修復能力。一個以12300表示之典型3D IC包含兩層,分別以第1層和第2層表示,在附圖中以虛線區分開來。第1層和第2層用此項技術中已知之方法,黏合到一起形成3D IC 12300並藉由TSV或其他間層互連技術進行了互相連接。第一層由控制邏輯塊12310,掃描觸發器12311和12312,複用器12313和12314,及邏輯錐12315組成。同樣地,第2層由控制邏輯塊12320,掃描觸發器12321和123222,複用器12323和12324及邏輯錐12325組成。 Figure 123 presents an optional case with independent logic cones on-site repair capability. A typical 3D IC denoted by 12300 contains two layers, respectively denoted as layer 1 and layer 2, which are distinguished by dotted lines in the figure. Layer 1 and Layer 2 are bonded together to form 3D IC 12300 using methods known in the art and are interconnected by TSV or other interlayer interconnect technology. The first layer consists of control logic block 12310 , scan flip-flops 12311 and 12312 , multiplexers 12313 and 12314 , and logic cone 12315 . Likewise, layer 2 consists of control logic block 12320 , scan flip-flops 12321 and 123222 , multiplexers 12323 and 12324 and logic cone 12325 .

在第1層中,掃描觸發器12311和12312與控制邏輯塊12310串聯耦合,形成了一條掃描鏈。掃描觸發器12311和12312可以是此項技術中已知的,一種普通類型之掃描觸發器。掃描觸發器12311和12312之Q輸出各自耦合到,複用器12313和12314之D1資料登錄上。典型之邏輯錐12315有一個輸出耦合到複用器12313之典型輸入上,另一個輸出耦合到掃描觸發器12312之D輸入上。 In layer 1, scan flip-flops 12311 and 12312 are coupled in series with control logic block 12310 to form a scan chain. Scan flip-flops 12311 and 12312 may be a common type of scan flip-flop known in the art. The Q outputs of scan flip-flops 12311 and 12312 are coupled to the D1 data entry of multiplexers 12313 and 12314, respectively. A typical cone of logic 12315 has one output coupled to a typical input of a multiplexer 12313 and another output coupled to the D input of a scan flip-flop 12312.

在第2層,掃描觸發器12321和12322與控制邏輯塊12320串聯耦合形成了一條掃描鏈。掃描觸發器12321和12322可以是此項技術中已知的,一種普通類型之掃描觸發器。掃描觸發器12321和12312之Q輸出各自耦合到複用器12323和12324之D1資料登錄上。典型之邏輯錐12325有一個輸出耦合到複用器12323之典型輸入上,另一個輸出耦合到掃描觸發器12322之D輸入上。 In layer 2, scan flip-flops 12321 and 12322 are coupled in series with control logic block 12320 to form a scan chain. Scan flip-flops 12321 and 12322 may be a common type of scan flip-flop known in the art. The Q outputs of scan flip-flops 12321 and 12312 are coupled to the D1 data entry of multiplexers 12323 and 12324, respectively. A typical cone of logic 12325 has one output coupled to a typical input of a multiplexer 12323 and another output coupled to the D input of a scan flip-flop 12322.

掃描觸發器12311之Q輸出耦合到,複用器12323之D0輸入上,掃描觸發器12321之Q輸出耦合到,複用器12313 之D0輸入上,掃描觸發器12312之Q輸出耦合到,複用器12324之D0輸入上,且掃描觸發器12322之Q輸出耦合到,複用器12314之D0輸入上。控制邏輯塊12310以一種協調層間測試功能之方式,耦合到控制邏輯塊12320上。在一些案例中,控制邏輯塊12310和12320可自行測試或彼此測試,且當其中一個出現故障時,另一個也能同時控制兩層上之測試。這些層間耦合可透過TSV或其他層間互連技術得到實現。 The Q output of scan flip-flop 12311 is coupled to the DO input of multiplexer 12323, and the Q output of scan flip-flop 12321 is coupled to multiplexer 12313 The Q output of scan flip-flop 12312 is coupled to the DO input of multiplexer 12324 , and the Q output of scan flip-flop 12322 is coupled to the DO input of multiplexer 12314 . Control logic block 12310 is coupled to control logic block 12320 in a manner that coordinates interlayer test functions. In some cases, the control logic blocks 12310 and 12320 can test themselves or each other, and when one fails, the other can also control the testing on both layers. These interlayer couplings can be achieved through TSVs or other interlayer interconnect technologies.

第1層上之邏輯功能與第2層上之邏輯功能大體一致。3D IC 12300在附圖123中之案例與3D IC 11900在附圖11900中之案例相似,主要區別在於:在附圖120之典型掃描觸發器12000和附圖119之3D IC 11900中,用於邏輯錐替代之層間可編程或選擇性交叉耦合之複用器,位置是緊跟掃描觸發器後面,而不是在前面。 The logical functions on layer 1 are roughly the same as those on layer 2. The case of 3D IC 12300 in accompanying drawing 123 is similar to the case of 3D IC 11900 in accompanying drawing 11900, the main difference is: in the typical scan flip-flop 12000 of accompanying drawing 120 and the 3D IC 11900 of accompanying drawing 119, for logic The interlayer programmable or selective cross-coupling multiplexer for cone replacement is located immediately after the scan flip-flops instead of before them.

附圖124是以12400表示之典型3D IC之示意圖,它也是採用這種方法作圖的。一個典型之3D IC 12400包含兩層,分別以第1層和第2層表示,在附圖中以虛線區分開來。第1層和第2層接合到一塊形成3D IC 12300,並藉由TSV或其他間層互連技術進行了互相連接。第1層由第1層邏輯錐12410,掃描觸發器12412,複用器12414和XOR門12416組成。同樣地,第2層由第2層邏輯錐12420,掃描觸發器12422,複用器12424和XOR門12426組成。 Accompanying drawing 124 is a schematic diagram of a typical 3D IC represented by 12400, which is also constructed by this method. A typical 3D IC 12400 includes two layers, respectively denoted as layer 1 and layer 2, which are distinguished by dotted lines in the drawing. Layer 1 and Layer 2 are bonded together to form 3D IC 12300 and interconnected by TSV or other interlayer interconnection technology. Level 1 consists of Level 1 logic cones 12410 , scan flip flops 12412 , multiplexers 12414 and XOR gates 12416 . Likewise, layer 2 consists of layer 2 logic cones 12420 , scan flip flops 12422 , multiplexers 12424 and XOR gates 12426 .

第1層邏輯錐12410和第2層邏輯錐12420實行,大致一樣之邏輯功能。為了檢測發現故障邏輯錐,在測試模式下 分別於掃描觸發器12412和12422中捕獲邏輯錐12410和12420之輸出。掃描觸發器12412和1262之Q輸出在附圖124中分別以Q1和Q2表示。藉由XOR門12416和12426來比較Q1和Q2,從而分別生成錯誤訊號ERROR1和ERROR2。複用器12414和12424各有一個耦合到,層選擇鎖存器(未體現在附圖124中)之選擇輸入,這個鎖存器優選,位於相應複用器所在層內,而複用器則相對在鄰近範圍內,使得Q1和Q2選擇性或可編程之耦合到DATA1或DATA2上。 Level 1 logic cones 12410 and level 2 logic cones 12420 perform substantially the same logic functions. To detect faulty logic cones, in test mode The outputs of logic cones 12410 and 12420 are captured in scan flip-flops 12412 and 12422, respectively. The Q outputs of scan flip flops 12412 and 1262 are denoted Q1 and Q2, respectively, in FIG. 124 . Q1 and Q2 are compared by XOR gates 12416 and 12426 to generate error signals ERROR1 and ERROR2 respectively. Multiplexers 12414 and 12424 each have a select input coupled to a layer select latch (not shown in FIG. Relatively within close range, Q1 and Q2 are selectively or programmable coupled to DATA1 or DATA2.

依照附圖121A、121B和122所描述案例中的,所有ERROR1和ERROR2評價方法,可用來評價附圖124中之ERROR1和ERROR2。同樣地,一旦評價ERROR1和ERROR2,就能將正確值應用到,複用器12414和12424之層選擇鎖存器中,從而實現邏輯錐替代,若必要的話。在這個案例中,邏輯錐替代時也包含替代相關掃描觸發器。 According to the cases described in accompanying drawings 121A, 121B and 122, all ERROR1 and ERROR2 evaluation methods can be used to evaluate ERROR1 and ERROR2 in accompanying drawing 124. Likewise, once ERROR1 and ERROR2 are evaluated, the correct values can be applied to the layer select latches of multiplexers 12414 and 12424, enabling logic cone replacement, if necessary. In this case, the cone of logic substitution also contains the substitution-associated scan flip-flop.

附圖125A給出的是一個採用更加經濟之方法,來實現現場修復之典型案例。一個以12500表示之典型3D IC 12400包含兩層,分別以第1層和第2層表示,在附圖中以虛線區分開來。第1層和第2層各自包含至少一個電路層。第1層和第2層用此項技術中已知之方法,接合到一塊形成3D IC 12500並藉由TSV或其他間層互連技術,進行了互相連接。每一層還包含一個邏輯功能塊12510案例,每個案例又反過來構成一個邏輯功能塊12520案例。以一種類似與附圖122中LFB 12200所述之方法,LFB 12520在其輸入(未體現在附圖125A中)上包含LSFR電路,在其輸出 (未體現在附圖125A中)上包含CRC電路。 Accompanying drawing 125A provided is a typical case that adopts more economical method to realize on-site restoration. A typical 3D IC 12400 denoted by 12500 includes two layers, respectively denoted as layer 1 and layer 2, which are distinguished by dotted lines in the figure. Layer 1 and Layer 2 each include at least one circuit layer. Layer 1 and Layer 2 are bonded together to form 3D IC 12500 by methods known in the art and interconnected by TSV or other interlayer interconnection technology. Each layer also contains a logic function block 12510 instance, and each case in turn constitutes a logic function block 12520 instance. In a manner similar to that described for LFB 12200 in Figure 122, LFB 12520 includes LSFR circuitry on its input (not shown in Figure 125A) and (not shown in Figure 125A) contains a CRC circuit.

LFB 12520之每一案例都有很多,與輸入相關之複用器12522,以及與輸出相關之複用器12524。而這些複用器則以第1層或第2層上之對應部分,可編程或選擇性地替代,第1層或第2層上之LFB 12520全部案例。 Each instance of LFB 12520 has many, multiplexers 12522 associated with inputs, and multiplexers 12524 associated with outputs. And these multiplexers can be programmed or selectively replaced with the corresponding parts on the first layer or the second layer, all cases of LFB 12520 on the first layer or the second layer.

在開啟、系統重定或來自3D IC 12500內部控制邏輯之請求,或3D IC 12500分佈所在系統之其他地方之請求時,即可對層次結構中之不同塊進行測試。處於層次結構任一電平,並具有BIST能力之故障塊,都可被另一層上之對應案例可編程並選擇性地替代。由於是在封鎖電平確定的,則這個決議可由每個塊(未體現在附圖125A中)上之BIST控制邏輯局部做出,儘管還需協調層次結構中之較高電平塊,有關多數複用器12522在設定層次結構中同一範圍內之多次修復情況下,將輸入提供給功能性LFB 12520之哪一層。由於第1層和第2層優選出廠時,完全可操作或幾乎完全可操作,則可採用一個簡單之方法就能,指定兩層中之一層,比如第1層作為主要功能層。之後,每塊之BIST控制器會局部協調,並決定哪個塊擁有經由第1層複用器12522和12524耦合到,第1層之輸入和輸出。 Different blocks in the hierarchy can be tested upon power-up, system reset, or request from the control logic inside the 3D IC 12500, or elsewhere in the system where the 3D IC 12500 is distributed. A faulty block at any level of the hierarchy, and BIST-capable, can be programmed and selectively replaced by a corresponding case at another level. Since it is determined at the blocking level, this decision can be made locally by the BIST control logic on each block (not shown in Figure 125A), although higher level blocks in the hierarchy still need to be coordinated, most Multiplexer 12522 provides input to which level of functional LFB 12520 in case of multiple repairs within the same range in the hierarchy. Since layers 1 and 2 are preferably fully or nearly fully operational when shipped, a simple method can be used to designate one of the two layers, such as layer 1, as the primary functional layer. The BIST controller of each block then coordinates locally and decides which block has the input and output of layer 1 coupled to via layer 1 multiplexers 12522 and 12524.

本技術領域之技術普通者知悉,採用這種案例就能節省大量空間之做法。例如,由於取代,獨立邏輯錐而只對LFB進行了評價,那麼每個與附圖120中複用器12006,和附圖124中複用器12414一樣之獨立觸發器層間,選擇複用器就能與附圖121B中之LAYER_SEL鎖存器12179一同移 除,因為這個功能現由,附圖125A中之多數複用器12522和12524實現,所有複用器都可透過平行之一個或多個控制訊號,進行控制。同樣地,錯誤訊號生成器(例如附圖121A中之XOR門12114和12124以及附圖124中之12416和7826)和需要讀取它們之任一電路(例如將它們耦合到掃描觸發器),或附圖121B中之編址電路也應移除,因為在這個案例中,全部邏輯功能塊,而不是獨立邏輯錐,被替代了。 Those of ordinary skill in the art know that adopting this case can save a lot of space. For example, since only the LFB has been evaluated due to the replacement of independent logic cones, then each of the separate flip-flop levels between multiplexer 12006 in Figure 120 and multiplexer 12414 in Figure 124, select the multiplexer Can be shifted together with LAYER_SEL latch 12179 among accompanying drawing 121B Except, because this function is now implemented by multiplexers 12522 and 12524 in Figure 125A, all multiplexers can be controlled by one or more control signals in parallel. Likewise, error signal generators (such as XOR gates 12114 and 12124 in FIG. 121A and 12416 and 7826 in FIG. 124 ) and any circuitry that needs to read them (such as coupling them to scan flip-flops), or The addressing circuit in Figure 121B should also be removed, since in this case the entire logic functional block, rather than the individual logic cones, is replaced.

甚至在一些案例中也可將掃描鏈移除,儘管這是設定選擇決定的。在將掃描鏈移除之案例中,工廠測試和修復也必須依賴塊BIST電路。當檢測發現不良塊,修復層就必須用電子束靜心製作一個全新之塊。特別是,由於有更多之圖樣需要成形,這比製作替代之邏輯錐費時多了,而且空間節約量需要與測試時間損失比較,從而確定經濟上可行之方案。 Even scan chains can be removed in some cases, although this is a matter of configuration choice. In cases where the scan chains are removed, factory testing and repair must also rely on block BIST circuitry. When the detection finds a bad block, the repair layer must use the electron beam to calmly make a brand new block. In particular, since there are more patterns to be formed, it is more time consuming than making alternative logic cones, and the space savings need to be compared with the test time loss to determine an economically viable solution.

移除掃描鏈時,會附帶設定早期調試和樣機階段之風險,因為BIST電路在診斷問題性質方面,還有所欠缺。若設定本身有問題,掃描測試之不存在,將加大發現和解決問題之難度,而且失去市場時機之成本非常巨大,難以量化。鑒於與本發明現場修復方面無關之原因,謹慎提示離開掃描鏈。 Removing the scan chains comes with the risk of setting up the early debug and prototyping stages, as the BIST circuitry is still limited in diagnosing the nature of the problem. If there is a problem with the setting itself, the absence of scan testing will increase the difficulty of finding and solving the problem, and the cost of losing market opportunities is very huge and difficult to quantify. For reasons unrelated to the field repair aspect of the present invention, it is prudent to prompt to leave the scan chain.

使用塊BIST方法之案例之另一優勢,見附圖125B所述。一些較早案例之一個優勢在於,第1層和第2層上之大部分電路在正常運行期間,是有源電路。因此透過操作位 於兩層中一層上之唯一一個塊案例,對於較早案例來說,可大大減少功率。 Another advantage of the case of using the block BIST approach is described in Figure 125B. One advantage of some of the earlier cases was that most of the circuitry on layer 1 and layer 2 was active during normal operation. Therefore, through the operation bit In the case of only one block on one of the two layers, the power can be greatly reduced compared to the earlier case.

附圖125B包含3D IC 12500,第1層和第2層,LFB 12510和12520各2個案例,以及之前探討之多數複用器12522和12524。附圖125B每層同時包含一個與該層模式LFB 12520相關之功率選擇複用率12530。每個功率選擇複用器12530有一個耦合到,其相關LFB 12520功率端子之輸出,第一個選擇輸入耦合到正電源(附圖中以VCC表示),第二個輸入一個耦合到接地電位電源(附圖中以GND表示)。每個功率選擇複用器12530有一個耦合到控制邏輯(未體現在附圖125B中)之選擇輸入(未體現在附圖125B中),並以一式二份之形式存在於第1層和第2層上,儘管它可能位於3D IC 12500內部之其他地方,或3D IC 12500分佈所在系統之其他地方。 Figure 125B includes 3D IC 12500, Layer 1 and Layer 2, 2 instances each of LFB 12510 and 12520, and multiplexers 12522 and 12524 as previously discussed. Each layer of Figure 125B also includes a power selection multiplex rate 12530 associated with the mode LFB 12520 of that layer. Each power select multiplexer 12530 has an output coupled to the power terminal of its associated LFB 12520, with a first select input coupled to a positive supply (indicated as VCC in the figure), and a second input coupled to a ground potential supply (Denoted by GND in the attached figure). Each power select multiplexer 12530 has a select input (not shown in FIG. 125B ) coupled to control logic (not shown in FIG. 125B ) and exists in duplicate between Layer 1 and Layer 1 2, although it may be located elsewhere within the 3D IC 12500, or elsewhere in the system where the 3D IC 12500 is distributed.

本技術領域之技術普通者知悉,有很多方法可編程或選擇性地停止,位於此項技術已知之積體電路中之塊,且在附圖125B案例中使用之功率複用器12530,只為舉例示範目的。停止LFB 12520之任一方法為本文明內容。例如,電源開關可同時用於VCC和GND。或者,當VCC從LFB 12530去耦時,可忽略GND電源開關,並允許電源節點“飄下”至地面。在一些案例中,VCC可由一個電晶體控制,就像自身被調壓器控制之源極輸出器,或射極輸出器,而且VCC可透過遮罩或切斷電晶體進行移除。很多其他替代方案也是可行的。 Those of ordinary skill in the art know that there are many ways to programmably or selectively disable blocks located in integrated circuits known in the art, and the power multiplexer 12530 used in the case of Figure 125B is only for Example for demonstration purposes. Any method of stopping LFB 12520 is the content of this document. For example, a power switch can be used for both VCC and GND. Alternatively, when VCC is decoupled from the LFB 12530, the GND power switch can be ignored and the power node allowed to "float down" to ground. In some cases, VCC can be controlled by a transistor, like a source follower itself controlled by a voltage regulator, or an emitter follower, and VCC can be removed by masking or cutting off the transistor. Many other alternatives are also possible.

在一些是案例中,控制邏輯(未體現在附圖125B中)採用,每塊中存在之BIST電路,來縫合單一拷貝之設定(使用每塊之多數輸入和輸出複用器,其功能與LFB 12520相關之多數複用器12522和12524相似),包含所有LFB之功能性拷貝。如果映象完整,透過與它們相關之功率選擇複用器(與功率選擇複用器12530相似),切斷所有故障LFB和未用之功能性LFB之電源。因此,透過使用標準之二維積體電路技術,就能達到節約功率到單一拷貝設定需要之平。 In some cases, the control logic (not shown in FIG. 125B ) employs the BIST circuitry present in each block to stitch a single copy of the settings (using each block's multiple input and output multiplexers, which function the same as the LFB The multiplexers 12522 and 12524 associated with 12520 are similar) and contain functional copies of all LFBs. If the image is complete, power off all faulty LFBs and unused functional LFBs through their associated power select multiplexers (similar to power select multiplexer 12530). Thus, by using standard 2D IC technology, power savings to the level required for a single copy setup can be achieved.

或者,如果一層,例如第1層被選定為主層,那麼每塊中之BIST控制器就能獨立決定採用哪個模式之塊。然後設定多數複用器12522和12524之設定值,從而將已用塊耦合到第1層,並設定多數複用器12530之設定值來切斷未用塊。值得一提的是,與不採用功率選擇複用器12530或等同複用器相關之案例中,這可以節省一半功耗。 Alternatively, if a layer, such as layer 1, is selected as the main layer, then the BIST controller in each block can independently decide which mode of block to use. Majority multiplexers 12522 and 12524 are then set to couple used blocks to layer 1, and majority multiplexer 12530 is set to switch off unused blocks. It is worth mentioning that in the case associated with not using the power select multiplexer 12530 or an equivalent multiplexer, this can save half the power consumption.

此項技術中已知之測試技術,正是掃描測試詳細診斷能力與BIST測試簡單性之折中做法。在採用這些方案之案例中,每個BIST塊(比典型之LFB小,但卻包含數十至數百個邏輯錐)存儲了少量之初態,特別是掃描觸發器,而大部分之掃描觸發器可使用缺省值。藉由CAD工具來分析設定網表,從而確定必要之掃描觸發器,完成高效測試。 Test techniques known in the art are a compromise between the detailed diagnostic capabilities of scan tests and the simplicity of BIST tests. In the case of these schemes, each BIST block (smaller than a typical LFB, but containing tens to hundreds of logic cones) stores a small number of initial states, especially scan flip-flops, and most scan flip-flops can use the default value. Use CAD tools to analyze and set the netlist to determine the necessary scan triggers and complete efficient testing.

在測試模式下,BIST控制器移入初值後,開始設定計時。BIST控制器有一個特徵寄存器,有可能是CRC或其他電路,監控測試塊內部之比特。經過預設數量之時鐘週期 後,BIST控制器停止設定計時,移除存儲在掃描觸發器內之資料,同時將它們之內容加到塊特徵中,並將特徵與少量存儲特徵(存儲初態各一個)進行比對。 In the test mode, after the BIST controller moves into the initial value, it starts to set the timing. The BIST controller has a signature register, possibly a CRC or other circuit, that monitors the bits inside the test block. After a preset number of clock cycles Finally, the BIST controller stops setting the timing, removes the data stored in the scan flip-flops, and adds their content to the block signature at the same time, and compares the signature with a small number of stored signatures (one for each initial state).

該方法具有之優點是,不需要大量存儲掃描向量以及簡單之“合格”或“不合格”BIST測試。試塊沒有確定之單個故障邏輯錐那麼精細,但比大的邏輯功能塊要粗糙的多。一般情況下,測試粒度越精細(即取代故障電路之電路尺寸越小),那麼第1層和第2層上同一試塊出現延遲故障之幾率就越小。一旦確定了BIST塊之功能性狀態,就能將合適之值,寫入控制層間複用器之鎖存器上,從而替代一層上之故障BIST塊,若必要的話。在一些案例中,故障和未用BIST塊可切斷電源,從而節省耗電量。 This approach has the advantage that it does not require a large store of scan vectors and a simple "pass" or "fail" BIST test. Test blocks are not as fine-grained as the cone of logic for identifying individual faults, but are much coarser than large logic function blocks. In general, the finer the test granularity (i.e., the smaller the size of the circuit that replaces the faulty circuit), the smaller the probability of delayed failures on the same test block on layer 1 and layer 2. Once the functional state of a BIST block is determined, appropriate values can be written to the latches controlling the inter-layer multiplexers, thereby replacing faulty BIST blocks on a layer, if necessary. In some cases, faulty and unused BIST blocks can cut power, thereby saving power consumption.

至今對所述不同典型案例之探討,關於它們自身之發現並修復靜態測試模式下缺陷之邏輯錐或邏輯塊,本發明案例可找到,由於噪音或計時問題導致之故障位址。例如,在附圖119之3D IC 11900,和附圖123之3D IC 12300中,以此項技術中已知之方法,使用掃描鏈展開全速測試。方法一涉及透過掃描鏈移入向量,採用至少兩個全速時鐘脈衝,然後透過掃描鏈移出結果。這會捕獲低速測試時運行無誤之邏輯錐,但運行太慢卻導致,不能在全時鐘速度下在電路中作用。但這個方法使得慢邏輯錐之現場修復成為可能,需要存儲、運行並評價掃描向量必要之時間、智慧和存儲容量。 The different typical cases discussed so far have found and repaired defective logic cones or logic blocks in static test mode on their own, and the present invention case can find fault addresses due to noise or timing problems. For example, in the 3D IC 11900 of FIG. 119 and the 3D IC 12300 of FIG. 123 , scan chains are used to carry out full-speed testing in a manner known in the art. Method one involves shifting in the vector through the scan chain, taking at least two full-speed clock pulses, and then shifting the result out through the scan chain. This captures cones of logic that run fine when tested at low speeds, but run too slowly to function in the circuit at full clock speed. But this approach enables field repair of slow logic cones, requiring the time, intelligence and memory capacity necessary to store, run and evaluate scan vectors.

另一個方法就是在開啟、復位或請求時使用塊BIST測 試,從而在不斷增長之頻率中超頻每塊,直至出現故障,確定哪塊之層模式運行較快,然後在設定之每一案例中用較快之塊來代替較慢之塊。這個方法具有與塊BIST測試相關之更多普通時間、智慧和存儲要求,但是它還是要在測試模式下放置3D IC。 Another method is to use the block BIST test on turn-on, reset or request Try to overclock each block at increasing frequencies until failure occurs, determine which block's layer mode runs faster, and then replace the slower block with the faster block in each instance of the setup. This approach has more of the usual time, intelligence and memory requirements associated with block BIST testing, but it still places the 3D IC in test mode.

附圖126說明了一個案例,即由於慢邏輯錐導致之錯誤在電路處於正常運行模式下可即時監測。一個以12600表示之典型3D IC包含兩層,分別以第1層和第2層表示,在附圖中以虛線區分開來。各層包含一個或多個電路層,並接合到一塊形成3D IC 12600。各層可透過TSV或其他層間互連技術進行電耦。 Figure 126 illustrates a case where errors due to slow logic cones can be monitored in real time while the circuit is in normal operating mode. A typical 3D IC denoted by 12600 contains two layers, denoted as layer 1 and layer 2, which are distinguished by dotted lines in the figure. Each layer contains one or more circuit layers and is bonded together to form 3D IC 12600. Each layer can be electrically coupled through TSV or other interlayer interconnection technology.

附圖126主要為耦合到單個第2層邏輯錐12620輸出之電路操作上,儘管大體上一致之電路也出現在第1層中(未體現在附圖82中)。附圖126中還包含D輸入耦合到,第2層邏輯錐12620輸出,以及Q輸出透過層間線12612(附圖中以Q2表示)耦合到複用器12624之D1輸入之掃描觸發器12622上。複用器12624有一個輸入耦合到邏輯錐(未體現在附圖126中)之輸出DATA2,另一個輸入將第1層觸發器透過層間線12610耦合到觸發器12622(未體現在附圖中)之D0。 Figure 126 is primarily operational on circuitry coupled to the output of a single layer 2 logic cone 12620, although substantially identical circuitry is also present in layer 1 (not shown in Figure 82). Also included in Figure 126 is the D input coupled to the Layer 2 logic cone 12620 output, and the Q output coupled to the scan flip-flop 12622 of the D1 input of the multiplexer 12624 through an interlayer line 12612 (represented as Q2 in the figure). Multiplexer 12624 has one input coupled to the output DATA2 of the logic cone (not shown in FIG. 126 ) and another input coupling layer 1 flip-flops to flip-flops 12622 (not shown in FIG. 1 ) via interlayer lines 12610 of D0.

XOR門12626有一個輸入耦合到Q1之第一個輸入,耦合到Q2之第二個輸入以及耦合到AND門12646第一次輸入之輸出。AND門12646,同時另一個輸入一個耦合到TEST_EN線12648之第二個輸入和一個耦合到RS觸發器 3828之設定輸入上。RS觸發器同時有一個輸出耦合到第2層復位線12630之復位輸入,另一個輸出耦合到OR門12632和N型通路電晶體12638門之第一次輸入。OR門12632同時有一個輸出耦合到第2層OR鏈輸入線12634之第二個輸入,另一個輸出一個耦合到第2層OR鏈輸出線12636上。 XOR gate 12626 has an input coupled to a first input of Q1, a second input coupled to Q2 and an output coupled to a first input of AND gate 12646. AND gate 12646 with another input one coupled to the second input of TEST_EN line 12648 and one coupled to the RS flip-flop The setting input of 3828 is on. The RS flip-flop also has an output coupled to the reset input of layer 2 reset line 12630 and another output coupled to the first input of OR gate 12632 and N-type pass transistor 12638 gate. OR gate 12632 also has one output coupled to a second input of level 2 OR chain input line 12634 and another output coupled to level 2 OR chain output line 12636 .

第2層控制邏輯(未體現在附圖126中)控制XOR門12626、AND門12646、RS觸發器12628和OR門12636之運算。TEST_EN線12648用來遮罩Q1和Q2之測試過程。理想之方式,比如就是已經修復了功能性錯誤,Q1和Q2之間之區別已例行預期,並可能干擾定位邊際計時錯誤之背景測試過程。 Layer 2 control logic (not shown in FIG. 126 ) controls the operation of XOR gate 12626 , AND gate 12646 , RS flip-flop 12628 and OR gate 12636 . TEST_EN line 12648 is used to mask the test process of Q1 and Q2. Ideally, such as functional bugs have been fixed, the difference between Q1 and Q2 is routinely expected, and may interfere with the background testing process for locating marginal timing errors.

除第2層上其他邏輯錐有關之所有其他RS觸發器以外,第2層復位線12630還將RS觸發器12628之內部狀態重定到邏輯值-0。OR門12632與第2層其他邏輯錐有關之所有其他OR門一道耦合,而形成一個大的耦合到第2層RS觸發器(如附圖126中之12628)之第2層分配OR功能。如果所有RS觸發器復位到邏輯值-0,那麼分配OR功能之輸出則為邏輯值-0。如果生成Q1和Q2訊號之觸發器之間發生邏輯狀態差異,XOR門12626透過AND門12646(如果TEST_EN=邏輯值-1)將邏輯值-1顯示到RS觸發器12628之設定輸入上,使其改變狀態並將邏輯值-1顯示到OR門12632之第一個輸入上,反過來在第2層分配OR功能處(未體現在附圖126中)產生邏輯值-1,提示控制邏輯 (未體現在附圖中)存在錯誤。 Layer 2 reset line 12630 also resets the internal state of RS flip-flop 12628 to a logic value of -0, in addition to all other RS flip-flops associated with other logic cones on layer 2. OR gate 12632 is coupled with all other OR gates associated with other logic cones of level 2 to form a large level 2 distributed OR function coupled to level 2 RS flip-flops (eg, 12628 in FIG. 126). If all RS flip-flops are reset to logic-0, then the output of the assigned OR function is logic-0. If a logic state difference occurs between the flip-flops generating the Q1 and Q2 signals, XOR gate 12626 displays a logic value of -1 to the set input of RS flip-flop 12628 through AND gate 12646 (if TEST_EN = logic value -1), making it Changes state and presents a logic value of -1 to the first input of OR gate 12632, which in turn produces a logic value of -1 at the level 2 assigned OR function (not shown in Figure 126), prompting the control logic (not shown in the picture) there is an error.

控制邏輯可使用疊層之N型通路電晶體12638、12640和12642,來確定錯誤生成邏輯錐之位置。電晶體12638包含一個耦合到,RS觸發器12628 Q輸出之柵極端子,一個漏極端子耦合到地面之源極端子,另一個漏極端子耦合到電晶體12640源極上。電晶體12640包含一個耦合到行位址線ROW_ADDR線之柵極端子,一個漏極端子耦合到電晶體12638漏極之源極端子和另一個漏極端子耦合到電晶體12642源極上。電晶體12642包含一個耦合到列位址線COL_ADDR線之柵極端子,一個漏極端子耦合到電晶體12640漏極上子和另一個漏極端子耦合到傳感線SENSE上。 The control logic may use the stack of N-type pass transistors 12638, 12640 and 12642 to determine the location of the error generating logic cone. Transistor 12638 includes a gate terminal coupled to the Q output of RS flip-flop 12628, a source terminal with a drain terminal coupled to ground, and a drain terminal coupled to the source of transistor 12640. Transistor 12640 includes a gate terminal coupled to the row address line ROW_ADDR line, a drain terminal coupled to the source terminal of the drain of transistor 12638 and another drain terminal coupled to the source of transistor 12642. Transistor 12642 includes a gate terminal coupled to column address line COL_ADDR line, a drain terminal coupled to the upper drain terminal of transistor 12640 and another drain terminal coupled to sense line SENSE.

行列位址為虛擬位址,因為在邏輯設定中,觸發器之位置不會整齊地排列在行列中。在一些案例中,藉由電腦輔助設定(CAD)工具來修改網表,以正確對每個邏輯錐進行編址,然後ROW_ADDR和COL_ADDR訊號就能像設定中之其他訊號一樣佈線。 The row and column addresses are virtual addresses, because in the logic setting, the positions of the flip-flops are not neatly arranged in the rows and columns. In some cases, the netlist is modified by a computer-aided design (CAD) tool to correctly address each cone of logic, and the ROW_ADDR and COL_ADDR signals can then be routed like other signals in the setup.

這就產生了一種控制邏輯循環經過虛擬位址空間之有效方法。如果COL_ADDR=ROW_ADDR=邏輯值-1且RS觸發器狀態為邏輯值-1,那麼電晶體疊層將控制SENSE=邏輯值-1。因此,邏輯值-1只發生在RS觸發器捕獲錯誤之虛擬位址位置。一旦發現錯誤,RS觸發器12628就可與第2層復位線12630一起復位到邏輯值-0,從而可以發現可能之另一錯誤。 This results in an efficient method of controlling the looping of logic through the virtual address space. If COL_ADDR = ROW_ADDR = logic-1 and the RS flip-flop state is logic-1, then the transistor stack will control SENSE = logic-1. Therefore, a logic value of -1 occurs only at the virtual address location where the RS flip-flop catches the error. Once an error is found, RS flip-flop 12628 can be reset to a logic value of -0 along with layer 2 reset line 12630 so that another possible error can be found.

設定控制邏輯以許多方法中之一種方法處理錯誤。例如,記錄錯誤並在同一個邏輯錐位置反復出現邏輯錯誤時進入測試模式,確定該位置是否需要修復。這是一個處理只因噪音問題,而偶爾出現故障,但在正常測試下,測試合格之邊際邏輯錐導致之間歇錯誤之好方法。或者,可在收到第一次錯誤通知時採取行動,具體情況視設定選擇而定。 Set the control logic to handle errors in one of many ways. For example, log errors and enter test mode when logic errors occur repeatedly at the same logic cone location to determine if the location needs to be repaired. This is a good way to deal with intermittent errors caused by marginal logic cones that fail only occasionally due to noise issues, but under normal testing, pass the test. Alternatively, depending on the setting selection, action can be taken on the first error notification received.

依照上述附圖27,在邏輯錐平採用三模冗餘(TMR),也可作為一個有效之現場修復法運行,儘管它確實產生了高平之冗餘,掩蓋而不是修復了由於延遲故障機構或邊際慢邏輯錐而產生之錯誤。如果利用工廠修復,來確認每層上所有等同之邏輯錐在3D IC出廠前測試合格,那麼冗余平將會更高。比對三層與兩層,有或沒有修復層之成本必須在確定應用最佳案例時計算在內。 The use of triple-mode redundancy (TMR) at the logical level, in accordance with Figure 27 above, also operates as an effective field fix, although it does create a high level of redundancy that masks rather than repairs failures due to delayed mechanisms or Errors due to marginally slow logic cones. The level of redundancy will be even higher if factory remediation is used to verify that all equivalent cones of logic on each layer are tested to pass the 3D IC before it leaves the factory. Comparing three-ply versus two-ply, with or without repair ply, the cost must be taken into account when determining the best case for application.

附圖127介紹了典型3D IC 12700中一個替代性之TMR方法。在附圖127中有很多幾乎相同之層,分別表示為第1層、第2層和第3層,在附圖中以虛線分隔開來。第1層、第2層和第3層各自包含一個或多個電路層。並接合到一塊形成了使用此項技術中已知方法之3D IC 12700。第1層由第1層邏輯錐12710、觸發器12714和三者取多數(MAJ3)門12716組成。第2層包含第2層邏輯錐12720、觸發器12724和MAJ3門12726。第3層包含第3層邏輯錐12730、觸發器12734和MAJ3門12736。 Figure 127 illustrates an alternative TMR approach in exemplary 3D IC 12700. In Figure 127 there are a number of nearly identical layers, denoted as Layer 1, Layer 2 and Layer 3, separated by dotted lines in the drawing. Layer 1, Layer 2, and Layer 3 each contain one or more circuit layers. and bonded together to form a 3D IC 12700 using methods known in the art. Level 1 consists of level 1 logic cones 12710 , flip flops 12714 , and majority-of-three (MAJ3) gates 12716 . Layer 2 contains layer 2 logic cones 12720 , flip flops 12724 and MAJ3 gates 12726 . Layer 3 contains layer 3 logic cones 12730 , flip flops 12734 and MAJ3 gates 12736 .

邏輯錐12710、12720和12730統統執行幾乎一樣之邏 輯功能。觸發器12714、12724和12734偏好掃描觸發器。如果存在修復層(未體現在附圖127中),那麼附圖25中之觸發器2502,就能用來修復3D IC 12700出廠前之缺陷邏輯錐。MAJ3門12716、12726和12736對三隻觸發器12714、12724和12734之輸出進行比對後,輸出一個與輸入大多數一致之邏輯值。如果三個輸入中之兩個或三個等於邏輯值-0,那麼MAJ3門將輸出邏輯值-1。因此當三個邏輯錐中之一個或三隻觸發器中之一只有缺陷,那麼所有三個MAJ3門之輸出就會出現正確之邏輯值。 Logic cones 12710, 12720 and 12730 all perform almost the same logic editing function. Flip-flops 12714, 12724, and 12734 favor scan flip-flops. If there is a repair layer (not shown in FIG. 127 ), then the flip-flop 2502 in FIG. 25 can be used to repair the defective logic cone of the 3D IC 12700 before it leaves the factory. MAJ3 gates 12716, 12726 and 12736 compare the outputs of the three flip-flops 12714, 12724 and 12734, and output a logic value that is most consistent with the input. If two or three of the three inputs are equal to a logic value of -0, then the MAJ3 gate will output a logic value of -1. Therefore when one of the three logic cones or one of the three flip-flops is only defective, the outputs of all three MAJ3 gates will exhibit correct logic values.

附圖127中之案例之優勢之一在於:第1層、第2層或第3層可使用全部或幾乎一樣之掩模進行封裝。另一優勢在於:MAJ3門12716、12726和12736也可作為單事件翻轉(SEU)過濾有效運行,從而保證上述引用之Rezgui中描述之高依賴性或抗輻射應用。 One of the advantages of the example in Figure 127 is that layer 1, layer 2 or layer 3 can be encapsulated using all or almost the same mask. Another advantage is that the MAJ3 gates 12716, 12726 and 12736 also operate efficiently as single event upset (SEU) filtering, enabling high-dependency or radiation-hardened applications as described in Rezgui cited above.

附圖128中之典型3D IC 12800介紹了另一個TMR案例。在這個案例中,MAJ3門放在邏輯錐和其各自觸發器之間。附圖128中有幾乎一樣之層,分別以第1層、第2層和第3層表示,在附圖中以虛線分割開來。第1層、第2層和第3層各自包含一個或多個電路層並接合到一塊形成了使用此項技術中已知方法之3D IC 12800。第1層由第1層邏輯錐12810、觸發器12814和三者取多數(MAJ3)門12812組成。第2層包含第2層邏輯錐12820、觸發器12824和MAJ3門12822。第3層包含第3層邏輯錐12830、觸發器12834和MAJ3門12832。 Typical 3D IC 12800 in Figure 128 presents another example of TMR. In this case, the MAJ3 gate is placed between the logic cone and its respective flip-flop. In Figure 128 there are nearly identical layers, represented as Layer 1, Layer 2, and Layer 3, which are separated by dotted lines in the drawing. Layers 1, 2 and 3 each contain one or more circuit layers and are bonded together to form the 3D IC 12800 using methods known in the art. Level 1 consists of a level 1 logic cone 12810 , a flip-flop 12814 and a majority-of-three (MAJ3) gate 12812 . Layer 2 contains layer 2 logic cones 12820 , flip flops 12824 and MAJ3 gates 12822 . Layer 3 contains layer 3 logic cones 12830 , flip flops 12834 and MAJ3 gates 12832 .

邏輯錐12810、12820和12830統統執行幾乎一樣之邏輯功能。觸發器12814、12824和12834偏好掃描觸發器。如果存在修復層(未體現在附圖128中),那麼附圖25中之觸發器2502就能用來修復3D IC 12800出廠前之缺陷邏輯錐。MAJ3門12812、12822和12832對三個邏輯錐12810、12820和12830之輸出進行比對後輸出一個與輸入大多數一致之邏輯值。因此當三個邏輯錐中之一個有缺陷,那麼所有三個MAJ3門之輸出就會出現正確之邏輯值。 Logic cones 12810, 12820, and 12830 all perform nearly the same logic function. Flip-flops 12814, 12824, and 12834 favor scan flip-flops. If there is a repair layer (not shown in FIG. 128 ), then the flip-flop 2502 in FIG. 25 can be used to repair the defective logic cones of the 3D IC 12800 before shipment. The MAJ3 gates 12812, 12822 and 12832 compare the outputs of the three logic cones 12810, 12820 and 12830, and then output a logic value that is most consistent with the input. Thus when one of the three logic cones is defective, the outputs of all three MAJ3 gates will exhibit correct logic values.

附圖128中之案例之優勢之一在於:第1層、第2層或第3層可使用全部或幾乎一樣之掩模進行封裝。另一優勢在於:MAJ3門12712、12722和12732也可作為單事件瞬態(SET)過濾有效運行,從而保證上述引用之Rezgui中描述之高依賴性或抗輻射應用。 One of the advantages of the example in Figure 128 is that layer 1, layer 2 or layer 3 can be encapsulated using all or almost the same mask. Another advantage is that the MAJ3 gates 12712, 12722 and 12732 also operate effectively as single event transient (SET) filtering, thus enabling high-dependency or radiation-hardened applications as described in Rezgui cited above.

附圖129中之典型3D IC 12900介紹了另一個TMR案例。在這個案例中,MAJ3門放在邏輯錐和其各自觸發器之間。附圖129中有幾乎一樣之層,分別以第1層、第2層和第3層表示,在附圖中以虛線分割開來。第1層、第2層和第3層,各自包含一個或多個電路層,並接合到一塊形成了使用此項技術中已知方法之3D IC 12900。第1層由第1層邏輯錐12910、觸發器12914和三者取多數(MAJ3)門12912和12916組成。第2層包含第2層邏輯錐12920、觸發器12924和MAJ3門12922和12926。第3層包含第3層邏輯錐12930、觸發器12934和MAJ3門12932和12936。 Typical 3D IC 12900 in Figure 129 presents another example of TMR. In this case, the MAJ3 gate is placed between the logic cone and its respective flip-flop. In Figure 129 there are nearly identical layers, represented as Layer 1, Layer 2, and Layer 3, which are separated by dotted lines in the drawing. Layers 1, 2 and 3, each comprising one or more circuit layers, are bonded together to form the 3D IC 12900 using methods known in the art. Level 1 consists of Level 1 logic cone 12910 , flip-flop 12914 , and majority-of-three (MAJ3) gates 12912 and 12916 . Layer 2 contains a layer 2 logic cone 12920 , flip-flop 12924 and MAJ3 gates 12922 and 12926 . Level 3 contains the level 3 logic cone 12930 , flip-flop 12934 and MAJ3 gates 12932 and 12936 .

邏輯錐12910、12920和12930統統執行幾乎一樣之邏輯功能。觸發器12914、12924和12934偏好掃描觸發器。如果存在修復層(未體現在附圖129中),那麼附圖25中之觸發器2502就能用來修復,3D IC 12900出廠前之缺陷邏輯錐。MAJ3門12912、12922和12932對三個邏輯錐12910、12920和12930之輸出,進行比對後輸出一個與輸入大多數一致之邏輯值。同樣地,MAJ3門12916、12926和12936對三個觸發器12914、12924和12934之輸出,進行比對後輸出一個與輸入大多數一致之邏輯值。因此當三個邏輯錐中之一個或三隻觸發器中之一只有缺陷,那麼所有六個MAJ3門之輸出就會出現正確之邏輯值。 Logic cones 12910, 12920, and 12930 all perform nearly the same logic function. Flip-flops 12914, 12924, and 12934 favor scan flip-flops. If there is a repair layer (not shown in FIG. 129 ), then the flip-flop 2502 in FIG. 25 can be used to repair the defective logic cones of the 3D IC 12900 before shipment. MAJ3 gates 12912, 12922 and 12932 compare the outputs of the three logic cones 12910, 12920 and 12930, and then output a logic value that is most consistent with the input. Similarly, the MAJ3 gates 12916, 12926 and 12936 compare the outputs of the three flip-flops 12914, 12924 and 12934, and then output a logic value that is most consistent with the input. Thus when one of the three logic cones or one of the three flip-flops is defective, the outputs of all six MAJ3 gates will have correct logic values.

附圖129中之案例之優勢之一在於:第1層、第2層或第3層可使用全部或幾乎一樣之掩模進行封裝。另一優勢在於:MAJ3門12712、12722和12732也可作為單事件瞬態(SET)過濾有效運行,MAJ3門12716、12726和12736也可作為單事件翻轉(SEU)過濾有效運行,從而保證上述引用之Rezgui中描述之高依賴性或抗輻射應用。 One of the advantages of the example in Figure 129 is that layer 1, layer 2 or layer 3 can be encapsulated using all or almost the same mask. Another advantage is that MAJ3 gates 12712, 12722, and 12732 also operate effectively as single-event transient (SET) filters, and MAJ3 gates 12716, 12726, and 12736 also operate effectively as single-event upset (SEU) filters, thereby guaranteeing the above mentioned Highly dependent or radiation-hardened applications as described in Rezgui.

本發明之一些案例,可應用到大量之商業以及高依賴性之航太航空和軍事領域。用修復層,在工廠內解決缺陷之能力,結合自動解決延遲缺陷(用三層TMR案例掩蓋或用兩層替代案例代替故障電路)之能力,較之傳統之二維積體電路(IC)技術相比,使更大更複雜之三維系統之產生成為可能。本發明之這些不同方面可協調目標應用領域之成本要求。 Some examples of the present invention can be applied to a large number of commercial and highly dependent aerospace and military fields. The ability to resolve defects in the factory with a repair layer, combined with the ability to automatically resolve delay defects (cover up with three-layer TMR cases or replace faulty circuits with two-layer replacement cases), compared to traditional two-dimensional integrated circuit (IC) technology In comparison, it is possible to generate larger and more complex three-dimensional systems. These various aspects of the invention can be coordinated with the cost requirements of the target application area.

依照本發明一些案例,為了降低3D IC之成本,在製造每層時最好使用同一掩模組。透過以適當之方式在每層上製造相同之VIAS結構,然後在對齊第1層和第2層時以預期之量進行補償就能完成。 According to some cases of the present invention, in order to reduce the cost of 3D IC, it is better to use the same mask set when manufacturing each layer. This is done by fabricating the same VIAS structure on each layer in an appropriate manner and then compensating by the desired amount when aligning layers 1 and 2.

附圖130A介紹了一種通孔模式13000,位於像上述之3D IC 11900、12100、12200、12300、12400、12500和12600之第1層上。每個通孔位置13002、13004、13006和13008上之金屬疊片,至少存在於第1層之上下金屬層上。通孔模式13000接近第1層上之每個修復或替代複用器而發生,而通孔金屬疊片13002和13004(附圖中以L1/D0表示第1層輸入D0)耦合到那個位置之D0複用器輸入上,且通孔金屬疊片13006和13008(附圖中以L1/D1表示第1層輸入D1)耦合到D1複用器輸入上。 Figure 130A illustrates a via pattern 13000 on layer 1 of 3D ICs 11900, 12100, 12200, 12300, 12400, 12500, and 12600 as described above. Metal stacks on each via location 13002, 13004, 13006 and 13008 are present on at least the metal layers above and below layer 1. Via pattern 13000 occurs close to each repair or replacement multiplexer on layer 1, and via metal stacks 13002 and 13004 (layer 1 input D0 denoted by L1/D0 in the figure) are coupled between that location D0 multiplexer input, and via metal stacks 13006 and 13008 (L1/D1 in the figure represent layer 1 input D1) are coupled to D1 multiplexer input.

同樣地,附圖130B介紹了一種大體上一致之通孔模式13010,位於像上述之3D IC 11900、12100、12200、12300、12400、12500和12600之第2層上。每個通孔位置13012、13014、13016和13018上之金屬疊片,至少存在於第2層之上下金屬層上。通孔模式13010接近第2層上之每個修復或替代複用器而發生,而通孔金屬疊片13012和13014(附圖中以L2/D0表示第2層輸入D0)耦合到那個位置之D0複用器輸入上,且通孔金屬疊片13016和13018(附圖中以L2/D1表示第2層輸入D1)耦合到D1複用器輸入上。 Likewise, Figure 130B depicts a substantially uniform via pattern 13010 on layer 2 of 3D ICs 11900, 12100, 12200, 12300, 12400, 12500, and 12600 as described above. Metal stacks on each via location 13012, 13014, 13016, and 13018 exist on at least the metal layers above and below layer 2. Via pattern 13010 occurs close to each repair or replacement multiplexer on layer 2, and via metal stacks 13012 and 13014 (layer 2 input D0 denoted by L2/D0 in the figure) are coupled between that location D0 multiplexer input, and via metal stacks 13016 and 13018 (in the figure, L2/D1 represents layer 2 input D1) are coupled to D1 multiplexer input.

附圖130C為通孔圖案13000和13010對齊並由一層間互 連節距補充之頂視圖。層間互連可透過TSV或其它層間互連技術實現。附圖130C中包含上述探討之金屬疊片13002、13004、13006、13008、13012、13014、13016和13018。在附圖130C中,第2層由位於第1層右邊之一層間連接節距補充。但補充卻造成通孔金屬疊片13004和13018之物理疊層。同樣地,補充也會造成通孔疊層13006和13012之物理疊層。如果矽通孔技術或其它層間垂直耦合點位於這兩個重疊位置(藉由單個掩模),則將第2層之複用器輸入D1耦合到第1層之複用器輸入D0上,並將第2層之複用器輸入D0耦合到第1層之複用器輸入D1上。這正是實現附圖121A和123中所述案例中邏輯錐及功能塊修復或替代所必需之層間連接拓撲技術。 Figure 130C is via pattern 13000 and 13010 aligned and interconnected by a layer Top view with pitch complement. The interlayer interconnection can be realized through TSV or other interlayer interconnection technologies. Figure 130C includes metal laminations 13002, 13004, 13006, 13008, 13012, 13014, 13016, and 13018 discussed above. In Figure 130C, layer 2 is supplemented by an interlayer connection pitch located to the right of layer 1. But the addition results in a physical stack of via metal laminations 13004 and 13018. Likewise, supplementation also results in a physical stack of via stacks 13006 and 13012. If TSV or other interlayer vertical coupling points are located at these two overlapping locations (via a single mask), then layer 2 mux input D1 is coupled to layer 1 mux input D0 and Coupling layer 2 multiplexer input D0 to layer 1 multiplexer input D1. This is exactly the inter-layer connection topology technology necessary for the repair or replacement of logical cones and functional blocks in the cases described in Figures 121A and 123 .

附圖130D為採用附圖130A、130B和130C所述方法之結構側視圖。附圖130D介紹了以13020表示之典型3D IC,由層13030之兩個案例組成,分別為附圖中以第2層表示之頂層案例和以第1層表示之底層案例。層13020之每個案例包含一個典型之晶體管13031、一個典型之接點13032、典型之金屬1 13033、典型之通孔1 13034、典型之金屬2 13035、典型之通孔2 13036以及典型之金屬3 13037。以13000表示之虛線橢圓指代對應於附圖130A和130C中通孔圖案13000之第1層部分。同樣地,以13010表示之虛線橢圓指代對應於附圖130B和130C中通孔圖案13010之第2層部分。本案例中例如TSV 13040之一個層間通孔將第2層之訊號D1耦合到第1層之訊號D0。另一個層間通孔(未體 現,因為它不在附圖130D平面內)將第2層之訊號D01耦合到第1層之訊號D1。依照附圖130D所示,當第1層與第2層相同時,第2層則由一個層間通孔節距補充,使得TSV能正確對齊每1層,但只需單個層間通孔掩模就能實現正確之層間連接。 Figure 130D is a side view of a structure employing the method described in Figures 130A, 130B and 130C. Figure 130D illustrates a typical 3D IC, indicated at 13020, consisting of two instances of layer 13030, a top-level instance indicated as layer 2 and a bottom-level instance indicated as layer 1 in the drawing. Each instance of layer 13020 includes a typical transistor 13031 , a typical contact 13032 , typical metal 1 13033 , typical via 1 13034 , typical metal 2 13035 , typical via 2 13036 and typical metal 3 13037. The dotted ellipse indicated at 13000 indicates the portion of layer 1 corresponding to via pattern 13000 in FIGS. 130A and 130C. Likewise, the dotted ellipse indicated at 13010 indicates the portion of layer 2 corresponding to via pattern 13010 in FIGS. 130B and 130C. In this case, for example, an interlayer via of TSV 13040 couples the signal D1 of the second layer to the signal D0 of the first layer. Another interlayer via (not body Now, since it is not in the plane of FIG. 130D ), the signal D01 of layer 2 is coupled to the signal D1 of layer 1. As shown in Figure 130D, when layer 1 is identical to layer 2, layer 2 is complemented by an interlayer via pitch such that TSVs are properly aligned for each layer, but only a single interlayer via mask is required To achieve the correct inter-layer connection.

依照上述,本發明之一些案例中,3D IC每層上之控制邏輯最好知道是哪一層。同時每層也最好都使用一樣之掩模。在一個使用一層間通孔節距補充以正確耦合功能性和修復連接之案例中,在控制邏輯附近安裝了一個不同之通孔圖案,以開發層間補充並獨特地確定各層至其控制邏輯。 According to the above, in some cases of the present invention, it is better for the control logic on each layer of the 3D IC to know which layer it is. At the same time, it is also best to use the same mask for each layer. In one case where interlayer via pitch complementation was used to properly couple functionality and repair connections, a different via pattern was installed near the control logic to exploit interlayer complementation and uniquely identify each layer to its control logic.

附圖131A介紹了一種通孔圖案13100,位於像上述之3D IC 11900、12100、12200、12300、12400、12500和12600之第1層上。每個通孔位置13102、13104和13106上之金屬疊片至少存在於第1層之上下金屬層上。通孔圖案13100鄰近第1層上之控制邏輯而發生。通孔金屬疊片13102耦合到地面(附圖中以L1/G表示第1層地面)。通孔金屬疊片13104耦合到名為ID之訊號上(附圖中以L1/ID表示第1層ID)。通孔金屬疊片13106耦合到電源電壓上(附圖中以L1/V表示第1層VCC)。 Figure 131A shows a via pattern 13100 on layer 1 of 3D ICs 11900, 12100, 12200, 12300, 12400, 12500 and 12600 as described above. Metal stacks at each via location 13102, 13104, and 13106 are present on at least the metal layers above and below layer 1. The via pattern 13100 occurs adjacent to the control logic on layer 1 . Via metal stack 13102 is coupled to the ground (L1/G in the figure represents layer 1 ground). Via metal stack 13104 is coupled to a signal named ID (Level 1 ID is denoted by L1/ID in the figure). Via metal stack 13106 is coupled to the supply voltage (L1/V in the figure represents layer 1 VCC).

附圖131B介紹了一種通孔圖案13110,位於像上述之3D IC 11900、12100、12200、12300、12400、12500和12600之第1層上。每個通孔位置13112、13114和13116上之金屬疊片至少存在於第2層之上下金屬層上。通孔圖案 13110鄰近第2層上之控制邏輯而發生。通孔金屬疊片13112耦合到地面(附圖中以L2/G表示第2層地面)。通孔金屬疊片13114耦合到名為ID之訊號上(附圖中以L2/ID表示第2層ID)。通孔金屬疊片13116耦合到電源電壓上(附圖中以L2/V表示第2層VCC)。 Figure 131B shows a via pattern 13110 on layer 1 of 3D ICs 11900, 12100, 12200, 12300, 12400, 12500 and 12600 as described above. Metal stacks at each via location 13112, 13114, and 13116 are present on at least the metal layers above and below layer 2. Via pattern The 13110 occurs adjacent to the control logic on layer 2. The via metal stack 13112 is coupled to the ground (L2/G in the figure indicates layer 2 ground). Via metal stack 13114 is coupled to a signal named ID (Layer 2 ID is denoted by L2/ID in the figure). Via metal stack 13116 is coupled to the supply voltage (L2/V in the figure represents Layer 2 VCC).

附圖131C為通孔圖案13100和13110對齊並由一層間互連節距補充之頂視圖。層間互連可透過TSV或其它層間互連技術實現。附圖130C中包含上述探討之金屬疊片13102、13104、13106、13108、13112、13114和13116。在附圖130C中,第2層由位於第1層右邊之一層間連接節距補充。但補充卻造成通孔金屬疊片13104和13112之物理疊層。同樣地,補充也會造成通孔疊層13106和13114之物理疊層。如果矽通孔技術或其它層間垂直耦合點位於這兩個重疊位置(藉由單個掩模),則將第1層ID訊號地面,並將第2層ID訊號耦合到VCC上。而這種結構使得第1層和第2層上之控制邏輯唯一知道它們在疊層中之垂直位置。 Figure 131C is a top view of via patterns 13100 and 13110 aligned and complemented by inter-layer interconnect pitch. The interlayer interconnection can be realized through TSV or other interlayer interconnection technologies. Figure 130C includes the metal laminations 13102, 13104, 13106, 13108, 13112, 13114, and 13116 discussed above. In Figure 130C, layer 2 is supplemented by an interlayer connection pitch located to the right of layer 1. But supplementation results in a physical stack of via metal laminations 13104 and 13112. Likewise, supplementation also results in a physical stack of via stacks 13106 and 13114. If TSV or other interlayer vertical coupling points are at these two overlapping locations (via a single mask), ground the Layer 1 ID signal and couple the Layer 2 ID signal to VCC. This structure allows the control logic on layers 1 and 2 to uniquely know their vertical position in the stack.

通常所屬技術領域之知識者知悉第1層和第2層之間之金屬連接較大,因為它包括了更大之疊片和很多之TSV或其它層間互連。增大之尺寸有助於電源節點之對齊並保證L1/V和L2/V均處於正電源電位而L1/G和L2/G均處於節點電位。 Those skilled in the art generally know that the metal connection between layer 1 and layer 2 is larger because it includes larger stacks and many TSVs or other interlayer interconnects. The increased size facilitates alignment of the supply nodes and ensures that L1/V and L2/V are both at positive supply potentials and L1/G and L2/G are at node potentials.

本發明之很多案例在三層分配中運用三模冗餘(RMR)方法。在這些案例中,最佳方式就是三層均採用一樣之掩模。 Many examples of the present invention employ a triple-modular redundancy (RMR) approach in three-tier distribution. In these cases, the best approach is to use the same mask for all three layers.

附圖132A介紹了一種包含一個3x3陣列之TSV(或其它層間耦合技術)之通孔金屬重疊模式13200。TMR層間連接發生在自觸發器或功能塊扇入或扇出之三者取多數(MAJ3)門之附近。因此在每個位置,三層各層上均採用函數f(X0、X1、X2)=MAJ3(X0、X1、X2),其中X0、X1和X2表示MAJ3門之三次輸入。為了本探討目的,由於MAJ3門和X1及X2輸入來自其它兩層,X0輸入一直耦合到同一層上生成之訊號模式。 Figure 132A illustrates a via metal overlay pattern 13200 comprising a 3x3 array of TSVs (or other interlayer coupling techniques). TMR interlayer connections occur near the majority-of-three (MAJ3) gates that fan-in or fan-out from flip-flops or functional blocks. Therefore, at each position, the function f(X0, X1, X2)=MAJ3(X0, X1, X2) is used on each layer of the three layers, where X0, X1 and X2 represent the three inputs of the MAJ3 gate. For the purposes of this discussion, since the MAJ3 gate and the X1 and X2 inputs come from the other two layers, the X0 input is always coupled to the signal pattern generated on the same layer.

在通孔圖案13200中,通孔金屬疊層13202、13212和13216耦合到那層MAJ3門之X0輸入上,通孔金屬疊層13204、13208和13218耦合到那層MAJ3門之X1輸入上,而通孔金屬疊層13206、13210和13214耦合到那層MAJ3門之X2輸入上。 In via pattern 13200, via metal stacks 13202, 13212, and 13216 are coupled to the X0 input of the MAJ3 gate on that layer, via metal stacks 13204, 13208, and 13218 are coupled to the X1 input of the MAJ3 gate on that layer, and Via metal stacks 13206, 13210 and 13214 are coupled to the X2 input of the MAJ3 gate on that level.

附圖132B介紹了一個以9220表示之典型3D IC,具有三層,分別以第1層、第2層和第3層從下到上表示。在用來實行TMR相關層間耦合之MAJ3門附近,每層均包含一個通孔圖案13200之案例。第2層將一個層間通孔節距補充到第1層之右側,而第3層則將一個層間通孔節距補充到第2層之右側。附圖132B中之介紹只為截取部分。當它在水平方向正確之顯示兩個層間通孔節距補充時,通常所屬技術領域之知識者知道13200每個案例之每行通孔金屬疊片與另一個案例中之同一行左右對齊。 Figure 132B shows a typical 3D IC, designated 9220, having three layers, represented as layer 1, layer 2 and layer 3 from bottom to top. Each layer contains an instance of via pattern 13200 near the gate of MAJ3 for TMR related interlayer coupling. Layer 2 adds an interlayer via pitch to the right of layer 1, and layer 3 adds an interlayer via pitch to the right of layer 2. The description in accompanying drawing 132B is only an excerpt. While it shows the two interlayer via pitch complements correctly in the horizontal direction, generally those skilled in the art know that each row of via metal laminations in each case of the 13200 is left-to-right aligned with the same row in the other case.

因此,三個位置之通孔金屬疊片對準所有三層。附圖132B顯示了耦合第1層到第2層之那些位置上之三個層間通 孔13230、13240和13250,以及耦合第2層到第3層之那些位置上之三個層間通孔13232、13242和13252。同一層間通孔掩模均可用於層間通孔封裝階段。 Thus, the via metal laminations at three locations are aligned to all three layers. Accompanying drawing 132B has shown the three interlayer vias on those locations that couple layer 1 to layer 2. Holes 13230, 13240, and 13250, and three interlayer vias 13232, 13242, and 13252 at those locations that couple layer 2 to layer 3. The same via mask can be used in the via packaging stage.

因此層間通孔13230和13232上下對齊,並耦合第1層X2 MAJ3門輸入,第2層X0 MAJ3門輸入和第3層X1 MAJ3門輸入。同樣地,層間通孔13240和13242上下對齊,並耦合第1層X1 MAJ3門輸入,第2層X2 MAJ3門輸入和第3層X0 MAJ3門輸入。最後,層間通孔13250和13252上下對齊,並耦合第1層X0 MAJ3門輸入,第2層X1 MAJ3門輸入和第3層X2 MAJ3門輸入。由於每層中之MAJ3門X0輸入是從那層驅動之,因此每個驅動器耦合到每層上之一個不同MAJ3門輸入,避免驅動器短接,而每層上之每個MAJ3門接收來自三層上三個驅動器之輸入。 Therefore, the interlayer vias 13230 and 13232 are aligned up and down, and couple the layer 1 X2 MAJ3 gate input, the layer 2 X0 MAJ3 gate input and the layer 3 X1 MAJ3 gate input. Likewise, interlayer vias 13240 and 13242 are aligned top and bottom and couple the layer 1 X1 MAJ3 gate input, layer 2 X2 MAJ3 gate input and layer 3 X0 MAJ3 gate input. Finally, the interlayer vias 13250 and 13252 are aligned up and down and couple the layer 1 X0 MAJ3 gate input, the layer 2 X1 MAJ3 gate input and the layer 3 X2 MAJ3 gate input. Since the X0 input of the MAJ3 gate in each layer is driven from that layer, each driver is coupled to a different MAJ3 gate input on each layer to avoid driver shorting, while each MAJ3 gate on each layer receives signals from three layers. The input of the last three drivers.

本發明之一些案例可大量應用到商業以及高依賴性之航天航空和軍事領域。用修復層在工廠內解決缺陷之能力結合自動解決延遲缺陷(用三層TMR案例掩蓋或用兩層替代案例代替故障電路)之能力,與傳統之二維集成電路(IC)技術相比,使更大更複雜之三維繫統之產生成為可能。本發明之這些不同方面可抵消目標應用領域之成本要求。 Some examples of the present invention can be widely applied in commercial and highly dependent aerospace and military fields. The ability to resolve defects in the factory with a repair layer combined with the ability to automatically resolve delayed defects (masking with a three-layer TMR case or replacing faulty circuits with a two-layer replacement case) enables The generation of larger and more complex three-dimensional systems becomes possible. These various aspects of the invention can offset the cost requirements of the targeted application areas.

例如,目標為不昂貴消費品之3D IC視成本為主要考量因素,可在工廠現場修復以使成品率最大化,但不包括使短使用壽命產品成本最小化之現場修復電路。目標為較高端消費者或較低端商業產品之3D IC可在工廠修復中結 合兩層現場替代。目標為平衡成本和可靠性之企業級計算設備之3D IC可省略工廠修復步驟並在合格之成品率和現場修復中採用TMR方法。目標為高依賴性、軍事、航天航空、空間或抗輻射應用之3D IC可採取工廠修復來保證每個電路之所有三個案例完全運行無誤並在現場修復和SET及SEU過濾中採用TMR方法。用於軍事市場之蓄電池驅動組件可加入電路使得組件只運行TMR三層中之一層,從而延長電池壽命,且包括一個輻射檢測電路,可在運行環境發生變化時依照需要自動轉換成TMR模式。在本發明範圍內是可能實現很多其他組合及交替使用。 For example, 3D ICs targeted at inexpensive consumer products see cost as a major consideration and can be repaired on-site at the factory to maximize yield, but exclude field-repaired circuits that minimize cost for short-lifetime products. 3D ICs targeted at higher-end consumer or lower-end commercial products can end up in factory refurbishment Combining two layers of on-site replacement. 3D ICs targeting enterprise-class computing devices that balance cost and reliability can omit factory repair steps and employ TMR methods in qualified yield and field repair. 3D ICs targeting high-dependency, military, aerospace, space, or radiation-hardened applications can take factory repair to ensure that all three cases of each circuit are fully operational and employ TMR methods in field repair and SET and SEU filtering. Battery-driven components for the military market can add circuitry to allow the component to run only one of the three layers of TMR, thereby extending battery life, and include a radiation detection circuit that can automatically switch to TMR mode as needed when the operating environment changes. Many other combinations and alternations are possible within the scope of the invention.

值得注意之处是,本發明之很多原理也適用於傳統之二維集成電路(2D IC)。例如,一個相似之兩層現場修復案例建在單層上,重工電路兩個模式都在一個2D IC上,而重工模式間則採用同一個交叉連接。熔絲、反熔絲、閃存存儲器等可編程技術可用來生效工廠修復和現場修復。同樣地,一些TMR案例之類似模式不管在2D IC中還是3D IC中都是獨一無二之拓撲技術,若應用在單層上,則也能提高2D IC系統之成品率或可靠性。 It is worth noting that many principles of the present invention are also applicable to traditional two-dimensional integrated circuits (2D ICs). For example, a similar two-layer field repair case is built on a single layer, reworking the circuit for both modes on one 2D IC, and using the same cross-connect between the reworking modes. Programmable technologies such as fuses, antifuses, and flash memory can be used to effect factory and field repairs. Likewise, similar patterns of some TMR cases are unique topological techniques in both 2D IC and 3D IC, and if applied on a single layer, can also improve the yield or reliability of 2D IC systems.

附圖13為3D邏輯劃分法之流程示意圖。將一個邏輯設定劃分為兩個以上之垂直連接晶粒給佈局佈線-P&R工具帶來了新一輪之挑戰。佈局佈線工具是CAD軟體中之一種工具,具有運算上述成庫邏輯晶片(以及成庫其它晶片)之能力。已有技術P&R工具之版式流程計劃一般從佈局開始,之後進行佈線。但是垂直連接晶粒之邏輯設定卻優先 考量了晶粒間大大減小之頻率,從而產生了特殊設定流程以及專門支持設定流程之CAD軟體之需要。事實上,從附圖13中之流程來看,3D系統是值得將一部分之佈線優先。 Accompanying drawing 13 is the schematic flow chart of 3D logical division method. Dividing a logic setup into more than two vertically connected dies presents a new round of challenges for place-and-route-P&R tools. The layout and routing tool is a tool in CAD software, which has the ability to operate the logic chips (and other chips in the library) mentioned above. The layout flow planning of prior art P&R tools generally starts with layout, followed by routing. But the logic setting of the vertically connected die is prioritized Considering the greatly reduced frequency between grains, there is a need for a special setting process and CAD software that specifically supports the setting process. In fact, judging from the flow chart in Figure 13, it is worth prioritizing part of the wiring for the 3D system.

附圖13之流程圖採用以下術語: The flowchart of accompanying drawing 13 uses the following terminology:

M-邏輯之TSV數量; M-logic TSV number;

N(n)-連到線網n之節點數量; N(n) - the number of nodes connected to the network n;

S(n)-線網n之中位鬆弛; S(n)-Slack in median of line network n;

MinCut-一個用最少數量連接兩半之線網(MC)將邏輯設定(網表)分割成兩半一樣大小之已知算法; MinCut - a known algorithm for dividing a logical setup (netlist) into two halves of the same size with a minimum number of nets (MC) connecting the two halves;

MC-連接兩部分之線網數量; MC - the number of nets connecting the two parts;

K1,K2-設定者選定之兩個參數。 K1, K2-two parameters selected by the setter.

附圖13中所提議之流程之一個構想是在邏輯設定中建立一份網表,從而連接數量大於K1並小於K2之節點。K1和K2是設定者選定之參數,在迭代過程中可進行修改。K1應足夠高,才能限制放入網表之網數量。流程之目的是將TSV分配到緊定時約束之線網中-臨界線網。同時,還有很多節點可以將佈局延伸到很多之晶粒,有助於縮短總體之物理長度,滿足定時約束。表中線網之數量應接近一致,但不能小於TSV之數量。相應地,K1設定值必須高,這樣才能達到流程目的。K2為線網之上限,它之節點數量N(n)可成為得到特殊處理之事由。 One idea of the proposed flow in Fig. 13 is to build a netlist in the logical setup, so that the number of nodes greater than K1 and less than K2 is connected. K1 and K2 are parameters selected by the setter and can be modified during iteration. K1 should be high enough to limit the number of nets put into the netlist. The purpose of the process is to allocate TSVs into nets with tight timing constraints - critical nets. At the same time, there are many nodes that can extend the layout to many dies, which helps to shorten the overall physical length and meet timing constraints. The number of nets in the table should be close to the same, but not less than the number of TSVs. Correspondingly, the K1 setting value must be high, so as to achieve the purpose of the process. K2 is the upper limit of the line network, and its node number N(n) can be the subject of special treatment.

臨界線網通常藉由設定靜態定時分析確定關鍵路徑以及路徑上可用之鬆弛時間,經過路徑約束到達平面規劃、佈局和佈線工具,這樣最終設定就不會因為超出要求而降 級。 The critical line net usually determines the critical path and the available slack time on the path by setting static timing analysis, and reaches the floorplanning, placement and routing tools through path constraints, so that the final setting will not be degraded due to exceeding requirements. class.

網表建好後,依照線網之遞增鬆弛或中位鬆弛S(n)做出優先命令。然後使用劃分算法,比如但不限於MinCut,設定就能分成兩部分,而最高優先權線網在兩部分之間等分分割。目的是為了給緊鬆弛之線網一個更好之機會佈局地更近,從而滿足定時挑戰。具有高於K1節點數量之線網傾向於覆蓋較大之空間,並透過延伸成三維,我們就能更好地滿足定時挑戰。 After the netlist is built, make a priority command according to the incremental slack or median slack S(n) of the net. Then using a partitioning algorithm, such as but not limited to MinCut, the setting can be split into two parts, with the highest priority net being split equally between the two parts. The purpose is to give tight and slack nets a better chance of being placed closer together to meet the timing challenge. Nets with a higher number of nodes than K1 tend to cover larger spaces, and by extending into three dimensions, we can better meet the timing challenge.

附圖13之流程圖提示了一個將TSV分配到很多節點線網之迭代過程,伴隨最緊湊之定時挑戰或最小鬆弛量。 The flow diagram of Figure 13 suggests an iterative process for distributing TSVs to many node nets with tightest timing challenges or minimal slack.

顯而易見,依照邏輯所延伸之晶粒數量來看,同一個流程能調整成三向分割或任何其他之數量。 Obviously, the same flow can be scaled to 3-way splits or any other amount depending on how many dies the logic extends.

構建一個由基於反熔絲邏輯組成之3D可配置系統所帶來之特徵可以透過利用冗餘實現成本率之增長。但對於本發明案例之3D結構來說,甚至可以更便利,因為存儲器不會隨意分佈在邏輯之間,卻會集中在與邏輯晶粒垂直連接之存儲晶粒當中。存儲器冗餘以及正確之自動修復流程對邏輯和系統之性能影響較小。 Building a 3D configurable system based on antifuse logic brings features that enable cost-effectiveness gains through the use of redundancy. But for the 3D structure in the case of the present invention, it can be even more convenient, because the memory will not be randomly distributed between the logic, but will be concentrated in the memory die connected vertically to the logic die. Memory redundancy and proper auto-repair procedures have less impact on logic and system performance.

本發明之一系列電平劃片街區代表之是矽面積之部分損失。街區越窄,損失越小,因此採用能與窄街區一同製造和工作之先進劃片方法還是有優勢。 A series of level scribe blocks in the present invention represents a partial loss of silicon area. The narrower the blocks, the less damage there is, so there are advantages to using advanced scribing methods that can be manufactured and work with narrow blocks.

這樣一個先進之劃片方法藉由鐳射對3D IC晶圓進行劃片。鐳射劃片技術,包括藉由水柱冷卻襯底並移除碎片,可用來將對3D IC結構之損害降到最低並切割3D IC中 之敏感層,再做最後之普通劃片處理。 Such an advanced dicing method uses a laser to scribe 3D IC wafers. Laser scribing techniques, including cooling the substrate with a water jet and removing debris, can be used to minimize damage to 3D IC structures and cut 3D ICs The sensitive layer, and then do the final normal scribing process.

本發明各個案例之3D可配置系統之附加優勢就是降低測試成本,而這正是應用標準'Lego®'積木建立獨特系統之結果。測試標準塊可透過應用探針板和標準測試程式降低測試成本。 An added advantage of the 3D configurable systems in each case of the present invention is the reduced cost of testing, which is a result of the use of standard 'Lego®' building blocks to create unique systems. Test standard block can reduce test cost by applying probe card and standard test program.

本次公開包括兩種形式之3D IC系統,第一種藉由TSV,而第二種方式則藉由文中稱為'頂樓'之方法,具體描述如見附圖21~35及39~40。在組件藉由層轉移或沉澱和文中稱為'地基'和'頂樓'之方法並用TSV連接到一塊而生成多層單或多晶矽之情況下,這兩種方法就可以一起使用。最主要之區別在於先前之TSV與相對大之未對準(約1微米)和連接完全封裝組件之每平方毫米10000左右之有限連接(TSV)有關,而公開之'智能切割'層轉移方法允許3D結構有微小之未對準(<10nm)和每平方毫米100百萬左右之大量連接(通孔),因為它們是在一個集成封裝流程中生產之。基於TSV之3D有一個優勢就是具備集合前之組件測試能力以及在3D疊層或系統中利用已知合格晶粒(KGD)之能力,而這對於保證良好之3D集成系統成品率以及合理之成本是非常有利之。 This disclosure includes two forms of 3D IC systems, the first is through TSV, and the second is through the method called "top floor" in the text. See Figures 21~35 and 39~40 for details. These two methods can be used together in the case of devices that generate multiple layers of mono- or poly-silicon by layer transfer or deposition and what is referred to herein as a 'foundation' and 'top floor' approach connected together with TSVs. The main difference is that the previous TSVs were associated with relatively large misalignments (about 1 micron) and limited connections (TSVs) of the order of 10,000 per square mm connecting fully packaged components, whereas the disclosed 'smart dicing' layer transfer method allows The 3D structures have tiny misalignments (<10nm) and a large number of connections (vias) around 100 million per square millimeter because they are produced in an integrated packaging process. One of the advantages of TSV-based 3D is the ability to test components before assembly and the ability to utilize known good die (KGD) in 3D stacks or systems, which is essential to ensure good 3D integrated system yield and reasonable cost It is very beneficial.

本發明之一個附加替代方案為允許冗餘存在之方法,這樣採用層轉移技術之高度集成3D系統就能有較高之成品率。為了闡釋這個冗餘理念,我們將採用附圖11A 36-38中之可編程瓷磚陣列。 An additional alternative of the present invention is a method that allows redundancy so that highly integrated 3D systems using layer transfer techniques can have higher yields. To illustrate this redundancy concept, we will use the programmable tile array shown in Figure 11A 36-38.

附圖41為冗餘3D IC系統之示意圖,它介紹了3D IC可 編程系統由3X3瓷磚4102之可編程第一層4100組成,上面覆蓋3X3瓷磚4112之可編程第一層4110,而最上面覆蓋3X3瓷磚4122之可編程第一層4120。在該層一塊瓷磚和其鄰近瓷磚之間存在很多可編程連接4104。可編程組件4106可以是反熔絲、通路晶體管控制之驅動器、浮動柵閃光晶體管或相似之電可編程組件。每個瓷磚間連接4104有一個分支可編程連接4105,連接到層間垂直連接4140上。最終產品是這樣設定之,使得至少一層比如4110為冗餘保留。 Accompanying drawing 41 is the schematic diagram of redundant 3D IC system, it has introduced 3D IC can The programming system consists of a programmable first layer 4100 of 3X3 tiles 4102 overlaid with a programmable first layer 4110 of 3X3 tiles 4112 and a programmable first layer 4120 of 3X3 tiles 4122 on top. There are many programmable connections 4104 between a tile and its neighbors in the layer. Programmable device 4106 may be an antifuse, pass transistor controlled driver, floating gate flash transistor, or similar electrically programmable device. Each inter-tile connection 4104 has a branch programmable connection 4105 connected to an inter-layer vertical connection 4140 . The final product is configured such that at least one layer such as 4110 is reserved for redundancy.

當最終產品可編程系統為終端應用進行編程時,每個瓷磚會使用自身之MCU進行內建自測試。檢測發現有缺陷之瓷磚被冗餘層4410中之瓷磚所替代。替代過程將由位於冗餘層內同一位置之瓷磚完成,因此它對於整體產品之功能性和性能之影響應是合意之。例如,如果瓷磚(1,0,0)有缺陷,那麼瓷磚(1,0,1)將被編程以具備同樣之功能並透過準確設定瓷磚間之可編程連接來取代瓷磚(1,0,0)。因此,如果缺陷瓷磚(1,0,0)假設藉由可編程組件4106透過連接4104與瓷磚(2,0,0)相連,那麼可編程組件4106會被關掉,而可編程組件4116、4117和4107則開啟。不管是重複瓷磚之內部還是外部連接,都應使用相似之多層連接結構。因此當瓷磚出現缺陷時,冗餘層之冗餘瓷磚將被編程到缺陷瓷磚之功能中去,而多層瓷磚間結構則被激活,切斷故障瓷磚後接通冗餘瓷磚。當瓷磚(2,0,0)為次品時,也可採用層間垂直連接4140插入冗餘層之瓷磚(2,0,1)。在這種情況下,瓷磚 (2,0,1)會被編程而具有與瓷磚(2,0,0)一樣之功能,而可編程組件4108關掉,可編程組件4118、4117和4107開啟。 When the end-product programmable system is programmed for the end application, each tile performs a built-in self-test using its own MCU. The tiles found to be defective are replaced by tiles in the redundant layer 4410 . The replacement process will be done with tiles located at the same location within redundant layers, so its effect on the functionality and performance of the overall product should be desirable. For example, if tile (1, 0, 0) is defective, then tile (1, 0, 1) will be programmed to perform the same function and replace tile (1, 0, 0) by precisely setting the programmable connections between the tiles. ). Thus, if a defective tile (1,0,0) is assumed to be connected to tile (2,0,0) by programmable component 4106 through connection 4104, then programmable component 4106 is turned off and programmable components 4116, 4117 and 4107 are turned on. Both internal and external connections of repeating tiles should use similar multi-level connection structures. Therefore, when a tile is defective, the redundant tile of the redundant layer will be programmed into the function of the defective tile, and the structure between the multi-layer tiles will be activated, and the redundant tile will be connected after the faulty tile is cut off. When the tile (2, 0, 0) is defective, the vertical connection 4140 between layers can also be used to insert the tile (2, 0, 1) of the redundant layer. In this case, the tile (2,0,1) would be programmed to function the same as tile (2,0,0), with programmable component 4108 off and programmable components 4118, 4117, and 4107 on.

本發明之一個附加案例為修改之TSV(矽通孔技術)流程。該流程針對晶圓對晶圓TSV,並會提供一種方法,即增加晶圓之厚度可減少到1微米左右。附圖93A~D介紹了這樣一種方法。第一個晶圓9302為基極,頂部建有混合3D結構。第二個晶圓9304接合到第一個晶圓9302之上面。新之上層晶圓面朝下,使得電路9305與第一層晶圓9302電路9303面對面。 An additional example of the present invention is a modified TSV (Through Silicon Via) process. The process is targeted at wafer-to-wafer TSV and will provide a method that increases wafer thickness down to around 1 micron. Figures 93A-D illustrate such a method. The first wafer, 9302, is the base with hybrid 3D structures built on top. A second wafer 9304 is bonded on top of the first wafer 9302 . The new upper wafer faces down so that the circuitry 9305 faces the first tier wafer 9302 with circuitry 9303.

在一些應用中,接合方式為氧化物對氧化物;而在另外一些應用中,接合方式為銅對銅。此外,接合物為混合接合方式,即一些接合面為氧化物而一些為銅。 In some applications, the bonding is oxide-to-oxide; in others, the bonding is copper-to-copper. In addition, the joint is a hybrid joint, ie some joint surfaces are oxide and some are copper.

接合後,上晶圓9304透過普通背面研磨和CMP工藝變細至60微米左右。附圖93B介紹了現變細之晶圓9306接合到第一層晶圓9302之情況。 After bonding, the upper wafer 9304 is thinned to about 60 microns through common back grinding and CMP processes. FIG. 93B illustrates the bonding of the now thinned wafer 9306 to the first tier wafer 9302.

下一步包括高精度測量上晶圓9306厚度,之後透過高功率1-4MeV H+植入,就能在上晶圓9306內確定解理面9310。解理面9310可定位在接合面上方1微米左右處之位置,見附圖93C所示。執行這個過程時,可安裝一個專門之高功率植入器,例如SiGen公司在其PV(光電)應用領域中使用之植入器。 The next step includes high-precision measurement of the thickness of the upper wafer 9306, after which the cleavage plane 9310 can be determined in the upper wafer 9306 through high-power 1-4MeV H+ implantation. The cleavage surface 9310 can be positioned approximately 1 micron above the junction surface, as shown in Figure 93C. To perform this process, a specialized high-power implanter, such as that used by SiGen in its PV (photovoltaic) applications, can be installed.

具備準確測量上晶圓9306厚度和高度控制植入程式之能力使得劈開大部分之上晶圓9306成為可能,並留下一個 1微米左右之極細層9312,接合在第一個晶圓9302上面,見附圖93D所示。 The ability to accurately measure the thickness of the upper wafer 9306 and to control the height of the implant program makes it possible to cleave a large portion of the upper wafer 9306, leaving a A very fine layer 9312 of about 1 micron is bonded on the first wafer 9302, as shown in Figure 93D.

此工藝流程之一個優點在於帶電路之附加晶圓現可佈局並以相似之方式接合到接合結構9322之上面。但首先,連接層建在9312之背面,允許電氣連接到接合結構9322電路。將上層變細至單個微米水準使得這樣之電氣連接金屬層能完全對準於上晶圓9312電路9305,而且透過上層9312背面之通孔相對較小,直徑為100nm左右。 One advantage of this process flow is that additional wafers with circuitry can now be laid out and bonded in a similar manner over bonding structures 9322 . But first, a connection layer is built on the backside of 9312, allowing electrical connections to bond structure 9322 circuits. Thinning the upper layer to a single micron level allows such an electrical connection metal layer to be completely aligned with the circuit 9305 of the upper wafer 9312, and the via holes through the back of the upper layer 9312 are relatively small, with a diameter of about 100 nm.

上層9312之變細能使修改之TSV處於100nm之水準,對比TSV需要經過50微米矽所需之5微米。不幸之是,晶圓對晶圓接合工藝之未對準水平依舊較大,+/-0.5微米左右。相應地,本文中有關附圖75所述,一個1x1微米左右之接合焊盤用在第一個晶圓9302之上面,透過銅對銅接合與一個小之金屬接點連接到第二個晶圓9304之表面上。該工藝提供了一個連接密度,即每平方微米約1個連接。 The thinning of the upper layer 9312 enables modified TSVs at the 100nm level, compared to the 5 microns required for TSVs to pass through 50 microns of silicon. Unfortunately, the misalignment level of the wafer-to-wafer bonding process is still large, around +/-0.5 micron. Correspondingly, as described herein with respect to Figure 75, a bond pad of around 1x1 micron is used on top of the first wafer 9302 to connect to the second wafer via copper-to-copper bonding and a small metal contact 9304 on the surface. The process provides a connection density of about 1 connection per square micron.

最理想之方式就是藉由附圖80中介紹之理念和相關之解釋來增加連接密度。在修改TSV之情況下,這樣做會更具挑戰性,因為接合之兩個晶圓全部處理後如果接合,通向接合焊條之空間就非常有限。儘管如此,為了構成一個通孔,則需要在所有層中進行蝕刻。附圖94介紹了一種方法以及對這些問題進行編址之結構。 The ideal way is to increase the connection density by introducing the concepts and related explanations in Figure 80. This is even more challenging in the case of modified TSVs, since the two wafers to be bonded have very limited access to the bonding electrodes if bonded after both wafers are fully processed. However, to form a via, it needs to be etched in all layers. Figure 94 presents a method and structure for addressing these issues.

附圖94A介紹了四條暴露在第一個晶圓9302上層上之金屬接合焊條9402。接合焊條9402為東西朝向,東西接合最大未對準Mx為9406之長度加上一個三角D,稍後給予解 釋。接合焊條之節距為第一個晶圓9302上層最小節距Py之兩倍。9403表明了一個附加金屬焊條之未用電位空間。 FIG. 94A shows four metal bonding electrodes 9402 exposed on the upper layer of the first wafer 9302. The joint welding rod 9402 is oriented east-west, and the maximum misalignment Mx of the east-west joint is the length of 9406 plus a triangle D, and the solution will be given later release. The pitch of bonding electrodes is twice the minimum pitch Py of the upper layer of the first wafer 9302 . 9403 indicates the unused potential space of an additional metal electrode.

附圖94B介紹了裸露在第二個晶圓9312上層上之接合焊條9412和9413。附圖94B同時顯示了兩列接合焊條,即從北到南走向之A和B。這些接合焊條之長度為1.25Py。兩個晶圓9302和9312以銅對銅方式接合,而附圖94A和附圖94B中之接合焊條之設定使得接合未對準不超過東西方向之最大未對準Mx和北南方向之My。附圖94B中之接合焊條9412和9413之設定應使得它們不會無意短接於94A中之接合焊條9402,並且不管是A行之接合焊條9412還是B行之接合焊條9413都能與接合焊條9402取得完整之接觸。三角D為從B行接合焊條9413東邊開始至A行接合焊條9412西邊之大小。附圖94B中之接合焊條9412和9413之數量應設定為等同附圖94A中接合焊條9402加上My之值,以抵消北南方向上之最大未對準錯誤。 FIG. 94B shows bonding electrodes 9412 and 9413 exposed on the upper layer of the second wafer 9312. Figure 94B also shows two rows of bonding electrodes, A and B running from north to south. The length of these bonding electrodes is 1.25Py. The two wafers 9302 and 9312 are copper-to-copper bonded, and the bonding electrodes in FIGS. 94A and 94B are configured such that the bonding misalignment does not exceed the maximum misalignment Mx in the east-west direction and My in the north-south direction. Joining electrodes 9412 and 9413 in accompanying drawing 94B are set such that they do not inadvertently short the joining electrodes 9402 in 94A, and whether it is the joining electrodes 9412 of the A row or the joining electrodes 9413 of the B row can connect with the joining electrodes 9402 Get complete contact. Triangle D is the size from the east side of row B bonding electrodes 9413 to the west side of row A bonding electrodes 9412 . The number of bonding electrodes 9412 and 9413 in FIG. 94B should be set to equal the value of bonding electrodes 9402 in FIG. 94A plus My to offset the maximum misalignment error in the north-south direction.

大體上附圖94B中所有之接合焊條都可透過上晶圓9312之內部佈線佈線至與晶體管層鄰近之晶圓底部上。晶圓底部之位置和9322結構之上端示意圖見附圖93D。至此,新之通孔9432形成,透過傳統之晶圓工藝步驟將接合焊條連到接合結構之頂面。附圖94C介紹了所有佈線至附圖94B中接合焊條之通孔連接,排在A行9432和B行9433。此外,引入訊號之通孔8436也應加工處理。所有這些通孔可與上晶圓9312對齊。 Substantially all of the bonding electrodes in FIG. 94B can be routed through the internal wiring of the upper wafer 9312 to the bottom of the wafer adjacent to the transistor layer. See Figure 93D for the location of the bottom of the wafer and the top view of the 9322 structure. At this point, new vias 9432 are formed to connect bonding electrodes to the top surface of the bonding structure through conventional wafer processing steps. Figure 94C shows all the through-hole connections routed to the bond electrodes in Figure 94B, in row A 9432 and row B 9433. In addition, the through hole 8436 for introducing signals should also be processed. All of these vias can be aligned with the upper wafer 9312.

依照附圖93C所示,藉由金屬條9438,一個金屬掩模 被用來連接,例如四個通孔9432和9433到四個通孔9436上。這個金屬條以東西方向與上晶圓9312對齊,也可在北南方向與上晶圓9312對齊,但必須設定一個基於北南方向之接合未對準之專用偏移,但是北南方向之金屬結構9438長度應能足夠抵消最壞情況下北南方向之接合未對準。 According to FIG. 93C, by means of metal strips 9438, a metal mask are used to connect, for example, the four vias 9432 and 9433 to the four vias 9436. This metal strip is aligned with the upper wafer 9312 in the east-west direction, and can also be aligned with the upper wafer 9312 in the north-south direction, but a special offset must be set based on the bonding misalignment in the north-south direction, but the metal strip in the north-south direction Structure 9438 shall be of sufficient length to offset worst case north-south joint misalignment.

再次聲明,本發明可應用於除由很多重複處理晶片組成之圖形處理器等可編程邏輯外之很多應用領域。其它應用領域包括3D ASIC(專用集成電路)中之一般邏輯設定或將ASIC層與由至少部分其它專用功能組成之層結合之系統。通常所屬技術領域之知識者知悉透過運用本文中之發明原理是可以完成很多案例和組合方案的,而且這種案例會適時將自己介紹給這些專業技術人員。所附權利要求除外,本發明不受任何形式之限制。 Again, the invention is applicable to many applications other than programmable logic such as graphics processors consisting of many repeatedly processed chips. Other areas of application include general logic setup in 3D ASICs (Application Specific Integrated Circuits) or systems combining ASIC layers with layers consisting of at least some other specialized functions. Usually those who are knowledgeable in the technical field know that many cases and combination schemes can be completed by using the inventive principles in this paper, and this case will introduce itself to these professional technicians in due course. The invention is not restricted in any way except by the appended claims.

但另外一個透過更換缺陷電路並運用3D冗餘提高成品率之選擇方案就是代替可編程連接運用直讀式電子束。 But another option to improve yield by replacing defective circuits and using 3D redundancy is to use direct read e-beams instead of programmable connections.

可編程3D系統之附加變化包括一個平鋪式之可編程邏輯瓷磚,與預裝配在附圖14所示基極晶圓1402上之I/O結構連接。 Additional variations of the programmable 3D system include a tiled programmable logic tile connected to I/O structures pre-assembled on the base wafer 1402 shown in FIG. 14 .

但在一個附加變化中,藉由附圖21~35或附圖39~40所示之任一方法,可編程3D系統應包括一個平鋪式之可編程邏輯瓷磚,與預裝配在成品基極晶圓1402頂部之I/O結構連接。實際上,附圖11中之任一選擇性結構都可封裝在彼此上方,只要運用附圖21~35或附圖39~40中所示之3D技術。相應地,3D可編程系統之許多變化可透過有限之一套 掩模實現,只需混合不同結構形成不同之3D可編程系統,並改變量、邏輯3D位置、I/O類型以及存儲器類型等等。 But in an additional variation, by any of the methods shown in Figures 21-35 or Figures 39-40, the programmable 3D system should include a tiled programmable logic tile pre-assembled on the finished base The I/O structures on top of wafer 1402 are connected. In fact, any of the optional structures in Fig. 11 can be packaged on top of each other, as long as the 3D technology shown in Figs. 21-35 or Figs. 39-40 is used. Accordingly, many variations of 3D programmable systems can be achieved through a limited set of For mask implementation, just mix different structures to form different 3D programmable systems, and change the amount, logical 3D position, I/O type, memory type, etc.

透過運用全掩模版曝光之一小部分取得附加之撓性和掩模之複用。現代步進電機允許覆蓋掩模版部分,由此投射掩模版之一小部分。相應地,掩模組之一部分可用於一個功能,而另一部分則用於另一功能。例如,讓附圖37中之結構代表3D可編程系統終端設備之邏輯部分。在3X3可編程瓷磚結構上方,透過運用附圖21~35或附圖39~40中之工藝方法可建立I/O結構。應當有一組掩模,它們之不同部分為不同I/O結構之重疊所用;例如,組成簡單I/O之一部分和串行化器/反串行化器(Ser/Des)I/O之另一部分。每組經設定後提供成瓦之I/O,完美疊加在可編程邏輯瓷磚上。然後在一個掩模組上之兩部分,可在終端系統生成很多變化,包括一個帶有所有九塊瓷磚之簡單I/O,另一個帶有SerDes重疊瓷磚(0,0),而簡單I/O疊加在其它八塊瓷磚上,另一個帶有SerDes重疊瓷磚(0,0)、(0,1)和(0,2),而簡單I/O疊加在其它六塊瓷磚上,以此類推。事實上,如果設定合理之,很多層都可以一層疊加在另外一層上之方式生產,從而在一組有限之掩模內生產出多種多樣之終端產品。通常所屬技術領域之知識者知悉這種方法之適用性超出可編程邏輯範圍,最好應用在有許多3D IC和3D系統之結構中。因此本發明範圍只在所附權利要求範圍內。 Additional flexibility and mask re-use is achieved by using a fraction of the full reticle exposure. Modern stepper motors allow covering portions of the reticle, thereby projecting a small portion of the reticle. Accordingly, one part of the mask set may be used for one function while another part is used for another function. For example, let the structure in Figure 37 represent the logical part of a 3D programmable system terminal device. On top of the 3X3 programmable tile structure, the I/O structure can be built by using the process in Figures 21-35 or Figures 39-40. There should be a set of masks whose different parts are used for the overlap of different I/O structures; part. Each group is configured to provide a tile of I/O, perfectly superimposed on the programmable logic tile. Then two parts on one mask set, many variations can be generated at the end system, including a simple I/O with all nine tiles, another with SerDes overlapping tiles (0, 0), and a simple I/O O stacked on eight other tiles, another with SerDes overlapping tiles (0,0), (0,1) and (0,2), simple I/O stacked on other six tiles, and so on . In fact, if properly set up, many layers can be produced one on top of the other to produce a wide variety of end products within a limited set of masks. It is generally known by those skilled in the art that the applicability of this approach extends beyond programmable logic, preferably in structures with many 3D ICs and 3D systems. The scope of the invention is therefore only as defined by the appended claims.

但在本發明之一個附加選擇方案中,3D反熔絲可配置 系統也應包括一個編程晶粒。在FPGA產品之一些情況中,主要是反熔絲基礎產品,安裝了一個外接組件用於編程。在很多情況下,這可以便利用戶將該編程功能集成到FPGA組件中。當編程過程需要更高之電壓以及控制邏輯時,這就容易導致晶粒之嚴重架空。因此,可在一個專門之編程晶粒中設定編程器功能。這種編程晶粒之電荷泵能產生更高之編程電壓,而與編程相關之一個控制器在3D可配置電路和編程檢驗電路內部對反熔絲可編程晶粒進行編程。可編程晶粒透過採用較低成本較老式之半導體工藝進行生產。可配置系統之3D結構之一個附加優勢在於它之高產能成本縮減方案,其中反熔絲層被定制層所取代,由此,可編程晶粒才從3D系統中移除,從而實現了更多之節省成本高產能生產。 But in an additional option of the present invention, the 3D antifuse can be configured The system shall also include a programming die. In some cases of FPGA products, mainly antifuse based products, an add-on component is installed for programming. In many cases, this facilitates the user's integration of this programming capability into the FPGA component. This can easily lead to severe overhead of the die when the programming process requires higher voltages and control logic. Therefore, the programmer function can be set in a dedicated programming die. The charge pump of the programming die can generate a higher programming voltage, and a controller associated with programming programs the anti-fuse programmable die inside the 3D configurable circuit and the program verification circuit. Programmable die are produced using lower cost older semiconductor processes. An additional advantage of the 3D structure of the configurable system is its high throughput cost reduction solution, where the antifuse layer is replaced by a custom layer, whereby the programmable die is removed from the 3D system, enabling more Cost-saving and high-capacity production.

通常所屬技術領域之知識者知悉本發明使用了反熔絲術語,因為它是同業之通用名稱,但本發明也提及了像開關一樣運行之微組件,表示在初態時,微組件具有高阻抗OFF狀態,而在電子上,它可切換到極低之電阻-ON狀態。它也可對應於多次切換ON-OFF之組件-再編程開關。例如新之發明,像美國加州大學洛杉磯分校微納米製造實驗室工作人員CJKim介紹之靜電激勵金屬微滴微動開關,就可兼容集成到CMOS芯片上。 Those of ordinary skill in the art know that the present invention uses the term antifuse because it is a common name in the industry, but the present invention also refers to a microcomponent that operates like a switch, indicating that in its initial state, the microcomponent has a high Impedance OFF state, and electronically, it can be switched to very low resistance -ON state. It can also correspond to a component that switches ON-OFF multiple times - a reprogramming switch. For example, new inventions, such as the electrostatically actuated metal droplet micro-switches introduced by CJ Kim, a staff member of the Micro-Nano Manufacturing Laboratory at the University of California, Los Angeles, can be compatible and integrated into CMOS chips.

所屬技術領域之專業技術人員知悉本發明不限於反熔絲可配置邏輯,並適用於其它非易失性可配置邏輯。一個很好之例子就是基於閃光之可配置邏輯。閃光編程也需要 較高之電壓,而且在基極擴散層內安裝編程晶體管和編程電路就能降低基極擴散層之總體密度。運用本發明之不同案例是有利之,並能得到更高之組件密度。因此建議依照本發明之一個或多個案例,而不是作為擴散層之一部分,去建立編程晶體管和編程電路。在高產能生產中,一個或多個定制掩模用來取代閃光編程之功能並相應地保留了添加到編程晶體管和編程電路之需要。 Those skilled in the art know that the present invention is not limited to antifuse configurable logic, and is applicable to other non-volatile configurable logic. A good example is Flash-based configurable logic. Flash programming also requires Higher voltage, and the installation of programming transistors and programming circuits in the base diffusion layer can reduce the overall density of the base diffusion layer. It is advantageous to use different instances of the present invention and to achieve higher device densities. It is therefore proposed to build programming transistors and programming circuits in accordance with one or more embodiments of the present invention, rather than as part of the diffusion layer. In high-volume production, one or more custom masks are used to replace the flash programming function and accordingly retain the need to add programming transistors and programming circuitry.

不像金屬對金屬反熔絲那樣能佈局作為金屬互連之一部分,閃光電路需要封裝在基極擴散層內。因而,在一個離層很遠之上方安裝編程晶體管就沒那麼高效能。本發明之另一選擇案例:藉由矽通孔816將可配置邏輯組件和其閃光組件連接到包括編程晶體管之底層結構814上。 Unlike metal-to-metal antifuse, which can be placed as part of the metal interconnect, the flash circuit needs to be encapsulated in the base diffusion layer. Therefore, it is not so efficient to install the programming transistor on a layer far above. Another option of the present invention: TSVs 816 are used to connect the configurable logic device and its flash device to the underlying structure 814 including programming transistors.

在本文中,組件之表達方式有多種術語表示。例如,“收納盒”指的是帶有晶體管和金屬互連層之第一個單晶層。這個單晶層有時也可指代主要晶圓、受主晶圓或基極晶圓。 In this article, there are various terms for expressing components. For example, "box" refers to the first monocrystalline layer with transistors and metal interconnect layers. This monocrystalline layer is also sometimes referred to as the master wafer, acceptor wafer, or base wafer.

本發明之一些案例包括用構造3D IC系統之技術和方法來開發IC(集成電路)組件之選擇方法。本發明之一些案例,能以比已有技術更少之功耗使組件解決方案得以實現。這些組件解決方案對行動電子組件如行動電話、智能行動電話、相機等之增加應用非常有利。例如,依照本發明之一些案例在這些行動電子組件範圍內併入3D半導體組件可提供高級之行動晶片,比已有技術運行更有效,更持久。 Some examples of the present invention include developing a selection method of IC (Integrated Circuit) components using techniques and methods of constructing 3D IC systems. Some instances of the present invention enable component solutions that consume less power than the prior art. These component solutions are very beneficial for increasing applications of mobile electronic components such as mobile phones, smart phones, cameras, etc. For example, the incorporation of 3D semiconductor components within these mobile electronic components according to some aspects of the present invention can provide advanced mobile chips that operate more efficiently and last longer than prior art.

依照本發明之一些案例,3D IC也能使電子和半導體組件以更高之性能水平運行,鑑於更短之互連以及更加複雜通孔多個級別之半導體組件,且提供修復或使用冗餘之能力。依照本發明一些案例,半導體組件可以達到之複雜性遠遠超過已有技術實踐之水準。這些優點就保證了嵌入式計算機更強勁之計算機系統和改善系統。 According to some examples of the present invention, 3D ICs can also enable electronic and semiconductor components to operate at higher performance levels, in view of shorter interconnects and more complex vias multiple levels of semiconductor components, and provide repair or use redundancy. ability. According to some examples of the present invention, the complexity of semiconductor devices can be achieved far beyond the level of prior art practice. These advantages have just guaranteed the more powerful computer system of embedded computer and improved system.

藉由高密度之3D FPGA或帶有上述縮小定制掩模之不同形式之3D陣列基礎IC,本發明之一些案例也能使現有技術電子系統之設定大幅度節省一次性(NRE)費用。這些系統可分布在許多產品和許多細分市場中。透過開發市場前降低之前期投資風險,NRE之降低使得新產品組或產品週期早期之應用開發和部署成為可能。上述優勢也能透過不同混合方式實現,例如在邏輯層中使用總掩模和存儲層中使用其它總掩模降低NRE,從而建立一個非常複雜之系統,藉由修復技術克服了內在之成品率限制問題。另一個混合方式就是建立3D FPGA並在上面添加3D層定制邏輯和存儲器,這樣終端系統就能在工廠定制邏輯上方擁有現場可編程邏輯。事實上,有很多方式混合極具創意之組件以構成3D IC,來支持一個終端系統之需要,包括運用多個組件,其中不止一個組件併入了發明要素。終端系統可從運用發明3D存儲器和高性能3D FPGA以及高沒密度3D邏輯等中受益。採用由一個或多個發明要素構成之組件可保證更好之性能和/或更低之能耗以及其他發明帶來之優勢,從而為終端系統提供了競爭優勢。這種終端系統應為 基於電子之產品或包括如汽車、遠程控制車輛等某一水平嵌入式電子之其它類型之系統。 Some examples of the present invention can also enable significant non-recurring (NRE) cost savings in the setup of prior art electronic systems with high-density 3D FPGAs or different forms of 3D array-based ICs with the aforementioned scaled-down custom masks. These systems can be distributed across many products and many market segments. By reducing the initial investment risk before developing the market, the reduction of NRE makes it possible to develop and deploy new product groups or applications early in the product cycle. The above mentioned advantages can also be achieved by different hybrid approaches, such as using the overall mask in the logic layer and other overall mask in the memory layer to reduce NRE, thus creating a very complex system, which overcomes the inherent yield limitation by repair technology question. Another hybrid approach is to build a 3D FPGA and add a 3D layer of custom logic and memory on top, so that the end system can have field programmable logic on top of the factory custom logic. In fact, there are many ways to combine highly creative components to form a 3D IC to support the needs of an end system, including using multiple components, more than one of which incorporates the inventive elements. End systems can benefit from the use of inventive 3D memories and high-performance 3D FPGAs, as well as high-density 3D logic. The use of components consisting of one or more of the inventive elements can guarantee better performance and/or lower power consumption, as well as the advantages brought by other inventions, thus providing a competitive advantage for the end system. Such an end system should be Electronics-based products or other types of systems that include some level of embedded electronics such as automobiles, remote control vehicles, etc.

為了提高極小刻度接點之接觸電阻,半導體工業採用各種各樣之金屬矽化物,比如矽化鈷、矽化鈦、二矽化鉭、矽化鎳。現行先進之CMOS工藝,比如45nm、32nm和22nm,採用矽化鎳來提高深亞微米源極和漏極接點之電阻。有關用來降低接頭電阻之矽化物之背景訊息可見《刻度CMOS NiSi自對準矽化物技術》,H.Iwai等人,微電子工程,60(2002),第157~169頁;《亞50nm CMOS之矽化鎳對比矽化鈷集成》,B.Froment等人,IMEC ESS電路,2003年和《65及45nm組件-介紹》,D.James,Semicon West,2008年7月份,ctr_024377。為了達到最低之矽化鎳接觸和源極/漏極電阻,矽上之鎳必須加熱到週四好450℃。 In order to increase the contact resistance of extremely fine-scale contacts, the semiconductor industry uses various metal silicides, such as cobalt silicide, titanium silicide, tantalum disilicide, and nickel silicide. Current advanced CMOS processes, such as 45nm, 32nm and 22nm, use nickel silicide to increase the resistance of deep submicron source and drain contacts. For background information on silicide used to reduce junction resistance, see "Scaled CMOS NiSi Self-Aligned Silicide Technology", H.Iwai et al., Microelectronics Engineering, 60 (2002), pp. 157~169; "Sub-50nm CMOS NiSi vs. CoSi2 Integration", B.Froment et al., IMEC ESS Circuits, 2003 and "65 and 45nm Components - Introduction", D.James, Semicon West, July 2008, ctr_024377. In order to achieve the lowest NiSi contact and source/drain resistance, the nickel-on-silicon must be heated to about 450°C.

因此最好保證本文中工藝流程之低電阻,而由於銅鋁和低k電介質等金屬化後層轉移溫度曝光必須保持在400℃以下。這個典型之工藝流程構成了凹陷溝道陣列晶體管(RCAT),但這樣或類似之流程可應用於其它工藝流程和組件中,比如S-RCAT、JLT、V槽、JEFE、雙極和替代柵極流程。 Therefore, it is best to ensure the low resistance of the process flow in this article, and the layer transfer temperature exposure must be kept below 400°C after metallization such as copper, aluminum and low-k dielectrics. This typical process flow constitutes a recessed channel array transistor (RCAT), but this or a similar flow can be applied to other process flows and components such as S-RCAT, JLT, V-trough, JEFE, bipolar and replacement gate process.

一個適用於3D IC之金屬矽化物源極和漏極接頭之平面n型通路凹陷溝道陣列晶體管(RCAT)是可以構建之。如附圖133A所示,P型襯底之施主晶圓13302加工後包含穿過晶圓之同晶圓大小一樣之N+摻雜層13304和P-摻雜層 13301。N+摻雜層13304可透過離子注入和熱退火技術形成。此外,P-摻雜層13301含有附加之離子注入和退火過程,較P-襯底13302相比提供不一樣之摻雜水準。P-摻雜層13301也具有分級之P-摻雜,可緩解晶體管性能問題,如RCAT形成後之短通路效應。層疊加可為連續外延沉積摻雜之矽P-摻雜層13301和N+摻雜層13304構成,也可透過外延和植入組合技術來實現。植入物退火和摻雜將用到快速熱退火(RTA或尖峰式)光學退火技術或類型。 A planar n-access recessed channel array transistor (RCAT) with metal silicide source and drain contacts for 3D ICs can be constructed. As shown in FIG. 133A, the donor wafer 13302 of the P-type substrate is processed and includes an N+ doped layer 13304 and a P- doped layer that pass through the wafer and are the same size as the wafer. 13301. The N+ doped layer 13304 can be formed by ion implantation and thermal annealing techniques. Additionally, the P-doped layer 13301 contains additional ion implantation and annealing processes that provide a different doping level than the P-substrate 13302. The P-doped layer 13301 also has graded P-doping, which can alleviate transistor performance problems, such as the short channel effect after RCAT formation. Layer stacking can be formed by continuous epitaxial deposition of doped silicon P-doped layer 13301 and N+ doped layer 13304, and can also be realized through a combination of epitaxy and implantation techniques. Implant annealing and doping will use a rapid thermal annealing (RTA or spike) optical annealing technique or type.

如附圖133B所示,矽反應金屬,如鎳或鈷,可沉積到N+摻雜層13304並退火,利用RTA、熱或光學退火工藝,從而形成金屬矽化層13306。施主晶圓13301之頂面應準備好氧化物晶圓接合氧化物沉澱物以形成氧化層13308。 As shown in FIG. 133B, a silicon-reactive metal, such as nickel or cobalt, can be deposited onto the N+ doped layer 13304 and annealed, using RTA, thermal or optical annealing processes, thereby forming a metal silicide layer 13306. The top surface of the donor wafer 13301 should be prepared with an oxide wafer bonding oxide deposit to form the oxide layer 13308.

如附圖133C所示,一個層轉移分隔平面(以虛線表示)13399可透過氫氣注入或上述其他方法形成。 As shown in Figure 133C, a layer transfer separation plane (shown in dashed lines) 13399 may be formed by hydrogen implantation or other methods as described above.

如附圖133D所示,包含層轉移分隔平面13399、P-摻雜層13301、N+摻雜層13304、金屬矽化層13306和氧化層13308之施主晶圓13302,透過輔助低壓釋放之低壓工藝能暫時接合到載體或支架襯底13312上。載體或支架襯底13312應為玻璃襯底,使得一流之光學工藝與受主晶圓一致。載體或支架襯底13312和施主晶圓13302之間之臨時接合物可為聚合材料,例如聚酰亞胺杜邦HD3007,它可透過鐳射燒蝕、紫外線輻射曝光或熱分解方式在後期釋放為所示之黏合層13314。或者,臨時接合物也可透過單極或雙極靜電技術,如Beam Services公司之Apache工具進行製 備。 As shown in Figure 133D, the donor wafer 13302 including layer transfer separation plane 13399, P-doped layer 13301, N+ doped layer 13304, metal silicide layer 13306 and oxide layer 13308 can be temporarily Bonded to a carrier or carrier substrate 13312. The carrier or holder substrate 13312 should be a glass substrate to enable state-of-the-art optical processing consistent with the acceptor wafer. The temporary bond between the carrier or carrier substrate 13312 and the donor wafer 13302 can be a polymeric material, such as polyimide DuPont HD3007, which can be released at a later stage by laser ablation, exposure to ultraviolet radiation, or thermal decomposition as shown The adhesive layer 13314. Alternatively, temporary joints can also be made by unipolar or bipolar electrostatic techniques, such as Apache tools from Beam Services, Inc. prepare.

如附圖133E所示,施主晶圓13302位於層轉移分隔平面13399之部分可透過裂開或上述其他工藝如離子切除或其它方法進行移除。剩餘之施主晶圓P-摻雜層13301可透過化學機械拋光(CMP)工藝變細,這樣P-層13316就能達到預期之厚度。氧化物13318可沉積到P-層13316之曝光面上。 As shown in Figure 133E, the portion of the donor wafer 13302 at the layer transfer separation plane 13399 may be removed by cleaving or other processes as described above such as ion ablation or other methods. The remaining donor wafer P-doped layer 13301 can be thinned by a chemical mechanical polishing (CMP) process so that the P-layer 13316 can reach the desired thickness. Oxide 13318 may be deposited onto the exposed side of the P- layer 13316 .

如附圖133F所示,施主晶圓13302和受主襯底或晶圓13301均可為前述之晶圓接合做好準備,然後低溫(低於400℃)對準,氧化物對氧化物接合。前述之受主襯底13310會兼顧到晶體管、電路、鋁或銅等金屬、互連接線和直通層通孔金屬互連條或盤,然後利用鐳射燒蝕等低溫工藝釋放載體或支架襯底13312和施主晶圓13302。氧化層13318、P-層13316、N+摻雜層13304、金屬矽化層13306和氧化層13308層轉移到受主晶圓13310。氧化物13308之頂面可透過化學或機械方式拋光。當前RCAT晶體管利用低溫(低於400℃)工藝形成後對準與受主晶圓13310對準標記(未體現)。 As shown in Figure 133F, both the donor wafer 13302 and the acceptor substrate or wafer 13301 can be prepared for the aforementioned wafer bonding, followed by low temperature (below 400°C) aligned, oxide-to-oxide bonding. The aforementioned acceptor substrate 13310 will take care of transistors, circuits, metals such as aluminum or copper, interconnection wires, and metal interconnection strips or disks through layer through holes, and then use low-temperature processes such as laser ablation to release the carrier or support substrate 13312 and donor wafer 13302. Oxide layer 13318 , P- layer 13316 , N+ doped layer 13304 , metal silicide layer 13306 and oxide layer 13308 are layer transferred to acceptor wafer 13310 . The top surface of oxide 13308 can be chemically or mechanically polished. Current RCAT transistors are post-aligned and acceptor wafer 13310 alignment marks (not shown) are formed using a low temperature (below 400°C) process.

如附圖133G所示,晶體管隔離區13322透過掩模定義形成,之後等離子體/RIE將氧化層13308、金屬矽化層13306、N+摻雜層13304和P-層13316蝕刻到氧化層13318之上面。然後低溫填隙氧化物沉積並經化學機械拋光,而氧化物保留在隔離區13322。因此,凹陷溝道13323進行掩模定義和蝕刻。凹陷溝道表面和邊角透過濕式化學或等離子 體/RIE蝕刻工藝變得光滑,從而緩解高場效應。這些工藝步驟構成了氧化物區13324、金屬矽化物源極和漏極區13326,N+源極和漏極區13328和P-溝道區13330。 As shown in FIG. 133G, the transistor isolation region 13322 is defined through the mask, and then the oxide layer 13308, the metal silicide layer 13306, the N+ doped layer 13304 and the P- layer 13316 are etched on top of the oxide layer 13318 by plasma/RIE. A low temperature interstitial oxide is then deposited and chemical mechanically polished, while the oxide remains in the isolation region 13322. Thus, the recessed channel 13323 is mask defined and etched. Recessed channel surfaces and corners permeated by wet chemical or plasma The bulk/RIE etch process is smoothed to mitigate high field effects. These process steps form oxide region 13324 , metal silicide source and drain region 13326 , N+ source and drain region 13328 and P- channel region 13330 .

如附圖133H所示,柵極介質13332形成而柵極金屬材料沉積。柵極介質13332為一原子層沉積(ALD)柵極介質,與前述之同業標準高k金屬柵極工藝方案中之功函數特定柵極金屬成對。或者柵極介質13332形成於矽表面之低溫氧化物沉積或低溫微波等離子體氧化,然後柵極材質如鎢或鋁則會沉積下來。最後柵極材料經化學機械拋光,而柵極面積經掩模和蝕刻確定後形成柵電極13334。 As shown in Figure 133H, gate dielectric 13332 is formed and gate metal material is deposited. Gate dielectric 13332 is an atomic layer deposition (ALD) gate dielectric paired with a work function specific gate metal in the industry standard high-k metal gate process scheme described above. Or the gate dielectric 13332 is formed on the silicon surface by low-temperature oxide deposition or low-temperature microwave plasma oxidation, and then the gate material such as tungsten or aluminum will be deposited. Finally, the gate material is chemically mechanically polished, and the area of the gate is determined by masking and etching to form the gate electrode 13334 .

如附圖133I所示,低溫厚氧化物13338沉積,而源極、柵極和漏極接頭以及直通層通孔(未體現)開口經掩模和蝕刻後製備晶體管,透過金屬化連接。因此,柵極接頭13342連接到柵電極13334,而源極和漏極接頭13336連接到金屬矽化物源極和漏極區13326。 As shown in Figure 133I, a low temperature thick oxide 13338 is deposited, and the source, gate and drain contacts and through layer via (not shown) openings are masked and etched to produce transistors connected through metallization. Thus, gate contact 13342 is connected to gate electrode 13334 , while source and drain contacts 13336 are connected to metal suicide source and drain regions 13326 .

通常所屬技術領域之知識者知悉,附圖133A到附圖133I中之介紹只為舉例目的,因此未依照比例作圖。這些技術人員將進一步知悉很多變化都是可能的,例如臨時載體襯底可由載體晶圓取代,而附圖40中所示之永久接合載體晶圓流程可得到應用。本發明範圍內之很多其他修改方案,待這些專業技術人員仔細閱讀後會適時引薦自己。因此本發明範圍只在所附權利要求範圍內。 Those of ordinary skill in the art will appreciate that the illustrations in Figures 133A through 133I are for illustration purposes only and thus are not drawn to scale. Those skilled in the art will further appreciate that many variations are possible, for example the temporary carrier substrate can be replaced by a carrier wafer and the permanently bonded carrier wafer flow shown in Figure 40 can be used. Many other modifications within the scope of the present invention will be recommended in due course by these professionals after careful reading. The scope of the invention is therefore only as defined by the appended claims.

由於本發明案例採用而涉及之高密度層對層互連以及存儲組件和晶體管之形成,採用新之FPGA(現場可編程 邏輯門陣列)編程結構和組件可節省成本、空間並提高3D FPGA之性能。通路晶體管或開關及控制通路晶體管開關狀態之存儲組件可位於不同層內,並透過直通層通孔(TLV)與彼此和佈線網路金屬線連接,或者通路晶體管和存儲組件可處於同一層,而採用TLV連至網路金屬線。 Due to the formation of the high-density layer-to-layer interconnection and storage components and transistors involved in the case of the present invention, a new FPGA (field programmable Logic gate array) programming structures and components can save cost, space and improve the performance of 3D FPGA. The pass transistor or switch and the storage element that controls the switch state of the pass transistor can be located in different layers and connected to each other and the wiring network metal line through the through layer via (TLV), or the pass transistor and the storage element can be in the same layer, and Use TLV to connect to the network metal line.

如附圖134A所示,受主晶圓13400加工後兼顧邏輯電路、模擬電路和其他組件,同金屬互連和金屬配置網路形成基礎之FPGA。受主晶圓13400也包括配置組件,如開關、通路晶體管、存儲晶片、編程晶體管,並包含上述一層或多層基礎層。 As shown in Figure 134A, the acceptor wafer 13400 is processed to accommodate logic circuits, analog circuits and other components, with metal interconnects and metal configuration networks forming the basis of the FPGA. The acceptor wafer 13400 also includes configuration components such as switches, pass transistors, memory chips, programming transistors, and includes one or more base layers as described above.

如附圖134B所示,施主晶圓13402以一層或多層通路晶體管或開關或局部構成之通路晶體管或開關進行預處理。通路晶體管可利用上述之局部晶體管工藝流程(如RCAT或JLT或其它)或運用替代柵極技術(如CMOS或CMOS N~P或門陣列,帶或不帶上述之載體晶圓)進行構建。施主晶圓13402和受主襯底13400及相關表面為上述之晶圓接合做好準備。 As shown in Figure 134B, the donor wafer 13402 is preprocessed with one or more layers of pass transistors or switches or partially formed pass transistors or switches. Pass transistors can be constructed using the local transistor process flow described above (such as RCAT or JLT or others) or using replacement gate technology (such as CMOS or CMOS N~P OR gate array, with or without the above-mentioned carrier wafer). The donor wafer 13402 and acceptor substrate 13400 and associated surfaces are prepared for wafer bonding as described above.

如附圖134C所示,施主晶圓13402和受主襯底13400在低溫狀態下接合(低於400℃),而施主晶圓13402之一部分透過裂開和拋光或上述其它方式如離子切割或其它方法進行移除,從而形成剩餘之通路晶體管層13402。當前,晶體管或晶體管之多個部分形成或完成,並對準於上述之受主襯底13400對準標記(未體現)。直通層通孔(TLV)13410可透過上述方式形成,互連和介質層同 理,然後形成了帶通路晶體管13400A之受主襯底,包括受主襯底13400、通路晶體管層13402和TLV 13410。 As shown in Figure 134C, the donor wafer 13402 and the acceptor substrate 13400 are bonded at a low temperature (below 400°C), and a portion of the donor wafer 13402 is cleaved and polished or otherwise described above such as ion dicing or other method to remove, thereby forming the remaining pass transistor layer 13402. Currently, transistors or portions of transistors are formed or completed and aligned to the above-mentioned acceptor substrate 13400 alignment marks (not shown). Through layer via (TLV) 13410 can be formed through the above-mentioned method, interconnection and dielectric layer are the same Then, the acceptor substrate with pass transistor 13400A is formed, including acceptor substrate 13400, pass transistor layer 13402 and TLV 13410.

如附圖134D所示,存儲晶片施主晶圓13404用一層或多層之存儲晶片或局部形成之存儲晶片進行預處理。存儲晶片可利用上述之局部存儲器工藝流程(如RCAT DRAM、JLT或其它)或運用替代柵極技術如CMOS門陣列新年工程SRAM組件,帶或不帶上述之載體晶圓之方式,抑或透過非易失性存儲器如R-RAM或上述FG快閃進行構建。存儲晶片施主晶圓13402和受主襯底13400A及相關表面為上述之晶圓接合做好準備。 As shown in Figure 134D, the memory wafer donor wafer 13404 is preprocessed with one or more layers of memory wafers or partially formed memory wafers. The memory chip can use the above-mentioned local memory process flow (such as RCAT DRAM, JLT or others) or use alternative gate technology such as CMOS gate array New Year's project SRAM components, with or without the above-mentioned carrier wafer, or through non-easy A volatile memory such as R-RAM or the aforementioned FG flash is constructed. Storage wafers The donor wafer 13402 and acceptor substrate 13400A and associated surfaces are prepared for wafer bonding as described above.

如附圖134E所示,存儲晶片施主晶圓13404和受主襯底13400A在低溫狀態下接合(低於400℃),而存儲晶片施主晶圓13404之一部分透過裂開和拋光或上述其它方式如離子切割或其它方法進行移除,從而形成剩餘之存儲晶片層13404。當前,存儲晶片和晶體管或晶體管之多個部分形成或完成,並對準於上述之受主襯底13400A對準標記(未體現)。存儲器到開關直通層通孔13420和存儲器到受主直通層通孔13430以及互連和介質層以上述方式構成,從而形成了帶通路晶體管和存儲晶片13400B之受主襯底,包括受主襯底13400、通路晶體管層13402、TLV 13410、存儲器到開關直通層通孔13420、存儲器到受主直通層通孔13430和存儲晶片層13404。 As shown in Figure 134E, the storage wafer donor wafer 13404 and the acceptor substrate 13400A are bonded at low temperature (below 400°C), and a portion of the storage wafer donor wafer 13404 is cleaved and polished or otherwise described as described above. Ion dicing or other methods remove, thereby forming the remaining memory wafer layer 13404. Currently, a memory wafer and transistors or portions of transistors are formed or completed and aligned to the above-described acceptor substrate 13400A alignment marks (not shown). Memory-to-switch TLV 13420 and memory-to-acceptor TLV 13430 and interconnects and dielectric layers are constructed in the manner described above to form the acceptor substrate with pass transistors and memory die 13400B, including the acceptor substrate 13400 , Pass Transistor Layer 13402 , TLV 13410 , Memory-to-Switch SLV 13420 , Memory-to-Acceptor SLV 13430 , and Memory Wafer Layer 13404 .

如附圖134F所示,這是一個帶通路晶體管和存儲晶片13400B之受主襯底重要組件之簡單示意圖。一個位於存儲 晶片層13404之典型存儲晶片13440可電耦到一個位於通路晶體管層之典型通路晶體管柵極13442,其包含存儲器到開關直通層通孔13420。一個位於通路晶體管層13402之通路晶體管源極13444可電耦到位於受主襯底13400並帶有TLV 13410A之FPGA配置網路金屬線13446。一個位於通路晶體管層13402之通路晶體管漏極13445可電耦到位於受主襯底13400並帶有TLV 13410B之FPGA配置網路金屬線13447。存儲晶片13440之編程訊號來自芯片外,或位於存儲晶片層13404之上方、內部或下方。存儲晶片13440也包括一個逆向配置,其中一個存儲組件,例如FG快閃組件,開啟時可將通路晶體管之柵極耦合到地面。因此,攜帶來自受主襯底13400邏輯晶片之輸出訊號之FPGA配置網路金屬線13446可電耦到FPGA配置網路金屬線13447,它將佈線到受主襯底13430中之一個邏輯晶片之輸入上。 As shown in Figure 134F, which is a simplified schematic diagram of the main components of a receiver substrate with pass transistors and memory wafer 13400B. one in storage A representative memory die 13440 of the die layer 13404 may be electrically coupled to a representative pass transistor gate 13442 at the pass transistor layer, which includes a memory-to-switch pass-through layer via 13420 . A pass transistor source 13444 on pass transistor layer 13402 may be electrically coupled to FPGA configuration network metal line 13446 on acceptor substrate 13400 with TLV 13410A. A pass transistor drain 13445 in pass transistor layer 13402 can be electrically coupled to FPGA configuration network metal line 13447 on acceptor substrate 13400 with TLV 13410B. The programming signals for the memory chip 13440 come from outside the chip, or located above, inside or below the memory chip layer 13404 . Memory die 13440 also includes an inverse configuration where a memory element, such as a FG flash element, is turned on to couple the gate of the pass transistor to ground. Thus, the FPGA configuration net metal line 13446 carrying the output signal from the logic chip in the acceptor substrate 13400 can be electrically coupled to the FPGA configuration net metal line 13447, which will be routed to the input of one of the logic chips in the acceptor substrate 13430 superior.

通常所屬技術領域之知識者知悉,附圖134A到附圖134F中之介紹只為舉例目的,因此未依照比例作圖。這些技術人員將進一步知悉很多變化都有可能,例如存儲晶片層13404可構建於通路晶體管層13402下面。另外,通路晶體管層13402除通路晶體管和開關外還包括控制和邏輯電路。此外,存儲晶片層13404包含除存儲晶片外之控制和邏輯電路。因此,通路晶體管組件反過來可為傳輸門電路,或者為有源驅動類型之開關。本發明範圍內之很多其他修改方案,待這些專業技術人員仔細閱讀後會適時引薦自己。因此本發明範圍只在所附權利要求範圍內。 Those of ordinary skill in the art appreciate that the illustrations in Figures 134A through 134F are for illustration purposes only and thus are not drawn to scale. Those skilled in the art will further appreciate that many variations are possible, for example memory die layer 13404 may be built under pass transistor layer 13402 . Additionally, pass transistor layer 13402 includes control and logic circuitry in addition to pass transistors and switches. In addition, the memory die layer 13404 contains control and logic circuits in addition to the memory die. Thus, the pass transistor element can in turn be a transmission gate, or an actively driven type switch. Many other modifications within the scope of the present invention will be recommended in due course by these professionals after careful reading. The scope of the invention is therefore only as defined by the appended claims.

控制通路晶體管ON或OFF狀態之通路晶體管或開關以及存儲組件處於同一層,而TLV可用來連至網路金屬線。如附圖135A所示,受主晶圓13500加工後可兼顧邏輯電路、模擬電路和其他組件,與金屬互連和金屬配置網路一同構成基礎之FPGA。受主晶圓13500也可包括配置組件,例如開關、通路晶體管、存儲晶片、可編程晶體管,以及包含上述一層或多層之基礎層。 The pass transistor or switch that controls the ON or OFF state of the pass transistor and the memory element are on the same layer, and the TLV can be used to connect to the net metal line. As shown in FIG. 135A , the acceptor wafer 13500 can be processed to accommodate logic circuits, analog circuits and other components, together with metal interconnects and metal configuration networks to form the basic FPGA. The acceptor wafer 13500 may also include configuration components such as switches, pass transistors, memory chips, programmable transistors, and a base layer comprising one or more layers of the foregoing.

如附圖135B所示,施主晶圓13502以一層或多層通路晶體管或開關或局部構成之通路晶體管或開關進行預處理。通路晶體管可利用上述之局部晶體管工藝流程(如RCAT或JLT或其它)或運用替代柵極技術(如CMOS或CMOS N~P或CMOS門陣列,帶或不帶上述之載體晶圓)進行構建。施主晶圓13502以一層或多層存儲晶片或局部構成之存儲晶片進行預處理。存儲晶片可利用上述之局部存儲器工藝流程(如RCAT DRAM或其它)或運用替代柵極技術(如CMOS門陣列,帶或不帶上述之載體晶圓)進行構建。例如透過運用CMOS門陣列替代柵極工藝,可實現存儲晶片和通路晶體管之同步形成,其中CMOS通路晶體管和SRAM存儲晶片,例如一個6個晶體管晶片產生或一個RCAT通路晶體管與RCAT DRAM存儲器產生。施主晶圓13502和受主襯底13500及相關表面為上述之晶圓接合做好準備。 As shown in Figure 135B, the donor wafer 13502 is preprocessed with one or more layers of pass transistors or switches or partially formed pass transistors or switches. Pass transistors can be constructed using the local transistor process flow described above (such as RCAT or JLT or others) or using replacement gate technology (such as CMOS or CMOS N~P or CMOS gate array, with or without the above-mentioned carrier wafer). Donor wafer 13502 is preprocessed with one or more layers of memory wafers or partially formed memory wafers. Memory chips can be constructed using the local memory process flow described above (such as RCAT DRAM or others) or using replacement gate technology (such as CMOS gate arrays, with or without the above-mentioned carrier wafer). For example, by using a CMOS gate array to replace the gate process, the simultaneous formation of memory chips and pass transistors can be realized, wherein CMOS pass transistors and SRAM memory chips, for example, a 6-transistor chip is produced or an RCAT pass transistor is produced with RCAT DRAM memory. The donor wafer 13502 and acceptor substrate 13500 and associated surfaces are prepared for wafer bonding as described above.

如附圖135C所示,施主晶圓13502和受主襯底13500在低溫狀態下接合(低於400℃),而施主晶圓13502之一部 分透過裂開和拋光或上述其它方式如離子切割或其它方法進行移除,從而形成剩餘之通路晶體管層和存儲層13502。當前,晶體管或晶體管之多個部分形成或完成,並對準於上述之受主襯底13500對準標記(未體現)。直通層通孔(TLV)13510可透過上述方式形成,然後帶通路晶體管和存儲晶片13500A之受主襯底產生,它包括受主襯底13500、通路晶體管層13502和TLV 13510。 As shown in FIG. 135C , the donor wafer 13502 and the acceptor substrate 13500 are bonded at a low temperature (below 400° C.), and a part of the donor wafer 13502 The remaining pass transistor layer and memory layer 13502 are formed by cleaving and polishing or other means as described above such as ion dicing or other methods. Currently, transistors or portions of transistors are formed or completed and aligned to the above-mentioned acceptor substrate 13500 alignment marks (not shown). Through layer vias (TLVs) 13510 can be formed in the above manner, and then the acceptor substrate with pass transistors and memory wafer 13500A is produced, which includes acceptor substrate 13500, pass transistor layer 13502 and TLV 13510.

如附圖135D所示,這是一個帶通路晶體管和存儲晶片13500A之受主襯底重要組件之簡單示意圖。一個位於通路晶體管和存儲層13502之典型存儲晶片13540可電耦到一個位於通路晶體管層13502之典型通路晶體管柵極13542,其包含通路晶體管和存儲層互連金屬化13525。一個位於通路晶體管和存儲層13502之通路晶體管源極13544可電耦到位於受主襯底13500並帶有TLV 13510A之FPGA配置網路金屬線13546。一個位於通路晶體管和存儲層13502之通路晶體管漏極13545可電耦到位於受主襯底13500並帶有TLV 13510B之FPGA配置網路金屬線13547。存儲晶片13540之編程訊號來自芯片外,或位於通路晶體管和存儲晶片層13502之上方、內部或下方。存儲晶片13540也包括一個逆向配置,其中一個存儲組件,例如FG快閃組件,開啟時可將通路晶體管之柵極耦合到電源電壓,而另一個FG快閃組件開啟時可將通路晶體管柵極耦合到地面。因此,攜帶來自受主襯底13500邏輯晶片之輸出訊號之FPGA配置網路金屬線13546可電耦到FPGA配置網路金屬線13547,它 將佈線到受主襯底13530中之一個邏輯晶片之輸入上。 As shown in Figure 135D, which is a simplified schematic diagram of the main components of a receiver substrate with pass transistors and memory wafer 13500A. A representative memory die 13540 at the pass transistor and memory layer 13502 can be electrically coupled to a representative pass transistor gate 13542 at the pass transistor layer 13502 , which includes the pass transistor and memory layer interconnect metallization 13525 . A pass transistor source 13544 on the pass transistor and storage layer 13502 can be electrically coupled to an FPGA configuration network metal line 13546 on the acceptor substrate 13500 with TLV 13510A. A pass transistor drain 13545 located in the pass transistor and memory layer 13502 can be electrically coupled to an FPGA configuration network metal line 13547 located on the acceptor substrate 13500 with TLV 13510B. The programming signals for the memory chip 13540 come from outside the chip, or above, inside or below the pass transistors and the memory chip layer 13502 . Memory die 13540 also includes an inverse configuration where one memory element, such as a FG flash element, is turned on to couple the gate of the pass transistor to the supply voltage, and the other FG flash element is turned on to couple the gate of the pass transistor to the supply voltage. to the ground. Accordingly, FPGA configuration net metal lines 13546 carrying output signals from the acceptor substrate 13500 logic die may be electrically coupled to FPGA configuration net metal lines 13547, which A wire will be routed to the input of one of the logic chips in the acceptor substrate 13530.

通常所屬技術領域之知識者知悉,附圖135A到附圖134D中之介紹只為舉例目之,因此未依照比例作圖。這些技術人員將進一步知悉很多變化都是可能之,例如通路晶體管和存儲層13502除通路晶體管或開關和存儲晶片外還包括控制和邏輯電路。此外,通路晶體管組件反過來可為傳輸門電路,或者為有源驅動類型之開關。本發明範圍內之很多其他修改方案,待這些專業技術人員仔細閱讀後會適時引薦自己。因此本發明範圍只在所附權利要求範圍內。 Those of ordinary skill in the art appreciate that the illustrations in Figures 135A through 134D are for illustration purposes only and thus are not drawn to scale. Those skilled in the art will further appreciate that many variations are possible, such as pass transistors and memory layer 13502 including control and logic circuitry in addition to pass transistors or switches and memory die. Furthermore, the pass transistor element can in turn be a transmission gate, or an actively driven type switch. Many other modifications within the scope of the present invention will be recommended in due course by these professionals after careful reading. The scope of the invention is therefore only as defined by the appended claims.

如附圖136所示,這是一個帶集成浮動門(FG)閃存之示意圖。控制門13602和浮動門13604常用於感應晶體管通路13620和開關晶體管通路13610。開關晶體管源極13612和開關晶體管漏極13614耦合到FPGA配置網路金屬線上。感應晶體管源極13622和感應晶體管漏極13624耦合到程式、抹音和讀取電路。這種集成之NVM開關為FPGA生產廠商Actel公司所用並採用高溫(高於400℃)下之2D嵌入式FG快閃工藝技術進行製備。 As shown in Figure 136, which is a schematic diagram of a flash memory with integrated floating gate (FG). Control gate 13602 and floating gate 13604 are commonly used for sense transistor pass 13620 and switch transistor pass 13610 . Switching transistor source 13612 and switching transistor drain 13614 are coupled to FPGA configuration network metal lines. Sense transistor source 13622 and sense transistor drain 13624 are coupled to programming, erasing and reading circuits. This integrated NVM switch is used by FPGA manufacturer Actel and is prepared by 2D embedded FG flash technology under high temperature (higher than 400°C).

如附圖137A~137G所示,一個1T NVM FPGA組件透過適用於3D IC生產工藝流程之單層轉移之晶圓大小摻雜層和後層轉移進行構建。這個組件之編程訊號來自芯片外,或位於組件層之上方、內部或下方。 As shown in Figures 137A-137G, a 1T NVM FPGA device is constructed by wafer-sized doped layer transfer and post-layer transfer suitable for single-layer transfer in a 3D IC production process. The programming signals for this device come from outside the chip, either above, inside or below the device layer.

如附圖137A所示,一個P-襯底之施主晶圓13700處理後包含兩個晶圓大小之N+摻雜層和P-摻雜層13706。較P- 襯底13700相比,P-摻雜層13706有同樣或不同之摻雜濃度。摻雜層可透過離子注入和熱退火方式產生。層疊加可為連續外延沉積摻雜之矽層構成,也可透過外延和植入及退火組合技術實現。P-摻雜層13706和N+摻雜層13704也可具有分級摻雜來緩解晶體管性能問題,如短通路效應,並提高編程和消音效能。植入前,屏蔽氧化物13701將增長或沉積,以保護矽不受注入污染影響,並為後期之晶圓對晶圓接合提供氧化物表面。這些工藝都應在400℃以上完成,因為層轉移到帶金屬互連之加工襯底尚待完成。 As shown in FIG. 137A, a P-substrate donor wafer 13700 is processed to contain two wafer-sized N+ doped layers and P- doped layers 13706. Compared to P- Compared to the substrate 13700, the P-doped layer 13706 has the same or different doping concentration. The doped layer can be produced by ion implantation and thermal annealing. Layer stacking can be formed by continuous epitaxial deposition of doped silicon layers, or it can be realized by a combination of epitaxy, implantation and annealing. P-doped layer 13706 and N+ doped layer 13704 can also have graded doping to alleviate transistor performance issues such as short channel effects, and to improve programming and noise cancellation performance. Before implantation, a screen oxide 13701 will be grown or deposited to protect the silicon from implant contamination and provide an oxide surface for later wafer-to-wafer bonding. These processes should all be done above 400°C because layer transfer to the processed substrate with metal interconnects is yet to be done.

如附圖137B所示,施主晶圓13700之頂面可透過沉積氧化物13702或透過P-摻雜層13706之熱氧化作用形成氧化層13702或透過注入屏蔽氧化物13701之再氧化作用做好氧化物晶圓接合準備。一個層轉移分隔平面13799(以虛線表示)可透過氫氣注入或上述其他方法在施主晶圓13700(有體現)或N+摻雜層13704內形成。施主晶圓13700和受主晶圓13710均可為上述之晶圓接合做好準備,然後進行低溫(低於400℃)接合。位於層轉移分隔平面13799上方之P-施主晶圓襯底13700部分可透過裂開和拋光或上述之其它低溫工藝進行移除。這種離子注入原子種類,例如氫氣,而形成層轉移分隔平面以及隨後之裂開或變細做法稱為“離子切割”。參照附圖8,受主晶圓13710與上述之晶圓808有相同之意思。 As shown in Figure 137B, the top surface of the donor wafer 13700 can be oxidized by depositing an oxide 13702 or by thermal oxidation of the P-doped layer 13706 to form an oxide layer 13702 or by re-oxidation of an implanted barrier oxide 13701 object wafer bonding preparation. A layer transfer separation plane 13799 (shown in dashed lines) can be formed in the donor wafer 13700 (shown) or the N+ doped layer 13704 by hydrogen implantation or other methods as described above. Both the donor wafer 13700 and the acceptor wafer 13710 can be prepared for wafer bonding as described above, followed by low temperature (less than 400° C.) bonding. Portions of the P-donor wafer substrate 13700 above the layer transfer separation plane 13799 may be removed by cleaving and polishing or other low temperature processes as described above. This ion implantation of atomic species, such as hydrogen, to form layer transfer separation planes and subsequent cleaving or thinning is called "ion cutting". Referring to FIG. 8 , the acceptor wafer 13710 has the same meaning as the aforementioned wafer 808 .

如附圖137C所示,剩餘之N+摻雜層13704和P-摻雜層13706以及氧化層13702已經層轉移到受主晶圓13710。N+ 摻雜層13704之頂面可化學或機械拋光磨平。因此,FG和其他晶體管可透過低溫(低於400℃)過程且對準受主晶圓13710對準標誌(未體現)而產生。為了闡釋清楚,用來輔助晶圓對晶圓接合之氧化層,例如13702,未體現在隨後之圖紙中。 The remaining N+ doped layer 13704 and P- doped layer 13706 and oxide layer 13702 have been layer transferred to the acceptor wafer 13710 as shown in FIG. 137C . N+ The top surface of the doped layer 13704 can be chemically or mechanically polished. Therefore, FG and other transistors can be produced by low temperature (less than 400°C) process and aligned to the acceptor wafer 13710 alignment marks (not shown). Oxide layers, such as 13702, used to aid in wafer-to-wafer bonding are not shown in the subsequent drawings for clarity of illustration.

如附圖137D所示,晶體管隔離區經微影定義,且經由等離子體/RIE蝕刻去除多個N+摻雜層13704和P-摻雜層13706到至少受主襯底13710之上氧化物。然後一個低溫填隙氧化物沉積並經化學機械拋光,保留在晶體管隔離區13720和西南至東南方向之隔離區13721。附圖137中之“西南”代表之是開關晶體管形成之位置,而“東南”則代表之感應晶體管形成之位置,因而產生之為未來晶體管西南區N+摻雜層13714和P-摻雜層13716,以及未來晶體管東南區N+摻雜13715和P-摻雜13717 As shown in Figure 137D, transistor isolation regions are lithographically defined, and a plurality of N+ doped layers 13704 and P- doped layers 13706 are removed via plasma/RIE etching to at least the oxide above the acceptor substrate 13710. A low temperature interstitial oxide is then deposited and chemical mechanically polished, leaving transistor isolation region 13720 and southwest to southeast isolation region 13721. "Southwest" in the accompanying drawing 137 represents the position where the switching transistor is formed, while "southeast" represents the position where the sensing transistor is formed, so it is the N+ doped layer 13714 and the P-doped layer 13716 in the southwestern region of the future transistor. , and N+ doping 13715 and P-doping 13717 in the southeast region of future transistors

如附圖137E所示,西南凹陷溝道13742和東南凹陷溝道13743可微影定義並蝕刻,去除多個未來晶體管西南區N+摻雜13714和P-摻雜13716,及未來晶體管西南區N+摻雜13715和P-摻雜13717。凹陷溝道之表面和邊角可透過濕式化學或等離子體/RIE蝕刻工藝弄平,以緩解高場效應。西南凹陷之溝道13742和東南凹陷之溝道13743分開或同步掩模定義和蝕刻。西南溝道寬度比東南溝道寬度要大。這些工藝步驟形成了西南源極和漏極區13724,東南源極和漏極區13725,西南晶體管溝道區13716和東南晶體管溝道區13717。 As shown in Figure 137E, the southwest recessed channel 13742 and the southeast recessed channel 13743 can be lithographically defined and etched to remove N+ doping 13714 and P- doping 13716 in the southwest region of future transistors, and N+ doping in the southwest region of future transistors. Doped 13715 and P-doped 13717. The surface and corners of the recessed trenches can be flattened by wet chemical or plasma/RIE etching processes to mitigate high field effects. The southwest recessed trench 13742 and the southeastern recessed trench 13743 are separately or simultaneously mask defined and etched. The southwest channel width is larger than the southeast channel width. These process steps form the southwest source and drain region 13724 , the southeast source and drain region 13725 , the southwest transistor channel region 13716 and the southeast transistor channel region 13717 .

如附圖137F所示,隧道施工介質13711形成,而浮動門材料沉積。隧道施工介質13711為一種原子層沉積(ALD)介質。或隧道施工介質13711形成低溫氧化物沉積或矽表面之低溫微波等離子體氧化。然後浮動門材料,例如摻雜多晶體或非晶矽沉積下來。最後,浮動門材料經化學機械拋光,而浮動門13752則透過微影定義和等離子體/RIE蝕刻部分或全部形成。 As shown in Figure 137F, the tunnel construction medium 13711 is formed and the floating gate material is deposited. Tunnel construction medium 13711 is an atomic layer deposition (ALD) medium. Or tunnel construction dielectric 13711 to form low temperature oxide deposition or low temperature microwave plasma oxidation of silicon surface. Then the floating gate material, such as doped polycrystalline or amorphous silicon, is deposited. Finally, the floating gate material is chemically mechanically polished, while the floating gate 13752 is partially or fully formed by lithographic definition and plasma/RIE etching.

如附圖137G所示,多晶矽層間介質體13741透過低溫氧化和介質沉積或多層介質,例如氧化物-氮化物-氧化物(ONO)層產生,而控制門材料,例如摻雜多晶體或非晶矽,沉積下來。控制門材料經化學機械拋光後,控制門13754透過微影定義和等離子體/RIE蝕刻產生。控制門13754之蝕刻範圍也包括多個採用自對準疊層蝕刻工藝之多晶矽層間介質體和浮動門13752。控制功能之邏輯晶體管透過採用本文描述之3D IC兼容法(例如RCAT、V-槽和接頭以及直通層通孔)而產生(未體現),且互連金屬化由此構建。該流程使得單晶矽1T NVM FPGA配置組件構建在單層轉移之預製式晶圓大小之摻雜層中,而摻雜層在高溫下不曝光下層組件之情況下產生並連接到下層多金屬層半導體組件。 As shown in Figure 137G, interpoly dielectric body 13741 is produced by low temperature oxidation and dielectric deposition or multi-layer dielectric, such as oxide-nitride-oxide (ONO) layer, and the control gate material, such as doped polycrystalline or amorphous Silicon, deposited. After the control gate material is chemically mechanically polished, the control gate 13754 is produced by lithographic definition and plasma/RIE etching. The etching range of the control gate 13754 also includes a plurality of polysilicon interlayer dielectric bodies and the floating gate 13752 using a self-aligned stack etching process. Logic transistors for control functions are created (not shown) by employing 3D IC compatible methods described herein (eg, RCAT, V-grooves and contacts, and through-layer vias), and interconnect metallization is constructed thereby. This process enables monocrystalline silicon 1T NVM FPGA configuration components to be built in prefabricated wafer-sized doped layers transferred from a single layer, and the doped layers are generated and connected to the underlying multi-metal layer at high temperatures without exposing the underlying components semiconductor components.

通常所屬技術領域之知識者知悉,附圖137A到附圖137G中之介紹只為舉例目之,因此未依照比例作圖。這些技術人員將進一步知悉很多變化都是可能之,例如浮動門包含矽納米晶粒和其他材料。另外,一個通用之組件可透 過去除西南至東南方向之隔離區13721而產生。此外,溝道晶體管之凹陷坡度為0~180度。而且,邏輯晶體管和組件可透過將控制門作為組件門使用而產生。邏輯組件門與控制門形成可分開完成。需要補充之是,1T NVM FPGA配置組件可透過電荷捕獲技術NVM、抗存儲技術產生,也可具有無接合西南或東南晶體管構造。本發明範圍內之很多其他修改方案,待這些專業技術人員仔細閱讀後會適時引薦自己。因此本發明範圍只在所附權利要求範圍內。 Those of ordinary skill in the art appreciate that the illustrations in Figures 137A to 137G are for illustration purposes only and thus are not drawn to scale. Those skilled in the art will further appreciate that many variations are possible, such as floating gates incorporating silicon nanocrystals and other materials. Additionally, a generic component can be Generated in the past by removing the isolation zone 13721 from southwest to southeast. In addition, the slope of the recess of the channel transistor is 0-180 degrees. Also, logic transistors and components can be created by using control gates as component gates. Formation of logic component gates and control gates can be done separately. What needs to be added is that 1T NVM FPGA configuration components can be produced by charge trap technology NVM, anti-memory technology, and can also have a junctionless SW or SE transistor structure. Many other modifications within the scope of the present invention will be recommended in due course by these professionals after careful reading. The scope of the invention is therefore only as defined by the appended claims.

所屬技術領域之通常知識者同時知悉本發明不限於上述已經特定描述之內容。相反地,上述技術人員在閱讀上述內容時,就會發現本發明之範圍包括文中所述不同特徵之組合和次組合以及更改和變化。因此本發明範圍只在所附權利要求範圍內。 Those skilled in the art also know that the present invention is not limited to what has been specifically described above. Rather, those skilled in the art upon reading the foregoing will find that the scope of the present invention includes combinations and sub-combinations as well as modifications and variations of the various features described herein. The scope of the invention is therefore only as defined by the appended claims.

19C10:晶片 19C10: chip

19C12:直通矽晶穿孔 19C12: Through silicon via

19C14:初晶矽 19C14: Primary silicon

19C20:晶片 19C20: chip

19C22:直通矽晶穿孔 19C22: Through silicon via

19C24:初晶矽 19C24: Primary silicon

19C30:晶片 19C30: chip

19C32:直通矽晶穿孔 19C32: Through silicon via

19C34:初晶矽 19C34: Primary silicon

19C40:凸點 19C40: bump

Claims (12)

一種構成半導體裝置的方法,其包含: A method of forming a semiconductor device comprising: 形成第一單晶化半導體層及第二單晶化半導體層; forming a first monocrystalline semiconductor layer and a second monocrystalline semiconductor layer; 其中該第二單晶化半導體層覆蓋該第一單晶化半導體層,以及 wherein the second monocrystalline semiconductor layer covers the first monocrystalline semiconductor layer, and 其中該第一單晶化半導體層包含邏輯電路,以及 wherein the first monocrystalline semiconductor layer includes logic circuits, and 使用構成在該等邏輯電路之上的該第二單晶化半導體層上之輸入輸出(I/O)電路將該邏輯電路連接至外部裝置。 The logic circuits are connected to external devices using input-output (I/O) circuits formed on the second monocrystalline semiconductor layer above the logic circuits. 一種構成半導體裝置的方法,其包含: A method of forming a semiconductor device comprising: 形成第一單晶化半導體層及第二單晶化半導體層; forming a first monocrystalline semiconductor layer and a second monocrystalline semiconductor layer; 其中該第一單晶化半導體層及該第二單晶化半導體層中的一者覆蓋在另一者之上,以及 wherein one of the first monocrystallized semiconductor layer and the second monocrystallized semiconductor layer overlies the other, and 應用用於構成該裝置的一或多個遮罩來構成具有不同尺寸的另一裝置。 Another device having a different size is constructed using one or more of the masks used to construct the device. 一種構成半導體裝置的方法,其包含: A method of forming a semiconductor device comprising: 形成第一單晶化半導體層及第二單晶化半導體層; forming a first monocrystalline semiconductor layer and a second monocrystalline semiconductor layer; 其中該第一單晶化半導體層及該第二單晶化半導體層中的一者覆蓋在另一者之上,以及 wherein one of the first monocrystallized semiconductor layer and the second monocrystallized semiconductor layer overlies the other, and 執行蝕刻步驟以形成切割線。 An etching step is performed to form cut lines. 一種處理積體電路裝置的方法,其包含: A method of processing an integrated circuit device comprising: 處理第一電晶體的第一層, process the first layer of the first transistor, 處理覆蓋該等第一電晶體的第一金屬層,並提供至該等第一電晶體的至少一連接, treating a first metal layer covering the first transistors and providing at least one connection to the first transistors, 沉積覆蓋該第一金屬層之第二金屬層,以及 depositing a second metal layer overlying the first metal layer, and 處理覆蓋該第二金屬層之第二電晶體的第二層,其中 processing a second layer of a second transistor overlying the second metal layer, wherein 其中該第二金屬層被連接,以向至少一該等第二電晶體供電。 Wherein the second metal layer is connected to supply power to at least one of the second transistors. 一種處理積體電路裝置的方法,其包含: A method of processing an integrated circuit device comprising: 處理第一電晶體的第一層, process the first layer of the first transistor, 處理覆蓋該等第一電晶體的第一金屬層,並提供至該等第一電晶體的至少一連接, treating a first metal layer covering the first transistors and providing at least one connection to the first transistors, 沉積覆蓋該第一金屬層之第二金屬層,以及 depositing a second metal layer overlying the first metal layer, and 處理覆蓋該第二金屬層之第二電晶體的第二層,包含 treating a second layer of a second transistor overlying the second metal layer, comprising 在該等第二電晶體與該第二金屬層之間形成至少一連接路徑,其中 At least one connection path is formed between the second transistors and the second metal layer, wherein 該連接路徑包含至少一直通層通孔且其中該直通層通孔包含熱膨脹係數在該第二層之熱膨脹係數的百分之五十以內的材料。 The connection path includes at least one through-layer via and wherein the through-layer via includes a material having a coefficient of thermal expansion within fifty percent of a coefficient of thermal expansion of the second layer. 一種處理積體電路裝置的方法,其包含: A method of processing an integrated circuit device comprising: 處理第一電晶體的第一層, process the first layer of the first transistor, 處理覆蓋該等第一電晶體的第一金屬層,並提供至該等第一電晶體的至少一連接, treating a first metal layer covering the first transistors and providing at least one connection to the first transistors, 沉積覆蓋該第一金屬層之第二金屬層,以及 depositing a second metal layer overlying the first metal layer, and 處理覆蓋該第二金屬層之第二電晶體的第二層,以及 treating a second layer of a second transistor overlying the second metal layer, and 處理覆蓋該等第二電晶體之第三金屬層, processing the third metal layer covering the second transistors, 其中至少一該等第二電晶體係下列中的一者: wherein at least one of the second crystal systems is one of: (i)置換閘極墊晶體; (i) Replacement gate pad crystals; (ii)Finfet電晶體;或 (ii) Finfet transistors; or (iii)雙閘極水平取向電晶體。 (iii) Double gate horizontal orientation transistor. 一種處理3D積體電路的方法,該方法包含: A method of processing 3D integrated circuits, the method comprising: 提供包含第一晶圓的第一層,該第一晶圓包含第一晶體基板、複數個第一電晶體、及第一銅互連層, providing a first layer comprising a first wafer comprising a first crystalline substrate, a plurality of first transistors, and a first copper interconnect layer, 其中該第一銅互連層至少互連該複數個第一電晶體; Wherein the first copper interconnection layer at least interconnects the plurality of first transistors; 處理包含第二晶圓的第二層,該第二晶圓包含第二晶體基板、複數個第二電晶體、及第二銅互連層, processing a second layer comprising a second wafer comprising a second crystalline substrate, a plurality of second transistors, and a second copper interconnect layer, 其中該第二銅互連層至少互連該複數個第二電晶體, Wherein the second copper interconnection layer at least interconnects the plurality of second transistors, 其中該第一銅互連層及該第二銅互連層包含阻擋金屬及氧化物;以及 wherein the first copper interconnect layer and the second copper interconnect layer comprise barrier metals and oxides; and 藉由將該第一層接合至該第一層形成接合的結構, forming a bonded structure by bonding the first layer to the first layer, 其中該接合包含金屬對金屬接合, wherein the bonding comprises a metal-to-metal bonding, 其中該接合包含氧化物對氧化物接合,以及 wherein the bonding comprises an oxide-to-oxide bonding, and 執行微影處理以界定該接合的結構的切割線;以及 performing lithography to define cut lines of the bonded structure; and 蝕刻該等切割線。 The dicing lines are etched. 一種處理3D積體電路的方法,該方法包含: A method of processing 3D integrated circuits, the method comprising: 提供包含第一晶圓的第一層,該第一晶圓包含第一晶體基板、複數個第一電晶體、及第一銅互連層, providing a first layer comprising a first wafer comprising a first crystalline substrate, a plurality of first transistors, and a first copper interconnect layer, 其中該第一銅互連層至少互連該複數個第一電晶體; Wherein the first copper interconnection layer at least interconnects the plurality of first transistors; 處理包含第二晶圓的第二層,該第二晶圓包含第二晶體基板、複數個第二電晶體、及第二銅互連層, processing a second layer comprising a second wafer comprising a second crystalline substrate, a plurality of second transistors, and a second copper interconnect layer, 其中該第二銅互連層至少互連該複數個第二電晶體, Wherein the second copper interconnection layer at least interconnects the plurality of second transistors, 其中該第一銅互連層及該第二銅互連層包含阻擋金屬及氧化物;以及 wherein the first copper interconnect layer and the second copper interconnect layer comprise barrier metals and oxides; and 藉由將該第一層接合至該第一層形成接合的結構, forming a bonded structure by bonding the first layer to the first layer, 其中該接合包含金屬對金屬接合, wherein the bonding comprises a metal-to-metal bonding, 其中該接合包含氧化物對氧化物接合,以及 wherein the bonding comprises an oxide-to-oxide bonding, and 藉由研磨及/或蝕刻處理薄化該第二晶體基板。 The second crystalline substrate is thinned by grinding and/or etching. 一種處理3D積體電路的方法,該方法包含: A method of processing 3D integrated circuits, the method comprising: 提供包含第一晶圓的第一層,該第一晶圓包含第一晶體基板、複數個第一電晶體、及第一銅互連層, providing a first layer comprising a first wafer comprising a first crystalline substrate, a plurality of first transistors, and a first copper interconnect layer, 其中該第一銅互連層至少互連該複數個第一電晶體; Wherein the first copper interconnection layer at least interconnects the plurality of first transistors; 處理包含第二晶圓的第二層,該第二晶圓包含第二晶體基板、複數個第二電晶體、及第二銅互連層, processing a second layer comprising a second wafer comprising a second crystalline substrate, a plurality of second transistors, and a second copper interconnect layer, 其中該第二銅互連層至少互連該複數個第二電晶體, Wherein the second copper interconnection layer at least interconnects the plurality of second transistors, 其中該第一銅互連層及該第二銅互連層包含阻擋金屬及氧化物;以及 wherein the first copper interconnect layer and the second copper interconnect layer comprise barrier metals and oxides; and 藉由將該第一層接合至該第一層形成接合的結構, forming a bonded structure by bonding the first layer to the first layer, 其中該接合包含金屬對金屬接合, wherein the bonding comprises a metal-to-metal bonding, 其中該接合包含氧化物對氧化物接合,以及 wherein the bonding comprises an oxide-to-oxide bonding, and 處理穿過該第一晶體基板的通孔, processing a via through the first crystalline substrate, 其中至外部裝置的連接包含該通孔。 Wherein the connection to the external device comprises the through hole. 一種3D半導體裝置,該裝置包含: A 3D semiconductor device, the device comprising: 第一層,其包含第一單晶層,該第一層包含第一電晶體, a first layer comprising a first monocrystalline layer comprising a first transistor, 其中該等第一電晶體各包含單晶通道; wherein each of the first transistors comprises a single crystal channel; 第一金屬層,其至少互連該等第一電晶體;以及 a first metal layer interconnecting at least the first transistors; and 第二層,其包含第二單晶層,該第二層包含第二電晶體, a second layer comprising a second monocrystalline layer comprising a second transistor, 其中該第二層覆蓋該第一層, wherein the second layer covers the first layer, 其中該第二層係接合至該第一層, wherein the second layer is bonded to the first layer, 其中該接合包含氧化物對氧化物接合, wherein the bonding comprises an oxide-to-oxide bonding, 其中該第二層包含記憶體單元陣列,以及 wherein the second layer contains an array of memory cells, and 其中每一該等記憶體單元包含至少一凹槽通道陣列電晶體(RCAT)。 Each of the memory cells includes at least one recessed channel array transistor (RCAT). 一種3D半導體裝置,該裝置包含: A 3D semiconductor device, the device comprising: 第一層,其包含第一單晶層,該第一層包含第一電晶體, a first layer comprising a first monocrystalline layer comprising a first transistor, 其中該等第一電晶體各包含單晶通道; wherein each of the first transistors comprises a single crystal channel; 第一金屬層,其至少互連該等第一電晶體; a first metal layer interconnecting at least the first transistors; 第二層,其包含第二單晶層,該第二層包含第二電晶體, a second layer comprising a second monocrystalline layer comprising a second transistor, 其中該第二層覆蓋該第一層, wherein the second layer covers the first layer, 其中該第二層係接合至該第一層, wherein the second layer is bonded to the first layer, 其中該接合包含氧化物對氧化物接合, wherein the bonding comprises an oxide-to-oxide bonding, 其中該第二層包含記憶體單元陣列;以及 wherein the second layer comprises an array of memory cells; and 刷新控制電路,其適用於刷新該記憶體單元陣列。 A refresh control circuit is suitable for refreshing the memory cell array. 一種3D半導體裝置,該裝置包含: A 3D semiconductor device, the device comprising: 第一層,其包含第一單晶層,該第一層包含第一電晶體, a first layer comprising a first monocrystalline layer comprising a first transistor, 其中該等第一電晶體各包含單晶通道; wherein each of the first transistors comprises a single crystal channel; 第一金屬層,其至少互連該等第一電晶體;以及 a first metal layer interconnecting at least the first transistors; and 第二層,其包含第二單晶層,該第二層包含第二電晶體, a second layer comprising a second monocrystalline layer comprising a second transistor, 其中該第二層覆蓋該第一層, wherein the second layer covers the first layer, 其中該第二層係接合至該第一層, wherein the second layer is bonded to the first layer, 其中該接合包含氧化物對氧化物接合,以及 wherein the bonding comprises an oxide-to-oxide bonding, and 其中該第二層包含至少四個獨立的記憶體單元陣列。 Wherein the second layer includes at least four independent memory cell arrays.
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TWI827396B (en) 2023-12-21

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