TWI785593B - 半導體裝置及其形成方法 - Google Patents

半導體裝置及其形成方法 Download PDF

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TWI785593B
TWI785593B TW110116140A TW110116140A TWI785593B TW I785593 B TWI785593 B TW I785593B TW 110116140 A TW110116140 A TW 110116140A TW 110116140 A TW110116140 A TW 110116140A TW I785593 B TWI785593 B TW I785593B
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Taiwan
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forming
opening
layer
etching process
dielectric layer
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TW110116140A
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TW202143385A (zh
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黃玉蓮
王冠人
張雲閔
傅勁逢
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台灣積體電路製造股份有限公司
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Abstract

一種半導體裝置的形成方法，包括：形成閘極結構於鰭片之上，其中鰭片突出於基板之上；形成源極/汲極區域於鰭片之上且位於閘極結構的相對兩側上；相繼形成第一介電層及第二介電層於源極/汲極區域之上；進行第一蝕刻製程，以形成開口於第一介電層及第二介電層中，其中開口暴露出位於下方的導電部件；在進行第一蝕刻製程之後，進行第二蝕刻製程，以擴大靠近基板的開口的下部分；以及在第二蝕刻製程之後，形成接觸插塞於開口中。

Description

半導體裝置及其形成方法
本發明實施例係有關於一種半導體結構，且特別係有關於一種具有接觸插塞的半導體裝置及其形成方法。
由於各種電子組件(例如，電晶體、二極體、電阻、電容等)的積體密度的持續提高，半導體工業經歷了快速的增長。在大部分的情況下，積體密度的提高來自最小部件尺寸的持續降低，這允許將更多的組件集積到特定區域中。
鰭式場效電晶體(fin field-effect transistor, FinFET)裝置變得普遍使用於積體電路中。鰭式場效電晶體裝置具有三維結構，此三維結構包括從基板突出的半導體鰭片。閘極結構被配置為控制鰭式場效電晶體裝置的導電通道內的電荷載子流動，且閘極結構圍繞半導體鰭片。例如，在三閘極鰭式場效電晶體(tri-gate FinFET)裝置中，閘極結構圍繞半導體鰭片的三個側面，而在半導體鰭片的三個側面上形成導電通道。
本揭露之一實施例揭示一種半導體裝置的形成方法，包括：形成閘極結構於鰭片之上，其中鰭片突出於基板之上；形成源極/汲極區域於鰭片之上且位於閘極結構的相對兩側上；相繼形成第一介電層及第二介電層於源極/汲極區域之上；進行第一蝕刻製程，以形成開口於第一介電層及第二介電層中，其中開口暴露出位於下方的導電部件；在進行第蝕刻製程之後，進行第二蝕刻製程，以擴大靠近基板的開口的下部分；以及在第二蝕刻製程之後，形成接觸插塞於開口中。
本揭露之一實施例揭示一種半導體裝置的形成方法，包括：形成閘極結構於鰭片之上，其中鰭片突出於基板之上；形成源極/汲極區域於鰭片之上且相鄰於閘極結構；形成第一介電層於源極/汲極區域之上且圍繞閘極結構；形成第二介電層於第一介電層之上；使用第一蝕刻製程形成開口延伸進入第一介電層及第二介電層中，其中開口暴露出位於下方的導電部件；使用第二蝕刻製程，增加位於第一介電層中的開口的體積；沿著開口的側壁形成犧牲層；沿著犧牲層形成間隔物層；使用導電材料填充開口；以及在填充開口之後，移除犧牲層，其中在移除犧牲層之後，形成氣隙於第一及第二介電層與導電材料之間。
本揭露之一實施例揭示一種半導體裝置，包括：鰭片，突出於基板之上；閘極結構，位於鰭片之上；源極/汲極區域，位於閘極結構的相對兩側上；介電層，位於源極/汲極區域之上；接觸插塞，延伸穿過介電層並且電性連接到位於下方的導電部件，其中接觸插塞的上部分具有線性的側壁剖面輪廓，且開口的下部分具有彎曲的側壁剖面輪廓。
以下的揭露內容提供許多不同的實施例或範例以實施本案的不同部件(feature)。以下的揭露內容敘述各個構件及其排列方式的特定範例，以簡化說明。當然，這些特定的範例並非用以限定。例如，元件的尺寸不限於所揭露的範圍或數值，而是可以取決於製程條件及/或所期望的裝置特性。此外，若是本說明書敘述了一第一部件形成於一第二部件之上或上方，即表示其可能包含上述第一部件與上述第二部件被形成為直接接觸的實施例，亦可能包含了有額外的部件形成於上述第一部件與上述第二部件之間，而使上述第一部件與第二部件可能未直接接觸的實施例。
再者，空間相關用詞，例如“在…下方”、“下方”、“較低的”、“上方”、“較高的”及類似的用詞，係為了便於描述圖式中一個元件或部件與另一個(些)元件或部件之間的關係。除了在圖式中繪示的方位外，這些空間相關用詞意欲包含部件的裝置之不同方位。裝置能夠以其他方式定向(旋轉90度或其他方向)，並且本文中所使用的空間相關用詞可以同樣地被相應地解釋。在下文中，除非另有特別說明，否則在不同的圖式中的相同標號用以代表相同或相似的元件，其中這些元件是使用相同或相似的材料且藉由相同或相似的方法而形成。
在形成鰭式場效電晶體裝置的上下文中，特別是在形成用於鰭式場效電晶體裝置的具有凹角(re-entrant)剖面輪廓的接觸插塞的上下文中，而討論本揭露的實施例。雖然使用鰭式場效電晶體裝置作為示例而討論所揭露的實施例，但是所揭露的方法也可以應用於其他類型的裝置中，例如，平面裝置。
在一些實施例中，在鰭式場效電晶體裝置的源極/汲極區域之上形成第一介電層及第二介電層。使用第一蝕刻製程(例如，非等向性蝕刻製程)在第一介電層及第二介電層中形成開口，以暴露出位於其下方的導電部件，此導電部件可以是源極/汲極區域、連接至鰭式場效電晶體裝置的閘極結構的導通孔、或是連接到源極/汲極區域的導通孔。接著，進行第二蝕刻製程(例如，等向性蝕刻製程)以擴大此開口的下部分，使得開口的下部分具有彎曲的側壁剖面輪廓，而開口的上部分具有線性的側壁剖面輪廓。接著，藉由以下步驟在開口中形成接觸插塞(也可以稱為導通孔)：沿著開口的側壁形成犧牲層；形成間隔物層於犧牲層之上；用導電材料填充開口；以及在填充開口之後移除犧牲層。在移除犧牲層之後，在間隔物層與第一介電層與第二介電層之間形成氣隙。可以在第二介電層之上形成另一介電層，藉此將氣隙密封。開口的經過增大的下部分導致所形成的接觸插塞的下部分增大，因而減小接觸插塞的電阻。此外，藉由減小接觸插塞周圍的介電材料的平均介電常數(k值)，氣隙能夠有利於減小電容。
第1圖以立體示意圖繪示出鰭式場效電晶體30的示範例。鰭式場效電晶體30包括基板50以及突出於基板50之上的鰭片64。隔離區62形成於鰭片64的相對兩側上，且鰭片64突出於隔離區62之上。閘極介電質66沿著鰭片64的側壁且在鰭片64的頂表面上延伸，且閘極電極68位於閘極介電質66之上。源極/汲極區域80位於鰭片64中並且位於閘極介電質66及閘極電極68的相對兩側。第1圖進一步繪示出在後續的圖式中所使用的參考剖面。剖面B-B沿著鰭式場效電晶體30的閘極電極68的縱軸延伸。剖面A-A垂直於剖面B-B，並且沿著鰭片64的縱軸延伸，並且位在，例如，源極/汲極區域80之間的電流流動的方向上。剖面C-C平行於剖面B-B，並且延伸穿過源極/汲極區域80。為了清楚起見，後續的圖式將參考這些參考剖面。
第2圖至第7圖、第8A圖、第9圖至第13圖及第14A圖至第14C圖是依據一實施例之製造鰭式場效電晶體裝置100的中間階段的剖面示意圖。除了具有多個鰭片及多個閘極結構之外，鰭式場效電晶體裝置100相似於第1圖中的鰭式場效電晶體30。第2圖至第5圖繪示出沿著剖面B-B的鰭式場效電晶體裝置100的剖面示意圖。第6圖至第7圖、第8A圖、第9圖至第13圖及第14A圖繪示出鰭式場效電晶體裝置100沿著剖面A-A的剖面示意圖。第8B圖及第8C圖繪示出沿著剖面C-C的鰭式場效電晶體裝置100的實施例的剖面示意圖。第14B圖及第14C圖分別繪示出鰭式場效電晶體裝置100沿著剖面C-C及B-B的剖面示意圖。在本文的整個討論中，除非另有特別說明，否則具有相同編號但不同字母的圖(例如，第14A圖及第14B圖)是指相同裝置在相同製造階段的不同剖面示意圖。
第2圖繪示出基板50的剖面示意圖。基板50可以是半導體基板，例如，塊體(bulk)半導體、絕緣體上覆半導體(semiconductor-on-insulator, SOI)基板或其他類似物，其可以被摻雜(例如，用p型或n型摻質)或是未經摻雜。基板50可以是晶圓，例如，矽晶圓。通常，絕緣體上覆半導體基板包括形成在絕緣體層上的一層半導體材料。絕緣體層可以是，例如，埋藏氧化物(buried oxide, BOX)層、氧化矽層或其他類似物。絕緣體層設置在通常為矽或玻璃基板的基板上。也可使用其他基板，例如，多層(multi-layered)或漸變(gradient)基板。在一些實施例中，基板50的半導體材料可包括矽；鍺；化合物半導體，包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦(indium antimonide)；合金半導體，包括矽鍺(SiGe)、磷砷化鎵(GaAsP)、砷化銦鋁(AlInAs)、砷化鎵鋁(AlGaAs)、砷化銦鎵(GaInAs)、磷化銦鎵(GaInP)及/或磷砷化銦鎵(GaInAsP)；或上述之組合。
請參照第3圖，使用，例如，光微影及蝕刻技術對第2圖所繪示的基板50進行圖案化。舉例而言，形成罩幕層於基板50之上，罩幕層可以是，例如，墊氧化物層52及位於其上的墊氮化物層56。墊氧化物層52可以是一層薄膜，其包括使用，例如，熱氧化法形成的氧化矽。墊氧化物層52可作為半導體基板50與位於其上的墊氮化物層56之間的黏著層。在一些實施例中，墊氮化物層56由氮化矽、氮氧化矽、碳氮化矽、其他類似物或上述之組合所形成。例如，其可以使用低壓化學氣相沉積(low-pressure chemical vapor deposition, LPCVD)或電漿輔助化學氣相沉積(plasma enhanced chemical vapor deposition, PECVD)而形成。
可以使用光微影技術將罩幕層圖案化。通常，光微影技術使用光阻材料(未繪示)，光阻材料被沉積、照射(曝光)並顯影，以移除光阻材料的一部分。剩餘的光阻材料保護位於其下方的材料(例如，在本實施例中為罩幕層)免於受到後續處理步驟(例如，蝕刻)的影響。在本實施例中，光阻材料用於圖案化墊氧化物層52及墊氮化物層56，以形成經過圖案化的罩幕58，如第3圖所繪示。
經過圖案化的罩幕58在後續被用於將基板50的暴露部分圖案化，以形成溝槽61，而在相鄰的溝槽61之間定義出半導體鰭片64 (例如，64A及64B)，如第3圖所繪示。藉由使用，例如，反應性離子蝕刻(reactive ion etch , RIE)、中性束蝕刻(neutral beam etch, NBE)、其他類似方法或上述之組合，在基板50中蝕刻溝槽，以形成半導體鰭片64。蝕刻製程可以是非等向性的。在一些實施例中，溝槽61可以是彼此平行的，並且相對於彼此緊密間隔的條帶(從上方觀察)。在一些實施例中，溝槽61可以是連續的，並且圍繞半導體鰭片64。半導體鰭片64在下文中也可以被稱為鰭片64。
可藉由任何合適的方法將鰭片64圖案化。舉例而言，可使用一個或多個光微影(photolithography)製程將鰭片64圖案化，包括雙重圖案化(double-patterning)製程或多重圖案化(multi-patterning)製程。一般而言，雙重圖案化或多重圖案化製程結合了光微影製程及自對準製程(self-aligned process)，以創造具有較小節距的圖案，舉例而言，此圖案所具有的節距比使用單一直接光微影製程所能夠得到的節距更小。舉例而言，在一實施例中，形成犧牲層於基板之上並使用光微影製程將其圖案化。使用自對準製程形成間隔物於經過圖案化的犧牲層旁。之後，移除犧牲層，並且可接著使用剩餘的間隔物或心軸(mandrel)將鰭片圖案化。
第4圖繪示出在相鄰的半導體鰭片64之間形成絕緣材料以形成隔離區域62的情況。絕緣材料可以是氧化物(例如，氧化矽)、氮化物、其他類似物或上述之組合，並且可藉由下列方法形成，包括高密度電漿化學氣相沉積(high density plasma chemical vapor deposition, HDP-CVD)、流動式化學氣相沉積(flowable chemical vapor deposition, FCVD) (例如，在遠距電漿系統中進行的基於CVD的材料沉積，以及後固化(post curing)而使其轉化為另一種材料，例如，氧化物)、其他類似方法或上述之組合。可使用其他絕緣材料及/或其他形成製程。在所示的實施例中，絕緣材料是藉由流動式化學氣相沉積製程所形成的氧化矽。當形成絕緣材料後，即可進行退火製程。可使用平坦化製程，例如，化學機械研磨(chemical mechanical polish, CMP)移除任何多餘的絕緣材料，並且使得隔離區域62的頂表面與半導體鰭片64的頂表面形成為共平面的(未繪示)。經過圖案化的罩幕58 (見第3圖)也可以藉由平坦化製程移除。
在一些實施例中，在隔離區域62與基板50/半導體鰭片64之間的界面處，隔離區域62包括襯層，例如，襯層氧化物(未繪示)。在一些實施例中，形成襯層氧化物以減少基板50與隔離區域62之間的界面處的晶體缺陷(crystalline defect)。相似地，襯層氧化物也可以用於減少半導體鰭片64與隔離區域62之間的界面處的晶體缺陷。襯層氧化物(例如，氧化矽)可以是藉由對基板50的表面層進行熱氧化而形成的熱氧化物，但是也可以使用其他合適的方法而形成襯層氧化物。
接著，將隔離區域62凹陷化，以形成淺溝槽隔離(STI)區域62。將淺溝槽隔離隔離區域62凹陷化，使得半導體鰭片64的上部分從相鄰的淺溝槽隔離區域62之間突出。淺溝槽隔離區域62的頂表面可具有平坦表面(如圖式所繪示)、凸表面、凹表面(例如，碟形凹陷)或上述之組合。淺溝槽隔離區域62的頂表面可藉由合適的蝕刻而形成為平坦的、凸的及/或凹的。可使用可接受的蝕刻製程將淺溝槽隔離區域62凹陷化，例如，對淺溝槽隔離區域62的材料具有選擇性的蝕刻製程。舉例而言，可進行乾式蝕刻或是，例如，使用稀氫氟酸的濕式蝕刻，將淺溝槽隔離區域62凹陷化。
第2圖至第4圖繪示出形成鰭片64的實施例，但是可以藉由各種不同的製程而形成鰭片。例如，基板50的頂部可以由合適的材料取代，例如，適合於所欲形成的半導體裝置的預期類型(例如，N型或P型)的磊晶材料。之後，對在頂部上具有磊晶材料的基板50進行圖案化，以形成包括此磊晶材料的半導體鰭片64。
作為另一示例，可以形成介電層於基板的頂表面之上；可以蝕刻穿過此介電層的溝槽；可以磊晶成長同質磊晶(homoepitaxial)結構於此溝槽中。可以將此介電層凹陷化，使得此同質磊晶結構從介電層突出，以形成鰭片。
在又一個示例中，可以形成介電層於基板的頂表面之上；可以蝕刻穿過此介電層的溝槽；可以使用與基板不同的材料磊晶成長異質磊晶(heteroepitaxial)結構於此溝槽中。可以將此介電層凹陷化，使得此異質磊晶結構從介電層突出，以形成鰭片。
在成長磊晶材料或磊晶結構(例如，異質磊晶結構或同質磊晶結構)的實施例中，可以在成長期間原位(in situ)摻雜成長的材料或結構，如此可以省略之前及之後的佈植，雖然也可以一起使用原位摻雜和佈植摻雜。更進一步而言，在N型金屬氧化物半導體(NMOS)區域中磊晶成長與在P型金屬氧化物半導體(PMOS)區域中的材料不同的材料，如此可能是有優點的。在各個實施例中，鰭片64可以包括矽鍺(Six Ge1-x ，其中x可以在0至1的範圍內)、碳化矽、純的或實質上純的鍺、III-V族化合物半導體、II-VI化合物半導體或其他類似物。舉例而言，用以形成III-V化合物半導體的可用材料包括但不限於砷化銦(InAs)、砷化鋁(AlAs)、砷化鎵(GaAs)、磷化銦(InP)、氮化鎵(GaN)、砷化鎵銦(InGaAs)、砷化鋁銦(InAlAs)、銻化鎵(GaSb)、銻化鋁(AlSb)、磷化鋁(AlP)、磷化鎵(GaP)或其他類似物。
第5圖繪示出形成虛置閘極結構75在半導體鰭片64之上。在一些實施例中，虛置閘極結構75包括閘極介電質66及閘極電極68。可以形成罩幕70於虛置閘極結構75之上。為了形成虛置閘極結構75，形成介電層於半導體鰭片64之上。介電層可以是，例如，氧化矽、氮化矽、上述之多層結構、或其他類似物，並且可以沉積或熱成長。
形成閘極層於介電層之上，並且形成罩幕層於閘極層之上。可以沉積閘極層於介電層之上，然後，例如，藉由化學機械研磨將其平坦化。可以沉積罩幕層於閘極層之上。閘極層可以由，例如，多晶矽所形成，但是也可以使用其他材料。罩幕層可以由，例如，氮化矽或其他類似物所形成。
在形成上述膜層(例如，介電層、閘極層及罩幕層)之後，可以使用可接受的光微影及蝕刻技術對罩幕層進行圖案化，以形成罩幕70。然後可以藉由可接受的蝕刻技術將罩幕70的圖案轉移至閘極層及介電層，以分別形成閘極電極68及閘極介電層66。閘極電極68及閘極介電層66覆蓋半導體鰭片64的相應的通道區域。閘極電極68還可以具有實質上垂直於相應的半導體鰭片64的長度方向的長度方向。
在第5圖的示例中，閘極介電質66被繪示為形成於鰭片64之上(例如，位於鰭片64的頂表面及側壁之上)及淺溝槽隔離區域62之上。在其他實施例中，可以藉由，例如，鰭片64的材料的熱氧化，而形成閘極介電質66，並且因此可以在鰭片64之上而不會在淺溝槽隔離區域62之上形成閘極介電質66。這些實施例及其他變化例完全包括在本揭露的範圍內。
第6圖至第7圖、第8A圖、第9圖至第13圖及第14A圖繪示出沿著剖面A-A (沿著鰭片64的縱軸)對鰭式場效電晶體裝置100進行進一步處理的剖面示意圖。注意，在第6圖至第7圖、第8A圖及第9圖中，形成三個虛置閘極結構75 (例如，75A、75B及75C)於鰭片64之上。本技術領域中具有通常知識者將理解，可以形成多於或少於三個閘極結構於鰭片64之上，這些實施例及其他變化例完全包括在本揭露的範圍內。
如第6圖所繪示，形成輕摻雜汲極(LDD)區域65於鰭片64之中。可以藉由電漿摻雜製程而形成輕摻雜汲極區域65。電漿摻雜製程可以包括形成罩幕(例如，光阻)並將其圖案化，以覆蓋鰭式場效電晶體的部分區域，這些區域將被保護而不會受到電漿摻雜製程的影響。電漿摻雜製程可以在鰭片64中佈植N型雜質或P型雜質，以形成輕摻雜汲極區域65。舉例而言，可以將P型雜質(例如，硼)佈植到鰭片64中，以形成用於P型設備的輕摻雜汲極區域65。作為另一個示例，可以將N型雜質(例如，磷)佈植到鰭片64中，以形成用於N型裝置的輕摻雜汲極區域65。在一些實施例中，輕摻雜汲極區域65鄰接鰭式場效電晶體裝置100的通道區域。輕摻雜汲極區域65的部分可以在閘極電極68下方延伸並進入鰭式場效電晶體裝置100的通道區域。第6圖繪示出輕摻雜汲極區域65的非限制性示例。輕摻雜汲極區域65的其他配置、形狀及形成方法也是可能的，並且完全包括在本揭露的範圍內。舉例而言，可以在形成閘極間隔物87之後，形成輕摻雜汲極區域65。在一些實施例中，省略了輕摻雜汲極區域65。為了簡單起見，在後續的圖式中並未繪示輕摻雜汲極區域65，應當理解的是，輕摻雜汲極區域65可以形成於鰭片64之中。
仍請參照第6圖，在形成輕摻雜汲極區域65之後，形成閘極間隔物87圍繞虛置閘極結構75。閘極間隔物87可以包括第一閘極間隔物72及第二閘極間隔物86。第一閘極間隔物72可以是閘極密封間隔物(gate seal spacer)，並且形成在閘極電極68的相對兩側側壁上與閘極介電質66的相對兩側側壁上。第二閘極間隔物86形成在第一閘極間隔物72上。第一閘極間隔物72可以由氮化物所形成，例如，氮化矽、氮氧化矽、碳氮化矽、其他類似物或上述之組合，並且可以使用，例如，熱氧化、化學氣相沉積或其他合適的沉積製程，而形成第一閘極間隔物72。第二閘極間隔物86可以由氮化矽、碳氮化矽或上述之組合所形成，且可使用合適的沉積方法而形成。
在一實施例中，首先，順應性地沉積第一閘極間隔物層於鰭式場效電晶體裝置100之上，然後順應性地沉積第二閘極間隔物層於所沉積的第一閘極間隔物層之上，藉此形成閘極間隔物87。接著，進行非等向性蝕刻製程，例如，乾式蝕刻製程，以移除設置在鰭式場效電晶體裝置100的上表面(例如，罩幕70的上表面)上的第二閘極間隔物層的第一部分，並且沿著閘極結構的側壁設置第二閘極間隔物層的第二部分。在非等向性蝕刻製程之後，剩餘的第二閘極間隔物層的第二部分形成第二閘極間隔物86。非等向性蝕刻製程也移除第一閘極間隔物層的一部分，此部分設置在第二閘極間隔物86的側壁的外側，並且第一閘極間隔物層的其餘部分形成第一閘極間隔物72。
如第6圖所繪示的閘極間隔物87的形狀及形成方法僅是非限制性的示例，並且其他形狀及形成方法也是可能的。這些實施例及其他變化例完全包括在本揭露的範圍內。
接著，如第7圖所繪示，形成凹口88於鰭片64中鄰近虛置閘極結構75的區域中，例如，在相鄰的虛置閘極結構75之間及/或鄰近虛置閘極結構75的區域中。在一些實施例中，藉由，例如，使用虛置閘極結構75及閘極間隔物87作為蝕刻罩幕的非等向性蝕刻製程，而形成閘極，但是也可以使用任何其他合適的蝕刻製程。
接著，如第8A圖所繪示，形成源極/汲極區域80於凹口88之中。可使用合適的方法磊晶成長一種材料於凹口88之中，藉以形成源極/汲極區域80，合適的方法包括，例如，金屬有機化學氣相沉積(metal-organic chemical vapor deposition, MOCVD)、分子束磊晶(molecular beam epitaxy, MBE)、液相磊晶(liquid phase epitaxy, LPE)、氣相磊晶(vapor phase epitaxy, VPE)、選擇性磊晶成長(selective epitaxial growth, SEG)、其他類似之方法或上述之組合。
如第8A圖所繪示，磊晶源極/汲極區域80可以具有從鰭片64的各個表面凸起的表面(例如，凸起到高於鰭片64的未經凹陷化的上表面64U)，並且可以具有刻面(facet)。相鄰鰭片64的源極/汲極區域80可以合併，以形成連續的磊晶源極/汲極區域80 (見第8B圖)。在一些實施例中，相鄰鰭片64的源極/汲極區域80並未合併在一起，而是保持分開的源極/汲極區域80 (見第8C圖)。在一些實施例中，所得到的鰭式場效電晶體是N型鰭式場效電晶體，並且源極/汲極區域80包括碳化矽(silicon carbide, SiC)、磷矽(silicon phosphorous, SiP)、磷摻雜矽碳(phosphorous-doped silicon carbon, SiCP)等。在一些實施例中，所得到的鰭式場效電晶體是P型鰭式場效電晶體，並且源極/汲極區域80包括矽鍺，以及P型雜質，例如，硼或銦。
可使用摻質對磊晶源極/汲極區域80進行佈植，以形成源極/汲極區域80，隨後進行退火製程。佈植製程可以包括形成罩幕(例如，光阻)並將其圖案化，以覆蓋鰭式場效電晶體裝置100的部分區域，這些區域將被保護而不會受到佈植製程的影響。源極/汲極區域80可以具有在大約1E19cm-3 至大約1E21cm-3 的範圍內的雜質(例如，摻質)濃度。可以將P型雜質(例如，硼或銦)佈植到P型電晶體的源極/汲極區域80中。可以將N型雜質(例如，磷或砷)佈植到N型電晶體的源極/汲極區域80中。在一些實施例中，可以在成長期間對磊晶源極/汲極區域進行原位摻雜。
接著，如第9圖所繪示，形成接觸蝕刻停止層(contact etch stop layer, CESL) 89於第8A圖所繪示的結構之上。接觸蝕刻停止層89在後續的蝕刻製程中用以作為蝕刻停止層，並且可以包括合適的材料，例如，氧化矽、氮化矽、氮氧化矽、上述之組合或其他類似物，並且可以藉由合適的形成方法而形成，例如，化學氣相沉積、物理氣相沉積、上述之組合或其他類似方法。
接著，形成第一層間介電質(ILD) 90於接觸蝕刻停止層89之上及虛置閘極結構75 (例如，75A、75B及75C)之上。在一些實施例中，第一層間介電質90由介電材料形成，例如，磷矽酸鹽玻璃(phosphosilicate glass, PSG)、硼矽酸鹽玻璃(borosilicate glass, BSG)、摻雜硼的磷矽酸鹽玻璃(boron-doped phospho-silicate glass, BPSG)、未摻雜的矽酸鹽玻璃(undoped silicate glass, USG)或其他類似物，並且可藉由任何合適的方法而沉積第一層間介電質90，例如，化學氣相沉積、電漿輔助化學氣相沉積或流動式化學氣相沉積。可以進行平坦化製程，例如，化學機械研磨製程，以移除罩幕70並移除設置於閘極電極68之上的接觸蝕刻停止層89的部分。在平坦化製程之後，第一層間介電質90的頂表面與閘極電極68的頂表面齊平。
接著，在第10圖中，進行實施例的閘極後製製程(gate-last process，有時稱為替換閘極製程(replacement gate process))，使用主動閘極(也可以稱為替換閘極或金屬閘極)與主動閘極介電材料分別替換閘極電極68與閘極介電質66。因此，在閘極後製製程中，閘極電極68與閘極介電質66可以分別稱為虛置閘極電極與虛置閘極介電質。在一些實施例中，主動閘極是金屬閘極。
請參照第10圖，使用替換閘極結構97A、97B與97C分別替換虛置閘極結構75A、75B與75C (見第9圖)。依據一些實施例，為了形成替換閘極結構97(例如97A，97B或97C)，在蝕刻步驟中移除閘極電極68及位於閘極電極68正下方的閘極介電質66，因而形成凹口(未繪示)於閘極間隔物87之間。每一個凹口暴露出各自的鰭片64的通道區域。在虛置閘極的移除期間，當蝕刻閘極電極68時，可使用閘極介電質66作為蝕刻停止層。可以在移除閘極電極68之後移除閘極介電質66。
接著，在用於替換閘極結構97的凹口中形成閘極介電層94、阻障層96、功函數層98及閘極電極99。順應性地沉積閘極介電層94於凹口中，例如，在鰭片64的頂表面及側壁上，以及在閘極間隔物87的側壁上，以及在第一層間介電質90的頂表面上(未繪示)。依據一些實施例，閘極介電層94包括氧化矽、氮化矽或上述之多層結構。在其他實施例中，閘極介電層94包括高介電常數(high-k)介電材料，並且在這些實施例中，閘極介電層94可以具有大於約7.0的介電常數值(k值)，並且可包括下列金屬的金屬氧化物或矽酸鹽，這些金屬包括：鉿、鋁、鋯、鑭、鎂、鋇、鈦、鉛及上述之組合。閘極介電層94的形成方法可包括分子束沉積(Molecular-Beam Deposition, MBD)、原子層沉積、電漿輔助化學氣相沉積及其他類似方法。
接著，順應性地形成阻障層96於閘極介電層94之上。阻障層96可以包括導電材料，例如，氮化鈦，但是也可以使用其他材料，例如，氮化鉭、鈦、鉭或其他類似物。可以使用化學氣相沉積製程而形成阻障層96，例如，電漿輔助化學氣相沉積。但是，也可以替代地使用其他替代方法，例如，濺鍍(sputtering)、金屬有機化學氣相沉積或原子層沉積。
在一些實施例中，接著，可以在阻障層96上方的凹口中並且在形成閘極電極99之前，形成功函數層98，功函數層98可包括，例如，P型功函數層或N型功函數層。可以包括在用於P型裝置的閘極結構中的例示性P型功函數金屬包括氮化鈦(TiN)、氮化鉭(TaN)、釕(Ru)、鉬(Mo)、鋁(Al)、氮化鎢(WN)、矽化鋯(ZrSi2 )、矽化鉬(MoSi2 )、矽化鉭(TaSi2 )、矽化鎳(NiSi2 )、氮化鎢(WN)、其他合適的P型功函數材料或上述之組合。可用於N型裝置的閘極結構中的例示性N型功函數金屬包括：鈦(Ti)、銀(Ag)、鋁化鉭(TaAl)、碳化鋁鉭(TaAlC)、氮化鋁鈦(TiAlN)、碳化鉭(TaC)、碳氮化鉭(TaCN)、氮化矽鉭(TaSiN)、錳(Mn)、鋯(Zr)、其他合適的N型功函數材料或上述之組合。功函數值與功函數層的材料組成有關聯性，因此，可選擇功函數層的材料以調整其功函數值，進而在後續形成的裝置中實現目標的閾值電壓(threshold voltage) Vt。可藉由化學氣相沉積、物理氣相沉積及/或其他合適的製程，以沉積功函數層。
接著，在功函數層98之上順應性地形成晶種層(未繪示)。晶種層可以包括銅、鈦、鉭、氮化鈦、氮化鉭、其他類似物或上述之組合，並且可藉由原子層沉積、濺鍍、物理氣相沉積或其他類似方法而沉積晶種層。在一些實施例中，晶種層是金屬層，其可以是單層或複合層，其中此複合層包括由不同材料形成的多個子層。例如，晶種層可包括鈦層及位於鈦層上方的銅層。
接著，沉積閘極電極99於晶種層之上，並且填充凹口的其餘部分。閘極電極99可由含金屬材料所形成，例如，銅、鋁、鎢、其他類似物，上述之組合或上述之多層結構，並且可藉由，例如，電鍍(electroplating)、無電電鍍(electroless plating)或其他合適的方法而形成。在形成閘極電極99之後，可進行平坦化製程(例如，化學機械研磨)，以移除閘極介電層94、阻障層96、功函數層98、晶種層及閘極電極99的多餘部分，這些多餘部分是指位於第一層間介電質90的頂表面上方的部分。因此，所得到的閘極介電層94、阻障層96、功函數層98、晶種層及閘極電極99的剩餘部分形成最終的鰭式場效電晶體裝置100的替換閘極結構97。
接下來請參照第11圖，形成第二層間介電質92於第一層間介電質90之上。形成穿過第二層間介電質92及第一層間介電質90的開口93，以暴露源極/汲極區域80。
在一實施例中，第二層間介電質92是藉由流動式化學氣相沉積方法形成的可流動膜。在一些實施例中，第二層間介電質92由介電材料形成，例如，磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃、未摻雜的矽酸鹽玻璃或其他類似物，並且第二層間介電質92可藉由的任何合適的方法而沉積，例如，化學氣相沉積及電漿輔助化學氣相沉積。在一些實施例中，第二層間介電質92及第一層間介電質90由相同的材料所形成。在一些實施例中，第二層間介電質92及第一層間介電質90由不同的材料所形成。
在一些實施例中，使用光微影及蝕刻形成第11圖中的開口93。蝕刻製程蝕刻穿過接觸蝕刻停止層89以暴露源極/汲極區域80。在一些實施例中，使用非等向性蝕刻製程，例如，非等向性電漿蝕刻製程，而形成第11圖中的開口93。在一實施例中，非等向性電漿蝕刻製程使用的氣體源包括全氟甲烷(CF4 )、六氟丁二烯(C4 F6 )、八氟環丁烷(C4 F8 )或上述之組合。在非等向性蝕刻製程之後，第11圖中的開口93的側壁具有線性的剖面輪廓，例如，開口93的每一個側壁沿著各自的直線(例如，傾斜的直線)延伸。
接著，在第12圖中，進行等向性蝕刻製程，例如等向性電漿蝕刻製程，以擴大開口93的下部分。在一實施例中，等向性電漿蝕刻製程使用的氣體源包括氯氣、溴化氫或上述之組合。作為示例，可以調整(例如，減小)電漿蝕刻設備的偏壓功率(或偏壓)，以實現等向性電漿蝕刻。在一些實施例中，第一層間介電質90及第二層間介電質92由相同或相似的材料所形成(例如，第一層間介電質90是藉由電漿輔助化學氣相沉積而形成的氧化矽，第二層間介電質92是藉由流動式化學氣相沉積而形成的氧化矽)，並且相對於源極/汲極區域80，等向性蝕刻製程的氣體源對第一及第二層間介電質90/92具有高蝕刻選擇性(例如，較高的蝕刻速率)。在一些實施例中，在等向性蝕刻製程的期間，當位於開口93的下部分中的蝕刻氣體保留並移除(例如，蝕刻)第一層間介電質90的部分時，位於開口93的上部分中的蝕刻氣體容易從開口93中擴散出來，使得開口93的下部分(例如，第一層間介電質90內部的部分)藉由等向性蝕刻製程而被擴大，而開口93的上部分(例如，位於第二層間介電質92中的部分)實質上保持不變。因此，在等向性蝕刻製程之後，開口93的上部分具有線性的側壁剖面輪廓，而開口93的下部分具有彎曲的側壁剖面輪廓，例如，每一個開口93的下部分的側壁是彎曲的。雖然以等向性電漿蝕刻製程為例，但是也可以使用其他合適的等向性蝕刻製程，例如，濕式蝕刻製程。
等向性蝕刻製程增加了開口93的下部分的體積。如第12圖所繪示，每一個開口93在第二層間介電質92的上表面具有第一寬度A，且在開口93的底部有第二寬度B。，其中B大於A。在一些實施例中，第二寬度B比第一寬度A大的值為大約1 nm至大約5 nm之間(例如，5 nm≥ B-A ≥1 nm)，例如，約1 nm。線R1與線R2之間的角度α在大約87度與大約91度之間，例如，約87度，其中線R1沿著開口93的上部分的線性側壁(例如，傾斜的直線側壁)延伸，線R2平行於基板50的主要上表面。
接著，在第13圖中，沿著第一層間介電質90的側壁及沿著第二層間介電質92的側壁，形成(例如，順應性地形成)犧牲層121於開口93之中。接著，在犧牲層121之上並且沿著犧牲層121形成(例如，順應性地形成)間隔物層123。接著，在源極/汲極區域80上方的開口93的底部處形成矽化物區域95，並且形成導電材料125以填充開口93。下文將詳細討論。
在一實施例中，犧牲層121是半導體層(例如，矽層)，並且藉由合適的沉積製程而形成，例如，原子層沉積、化學氣相沉積、電漿輔助化學氣相沉積或其他類似方法。在一些實施例中，所沉積的犧牲層121沿著開口93的側壁及底部並且沿著第二層間介電質92的上表面而順應性地延伸。接著，進行蝕刻製程(例如，非等向性蝕刻製程)以從開口93的底部移除犧牲層121的一部分，而暴露出位於其下方的源極/汲極區域80。蝕刻製程也可以從第二層間介電質92的上表面移除犧牲層121的一部分。在蝕刻製程之後，犧牲層121沿著開口93的側壁而設置。在後續的處理中，移除犧牲層121，以在第一層間介電質/第二層間介電質90/92與間隔物層123之間形成氣隙。雖然使用矽作為犧牲層121的一個示例，但是也可以使用任何其他合適的材料(例如，可以藉由後續的蝕刻製程而選擇性地移除的材料)作為犧牲層121。
接著，在開口93之中並且在犧牲層121上方形成(例如，順應性地形成)間隔物層123。在一實施例中，間隔物層123是介電層，例如，氮化矽層，並且藉由合適的沉積製程形成，例如，原子層沉積、化學氣相沉積、電漿輔助化學氣相沉積或其他類似方法。使用與犧牲層121的材料不同的材料形成間隔物層123，以提供蝕刻選擇性，使得在後續的移除犧牲層121的蝕刻製程中，移除犧牲層121而實質上不會侵蝕間隔物層123。
在一些實施例中，所沉積的間隔物層123沿著開口93的側壁及底部並且沿著第二層間介電質92的上表面而順應性地延伸。接著，進行另一蝕刻製程(例如，非等向性蝕刻製程)，以從開口93的底部移除間隔物層123的一部分，而暴露出位於其下方的源極/汲極區域80。此另一蝕刻製程也可以從第二層間介電質92的上表面移除間隔物層123的一部分。在此另一蝕刻製程之後，間隔物層123沿著開口93的側壁而設置於犧牲層121上。
接著，可以在源極/汲極區域80上方的開口93中視需要而形成非必要的矽化物區域95。在一些實施例中，矽化物區域95可藉由以下步驟而形成，首先沉積能夠與半導體材料(例如矽，鍺)反應的金屬，以在磊晶源極/汲極區域80的暴露部分上形成矽化物或鍺化物區域，這些金屬可包括，例如，鎳、鈷、鈦、鉭、鉑、鎢、其他貴金屬(noble metal)、其他難熔金屬(refractory metal)、稀土金屬或其合金，然後，進行熱退火製程，以形成矽化物區域95。然後，例如，藉由蝕刻製程移除所沉積的金屬的未反應部分。雖然區域95被稱為矽化物區域，但是區域95也可以是鍺化物區域或矽鍺化物區域(例如，包括矽化物及鍺化物的區域)。
接著，形成(例如，順應性地形成)阻障層(未繪示)於開口93之中。此阻障層可以包括導電材料，例如，氮化鈦，但是也可以替代的使用其他材料，例如，氮化鉭、鈦、鉭或其他類似物。可以使用原子層沉積、化學氣相沉積、電漿輔助化學氣相沉積、金屬有機化學氣相沉積或其他類似方法形成阻障層。
接著，形成導電材料125於開口93中，以填充開口93。導電材料125可由含金屬材料所形成，例如，銅、鋁、鎢、其他類似物，上述之組合或上述之多層結構，並且可藉由，例如，電鍍(electroplating)、無電電鍍(electroless plating)或其他合適的方法而形成。可進行平坦化製程(例如，化學機械研磨)，以移除設置在第二層間介電質92的上表面之上的膜層(例如，121、123、阻障層及125)的多餘部分。應注意的是，由於開口93的經過擴大的下部分，導電材料125也具有經過擴大的下部分，如此能夠有利於減小所形成的接觸插塞的電阻。舉例而言，位於每一個開口93中的導電材料125具有上部分及下部分，其中，上部分具有線性的側壁剖面輪廓，而下部分具有彎曲的側壁剖面輪廓，並且下部分比上部分更寬。
接著，在第14A圖中，進行選擇性蝕刻製程，以移除犧牲層121。在一實施例中，犧牲層121是矽層，並且在選擇性蝕刻製程中所使用的化學物質包括氫氣(H2 )及氟化氮(NF3 )。在另一實施例中，使用包含氫氧化銨(NH4 OH)的化學物質，以選擇性地移除犧牲層121。應注意的是，移除犧牲層121的選擇性蝕刻製程與形成開口93的蝕刻製程不同。在選擇性蝕刻製程之後，形成氣隙124於第一層間介電質/第二層間介電質90/92與間隔物層123之間。氣隙124有利於減小所形成的裝置的電容，這是因為氣隙減小了所形成的接觸插塞周圍的介電材料(例如，第一層間介電質90及第二層間介電質92)的平均介電常數。因此，每一個開口93中的氣隙124、間隔物層123、阻障層及導電材料125形成具有凹角剖面輪廓的接觸插塞104。第14A圖中的接觸插塞104電性連接至源極/汲極區域80，因此也被稱為源極/汲極接觸插塞。
接著，藉由佈植製程將雜質(例如，Ge)佈植到第二層間介電質92的頂部分之中，以密封(至少部分地密封)氣隙124，之後，形成介電層111於第二層間介電質92之上。在一些實施例中，佈植製程將合適的雜質(例如，鍺)佈植到第二層間介電質92的頂部分之中。佈植製程使第二層間介電質92的頂部分增大(例如，膨脹)。因此，密封(例如，完全地密封或部分地密封)氣隙124。如第14A圖所繪示，可包括雜質(例如，鍺)於其中的部分92S (由第二層間介電質92的頂部分膨脹所造成)將氣隙124密封。形成導電部件113 (例如，導線)於介電層111中。介電層111及/或位於介電層111中的導電部件113可以進一步將氣隙124密封。如本技術領域中具有通常知識者所理解，在第14A圖的製程之後可能會進行其他製程，以完成鰭式場效電晶體裝置100的製造，在此不再詳述細節。
第14B圖繪示出第14A圖的鰭式場效電晶體裝置100，但是沿著剖面C-C。第14C圖繪示出第14A圖的鰭式場效電晶體裝置100，但是沿著剖面B-B。
第15圖是依據另一實施例之鰭式場效電晶體裝置100A的剖面示意圖。鰭式場效電晶體裝置100A相似於鰭式場效電晶體裝置100，但是具有形成於介電層111/112之中的接觸插塞104 (也稱為導通孔對接觸插塞(via-to-contact plug))，介電層111/112被設置在第二層間介電質92之上。換言之，首先將源極/汲極區域80電性連接至接觸插塞102 (其可以具有或可以不具有凹角剖面輪廓)，然後，將導通孔對接觸插塞104形成於接觸插塞102之上並與接觸插塞102電性耦合。第15圖的示例中的接觸插塞102不具有凹角剖面輪廓。在其他實施例中，第15圖中的接觸插塞102可以被具有凹角剖面輪廓的接觸插塞(例如，接觸插塞104)代替。
在第15圖中，接觸插塞102 (也可以稱為接觸件)形成在第一層間介電質90及第二層間介電質92中。每一個接觸件102包括阻障層101、晶種層103及導電材料105，並且電性耦合到位於其下方的導電部件(例如，源極/汲極區域80)。阻障層101、晶種層103及導電材料105的材料與形成方法可以分別與上文針對替換閘極結構97的阻障層96、晶種層及閘極電極99所討論的材料與形成方法相同或相似，因此不再重複細節。可以使用與第11圖至第14A圖所繪示相同或相似的處理步驟，而形成接觸插塞104。如第15圖所繪示，可以將雜質(例如，鍺)佈植到介電層112的頂部分之中，以使其增大，使得介電層112的部分112S密封(例如，完全地密封或部分地密封)各自的氣隙124。介電層115及/或介電層115之中的導電部件113可進一步密封氣隙124。
第16圖是依據另一實施例之鰭式場效電晶體裝置100B的剖面示意圖。鰭式場效電晶體裝置100B相似於鰭式場效電晶體裝置100，但是具有形成於絕緣層111/112及第一層間介電質/第二層間介電質90/92之中的接觸插塞104 (也稱為導通孔對接觸插塞)，此接觸插塞104具有凹角剖面輪廓，並且電性耦合到替換閘極結構97。
針對所揭露的實施例的變化例是可能的，並且完全包括在本揭露的範圍內。例如，通孔對接觸插塞104 (具有凹角剖面輪廓)與位於其下方的接觸插塞102 (請參照，例如，第15圖)的組合可以用來代替為了電性連接而單獨使用作為接觸件的接觸插塞102，例如，第16圖中的接觸插塞102。
第17圖是依據本揭露之一些實施例之形成半導體裝置的方法1000的流程圖。應可理解的是，第17圖所繪示的實施例方法僅僅是許多可能的實施例方法的例子。本技術領域中具有通常知識者將可理解到許多變化、替換及修飾。舉例而言，可以增加、移除、置換、重新排列與重複如第17圖所繪示的各個步驟。
請參照第17圖，在步驟1010，在突出於基板上方的鰭片之上形成閘極結構。在步驟1020，在閘極結構的相對兩側上的鰭片之上形成源極/汲極區域。在步驟1030，在源極/汲極區域上方相繼形成第一介電層及第二介電層。在步驟1040，進行第一蝕刻製程，以在第一介電層及第二介電層中形成開口，其中此開口暴露出位於其下方的導電部件。在步驟1050，在進行第一蝕刻製程之後，進行第二蝕刻製程，以擴大靠近基板的開口的下部分。在步驟1060，在第二蝕刻製程之後，在開口中形成接觸插塞。
本文所描述的實施例可實現許多優點。舉例而言，本文所述的清潔方法能夠使所形成的接觸插塞具有經過擴大的下部分，因而減小所形成的接觸插塞的電阻。此外，接觸插塞的氣隙有助於防止或減少金屬擴散，並且可以額外地減小所形成的裝置的平均介電常數值。
依據一些實施例，提供一種半導體裝置的形成方法，包括：形成閘極結構於鰭片之上，其中上述鰭片突出於基板之上；形成源極/汲極區域於上述鰭片之上且位於上述閘極結構的相對兩側上；相繼形成第一介電層及第二介電層於上述源極/汲極區域之上；進行第一蝕刻製程，以形成開口於上述第一介電層及上述第二介電層中，其中上述開口暴露出位於下方的導電部件；在進行上述第一蝕刻製程之後，進行第二蝕刻製程，以擴大靠近上述基板的上述開口的下部分；以及在上述第二蝕刻製程之後，形成接觸插塞於上述開口中。在一實施例中，其中上述第一蝕刻製程為非等向性蝕刻製程。在一實施例中，其中上述第二蝕刻製程為一等向性蝕刻製程。在一實施例中，其中在上述第一蝕刻製程之後且在上述第二蝕刻製程之前，上述開口具有線性的側壁剖面輪廓，其中在上述第二蝕刻製程之後，上述開口的上述下部分具有彎曲的側壁剖面輪廓，並且遠離上述基板的上述開口的上部分具有線性的剖面輪廓。在一實施例中，其中在上述第二蝕刻製程之後，上述開口的上述下部分具有一第一寬度，且遠離上述基板的上述開口的上述上部分具有第二寬度，其中上述第一寬度大於上述第二寬度。在一實施例中，其中上述第一蝕刻製程為使用氣體源而進行的非等向性電漿蝕刻製程，且上述氣體源包括全氟甲烷(CF4 )、六氟丁二烯(C4 F6 )或八氟環丁烷(C4 F8 )。在一實施例中，其中上述第二蝕刻製程為使用氣體源而進行的等向性電漿蝕刻製程，且上述氣體源包括氯氣或溴化氫。在一實施例中，其中形成上述接觸插塞包括：形成犧牲層內襯於上述開口的側壁上；形成間隔物層於上述犧牲層上；使用導電材料填充上述開口；以及在填充上述開口之後，移除上述犧牲層，其中在移除上述犧牲層之後，形成氣隙於上述第一及第二介電層與上述間隔物層之間。在一實施例中，其中上述犧牲層是沿著上述開口的側壁而形成，且上述開口的底部並不具有上述犧牲層。在一實施例中，上述半導體裝置的形成方法更包括：在移除上述犧牲層之後，形成將上述氣隙密封的第三介電層。在一實施例中，其中上述間隔物層是使用氮化物所形成，且上述犧牲層是使用半導體材料所形成。在一實施例中，其中上述氮化物是氮化矽，且上述半導體材料是矽。
依據一些實施例，提供一種半導體裝置的形成方法，包括：形成閘極結構於鰭片之上，其中上述鰭片突出於基板之上；形成源極/汲極區域於上述鰭片之上且相鄰於上述閘極結構；形成第一介電層於上述源極/汲極區域之上且圍繞上述閘極結構；形成第二介電層於上述第一介電層之上；使用第一蝕刻製程形成開口延伸進入上述第一介電層及上述第二介電層中，其中上述開口暴露出位於下方的導電部件；使用第二蝕刻製程，增加位於上述第一介電層中的上述開口的體積；沿著上述開口的側壁形成犧牲層；沿著上述犧牲層形成間隔物層；使用導電材料填充上述開口；以及在填充上述開口之後，移除上述犧牲層，其中在移除上述犧牲層之後，形成氣隙於上述第一及第二介電層與上述導電材料之間。在一實施例中，上述半導體裝置的形成方法更包括：形成第三介電層於上述第二介電層之上，藉此將上述氣隙密封。在一實施例中，其中上述第一蝕刻製程為非等向性蝕刻製程，且上述第二蝕刻製程為等向性蝕刻製程。在一實施例中，其中上述第二蝕刻製程使用蝕刻劑，其中上述蝕刻劑對上述第一介電層具有選擇性。
依據一些實施例，提供一種半導體裝置，包括：鰭片，突出於基板之上；閘極結構，位於上述鰭片之上；源極/汲極區域，位於上述閘極結構的相對兩側上；介電層，位於上述源極/汲極區域之上；接觸插塞，延伸穿過上述介電層並且電性連接到位於下方的導電部件，其中上述接觸插塞的上部分具有線性的側壁剖面輪廓，且上述開口的下部分具有彎曲的側壁剖面輪廓。在一實施例中，其中靠近上述基板的上述開口的上述下部分的寬度大於遠離上述基板的上述開口的上述上部分的寬度。在一實施例中，其中上述接觸插塞包括：導電材料；間隔物層，圍繞上述導電材料；以及氣隙，位於上述間隔物層與上述介電層之間。在一實施例中，其中上述位於下方的上述導電部件是上述源極/汲極區域、上述閘極結構或導通孔的其中一者，其中上述導通孔連接到上述閘極結構或連接上述源極/汲極區域的其中一者。
前述內文概述了許多實施例的部件，使本技術領域中具有通常知識者可以從各個方面更佳地了解本發明實施例。本技術領域中具有通常知識者應可理解，且可輕易地以本發明實施例為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本發明的發明精神與範圍。在不背離本發明的發明精神與範圍之前提下，可對本發明進行各種改變、置換或修改。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
30:鰭式場效電晶體 50:基板 52:墊氧化物層 56:墊氮化物層 58:經過圖案化的罩幕 61:溝槽 62:隔離區域 64:半導體鰭片(鰭片) 64A:半導體鰭片(鰭片) 64B:半導體鰭片(鰭片) 64U:上表面 65:輕摻雜汲極區域 66:閘極介電質 68:閘極電極 70:罩幕 72:第一閘極間隔物 75:虛置閘極結構 75A:虛置閘極結構 75B:虛置閘極結構 75C:虛置閘極結構 80:源極/汲極區域(磊晶源極/汲極區域) 86:第二閘極間隔物 87:閘極間隔物 88:凹口 89:接觸蝕刻停止層 90:第一層間介電質 92:第二層間介電質 92S:部分 93:開口 94:閘極介電層 95:矽化物區域 96:阻障層 97:替換閘極結構 97A:替換閘極結構 97B:替換閘極結構 97C:替換閘極結構 98:功函數層 99:閘極電極 100:鰭式場效電晶體裝置 100A:鰭式場效電晶體裝置 100B:鰭式場效電晶體裝置 101:阻障層 102:接觸插塞(接觸件) 103:晶種層 104:接觸插塞(導通孔對接觸插塞) 105:導電材料 111:介電層 112:介電層 112S:部分 113:導電部件 121:犧牲層 123:間隔物層 124:氣隙 125:導電材料 A:第一寬度 B:第二寬度 R1:線 R2:線 α:角度 1000:方法 1010:步驟 1020:步驟 1030:步驟 1040:步驟 1050:步驟 1060:步驟
依據以下的詳細說明並配合所附圖式做完整揭露。應注意的是，依據本產業的一般作業，圖式並未必按照比率繪製。事實上，可能任意的放大或縮小元件的尺寸，以做清楚的說明。 第1圖是依據一些實施例之鰭式場效電晶體裝置的立體示意圖。 第2圖至第7圖、第8A圖、第9圖至第13圖及第14A圖至第14C圖是依據一實施例之製造鰭式場效電晶體裝置的中間階段的剖面示意圖。 第8B圖及第8C圖是繪示第8A圖的兩個實施例的剖面示意圖。 第15圖是依據另一實施例之鰭式場效電晶體裝置的剖面示意圖。 第16圖是依據又一實施例之鰭式場效電晶體裝置的剖面示意圖。 第17圖是依據本揭露之一些實施例之形成半導體裝置的方法的流程圖。
50:基板
64:半導體鰭片(鰭片)
80:源極/汲極區域(磊晶源極/汲極區域)
89:接觸蝕刻停止層
90:第一層間介電質
92:第二層間介電質
92S:部分
95:矽化物區域
97A:替換閘極結構
97B:替換閘極結構
97C:替換閘極結構
100:鰭式場效電晶體裝置
104:接觸插塞(導通孔對接觸插塞)
111:介電層
113:導電部件
123:間隔物層
124:氣隙
125:導電材料

Claims (14)

  1. 一種半導體裝置的形成方法，包括：形成一閘極結構於一鰭片之上，其中該鰭片突出於一基板之上；形成源極/汲極區域於該鰭片之上且位於該閘極結構的相對兩側上；相繼形成一第一介電層及一第二介電層於該等源極/汲極區域之上；進行一第一蝕刻製程，以形成一開口於該第一介電層及該第二介電層中，其中該開口暴露出位於下方的一導電部件；在進行該第一蝕刻製程之後，進行一第二蝕刻製程，以擴大靠近該基板的該開口的一下部分；以及在該第二蝕刻製程之後，形成一接觸插塞於該開口中，其中形成該接觸插塞包括：形成一犧牲層內襯於該開口的側壁上；使用一導電材料填充該開口；在填充該開口之後，移除該犧牲層，其中在移除該犧牲層之後，形成一氣隙於該第一及第二介電層與該導電材料之間；以及在移除該犧牲層之後，對該第二介電層進行一佈植製程，其中該佈植製程將該第二介電層的一上部分擴展到密封該氣隙。
  2. 如請求項1所述之半導體裝置的形成方法，其中該第一蝕刻製程為一非等向性蝕刻製程，且其中該第二蝕刻製程為一等向性蝕刻製程。
  3. 如請求項1或2所述之半導體裝置的形成方法，其中在該第一蝕刻製程之後且在該第二蝕刻製程之前，該開口具有一線性的側壁剖面輪廓，其中在該第二蝕刻製程之後，該開口的該下部分具有一彎曲的側壁剖面輪廓，並 且遠離該基板的該開口的一上部分具有一線性的剖面輪廓。
  4. 如請求項3所述之半導體裝置的形成方法，其中在該第二蝕刻製程之後，該開口的該下部分具有一第一寬度，且遠離該基板的該開口的該上部分具有一第二寬度，其中該第一寬度大於該第二寬度。
  5. 如請求項1或2所述之半導體裝置的形成方法，其中該第一蝕刻製程為使用一氣體源而進行的一非等向性電漿蝕刻製程，且該氣體源包括全氟甲烷(CF4)、六氟丁二烯(C4F6)或八氟環丁烷(C4F8)，且其中該第二蝕刻製程為使用一氣體源而進行的一等向性電漿蝕刻製程，且該氣體源包括氯氣或溴化氫。
  6. 如請求項1或2所述之半導體裝置的形成方法，其中形成該接觸插塞包括：形成一間隔物層於該犧牲層上，其中在移除該犧牲層之後，形成一氣隙於該第一及第二介電層與該間隔物層之間，且其中該犧牲層是沿著該開口的側壁而形成，且該開口的一底部並不具有該犧牲層。
  7. 如請求項6所述之半導體裝置的形成方法，更包括：在移除該犧牲層之後，形成將該氣隙密封的一第三介電層。
  8. 如請求項6所述之半導體裝置的形成方法，其中該間隔物層是使用一氮化物所形成，且該犧牲層是使用一半導體材料所形成。
  9. 如請求項8所述之半導體裝置的形成方法，其中該氮化物是氮化矽，且該半導體材料是矽。
  10. 一種半導體裝置的形成方法，包括：形成一閘極結構於一鰭片之上，其中該鰭片突出於一基板之上； 形成一源極/汲極區域於該鰭片之上且相鄰於該閘極結構；形成一第一介電層於該源極/汲極區域之上且圍繞該閘極結構；形成一第二介電層於該第一介電層之上；使用一第一蝕刻製程形成一開口延伸進入該第一介電層及該第二介電層中，其中該開口暴露出位於下方的一導電部件；使用一第二蝕刻製程，增加位於該第一介電層中的該開口的一體積；沿著該開口的側壁形成一犧牲層；沿著該犧牲層形成一間隔物層；使用一導電材料填充該開口；在填充該開口之後，移除該犧牲層，其中在移除該犧牲層之後，形成一氣隙於該第一及第二介電層與該導電材料之間；以及藉由一佈植製程將該第二介電層的一上部分擴展到至少部分地密封該氣隙。
  11. 如請求項10所述之半導體裝置的形成方法，其中該第二蝕刻製程使用一蝕刻劑，其中該蝕刻劑對該第一介電層具有選擇性。
  12. 一種半導體裝置，包括：一鰭片，突出於一基板之上；一閘極結構，位於該鰭片之上；源極/汲極區域，位於該閘極結構的相對兩側上；介電層，位於該等源極/汲極區域之上；一接觸插塞，延伸穿過該等介電層並且電性連接到位於下方的一導電部件，其中該接觸插塞的一上部分具有一線性的側壁剖面輪廓，且該開口的一下部分具有一彎曲的側壁剖面輪廓， 其中該接觸插塞包括：一導電材料；一間隔物層，圍繞該導電材料；以及一氣隙，位於該間隔物層與該等介電層之間，其中該等介電層的一上部分擴展到至少部分地密封該氣隙。
  13. 如請求項12所述之半導體裝置，其中靠近該基板的該開口的該下部分的一寬度大於遠離該基板的該開口的該上部分的一寬度。
  14. 如請求項12或13所述之半導體裝置，其中該位於下方的該導電部件是該等源極/汲極區域、該閘極結構或一導通孔的其中一者，其中該導通孔連接到該閘極結構或連接到該等源極/汲極區域的其中一者。
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