TWI775435B - Method for wafer-level testing and semiconductor device - Google Patents

Abstract

The present disclosure provides a method and a system for testing semiconductor device. The method includes providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first period; applying a stress signal to the input terminal of the DUT during a second period subsequent to the first period; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and comparing the output signal with the stress signal. The stress signal includes a plurality of sequences, each having a ramp-up stage and a ramp-down stage. The stress signal has a second voltage level and a third voltage level.

Description

Method and semiconductor device for wafer level testing

Embodiments of the present invention relate to a wafer-level testing method and apparatus.

In semiconductor manufacturing, a wafer typically undergoes many processes to form an integrated circuit. Various wafer-level tests are performed to determine the performance and reliability of integrated circuits and wafer acceptance under various conditions. Wafer-level reliability testing is used to detect the likelihood of early failure associated with defects generated during integrated circuit fabrication. Generally, reliability testing involves stressing integrated circuits and applying voltages in excess of normal operating conditions using various techniques, such as on/off power cycling. However, current testing techniques can provide ineffective reliability assessments due to unexpected damage or degradation of integrated circuits during testing. Therefore, it is desirable to develop a more efficient stressing method for testing.

One embodiment of the invention relates to a method comprising: providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the the input terminal of the DUT; applying a stress signal to the input terminal of the DUT during a second cycle after the first cycle, the stress signal comprising a plurality of sequences, each of the sequences having a ramp phase and a ramp-down phase, in which the The force signal has a second voltage level and a third voltage level; an output signal is obtained in response to the stress signal at the output terminal of the DUT; and the output signal is compared with the stress signal.

One embodiment of the invention relates to a method comprising: providing a device under test (DUT) having an input terminal and an output terminal; applying a stress signal to the input terminal of the DUT; The stress signal at the output terminal obtains an output signal, the output signal includes a plurality of sequences, each of the sequences has a ramp-up phase and a ramp-down phase, wherein the output signal has a first voltage level and a second voltage level; comparing the output signal with the stress signal; and determining whether the DUT has an abnormal structure based on a result of the comparison between the output signal and the stress signal.

One embodiment of the present invention relates to a semiconductor device comprising: a first input terminal configured to receive a stress signal; an output terminal configured to generate an output signal in response to the stress signal; a substrate; a gate disposed on the substrate; and a contact disposed on the substrate and beside the gate, wherein the contact is electrically connected to the first input terminal or the output terminal, and Wherein a distance between the gate and the contact is less than 3 nanometers (nm).

11A: Semiconductor Structure

11B: Semiconductor Structure

100: System

101: Probe

102: Signal Generator

104: Coupler

106: Mods

110: Wafer

110a: Substrate

110b: Gate

110c: gate dielectric

110d: Spacer

110e: Contact

110f: Epitaxy

111a: Substrate

111b: gate

111c: Gate dielectric

111d: Spacer

111e: Contact

111f: Epitaxy

111s: Surface

112: Integrated Circuits (ICs)

200: The first voltage level

210: First cycle

212: Second cycle

220: Stress Signal

221A: Sequence

221B: Sequence

222: Second voltage level/test voltage

224: the third voltage level

310: Test Cycle

311: Test voltage

312: Stress Signal

313: Ground

320: first cycle

321: Single step signal

322: Second cycle

323: Ground

324: single sequence signal

325: normal operating voltage

327: Test voltage

328: Stress Signal

412: Second cycle

420: Stress Signal

421A: Sequence

421B: Sequence

421C: Sequence

421D: Sequence

422: The second voltage level

424: The third voltage level

512: Second cycle

520: Stress Signal

521A: Sequence

521B: Sequence

522: The second voltage level

600: The first voltage level

610: first cycle

612: Second cycle

620: Stress Signal

621A: Sequence

621B: Sequence

621C: Sequence

700: Method

712: Operation

714: Operation

716: Operation

718: Operation

800: Method

812: Operation

814: Operation

816: Operation

818: Operation

900: Inverter circuit

901: PMOS

903: NMOS

1002: input signal

1004: output signal

1010: first cycle

1012: Second cycle

1020: first voltage level

1022: The second voltage level

1024: The third voltage level

1026: Voltage level

2231: Ramp phase

2231’: Ramp up phase

2232: Ramp down phase

2232’: ramp down stage

4231: Ramp up phase

4232: Ramp down phase

D1: Distance

D2: Distance

Aspects of the present disclosure are best understood from the following description when read in conjunction with the accompanying drawings. It should be noted that in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

1 is a diagrammatic view of a system for testing semiconductor devices in accordance with some embodiments of the present disclosure.

FIG. 2A is a multiplexer for testing a wafer in accordance with some embodiments of the present disclosure. One of the step power signals is shown.

2B illustrates one of the multi-step ramp-up and ramp-down phases of a sequence in accordance with some embodiments of the present disclosure.

3A is a diagram of a single step power signal for testing a wafer in a conventional dynamic voltage stress testing method.

3B is a diagram of a single step power signal for testing a wafer in a conventional high voltage stress testing method.

4 is a diagram of a multi-step power signal for testing a wafer in accordance with some embodiments of the present disclosure.

5 is a diagram of a multi-step power signal for testing a wafer, according to some embodiments of the present disclosure.

6 is a diagram of a multi-step power signal for testing a wafer, according to some embodiments of the present disclosure.

7 is a flowchart illustrating a method according to some embodiments of the present disclosure.

8 is a flowchart illustrating a method according to some embodiments of the present disclosure.

9 is a diagram of one of an inverter circuit according to some embodiments of the present disclosure.

FIG. 10 is a timing diagram showing the waveforms of input and output signals according to the embodiment of FIG. 9 .

11A illustrates a semiconductor structure according to some embodiments of the present disclosure.

FIG. 11B illustrates a semiconductor structure according to some embodiments of the present disclosure.

The following disclosure provides many different embodiments or examples of different means for implementing the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first member over or on a second member may include embodiments in which the first member and the second member are formed in direct contact, and may also include embodiments in which additional members may be formed on the first member Between the member and the second member, the first member and the second member may not be in direct contact with each other. Additionally, the present disclosure may repeat reference numerals and/or letters in various instances. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or configurations discussed.

Embodiments of the present disclosure are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are illustrative only and do not limit the scope of the present disclosure.

Also, for the convenience of description, such as "under", "under", "under", "above", "over", "under" The spatially relative terms "", "left", "right" and the like may be used herein to describe the relationship of one element or component to another element or component(s) depicted in the figures. In addition to the orientation depicted in the figures, spatially relative terms are also intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and thus the spatially relative descriptors used herein may likewise be interpreted. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present.

In some conventional voltage stress tests, it may be desirable to improve the sieving rate (ie, failure count divided by total device count) for wafer-level testing. Discovered that rapidly changing the switching state (ie, "0" state or "1" state) of semiconductor devices in integrated circuits (ICs) improves wafer-level measurement Test the sieving rate. According to some embodiments of the present disclosure, the signal generator can provide a cyclic alternating voltage stress (CAVS), the stress signal has a plurality of sequences, which make the voltage level a high voltage level and a low voltage level in a time period The voltage levels fluctuate alternately. The switching state (ie, "0" state or "1" state) of a semiconductor device in an integrated circuit (IC) can be more easily changed by CAVS during multiple ramp-up and ramp-down phases. The reason is that the field effects are locally alternating. Thus, the stress signal can cause some semiconductor devices to go into a short-circuit mode as a fault count. Due to the multiple ramp-up and ramp-down phases, the switching rate of semiconductor devices in the IC can be increased. Therefore, the screening rate for wafer-level testing can be improved.

1 is a diagrammatic view of a system 100 for testing a semiconductor device in accordance with some embodiments of the present disclosure. 2A is a diagram of a multi-step power signal for testing a wafer, according to some embodiments of the present disclosure.

Referring to FIGS. 1 and 2A , the system 100 is configured to test an integrated circuit (IC) formed on a wafer 110 . Wafer 110 may be referred to as a device under test (DUT). Wafer 110 may include an elemental semiconductor, such as silicon, germanium, or diamond. Wafer 110 may include one or more ICs 112 (or chips) formed thereon. Dicing lanes can be provided between adjacent ICs 112 so that the ICs can be separated in subsequent processing.

In some embodiments, the system 100 may be automatic test equipment (ATE). System 100 may include hardware and software components that provide a suitable operating and functional environment for testing. In some embodiments, the system 100 includes a signal generator 102 , a coupler 104 and a module 106 .

The signal generator 102 is configured to generate a cyclic alternating voltage stress (CAVS). CAVS includes a signal at a first voltage level 200 during a first period 210 and a stress signal 220 during a second period 212 following the first period 210 . It should be understood that other electrical signals such as data signals and pulse signals may be provided to the DUT, but for clarity and not shown for simplicity.

In some embodiments, during the first period 210, a single-step signal is generated that rises from ground (ie, 0V) to a first voltage level 200 . The first voltage level 200 may be the nominal voltage of the IC 112 or a high voltage (eg, 5% to 10% of the high nominal voltage). For a power cycling test, IC 112 may be powered with nominal voltage. In some embodiments, the duration of the rise from ground to the first voltage level 200 may be on the order of milliseconds based on the voltage slew rate.

In some embodiments, during the second period 212, the stress signal 220 is generated. The stress signal 220 is used to overstress the DUT and cause process-related failures. The stress signal 220 may include a plurality of sequences 221A and 221B. Each of sequences 221A and 221B includes a ramp-up phase 2231 and a ramp-down phase 2232 . Each of sequences 221A and 221B includes a voltage change between a second voltage level 222 and a third voltage level 224 . Either the ramp-up phase 2231 or the ramp-down phase 2232 is not limited in scope. In some embodiments, the ramp-up phase 2231 or the ramp-down phase 2232 ranges between about 0.1 V/millisecond (ms) and about 0.3 V/ms. The ramp-up phase 2231 increases the voltage from the first voltage level 200 to the second voltage level 222 , and the ramp-down phase 2232 reduces the voltage from the second voltage level 222 to the third voltage level 224 .

It should be understood that the stress signal may vary depending on test requirements and/or historical data. For example, the stress signal may depend on defects per million (DPPM). In some industries, the defect tolerance may be lower, for example, in the automotive or mobile phone industries, and the sequence of stress signals may be increased. The second voltage level 222 is higher than the first voltage level 200 . The value of the second voltage level 222 is not limited. In some embodiments, the second voltage level 222 may be about 1.3 times higher, about 1.58 times higher, about 2.0 times higher, or about 3.0 times higher than the first voltage level 200 . The second voltage level 222 acts as a test voltage (or stress voltage). The value of the third voltage level 224 is not limited. The third voltage level 224 is lower than the second voltage level 222 . In some embodiments, the third voltage level 224 may be equal to or lower at the first voltage level 200 . In some embodiments, a voltage difference between the second voltage level 222 and the third voltage level 224 is greater than a voltage difference between the first voltage level 200 and the second voltage level 222 . In some embodiments, the third voltage level 224 may be approximately 0.7 times the first voltage level 200 . In some embodiments, the third voltage level 224 may be approximately 0.9 times the second voltage level 222 . A duration of the third voltage level 224 may include a wait time and a check alarm time. The duration of the third voltage level 224 is not limited and can be considered as a cooling time to suppress the self-heating effect caused by voltage stress. In some embodiments, the duration of the third voltage level 224 may be about 6 to 10 ms, within or in excess of hundreds of ms.

2B illustrates one of the multi-step ramp-up and ramp-down phases of a sequence in accordance with some embodiments of the present disclosure. Referring to Figure 2B, in some embodiments, the ramp-up phase 2231' and the ramp-down phase 2232' comprise multiple steps. With multiple steps, current overshoot is avoided. It should be noted that the number of steps in the ramp-up phase 2231' and the ramp-down phase 2232' is not limited.

Referring back to FIGS. 1 and 2A , the coupler 104 is configured to couple the signal generator 102 to the IC 112 . In some embodiments, the coupler 104 may be coupled to the IC through a plurality of probes 101 . Probe 101 may be part of a probe head or probe package (not shown). Probes 101 may be electrically coupled to test pads and/or pads disposed on IC 112 . Test pads and/or pads provide electrical connection to an interconnect structure (eg, wires) of the IC. For example, some of the probes may be coupled to pads associated with one of the supply terminals (eg, Vdd) and ground terminals (eg, Vss) of the IC 112 . Other probes may be coupled to pads associated with input/output (I/O) terminals (eg, data signals) of IC 112 . Thus, system 100 is operable to apply electrical signals (eg, stress signals) to IC 112 and obtain response signals from IC 112 during wafer level testing.

Module 106 is configured to determine whether IC 112 meets a test criterion after stress signal 220 is applied to IC 112 . Responses may be evaluated against test criteria by module 106 signal to determine whether a particular IC 112 is defective.

3A is a diagram of a single step power signal for testing a wafer in a conventional dynamic voltage stress testing method. 3B is a diagram of a single step power signal for testing a wafer in a conventional high voltage stress testing method.

Referring to FIG. 3A , a stress signal 312 for dynamic voltage stress (DVS) testing is applied in a single test cycle 310 . The stress signal 312 consists of a single sequence signal including a ramp-up phase from ground 313 to a test voltage 311 and a ramp-down phase from the test voltage 311 to ground 313 . The DVS test uses a single sequence of signals to power up the DUT to the mode setting state, and tests the DUT at the test voltage 311 in the same cycle. The test voltage 311 exceeds the normal operating voltage during the test period 310 . In DVS testing, it was found that if the voltage level of test voltage 311 is increased, the sieving rate (ie, failure count divided by total number of devices) for wafer level testing can be increased. However, the test voltage 311 is used for both mode setting and defect testing, and the amount of voltage variation of the test voltage 311 is limited due to the requirements for the mode setting. In other words, it may not be possible to increase the test voltage 311 due to the requirement of the mode setting. Therefore, the sieving rate of the DVS test is limited.

To alleviate the problems of DVS testing, EVS testing is introduced. Referring to FIG. 3B, in the EVS test, a stress signal 328 includes a single-step signal 321 and a single-sequence signal 324, which are applied in a first period 320 and a second period 322, respectively. During the first cycle 320, a single-step signal 321 is applied that rises from ground 323 to a normal operating voltage 325. In the second period 322 following the first period 320, a single sequence of signals 324 is applied that rises from the normal operating voltage 325 to a test voltage 327. In EVS testing, it was found that the sieving rate for wafer level testing could be increased by increasing the duration of the test voltage 327 during the second period 322, rather than increasing the voltage level of the test voltage 327. However, to obtain a higher sieving rate, the second cycle 322 can be compared The test cycle 310 (shown in FIG. 3A ) of the DVS test is much longer. For example, the second period 322 of the EVS test may be ten times longer than the test period 310 of the DVS test. Furthermore, the sieving rate of the EVS test may be only equal to the DVS test or even less desirable than the DVS test.

According to the present disclosure, the above problems can be alleviated.

According to some embodiments of the present disclosure, the sieving rate for wafer level testing can be increased by increasing the amount of voltage variation in the stress signal 220, rather than increasing the voltage level or time period of the test voltage. Referring back to FIGS. 1 and 2A, in some embodiments of the present disclosure, the signal generator 102 provides the CAVS with a stress signal 220 having a plurality of sequences 221A and 221B, which equalize the voltage level in the second cycle 212 fluctuates between a second voltage level 222 and a third voltage level 224 . Thus, the wafer 110 experiences multiple iterations of the voltage change during the second period 212 .

As described above, for example, the stress signal 220 includes two sequences 221A and 221B, where each sequence 221A and 221B includes a ramp-up phase 2231 and a ramp-down phase 2232 . In some embodiments, signal generator 102 provides sequence 221A by increasing the voltage of IC 112 from a first voltage level 200 (ie, the IC's nominal voltage) to a second voltage level 222 (ie, the test voltage) ) to power IC 112. When the ramp-up phase 2231 is applied, one of the states (ie, the "0" state or the "1" state) of at least one semiconductor device in the IC 112 may be changed or switched. Next, the signal generator 102 continues the sequence 221A to power the IC 112 by lowering the voltage after the ramp-up phase 2231. The ramp-down phase 2232 reduces the voltage of the IC 112 from the second voltage level 222 to the third voltage level 224 . When the ramp-down stage 2232 is applied, the state of at least one semiconductor device in the IC 112 can be changed or switched.

Following sequence 221A, signal generator 102 provides sequence 221B to power IC 112. The signal generator 102 provides the sequence 221B by changing the voltage of the IC 112 from the third power The voltage level 224 is increased to the second voltage level 222 to power the IC 112 . Then, the signal generator 102 continues with sequence 221B to power the IC 112 by reducing the voltage of the IC 112 from the second voltage level 222 to ground or the first voltage level 200 . As with sequence 221A, during sequence 221B, the states of semiconductor devices in IC 112 may be changed or switched by ramping up phase 2231 and ramping down phase 2232.

In summary, according to some embodiments of the present disclosure, during the second period 212 , the stress signal 220 may include a plurality of ramp-up phases 2231 and ramp-down phases 2232 . It was found that the state of the semiconductor devices in IC 112 can be more easily changed or switched by CAVS during ramp-up phase 2231 and ramp-down phase 2232. The reason is that the field effects are locally alternating. Therefore, the voltage difference between ramp-up phase 2231 and ramp-down phase 2232 can cause some of the semiconductor devices in IC 112 to go into a short-circuit mode as a fault count. Due to the multiple ramp-up and ramp-down phases, the switching rate of semiconductor devices in IC 112 may be increased. Therefore, the sieving rate of wafer-level testing can be increased by means of the plurality of sequences 221A and 221B, thereby causing voltage fluctuations of the IC 112 between the second voltage level 222 and the third voltage level 224 .

Furthermore, according to some embodiments of the present disclosure, by increasing the amount of the ramp-up phase 2231 from the first voltage level 200 to the second voltage level 222 or by increasing the amount of the ramp-down phase 2232 from the second voltage level The level 222 is increased to the third voltage level 224 to further increase the switching rate of the semiconductor devices in the IC 112 . In other words, the sieving rate for wafer-level testing can be further increased by increasing the voltage changes that occur during ramp-up phase 2231 or during ramp-down phase 2232. It should be understood that any test algorithm that will cover the 0/1 state combination is not limited in order to increase the swap rate. For example, the MBIST (Memory Built-in Self Test) test can use a CKB (chessboard) and a reverse CKB test pattern. The logic test mode may consider a combination of one of several chain tests.

Compared to the DVS test, attributable to the ramp-up phase 2231 and the ramp-down phase 2232 During larger voltage differences, the tests of the present disclosure provide increased screening rates. In the present disclosure, the test voltage 222 is separated from the mode setting voltage (ie, the first voltage level 200). Therefore, the test voltage 222 in the present disclosure may be higher than the test voltage 311 (shown in FIG. 3A ) of the DVS test. Therefore, the sieving rate can be increased.

Compared to EVS testing, the extended period 322 (shown in FIG. 3 ) may be reduced in the present disclosure because the multiple ramp-up and ramp-down phases of the present disclosure may increase the switching rate of the semiconductor devices in IC 112 . Therefore, the duration of the second cycle 212 in the present disclosure can be reduced, and the time-consuming problem in conventional EVS testing can be alleviated.

It should be noted that the application of CAVS is not a limitation of the present disclosure. In some embodiments, CAVS can be applied at room temperature range (about 25°C to about 27°C) or at a temperature range from about 0°C to about -40°C or a temperature range from about 0°C to about 125°C In the wafer probe flow, final test flow, or wafer acceptance test flow.

4 is a diagram of a multi-step power signal for testing a wafer in accordance with some embodiments of the present disclosure. The signal generator 102 (shown in FIG. 1 ) is configured to generate a CAVS including a stress signal 420 during a second period 412 following the first period 210 . The first cycle 210 is depicted in FIG. 2A and is omitted here for brevity.

In some embodiments, during the second period 412, the stress signal 420 is generated. Stress signal 420 may include a plurality of sequences 421A, 421B, 421C, and 421D. Each sequence 421A, 421B, 421C, and 421D includes a ramp-up phase 4231 and a ramp-down phase 4232 . Each sequence 421A, 421B, 421C and 421D fluctuates between the second voltage level 422 and the third voltage level 424 . Either the ramp-up phase 4231 or the ramp-down phase 4232 is not limited in scope. In some embodiments, one of ramp up phase 4231 or ramp down phase 4232 ranges between about 0.1 V/ms and about 0.3 V/ms. The voltage is increased from the first voltage level 200 to the second voltage level 422, and then from the The two voltage levels 422 are decreased to the third voltage level 424, then increased from the third voltage level 424 to the second voltage level 422, and finally decreased from the second voltage level 422 to ground or the first voltage level 200 . It should be noted that the second voltage level 422 and the third voltage level 424 may be the same as the second voltage level 222 and the third voltage level 224 in FIG. 2A , respectively.

The second voltage level 422 is higher than the first voltage level 200 . The value of the second voltage level 422 is not limited. In some embodiments, the second voltage level 422 may be about 1.3 times higher, about 1.58 times higher, about 2.0 times higher, or about 3.0 times higher than the first voltage level 200 . The second voltage level 422 acts as a test voltage. The value of the third voltage level 424 is not limited. The third voltage level 424 is lower than the second voltage level 422 . In some embodiments, the third voltage level 424 may be equal to or less than the first voltage level 200 . In some embodiments, a voltage difference between the second voltage level 422 and the third voltage level 424 is greater than a voltage difference between the first voltage level 200 and the second voltage level 422 . In some embodiments, the third voltage level 424 may be approximately 0.7 times the first voltage level 200 . In some embodiments, the third voltage level 224 may be approximately 0.9 times the second voltage level 422 .

As described above, according to some embodiments of the present disclosure, the sieving rate for wafer-level testing may be increased by increasing the amount of voltage variation in stress signal 420 . In some embodiments, the signal generator 102 may provide the stress signal 420 with a plurality of sequences 421A, 421B, 421C, and 421D that fluctuate between the second voltage level 422 and the third voltage level 424 during the second period 412 .

As an example, stress signal 420 includes four sequences 421A, 421B, 421C, and 421D, and each sequence 421A, 421B, 421C, and 421D includes a ramp-up phase 4231 and a ramp-down phase 4232 . In some embodiments, signal generator 102 provides sequence 421A for IC 112 by increasing the voltage of IC 112 from first voltage level 200 to second voltage level 422 (shown in Figure 1) power supply. When the ramp-up phase 4231 is applied, one of the states of at least one semiconductor device in the IC 112 can be changed or switched. Next, the signal generator 102 continues the sequence 421A to power the IC 112 by lowering the voltage after the ramp-up phase 4231. The voltage of the IC 112 is reduced from the second voltage level 422 to the third voltage level 424 . When the ramp-down stage 4232 is applied, the state of at least one semiconductor device in the IC 112 can be changed or switched.

Following sequence 421A, signal generator 102 provides sequence 421B to power IC 112. Signal generator 102 provides sequence 421B to power IC 112 by increasing the voltage of IC 112 from third voltage level 424 to second voltage level 422 . Then, the signal generator 102 continues the sequence 421B to power the IC 112 by reducing the voltage of the IC 112 from the second voltage level 422 to the third voltage level 424. As with sequence 421A, during sequence 421B, the states of semiconductor devices in IC 112 may be changed or switched by ramping up phase 4231 and ramping down phase 4232. It should be understood that the ramp-down phase 4232 of the sequence 421B may reduce the voltage of the IC 112 from the second voltage level 422 to another voltage lower than the third voltage level 424 . Following sequence 421B, signal generator 102 provides sequence 421C to power IC 112 in a similar manner, and a description thereof is omitted here for brevity.

Following sequence 421C, signal generator 102 provides sequence 421D to power IC 112. Signal generator 102 provides sequence 421D to power IC 112 by increasing the voltage of IC 112 from third voltage level 424 to second voltage level 422 . Then, the signal generator 102 continues the sequence 421D to power the IC 112 by reducing the voltage of the IC 112 from the second voltage level 422 to ground or the first voltage level 200 . As with sequences 421A and 421B, during sequence 421D, the state of the semiconductor devices in IC 112 may be changed or switched by ramp-up stage 4231 and ramp-down stage 4232.

In summary, according to some embodiments of the present disclosure, during the second period 412, The stress signal 420 may include a plurality of ramp-up phases 4231 and ramp-down phases 4232 . It was found that the state of the semiconductor devices in IC 112 can be more easily changed or switched by CAVS during ramp up phase 4231 and ramp down phase 4232. The reason is that the field effects are locally alternating. Therefore, the voltage difference between the ramp-up phase 4231 and the ramp-down phase 4232 can cause some of the semiconductor devices in the IC 112 to go into a short-circuit mode as a fault count. Due to the multiple ramp-up and ramp-down phases, the switching rate of semiconductor devices in IC 112 can be increased by using the current CAVS. Therefore, the sieving rate of wafer level testing can be increased by means of the plurality of sequences 421A, 421B, 421C and 421D, thereby causing voltage fluctuations of the IC 112 between the second voltage level 422 and the third voltage level 424. It should be noted that CAVS may have higher defect coverage on short-circuit mode faults, but is not limited to covering only short-circuit mode faults.

Furthermore, according to some embodiments of the present disclosure, by increasing the amount of ramp-up phase 4231 from the first voltage level 200 to the second voltage level 422 or by increasing the amount of ramp-down phase 4232 from the second voltage level The level 422 is lowered to the third voltage level 424 to further increase the switching rate of the semiconductor devices in the IC 112 . In other words, the sieving rate for wafer-level testing can be further increased by increasing the voltage changes that occur during ramp-up phase 4231 or during ramp-down phase 4232.

5 is a diagram of a multi-step power signal for testing a wafer, according to some embodiments of the present disclosure. The signal generator 102 (shown in FIG. 1 ) is configured to generate a stress signal 520 during a second period 512 following the first period 210 . The first cycle 210 is depicted in FIG. 2A and is omitted here for brevity.

The difference between the stress signal 520 and the stress signal 220 in FIG. 2A is that the stress signal 520 can have a longer duration at the second voltage level 522 than the stress signal 220 . The stress signal 520 may have a sequence with a longer duration at the second voltage level 522 Column 521A and a sequence 521B with a shorter duration at the second voltage level 522. It should be noted that the stress signal 520 may have more than one sequence 521B with a shorter duration at the second voltage level 522. In some embodiments, the duration of sequence 521B is similar to the duration of sequences 221A, 221B in Figure 2A.

6 is a diagram of a multi-step power signal for testing a wafer, according to some embodiments of the present disclosure. The signal generator 102 (shown in FIG. 1 ) is configured to generate a signal at a first voltage level 600 during a first period 610 and a stress signal during a second period 612 following the first period 610 620. Stress signal 620 may include a plurality of sequences 621A, 621B, and 621C. Sequences 621A, 621B, and 621C are similar to sequences 421A, 421B, and 421D in FIG. 4, and are omitted here for brevity.

The difference between the signal in FIG. 6 and the signal in FIG. 2A is that the first voltage level 600 is higher than the first voltage 200 . The value of the first voltage level 600 is not limited. In some embodiments, the first voltage level 600 may be about 1.1 to about 1.3 times the first voltage level 200 .

7 is a flowchart illustrating a method according to some embodiments of the present disclosure. Method 700 of wafer level testing may include operations 712 , 714 , 716 and 718 . In operation 712, a wafer having an IC formed thereon is provided. In operation 714, the IC is powered by raising the voltage of the IC to a first voltage level during a first cycle. In operation 716, a stress signal is applied to the IC. The stress signal includes a sequence of ramp-up phases and ramp-down phases during a second cycle following the first cycle. The sequence fluctuates the voltage of the IC between a second voltage level and a third voltage level. In operation 718, after applying the stress signal, it is determined whether the IC meets a test criterion. Detailed descriptions of these operations are similar to those shown in Figures 1, 2A, and 4, and are therefore omitted for brevity.

FIG. 8 illustrates a flow of a method according to some embodiments of the present disclosure picture. Method 800 of wafer level testing may include operations 812 , 814 , 816 and 818 . In operation 812, a wafer having an IC formed thereon is provided. In operation 814, the IC is powered by raising the voltage of the IC to a first voltage level during a first cycle. In operation 816, a stress signal is applied to the IC. The stress signal includes a plurality of ramp-up phases and a plurality of ramp-down phases during a second cycle following the first cycle. The ramp-up phase and the ramp-down phase are applied alternately. In operation 818, after applying the stress signal, it is determined whether the IC meets a test criterion. Detailed descriptions of these operations are similar to those shown in Figures 1, 2A, and 4, and are therefore omitted for brevity.

In summary, according to some embodiments of the present disclosure, the switching state (ie, "0" state or "1" state) of semiconductor devices in an IC can be more easily changed by CAVS during multiple ramp-up and ramp-down phases or switch. The reason is that the field effects are locally alternating. Therefore, the voltage difference between the ramp-up phase and the ramp-down phase can cause some of the semiconductor devices in the IC to go into a short-circuit mode as a fault count. Due to the multiple ramp-up and ramp-down stages, the switching rate of semiconductor devices in the IC can be increased by using the current CAVS. Thus, the sieving rate (ie, failure count divided by total device count) for wafer-level testing can be increased. Furthermore, according to some embodiments of the present disclosure, the sieving rate for wafer-level testing can be further increased by virtue of a larger voltage difference in the ramp-up phase or the ramp-down phase.

FIG. 9 is a diagram of one of an inverter circuit 900 according to some embodiments of the present disclosure. In some embodiments, inverter circuit 900 may be included in IC 112 . Referring to FIG. 9 , the inverter circuit 900 includes a PMOS 901 and an NMOS 903 . The PMOS 901 has a source, a gate and a drain. The source of the PMOS 901 is connected to an input terminal Vin (also referred to as a power terminal), and is configured to receive an input signal (eg, CAVS). In some embodiments, the gate of PMOS 901 is connected to another input terminal Vin1. In some embodiments, The drain of the PMOS 901 is connected to an output terminal Vout, and is configured to output an output signal in response to the input signal. The NMOS 903 has a source, a drain and a gate. The drain of NMOS 903 is electrically connected to the drain of PMOS 901 . The source of NMOS 903 is connected to ground. The gate of NMOS 903 is electrically connected to the gate of PMOS 901 .

In some embodiments, an output signal in response to an input signal (eg, a stress signal) is monitored at the output terminal Vout to determine whether the inverter circuit 900 is operating normally. For example, during a voltage stress test, the input terminal Vin1 of inverter circuit 900 (the gate of each of PMOS 901 and NMOS 903 ) can be connected to ground and a stress signal (eg, CAVS) applied to the inverter The input terminal Vin of the circuit 900 (eg, the source of the PMOS 901 ). Under normal operation of the inverter circuit 900, the output signal at the output terminal Vout substantially follows the stress signal at the input terminal Vin because the gates of each of the PMOS 901 and NMOS 903 are connected to ground (which will turn off NMOS 903). For example, the output signal of inverter circuit 900 will be logically the same as the stress signal. In the event of abnormal operation of the inverter circuit 900, the output signal of the inverter circuit 900 may be partially or completely different from the stress signal. For example, the output signal does not follow the stress signal applied to the input terminal Vin.

10 illustrates an input signal 1002 as shown in FIG. 9 applied to the input terminal Vin of the inverter circuit 900 and an output obtained at the output terminal Vout of the inverter circuit 900 in accordance with some embodiments of the present disclosure A timing diagram of signal 1004. In some embodiments, the input signal 1002 is the same as or similar to the signal shown in FIG. 2A, and some description of the input signal 1002 is omitted here for brevity. In other embodiments, the signals shown in any of FIGS. 2B , 3A, 3B, 4 , 5 and 6 may be used as the input signal 1002 for the inverter circuit 900 .

As shown in FIG. 10, in response to the first period 210 of the input signal 1002 and the first In the two periods 212 , the output signal 1004 includes a first period 1010 and a second period 1012 correspondingly. In some embodiments, in response to the first voltage level 200 of the input signal 1002 during the first period 210, the output signal 1004 rises to a first voltage level 1020 during the first period 1010, and the output signal 1004 is Monitoring and input signal 1002 are logically the same. During the second period 1012 following the first period 1010, the output signal 1004 is partially different from the input signal 1002. For example, the logic difference between input signal 1002 and output signal 1004 occurs at the rising edge of stress signal 220 of input signal 1002 (eg, sequence 221A). The output signal 1004 ramps from a first voltage level 1020 to a lower voltage level 1026 in response to the sequence 221A of the stress signal 220 of the input signal 1002 . After the duration of the lower voltage level 1026, the output signal 1004 ramps up to a second voltage level 1022. The second voltage level 1022 is logically the same as the second voltage level 222 of the input signal 1002 . In response to the ramp-down phase of the first pulse 221A, the output signal 1004 ramps down to a third voltage level 1024 . The third voltage level 1024 is logically the same as the third voltage level 224 of the input signal 1002 . Then, the output signal 1004 is logically the same as the input signal 1002 in the remainder of the second cycle.

In some embodiments, a logical difference between the input signal 1002 and the output signal 1004 as shown in FIG. 10 may indicate an abnormal device structure (or an unnatural leakage or damage) in the inverter circuit 900 . This abnormal device structure (or an unnatural leak or damage) can occur due to the stress signal applied to the IC. In some embodiments, the logic difference between the input signal 1002 and the output signal 1004 may be indicative of leakage between the gate and drain of the semiconductor structure (eg, PMOS 901 or NMOS 903 ) caused by program variation or insufficient margin current or damage. Abnormal device structures, including but not limited to gates, sources, drains, contacts, interlayer dielectrics (ILDs), fins, Metal gate, epitaxy (EPI), etc. Unnatural damage can include a round of a metal gate of a semiconductor device profile deformation, deformation of a contact of a semiconductor device, or an impurity in a dielectric of a semiconductor device. In some embodiments, an input signal 1002 (eg, a stress signal) as shown in FIG. 10 can be applied to any other logic circuit to check for any defects in the logic circuit based on the output signal.

FIG. 11A illustrates a semiconductor structure 11A according to some embodiments of the present disclosure. In some embodiments, the semiconductor structure 11A is part of a transistor. For example, semiconductor structure 11A may be part of PMOS 901 or NMOS 903 , as shown in FIG. 9 . The semiconductor structure 11A includes a substrate 110a, a gate 110b, a gate dielectric 110c, a spacer 110d, a contact 110e, and an epitaxial 110f.

Referring to the circuit of FIG. 9 , the epitaxy 110f may be the source of either the PMOS 901 or the NMOS 903 . In some embodiments, epitaxial 110f may be the drain of either PMOS 901 or NMOS 903 . In some embodiments, the contact 110e may be a source contact of the PMOS 901 connected to the input terminal Vin. In some embodiments, the contact 110e may be a drain contact of the PMOS 901 connected to the output terminal Vout. In some embodiments, contact 110e may be a drain contact of NMOS 903 connected to the drain of PMOS 901 . In some embodiments, contact 110e may be a source contact of NMOS 903 connected to ground. The gate 110b may be the gate of the PMOS 901 or the NMOS 903 connected to the other input terminal Vin1.

The gate dielectric 110c is disposed on the substrate 110a. Gate 110b is disposed on gate dielectric 110c. The spacer 110d is disposed on the substrate 110a. The spacer 110d is disposed beside the gate electrode 110b. Spacer 110d may contact gate 110b and gate dielectric 110c. The contacts 110e are disposed on the substrate 110a. The contact 110e is positioned next to the spacer 110d. Contact 110e is physically spaced from spacer 110d. For example, a gap exists between the contact 110e and the spacer 110d. In some embodiments, a distance D1 between the contact 110e and the gate 110b is less than 3 nm.

If the distance between the contact and the gate of the transistor is less than 3 nm, it is difficult to perform a voltage stress test on the transistor using the prior art. As the size of semiconductor devices becomes smaller, it is difficult to test such structures. By using the method of the present disclosure, the escape defect rate as a result of performing the voltage stress test will be lower. In other words, with the method of the present disclosure, testing a transistor system with contacts and gates smaller than 3 nm is more accurate and reliable. In some embodiments, by using the stress signal as shown in Figure 2A and monitoring the output signal as shown in Figures 9 and 10, voltage can be performed on any transistor with a gate-to-contact spacing of less than 3 nm stress test.

FIG. 11B illustrates a semiconductor structure 11B according to some embodiments of the present disclosure. In some embodiments, the semiconductor structure 11B is part of a transistor. For example, semiconductor structure 11B may be part of PMOS 901 or NMOS 903 , as shown in FIG. 9 . The semiconductor structure 11B includes a substrate 111a, a gate 111b, a gate dielectric 111c, a spacer 111d, a contact 111e and an epitaxial 111f.

Referring to the circuit of FIG. 9 , the epitaxy 111f may be the source of either the PMOS 901 or the NMOS 903 . In some embodiments, epitaxial 111f may be the drain of either PMOS 901 or NMOS 903 . In some embodiments, the contact 111e may be a source contact of the PMOS 901 connected to the input terminal Vin. In some embodiments, the contact 111e may be a drain contact of the PMOS 901 connected to the output terminal Vout. In some embodiments, the contact 111e may be a drain contact of the NMOS 903 connected to the drain of the PMOS 901 . In some embodiments, the contact 111e may be a source contact of the NMOS 903 connected to ground. The gate 111b may be the gate of the PMOS 901 or the NMOS 903 connected to the other input terminal Vin1.

The substrate 111a has a surface 111s. The gate dielectric 111c is disposed on the surface 111s of the substrate 111a. The gate 111b is disposed on the gate dielectric 111c. The spacer 111d is disposed on the surface 111s of the substrate 111a. The spacer 111d is disposed beside the gate electrode 111b. spacer 111d can contact the gate 111b and the gate dielectric 111c. The contacts 111e are disposed on the substrate 111a. The contact point 111e is arranged beside the spacer 111d. The contact 111e is physically spaced from the spacer 111d. For example, a gap exists between the contact point 111e and the spacer 111d. The epitaxy 111f is disposed in the substrate 111a. The epitaxy 111f is below the contacts. In some embodiments, a minimum distance D2 between a projection line of the gate electrode 111b on the surface 111s of the substrate 111a and a projection line of the epitaxial layer 111f on the surface 111s of the substrate 111a is less than 1 nm.

If the minimum distance between a projected line of the gate on the substrate and a projected line of the epitaxial on the substrate is less than 1 nm, it is difficult to perform a voltage stress test on the transistor using the prior art. As the size of semiconductor devices becomes smaller, it is difficult to test such structures. By using the method of the present disclosure, the escape defect rate will be lower as a result of performing a voltage stress test using the prior art. In other words, by virtue of the method of the present disclosure, it is more accurate and reliable to test a transistor system having a projection line of the gate on the substrate and a projection line of the epitaxial on the substrate smaller than 1 nm. By using the stress signal as shown in Figure 2A and monitoring the output signal as shown in Figures 9 and 10, voltage stress testing can be performed on any transistor with a gate-to-epitaxial spacing of less than 1 nm.

According to some embodiments, a method is provided. The method includes: providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first cycle; A stress signal is applied to the input terminal of the DUT during the latter second cycle; an output signal is obtained in response to the stress signal at the output terminal of the DUT; and the output signal is compared with the stress signal. The stress signal includes a plurality of sequences, and each sequence has a ramp-up phase and a ramp-down phase. The stress signal has a second voltage level and a third voltage level.

According to other embodiments, a method is provided. The method includes: providing A device under test (DUT) with an input terminal and an output terminal; apply a stress signal to the input terminal of the DUT; obtain an output signal in response to the stress signal at the output terminal of the DUT; compare the output signal with the stress signal ; and determining whether the DUT has an abnormal structure based on a result of the comparison between the output signal and the stress signal. The output signal includes a plurality of sequences, and each sequence has a ramp-up phase and a ramp-down phase. The output signal has a first voltage level and a second voltage level.

According to other embodiments, a semiconductor device is provided. The semiconductor device includes a first input terminal configured to receive a stress signal and an output terminal configured to generate an output signal in response to the stress signal. The semiconductor device further includes a substrate, a gate and a contact. The gate is disposed on the substrate. The contacts are arranged on the substrate and next to the gate. The contacts are electrically connected to the first input terminal or the output terminal. A distance between the gate and the contact is less than 3 nanometers (nm).

The foregoing outlines the components of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other programs and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

100: System

101: Probe

102: Signal Generator

104: Coupler

106: Mods

110: Wafer

112: Integrated Circuits (ICs)

Claims (10)

A method for wafer level testing, comprising: providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the the input terminal of the DUT; applying a stress signal to the input terminal of the DUT during a second cycle after the first cycle, the stress signal comprising a plurality of sequences, each of the sequences having a ramp stage and a ramp-down stage, wherein the stress signal has a second voltage level and a third voltage level; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and combining the output signal with The stress signal is compared. The method of claim 1, further comprising determining whether the DUT has an abnormal structure based on a result of the comparison between the output signal and the stress signal. The method of claim 1, wherein the second voltage level is about 1.3 to about 3.0 times higher than the first voltage level. The method of claim 1, wherein the DUT comprises: a PMOS having a source connected to the input terminal of the DUT, a gate, and a drain connected to the output terminal of the DUT; and an NMOS , which has a source connected to ground, a gate connected to the PMOS a gate and a drain connected to the output terminal of the DUT. A method for wafer level testing, comprising: providing a device under test (DUT) having an input terminal and an output terminal; applying a stress signal to the input terminal of the DUT; The stress signal at the output terminal obtains an output signal comprising a plurality of sequences, each of the sequences having a ramp-up phase and a ramp-down phase, wherein the output signal has a first voltage level and a a second voltage level; comparing the output signal with the stress signal; and determining whether the DUT has an abnormal structure based on a result of the comparison between the output signal and the stress signal. The method of claim 5, wherein the DUT is determined to have the abnormal structure if the output signal is logically different from the stress signal in the same time domain. The method of claim 5, wherein the DUT comprises: a PMOS having a source connected to the input terminal of the DUT, a gate, and a drain connected to the output terminal of the DUT; and an NMOS , which has a source connected to ground, a gate connected to the gate of the PMOS, and a drain connected to the output terminal of the DUT. A semiconductor device comprising: a first input terminal configured to receive a stress signal; an output terminal configured to generate an output signal in response to the stress signal; a substrate; a gate disposed on the substrate; and a contact disposed on the substrate and beside the gate, wherein the contact is electrically connected to the first input terminal or the output terminal, and wherein a distance between the gate and the contact is less than 3 nanometers (nm). The semiconductor device of claim 8, further comprising: an epitaxial disposed in the substrate and below the contact, wherein a projection line of the gate on the substrate and one of the epitaxy on the substrate A minimum distance between projection lines is less than 1 nm. The semiconductor device of claim 8, wherein the output signal responsive to the stress signal comprises a plurality of sequences, each of the sequences having a ramp-up phase and a ramp-down phase, wherein the output signal has a first voltage level and a second voltage level.

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