TW202217996A - Method and device for wafer-level testing - Google Patents

Method and device for wafer-level testing Download PDF

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TW202217996A
TW202217996A TW110117581A TW110117581A TW202217996A TW 202217996 A TW202217996 A TW 202217996A TW 110117581 A TW110117581 A TW 110117581A TW 110117581 A TW110117581 A TW 110117581A TW 202217996 A TW202217996 A TW 202217996A
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voltage level
signal
dut
ramp
voltage
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TWI775435B (en
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軍 何
林裕庭
林威勳
郭永良
盧胤龍
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台灣積體電路製造股份有限公司
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    • G01R31/317—Testing of digital circuits
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
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    • G—PHYSICS
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    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

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Abstract

The present disclosure provides a method and a system for testing semiconductor device. The method includes providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first period; applying a stress signal to the input terminal of the DUT during a second period subsequent to the first period; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and comparing the output signal with the stress signal. The stress signal includes a plurality of sequences, each having a ramp-up stage and a ramp-down stage. The stress signal has a second voltage level and a third voltage level.

Description

晶圓級測試方法及裝置Wafer-level testing method and apparatus

本發明實施例係有關晶圓級測試方法及裝置。Embodiments of the present invention relate to a wafer-level testing method and device.

在半導體製造中，一晶圓通常經歷許多製程以形成一積體電路。執行各種晶圓級測試以判定各種條件下積體電路之效能及可靠性以及晶圓接受。晶圓級可靠性測試用於偵測與在積體電路製造期間產生之缺陷相關聯之早期故障之可能性。通常，可靠性測試涉及使用各種技術(諸如開/關電力循環)對積體電路加應力及施加超過正常操作條件之電壓。然而，歸因於在測試期間積體電路之非預期損壞或劣化，當前測試技術可提供無效之可靠性評估。因此，期望開發用於測試之一更有效之加應力方法。In semiconductor manufacturing, a wafer typically undergoes many processes to form an integrated circuit. Various wafer-level tests are performed to determine the performance and reliability of integrated circuits and wafer acceptance under various conditions. Wafer-level reliability testing is used to detect the likelihood of early failure associated with defects generated during integrated circuit fabrication. Generally, reliability testing involves stressing integrated circuits and applying voltages in excess of normal operating conditions using various techniques, such as on/off power cycling. However, current testing techniques can provide ineffective reliability assessments due to unexpected damage or degradation of integrated circuits during testing. Therefore, it is desirable to develop a more efficient stressing method for testing.

本發明的一實施例係關於一種方法，其包括：提供具有一輸入端子及一輸出端子之一受測試裝置(DUT)；在一第一週期期間將具有一第一電壓位準之電壓施加至該DUT之該輸入端子；在該第一週期之後之一第二個週期期間將一應力訊號施加至該DUT之該輸入端子，該應力訊號包含複數個序列，該序列之各者具有一斜升階段及一斜降階段，其中該應力訊號具有一第二電壓位準及一第三電壓位準；回應於該DUT之該輸出端子之該應力訊號獲得一輸出訊號；及將該輸出訊號與該應力訊號進行比較。One embodiment of the invention relates to a method comprising: providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the the input terminal of the DUT; applying a stress signal to the input terminal of the DUT during a second cycle after the first cycle, the stress signal comprising a plurality of sequences, each of the sequences having a ramp stage and a ramp-down stage, wherein the stress signal has a second voltage level and a third voltage level; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and combining the output signal with the stress signal for comparison.

本發明的一實施例係關於一種方法，其包括：提供具有一輸入端子及一輸出端子之一受測試裝置(DUT)；將一應力訊號施加至該DUT之該輸入端子；回應於在該DUT之該輸出端子處之該應力訊號獲得一輸出訊號，該輸出訊號包含複數個序列，該序列之各者具有一斜升階段及一斜降階段，其中該輸出訊號具有一第一電壓位準及一第二電壓位準；將該輸出訊號與該應力訊號進行比較；及基於該輸出訊號與該應力訊號之間的該比較之一結果判定該DUT是否具有一異常結構。One embodiment of the invention relates to a method comprising: providing a device under test (DUT) having an input terminal and an output terminal; applying a stress signal to the input terminal of the DUT; The stress signal at the output terminal obtains an output signal, the output signal includes a plurality of sequences, each of the sequences has a ramp-up phase and a ramp-down phase, wherein the output signal has a first voltage level and a second voltage level; comparing the output signal with the stress signal; and determining whether the DUT has an abnormal structure based on a result of the comparison between the output signal and the stress signal.

本發明的一實施例係關於一種半導體裝置，其包括：一第一輸入端子，其經組態以接收一應力訊號；一輸出端子，其經組態以回應於該應力訊號產生一輸出訊號；一基板；一閘極，其安置於該基板上；及一接點，其安置於該基板上及該閘極旁邊，其中該接點經電連接至該第一輸入端子或該輸出端子，且其中該閘極與該接點之間的一距離小於3奈米(nm)。One embodiment of the present invention relates to a semiconductor device comprising: a first input terminal configured to receive a stress signal; an output terminal configured to generate an output signal in response to the stress signal; a substrate; a gate disposed on the substrate; and a contact disposed on the substrate and beside the gate, wherein the contact is electrically connected to the first input terminal or the output terminal, and Wherein a distance between the gate and the contact is less than 3 nanometers (nm).

以下揭露提供用於實施所提供標的物之不同構件之許多不同實施例或實例。在下文描述組件及配置之特定實例以簡化本揭露。當然，此等僅為實例且不意欲為限制性的。例如，在以下描述中，在一第二構件上方或上形成一第一構件可包含其中第一構件及第二構件形成為直接接觸之實施例，且亦可包含其中額外構件可形成於第一構件與第二構件之間，使得第一構件及第二構件可不直接接觸之實施例。另外，本揭露可在各種實例中重複元件符號及/或字母。此重複係出於簡單及清晰之目的且本身不指示所論述之各種實施例及/或構形之間的一關係。The following disclosure provides many different embodiments or examples of different means for implementing the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first member over or on a second member may include embodiments in which the first member and the second member are formed in direct contact, and may also include embodiments in which additional members may be formed on the first member Between the member and the second member, the first member and the second member may not be in direct contact with each other. Additionally, the present disclosure may repeat reference numerals and/or letters in various instances. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or configurations discussed.

下文詳細討論本揭露之實施例。然而，應瞭解，本揭露提供可在各種特定內容背景中體現之許多可應用發明概念。所討論之特定實施例僅係繪示性的且不限制本揭露之範疇。Embodiments of the present disclosure are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are illustrative only and do not limit the scope of the present disclosure.

此外，為便於描述，諸如「在……下方」、「在……下」、「下」、「在……上方」、「上」、「下」、「左」、「右」及類似物之空間相對術語可在本文中用於描述一個元件或構件與圖中繪示之另一(些)元件或構件之關係。除在圖中描繪之定向以外，空間相對術語亦意欲涵蓋在使用或操作中之裝置之不同定向。設備可以其他方式定向(旋轉90度或按其他定向)且因此可同樣解釋本文中使用之空間相對描述詞。應理解，當一元件被稱為「連接」或「耦合」至另一元件時，其可直接連接或耦合至另一元件或可存在中介元件。Also, for ease of description, expressions such as "below", "below", "below", "above", "above", "below", "left", "right" and the like The spatially relative terms may be used herein to describe the relationship of one element or component to another element or component(s) depicted in the figures. In addition to the orientation depicted in the figures, spatially relative terms are also intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and thus the spatially relative descriptors used herein may likewise be interpreted. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present.

在一些習知電壓應力測試中，可需要改良用於晶圓級測試之篩分速率(即，故障計數除以總裝置數目)。發現快速改變積體電路(IC)中之半導體裝置之切換狀態(即，「0」狀態或「1」狀態)可改良晶圓級測試之篩分速率。根據本揭露之一些實施例，訊號產生器可提供一循環交變電壓應力(CAVS)，應力訊號具有複數個序列，其等使電壓位準在一時間週期中在一高電壓位準與一低電壓位準之間交替地波動。在多個斜升及斜降階段期間，積體電路(IC)中之半導體裝置之切換狀態(即，「0」狀態或「1」狀態)可藉由CAVS更容易地改變。原因係場效應係局部交替的。因此，應力訊號可使一些半導體裝置變為一短路模式作為一故障計數。歸因於多個斜升及斜降階段，可增加IC中之半導體裝置之調換速率。因此，可改良晶圓級測試之篩分速率。In some conventional voltage stress tests, it may be desirable to improve the sieving rate (ie, failure count divided by total device count) for wafer-level testing. Rapidly changing the switching state (ie, "0" state or "1" state) of a semiconductor device in an integrated circuit (IC) was found to improve the screening rate for wafer-level testing. According to some embodiments of the present disclosure, the signal generator can provide a cyclic alternating voltage stress (CAVS), the stress signal has a plurality of sequences, which make the voltage level a high voltage level and a low voltage level in a time period The voltage levels fluctuate alternately. The switching state (ie, "0" state or "1" state) of a semiconductor device in an integrated circuit (IC) can be more easily changed by CAVS during multiple ramp-up and ramp-down phases. The reason is that the field effects are locally alternating. Thus, the stress signal can cause some semiconductor devices to go into a short-circuit mode as a fault count. Due to the multiple ramp-up and ramp-down phases, the switching rate of semiconductor devices in the IC can be increased. Therefore, the screening rate for wafer-level testing can be improved.

圖1係根據本揭露之一些實施例之用於測試一半導體裝置之一系統100之一圖解視圖。圖2A係根據本揭露之一些實施例之用於測試一晶圓之一多步功率訊號之一繪示。1 is a diagrammatic view of a system 100 for testing a semiconductor device in accordance with some embodiments of the present disclosure. 2A is a diagram of a multi-step power signal for testing a wafer, according to some embodiments of the present disclosure.

參考圖1及圖2A，系統100經組態以測試形成在一晶圓110上之一積體電路(IC)。晶圓110可稱為一受測試裝置(DUT)。晶圓110可包括一元素半導體，諸如矽、鍺或金剛石。晶圓110可包含形成於其上之一或多個IC 112 (或晶片)。可在相鄰IC 112之間提供切割道，使得IC可在後續處理中分離。Referring to FIGS. 1 and 2A , the system 100 is configured to test an integrated circuit (IC) formed on a wafer 110 . Wafer 110 may be referred to as a device under test (DUT). Wafer 110 may include an elemental semiconductor, such as silicon, germanium, or diamond. Wafer 110 may include one or more ICs 112 (or chips) formed thereon. Dicing lanes can be provided between adjacent ICs 112 so that the ICs can be separated in subsequent processing.

在一些實施例中，系統100可為自動測試設備(ATE)。系統100可包含為測試提供一適當操作及功能環境之硬體及軟體組件。在一些實施例中，系統100包含一訊號產生器102、一耦合器104及一模組106。In some embodiments, the system 100 may be automatic test equipment (ATE). System 100 may include hardware and software components that provide a suitable operating and functional environment for testing. In some embodiments, the system 100 includes a signal generator 102 , a coupler 104 and a module 106 .

訊號產生器102經組態以產生一循環交變電壓應力(CAVS)。CAVS包含在一第一週期210期間之一第一電壓位準200之一訊號及在第一週期210之後之一第二週期212期間之一應力訊號220。應理解，諸如資料訊號及時脈訊號之其他電訊號可被提供至DUT，但為了清楚及簡單起見未繪示。The signal generator 102 is configured to generate a cyclic alternating voltage stress (CAVS). CAVS includes a signal at a first voltage level 200 during a first period 210 and a stress signal 220 during a second period 212 following the first period 210 . It should be understood that other electrical signals, such as data signals and clock signals, may be provided to the DUT, but are not shown for clarity and simplicity.

在一些實施例中，在第一週期210期間，產生從接地(即，0 V)上升至一第一電壓位準200之一單步訊號。第一電壓位準200可為IC 112之標稱電壓或高電壓(例如，高標稱電壓之5%至10%)。對於一電力循環測試，可用標稱電壓為IC 112供能。在一些實施例中，從接地上升至第一電壓位準200之持續時間可係基於電壓轉換率之毫秒級。In some embodiments, during the first period 210, a single-step signal is generated that rises from ground (ie, 0 V) to a first voltage level 200 . The first voltage level 200 may be the nominal voltage of the IC 112 or a high voltage (eg, 5% to 10% of the high nominal voltage). For a power cycling test, IC 112 may be powered with nominal voltage. In some embodiments, the duration of the rise from ground to the first voltage level 200 may be on the order of milliseconds based on the voltage slew rate.

在一些實施例中，在第二週期212期間，產生應力訊號220。應力訊號220用來對DUT加過應力，且引發與製程相關聯之故障。應力訊號220可包含複數個序列221A及221B。序列221A及221B之各者包含一斜升階段2231及一斜降階段2232。序列221A及221B之各者包含一第二電壓位準222與一第三電壓位準224之間的一電壓變化。斜升階段2231或斜降階段2232之一範圍不受限制。在一些實施例中，斜升階段2231或斜降階段2232之範圍在約0.1 V/毫秒(ms)與約0.3 V/ms之間。斜升階段2231將電壓從第一電壓位準200升高至第二電壓位準222，且斜降階段2232將電壓從第二電壓位準222降低至第三電壓位準224。In some embodiments, during the second period 212, the stress signal 220 is generated. The stress signal 220 is used to overstress the DUT and cause process-related failures. The stress signal 220 may include a plurality of sequences 221A and 221B. Each of sequences 221A and 221B includes a ramp-up phase 2231 and a ramp-down phase 2232 . Each of sequences 221A and 221B includes a voltage change between a second voltage level 222 and a third voltage level 224 . Either the ramp-up phase 2231 or the ramp-down phase 2232 is not limited in scope. In some embodiments, the ramp-up phase 2231 or the ramp-down phase 2232 ranges between about 0.1 V/millisecond (ms) and about 0.3 V/ms. The ramp-up phase 2231 increases the voltage from the first voltage level 200 to the second voltage level 222 , and the ramp-down phase 2232 reduces the voltage from the second voltage level 222 to the third voltage level 224 .

應理解，應力訊號可取決於測試要求及/或歷史資料而變化。例如，應力訊號可取決於每百萬份缺陷(DPPM)。在一些行業中，缺陷容差可更低，例如，在汽車或行動電話行業中，且可增加應力訊號之序列。第二電壓位準222高於第一電壓位準200。第二電壓位準222之值不受限制。在一些實施例中，第二電壓位準222可比第一電壓位準200高約1.3倍，高約1.58倍，高約2.0倍，或高約3.0倍。第二電壓位準222充當一測試電壓(或應力電壓)。第三電壓位準224之值不受限制。第三電壓位準224低於第二電壓位準222。在一些實施例中，第三電壓位準224可等於或低於第一電壓位準200。在一些實施例中，第二電壓位準222與第三電壓位準224之間的一電壓差大於第一電壓位準200與第二電壓位準222之間的一電壓差。在一些實施例中，第三電壓位準224可為第一電壓位準200之約0.7倍。在一些實施例中，第三電壓位準224可為第二電壓位準222之約0.9倍。第三電壓位準224之一持續時間可包含一等待時間及一檢查告警時間。第三電壓位準224之持續時間不受限制，且可被視為抑制由電壓應力引起之自加熱效應之冷卻時間。在一些實施例中，第三電壓位準224之持續時間可為約6至10 ms，在數百ms內或超過數百ms。It should be understood that the stress signal may vary depending on test requirements and/or historical data. For example, the stress signal may depend on defects per million (DPPM). In some industries, the defect tolerance may be lower, for example, in the automotive or mobile phone industries, and the sequence of stress signals may be increased. The second voltage level 222 is higher than the first voltage level 200 . The value of the second voltage level 222 is not limited. In some embodiments, the second voltage level 222 may be about 1.3 times higher, about 1.58 times higher, about 2.0 times higher, or about 3.0 times higher than the first voltage level 200 . The second voltage level 222 acts as a test voltage (or stress voltage). The value of the third voltage level 224 is not limited. The third voltage level 224 is lower than the second voltage level 222 . In some embodiments, the third voltage level 224 may be equal to or lower than the first voltage level 200 . In some embodiments, a voltage difference between the second voltage level 222 and the third voltage level 224 is greater than a voltage difference between the first voltage level 200 and the second voltage level 222 . In some embodiments, the third voltage level 224 may be approximately 0.7 times the first voltage level 200 . In some embodiments, the third voltage level 224 may be approximately 0.9 times the second voltage level 222 . A duration of the third voltage level 224 may include a wait time and a check alarm time. The duration of the third voltage level 224 is not limited and can be considered as a cooling time to suppress the self-heating effect caused by voltage stress. In some embodiments, the duration of the third voltage level 224 may be about 6 to 10 ms, within or in excess of hundreds of ms.

圖2B係根據本揭露之一些實施例之序列之一多步斜升及斜降階段之一繪示。參考圖2B，在一些實施例中，斜升階段2231’及斜降階段2232’包含多個步長。憑藉多個步長，可避免電流過衝。應注意，斜升階段2231’及斜降階段2232’之步長數目不受限制。2B illustrates one of the multi-step ramp-up and ramp-down phases of a sequence in accordance with some embodiments of the present disclosure. Referring to Figure 2B, in some embodiments, the ramp-up phase 2231' and the ramp-down phase 2232' comprise multiple steps. With multiple steps, current overshoot is avoided. It should be noted that the number of steps in the ramp-up phase 2231' and the ramp-down phase 2232' is not limited.

返回參考圖1及圖2A，耦合器104經組態以將訊號產生器102耦合至IC 112。在一些實施例中，耦合器104可藉由複數個探針101耦合至IC。探針101可為一探針頭或探針封裝(未展示)之部分。探針101可電耦合至安置在IC 112上之測試墊及/或接墊。測試墊及/或接墊提供至IC之一互連結構(例如，接線)之電連接。例如，探針之一些可耦合至與IC 112之一供應端子(例如，Vdd)及接地端子(例如，Vss)相關聯之墊。其他探針可耦合至與IC 112之輸入/輸出(I/O)端子(例如，資料訊號)相關聯之墊。因而，系統100可操作以在晶圓級測試期間將電訊號(例如，應力訊號)施加至IC 112並獲得來自IC 112之回應訊號。Referring back to FIGS. 1 and 2A , coupler 104 is configured to couple signal generator 102 to IC 112 . In some embodiments, the coupler 104 may be coupled to the IC through a plurality of probes 101 . Probe 101 may be part of a probe head or probe package (not shown). Probes 101 may be electrically coupled to test pads and/or pads disposed on IC 112 . Test pads and/or pads provide electrical connection to an interconnect structure (eg, wires) of the IC. For example, some of the probes may be coupled to pads associated with one of the supply terminals (eg, Vdd) and ground terminals (eg, Vss) of the IC 112 . Other probes may be coupled to pads associated with input/output (I/O) terminals (eg, data signals) of IC 112 . Thus, system 100 is operable to apply electrical signals (eg, stress signals) to IC 112 and obtain response signals from IC 112 during wafer level testing.

模組106經組態以判定在將應力訊號220施加至IC 112之後IC 112是否符合一測試準則。可藉由模組106相對於測試準則來評估回應訊號以判定一特定IC 112是否有缺陷。Module 106 is configured to determine whether IC 112 meets a test criterion after stress signal 220 is applied to IC 112 . The response signal may be evaluated by module 106 against test criteria to determine whether a particular IC 112 is defective.

圖3A係用於在一現有動態電壓應力測試方法中測試一晶圓之一單步功率訊號之一繪示。圖3B係用於在一現有高電壓應力測試方法中測試一晶圓之一單步功率訊號之一繪示。3A is a diagram of a single step power signal for testing a wafer in a conventional dynamic voltage stress testing method. 3B is a diagram of a single step power signal for testing a wafer in a conventional high voltage stress testing method.

參考圖3A，在一單一測試週期310中施加動態電壓應力(DVS)測試之一應力訊號312。應力訊號312由一單序列訊號組成，該單序列訊號包含從接地313上升至一測試電壓311之一斜升階段，以及從測試電壓311降低至接地313之一斜降階段。DVS測試利用單序列訊號來將DUT通電至模式設置狀態，且在同一週期依測試電壓311測試DUT。測試電壓311在測試週期310期間超過正常操作電壓。在DVS測試中，發現若測試電壓311之電壓位準上升，則用於晶圓級測試之篩分速率(即，故障計數除以總裝置數目)可增加。然而，測試電壓311同時用於模式設置及缺陷測試兩者，且歸因於對模式設置之要求，測試電壓311之電壓變化量因此受限制。換言之，由於對模式設置之要求，可能無法增加測試電壓311。因此，DVS測試之篩分速率受限制。Referring to FIG. 3A , a stress signal 312 for dynamic voltage stress (DVS) testing is applied in a single test cycle 310 . The stress signal 312 consists of a single sequence signal including a ramp-up phase from ground 313 to a test voltage 311 and a ramp-down phase from the test voltage 311 to ground 313 . The DVS test uses a single sequence of signals to power up the DUT to the mode setting state, and tests the DUT at the test voltage 311 in the same cycle. The test voltage 311 exceeds the normal operating voltage during the test period 310 . In DVS testing, it was found that if the voltage level of test voltage 311 is increased, the sieving rate (ie, failure count divided by total number of devices) for wafer level testing can be increased. However, the test voltage 311 is used for both mode setting and defect testing, and the amount of voltage variation of the test voltage 311 is limited due to the requirements for the mode setting. In other words, it may not be possible to increase the test voltage 311 due to the requirement of the mode setting. Therefore, the sieving rate of the DVS test is limited.

為減輕DVS測試之問題，引入EVS測試。參考圖3B，在EVS測試中，一應力訊號328包括一單步訊號321及一單序列訊號324，其等分別在一第一週期320及一第二週期322中施加。在第一週期320中，施加從接地323上升至一正常操作電壓325之單步訊號321。在緊接於第一週期320之第二週期322中，施加從正常操作電壓325上升至一測試電壓327之單序列訊號324。在EVS測試中，發現可藉由在第二週期322期間增加測試電壓327之持續時間而增加晶圓級測試之篩分速率，而非增加測試電壓327之電壓位準。然而，為了獲得一更高篩分速率，第二週期322可比DVS測試之測試週期310 (在圖3A中展示)長得多。例如，EVS測試之第二週期322可比DVS測試之測試週期310長十倍。再者，EVS測試之篩分速率可僅等於DVS測試或甚至不如DVS測試合意。To alleviate the problems of DVS testing, EVS testing is introduced. Referring to FIG. 3B, in the EVS test, a stress signal 328 includes a single-step signal 321 and a single-sequence signal 324, which are applied in a first period 320 and a second period 322, respectively. During the first cycle 320, a single-step signal 321 is applied that rises from ground 323 to a normal operating voltage 325. In the second period 322 following the first period 320, a single sequence of signals 324 is applied that rises from the normal operating voltage 325 to a test voltage 327. In EVS testing, it was found that the sieving rate for wafer level testing could be increased by increasing the duration of the test voltage 327 during the second period 322, rather than increasing the voltage level of the test voltage 327. However, to obtain a higher sieving rate, the second period 322 may be much longer than the test period 310 of the DVS test (shown in Figure 3A). For example, the second period 322 of the EVS test may be ten times longer than the test period 310 of the DVS test. Furthermore, the sieving rate of the EVS test may be only equal to the DVS test or even less desirable than the DVS test.

根據本揭露，可緩解上述問題。According to the present disclosure, the above problems can be alleviated.

根據本揭露之一些實施例，可藉由增加應力訊號220中之電壓變化量而增加用於晶圓級測試之篩分速率，而非增加測試電壓之電壓位準或時間週期。返回參考圖1及圖2A，在本揭露之一些實施例中，訊號產生器102為CAVS提供應力訊號220，該應力訊號220具有複數個序列221A及221B，其等使電壓位準在第二週期212中在第二電壓位準222與第三電壓位準224之間波動。因此，晶圓110在第二週期212期間經歷電壓變化之多次反覆。According to some embodiments of the present disclosure, the sieving rate for wafer level testing can be increased by increasing the amount of voltage variation in the stress signal 220, rather than increasing the voltage level or time period of the test voltage. Referring back to FIGS. 1 and 2A, in some embodiments of the present disclosure, the signal generator 102 provides the CAVS with a stress signal 220 having a plurality of sequences 221A and 221B, which equalize the voltage level in the second cycle 212 fluctuates between a second voltage level 222 and a third voltage level 224 . Thus, the wafer 110 experiences multiple iterations of the voltage change during the second period 212 .

如上文描述，例如，應力訊號220包含兩個序列221A及221B，其中各序列221A及221B包含斜升階段2231及斜降階段2232。在一些實施例中，訊號產生器102提供序列221A以藉由將IC 112之電壓從第一電壓位準200 (即，IC之標稱電壓)增加至第二電壓位準222 (即，測試電壓)而為IC 112供能。當施加斜升階段2231時，可改變或切換在IC 112中之至少一個半導體裝置之一狀態(即，「0」狀態或「1」狀態)。接著，訊號產生器102繼續序列221A以藉由在斜升階段2231之後降低電壓而為IC 112供能。斜降階段2232將IC 112之電壓從第二電壓位準222降低至第三電壓位準224。當施加斜降階段2232時，可改變或切換在IC 112中之至少一個半導體裝置之狀態。As described above, for example, the stress signal 220 includes two sequences 221A and 221B, where each sequence 221A and 221B includes a ramp-up phase 2231 and a ramp-down phase 2232 . In some embodiments, the signal generator 102 provides the sequence 221A by increasing the voltage of the IC 112 from the first voltage level 200 (ie, the nominal voltage of the IC) to the second voltage level 222 (ie, the test voltage) ) to power IC 112. When the ramp-up phase 2231 is applied, one of the states (ie, the "0" state or the "1" state) of at least one semiconductor device in the IC 112 may be changed or switched. Next, the signal generator 102 continues the sequence 221A to power the IC 112 by lowering the voltage after the ramp-up phase 2231. The ramp-down stage 2232 reduces the voltage of the IC 112 from the second voltage level 222 to the third voltage level 224 . When the ramp-down stage 2232 is applied, the state of at least one semiconductor device in the IC 112 can be changed or switched.

在序列221A之後，訊號產生器102提供序列221B以為IC 112供能。訊號產生器102提供序列221B以藉由將IC 112之電壓從第三電壓位準224增加至第二電壓位準222而為IC 112供能。接著，訊號產生器102繼續序列221B以藉由將IC 112之電壓從第二電壓位準222降低至接地或第一電壓位準200而為IC 112供能。如同序列221A，在序列221B期間，可藉由斜升階段2231及斜降階段2232改變或切換IC 112中之半導體裝置之狀態。Following sequence 221A, signal generator 102 provides sequence 221B to power IC 112. Signal generator 102 provides sequence 221B to power IC 112 by increasing the voltage of IC 112 from third voltage level 224 to second voltage level 222 . Then, the signal generator 102 continues with sequence 221B to power the IC 112 by reducing the voltage of the IC 112 from the second voltage level 222 to ground or the first voltage level 200 . As with sequence 221A, during sequence 221B, the states of semiconductor devices in IC 112 may be changed or switched by ramping up phase 2231 and ramping down phase 2232.

總之，根據本揭露之一些實施例，在第二週期212期間，應力訊號220可包含複數個斜升階段2231及斜降階段2232。發現IC 112中之半導體裝置之狀態可在斜升階段2231及斜降階段2232期間藉由CAVS更容易地改變或切換。原因係場效應係局部交替的。因此，斜升階段2231及斜降階段2232之電壓差可使IC 112中之一些半導體裝置變為一短路模式作為一故障計數。歸因於多個斜升及斜降階段，可增加IC 112中之半導體裝置之調換速率。因此，可憑藉複數個序列221A及221B增加晶圓級測試之篩分速率，從而造成IC 112在第二電壓位準222與第三電壓位準224之間之電壓波動。In summary, according to some embodiments of the present disclosure, during the second period 212 , the stress signal 220 may include a plurality of ramp-up phases 2231 and ramp-down phases 2232 . It was found that the state of the semiconductor devices in IC 112 can be more easily changed or switched by CAVS during ramp-up phase 2231 and ramp-down phase 2232. The reason is that the field effects are locally alternating. Therefore, the voltage difference between ramp-up phase 2231 and ramp-down phase 2232 can cause some of the semiconductor devices in IC 112 to go into a short-circuit mode as a fault count. Due to the multiple ramp-up and ramp-down phases, the switching rate of semiconductor devices in IC 112 may be increased. Therefore, the sieving rate of wafer-level testing can be increased by means of the plurality of sequences 221A and 221B, thereby causing voltage fluctuations of the IC 112 between the second voltage level 222 and the third voltage level 224 .

再者，根據本揭露之一些實施例，可藉由將斜升階段2231之量從第一電壓位準200增加至第二電壓位準222或藉由將斜降階段2232之量從第二電壓位準222增加至第三電壓位準224而進一步增加IC 112中之半導體裝置之調換速率。換言之，可藉由增加在斜升階段2231期間或在斜降階段2232期間發生之電壓改變而進一步增加晶圓級測試之篩分速率。應理解，為了增加調換速率，將覆蓋0/1狀態組合之任何測試演算法不受限制。例如，MBIST (記憶體內置自測)測試可使用一個CKB(棋盤)及一個反向CKB測試模式。邏輯測試模式可考慮若干鏈測試之一組合。Furthermore, according to some embodiments of the present disclosure, by increasing the amount of the ramp-up phase 2231 from the first voltage level 200 to the second voltage level 222 or by increasing the amount of the ramp-down phase 2232 from the second voltage level The level 222 is increased to the third voltage level 224 to further increase the switching rate of the semiconductor devices in the IC 112 . In other words, the sieving rate for wafer-level testing can be further increased by increasing the voltage changes that occur during ramp-up phase 2231 or during ramp-down phase 2232. It should be understood that any test algorithm that will cover the 0/1 state combination is not limited in order to increase the swap rate. For example, the MBIST (Memory Built-in Self Test) test can use a CKB (chessboard) and a reverse CKB test pattern. The logic test mode may consider a combination of one of several chain tests.

相較於DVS測試，歸因於在斜升階段2231及斜降階段2232期間之更大電壓差，本揭露之測試提供增加之篩分速率。在本揭露中，測試電壓222與模式設置電壓(即，第一電壓位準200)分離。因此，本揭露中之測試電壓222可高於DVS測試之測試電壓311 (圖3A中展示)。因此，篩分速率可增加。Compared to the DVS test, the test of the present disclosure provides an increased screening rate due to the larger voltage difference during the ramp-up phase 2231 and the ramp-down phase 2232. In the present disclosure, the test voltage 222 is separated from the mode setting voltage (ie, the first voltage level 200). Therefore, the test voltage 222 in the present disclosure may be higher than the test voltage 311 (shown in FIG. 3A ) of the DVS test. Therefore, the sieving rate can be increased.

相較於EVS測試，由於本揭露之多個斜升及斜降階段可增加IC 112中之半導體裝置之調換速率，故在本揭露中，延長之週期322 (圖3中展示)可減小。因此，本揭露中之第二週期212之持續時間可減小，且習知EVS測試中之耗時問題可緩解。Compared to EVS testing, the extended period 322 (shown in FIG. 3 ) may be reduced in the present disclosure because the multiple ramp-up and ramp-down phases of the present disclosure may increase the switching rate of the semiconductor devices in IC 112 . Therefore, the duration of the second cycle 212 in the present disclosure can be reduced, and the time-consuming problem in conventional EVS testing can be alleviated.

應注意，CAVS之應用並非對本揭露之一限制。在一些實施例中，CAVS可應用於在室溫範圍(約25 oC至約27 oC)或從約0 oC至約-40 oC之溫度範圍或從約0 oC至約125 oC之溫度範圍下之晶片探測流、最終測試流或晶圓接受測試流中。 It should be noted that the application of CAVS is not a limitation of the present disclosure. In some embodiments, CAVS can be applied in the room temperature range (about 25 ° C to about 27 ° C) or in the temperature range from about 0 ° C to about -40 ° C or from about 0 ° C to about 125 ° C In the wafer probe flow, final test flow, or wafer acceptance test flow under the temperature range of C.

圖4係根據本揭露之一些實施例之用於測試一晶圓之一多步功率訊號之一繪示。訊號產生器102(圖1中展示)經組態以在第一週期210之後之一第二週期412期間產生包含一應力訊號420之CAVS。第一週期210在圖2A中描述，且為簡潔起見在此處省略。4 is a diagram of a multi-step power signal for testing a wafer in accordance with some embodiments of the present disclosure. The signal generator 102 (shown in FIG. 1 ) is configured to generate a CAVS including a stress signal 420 during a second period 412 following the first period 210 . The first cycle 210 is depicted in FIG. 2A and is omitted here for brevity.

在一些實施例中，在第二週期412期間，產生應力訊號420。應力訊號420可包含複數個序列421A、421B、421C及421D。各序列421A、421B、421C及421D包含一斜升階段4231及一斜降階段4232。各序列421A、421B、421C及421D在第二電壓位準422與第三電壓位準424之間波動。斜升階段4231或斜降階段4232之一範圍不受限制。在一些實施例中，斜升階段4231或斜降階段4232之一範圍在約0.1 V/ms與約0.3 V/ms之間。電壓從第一電壓位準200增加至第二電壓位準422，接著從第二電壓位準422降低至第三電壓位準424，接著從第三電壓位準424增加至第二電壓位準422，且最後從第二電壓位準422降低至接地或第一電壓位準200。應注意，第二電壓位準422及第三電壓位準424可分別與圖2A中之第二電壓位準222及第三電壓位準224相同。In some embodiments, during the second period 412, the stress signal 420 is generated. Stress signal 420 may include a plurality of sequences 421A, 421B, 421C, and 421D. Each sequence 421A, 421B, 421C, and 421D includes a ramp-up phase 4231 and a ramp-down phase 4232 . Each sequence 421A, 421B, 421C and 421D fluctuates between the second voltage level 422 and the third voltage level 424 . Either the ramp-up phase 4231 or the ramp-down phase 4232 is not limited in scope. In some embodiments, one of ramp up phase 4231 or ramp down phase 4232 ranges between about 0.1 V/ms and about 0.3 V/ms. The voltage increases from the first voltage level 200 to the second voltage level 422 , then decreases from the second voltage level 422 to the third voltage level 424 , and then increases from the third voltage level 424 to the second voltage level 422 , and finally drops from the second voltage level 422 to ground or the first voltage level 200 . It should be noted that the second voltage level 422 and the third voltage level 424 may be the same as the second voltage level 222 and the third voltage level 224 in FIG. 2A , respectively.

第二電壓位準422高於第一電壓位準200。第二電壓位準422之值不受限制。在一些實施例中，第二電壓位準422可比第一電壓位準200高約1.3倍，高約1.58倍，高約2.0倍，或高約3.0倍。第二電壓位準422充當測試電壓。第三電壓位準424之值不受限制。第三電壓位準424低於第二電壓位準422。在一些實施例中，第三電壓位準424可等於或小於第一電壓位準200。在一些實施例中，第二電壓位準422與第三電壓位準424之間的一電壓差大於第一電壓位準200與第二電壓位準422之間的一電壓差。在一些實施例中，第三電壓位準424可為第一電壓位準200之約0.7倍。在一些實施例中，第三電壓位準224可為第二電壓位準422之約0.9倍。The second voltage level 422 is higher than the first voltage level 200 . The value of the second voltage level 422 is not limited. In some embodiments, the second voltage level 422 may be about 1.3 times higher, about 1.58 times higher, about 2.0 times higher, or about 3.0 times higher than the first voltage level 200 . The second voltage level 422 acts as a test voltage. The value of the third voltage level 424 is not limited. The third voltage level 424 is lower than the second voltage level 422 . In some embodiments, the third voltage level 424 may be equal to or less than the first voltage level 200 . In some embodiments, a voltage difference between the second voltage level 422 and the third voltage level 424 is greater than a voltage difference between the first voltage level 200 and the second voltage level 422 . In some embodiments, the third voltage level 424 may be approximately 0.7 times the first voltage level 200 . In some embodiments, the third voltage level 224 may be approximately 0.9 times the second voltage level 422 .

如上文描述，根據本揭露之一些實施例，可藉由增加應力訊號420中之電壓變化量而增加用於晶圓級測試之篩分速率。在一些實施例中，訊號產生器102可在第二週期412期間為應力訊號420提供在第二電壓位準422與第三電壓位準424之間波動之複數個序列421A、421B、421C及421D。As described above, according to some embodiments of the present disclosure, the sieving rate for wafer-level testing may be increased by increasing the amount of voltage variation in stress signal 420 . In some embodiments, the signal generator 102 may provide the stress signal 420 with a plurality of sequences 421A, 421B, 421C, and 421D that fluctuate between the second voltage level 422 and the third voltage level 424 during the second period 412 .

如一實例，應力訊號420包含四個序列421A、421B、421C及421D，且各序列421A、421B、421C及421D包含一斜升階段4231及一斜降階段4232。在一些實施例中，訊號產生器102提供序列421A以藉由將IC 112之電壓從第一電壓位準200增加至第二電壓位準422而為IC 112 (圖1中展示)供能。當施加斜升階段4231時，可改變或切換在IC 112中之至少一個半導體裝置之一狀態。接著，訊號產生器102繼續序列421A以藉由在斜升階段4231之後降低電壓而為IC 112供能。IC 112之電壓從第二電壓位準422降低至第三電壓位準424。當施加斜降階段4232時，可改變或切換在IC 112中之至少一個半導體裝置之狀態。As an example, stress signal 420 includes four sequences 421A, 421B, 421C, and 421D, and each sequence 421A, 421B, 421C, and 421D includes a ramp-up phase 4231 and a ramp-down phase 4232 . In some embodiments, signal generator 102 provides sequence 421A to power IC 112 (shown in FIG. 1 ) by increasing the voltage of IC 112 from first voltage level 200 to second voltage level 422 . When the ramp-up phase 4231 is applied, one of the states of at least one semiconductor device in the IC 112 can be changed or switched. Next, the signal generator 102 continues the sequence 421A to power the IC 112 by lowering the voltage after the ramp-up phase 4231. The voltage of the IC 112 is reduced from the second voltage level 422 to the third voltage level 424 . When the ramp-down stage 4232 is applied, the state of at least one semiconductor device in the IC 112 can be changed or switched.

在序列421A之後，訊號產生器102提供序列421B以為IC 112供能。訊號產生器102提供序列421B以藉由將IC 112之電壓從第三電壓位準424增加至第二電壓位準422而為IC 112供能。接著，訊號產生器102繼續序列421B以藉由將IC 112之電壓從第二電壓位準422降低至第三電壓位準424而為IC 112供能。如同序列421A，在序列421B期間，可藉由斜升階段4231及斜降階段4232改變或切換IC 112中之半導體裝置之狀態。應理解，序列421B之斜降階段4232可將IC 112之電壓從第二電壓位準422降低至低於第三電壓位準424之另一電壓。在序列421B之後，訊號產生器102提供序列421C以依一類似方式為IC 112供能，且為了簡潔起見在此處省略其描述。Following sequence 421A, signal generator 102 provides sequence 421B to power IC 112. Signal generator 102 provides sequence 421B to power IC 112 by increasing the voltage of IC 112 from third voltage level 424 to second voltage level 422 . Then, the signal generator 102 continues the sequence 421B to power the IC 112 by reducing the voltage of the IC 112 from the second voltage level 422 to the third voltage level 424. As with sequence 421A, during sequence 421B, the states of semiconductor devices in IC 112 may be changed or switched by ramping up phase 4231 and ramping down phase 4232. It should be understood that the ramp-down phase 4232 of the sequence 421B may reduce the voltage of the IC 112 from the second voltage level 422 to another voltage lower than the third voltage level 424 . Following sequence 421B, signal generator 102 provides sequence 421C to power IC 112 in a similar manner, and a description thereof is omitted here for brevity.

在序列421C之後，訊號產生器102提供序列421D以為IC 112供能。訊號產生器102提供序列421D以藉由將IC 112之電壓從第三電壓位準424增加至第二電壓位準422而為IC 112供能。接著，訊號產生器102繼續序列421D以藉由將IC 112之電壓從第二電壓位準422降低至接地或第一電壓位準200而為IC 112供能。如同序列421A及421B，在序列421D期間，可藉由斜升階段4231及斜降階段4232改變或切換IC 112中之半導體裝置之狀態。Following sequence 421C, signal generator 102 provides sequence 421D to power IC 112. Signal generator 102 provides sequence 421D to power IC 112 by increasing the voltage of IC 112 from third voltage level 424 to second voltage level 422 . Then, the signal generator 102 continues the sequence 421D to power the IC 112 by reducing the voltage of the IC 112 from the second voltage level 422 to ground or the first voltage level 200 . As with sequences 421A and 421B, during sequence 421D, the state of the semiconductor devices in IC 112 may be changed or switched by ramp-up stage 4231 and ramp-down stage 4232.

總之，根據本揭露之一些實施例，在第二週期412期間，應力訊號420可包含複數個斜升階段4231及斜降階段4232。發現IC 112中之半導體裝置之狀態可在斜升階段4231及斜降階段4232期間藉由CAVS更容易地改變或切換。原因係場效應係局部交替的。因此，斜升階段4231及斜降階段4232之電壓差可使IC 112中之一些半導體裝置變為一短路模式作為一故障計數。歸因於多個斜升及斜降階段，藉由使用當前CAVS，可增加IC 112中之半導體裝置之調換速率。因此，可憑藉複數個序列421A、421B、421C及421D增加晶圓級測試之篩分速率，從而造成IC 112在第二電壓位準422與第三電壓位準424之間之電壓波動。應注意，CAVS可在短路模式故障上具有更高缺陷覆蓋，但不限於僅覆蓋短路模式故障。In summary, according to some embodiments of the present disclosure, during the second period 412 , the stress signal 420 may include a plurality of ramp-up phases 4231 and ramp-down phases 4232 . It was found that the state of the semiconductor devices in IC 112 can be more easily changed or switched by CAVS during ramp up phase 4231 and ramp down phase 4232. The reason is that the field effects are locally alternating. Therefore, the voltage difference between the ramp-up phase 4231 and the ramp-down phase 4232 can cause some of the semiconductor devices in the IC 112 to go into a short-circuit mode as a fault count. Due to the multiple ramp-up and ramp-down phases, the switching rate of semiconductor devices in IC 112 can be increased by using the current CAVS. Therefore, the sieving rate of wafer level testing can be increased by means of the plurality of sequences 421A, 421B, 421C and 421D, thereby causing voltage fluctuations of the IC 112 between the second voltage level 422 and the third voltage level 424. It should be noted that CAVS may have higher defect coverage on short-circuit mode faults, but is not limited to covering only short-circuit mode faults.

再者，根據本揭露之一些實施例，可藉由將斜升階段4231之量從第一電壓位準200增加至第二電壓位準422或藉由將斜降階段4232之量從第二電壓位準422降低至第三電壓位準424而進一步增加IC 112中之半導體裝置之調換速率。換言之，可藉由增加在斜升階段4231期間或在斜降階段4232期間發生之電壓改變而進一步增加晶圓級測試之篩分速率。Furthermore, according to some embodiments of the present disclosure, by increasing the amount of ramp-up phase 4231 from the first voltage level 200 to the second voltage level 422 or by increasing the amount of ramp-down phase 4232 from the second voltage level The level 422 is lowered to the third voltage level 424 to further increase the switching rate of the semiconductor devices in the IC 112 . In other words, the sieving rate for wafer-level testing can be further increased by increasing the voltage changes that occur during ramp-up phase 4231 or during ramp-down phase 4232.

圖5係根據本揭露之一些實施例之用於測試一晶圓之一多步功率訊號之一繪示。訊號產生器102(圖1中展示)經組態以在第一週期210之後之一第二週期512期間產生一應力訊號520。第一週期210在圖2A中描述，且為簡潔起見在此處省略。5 is a diagram of a multi-step power signal for testing a wafer, according to some embodiments of the present disclosure. The signal generator 102 (shown in FIG. 1 ) is configured to generate a stress signal 520 during a second period 512 following the first period 210 . The first cycle 210 is depicted in FIG. 2A and is omitted here for brevity.

壓力訊號520與圖2A中之應力訊號220之間的差異在於相較於應力訊號220，應力訊號520可在第二電壓位準522下具有更長持續時間。應力訊號520可具有在第二電壓位準522下具有更長持續時間之一序列521A及在第二電壓位準522下具有更短持續時間之一序列521B。應注意，應力訊號520可具有在第二電壓位準522下具有更短持續時間之超過一個序列521B。在一些實施例中，序列521B之持續時間類似於圖2A中之序列221A、221B之持續時間。The difference between the stress signal 520 and the stress signal 220 in FIG. 2A is that the stress signal 520 can have a longer duration at the second voltage level 522 than the stress signal 220 . The stress signal 520 may have a sequence 521A having a longer duration at the second voltage level 522 and a sequence 521B having a shorter duration at the second voltage level 522 . It should be noted that the stress signal 520 may have more than one sequence 521B with a shorter duration at the second voltage level 522. In some embodiments, the duration of sequence 521B is similar to the duration of sequences 221A, 221B in Figure 2A.

圖6係根據本揭露之一些實施例之用於測試一晶圓之一多步功率訊號之一繪示。訊號產生器102 (圖1中展示)經組態以在一第一週期610期間產生一第一電壓位準600之一訊號及在第一週期610之後之一第二週期612期間產生一應力訊號620。應力訊號620可包含複數個序列621A、621B及621C。序列621A、621B及621C類似於圖4中之序列421A、421B及421D，且為簡潔起見在此處省略。6 is a diagram of a multi-step power signal for testing a wafer, according to some embodiments of the present disclosure. The signal generator 102 (shown in FIG. 1 ) is configured to generate a signal at a first voltage level 600 during a first period 610 and a stress signal during a second period 612 following the first period 610 620. Stress signal 620 may include a plurality of sequences 621A, 621B, and 621C. Sequences 621A, 621B, and 621C are similar to sequences 421A, 421B, and 421D in FIG. 4, and are omitted here for brevity.

圖6中之訊號與圖2A中之訊號之間的差異在於第一電壓位準600高於第一電壓200。第一電壓位準600之值不受限制。在一些實施例中，第一電壓位準600可為第一電壓位準200之約1.1至約1.3倍。The difference between the signal in FIG. 6 and the signal in FIG. 2A is that the first voltage level 600 is higher than the first voltage 200 . The value of the first voltage level 600 is not limited. In some embodiments, the first voltage level 600 may be about 1.1 to about 1.3 times the first voltage level 200 .

圖7係繪示根據本揭露之一些實施例之一方法之一流程圖。晶圓級測試之方法700可包含操作712、714、716及718。在操作712中，提供具有在其上形成之一IC之一晶圓。在操作714中，藉由在一第一週期期間將IC之電壓升高至一第一電壓位準而為IC供能。在操作716中，將一應力訊號施加至IC。應力訊號包含在第一週期之後之一第二週期期間之多個斜升階段及斜降階段之一序列。序列使IC之電壓在一第二電壓位準與一第三電壓位準之間波動。在操作718中，在施加應力訊號之後，判定IC是否符合一測試準則。此等操作之詳細描述類似於圖1、圖2A及圖4中展示之操作的描述，且因此為簡潔起見省略。7 is a flowchart illustrating a method according to some embodiments of the present disclosure. Method 700 of wafer level testing may include operations 712 , 714 , 716 and 718 . In operation 712, a wafer having an IC formed thereon is provided. In operation 714, the IC is powered by raising the voltage of the IC to a first voltage level during a first cycle. In operation 716, a stress signal is applied to the IC. The stress signal includes a sequence of ramp-up phases and ramp-down phases during a second cycle following the first cycle. The sequence fluctuates the voltage of the IC between a second voltage level and a third voltage level. In operation 718, after applying the stress signal, it is determined whether the IC meets a test criterion. Detailed descriptions of these operations are similar to those shown in Figures 1, 2A, and 4, and are therefore omitted for brevity.

圖8係繪示根據本揭露之一些實施例之一方法之一流程圖。晶圓級測試之方法800可包含操作812、814、816及818。在操作812中，提供具有在其上形成之一IC之一晶圓。在操作814中，藉由在一第一週期期間將IC之電壓升高至一第一電壓位準而為IC供能。在操作816中，將一應力訊號施加至IC。應力訊號包含在第一週期之後之一第二週期期間之複數個斜升階段及複數個斜降階段。交替施加斜升階段及斜降階段。在操作818中，在施加應力訊號之後，判定IC是否符合一測試準則。此等操作之詳細描述類似於圖1、圖2A及圖4中展示之操作的描述，且因此為簡潔起見省略。8 is a flowchart illustrating a method according to some embodiments of the present disclosure. Method 800 of wafer level testing may include operations 812 , 814 , 816 and 818 . In operation 812, a wafer having an IC formed thereon is provided. In operation 814, the IC is powered by raising the voltage of the IC to a first voltage level during a first cycle. In operation 816, a stress signal is applied to the IC. The stress signal includes a plurality of ramp-up phases and a plurality of ramp-down phases during a second cycle following the first cycle. The ramp-up phase and the ramp-down phase are applied alternately. In operation 818, after applying the stress signal, it is determined whether the IC meets a test criterion. Detailed descriptions of these operations are similar to those shown in Figures 1, 2A, and 4, and are therefore omitted for brevity.

總之，根據本揭露之一些實施例，在多個斜升及斜降階段期間，IC中之半導體裝置之切換狀態(即，「0」狀態或「1」狀態)可藉由CAVS更容易地改變或切換。原因係場效應係局部交替的。因此，斜升階段及斜降階段之電壓差可使IC中之一些半導體裝置變為一短路模式作為一故障計數。歸因於多個斜升及斜降階段，藉由使用當前CAVS，可增加IC中之半導體裝置之調換速率。因此，可增加用於晶圓級測試之篩分速率(即，故障計數除以總裝置數目)。此外，根據本揭露之一些實施例，可憑藉斜升階段或斜降階段之更大電壓差進一步增加用於晶圓級測試之篩分速率。In summary, according to some embodiments of the present disclosure, the switching state (ie, "0" state or "1" state) of semiconductor devices in an IC can be more easily changed by CAVS during multiple ramp-up and ramp-down phases or switch. The reason is that the field effects are locally alternating. Therefore, the voltage difference between the ramp-up phase and the ramp-down phase can cause some of the semiconductor devices in the IC to go into a short-circuit mode as a fault count. Due to the multiple ramp-up and ramp-down stages, the switching rate of semiconductor devices in the IC can be increased by using the current CAVS. Thus, the sieving rate (ie, failure count divided by total device count) for wafer-level testing can be increased. Furthermore, according to some embodiments of the present disclosure, the sieving rate for wafer-level testing can be further increased by virtue of a larger voltage difference in the ramp-up phase or the ramp-down phase.

圖9係根據本揭露之一些實施例之反向器電路900之一繪示。在一些實施例中，反向器電路900可被包含在IC 112中。參考圖9，反向器電路900包含一PMOS 901及一NMOS 903。PMOS 901具有一源極、一閘極及一汲極。PMOS 901之源極連接至一輸入端子Vin (亦可被稱為一功率端子)，且經組態以接收一輸入訊號(例如，CAVS)。在一些實施例中，PMOS 901之閘極連接至另一輸入端子Vin1。在一些實施例中，PMOS 901之汲極連接至一輸出端子Vout，且經組態以回應於輸入訊號輸出一輸出訊號。NMOS 903具有一源極、一汲極及一閘極。NMOS 903之汲極經電連接至PMOS 901之汲極。NMOS 903之源極經連接至接地。NMOS 903之閘極經電連接至PMOS 901之閘極。FIG. 9 is a diagram of one of an inverter circuit 900 according to some embodiments of the present disclosure. In some embodiments, inverter circuit 900 may be included in IC 112 . Referring to FIG. 9 , the inverter circuit 900 includes a PMOS 901 and an NMOS 903 . The PMOS 901 has a source, a gate and a drain. The source of the PMOS 901 is connected to an input terminal Vin (also referred to as a power terminal) and is configured to receive an input signal (eg, CAVS). In some embodiments, the gate of PMOS 901 is connected to another input terminal Vin1. In some embodiments, the drain of PMOS 901 is connected to an output terminal Vout, and is configured to output an output signal in response to an input signal. The NMOS 903 has a source, a drain and a gate. The drain of NMOS 903 is electrically connected to the drain of PMOS 901 . The source of NMOS 903 is connected to ground. The gate of NMOS 903 is electrically connected to the gate of PMOS 901 .

在一些實施例中，在輸出端子Vout處監測回應於輸入訊號(例如，應力訊號)之輸出訊號，以判定反向器電路900是否正常操作。例如，在電壓應力測試期間，反向器電路900之輸入端子Vin1 (PMOS 901及NMOS 903之各者之閘極)可連接至接地，且將一應力訊號(例如，CAVS)施加至反向器電路900之輸入端子Vin (例如，PMOS 901之源極)。在反向器電路900正常操作的情況中，輸出端子Vout處之輸出訊號實質上緊跟輸入端子Vin處之應力訊號，此係因為PMOS 901及NMOS 903之各者之閘極連接至接地(其將關閉NMOS 903)。例如，反向器電路900之輸出訊號將與應力訊號邏輯上相同。在反向器電路900異常操作之情況中，反向器電路900之輸出訊號可部分地或完全不同於應力訊號。例如，輸出訊號不緊跟施加至輸入端子Vin之應力訊號。In some embodiments, an output signal in response to an input signal (eg, a stress signal) is monitored at the output terminal Vout to determine whether the inverter circuit 900 is operating normally. For example, during a voltage stress test, the input terminal Vin1 of inverter circuit 900 (the gate of each of PMOS 901 and NMOS 903 ) can be connected to ground and a stress signal (eg, CAVS) applied to the inverter The input terminal Vin of the circuit 900 (eg, the source of the PMOS 901). Under normal operation of the inverter circuit 900, the output signal at the output terminal Vout substantially follows the stress signal at the input terminal Vin because the gates of each of the PMOS 901 and NMOS 903 are connected to ground (which will turn off NMOS 903). For example, the output signal of inverter circuit 900 will be logically the same as the stress signal. In the event of abnormal operation of the inverter circuit 900, the output signal of the inverter circuit 900 may be partially or completely different from the stress signal. For example, the output signal does not follow the stress signal applied to the input terminal Vin.

圖10繪示根據本揭露之一些實施例之如圖9中展示之施加至反向器電路900之輸入端子Vin之一輸入訊號1002及在反向器電路900之輸出端子Vout處獲得之一輸出訊號1004之一時序圖。在一些實施例中，輸入訊號1002與如圖2A中展示之訊號相同或類似，且為了簡潔起見，在此處省略對輸入訊號1002之一些描述。在其他實施例中，如圖2B、圖3A、圖3B、圖4、圖5及圖6之任一者所展示之訊號可用作用於反向器電路900之輸入訊號1002。10 illustrates an input signal 1002 as shown in FIG. 9 applied to the input terminal Vin of the inverter circuit 900 and an output obtained at the output terminal Vout of the inverter circuit 900 in accordance with some embodiments of the present disclosure A timing diagram of signal 1004. In some embodiments, the input signal 1002 is the same as or similar to the signal shown in FIG. 2A, and some description of the input signal 1002 is omitted here for brevity. In other embodiments, the signals shown in any of FIGS. 2B , 3A, 3B, 4 , 5 and 6 may be used as the input signal 1002 for the inverter circuit 900 .

如圖10中展示，回應於輸入訊號1002之第一週期210及第二週期212，輸出訊號1004對應地包含一第一週期1010及一第二週期1012。在一些實施例中，回應於第一週期210期間之輸入訊號1002之第一電壓位準200，輸出訊號1004在一第一週期1010期間上升至一第一電壓位準1020，該輸出訊號1004經監測與輸入訊號1002邏輯上相同。在第一週期1010之後之第二週期1012期間，輸出訊號1004與輸入訊號1002部分不同。例如，輸入訊號1002與輸出訊號1004之間的邏輯差出現在輸入訊號1002之應力訊號220之上升緣(例如，序列221A)處。回應於輸入訊號1002之應力訊號220之序列221A，輸出訊號1004從第一電壓位準1020斜降至一更低之電壓位準1026。在更低電壓位準1026之持續時間之後，輸出訊號1004斜升至一第二電壓位準1022。第二電壓位準1022與輸入訊號1002之第二電壓位準222邏輯上相同。回應於第一脈衝221A之斜降階段，輸出訊號1004斜降至一第三電壓位準1024。第三電壓位準1024與輸入訊號1002之第三電壓位準224邏輯上相同。接著，輸出訊號1004與第二週期之剩餘部分中之輸入訊號1002邏輯上相同。As shown in FIG. 10, in response to the first period 210 and the second period 212 of the input signal 1002, the output signal 1004 includes a first period 1010 and a second period 1012, respectively. In some embodiments, in response to the first voltage level 200 of the input signal 1002 during the first period 210, the output signal 1004 rises to a first voltage level 1020 during the first period 1010, and the output signal 1004 is Monitoring and input signal 1002 are logically the same. During the second period 1012 following the first period 1010, the output signal 1004 is partially different from the input signal 1002. For example, the logic difference between input signal 1002 and output signal 1004 occurs at the rising edge of stress signal 220 of input signal 1002 (eg, sequence 221A). The output signal 1004 ramps from a first voltage level 1020 to a lower voltage level 1026 in response to the sequence 221A of the stress signal 220 of the input signal 1002 . After the duration of the lower voltage level 1026, the output signal 1004 ramps up to a second voltage level 1022. The second voltage level 1022 is logically the same as the second voltage level 222 of the input signal 1002 . In response to the ramp-down phase of the first pulse 221A, the output signal 1004 ramps down to a third voltage level 1024 . The third voltage level 1024 is logically the same as the third voltage level 224 of the input signal 1002 . Then, the output signal 1004 is logically the same as the input signal 1002 in the remainder of the second cycle.

在一些實施例中，輸入訊號1002與輸出訊號1004之間的如圖10中展示之邏輯差可指示反向器電路900中之一異常裝置結構(或一非自然洩漏或損壞)。歸因於施加至IC之應力訊號，可出現此異常裝置結構(或一非自然洩漏或損壞)。在一些實施例中，輸入訊號1002與輸出訊號1004之間的邏輯差可指示由程序偏差或不足裕度引起之半導體結構(例如，PMOS 901或NMOS 903)之閘極與汲極之間的漏電流或損壞。可藉由監測輸入訊號1002與輸出訊號1004之間的邏輯差而偵測異常裝置結構，包含但不限於閘極、源極、汲極、接點、層間介電質(ILD)、鰭片、金屬閘極、磊晶(EPI)等。非自然損壞可包含一半導體裝置之一金屬閘極之一輪廓變形、一半導體裝置之一接點變形或一半導體裝置之一介電質中之一雜質。在一些實施例中，如圖10中展示之輸入訊號1002 (例如，應力訊號)可施加至任何其他邏輯電路，以基於輸出訊號檢查邏輯電路中是否存在任何缺陷。In some embodiments, a logical difference between the input signal 1002 and the output signal 1004 as shown in FIG. 10 may indicate an abnormal device structure (or an unnatural leakage or damage) in the inverter circuit 900 . This abnormal device structure (or an unnatural leak or damage) can occur due to the stress signal applied to the IC. In some embodiments, the logic difference between the input signal 1002 and the output signal 1004 may be indicative of leakage between the gate and drain of the semiconductor structure (eg, PMOS 901 or NMOS 903 ) caused by program variation or insufficient margin current or damage. Abnormal device structures, including but not limited to gates, sources, drains, contacts, interlayer dielectrics (ILDs), fins, Metal gate, epitaxy (EPI), etc. Unnatural damage can include a profile deformation of a metal gate of a semiconductor device, a contact deformation of a semiconductor device, or an impurity in a dielectric of a semiconductor device. In some embodiments, an input signal 1002 (eg, a stress signal) as shown in FIG. 10 can be applied to any other logic circuit to check for any defects in the logic circuit based on the output signal.

圖11A繪示根據本揭露之一些實施例之一半導體結構11A。在一些實施例中，半導體結構11A係一電晶體之部分。例如，半導體結構11A可為PMOS 901或NMOS 903之部分，如圖9中展示。半導體結構11A包含一基板110a、一閘極110b、一閘極介電質110c、一間隔件110d、一接點110e及一磊晶110f。FIG. 11A illustrates a semiconductor structure 11A according to some embodiments of the present disclosure. In some embodiments, the semiconductor structure 11A is part of a transistor. For example, semiconductor structure 11A may be part of PMOS 901 or NMOS 903 , as shown in FIG. 9 . The semiconductor structure 11A includes a substrate 110a, a gate 110b, a gate dielectric 110c, a spacer 110d, a contact 110e, and an epitaxial 110f.

參考圖9之電路，磊晶110f可為PMOS 901或NMOS 903之任一者之源極。在一些實施例中，磊晶110f可為PMOS 901或NMOS 903之任一者之汲極。在一些實施例中，接點110e可為連接至輸入端子Vin之PMOS 901之一源極接點。在一些實施例中，接點110e可為連接至輸出端子Vout之PMOS 901之一汲極接點。在一些實施例中，接點110e可為連接至PMOS 901之汲極之NMOS 903之一汲極接點。在一些實施例中，接點110e可為連接至接地之NMOS 903之一源極接點。閘極110b可為連接另一輸入端子Vin1之PMOS 901或NMOS 903之閘極。Referring to the circuit of FIG. 9 , the epitaxy 110f may be the source of either the PMOS 901 or the NMOS 903 . In some embodiments, epitaxial 110f may be the drain of either PMOS 901 or NMOS 903 . In some embodiments, the contact 110e may be a source contact of the PMOS 901 connected to the input terminal Vin. In some embodiments, the contact 110e may be a drain contact of the PMOS 901 connected to the output terminal Vout. In some embodiments, contact 110e may be a drain contact of NMOS 903 connected to the drain of PMOS 901 . In some embodiments, contact 110e may be a source contact of NMOS 903 connected to ground. The gate 110b may be the gate of the PMOS 901 or the NMOS 903 connected to the other input terminal Vin1.

閘極介電質110c安置於基板110a上。閘極110b安置於閘極介電質110c上。間隔件110d安置於基板110a上。間隔件110d安置於閘極110b旁邊。間隔件110d可接觸閘極110b及閘極介電質110c。接點110e安置於基板110a上。接點110e安置於間隔件110d旁邊。接點110e與間隔件110d實體間隔開。例如，接點110e與間隔件110d之間存在一間隙。在一些實施例中，接點110e與閘極110b之間的一距離D1小於3 nm。The gate dielectric 110c is disposed on the substrate 110a. Gate 110b is disposed on gate dielectric 110c. The spacer 110d is disposed on the substrate 110a. The spacer 110d is disposed beside the gate electrode 110b. Spacer 110d may contact gate 110b and gate dielectric 110c. The contacts 110e are disposed on the substrate 110a. The contact 110e is positioned next to the spacer 110d. Contact 110e is physically spaced from spacer 110d. For example, a gap exists between the contact 110e and the spacer 110d. In some embodiments, a distance D1 between the contact 110e and the gate 110b is less than 3 nm.

若電晶體之接點與閘極之間的距離小於3 nm，則難以使用現有技術對該電晶體執行一電壓應力測試。由於半導體裝置之尺寸變得更小，故難以測試此類結構。藉由使用本揭露之方法，執行電壓應力測試之結果之逃脫缺陷率將較低。換言之，憑藉本揭露之方法，測試具有小於3 nm之接點及閘極之一電晶體係更準確且可靠的。在一些實施例中，藉由使用如圖2A中展示之應力訊號及監測如圖9及圖10中展示之輸出訊號，可對具有小於3 nm之一閘極至接點間距之任何電晶體執行電壓應力測試。If the distance between the contact and the gate of the transistor is less than 3 nm, it is difficult to perform a voltage stress test on the transistor using the prior art. As the size of semiconductor devices becomes smaller, it is difficult to test such structures. By using the method of the present disclosure, the escape defect rate as a result of performing the voltage stress test will be lower. In other words, with the method of the present disclosure, testing a transistor system with contacts and gates smaller than 3 nm is more accurate and reliable. In some embodiments, by using the stress signal as shown in Figure 2A and monitoring the output signal as shown in Figures 9 and 10, it can be performed on any transistor with a gate-to-contact spacing of less than 3 nm Voltage stress test.

圖11B繪示根據本揭露之一些實施例之一半導體結構11B。在一些實施例中，半導體結構11B係一電晶體之部分。例如，半導體結構11B可為PMOS 901或NMOS 903之部分，如圖9中展示。半導體結構11B包含一基板111a、一閘極111b、一閘極介電質111c、一間隔件111d、一接點111e及一磊晶111f。FIG. 11B illustrates a semiconductor structure 11B according to some embodiments of the present disclosure. In some embodiments, the semiconductor structure 11B is part of a transistor. For example, semiconductor structure 11B may be part of PMOS 901 or NMOS 903 , as shown in FIG. 9 . The semiconductor structure 11B includes a substrate 111a, a gate 111b, a gate dielectric 111c, a spacer 111d, a contact 111e and an epitaxial 111f.

參考圖9之電路，磊晶111f可為PMOS 901或NMOS 903之任一者之源極。在一些實施例中，磊晶111f可為PMOS 901或NMOS 903之任一者之汲極。在一些實施例中，接點111e可為連接至輸入端子Vin之PMOS 901之一源極接點。在一些實施例中，接點111e可為連接至輸出端子Vout之PMOS 901之一汲極接點。在一些實施例中，接點111e可為連接至PMOS 901之汲極之NMOS 903之一汲極接點。在一些實施例中，接點111e可為連接至接地之NMOS 903之一源極接點。閘極111b可為連接另一輸入端子Vin1之PMOS 901或NMOS 903之閘極。Referring to the circuit of FIG. 9 , the epitaxy 111f may be the source of either the PMOS 901 or the NMOS 903 . In some embodiments, epitaxial 111f may be the drain of either PMOS 901 or NMOS 903 . In some embodiments, the contact 111e may be a source contact of the PMOS 901 connected to the input terminal Vin. In some embodiments, the contact 111e may be a drain contact of the PMOS 901 connected to the output terminal Vout. In some embodiments, the contact 111e may be a drain contact of the NMOS 903 connected to the drain of the PMOS 901 . In some embodiments, the contact 111e may be a source contact of the NMOS 903 connected to ground. The gate 111b may be the gate of the PMOS 901 or the NMOS 903 connected to the other input terminal Vin1.

基板111a具有一表面111s。閘極介電質111c安置於基板111a之表面111s上。閘極111b安置於閘極介電質111c上。間隔件111d安置於基板111a之表面111s上。間隔件111d安置於閘極111b旁邊。間隔件111d可接觸閘極111b及閘極介電質111c。接點111e安置於基板111a上。接點111e安置於間隔件111d旁邊。接點111e與間隔件111d實體間隔開。例如，接點111e與間隔件111d之間存在一間隙。磊晶111f安置於基板111a內。磊晶111f在接點下方。在一些實施例中，基板111a之表面111s上之閘極111b之一投影線與基板111a之表面111s上之磊晶111f之一投影線之間的一最小距離D2小於1 nm。The substrate 111a has a surface 111s. The gate dielectric 111c is disposed on the surface 111s of the substrate 111a. The gate 111b is disposed on the gate dielectric 111c. The spacer 111d is disposed on the surface 111s of the substrate 111a. The spacer 111d is disposed beside the gate electrode 111b. The spacer 111d may contact the gate 111b and the gate dielectric 111c. The contacts 111e are disposed on the substrate 111a. The contact point 111e is arranged beside the spacer 111d. The contact 111e is physically spaced from the spacer 111d. For example, a gap exists between the contact point 111e and the spacer 111d. The epitaxy 111f is disposed in the substrate 111a. The epitaxy 111f is below the contacts. In some embodiments, a minimum distance D2 between a projection line of the gate electrode 111b on the surface 111s of the substrate 111a and a projection line of the epitaxial layer 111f on the surface 111s of the substrate 111a is less than 1 nm.

若基板上之閘極之一投影線與基板上之磊晶之一投影線之間的最小距離小於1 nm，則難以使用現有技術對該電晶體執行一電壓應力測試。由於半導體裝置之尺寸變得更小，故難以測試此類結構。藉由使用本揭露之方法，使用現有技術執行電壓應力測試之結果之逃脫缺陷率將較低。換言之，憑藉本揭露之方法，測試具有小於1 nm之基板上之閘極之一投影線及基板上之磊晶之一投影線之一電晶體係更準確且可靠的。藉由使用如圖2A中展示之應力訊號及監測如圖9及圖10中展示之輸出訊號，可對具有小於1 nm之一閘極至磊晶間距之任何電晶體執行電壓應力測試。If the minimum distance between a projected line of the gate on the substrate and a projected line of the epitaxial on the substrate is less than 1 nm, it is difficult to perform a voltage stress test on the transistor using the prior art. As the size of semiconductor devices becomes smaller, it is difficult to test such structures. By using the method of the present disclosure, the escape defect rate will be lower as a result of performing a voltage stress test using the prior art. In other words, by virtue of the method of the present disclosure, it is more accurate and reliable to test a transistor system having a projection line of the gate on the substrate and a projection line of the epitaxial on the substrate smaller than 1 nm. By using the stress signal as shown in Figure 2A and monitoring the output signal as shown in Figures 9 and 10, voltage stress testing can be performed on any transistor with a gate to epitaxial spacing of less than 1 nm.

根據一些實施例，提供一種方法。該方法包含：提供具有一輸入端子及一輸出端子之一受測試裝置(DUT)；在一第一週期期間將具有一第一電壓位準之一電壓施加至DUT之輸入端子；在第一週期後之一第二週期期間將一應力訊號施加至DUT之輸入端子；回應於DUT之輸出端子處之應力訊號獲得一輸出訊號；及將輸出訊號與應力訊號進行比較。應力訊號包含複數個序列，各序列具有一斜升階段及一斜降階段。應力訊號具有一第二電壓位準及一第三電壓位準。According to some embodiments, a method is provided. The method includes: providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first cycle; A stress signal is applied to the input terminal of the DUT during the latter second cycle; an output signal is obtained in response to the stress signal at the output terminal of the DUT; and the output signal is compared with the stress signal. The stress signal includes a plurality of sequences, and each sequence has a ramp-up phase and a ramp-down phase. The stress signal has a second voltage level and a third voltage level.

根據其他實施例，提供一種方法。該方法包含：提供具有一輸入端子及一輸出端子之一受測試裝置(DUT)；將一應力訊號施加至DUT之輸入端子；回應於DUT之輸出端子處之應力訊號獲得一輸出訊號；將輸出訊號與應力訊號進行比較；及基於輸出訊號與應力訊號之間的該比較之一結果判定DUT是否具有一異常結構。輸出訊號包含複數個序列，各序列具有一斜升階段及一斜降階段。輸出訊號具有一第一電壓位準及一第二電壓位準。According to other embodiments, a method is provided. The method includes: providing a device under test (DUT) having an input terminal and an output terminal; applying a stress signal to the input terminal of the DUT; obtaining an output signal in response to the stress signal at the output terminal of the DUT; comparing the signal with the stress signal; and determining whether the DUT has an abnormal structure based on a result of the comparison between the output signal and the stress signal. The output signal includes a plurality of sequences, and each sequence has a ramp-up phase and a ramp-down phase. The output signal has a first voltage level and a second voltage level.

根據其他實施例，提供一種半導體裝置。半導體裝置包含經組態以接收一應力訊號之一第一輸入端子及經組態以回應於該應力訊號產生一輸出訊號之一輸出端子。半導體裝置進一步包含一基板、一閘極及一接點。閘極安置於基板上。接點安置於基板上及閘極旁邊。接點經電連接至第一輸入端子或輸出端子。閘極與接點之間的一距離小於3奈米(nm)。According to other embodiments, a semiconductor device is provided. The semiconductor device includes a first input terminal configured to receive a stress signal and an output terminal configured to generate an output signal in response to the stress signal. The semiconductor device further includes a substrate, a gate and a contact. The gate is disposed on the substrate. The contacts are arranged on the substrate and next to the gate. The contacts are electrically connected to the first input terminal or the output terminal. A distance between the gate and the contact is less than 3 nanometers (nm).

前文概述若干實施例之構件，使得熟習此項技術者可更佳地理解本揭露之態樣。熟習此項技術者應瞭解，其等可容易地使用本揭露作為設計或修改用於實行本文中介紹之實施例之相同目的及/或達成相同優點之其他程序及結構之一基礎。熟習此項技術者亦應認知，此等等效構造不脫離本揭露之精神及範疇，且其等可在不脫離本揭露之精神及範疇的情況下在本文中進行各種改變、替換及更改。The foregoing outlines the components of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other programs and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

11A:半導體結構 11B:半導體結構 100:系統 101:探針 102:訊號產生器 104:耦合器 106:模組 110:晶圓 110a:基板 110b:閘極 110c:閘極介電質 110d:間隔件 110e:接點 110f:磊晶 111a:基板 111b:閘極 111c:閘極介電質 111d:間隔件 111e:接點 111f:磊晶 111s:表面 112:積體電路(IC) 200:第一電壓位準 210:第一週期 212:第二週期 220:應力訊號 221A:序列 221B:序列 222:第二電壓位準/測試電壓 224:第三電壓位準 310:測試週期 311:測試電壓 312:應力訊號 313:接地 320:第一週期 321:單步訊號 322:第二週期 323:接地 324:單序列訊號 325:正常操作電壓 327:測試電壓 328:應力訊號 412:第二週期 420:應力訊號 421A:序列 421B:序列 421C:序列 421D:序列 422:第二電壓位準 424:第三電壓位準 512:第二週期 520:應力訊號 521A:序列 521B:序列 522:第二電壓位準 600:第一電壓位準 610:第一週期 612:第二週期 620:應力訊號 621A:序列 621B:序列 621C:序列 700:方法 712:操作 714:操作 716:操作 718:操作 800:方法 812:操作 814:操作 816:操作 818:操作 900:反向器電路 901:PMOS 903:NMOS 1002:輸入訊號 1004:輸出訊號 1010:第一週期 1012:第二週期 1020:第一電壓位準 1022:第二電壓位準 1024:第三電壓位準 1026:電壓位準 2231:斜升階段 2231’:斜升階段 2232:斜降階段 2232’:斜降階段 4231:斜升階段 4232:斜降階段 D1:距離 D2:距離 11A: Semiconductor Structure 11B: Semiconductor Structure 100: System 101: Probe 102: Signal Generator 104: Coupler 106: Mods 110: Wafer 110a: Substrate 110b: Gate 110c: gate dielectric 110d: Spacer 110e: Contact 110f: Epitaxy 111a: Substrate 111b: gate 111c: Gate dielectric 111d: Spacer 111e: Contact 111f: Epitaxy 111s: Surface 112: Integrated Circuits (ICs) 200: The first voltage level 210: First cycle 212: Second cycle 220: Stress Signal 221A: Sequence 221B: Sequence 222: Second voltage level/test voltage 224: the third voltage level 310: Test Cycle 311: Test voltage 312: Stress Signal 313: Ground 320: first cycle 321: Single step signal 322: Second cycle 323: Ground 324: single sequence signal 325: normal operating voltage 327: Test voltage 328: Stress Signal 412: Second cycle 420: Stress Signal 421A: Sequence 421B: Sequence 421C: Sequence 421D: Sequence 422: The second voltage level 424: The third voltage level 512: Second cycle 520: Stress Signal 521A: Sequence 521B: Sequence 522: The second voltage level 600: The first voltage level 610: first cycle 612: Second cycle 620: Stress Signal 621A: Sequence 621B: Sequence 621C: Sequence 700: Method 712: Operation 714: Operation 716: Operation 718: Operation 800: Method 812: Operation 814: Operation 816: Operation 818: Operation 900: Inverter circuit 901: PMOS 903: NMOS 1002: input signal 1004: output signal 1010: first cycle 1012: Second cycle 1020: first voltage level 1022: The second voltage level 1024: The third voltage level 1026: Voltage level 2231: Ramp phase 2231’: Ramp up phase 2232: Ramp down phase 2232’: ramp down stage 4231: Ramp up phase 4232: Ramp down phase D1: Distance D2: Distance

當結合隨附圖式閱讀時自下列實施方式最佳地理解本揭露之態樣。應注意，根據行業中之標準實踐，各種構件不按比例繪製。實際上，為清晰論述，各種構件之尺寸可任意增大或減小。 Aspects of the present disclosure are best understood from the following description when read in conjunction with the accompanying drawings. It should be noted that in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

圖1係根據本揭露之一些實施例之用於測試半導體裝置之一系統之一圖解視圖。1 is a diagrammatic view of a system for testing semiconductor devices in accordance with some embodiments of the present disclosure.

圖2A係根據本揭露之一些實施例之用於測試一晶圓之一多步功率訊號之一繪示。2A is a diagram of a multi-step power signal for testing a wafer, according to some embodiments of the present disclosure.

圖2B係根據本揭露之一些實施例之序列之一多步斜升及斜降階段之一繪示。2B illustrates one of the multi-step ramp-up and ramp-down phases of a sequence in accordance with some embodiments of the present disclosure.

圖3A係用於在習知動態電壓應力測試方法中測試一晶圓之一單步功率訊號之一繪示。3A is a diagram of a single step power signal for testing a wafer in a conventional dynamic voltage stress testing method.

圖3B係用於在習知高電壓應力測試方法中測試一晶圓之一單步功率訊號之一繪示。3B is a diagram of a single step power signal for testing a wafer in a conventional high voltage stress testing method.

圖4係根據本揭露之一些實施例之用於測試一晶圓之一多步功率訊號之一繪示。4 is a diagram of a multi-step power signal for testing a wafer in accordance with some embodiments of the present disclosure.

圖5係根據本揭露之一些實施例之用於測試一晶圓之一多步功率訊號之一繪示。5 is a diagram of a multi-step power signal for testing a wafer, according to some embodiments of the present disclosure.

圖6係根據本揭露之一些實施例之用於測試一晶圓之一多步功率訊號之一繪示。6 is a diagram of a multi-step power signal for testing a wafer, according to some embodiments of the present disclosure.

圖7係繪示根據本揭露之一些實施例之一方法之一流程圖。7 is a flowchart illustrating a method according to some embodiments of the present disclosure.

圖8係繪示根據本揭露之一些實施例之一方法之一流程圖。8 is a flowchart illustrating a method according to some embodiments of the present disclosure.

圖9係根據本揭露之一些實施例之一反向器電路之一繪示。9 is a diagram of one of an inverter circuit according to some embodiments of the present disclosure.

圖10係繪示根據圖9中之實施例之輸入及輸出訊號之波形之一時序圖。FIG. 10 is a timing diagram showing the waveforms of input and output signals according to the embodiment of FIG. 9 .

圖11A繪示根據本揭露之一些實施例之一半導體結構。11A illustrates a semiconductor structure according to some embodiments of the present disclosure.

圖11B繪示根據本揭露之一些實施例之一半導體結構。FIG. 11B illustrates a semiconductor structure according to some embodiments of the present disclosure.

100:系統 100: System

101:探針 101: Probe

102:訊號產生器 102: Signal Generator

104:耦合器 104: Coupler

106:模組 106: Mods

110:晶圓 110: Wafer

112:積體電路(IC) 112: Integrated Circuits (ICs)

Claims (20)

一種方法，其包括： 提供具有一輸入端子及一輸出端子之一受測試裝置(DUT)； 在一第一週期期間將具有一第一電壓位準之一電壓施加至該DUT之該輸入端子； 在該第一週期之後之一第二個週期期間將一應力訊號施加至該DUT之該輸入端子，該應力訊號包含複數個序列，該序列之各者具有一斜升階段及一斜降階段，其中該應力訊號具有一第二電壓位準及一第三電壓位準； 回應於該DUT之該輸出端子處之該應力訊號獲得一輸出訊號；及 將該輸出訊號與該應力訊號進行比較。 A method comprising: providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first cycle; applying a stress signal to the input terminal of the DUT during a second cycle after the first cycle, the stress signal comprising a plurality of sequences, each of the sequences having a ramp-up phase and a ramp-down phase, wherein the stress signal has a second voltage level and a third voltage level; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and The output signal is compared with the stress signal. 如請求項1之方法，其進一步包括基於該輸出訊號與該應力訊號之間的該比較之一結果判定該DUT是否具有一異常結構。The method of claim 1, further comprising determining whether the DUT has an abnormal structure based on a result of the comparison between the output signal and the stress signal. 如請求項2之方法，其中若該輸出訊號與在一相同時域中之該應力訊號邏輯上不同，則該DUT經判定為具有該異常結構。The method of claim 2, wherein the DUT is determined to have the abnormal structure if the output signal is logically different from the stress signal in the same time domain. 如請求項3之方法，其中該輸出訊號與在該相同時域中之該應力訊號邏輯上部分不同。The method of claim 3, wherein the output signal is logically partially different from the stress signal in the same time domain. 如請求項3之方法，其中該輸出訊號與在該相同時域中之該應力訊號邏輯上完全不同。The method of claim 3, wherein the output signal is logically distinct from the stress signal in the same time domain. 如請求項1之方法，其中該第二電壓位準比該第一電壓位準高約1.3至約3.0倍。The method of claim 1, wherein the second voltage level is about 1.3 to about 3.0 times higher than the first voltage level. 如請求項1之方法，其中該第三電壓位準為該第一電壓位準之約0.7倍至該第二電壓位準之約0.9倍。The method of claim 1, wherein the third voltage level is about 0.7 times the first voltage level to about 0.9 times the second voltage level. 如請求項1之方法，其中該DUT包括： 一PMOS，其具有連接至該DUT之該輸入端子之一源極、一閘極及連接至該DUT之該輸出端子之一汲極；及 一NMOS，其具有連接至接地之一源極、連接至該PMOS之該閘極之一閘極及連接至該DUT之該輸出端子之一汲極。 The method of claim 1, wherein the DUT comprises: a PMOS having a source connected to the input terminal of the DUT, a gate and a drain connected to the output terminal of the DUT; and An NMOS having a source connected to ground, a gate connected to the gate of the PMOS, and a drain connected to the output terminal of the DUT. 一種方法，其包括： 提供具有一輸入端子及一輸出端子之一受測試裝置(DUT)； 將一應力訊號施加至該DUT之該輸入端子； 回應於在該DUT之該輸出端子處之該應力訊號獲得一輸出訊號，該輸出訊號包含複數個序列，該序列之各者具有一斜升階段及一斜降階段，其中該輸出訊號具有一第一電壓位準及一第二電壓位準； 將該輸出訊號與該應力訊號進行比較；及 基於該輸出訊號與該應力訊號之間的該比較之一結果判定該DUT是否具有一異常結構。 A method comprising: providing a device under test (DUT) having an input terminal and an output terminal; applying a stress signal to the input terminal of the DUT; An output signal is obtained in response to the stress signal at the output terminal of the DUT, the output signal comprising a plurality of sequences, each of the sequences having a ramp-up phase and a ramp-down phase, wherein the output signal has a first a voltage level and a second voltage level; comparing the output signal with the stress signal; and Whether the DUT has an abnormal structure is determined based on a result of the comparison between the output signal and the stress signal. 如請求項9之方法，其進一步包括在施加該應力訊號之前將具有一第三電壓位準之一電壓施加至該DUT之該輸入端子。The method of claim 9, further comprising applying a voltage having a third voltage level to the input terminal of the DUT prior to applying the stress signal. 如請求項10之方法，其中該第一電壓位準比該第三電壓位準高約1.3至約3.0倍。The method of claim 10, wherein the first voltage level is about 1.3 to about 3.0 times higher than the third voltage level. 如請求項10之方法，其中該第二電壓位準為該第三電壓位準之約0.7倍至該第一電壓位準之約0.9倍。The method of claim 10, wherein the second voltage level is about 0.7 times the third voltage level to about 0.9 times the first voltage level. 如請求項9之方法，其中若該輸出訊號與在一相同時域中之該應力訊號邏輯上不同，則該DUT經判定為具有該異常結構。The method of claim 9, wherein the DUT is determined to have the abnormal structure if the output signal is logically different from the stress signal in the same time domain. 如請求項9之方法，其中該DUT包括： 一PMOS，其具有連接至該DUT之該輸入端子之一源極、一閘極及連接至該DUT之該輸出端子之一汲極；及 一NMOS，其具有連接至接地之一源極、連接至該PMOS之該閘極之一閘極及連接至該DUT之該輸出端子之一汲極。 The method of claim 9, wherein the DUT comprises: a PMOS having a source connected to the input terminal of the DUT, a gate and a drain connected to the output terminal of the DUT; and An NMOS having a source connected to ground, a gate connected to the gate of the PMOS, and a drain connected to the output terminal of the DUT. 一種半導體裝置，其包括： 一第一輸入端子，其經組態以接收一應力訊號； 一輸出端子，其經組態以回應於該應力訊號產生一輸出訊號； 一基板； 一閘極，其安置於該基板上；及 一接點，其安置於該基板上及該閘極旁邊，其中該接點經電連接至該第一輸入端子或該輸出端子，且其中該閘極與該接點之間的一距離小於3奈米(nm)。 A semiconductor device comprising: a first input terminal configured to receive a stress signal; an output terminal configured to generate an output signal in response to the stress signal; a substrate; a gate disposed on the substrate; and a contact, disposed on the substrate and beside the gate, wherein the contact is electrically connected to the first input terminal or the output terminal, and wherein a distance between the gate and the contact is less than 3 nanometer (nm). 如請求項15之半導體裝置，其進一步包括：安置於該基板內且在該接點下方之一磊晶，其中該基板上之該閘極之一投影線與該基板上之該磊晶之一投影線之間的一最小距離小於1 nm。The semiconductor device of claim 15, further comprising: an epitaxial disposed in the substrate and below the contact, wherein a projection line of the gate on the substrate and one of the epitaxy on the substrate A minimum distance between projection lines is less than 1 nm. 如請求項15之半導體裝置，其進一步包括： 一間隔件，其安置於該基板上且安置於該閘極與該接點之間；及 一閘極介電質，其安置於該閘極與該基板之間。 The semiconductor device of claim 15, further comprising: a spacer disposed on the substrate between the gate and the contact; and A gate dielectric is disposed between the gate and the substrate. 如請求項15之半導體裝置，其中回應於該應力訊號之該輸出訊號包含複數個序列，該序列之各者具有一斜升階段及一斜降階段，其中該輸出訊號具有一第一電壓位準及一第二電壓位準。The semiconductor device of claim 15, wherein the output signal responsive to the stress signal comprises a plurality of sequences, each of the sequences having a ramp-up phase and a ramp-down phase, wherein the output signal has a first voltage level and a second voltage level. 如請求項18之半導體裝置，其中該半導體裝置之該第一輸入端子經進一步組態以在接收該應力訊號之前接收具有一第三電壓位準之一電壓。The semiconductor device of claim 18, wherein the first input terminal of the semiconductor device is further configured to receive a voltage having a third voltage level prior to receiving the stress signal. 如請求項19之半導體裝置，其中該接點經電連接至該半導體裝置之一汲極或一源極。The semiconductor device of claim 19, wherein the contact is electrically connected to a drain or a source of the semiconductor device.
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