KR100892680B1 - Test circuit - Google Patents

Abstract

A test circuit is provided to monitor each output signal from a plurality of transistor groups having gates arranged in a cross direction in a wafer level, thereby accurately testing a gate arrangement type of transistors. The first detecting unit(20) is comprised of the first transistors. The first transistors are comprised of the first gates arranged in the first direction. The first detecting unit processes an input signal by the first transistor to output the first gate detection signal. The second detecting unit(22) is comprised of the second transistors. The second transistors are comprised of the second gates arranged in the second direction. The second detecting unit processes an input signal by the second transistor to output the second gate detection signal. A comparison unit(24) compares the first gate detection signal with the second gate detection signal to output the comparison result. An edge trigger signal output unit is synchronized with an edge of the first gate detection signal to output a logic signal corresponding to the second gate detection signal.

Description

Test Circuit {TEST CIRCUIT}

The present invention relates to a test circuit, and more particularly to a test circuit for testing the characteristic difference according to the gate arrangement of the transistors.

In general, poly gates are mixed in a horizontal direction and a vertical direction with respect to a flat zone of a wafer in a semiconductor memory chip. In this case, when the poly gates are all laid out in the same size, it is preferable that the poly gates formed through the process are also the same as intended in the layout. However, in the actual process, it is difficult for all of the poly gates to be formed identically. In particular, the gate critical demension in the horizontal direction and the gate line width in the vertical direction may be different from each other.

That is, as shown in FIG. 1, in a typical semiconductor memory device, gates 12 patterned in a horizontal direction and gates patterned in a vertical direction with respect to the flat zone 11 of the wafer 10 ( 13) are mixed.

At this time, even if the gates 12 and 13 are laid out in the same size, the line width of the gate 12 arranged in the horizontal direction is formed to about 90 nm in the actual process, and the line width of the gate 13 arranged in the vertical direction is smaller than this. It may be formed at about 80nm. That is, in the process, the line width difference between the gate 12 arranged in the horizontal direction and the gate 13 arranged in the vertical direction may occur.

Such a difference in gate line width may occur frequently in a micro process, and when the gate line width difference occurs due to such an arrangement type in transistors requiring the same characteristics, the transistors may have different characteristics. In particular, when the gate line width is smaller than the target, the threshold voltage of the transistor is lowered and the leakage current increases in the turn-off state, which requires continuous monitoring and improvement.

Conventionally, the reduction of the gate line width has been analyzed through manual inspection, such as a method of directly inspecting the eye through a microscope. However, the analysis takes a lot of time, and the finer the process, the less accurate the gate line width is. have.

The present invention provides a test circuit capable of accurately monitoring the difference in characteristics of transistors according to the difference in gate line width of the transistors. In particular, the test circuit can be applied when the gates have an arrangement in the direction of crossing each other at the wafer level.

According to an exemplary embodiment of the present invention, a test circuit includes first transistors including first gates disposed in a first direction on a predetermined substrate in a circuit combination, and processes the input signal by using the first transistors. A first detector for outputting a gate detection signal; Second transistors including second gates disposed in a second direction on the substrate are provided in a circuit combination similarly to the first detection unit, and the second signal is processed by the combined second transistors. A second detector for outputting a gate detection signal; And a comparator for comparing a difference between the first gate detection signal and the second gate detection signal and outputting a comparison result.

The first detector may include a first delay unit configured to delay the input signal; And a first combination unit combining the output of the first delay unit and the input signal and outputting the first gate detection signal, wherein the first delay unit and the first combination unit are configured as the first transistors. This is preferred.

The second detector may include a second delay unit configured to delay the input signal with the same structure as the first delay unit; And a second combiner configured to combine the output of the second delay unit and the input signal and output the second gate detection signal in the same structure as the first combiner. Preferably, the combination portion is composed of the second transistors.

The comparator may include an edge trigger signal output unit configured to output a logic signal corresponding to the second gate detection signal in synchronization with an edge of the first gate detection signal. The comparator may further include a margin controller configured to adjust a margin between the first gate detection signal and the second gate detection signal by adjusting the second gate detection signal. The margin controller preferably delays the second gate detection signal to the edge trigger signal output unit.

Meanwhile, the first and second gates are preferably arranged in a direction orthogonal to each other on the substrate.

The present invention accurately tests the difference in characteristics of gate arrangements of transistors by monitoring signals output from a plurality of transistor groups each having gates having different line widths, particularly gates arranged in cross directions at the wafer level. It can work.

The present invention discloses a test circuit capable of monitoring the difference in characteristics of transistors having gates with different line widths. In particular, the test circuit according to the present invention compares the output signals of the two circuits by configuring the transistors having the gate formed in the first direction and the transistors having the gate formed in the second direction, respectively, with the same circuit receiving the same input. And a configuration for detecting a change in characteristics of the transistor in accordance with the arrangement. Here, the test circuit according to the present invention may be configured in a cell unit, a plurality of the cell unit, or a wafer unit included in one package, alternatively configured on a test board externally connected to the cell or wafer. Can be. In addition, the transistors included in the test circuit according to the present invention are modeled by the transistors to be tested. The above configuration will be apparent to those skilled in the art.

In detail, the embodiment of FIG. 2 includes detectors 20 and 22 and a comparator 24.

The detector 20 is a circuit combination of a plurality of transistors composed of gates arranged in the first direction, the detector 22 is a circuit combination of a plurality of transistors composed of gates arranged in the second direction. will be. Here, the detector 20 and the detector 22 have the same components in the same combination, but have different outputs due to the difference in the line widths according to the arrangement direction by having a difference in the arrangement direction of the gate even when receiving the same input IN. Can be. At this time, the input signal IN is preferably a signal input from the outside in the test mode.

The comparison unit 24 compares the output VGO and HGO differences of the detection units 20 and 22 to compare the output characteristic differences of the detection units 20 and 22 due to the difference in line widths according to different arrangement directions. Outputs

More specifically, referring to FIGS. 3 and 4, the detector 20 includes a plurality of first transistors that are circuitally combined, and processes the input signal IN with the first transistors to output the gate detection signal VGO. Here, each of the first transistors is formed through a process in which a gate is laid out in a first direction on a predetermined substrate, and the first direction may correspond to a vertical direction based on, for example, the flat zone of the semiconductor wafer.

The detector 20 may be configured to output a signal that may indicate gate characteristics of the first transistors, and as an example, a configuration of delaying and outputting the input signal IN as the first transistors may be presented.

That is, as illustrated in FIG. 3, the detector 20 delays the input signal IN and outputs the delay signal VGDLY, and the gate detection signal VGO that is a pulse by combining the input signal IN and the delay signal VGDLY. It can be configured to include a combination unit 31 for outputting.

For example, the delay unit 30 may be configured as an inverter chain that receives an input signal IN and delays the input signal IN, and each inverter INV1 constituting the inverter chain may be configured as first transistors. In another example, the delay unit 30 may include a plurality of MOS capacitor pairs connected in parallel to a node between an input terminal to which an input signal IN is input and an output terminal to which a delay signal VGDLY is output. Here, each MOS capacitor pair may be composed of a pull up MOS capacitor and a pull down MOS capacitor, and each of the pull up and pull down MOS capacitors may be configured as a first transistor.

The combination unit 31 is a NAND gate NA1 for NAND combining the input signal IN and the output of the delay unit 30, and an inverter INV2 that inverts the output of the NAND gate NA1 and outputs the gate detection signal VGO. It may be configured to include). Here, the NAND gate NA1 and the inverter INV2 may be configured of first transistors.

The detector 22 includes a plurality of second transistors that are circuitically combined in the same manner as the detector 20, and processes the input signal IN with the second transistors, and outputs the input signal IN as the gate detection signal HGO. Here, each of the second transistors is formed through a process in which a gate is laid out in a second direction on a predetermined substrate, and the second direction may correspond to a horizontal direction based on, for example, the flat zone of the semiconductor wafer. Each of the second transistors may be one-to-one correspondence with each of the first transistors and be laid out in the same size.

The detector 22 may be configured to output a signal indicating the gate characteristics of the second transistors, and may have the same structure as the detector 20. For example, when the detector 20 is configured to delay and output the input signal IN with the first transistors, the detector 22 may delay and output the input signal IN with second transistors having the same structure as the first transistors. The configuration of can be presented.

That is, as shown in FIG. 3, the detector 22 combines the delay unit 32 for delaying the input signal IN and the output of the input signal IN and the delay unit 32 to output the pulse detection gate VGO. It can be configured to include a combination unit 33.

Here, the delay unit 32 includes second transistors having the same structure as the delay unit 30. For example, the delay unit 32 may be configured as an inverter chain, and each inverter INV3 constituting the inverter chain may be configured as second transistors.

The combiner 33 includes second transistors having the same structure as the combiner 31. For example, the combiner 33 performs an NAND gate NA2 for NAND combining the input signal IN and the output of the delay unit 32, and an inverter for inverting the output of the NAND gate NA2 and outputting the gate detection signal HGO. And an INV4, and the NAND gate NA2 and the inverter INV4 may be configured as second transistors.

The comparator 24 compares the difference between the gate detection signal VGO output from the detector 20 and the gate detection signal HGO output from the detector 22 and outputs the difference as the output signal CDLOW. Here, when the gate detection signals VGO and HGO are delayed signals through the detectors 20 and 22, respectively, the comparator 24 may compare the delay differences between the two gate detection signals VGO and HGO and output the output signal CDLOW. have.

That is, as shown in FIG. 4, the comparator 24 has a margin adjusting unit 40 for margining the difference between the gate detection signal VGO and the gate detection signal HGO, and a margin synchronized with the edge of the gate detection signal HGO. And an edge trigger signal output unit 42 for outputting an output signal CDLOW corresponding to the output VGOD state of the controller 40.

Here, the margin controller 40 may be configured to delay the gate detection signal VGO by a predetermined delay and output the delayed gate detection signal VGOD in order to provide a margin of a difference between the two gate detection signals VGO and HGO.

The edge trigger signal output section 42 outputs an output signal CDLOW having a logic level corresponding to the state of the delay gate detection signal VGOD in synchronization with the rising edge of the gate detection signal HGO. That is, the edge trigger signal output section 42 outputs the output signal CDLOW corresponding to the logic level of the delay gate detection signal VGOD at the time when the gate detection signal HGO transitions from the low level to the high level.

The test circuit of the present invention having the configuration as shown in FIGS. 3 and 4 has an output characteristic as shown in FIG. 5A or 5B according to the size difference between the gate pattern of the first transistors and the gate pattern of the second transistors formed on the substrate. .

First, as shown in FIG. 5A, the delay signal VGDLY output from the delay unit 30 is much less than the delay signal HGDLY output from the delay unit 33 due to the difference in characteristics of the first and second transistors. May occur.

In this case, the rising time of the gate detection signal VGO output from the combining unit 31 is much faster than the rising time of the gate detection signal HGO output from the combining unit 33, and the gate detection signal VGO is applied to the margin adjusting unit 40. Even if it is through, the rising time of the delay gate detection signal VGOD output from the margin adjusting unit 40 is formed earlier than the rising time of the gate detection signal HGO.

Accordingly, since the delay gate detection signal VGOD is at the high level at the rising edge of the gate detection signal HGO, the output signal CDLOW is output at a high level, that is, a logic level '1'.

As such, when the output signal CDLOW is output at a high level, the gate-critical dimensions of the first and second transistors are identically laid out, but the gate-critical dimensions of the first and second transistors formed on the substrate through the actual process. Can be judged to be large. In particular, since the configuration of FIGS. 3 and 4 compares the gate critical dimension of the first transistors based on the gate critical dimension of the second transistors, the gate critical decode of the first transistors when the output signal CDLOW is high level. It can be seen that the junction is formed smaller than the gate critical dimension of the second transistors.

On the other hand, as shown in FIG. 5B, when the delay difference between the delay signal VGDLY output from the delay unit 30 and the delay signal HGDLY output from the delay unit 33 is substantially the same, the output is performed through the margin controller 40. The rising time of the delayed gate detection signal VGOD is formed later than the rising time of the gate detection signal HGO.

Accordingly, since the delay gate detection signal VGOD is at the low level at the rising edge of the gate detection signal HGO, the output signal CDLOW is output at a low level, that is, a logic level '0'.

As such, when the output signal CDLOW is output at a low level, it may be determined that there is almost no difference such that the difference between the gate critical dimensions of the first and second transistors can be ignored.

As described above, the test circuit of the present invention compares the output of the first circuit composed of the first transistors with the output of the second circuit composed of the second transistors of the same combination as the first circuit. It is easy to detect whether there is a gate line width difference between the second transistors.

Here, the first and second transistors have the same size and are differently laid out only in the gate direction. For example, the gates of the first transistors may be laid out in a vertical direction with respect to the wafer flat zone, and the gates of the second transistors may be laid out. It may be laid out in a horizontal room based on the wafer flat zone.

The test circuit of the present invention outputs the output signal CDLOW which shows the difference in characteristics of the transistors according to the gate arrangement type, so that the characteristic difference of the transistor according to the gate arrangement type can be accurately monitored as the output signal CDLOW state. have.

In addition, the test circuit of the present invention outputs the output signal CDLOW which shows the difference in the characteristics of the transistors according to the gate arrangement according to the input of the input signal IN, thus eliminating the need for manual inspection in the wafer state and during the development period. Whenever necessary, the characteristics of the transistors can be tested. Therefore, the difference in characteristics of the transistors can be easily monitored, development feedback is easy, and the development period can be shortened.

1 is a plan view illustrating a gate pattern size difference according to a gate arrangement of transistors formed on a wafer of a general semiconductor memory device.

2 is a circuit diagram showing a test circuit of the present invention.

3 is a circuit diagram showing a detailed configuration of the detectors 20 and 22 of FIG.

4 is a block diagram showing a detailed configuration of the comparison unit 24 of FIG.

5A and 5B are waveform diagrams showing output characteristics according to gate pattern size differences of the test circuit of the present invention.

Claims (7)

First transistors comprising first gates disposed in a first direction on a predetermined substrate are provided in a circuit-combined manner, and the first transistors process an input signal with the combined first transistors to output a first gate detection signal. Detection unit; Second transistors including second gates disposed in a second direction on the substrate are provided in a circuit combination similarly to the first detection unit, and the second signal is processed by the combined second transistors. A second detector for outputting a gate detection signal; And And a comparison unit comparing the difference between the first gate detection signal and the second gate detection signal and outputting a comparison result. And the comparing unit includes an edge trigger signal output unit configured to output a logic signal corresponding to the second gate detection signal in synchronization with an edge of the first gate detection signal. The method of claim 1, The first detection unit, A first delay unit delaying the input signal; And And a first combining unit combining the output of the first delay unit and the input signal to output the first gate detection signal. And the first delay unit and the first combination unit are configured of the first transistors. The method of claim 2, The second detection unit, A second delay unit configured to delay the input signal with the same structure as the first delay unit; And And a second combiner configured to combine the output of the second delay unit and the input signal and output the second gate detection signal in the same structure as the first combiner. And the second delay unit and the second combination unit are configured of the second transistors. delete The method of claim 1, The comparator further includes a margin controller configured to adjust the second gate detection signal to adjust a margin between the first gate detection signal and the second gate detection signal. The method of claim 5, wherein And the margin controller transfers the second gate detection signal to the edge trigger signal output unit by a predetermined delay. The method of claim 1, And the first and second gates are disposed on the substrate in a direction orthogonal to each other.

Images