TWI773130B - 多晶片模組溝槽化蓋及低熱膨脹係數加強環 - Google Patents
多晶片模組溝槽化蓋及低熱膨脹係數加強環 Download PDFInfo
- Publication number
- TWI773130B TWI773130B TW110104737A TW110104737A TWI773130B TW I773130 B TWI773130 B TW I773130B TW 110104737 A TW110104737 A TW 110104737A TW 110104737 A TW110104737 A TW 110104737A TW I773130 B TWI773130 B TW I773130B
- Authority
- TW
- Taiwan
- Prior art keywords
- cover
- die
- module
- lid
- component
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/06—Containers; Seals characterised by the material of the container or its electrical properties
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16151—Cap comprising an aperture, e.g. for pressure control, encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
- H01L2924/16153—Cap enclosing a plurality of side-by-side cavities [e.g. E-shaped cap]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/163—Connection portion, e.g. seal
- H01L2924/164—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Dispersion Chemistry (AREA)
- Materials Engineering (AREA)
- Casings For Electric Apparatus (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Micromachines (AREA)
- Light Receiving Elements (AREA)
- Semiconductor Lasers (AREA)
Abstract
描述多晶片模組(MCM)結構。在一實施例中,一種模組包括:一第一組件及一第二組件,其在一模組基材之該頂側上;一加強件結構,其安裝在該模組基材之該頂側上;及一蓋,其安裝在該加強件結構上並覆蓋該第一組件及該第二組件。該加強件在形成於該蓋之一蓋頂中的一溝槽內接合至該蓋。
Description
本文描述之實施例係關於多晶片模組,且具體地係關於其蓋。
由於各種原因,蓋被廣泛地使用在多晶片模組(multiple chip module, MCM)中,諸如以提供機械完整性、對環境的氣密、及熱效能。在一例示性實施方案中,將一或多個組件表面安裝至模組基材上,然後可選地受底部填充。接著將蓋固定至模組基材上與(多個)組件上方。
實施例描述多晶片模組(MCM)結構,其中產生蓋及加強件結構的一組合以獲得一蓋的機械完整性及熱效益,並減少由該加強件結構提供之翹曲。具體而言,該加強件結構可減少可能由該蓋的熱膨脹係數(coefficient of thermal expansion, CTE)與該MCM的其餘部分的失配所導致的翹曲。描述各種可進一步減輕應力及翹曲的各種蓋設計,包括用以增加加強件結構對蓋、多部件蓋、及混合蓋之體積比的溝槽設計。
雖然蓋可提供機械完整性給MCM,但已觀察到蓋亦可在MCM中造成大應力及高翹曲並造成機械故障。例如,由銅形成的蓋可相對於其他模組特徵具有相對高的熱膨脹係數(CTE)。當蓋與模組的其餘部分強耦接時,此可導致熱膨脹並在MCM組件(例如,封裝)中造成應力及翹曲。具體而言,已觀察到模具破裂可在包覆成型的並排晶粒之間產生,其可因為蓋所造成的應力而加劇。根據實施例,提供蓋及加強件結構(亦稱為加強環)的各種組合以平衡蓋之提供模組之機械完整性但不造成機械故障的能力。
根據實施例,蓋可包括溝槽化設計。溝槽化設計可包括在模組組件之頂部上的足夠蓋體積,以保持足夠熱效能,但減少蓋在連接區域處的體積,以進一步減少由蓋導致的應力及翹曲。在一些實施例中,蓋體積的減少可對應於加強件結構在體積上增加,其增加加強件結構對蓋之體積比。此可進一步提供選擇(多個)加強件結構材料的可行性,以減少MCM中的應力及翹曲。
根據實施例,加強件結構(例如,環)可完全或部分地由低CTE材料形成。在此態樣中,加強件結構對蓋之體積比的增加(例如,因為溝槽化蓋設計的緣故)促進藉由選擇具有比蓋更低之CTE的加強件材料來降低蓋-加強件組合之有效CTE的能力。蓋-加強件結構之有效CTE的降低可繼而減少MCM的應力及翹曲問題。在一例示性實施方案中,低CTE加強件材料可係鎳-鐵合金(FeNi36)、鐵-鎳-鈷合金(以KOVAR商標(CRS Holdings, Inc., Delaware的商標)銷售)、鐵-鎳合金(Alloy42)、不銹鋼(SUS410、SUS430)等,而蓋係由較高CTE的材料(諸如銅)形成。
根據實施例,描述多部件蓋設計。多部件蓋設計可減少蓋對模組之其餘部分的耦接效應,並進一步減少由蓋導致的應力。此可包括晶粒對晶粒模製化合物應力及模組翹曲的減少。在一些實施例中,多部件蓋設計合併不同蓋材料以符合MCM的不同機械及熱需求。亦描述將不同材料的蓋接合在一起或將一者嵌入其他者內的混合蓋設計。可藉由組合不同材料來調諧蓋的有效CTE及勁度,以達到目標機械及熱效能匹配。
在各種實施例中,參照圖式進行說明。然而,某些實施例可在無這些特定細節之一或多者的情況下實行或可與其他已知的方法及組態結合實行。在下列敘述中,為了提供對實施例的全面瞭解而提出眾多特定細節(例如,特定組態、尺寸、及程序等)。在其他例子中,為了避免不必要地使本實施例失焦,所以並未特別詳細地敘述公知的半導體程序及製造技術。此專利說明書通篇指稱的「一實施例(one embodiment)」係指與該實施例一同描述之具體特徵、結構、組態、或特性係包括在至少一實施例中。因此,此專利說明書通篇於各處出現之詞組「在一實施例中(in one embodiment)」不必然指稱相同實施例。此外,在一或多個實施例中,可以任何合適的方式結合特定特徵、結構、組態、或特性。
如本文所用之「在…上面(above)」、「在…上方(over)」、「至(to)」、「介於…之間(between)」、「橫跨(spanning)」、及「在…上(on)」之用語可指稱一層相對於其他層之一相對位置。一層在另一層「上面」、在另一層「上方」、「橫跨」另一層、或在另一層「上」或者一層接合「至」另一層或與另一層「接觸(contact)」可直接與另一層接觸或可具有一或多個中介層。一層介於(多個)層「之間」可直接與該等層接觸或可具有一或多個中介層。
現在參照圖1,提供包括蓋300及分別具有內支撐件220及外支撐件210的加強件結構200之MCM 150的截面側視圖繪示。在例示性實施例中,MCM 150包括模組基材100,該模組基材包括頂側102及底側104。複數個第一組件120可安裝在模組基材100的頂側102上。第一組件120可係主動或被動裝置,且可係晶片或封裝。例如,第一組件120可係記憶體封裝,諸如包括可係堆疊或並排晶粒的一或多個晶粒的動態隨機存取記憶體(DRAM)。在一實施例中,第一組件係晶片級封裝。第一組件120可額外地係不同類型的組件,且不需要相同。一或第二組件130亦可安裝在模組基材100的頂側102上。在一實施例中,第二組件130係包括複數個(例如,二或更多個)並排晶粒的封裝。例如,第二組件130可包括複數個並排邏輯晶粒、或系統單晶片晶粒。
現在參照圖2A至圖2C,提供根據實施例的蓋及加強件結構配置的示意截面側視圖繪示及俯視圖繪示。在一例示性實施方案中,使用任何合適技術(諸如,焊料凸塊160)以可選底膠162(例如,環氧樹脂)將第一組件120及第二組件130表面安裝至模組基材100上。在所繪示的實施例中,第二組件130係包括封裝在模製化合物134中的複數個並排晶粒132的封裝。如圖所示,可用模製化合物134填充側向於晶粒132之間的空間133。已觀察到導因於多種材料與MCM結構的緊密鄰接,此可係MCM內的一高應力地點。
熱界面材料(thermal interface material, TIM) 170可位於第一組件120及第二組件130的頂側上,以固定至蓋300。TIM 170可使用任何合適技術(諸如施配或膠帶)施加。例示性TIM 170材料包括但不限於:熱油脂、焊料、金屬填充聚合物基質等。
根據實施例,蓋300可接合至中間加強件結構200(亦稱為加強環),其繼而接合至模組基材100。加強件結構200及蓋300可使用黏著劑材料接合。例如,黏著劑可在連接區域(例如,外連接區域180及內連接區域182)處施配至模組基材100上,之後安裝加強件結構200。例示性黏著劑材料包括玻璃膏、環氧樹脂、胺甲酸酯、聚胺甲酸酯、聚矽氧彈性體等。蓋300可在將加強件結構200安裝在模組基材100上之後或之前類似地接合至該加強件結構。
如所繪示的,蓋300可包括蓋頂330、外(周邊)壁310、及可選地內壁320。蓋頂的底表面302可接合至在第二組件130及第一組件120之頂部上的TIM 170。可針對各種第一組件120及第二組件130調整底表面302的輪廓(蓋頂330的厚度),以與TIM 170均勻地配接。外壁310及內壁320可從蓋頂330延伸(例如,從底表面突出),以形成容納第二組件130及第一組件120的一或多個腔穴305。根據實施例,加強件結構200經成形以與蓋300的外壁310及內壁320配接。具體而言,加強件結構200可包括外支撐件(壁)210及內支撐件220(壁)。外支撐件210及內支撐件220可由相同材料一體成形。替代地,外支撐件210及內支撐件220可由具有不同CTE的不同材料形成。具有不同材料的各種額外組態係可行的。加強件結構200與蓋300之間的配接表面可具有相同的表面積。複數個模組焊料凸塊190可可選地施加至模組基材100的底側104,以用於進一步整合。
根據實施例,提供蓋及加強件結構的各種組合以平衡蓋之將機械完整性提供給模組但不造成機械故障的能力。具體而言,描述溝槽化蓋的各種組合、加強件結構對蓋之體積比、多部件蓋設計、及具有不同CTE之材料的組合。
現在參照圖3至圖9,根據實施例繪示各種溝槽化蓋設計及加強件結構。如圖所示,MCM 150可包括模組基材100、在模組基材之頂側102上的第一組件120、及在模組基材之頂側102上的第二組件130。將加強件結構200安裝在模組基材的頂側102上,並將蓋300安裝在加強件結構200上並覆蓋第一組件120及第二組件130二者。根據各種實施例,加強件結構200可在形成於蓋之蓋頂330中的溝槽315內接合至蓋300。加強件結構200可包括外支撐件210及內支撐件220的任一者或二者。
圖3係根據一實施例之在外支撐件210上之蓋的溝槽化設計的示意截面側視圖繪示。如圖所示,溝槽315形成在蓋300之蓋頂330的底表面302中。各溝槽315可包括在蓋頂330中的一或多個溝槽邊緣(側壁)331。以此方式,蓋頂330在溝槽315區中的厚度小於蓋頂330的厚度,其中蓋300連接至具有TIM 170的第二組件130,且其中蓋300連接至具有TIM的第一組件120。因此,溝槽315減少蓋300在連接區域的體積。具體而言,溝槽315係形成在外(周邊)連接區域180處,其中溝槽於該處與加強件結構200的外支撐件(壁)210接合。在此繪示中,溝槽不包括外側壁(溝槽邊緣)。在所繪示的實施例中,外支撐件210在溝槽315內接合至蓋300。雖然未繪示,但蓋300可額外包括接合至加強件結構200之內支撐件220的內壁320。
圖4係根據一實施例之在內支撐件上之蓋的部分溝槽化設計的示意截面側視圖繪示。如圖所示,內支撐件220在溝槽315內接合至蓋300。額外地,蓋300包括接合至外支撐件210的外壁310。在所繪示的實施例中,內支撐件220比外支撐件210高。
圖5係根據一實施例之在外支撐件上之蓋的部分溝槽化設計的示意截面側視圖繪示。如圖所示,外支撐件210在溝槽內接合至蓋300。蓋300額外包括接合至內支撐件220的內壁320。在所繪示的實施例中,外支撐件210比內支撐件220高。亦如圖5所示,內壁320從溝槽315延伸。在一實施例中,蓋300可包括外壁310及從溝槽315延伸的內壁320二者。
圖6係根據一實施例之在內支撐件及外支撐件二者上之蓋的部分溝槽化設計的示意截面側視圖繪示。圖6類似於繪示於圖3中的實施例,其中加入亦於溝槽315內接合至蓋的內支撐件220,該溝槽與外支撐件210於其中接合至蓋的溝槽315可係相同溝槽或分開的溝槽。
圖7係根據一實施例之在內支撐件或外支撐件上之蓋的部分溝槽化設計的示意截面側視圖繪示。如圖所示,圖7結合圖4至圖6的特徵以顯示各種組態係可行的,其中內支撐件220及外支撐件210的部分可具有不同高度,且外壁310及內壁320可係不連續的。
根據實施例的溝槽化蓋設計可減少蓋在連接區域處的體積,以減少由蓋所導致的應力及翹曲。此外,蓋體積的減少可對應於加強件結構在體積(高度)上的增加,其增加加強件結構對蓋之體積比。在所繪示的實施例中,加強件結構對蓋的比例大於1,意指加強件結構可高於蓋之溝槽化蓋頂的厚度。
根據實施例,加強件結構可完全或部分地由低CTE材料形成。在一例示性實施方案中,低CTE加強件材料可係鎳-鐵合金(FeNi36)、鐵-鎳-鈷合金(以KOVAR商標(CRS Holdings, Inc., Delaware的商標)銷售)、鐵-鎳合金(Alloy42)、不銹鋼(SUS410、SUS430)等,而蓋係由較高CTE材料(諸如銅)形成。加強件結構亦可由不同材料(不同的化學組成物、或合金比例)形成,以調諧應力及翹曲。
圖8係根據一實施例之由具有不同熱膨脹係數的相鄰材料形成的加強件結構的示意截面側視圖繪示。例如,外支撐件210及內支撐件220可由具有不同CTE的不同材料221、223形成。再者,外支撐件210及內支撐件220的不同區域可由不同材料221、223形成,以局部地調諧應力及翹曲。
圖9係根據一實施例之由具有不同熱膨脹係數的堆疊材料221、223形成的加強件結構的示意截面側視圖繪示。此外,堆疊材料221、223的相對厚度在外支撐件210及內支撐件220的不同區域中可不同。
根據實施例的蓋亦可具有複數個實體分開的部件。此類多部件蓋設計可減少蓋對模組之其餘部分的耦接效應,並進一步減少由蓋導致的應力。此可包括晶粒對晶粒模製化合物應力及模組翹曲的減少。
現在參照圖10A至圖10C,提供根據實施例之多部件蓋的示意俯視圖繪示及截面側視圖繪示。在所繪示的實施例中,蓋300可包括接合至加強件結構200的複數個實體分開的蓋頂330A、330B、330C。蓋頂330A、330B、330C可額外具有包括溝槽315的溝槽設計。在所繪示的實施例中,溝槽315可沿著蓋頂330A、330B、330C的側形成,使得一對蓋頂係接合至各內支撐件220,且單一蓋頂係接合至各外支撐件210。各蓋可經錨定至其周圍的內支撐件220,及/或外支撐件210。在繪示於圖10C的具體實施例中,蓋可進一步包括與組件(例如,第二組件130)邊緣配接的組件凹部335。組件凹部335可提昇TIM 170與組件邊緣的覆蓋率,並減少TIM剝離應力。
現在參照圖11A至圖11B,提供根據實施例之多部件蓋的示意俯視圖繪示及截面側視圖繪示。圖11A至圖11B與圖10A至圖10B之實施例的不同之處在於:溝槽225係形成在與蓋之蓋頂相對的內支撐件220及/或外支撐件210內。類似地,溝槽225可包括溝槽邊緣227。在所繪示的特定實施例中,內支撐件220包括溝槽225以容納蓋300的蓋頂330A。圖11A至圖11B的實體分開的蓋頂330A、330B、330C可具有不同厚度,以管理應力及翹曲。
根據實施例的多部件蓋設計亦可包括內壁及/或外壁。現在參照圖12A至圖12C,提供根據實施例之多部件蓋的示意截面側視圖繪示及俯視圖繪示。應理解,雖然分開繪示及描述,但圖12A至圖12C的多部件蓋實施例可與圖10A至圖11B的多部件蓋實施例以及本文描述的其他實施例組合。
如圖所示,多部件蓋300可包括:第一蓋部件300A,其跨越在第二組件130中的第一晶粒132上方;及第二蓋部件300B,其跨越在第二組件130中的第二晶粒132上方。可包括多個蓋部件300A、300B、300C、300D等。如圖所示,模製化合物134可填充側向於第一晶粒132與第二晶粒132之間的空間133,該空間可對應於一高應力區。間隙325可位於第一蓋部件300A與第二蓋部件300B之間。在所繪示的實施例中,間隙325係在側向於組件130的第一晶粒132與第二晶粒132之間的空間133的正上方,該間隙可以模製化合物134填充。間隙325可進一步減少蓋對模組之其餘部分的耦接效應,並進一步減少由蓋導致的應力。根據實施例,分開的蓋部件300A、300B等可由不同材料321、323形成。可調諧不同蓋材料的使用,以符合微電子模組的不同機械及熱需求。可將間隙325如圖13A至圖13B所示地可選地以填充材料400填充。例如,填充材料可係焊料、黏著劑等。
現在參照圖14A至圖14C,提供根據實施例之包括混合蓋設計之多晶片模組的分解等角圖繪示、示意截面側視圖繪示、及俯視圖繪示。除了上述結構或替代上述結構,混合蓋300設計可包括接合在一起或一者嵌入於其他者內的不同材料。可藉由組合不同材料來調諧蓋的有效CTE及勁度,以達到目標機械及熱效能匹配。在一實施例中,蓋300可包括接合至主蓋結構之蓋頂330的第一蓋圖案500,其中第一蓋圖案500具有與主蓋結構不同的CTE。主蓋結構可類似於先前描述的蓋300,其中加入將第一蓋圖案500固定於其中的陰圖案360。第一蓋圖案500可包括各種特徵,該等特徵可可選地包括內肋520及外(周邊)輪廓510。第一蓋圖案500可位於高應力區處,諸如在連接區域(180、182)及在並排晶粒之間的空間上方。在一實施例中,內肋520係在相鄰晶粒132之間的空間133的正上方。
目前為止,已繪示及描述作為單部件蓋配置或多部件蓋配置的蓋結構。根據實施例,一或多個局部開口可形成在蓋結構的任一者中以減少應力及翹曲。圖15A至圖15C繪示此一局部開口326的例示性實施方案。如圖所示,圖15A至圖15C類似於相關於圖2A至圖2C所先前繪示及描述的蓋設計,但實施例並未如此受限。在一實施例中,一或多個局部開口326可位於側向於晶粒132之間的空間133的正上方(上方)。一或多個局部開口326可與空間133完全或部分地重疊。一或多個局部開口亦可位於其他區上方以減輕應力。在一實施例中,從蓋頂330的頂側304至底表面302形成完全穿過蓋之蓋頂330的一或多個局部開口326。
(多個)加強件結構200及/或(多個)蓋300亦可經設計以突出於模組基材100的周邊邊緣以減少應力及翹曲。圖16A係根據一實施例之在內支撐件及外支撐件上之具有突出於模組基材100之外連接區域180之蓋設計的示意截面側視圖繪示。圖16B係根據一實施例之在外支撐件上之具有突出於模組基材100之外連接區域180之蓋設計的示意截面側視圖繪示。繪示於圖16A至圖16B中的特定實施例類似於相關於圖2A至圖2B所先前繪示及描述的該等者,然而,此僅係例示性的,且突出設計可與加強件結構200、內支撐件220及外支撐件210、及具有對應內壁320及外壁310之蓋300組合的任一者組合。突出設計亦與本文描述的多部件蓋結構相容。
根據實施例的突出蓋設計可突出於模組基材100之一或多個或所有的周邊(側向)邊緣106。具體而言,加強件結構200的一或多個周邊邊緣216及/或對應於外連接區域180之(多個)蓋300的周邊邊緣316可突出於模組基材的一或多個周邊邊緣106。具體而言,外支撐件210的周邊邊緣216及蓋300之外壁310的周邊邊緣316可突出於模組基材100的周邊邊緣106。圖16C係根據一實施例之包括在一個方向上突出於模組基材之外連接區域之蓋300設計的示意俯視圖繪示。如圖所示,蓋300之外壁310的周邊邊緣316在模組基材100的二相對側上側向地延伸越過周邊邊緣106。圖16D係根據一實施例之包括在多個方向上突出於模組基材之外連接區域之蓋300設計的示意俯視圖繪示。如圖所示,蓋300之外壁310的周邊邊緣316在模組基材100的四側上側向地延伸越過周邊邊緣106。雖然在圖16C至圖16D的俯視圖繪示中不可見,但加強件結構200之外支撐件210的周邊邊緣216可類似地定向,或是在若蓋300不包括外壁310的情況下可替代地定向。應理解,圖16B至圖16C的特定定向係例示性的,且各種替代配置係可能的,其中外連接區域突出於模組基材的一或多個周邊邊緣106。額外地,外連接區域180可部分或完全地突出於模組基材100之周邊邊緣106之任一者的長度。
現在參照圖16E,提供根據一實施例之突出於模組基材之蓋300及支撐結構200的特寫示意截面側視圖繪示。在此一組態中,支撐結構200的底側211可係水平或平面的。如圖所示,支撐結構200及蓋300的周邊邊緣216、316以寬度(W)超覆於(或延伸越過)模組基材100的周邊邊緣106。支撐結構200及/或蓋300亦可具有L形組態,其中支撐結構及/或蓋300的懸掛部分側向相鄰於模組基材100的周邊邊緣106。在此類組態中,支撐結構200的底側211或蓋300的底側311可具有L形輪廓。
圖16F係根據一實施例之突出於模組基材100之L形支撐結構200的特寫示意截面側視圖繪示。如圖所示,支撐結構200可以寬度(W)超覆於(或延伸越過)模組基材100的周邊邊緣106,且亦包括向下突出並側向相鄰於模組基材100之周邊邊緣106的懸掛部分213。懸掛部分213可包括以間隙(G)與周邊邊緣106分開的內側邊緣217。
圖16G係根據一實施例之突出於模組基材100之L形蓋300的特寫示意截面側視圖繪示。如圖所示,蓋300可以寬度(W)超覆於(或延伸越過)模組基材100的周邊邊緣106,且亦包括向下突出並側向相鄰於模組基材100之周邊邊緣106的懸掛部分313。懸掛部分313可包括以間隙(G)與周邊邊緣106分開的內側邊緣317。
在使用實施例的各種態樣的過程中,所屬技術領域中具有通常知識者將明白上述實施例的組合或變化對於整合MCM蓋結構並同時減輕模組翹曲係可行的。雖然已經以結構特徵及/或方法動作之特定語言敘述實施例,應了解附加的申請專利範圍不必受限於所述的特定特徵或行為。替代地,所揭示之特定的特徵及動作應理解為可用於說明之申請專利範圍的實施例。
100:模組基材
102:頂側
104:底側
106:周邊(側向)邊緣
120:第一組件
130:第二組件/組件
132:並排晶粒/晶粒/第一晶粒/第二晶粒
133:空間
134:模製化合物
150:MCM
160:焊料凸塊
162:底膠
170:熱介面材料/TIM
180:外(周邊)連接區域/連接區域
182:內連接區域/連接區域
190:模組焊料凸塊
200:加強件結構/支撐結構
210:外支撐件(壁)
211:底側
213:懸掛部分
216:周邊邊緣
217:內側邊緣
220:內支撐件
221:材料/堆疊材料
223:材料/堆疊材料
225:溝槽
227:溝槽邊緣
300:蓋
300A:第一蓋部件/蓋部件
300B:第二蓋部件/蓋部件
300C:蓋部件
300D:蓋部件
302:底表面
304:頂側
305:腔穴
310:外(周邊)壁
311:底側
313:懸掛部分
315:溝槽
316:周邊邊緣
317:內側邊緣
320:內壁
321:材料
323:材料
325:間隙
326:局部開口
330:蓋頂
330A:蓋頂
330B:蓋頂
330C:蓋頂
331:溝槽邊緣(側壁)
335:組件凹部
360:陰圖案
400:填充材料
500:第一蓋圖案
510:外(周邊)輪廓
520:內肋
G:間隙
W:寬度
[圖1]係根據一實施例之包括蓋及具有內支撐結構及外支撐結構之加強件結構的多晶片模組的分解等角視圖繪示。
[圖2A]係根據一實施例之在內支撐件及外支撐件上的蓋設計的示意截面側視圖繪示。
[圖2B]係根據一實施例之在外支撐件上的蓋設計的示意截面側視圖繪示。
[圖2C]係根據一實施例之在模組基材上方之蓋設計的示意俯視圖繪示。
[圖3]係根據一實施例之在外支撐件上之蓋的溝槽化設計的示意截面側視圖繪示。
[圖4]係根據一實施例之在內支撐件上之蓋的部分溝槽化設計的示意截面側視圖繪示。
[圖5]係根據一實施例之在外支撐件上之蓋的部分溝槽化設計的示意截面側視圖繪示。
[圖6]係根據一實施例之在內支撐件及外支撐件二者上之蓋的部分溝槽化設計的示意截面側視圖繪示。
[圖7]係根據一實施例之在內支撐件或外支撐件上之蓋的部分溝槽化設計的示意截面側視圖繪示。
[圖8]係根據一實施例之由具有不同熱膨脹係數的相鄰材料形成的加強件結構的示意截面側視圖繪示。
[圖9]係根據一實施例之由具有不同熱膨脹係數的堆疊材料形成的加強件結構的示意截面側視圖繪示。
[圖10A]係根據一實施例之具有多部件蓋之多晶片模組的示意俯視圖繪示。
[圖10B]係根據一實施例之具有溝槽設計蓋頂組件之多部件蓋的示意截面側視圖繪示。
[圖10C]係根據一實施例之具有組件腔穴之多部件蓋的示意截面側視圖繪示。
[圖11A]係根據一實施例之具有多部件蓋之多晶片模組的示意俯視圖繪示。
[圖11B]係根據一實施例之具有溝槽設計壁組件之多部件蓋的示意截面側視圖繪示。
[圖12A]至[圖12B]係根據一實施例之由不同材料形成之多部件蓋的示意截面側視圖繪示。
[圖12C]係根據一實施例之由不同材料形成之多部件蓋的示意俯視圖繪示。
[圖13A]係根據一實施例之具有密封間隙之多部件蓋的示意截面側視圖繪示。
[圖13B]係根據一實施例之具有密封間隙之多部件蓋的示意俯視圖繪示。
[圖14A]係根據一實施例之包括混合蓋設計之多晶片模組的分解等角視圖繪示。
[圖14B]係根據一實施例之包括混合蓋設計之多晶片模組的示意截面側視圖繪示。
[圖14C]係根據一實施例之包括混合蓋設計之多晶片模組的示意俯視圖繪示。
[圖15A]係根據一實施例之在內支撐件及外支撐件上並包括局部開口之蓋設計的示意截面側視圖繪示。
[圖15B]係根據一實施例之在外支撐件上並包括局部開口之蓋設計的示意截面側視圖繪示。
[圖15C]係根據一實施例之在模組基材上方之包括局部開口之蓋設計的示意俯視圖繪示。
[圖16A]係根據一實施例之在內支撐件及外支撐件上之具有突出於模組基材之外連接區域之蓋設計的示意截面側視圖繪示。
[圖16B]係根據一實施例之在外支撐件上之具有突出於模組基材之外連接區域之蓋設計的示意截面側視圖繪示。
[圖16C]係根據一實施例之包括在一個方向上突出於模組基材之外連接區域之蓋設計的示意俯視圖繪示。
[圖16D]係根據一實施例之包括在多個方向上突出於模組基材之外連接區域之蓋設計的示意俯視圖繪示。
[圖16E]係根據一實施例之突出於模組基材之蓋及支撐結構的特寫示意截面側視圖繪示。
[圖16F]係根據一實施例之突出於模組基材之L形支撐結構的特寫示意截面側視圖繪示。
[圖16G]係根據一實施例之突出於模組基材之L形蓋的特寫示意截面側視圖繪示。
100:模組基材
210:外支撐件(壁)
220:內支撐件
221:材料/堆疊材料
223:材料/堆疊材料
330:蓋頂
Claims (17)
- 一種多晶片模組,其包含:一模組基材;一第一組件,其在該模組基材的一頂側上;一第二組件,其在該模組基材的該頂側上;一加強件結構,其安裝在該模組基材的該頂側上;及一蓋,其安裝在該加強件結構上並覆蓋該第一組件及該第二組件;其中該加強件結構在形成於該蓋之一蓋頂中的一溝槽內接合至該蓋;及其中該蓋的一周邊邊緣突出於該模組基材的一周邊邊緣。
- 如請求項1之多晶片模組,其中該加強件結構包括一外支撐件及一內支撐件。
- 如請求項2之多晶片模組,其中該外支撐件在該溝槽內接合至該蓋。
- 如請求項3之多晶片模組,其中該蓋包含一內壁,該內壁接合至該加強件結構的該內支撐件。
- 如請求項2之多晶片模組,其中該內支撐件在該溝槽內接合至該蓋。
- 如請求項5之多晶片模組,其中該蓋包含一外壁,該外壁接合至該加強件結構的該外支撐件。
- 如請求項2之多晶片模組,其中該外支撐件在該溝槽內接合至該蓋,且該內支撐件在形成於該蓋之該蓋頂中的一第二溝槽內接合至該蓋。
- 如請求項2之多晶片模組,其中該加強件結構係由具有比該蓋更低之一CTE的一材料形成。
- 如請求項2之多晶片模組,其中該加強件結構的該外支撐件及該內支撐件包含具有一不同CTE的不同材料。
- 如請求項2之多晶片模組,其中該蓋包含實體分開的部件。
- 如請求項10之多晶片模組,其中該第二組件包含封裝在一模製化合物內的一第一晶粒及一第二晶粒,且該模製化合物填充側向於該第一晶粒與該第二晶粒之間的一空間。
- 如請求項11之多晶片模組,其中該蓋包括:一第一蓋部件,其跨越該第一晶粒上方;及一第二蓋部件,其跨越該第二晶粒上方。
- 如請求項12之多晶片模組,其中該第一蓋部件具有與該第二蓋部件不同的一化學組成物。
- 如請求項12之多晶片模組,其進一步包含在該第一蓋部件與該第二蓋部件之間的一間隙,其中該間隙係在側向於該第一晶粒與該第二晶粒之間的該空間的正上方。
- 如請求項14之多晶片模組,其中該間隙經填充。
- 如請求項1之多晶片模組:進一步包含一局部開口,其在該蓋之該蓋頂中;其中該第二組件包含封裝在一模製化合物內的一第一晶粒及一第二晶粒,且該模製化合物填充側向於該第一晶粒與該第二晶粒之間的一空間;且其中該局部開口係在側向於該第一晶粒與該第二晶粒之間的一空間的正上方。
- 如請求項1之多晶片模組,其中該蓋包含一向下突出的懸掛部分。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US202063002888P | 2020-03-31 | 2020-03-31 | |
US63/002,888 | 2020-03-31 | ||
US17/013,279 US11646302B2 (en) | 2020-03-31 | 2020-09-04 | Multiple chip module trenched lid and low coefficient of thermal expansion stiffener ring |
US17/013,279 | 2020-09-04 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW202147528A TW202147528A (zh) | 2021-12-16 |
TWI773130B true TWI773130B (zh) | 2022-08-01 |
Family
ID=77857563
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW111125267A TW202240798A (zh) | 2020-03-31 | 2021-02-08 | 多晶片模組溝槽化蓋及低熱膨脹係數加強環 |
TW110104737A TWI773130B (zh) | 2020-03-31 | 2021-02-08 | 多晶片模組溝槽化蓋及低熱膨脹係數加強環 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW111125267A TW202240798A (zh) | 2020-03-31 | 2021-02-08 | 多晶片模組溝槽化蓋及低熱膨脹係數加強環 |
Country Status (6)
Country | Link |
---|---|
US (2) | US11646302B2 (zh) |
EP (2) | EP4128332A1 (zh) |
KR (1) | KR20220124759A (zh) |
CN (1) | CN115136298A (zh) |
TW (2) | TW202240798A (zh) |
WO (1) | WO2021201990A1 (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7235752B2 (ja) * | 2018-08-03 | 2023-03-08 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置 |
KR20210059417A (ko) * | 2019-11-15 | 2021-05-25 | 삼성전자주식회사 | 보강 구조물을 갖는 반도체 패키지 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010023533A1 (en) * | 1996-11-08 | 2001-09-27 | Sylvester Mark F. | Method of increasing package reliability using package lids with plane CTE Gradients |
US20150001701A1 (en) * | 2013-06-27 | 2015-01-01 | International Business Machines Corporation | Multichip module with stiffing frame and associated covers |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5881945A (en) * | 1997-04-30 | 1999-03-16 | International Business Machines Corporation | Multi-layer solder seal band for semiconductor substrates and process |
JP2005116762A (ja) | 2003-10-07 | 2005-04-28 | Fujitsu Ltd | 半導体装置の保護方法及び半導体装置用カバー及び半導体装置ユニット及び半導体装置の梱包構造 |
TWI239655B (en) | 2004-02-23 | 2005-09-11 | Siliconware Precision Industries Co Ltd | Photosensitive semiconductor package with support member and method for fabricating the same |
US7585702B1 (en) | 2005-11-08 | 2009-09-08 | Altera Corporation | Structure and assembly procedure for low stress thin die flip chip packages designed for low-K Si and thin core substrate |
US9202769B2 (en) | 2009-11-25 | 2015-12-01 | Stats Chippac, Ltd. | Semiconductor device and method of forming thermal lid for balancing warpage and thermal management |
US8299633B2 (en) | 2009-12-21 | 2012-10-30 | Advanced Micro Devices, Inc. | Semiconductor chip device with solder diffusion protection |
JP5733893B2 (ja) * | 2009-12-22 | 2015-06-10 | 新光電気工業株式会社 | 電子部品装置 |
US8900927B2 (en) * | 2010-08-16 | 2014-12-02 | International Business Machines Corporation | Multichip electronic packages and methods of manufacture |
US8976529B2 (en) * | 2011-01-14 | 2015-03-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lid design for reliability enhancement in flip chip package |
US20130001740A1 (en) | 2011-06-30 | 2013-01-03 | Stmicroelectronics Pte Ltd. | Heat spreader for thermally enhanced flip-chip ball grid array package |
US9204548B2 (en) | 2012-03-14 | 2015-12-01 | Cisco Technology, Inc | Electronic devices mounted on multiple substrates |
US20140091461A1 (en) | 2012-09-30 | 2014-04-03 | Yuci Shen | Die cap for use with flip chip package |
US9269694B2 (en) | 2013-12-11 | 2016-02-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages with thermal management features for reduced thermal crosstalk and methods of forming same |
US9735043B2 (en) | 2013-12-20 | 2017-08-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor packaging structure and process |
US10163754B2 (en) * | 2013-12-26 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lid design for heat dissipation enhancement of die package |
US9330999B2 (en) * | 2014-06-05 | 2016-05-03 | Intel Corporation | Multi-component integrated heat spreader for multi-chip packages |
JP6314731B2 (ja) * | 2014-08-01 | 2018-04-25 | 株式会社ソシオネクスト | 半導体装置及び半導体装置の製造方法 |
KR102588807B1 (ko) | 2016-12-15 | 2023-10-13 | 쑤저우 레킨 세미컨덕터 컴퍼니 리미티드 | 반도체 소자 패키지 및 그 제조방법, 자동 초점 장치 |
US10643938B2 (en) * | 2017-05-31 | 2020-05-05 | Intel Corporation | Standoff spacers for managing bondline thickness in microelectronic packages |
US11676873B2 (en) | 2017-06-30 | 2023-06-13 | Intel Corporation | Semiconductor package having sealant bridge |
WO2019066993A1 (en) | 2017-09-30 | 2019-04-04 | Intel Corporation | LOWERING MITIGATION STRUCTURES CREATED ON A SUBSTRATE USING HIGH-PERFORMANCE ADDITIVE MANUFACTURE |
US10681846B2 (en) | 2018-04-19 | 2020-06-09 | Google Llc | Cooling electronic devices in a data center |
JP7235752B2 (ja) | 2018-08-03 | 2023-03-08 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置 |
KR20200145267A (ko) | 2019-06-21 | 2020-12-30 | 삼성전자주식회사 | 반도체 패키지 |
-
2020
- 2020-09-04 US US17/013,279 patent/US11646302B2/en active Active
-
2021
- 2021-02-08 TW TW111125267A patent/TW202240798A/zh unknown
- 2021-02-08 TW TW110104737A patent/TWI773130B/zh active
- 2021-02-10 EP EP21711077.4A patent/EP4128332A1/en active Pending
- 2021-02-10 CN CN202180015001.1A patent/CN115136298A/zh active Pending
- 2021-02-10 KR KR1020227027054A patent/KR20220124759A/ko not_active Application Discontinuation
- 2021-02-10 EP EP23177407.6A patent/EP4235777A3/en active Pending
- 2021-02-10 WO PCT/US2021/017445 patent/WO2021201990A1/en unknown
-
2023
- 2023-03-31 US US18/194,236 patent/US20230317708A1/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010023533A1 (en) * | 1996-11-08 | 2001-09-27 | Sylvester Mark F. | Method of increasing package reliability using package lids with plane CTE Gradients |
US20150001701A1 (en) * | 2013-06-27 | 2015-01-01 | International Business Machines Corporation | Multichip module with stiffing frame and associated covers |
Also Published As
Publication number | Publication date |
---|---|
EP4128332A1 (en) | 2023-02-08 |
US20210305227A1 (en) | 2021-09-30 |
EP4235777A3 (en) | 2024-02-28 |
TW202147528A (zh) | 2021-12-16 |
TW202240798A (zh) | 2022-10-16 |
US11646302B2 (en) | 2023-05-09 |
US20230317708A1 (en) | 2023-10-05 |
CN115136298A (zh) | 2022-09-30 |
EP4235777A2 (en) | 2023-08-30 |
WO2021201990A1 (en) | 2021-10-07 |
KR20220124759A (ko) | 2022-09-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20230317708A1 (en) | Multiple Chip Module Trenched Lid and Low Coefficient of Thermal Expansion Stiffener Ring | |
TWI767099B (zh) | 腔體封裝 | |
US20190348401A1 (en) | Semiconductor device assembly with heat transfer structure formed from semiconductor material | |
US9355997B2 (en) | Integrated circuit assemblies with reinforcement frames, and methods of manufacture | |
US6873041B1 (en) | Power semiconductor package with strap | |
US20180358280A1 (en) | Methods and apparatus for thermal interface material (tim) bond line thickness (blt) reduction and tim adhesion enhancement for efficient thermal management | |
US20140091461A1 (en) | Die cap for use with flip chip package | |
US11289401B2 (en) | Semiconductor package | |
TWI680543B (zh) | 具有底部填充控制腔之半導體裝置總成 | |
KR19990069643A (ko) | 히트 스프레드를 갖는 리드 프레임 및 이를 이용한반도체 패키지 | |
US20050199998A1 (en) | Semiconductor package with heat sink and method for fabricating the same and stiffener | |
TWI719205B (zh) | 晶片封裝製程 | |
CN103635999A (zh) | 半导体装置 | |
TWI834260B (zh) | 凹陷蓋及環設計、及蓋局部周邊強化設計 | |
TWI817399B (zh) | 半導體封裝及其形成方法 | |
WO2022007506A1 (zh) | 封装结构和封装结构制造方法 | |
TW202326954A (zh) | 凹陷蓋及環設計、及蓋局部周邊強化設計 | |
TW202301611A (zh) | 封裝組件 | |
US8564115B2 (en) | Package structure having micro-electromechanical element | |
TWI771242B (zh) | 雙晶片半導體封裝及其製備方法 | |
TWI778632B (zh) | 半導體封裝以及其製造方法 | |
US20230386961A1 (en) | Semiconductor package and manufacturing method thereof | |
KR20060066214A (ko) | 칩 스택 패키지 | |
KR20220065292A (ko) | 반도체 패키지 및 그의 제조 방법 | |
KR20060131191A (ko) | 칩 스택 패키지 |