TWI770920B - 半導體結構及其形成方法 - Google Patents

半導體結構及其形成方法 Download PDF

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TWI770920B
TWI770920B TW110111830A TW110111830A TWI770920B TW I770920 B TWI770920 B TW I770920B TW 110111830 A TW110111830 A TW 110111830A TW 110111830 A TW110111830 A TW 110111830A TW I770920 B TWI770920 B TW I770920B
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Taiwan
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semiconductor
source
dielectric
silicide
layer
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TW110111830A
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TW202209448A (zh
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黃麟淯
游力蓁
張家豪
莊正吉
程冠倫
王志豪
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台灣積體電路製造股份有限公司
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Abstract

一種形成半導體結構的方法，包括：提供半導體結構，包括基板；鰭片；源極/汲極（S/D）部件；隔離結構鄰近鰭片的側壁；一個或多個通道層在第一介電層上並連接S/D部件；以及閘極結構齒合（engaging）一個或多個通道層；從結構的背側薄化結構直到露出鰭片；選擇性蝕刻鰭片以形成溝槽，溝槽露出S/D部件的表面、第一介電層以及隔離結構；在S/D部件上形成矽化物部件；選擇性沉積抑制劑在矽化物部件上，而未被沉積在第一介電層的表面上以及隔離結構上；選擇性沉積介電襯層在隔離結構以及第一介電層的表面上，而未沉積在抑制劑上；以及選擇性去除抑制劑。

Description

半導體結構及其形成方法
本發明實施例係有關於一種半導體結構及其形成方法，且特別關於一種具有背側金屬部件的半導體結構及其形成方法。
常規上，積體電路(IC)是以堆疊的方式建構，其具有處於最低水平處的電晶體以及在電晶體上的互連結構(導孔和導線)以提供電晶體的連接。電源軌(例如電壓源和接地的金屬線)也位於電晶體上方，並且可以是互連結構的一部分。隨著積體電路的不斷微縮化，電源軌也隨之縮小。這不可避免地導致跨電源軌的壓降增加，以及積體電路的功耗增加。因此，儘管半導體製造中現有的方法通常已經足以滿足其預期目的，但是它們並非在所有方面都完全令人滿意。如何在IC的背側形成具有減小電阻的電源軌和導孔為令人感興趣的領域之一。
本揭露一些實施例提供一種形成半導體結構的方法，包括：提供半導體結構，半導體結構具有前側與背側，半導體結構包括基板；半導體鰭片， 在基板上；兩個源極/汲極(S/D)部件，在半導體鰭片上；第一介電層，在半導體鰭片上；隔離結構，鄰近半導體鰭片的側壁；一個或多個通道半導體層，在第一介電層上並連接兩個源極/汲極部件；以及閘極結構，齒合(engaging)一個或多個通道半導體層，其中基板在半導體結構的背側，並且閘極結構在半導體結構的前側；從半導體結構的背側薄化半導體結構，直到露出半導體鰭片；從半導體結構的背側選擇性蝕刻半導體鰭片以形成溝槽，其中溝槽露出兩個源極/汲極部件的表面、第一介電層的表面以及隔離結構的側壁；在源極/汲極部件的表面上形成矽化物部件；在溝槽中選擇性沉積抑制劑，其中抑制劑被沉積在矽化物部件上，而未被沉積在第一介電層的表面上以及隔離結構的側壁上；在溝槽中選擇性沉積介電襯層，其中介電襯層被沉積在隔離結構的側壁上以及在第一介電層的表面上，而未被沉積在抑制劑上；以及選擇性去除抑制劑。
本揭露另一些實施例提供一種形成半導體結構的方法，包括：提供半導體結構，半導體結構具有基板；半導體鰭片，在基板上；兩個源極/汲極部件，在半導體鰭片上；隔離結構，在半導體鰭片的側壁上；介電蓋層，在半導體鰭片上；一個或多個通道半導體層，在介電蓋層上；以及閘極結構，齒合一個或多個通道半導體層；薄化半導體結構，直到露出半導體鰭片；選擇性蝕刻半導體鰭片以形成溝槽，其中溝槽露出兩個源極/汲極部件的表面、介電蓋層的表面以及隔離結構的側壁；在源極/汲極部件的表面上形成矽化物部件；沉積抑制劑在矽化物部件上，而未在介電蓋層的表面上以及隔離結構的側壁上；沉積介電襯層在隔離結構的側壁上以及介電蓋層的表面上，而未在抑制劑上；選擇性去除抑制劑；以及在溝槽中形成導孔結構。
本揭露又一些實施例提供一種半導體結構，包括：兩個源極/汲極 部件；一個或多個通道半導體層，連接兩個源極/汲極部件；閘極結構，齒合一個或多個通道半導體層，其中兩個源極/汲極部件、一個或多個通道半導體層以及閘極結構在半導體結構的前側；金屬軌(metal track)，在半導體結構的背側；第一介電層，在金屬軌與一個或多個通道半導體層之間；介電襯層，在第一介電層的表面上，並且與兩個源極/汲極部件的其中一個以第一間隙隔開；以及導孔結構，連接金屬軌至兩個源極/汲極部件的其中一個，其中導孔結構的一部分設置在第一間隙中。
100:方法
102:操作
104:操作
106:操作
108:操作
110:操作
112:操作
114:操作
116:操作
118:操作
120:操作
122:操作
124:操作
126:操作
200:半導體裝置
201:基板
203:底部自對準蓋層
204:半導體鰭片(半導體層)
215:通道半導體層
230:隔離結構
240:閘極堆疊
247:(外部)閘極間隔物
255:內部間隔物(內部間隔層)
260:源極/汲極部件
269:接觸蝕刻停止層
270:層間介電層
272:溝槽
273:矽化物部件
275:源極/汲極接觸件
276:介電層
277:互連層
278:通孔
280:矽化物部件
282:源極/汲極導孔
284:電源軌
302:抑制劑
304:介電襯層
327:角落區域
333:間隙
349:閘極介電層
350:閘極電極
352:自對準蓋層
356:蓋層
358:源極/汲極接觸導孔
360:遮罩
362:開口
370:載體
d1:厚度
d2:距離
d3:厚度
d5:厚度
以下將配合所附圖示詳述本揭露之各面向。應注意的是，依據在業界的標準做法，各種特徵並未按照比例繪製且僅用以說明例示。事實上，可能任意地放大或縮小單元的尺寸，以清楚地表現出本揭露的特徵。
第1A和1B圖係根據本揭露各種方面，繪示形成具有背側電源軌和背側導孔的半導體裝置的方法流程圖。
第2A、3A、4A、5A、6A、7A、8A、9A、10A、11A、12A和13A圖係根據一些實施例，繪示半導體裝置的一部分的俯視圖。
第2B、3B、4B、5B、6B、7B、8B、9B、10B、11B、12B和13B圖係根據一些實施例，分別繪示沿著第2A、3A、4A、5A、6A、7A、8A、9A、10A、11A、12A和13A圖中B-B線的半導體裝置的一部分的截面圖。
第2C、4C、5C、6C、7C、8C、9C、10C、11C、12C和13C圖係根據一些實施例，分別繪示沿著第2A、4A、5A、6A、7A、8A、9A、10A、11A、12A和13A圖中C-C線的半導體裝置的一部分的截面圖。
第2D、4D、5D、6D、7D、8D、9D、10D、11D、12D和13D圖係根據一些實施例，分別繪示沿著第2A、4A、5A、6A、7A、8A、9A、10A、11A、12A和13A圖中D-D線的半導體裝置的一部分的截面圖。
第2E、4E、5E、6E、7E、8E、9E、10E、11E、12E和13E圖係根據一些實施例，分別繪示沿著第2A、4A、5A、6A、7A、8A、9A、10A、11A、12A和13A圖中E-E線的半導體裝置的一部分的截面圖。
以下內容提供了許多不同實施例或範例，以實現本揭露實施例的不同部件。以下描述組件和配置方式的具體範例，以簡化本揭露實施例。當然，這些僅僅是範例，而非意圖限制本揭露實施例。舉例而言，在以下描述中提及於第二部件上方或其上形成第一部件，其可以包含第一部件和第二部件以直接接觸的方式形成的實施例，並且也可以包含在第一部件和第二部件之間形成額外的部件，使得第一部件和第二部件可以不直接接觸的實施例。此外，本揭露實施例可在各個範例中重複參考標號及/或字母。此重複是為了簡化和清楚之目的，其本身並非用於指定所討論的各個實施例及/或配置之間的關係。
再者，其中可能用到與空間相對用詞，例如「在......之下」、「下方」、「較低的」、「上方」、「較高的」等相似用詞，是為了便於描述圖式中一個(些)部件或特徵與另一個(些)部件或特徵之間的關係。空間相對用詞用以包括使用中或操作中的裝置之不同方位，以及圖式中所描述的方位。當裝置被轉向不同方位時(旋轉90度或其他方位)，其中所使用的空間相對形容詞也將依轉向後的方位來解釋。此外，此處所使用的用語「約」、「近似」等 類似用語描述數字或數字範圍時，該用語意欲涵蓋的數值是在合理範圍內包含所描述的數字，例如在所描述的數字之+/-10%之內，或本發明所屬技術領域中具有通常知識者理解的其他數值。例如，用語「約5nm」涵蓋從4.5nm至5.5nm、4.0nm至5.0nm等的尺寸範圍。
本揭露整體關於半導體結構和製造製程，更詳細而言，關於具有背側電源軌和背側導孔的半導體裝置。如上所述，IC中的電源軌需要進一步改進，以提供所需的性能提升並降低功耗。本揭露的目的包括在包含電晶體(例如，全繞式閘極(gate-all-around,GAA)電晶體及/或FinFET電晶體)的結構的背側提供電源軌(或電源佈線)，此外在結構的前側提供互連結構(也可以包括電源軌)。這增加結構中可用於直接連接到源極/汲極接觸件和導孔的金屬軌的數量。與沒有背側電源軌的現有結構相比，還增加閘極密度以實現更大的裝置整合度。背側電源軌的尺寸可以比結構前側的第一層金屬(M0)軌的尺寸更寬，這有利地降低電源軌的電阻。本揭露還提供一種背側導孔結構，用於將背側電源軌連接到前側的源極/汲極部件。背側導孔結構具有襯層，襯層沉積在背側通孔的側壁上，而未沉積在背側通孔的底表面上。這消除了在將導體沉積到背側通孔中時，穿透襯層的步驟，從而防止對源極/汲極部件背側的損壞。其也增加用於矽化的源極/汲極部件的面積，並且增加源極/汲極接觸面積，從而減小晶圓背側的源極/汲極接觸電阻。以下結合附圖描述本揭露的結構和製造方法的細節，附圖根據一些實施例示出製造GAA裝置的製程。GAA裝置是指具有垂直堆疊的水平取向的多通道電晶體的裝置，例如奈米線電晶體和奈米片電晶體。GAA裝置具有更好的閘極控制能力、更低的漏電流以及完整的FinFET裝置佈局兼容性，因此有望將CMOS推向發展路程圖(roadmap)的下一個階段。為了簡 單起見，本揭露使用GAA裝置作為示例。本領域技術人員應該理解，他們可以容易地將本揭露用作設計或修改其他製程和結構(例如FinFET裝置)的基礎，為了實現本揭露介紹的實施例的相同目的及/或實現相同的優點。
第1A和1B圖係根據本揭露的各種方面，用於製造半導體裝置的方法100的流程圖。本揭露考慮額外的製程。可以在方法100之前、之中以及之後提供其他操作，並且對於方法100的額外實施例，可以移動、替換或消除所描述的一些操作。
根據一些實施例，以下結合第2A至13E圖描述方法100，示出根據方法100的各種製造步驟的半導體裝置(或半導體結構)200的各種俯視圖和截面圖。在一些實施例中，裝置200是IC晶片、晶片上系統(system on chip,SoC)或其部分的一部分，其包括各種被動和主動微電子裝置，例如電阻、電容、電感、二極體、p型場效電晶體(p-type field effect transistors,PFETs)、n型場效電晶體(n-type field effect transistors,NFETs)、鰭式場效電晶體(FinFET)、奈米片FET、奈米線FET、其他類型的多閘極FET、金屬氧化物半導體場效電晶體(metal-oxide semiconductor field effect transistors,MOSFETs)、互補式金屬氧化物半導體(complementary metal-oxide semiconductor,CMOS)電晶體、雙極接面電晶體(bipolar junction transistors,BJTs)、橫向擴散金屬氧化物半導體(laterally diffused MOS,LDMOS)電晶體、高壓電晶體、高頻電晶體、記憶體裝置、其他合適的組件、或其組合。為了清楚起見，已經簡化第2A至13E圖以更好地理解本揭露的發明構思。可以在裝置200中增加額外的部件，並且在裝置200的其他實施例中可以替換、修改或消除以下描述的一些部件。
在操作102，方法100(第1A圖)提供半導體裝置200，半導體裝 置200具有基板201和建構在基板201的前側的電晶體。第2A圖示出裝置200的俯視圖，第2B、2C、2D和2E圖分別示出沿著第2A圖中的B-B線、C-C線、D-D線和E-E線的部分裝置200的截面圖。詳細而言，沿著半導體鰭片204的長度方向(方向“X”)截取B-B線，沿著閘極堆疊240的長度方向(方向“Y”)截取C-C線，D-D線切入電晶體的源極區域並且與閘極堆疊240平行，而E-E線切入電晶體的汲極區域並且與閘極堆疊240平行。第3A至13A圖中的B-B線、C-C線、D-D線以及E-E線相似地配置。
參照第2A至2E圖，半導體裝置200包括在其背側的基板201以及建構在基板201前側上的各種元件。這些元件包括基板201上方的隔離結構230；從基板201延伸並與隔離結構230相鄰的半導體鰭片204；在半導體鰭片204上方的兩個磊晶源極/汲極(S/D)部件260；一個或多個通道半導體層215懸置在半導體鰭片204上方，並連接兩個源極/汲極部件260；兩個源極/汲極部件260之間的閘極堆疊240，其包繞每個通道半導體層215；以及底部自對準蓋(bottom self-aligned capping,B-SAC)層203設置在半導體鰭片204與通道層215和閘極堆疊240兩者之間。半導體裝置200還包括內部間隔物255，在源極/汲極部件260和閘極堆疊240之間；(外部)閘極間隔物247，在閘極堆疊240的側壁上和最頂部的通道層215上；接觸蝕刻停止層(contact etch stop layer,CESL)269，相鄰閘極間隔物247並且在磊晶源極/汲極部件260和隔離結構230上；層間介電(inter-layer dielectric,ILD)層270，在CESL 269上。在閘極堆疊240上，半導體裝置200還包括自對準蓋層352。在源極/汲極部件260上方，半導體裝置200進一步包括矽化物部件273、源極/汲極接觸件275、介電源極/汲極蓋層356以及源極/汲極接觸導孔358。在所描繪的實施例中，源極/汲極蓋層356設置在源極部件260上，並且源極/汲極接觸 導孔358設置在汲極部件260上。在替代實施例中，源極/汲極蓋層356可以設置在汲極部件260上，並且源極/汲極接觸導孔358可以設置在源極部件260上。在一些實施例中，源極/汲極蓋層356可以設置在源極和汲極部件260上。在一些實施例中，源極/汲極接觸導孔358可以設置在源極和汲極部件260上。
參照第3A和3B圖，半導體裝置200進一步包括一個或多個互連層(以277表示)，其具有嵌入介電層中的導線和導孔。一個或多個互連層連接各個電晶體的閘極、源極和汲極以及裝置200中的其他電路，以部分或整體形成積體電路。半導體裝置200可以進一步包括鈍化層、黏著層及/或建構在半導體裝置200前側上的其他層。這些層和一個或多個互連層共同用標記277表示。應注意的是，半導體裝置200在第3B圖中上下顛倒。以下進一步描述半導體裝置200的各種元件。
在一個實施例中，基板201是塊體矽基板(即，包括塊狀單晶矽)。在各種實施例中，基板201可以包括其他半導體材料，例如鍺(Ge)、碳化矽(silicon carbide)、砷化鎵(GaAs)、磷化鎵(GaP)、磷化銦(InP)、砷化銦(InAs)、銻化銦(InSb)，矽鍺(SiGe)、磷砷化鎵(GaAsP)、砷化鋁銦(AlInAs)、砷化鋁鎵(AlGaAs)、砷化鎵銦(GaInAs)、磷化鎵銦(GaInP)、磷砷化鎵銦(GaInAsP)或其組合。在替代實施例中，基板201是絕緣體上半導體基板、例如絕緣體上矽(silicon-on-insulator,SOI)基板、絕緣體上矽鍺(silicon germanium-on-insulator,SGOI)基板或絕緣體上鍺(germanium-on-insulator,GOI)基板。
在一些實施例中，半導體鰭片204可以包括矽、矽鍺、鍺或其他合適的半導體，並且可以摻雜n型摻質或p型摻質。鰭片204可以通過任何合適的 方法來圖案化。例如，可以使用一種或多種微影製程來圖案化鰭片204，包括雙重圖案化製程或多重圖案化製程。一般來說，雙重圖案化或多重圖案化製程結合了微影製程與自對準製程，以創建出例如，比使用單一、直接微影製程所得的節距更小的圖案。例如，在一實施例中，在基板上方形成犧牲層，並使用微影製程對其進行圖案化。使用自對準製程在圖案化的犧牲層旁邊形成間隔物。之後去除犧牲層，然後可以使用剩餘的間隔物或心軸作為遮罩以圖案化鰭片204。例如，掩膜元件可以用於將凹口蝕刻到基板201上方或之中的半導體層中，從而將鰭片204保留在基板201上。蝕刻製程可以包括乾式蝕刻、濕式蝕刻、反應離子蝕刻(reactive ion etching,RIE)及/或其他合適的製程。例如，乾式蝕刻製程可以實施含氧氣體、含氟氣體(例如，CF4、SF6、CH2F2、CHF3及/或C2F6)、含氯氣體(例如，Cl2、CHCl3、CCl4及/或BCl3)、含溴氣體(例如，HBr及/或CHBr3)、含碘氣體、其他合適的氣體及/或電漿、及/或其組合。例如，濕式刻蝕製程可以包括在稀釋氫氟酸(diluted hydrofluoric acid,DHF)；氫氧化鉀(KOH)溶液；氨；含有氫氟酸(HF)、硝酸(HNO3)及/或乙酸(CH3COOH)的溶液；或其他合適的濕式蝕刻劑中進行蝕刻。許多其他實施例以形成鰭片204的方法可以是合適的。
隔離部件230可以包括氧化矽、氮化矽、氮氧化矽、其他合適的隔離材料(例如，包括矽、氧、氮、碳或其他合適的隔離成分)或其組合。隔離部件230可以包括不同的結構，例如淺溝槽隔離(shallow trench isolation,STI)結構及/或深溝槽隔離(deep trench isolation,DTI)結構。在一個實施例中，可以通過用絕緣體材料填充鰭片204之間的溝槽(例如，通過使用CVD製程或旋塗玻璃製程)，執行化學機械研磨(chemical mechanical polishing,CMP)製程以去 除多餘的絕緣體材料及/或平坦化絕緣體材料層的頂表面，並回蝕絕緣體材料層以形成隔離部件230。在一些實施例中，隔離部件230包括多層結構，例如設置在熱氧化物襯層上方的氮化矽層。
源極/汲極部件260包括磊晶成長的半導體材料，例如磊晶成長的矽、鍺或矽鍺。源極/汲極部件260可以通過任何磊晶製程，包括化學氣相沉積(chemical vapor deposition,CVD)技術(例如，氣相磊晶及/或超高真空CVD(Ultra-High Vacuum CVD))，分子束磊晶、其他合適的磊晶成長製程或其組合形成。源極/汲極部件260可以摻雜有n型摻質及/或p型摻質。在一些實施例中，對於n型電晶體，源極/汲極部件260包括矽並且可以摻雜有碳、磷、砷、其他n型摻質或其組合(例如，形成Si：C磊晶源極/汲極部件、Si：P磊晶源極/汲極部件或Si：C：P磊晶源極/汲極部件)。在一些實施例中，對於p型電晶體，源極/汲極部件260包括矽鍺或鍺，並且可以摻雜有硼、其他p型摻質或其組合(例如，形成Si：Ge：B磊晶源極/汲極部件)。源極/汲極部件260可以包括具有不同程度的摻質密度的多個磊晶半導體層。在一些實施例中，執行退火製程(例如，快速熱退火(rapid thermal annealing,RTA)及/或激光退火)以活化磊晶源極/汲極部件260中的摻質。
在一些實施例中，通道層215包括合適於電晶體通道的半導體材料，例如矽、矽鍺或其他半導體材料。在各種實施例中，通道層215可以是棒狀、條狀、片狀或其他形狀。在一個實施例中，通道層215最初是半導體層的堆疊的一部分，其半導體層的堆疊包括通道層215和其他(犧牲)半導體層交替地逐層堆疊。犧牲半導體層和通道層215包括不同的材料組成(例如不同的半導體材料、不同的原子百分比及/或不同的重量百分比)以實現蝕刻選擇性。在形成閘 極堆疊240的閘極替換製程期間，選擇性地去除犧牲半導體層，從而將通道層215懸置在半導體鰭片204上方。
在一些實施例中，內部間隔層255包括介電材料，其介電材料包括矽、氧、碳、氮、其他合適的材料或其組合(例如，氧化矽、氮化矽、氮氧化矽、碳化矽或碳氮氧化矽)。在一些實施例中，內部間隔層255包括低介電常數介電材料，例如本揭露所述的低介電常數介電材料。可以通過沉積和蝕刻製程來形成內部間隔層255。例如，在蝕刻源極/汲極溝槽之後，並且在從源極/汲極溝槽磊晶成長源極/汲極部件260之前，可以使用蝕刻製程來在相鄰通道層215之間凹蝕犧牲半導體層以在相鄰的通道層215之間垂直地形成間隙。然後，沉積一種或多種介電材料(例如使用CVD或ALD)以填充間隙。執行另一蝕刻製程以去除間隙外的介電材料，從而形成內部間隔層255。
在一些實施例中，B-SAC層203可以包括La2O3、Al2O3、SiOCN、SiOC、SiCN、SiO2、ZnO、ZrN、Zr2Al3O9、TiO2、TaO2、ZrO2、HfO2、Si3N4、Y2O3、AlON、TaCN、ZrSi以及其他合適的材料的一種或多種。在一些實施例中，B-SAC層203可以包括低介電常數介電材料，例如包括Si、O、N和C的介電材料。示例的低介電常數介電材料包括：摻氟矽酸鹽玻璃(fluoride-doped silicate glass,FSG)、摻碳氧化矽、Black Diamond®(應用材料，加州聖塔克拉拉)、乾凝膠(xerogel)、氣凝膠(aerogel)、非晶質氟化碳(amorphous fluorinated carbon)、聚對二甲苯(parylene)、苯並環丁烯(benzocyclobutene,BCB)、SiLK®(陶氏化學，密西根米特蘭)、聚醯亞胺或其組合。可以使用CVD、ALD、PVD或氧化來沉積B-SAC層203。在一個實施例中，首先將B-SAC層203沉積在半導體鰭片204上，並使用與圖案化半導體鰭片204相同的製程來圖案化B-SAC層203。在另 一個實施例中，首先將犧牲半導體層(例如SiGe)沉積在半導體鰭片204上，並使用與圖案化半導體鰭片204相同的製程來圖案化犧牲半導體層。在形成閘極堆疊240的閘極替換製程期間，去除犧牲層並用B-SAC層203替換。B-SAC層203用於將通道層215和閘極堆疊240與將在後續製程中形成的背側導孔隔離。在一些實施例中，B-SAC層203可具有在0.5nm至約50nm範圍的厚度d5。在一些實施例中，如果B-SAC層203太薄(例如小於0.5nm)，則其可能不能提供通道層215和閘極堆疊240足夠的隔離。在一些實施例中，如果B-SAC層203太厚(例如，大於50nm)，則背側導孔將變長並且其電阻將變高，這將在以下進一步討論。
在所描繪的實施例中，閘極堆疊240包括閘極介電層349和閘極電極350。閘極介電層349可以包括高介電常數介電材料，例如HfO2、HfSiO、HfSiO4、HfSiON、HfLaO、HfTaO、HfTiO、HfZrO、HfAlOx、ZrO、ZrO2、ZrSiO2、AlO、AlSiO、Al2O3、TiO、TiO2、LaO、LaSiO、Ta2O3、Ta2O5、Y2O3、SrTiO3、BaZrO、BaTiO3(BTO)、(Ba、Sr)TiO3(BST)、Si3N4、二氧化鉿-氧化鋁(HfO2-Al2O3)合金、其他合適的高介電常數介電材料或其組合。高介電常數介電材料通常是指具有高介電常數的介電材料，例如，介電常數大於氧化矽的介電常數(介電常數約為3.9)。可以通過化學氧化、熱氧化、原子層沉積(atomic layer deposition,ALD)、化學氣相沉積(CVD)及/或其他合適的方法來形成閘極介電層349。在一些實施例中，閘極堆疊240還包括在閘極介電層349和通道層215之間的界面層。界面層可以包括二氧化矽、氮氧化矽或其他合適的材料。在一些實施例中，閘極電極層350包括n型或p型功函數層和金屬填充層。例如，n型功函數層可以包括具有足夠低的有效功函數的金屬，例如鈦、鋁、碳化鉭、氮化碳化鉭、氮化鉭矽或其組合。例如，p型功函數層可以包括具有足夠大的有 效功函數的金屬，例如氮化鈦、氮化鉭、釕、鉬、鎢、鉑或其組合。例如，金屬填充層可以包括鋁、鎢、鈷、銅及/或其他合適的材料。可以通過CVD、PVD、電鍍及/或其他合適的製程來形成閘極電極層350。由於閘極堆疊240包括高介電常數介電層和金屬層，因此其也被稱為高介電常數金屬閘極。
在一個實施例中，閘極間隔物247包括介電材料，例如包括矽、氧、碳、氮、其他合適材料或其組合的介電材料(例如氧化矽、氮化矽、氮氧化矽(SiON)、碳化矽、碳氮化矽(SiCN)、碳氧化矽(SiOC)、碳氮氧化矽(SiOCN))。在一個實施例中，閘極間隔物247可以包括La2O3、Al2O3、SiOCN、SiOC、SiCN、SiO2、SiC、ZnO、ZrN、Zr2Al3O9、TiO2、TaO2、ZrO2、HfO2、Si3N4、Y2O3、AlON、TaCN、ZrSi或其他合適的材料。例如，包括矽和氮的介電層，例如氮化矽層，可以沉積在虛設閘極堆疊(其隨後被高介電常數金屬閘極240替換)上，並且隨後被蝕刻(例如，非等向性蝕刻)以形成閘極間隔物247。在一些實施例中，閘極間隔物247包括多層結構，例如包括氮化矽的第一介電層和包括氧化矽的第二介電層。在一些實施例中，與閘極堆疊240相鄰地形成多於一組的間隔物，例如密封間隔物、偏置間隔物(offset spacers)、犧牲間隔物、虛設間隔物及/或主要間隔物。在一些實施例中，閘極間隔物247可以具有例如約1nm至約40nm的厚度。
在一些實施例中，SAC層352包括La2O3、Al2O3、SiOCN、SiOC、SiCN、SiO2、SiC、ZnO、ZrN、Zr2Al3O9、TiO2、TaO2、ZrO2、HfO2、Si3N4、Y2O3、AlON、TaCN、ZrSi或其他合適的材料。SAC層352保護閘極堆疊240免於用在蝕刻源極/汲極接觸孔的蝕刻和CMP製程。可以通過凹蝕閘極堆疊240並且可選地凹蝕閘極間隔物247，在凹陷的閘極堆疊240上方並且可選地在凹陷的閘極 間隔物247上方沉積一種或多種介電材料，對一種或多種介電材料進行CMP製程以形成SAC層352。SAC層352的厚度可以例如在大約3nm至大約30nm的範圍。
在一些實施例中，CESL 269可以包括La2O3、Al2O3、SiOCN、SiOC、SiCN、SiO2、SiC、ZnO、ZrN、Zr2Al3O9、TiO2、TaO2、ZrO2、HfO2、Si3N4、Y2O3、AlON、TaCN、ZrSi或其他合適的材料，並且可以通過CVD、PVD、ALD或其他合適的方法形成。ILD層270可以包括四乙基原矽酸鹽(tetraethylorthosilicate,TEOS)氧化物、未摻雜的矽酸鹽玻璃或摻雜的氧化矽，例如硼磷矽玻璃(borophosphosilicate glass,BPSG)、摻氟石英玻璃(fluoride-doped silica glass,FSG)、磷矽酸鹽玻璃(phosphosilicate glass,PSG)、摻硼矽玻璃(boron doped silicon glass,BSG)、低介電常數介電材料、其他合適的介電材料或其組合。ILD 270可以通過PECVD(電漿輔助CVD)、FCVD(流動式CVD)或其他合適的方法形成。
在一些實施例中，矽化物部件273可以包括矽化鈦(TiSi)、矽化鎳(NiSi)、矽化鎢(WSi)、矽化鎳鉑(NiPtSi)、矽化鎳鉑鍺(NiPtGeSi)、矽化鎳鍺(NiGeSi)、矽化鐿(YbSi)、矽化鉑(PtSi)、矽化銥(IrSi)、矽化鉺(ErSi)、矽化鈷(CoSi)或其他合適的化合物。
在一實施例中，源極/汲極接觸件275可以包括導電阻障層和在導電阻障層上方的金屬填充層。導電阻擋層可以包括鈦(Ti)、鉭(Ta)、鎢(W)、鈷(Co)、釕(Ru)或導電氮化物，例如氮化鈦(TiN)、氮化鈦鋁(TiAlN)、氮化鎢(WN)、氮化鉭(TaN)或其組合，並且可以通過CVD、PVD、ALD及/或其他合適的製程形成。金屬填充層可以包括鎢(W)、鈷(Co)、鉬(Mo)、釕(Ru)、鎳(Ni)、銅(Cu)或其他金屬，並且可以通過CVD、PVD、ALD、 電鍍或其他合適的製程形成。在一些實施例中，可以在源極/汲極接觸件275中省略導電阻障層。
在一些實施例中，蓋層356包括La2O3、Al2O3、SiOCN、SiOC、SiCN、SiO2、SiC、ZnO、ZrN、Zr2Al3O9、TiO2、TaO2、ZrO2、HfO2、Si3N4、Y2O3、AlON、TaCN、ZrSi或其他合適的材料。蓋層356保護源極/汲極接觸件275免受蝕刻和CMP製程的影響，並且使源極/汲極接觸件275與在其上形成的互連結構隔離。蓋層356可以具有例如在大約3nm至大約30nm的範圍的厚度。在一些實施例中，例如，在蓋層356的形成期間，SAC層352和蓋層356包括不同的材料以實現蝕刻選擇性。
在一個實施例中，源極/汲極接觸導孔358可以包括導電阻障層和在導電阻障層上方的金屬填充層。導電阻擋層可以包括鈦(Ti)、鉭(Ta)、鎢(W)、鈷(Co)、釕(Ru)或導電氮化物，例如氮化鈦(TiN)、氮化鈦鋁(TiAlN)、氮化鎢(WN)、氮化鉭(TaN)或其組合，並且可以通過CVD、PVD、ALD及/或其他合適的製程形成。金屬填充層可以包括鎢(W)、鈷(Co)、鉬(Mo)、釕(Ru)、鎳(Ni)、銅(Cu)或其他金屬，並且可以通過CVD、PVD、ALD、電鍍或其他合適的製程形成。在一些實施例中，可以在源極/汲極接觸導孔358中省略導電阻障層。
在操作104，方法100(第1A圖)將裝置200上下顛倒，並將裝置200的前側附接到載體370，如第3B圖所示。這使得可以從裝置200的背側進行進一步製程。操作104可以使用任何合適的附接製程，例如直接鍵合、混合鍵合(hybrid bonding)、使用黏著劑或其他鍵合方法。操作104可以進一步包括對準、退火及/或其他製程。在一些實施例中，載體370可以是矽晶圓。在第2A至13E圖 中，“z”方向從裝置200的背側指向裝置200的前側，而“-z”方向從裝置200的前側指向裝置200的背側。
在操作106，方法100(第1A圖)從裝置200的背側薄化裝置200，直到半導體鰭片204和隔離結構230從裝置200的背側露出。根據一個實施例，在第4A-4E圖中示出所得的結構。為簡化起見，第4C、4D和4E圖省略一些已經在第4B圖中顯示的部件，詳細而言為層277和載體370。薄化製程可以包括機械研磨製程及/或化學薄化製程。在機械研磨製程中，可以首先從基板201上去除大量的基板材料。之後，化學薄化製程可以將蝕刻化學品施加到基板201的背側，以進一步薄化基板201。
在操作108，方法100(第1A圖)選擇性地蝕刻半導體層204，以在閘極堆疊240和源極/汲極部件260的背側上形成溝槽272。溝槽272從背側暴露出源極/汲極部件260的表面。在本實施例中，操作108進一步在源極/汲極部件260的表面上形成矽化物部件280。根據一個實施例，在第5A-5E圖中示出所得的結構。在本實施例中，操作108應用蝕刻製程，其蝕刻製程被調整為對半導體層204的材料進行選擇性的蝕刻製程，而未(或最少)蝕刻閘極堆疊240、隔離結構230和B-SAC層203。在本實施例中，蝕刻製程也蝕刻源極/汲極部件260以使其凹陷至與隔離結構230和CESL 269之間的界面相等或更低的水平。這是為了準備溝槽272以用於隨後的襯層沉積。在一些實施例中，操作108可以應用不只一個蝕刻製程。例如，可以應用第一蝕刻製程以選擇性地去除半導體鰭片204，然後應用第二蝕刻製程以選擇性地凹蝕源極/汲極部件260至期望的水平，其中第一蝕刻製程和第二蝕刻製程使用不同的蝕刻參數，例如使用不同的蝕刻劑。蝕刻製程可以是乾式蝕刻、濕式蝕刻、反應離子蝕刻或其他蝕刻方法。B-SAC層203保護閘 極堆疊240免受一種或多種蝕刻製程的影響。在一實施例中，操作108包括將一種或多種金屬沉積到溝槽272中，對裝置200執行退火製程以引起一種或多種金屬與源極/汲極部件260之間的反應以產生矽化物部件280，以及去除一種或多種金屬的未反應部分，從而在溝槽272中留下矽化物部件280。一種或多種金屬可以包括鈦(Ti)、鉭(Ta)、鎢(W)、鎳(Ni)、鉑(Pt)、鐿(Yb)、銥(Ir)、鉺(Er)、鈷(Co)或其組合(例如，兩種或多種金屬的合金)，並且可以使用CVD、PVD、ALD或其他合適的方法進行沉積。矽化物部件280可以包括矽化鈦(TiSi)、矽化鎳(NiSi)、矽化鎢(WSi)、矽化鎳鉑(NiPtSi)、矽化鎳鉑鍺(NiPtGeSi)、矽化鎳鍺(NiGeSi)、矽化鐿(YbSi)、矽化鉑(PtSi)、矽化銥(IrSi)、矽化鉺(ErSi)、矽化鈷(CoSi)、其組合或其他合適的化合物。
在操作110，方法100(第1A圖)在源極/汲極部件260的背側上選擇性地沉積抑制劑302，更詳細而言，在本實施例中沉積在矽化物部件280上方。根據一個實施例，在第6A-6E圖示出所得的結構。抑制劑302包括有機薄膜或相似於有機薄膜，其包含兩親分子或相似於兩親分子。參照第6B-6E圖，抑制劑302沉積在矽化物部件280上，但是不沉積在介電層230、203和255上。應注意的是，在源極/汲極部件260及/或矽化物部件280與CESL 269和隔離結構230相遇的角落區域327中，抑制劑302可以接觸也可以不接觸CESL 269和隔離結構230。在一個實施例中，由於矽化物部件280的分子與抑制劑302的分子之間的共價鍵，抑制劑302沉積在矽化物部件280的表面上。在層230、203和255的介電表面與抑制劑302之間不存在這種共價鍵。因此，抑制劑302沒有沉積在這些介電表面上。抑制劑302還具有疏水性，使其不能附著到介電材料上(即排斥介電材料在其上的 沉積)，將參考操作112進一步解釋。例如，在一些實施例中，抑制劑302可以包括烷基鏈或羧酸的化合物，或者在一些實施例中可以具有化學式SHCH2C6H4CH2SH或HS-(CH2)n-COOH。可以使用ALD、PVD、CVD或其他合適的方法來沉積抑制劑302，並且可以具有大約0.5nm至5nm的厚度(沿著“z”方向)。在本實施例中，抑制劑302僅沉積在選定的表面(即，矽化物部件280的表面)上，而不涉及微影製程。因此，操作110為選擇性沉積製程。
在操作112處，方法100(第1A圖)在結構200的背側上選擇性地沉積介電襯層304。根據一個實施例，在第7A-7E圖示出所得的結構。參照第7A-7E圖，在此實施例中，沿B-SAC層203、隔離結構230和內部間隔物255的各個表面沉積介電襯層304以具有大抵均勻的厚度。由於抑制劑302的疏水性，除了抑制劑302的一些邊緣區域(例如，抑制劑302在角落區域327中的部分)之外，介電襯層304沒有沉積在抑制劑302上。介電襯層304可以接觸或可以不接觸抑制劑302的邊緣區域。在各種實施例中，介電襯層304可以包括La2O3、Al2O3、SiOCN、SiOC、SiCN、SiO2、SiC、ZnO、ZrN、Zr2Al3O9、TiO2、TaO2、ZrO2、HfO2、Si3N4、Y2O3、AlON、TaCN、ZrSi或其他合適的材料。介電襯層304用於隔離稍後將在溝槽272中形成的源極/汲極接觸件(背側導孔)(參照第12D圖)。沒有介電襯層304，來自源極/汲極接觸件的金屬可能隨時間擴散到隔離結構230中而引起問題。介電襯層304也具有使源極/汲極接觸件與附近的閘極堆疊240隔離的作用。可以使用ALD、CVD或其他合適的方法沉積介電襯層304，並且在各種實施例中可以具有大約1nm至大約5nm的厚度(例如，沿著“x”方向在B-SAC層203的側壁上測量)。在本實施例中，介電襯層304僅沉積在選定的表面(即，隔離結構230、B-SAC層203和內部間隔物255的表面)上，而不涉及微影製程。因此， 操作112是選擇性沉積製程。詳細而言，由於介電襯層304沒有沉積在抑制劑302上，因此不需要用於擊穿介電襯層304的垂直蝕刻製程。
在操作114，方法100(第1B圖)從裝置200，特別是從矽化物部件280的表面去除抑制劑302。根據一個實施例，在第8A-8E圖示出所得的結構。參照第8A-8E圖，去除抑制劑302導致在角落區域327中的間隙(或空隙)333。在第8B圖的截面圖中，間隙333直接存在於介電襯層304的下方和源極/汲極部件260和矽化物部件280的上方，並暴露出內部間隔物255的側表面的一部分。在第8D和8E圖的截面圖中，間隙333存在於介電襯層304正下方和矽化物部件280上方，並暴露出隔離結構230及/或CESL 269的側表面的一部分。在各種實施例中，介電襯層304的底表面與矽化物部件280的頂表面之間的距離d2在大約0.2nm至大約5nm的範圍。距離d2是間隙333的高度。如果距離d2小於0.2nm，則背側源極/汲極接觸件(或源極/汲極導孔)，例如源極/汲極導孔282(參見第12D圖)將較難以填充間隙，減小源極/汲極接觸件282和源極/汲極部件260(和矽化物部件280)之間的界面面積，並增加源極/汲極接觸件電阻。如果距離d2大於5nm，則隔離結構230、B-SAC層203及/或內部間隔物255上可能存在未被介電襯層304充分覆蓋的區域，導致金屬從源極/汲極接觸件282擴散進入這些介電層。因此，距離d2在0.2nm至5nm的範圍內，在減小源極/汲極接觸電阻和改善源極/汲極接觸隔離之間達到良好的平衡。
在一個實施例中，去除抑制劑302包括電漿乾式蝕刻製程、化學乾式蝕刻製程、灰化製程、濕式蝕刻製程或其組合。蝕刻和灰化製程對抑制劑302的材料具選擇性，而未(或最小)蝕刻介電襯層304、CESL 269、內部間隔物255、隔離結構230、矽化物部件280和源極/汲極部件260。例如，電漿乾式刻 蝕製程可以使用常規的乾式蝕刻劑來處理介電材料，例如與H2或O2混合的C4F6，化學乾式蝕刻製程可以使用一種或多種化學品(例如H2)，灰化製程可以使用氧氣或氫氣灰化，濕式蝕刻製程可以在例如高於100℃的溫度施加熱SPM溶液(硫酸和過氧化氫的混合物)。
操作110、112和114的結果，矽化物部件280的背側表面在溝槽272中露出，並且介電襯層304設置在隔離結構230、B-SAC層203以及內部間隔物255的各個表面之上。在不使用抑制劑302的方法(即，省略操作110和114)中，介電襯層304不僅將沉積在層230、203和255的表面上，而且還將沉積在矽化物部件280上。為了露出源極/汲極部件260及/或矽化物部件280以用於隨後的源極/汲極接觸件形成，將執行蝕刻製程以蝕刻介電襯層304。有時後為了確保將介電襯層304從源極/汲極部件260或矽化物部件280的表面完全去除，將執行過度蝕刻。過度蝕刻可能導致B-SAC層203以及源極/汲極部件260或矽化物部件280的不必要損失。B-SAC層203的損失或薄化可能導致閘極堆疊240和背側導孔(例如第12D圖中的導孔282)之間的短路。相反地，通過使用抑制劑302，根據本實施例的製程更穩健，並且對B-SAC層203的厚度具有更好的控制。此外，由於間隙333的存在，源極/汲極部件206和矽化物部件280的更多區域用於形成源極/汲極接觸件，從而減小源極/汲極接觸電阻。
在操作116，方法100(第1B圖)用一種或多種介電材料沉積介電層276，以填充溝槽272。在本實施例中，操作116對介電層276和介電襯層304執行CMP製程以將它們從隔離結構230的頂表面去除。根據一個實施例，在第9A-9E圖示出所得的結構。參照第9A至9E圖，介電層276沉積在介電襯層304和矽化物部件280上方，並填充間隙333。在一些實施例中，介電層276包括La2O3、Al2O3、 SiOCN、SiOC、SiCN、SiO2、SiC、ZnO、ZrN、Zr2Al3O9、TiO2、TaO2、ZrO2、HfO2、Si3N4、Y2O3、AlON、TaCN、ZrSi或其他合適的材料的一種或多種。此外，在本實施例中，介電層276和介電襯層304包括不同的材料以在背側接觸孔蝕刻製程期間實現蝕刻選擇性。更進一步，介電層276和隔離結構230可以包括不同的材料，使得當通過CMP製程平坦化介電層276時，隔離結構230可以用作CMP停止層。
在操作118，方法100(第1B圖)在結構200的背側上方形成蝕刻遮罩360。蝕刻遮罩360在源極/汲極部件260的背側上提供將被連接至背側導孔的開口362。根據一個實施例，在第10A-10E圖示出所得的結構。參照第10A至10E圖，在所描繪的實施例中，開口362設置在源極部件260的背側上，而閘極堆疊240和汲極部件260的背側被蝕刻遮罩360覆蓋。在各種實施例中，可以僅在汲極部件的背側上提供開口362，僅在源極部件的背側上提供開口362或在源極部件和汲極部件兩者的背側上提供開口362。蝕刻遮罩360包括與介電層276的材料不同的材料，以在背側通孔蝕刻期間實現蝕刻選擇性。例如，蝕刻遮罩360包括阻抗材料(因此可以被稱為圖案化的阻抗層及/或圖案化的光阻層)。在一些實施例中，蝕刻遮罩360具有多層結構，例如設置在抗反射塗層(anti-reflective coating,ARC)層及/或包括氮化矽或氧化矽的硬遮罩層上方的阻抗層。本揭露也考慮用於蝕刻遮罩360的其他材料，只要在介電層276的蝕刻期間可以實現蝕刻選擇性。在一些實施例中，操作118使用微影製程，微影製程包括在裝置200的背側上形成阻抗層(例如，通過旋轉塗佈)，執行曝光前烘烤製程，使用遮罩執行曝光製程，執行曝光後烘烤製程以及執行顯影製程。在曝光過程中，阻抗層被暴露於輻射能量(例如，UV光、DUV光或EUV光)，其中遮罩阻擋、透射及/ 或反射輻射至阻抗層，取決於遮罩及/或遮罩類型的遮罩圖案(例如，二元遮罩、相移遮罩或EUV遮罩)，使得圖像被投影到與遮罩圖案相對應的阻抗層上。由於阻抗層對輻射能量敏感，阻抗層的曝光部分發生化學變化，並且在顯影製程中，根據阻抗層的特性和在顯影製程中使用的顯影液的特性，阻抗層的曝光(或非曝光)部分溶解。在顯影之後，圖案化的阻抗層(例如，蝕刻遮罩360)包括與遮罩相對應的阻抗圖案。替代地，可以通過其他方法來實施或代替曝光製程，例如無遮罩微影、電子束寫入、離子束寫入或其組合。
在操作120處，方法100(第1B圖)通過蝕刻遮罩360蝕刻介電層276以形成通孔278。隨後例如通過阻抗層剝離製程或其他合適的製程去除蝕刻遮罩360。根據一個實施例，在第11A-11E圖示出所得的結構。參照第11A-11E圖，在所示實施例中，通孔278暴露出在源極部件260上的矽化物部件280。詳細而言，間隙333重新出現在通孔278內部的角落區域327中。在一個實施例中，蝕刻製程包括乾式(電漿)蝕刻製程，其經調整以選擇性地蝕刻介電層276並且不(或最少)蝕刻介電襯層304、隔離結構230、CESL 269、內部間隔物255、矽化物部件280及源極/汲極部件260。在替代實施例中，操作120可以使用其他類型的蝕刻(例如濕式蝕刻或反應離子蝕刻)，只要可以如上所述實現膜層之間的蝕刻選擇性。由於操作120沒有或最小地蝕刻隔離結構230和介電襯層304，因此通孔蝕刻在y-z平面和x-z平面中與介電襯層304自對準，從而提高製程寬裕度(process margin)。
在操作122，方法100(第1B圖)在通孔278中形成導孔結構(或導孔或金屬插塞)282。根據一個實施例，在第12A至12E圖示出所得的結構。參照第12A至12E圖，導孔282設置在矽化物部件280上方。
在一個實施例中，導孔282可以包括鎢(W)、鈷(Co)、鉬(Mo)、釕(Ru)、銅(Cu)、鎳(Ni)、鈦(Ti)、鉭(Ta)、氮化鈦(TiN)、氮化鉭(TaN)或其他金屬，並且可以通過CVD、PVD、ALD、電鍍或其他合適的製程形成。操作122可以執行CMP製程以去除導孔282的多餘材料。
在操作124，方法100(第1B圖)形成背側電源軌284。根據一個實施例，在第13A-13B圖示出所得的結構。如第13B-13E圖所示，背側導孔282電性連接到背側電源軌284。在一個實施例中，可以使用鑲嵌製程、雙鑲嵌製程、金屬圖案化製程或其他合適的製程形成背側電源軌284。背側電源軌284可以包括鎢(W)、鈷(Co)、鉬(Mo)、釕(Ru)、銅(Cu)、鎳(Ni)、鈦(Ti)、鉭(Ta)、氮化鈦(TiN)、氮化鉭(TaN)或其他金屬，並且可以通過CVD、PVD、ALD、電鍍或其他合適的製程沉積。儘管在第13A至13E圖中未示出，但是背側電源軌284嵌入在一個或多個介電層中。具有背側電源軌284有利地增加裝置200中可用於直接連接到源極/汲極接觸件和導孔的金屬軌的數量。與沒有背側電源軌284的其他結構相比，本揭露增加了閘極密度，以實現更大的裝置整合度。背側電源軌284的尺寸可以比裝置200的前側上的第一層金屬(M0)軌的尺寸更寬，這有利地減小了背側電源軌的電阻。在一個實施例中，背側電源軌284可以具有例如在大約5nm至大約40nm範圍的厚度d1，介電層276可以具有例如在大約3nm至大約50nm範圍的厚度d3，以及如上所述，B-SAC層203的厚度d5在大約0.5nm至大約50nm的範圍。
在操作126，方法100(第1B圖)對裝置200執行進一步的製造製程。例如，可以在結構200的背側上形成一個或多個互連層，可以在裝置200的背側上形成鈍化層，執行其他BEOL製程以及去除載體370。
儘管不意旨在限制，但是本揭露的實施例提供以下一個或多個益處。例如，本揭露的實施例形成用於背側導孔的襯層，其中襯層選擇性地沉積在通孔的側壁上，而不沉積在通孔的底部上。這消除隨後在通孔中形成導孔時穿透襯層的需求，並有利地降低了金屬閘極至背側導孔的短路風險。此外，本揭露的實施例使用自對準製程形成背側導孔，這最小化了背側導孔至附近導體包括閘極堆疊的短路風險。此外，本揭露的實施例形成背側電源軌以增加積體電路中可用的金屬軌的數量，並增加閘極密度以實現更大的裝置整合。本揭露的實施例可以容易地整合到現有的半導體製造製程中。
根據本揭露一些實施例，提供一種形成半導體結構的方法，包括：提供半導體結構，半導體結構具有前側與背側，半導體結構包括基板；半導體鰭片，在基板上；兩個源極/汲極(S/D)部件，在半導體鰭片上；第一介電層，在半導體鰭片上；隔離結構，鄰近半導體鰭片的側壁；一個或多個通道半導體層，在第一介電層上並連接兩個源極/汲極部件；以及閘極結構，齒合(engaging)一個或多個通道半導體層，其中基板在半導體結構的背側，並且閘極結構在半導體結構的前側；從半導體結構的背側薄化半導體結構，直到露出半導體鰭片；從半導體結構的背側選擇性蝕刻半導體鰭片以形成溝槽，其中溝槽露出兩個源極/汲極部件的表面、第一介電層的表面以及隔離結構的側壁；在源極/汲極部件的表面上形成矽化物部件；在溝槽中選擇性沉積抑制劑，其中抑制劑被沉積在矽化物部件上，而未被沉積在第一介電層的表面上以及隔離結構的側壁上；在溝槽中選擇性沉積介電襯層，其中介電襯層被沉積在隔離結構的側壁上以及在第一介電層的表面上，而未被沉積在抑制劑上；以及選擇性去除抑制劑。
在一些實施例中，更包括：沉積第二介電層以填充溝槽；蝕刻第二介電層以形成通孔，通孔露出在兩個源極/汲極部件的其中一個上的矽化物部件以及介電襯層；以及在通孔中形成導孔結構。
在一些實施例中，在蝕刻第二介電層之前，更包括：在半導體結構的背側上形成蝕刻遮罩，蝕刻遮罩提供開口在第二介電層的一部分上，上述部分在兩個源極/汲極部件的其中一個下方，其中第二介電層的蝕刻是通過開口進行。
在一些實施例中，導孔結構的至少一部分垂直地形成在該兩個源極/汲極部件的其中一個與該介電襯層之間。
在一些實施例中，矽化物部件包括矽化鈦(TiSi)、矽化鎳(NiSi)、矽化鎢(WSi)、矽化鎳鉑(NiPtSi)、矽化鎳鉑鍺(NiPtGeSi)、矽化鎳鍺(NiGeSi)、矽化鐿(YbSi)、矽化鉑(PtSi)、矽化銥(IrSi)、矽化鉺(ErSi)、矽化鈷(CoSi)或其組合。
在一些實施例中，抑制劑包括具有兩親性分子(amphiphilic molecules)的有機膜，並且介電襯層包括La2O3、Al2O3、SiOCN、SiOC、SiCN、SiO2、SiC、ZnO、ZrN、Zr2Al3O9、TiO2、TaO2、ZrO2、HfO2、Si3N4、Y2O3、AlON、TaCN以及ZrSi中的至少一者。
在一些實施例中，選擇性去除抑制劑的步驟使用蝕刻製程，蝕刻製程被調整為蝕刻抑制劑，而不蝕刻或最小程度蝕刻介電襯層。
在一些實施例中，選擇性去除抑制劑的步驟包括電漿乾式蝕刻、化學乾式蝕刻、灰化、濕式蝕刻或其組合。
在一些實施例中，選擇性去除抑制劑的步驟包括在超過100℃的 溫度，以SPM清潔溶液進行濕式蝕刻。
根據本揭露另一些實施例，提供一種形成半導體結構的方法，包括：提供半導體結構，半導體結構具有基板；半導體鰭片，在基板上；兩個源極/汲極部件，在半導體鰭片上；隔離結構，在半導體鰭片的側壁上；介電蓋層，在半導體鰭片上；一個或多個通道半導體層，在介電蓋層上；以及閘極結構，齒合一個或多個通道半導體層；薄化半導體結構，直到露出半導體鰭片；選擇性蝕刻半導體鰭片以形成溝槽，其中溝槽露出兩個源極/汲極部件的表面、介電蓋層的表面以及隔離結構的側壁；在源極/汲極部件的表面上形成矽化物部件；沉積抑制劑在矽化物部件上，而未在介電蓋層的表面上以及隔離結構的側壁上；沉積介電襯層在隔離結構的側壁上以及介電蓋層的表面上，而未在抑制劑上；選擇性去除抑制劑；以及在溝槽中形成導孔結構。
在另一些實施例中，在選擇性去除抑制劑之後，並且在形成導孔結構之前，更包括：沉積介電層以填充溝槽；以及蝕刻介電層以形成通孔，通孔露出在兩個源極/汲極部件的其中一個上的矽化物部件，其中導孔結構形成在通孔中。
在另一些實施例中，在蝕刻介電層之前，更包括：在半導體結構的背側上形成蝕刻遮罩，蝕刻遮罩提供開口在介電層的一部分上，其中介電層的蝕刻是通過開口進行。
在另一些實施例中，矽化物部件包括矽化鈦(TiSi)、矽化鎳(NiSi)、矽化鎢(WSi)、矽化鎳鉑(NiPtSi)、矽化鎳鉑鍺(NiPtGeSi)、矽化鎳鍺(NiGeSi)、矽化鐿(YbSi)、矽化鉑(PtSi)、矽化銥(IrSi)、矽化鉺(ErSi)、矽化鈷(CoSi)或其組合。
在另一些實施例中，抑制劑包括具有兩親性分子(amphiphilic molecules)的有機膜，並且介電襯層包括La2O3、Al2O3、SiOCN、SiOC、SiCN、SiO2、SiC、ZnO、ZrN、Zr2Al3O9、TiO2、TaO2、ZrO2、HfO2、Si3N4、Y2O3、AlON、TaCN以及ZrSi中的至少一者。
在另一些實施例中，選擇性去除抑制劑的步驟包括電漿乾式蝕刻、化學乾式蝕刻、灰化、濕式蝕刻或其組合。
根據本揭露又一些實施例，提供一種半導體結構，包括：兩個源極/汲極部件；一個或多個通道半導體層，連接兩個源極/汲極部件；閘極結構，齒合一個或多個通道半導體層，其中兩個源極/汲極部件、一個或多個通道半導體層以及閘極結構在半導體結構的前側；金屬軌(metal track)，在半導體結構的背側；第一介電層，在金屬軌與一個或多個通道半導體層之間；介電襯層，在第一介電層的表面上，並且與兩個源極/汲極部件的其中一個以第一間隙隔開；以及導孔結構，連接金屬軌至兩個源極/汲極部件的其中一個，其中導孔結構的一部分設置在第一間隙中。
在又一些實施例中，介電襯層與兩個源極/汲極部件的其中另一個以第二間隙隔開。
在又一些實施例中，更包括：第二介電層，在介電襯層上，其中第二介電層的一部分從金屬軌延伸至兩個源極/汲極部件的其中另一個，並填充第二間隙。
在又一些實施例中，更包括矽化物部件，在導孔結構與兩個源極/汲極部件的其中一個之間。
在又一些實施例中，更包括第二介電層，在介電襯層上，並在第 一介電層與金屬軌之間。
以上概述數個實施例之部件，以便在本發明所屬技術領域中具有通常知識者可以更加理解本發明實施例的觀點。在本發明所屬技術領域中具有通常知識者應理解，他們能輕易地以本發明實施例為基礎，設計或修改其他製程和結構，以達到與在此介紹的實施例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應理解，此類等效的結構並無悖離本發明的精神與範圍，且他們能在不違背本發明之精神和範圍下，做各式各樣的改變、取代和替換。因此，本發明之保護範圍當視後附之申請專利範圍所界定為準。
200:半導體裝置
201:基板
203:底部自對準蓋層
204:半導體鰭片(半導體層)
215:通道半導體層
247:(外部)閘極間隔物
255:內部間隔物(內部間隔層)
260:源極/汲極部件
269:接觸蝕刻停止層
273:矽化物部件
275:源極/汲極接觸件
277:互連層
349:閘極介電層
350:閘極電極
352:自對準蓋層
356:蓋層
358:源極/汲極接觸導孔
370:載體

Claims (15)

  1. 一種形成半導體結構的方法，包括：提供一半導體結構，該半導體結構具有一前側與一背側，該半導體結構包括一基板；一半導體鰭片，在該基板上；兩個源極/汲極(S/D)部件，在該半導體鰭片上；一第一介電層，在該半導體鰭片上；一隔離結構，鄰近該半導體鰭片的側壁；一個或多個通道半導體層，在該第一介電層上並連接該兩個源極/汲極部件；以及一閘極結構，齒合(engaging)該一個或多個通道半導體層，其中該基板在該半導體結構的該背側，並且該閘極結構在該半導體結構的該前側；從該半導體結構的該背側薄化該半導體結構，直到露出該半導體鰭片；從該半導體結構的該背側選擇性蝕刻該半導體鰭片以形成一溝槽，其中該溝槽露出該兩個源極/汲極部件的表面、該第一介電層的表面以及該隔離結構的側壁；在該源極/汲極部件的表面上形成一矽化物部件；在該溝槽中選擇性沉積一抑制劑，其中該抑制劑被沉積在該矽化物部件上，而未被沉積在該第一介電層的表面上以及該隔離結構的側壁上；在該溝槽中選擇性沉積一介電襯層，其中該介電襯層被沉積在該隔離結構的側壁上以及在該第一介電層的表面上，而未被沉積在該抑制劑上；以及選擇性去除該抑制劑。
  2. 如請求項1所述之形成半導體結構的方法，更包括：沉積一第二介電層以填充該溝槽；蝕刻該第二介電層以形成一通孔，該通孔露出在該兩個源極/汲極部件的其中一個上的該矽化物部件以及該介電襯層；以及 在該通孔中形成一導孔結構。
  3. 如請求項2所述之形成半導體結構的方法，在蝕刻該第二介電層之前，更包括：在該半導體結構的該背側上形成一蝕刻遮罩，該蝕刻遮罩提供一開口在該第二介電層的一部分上，該部分在該兩個源極/汲極部件的其中一個下方，其中該第二介電層的蝕刻是通過該開口進行。
  4. 如請求項2所述之形成半導體結構的方法，其中該導孔結構的至少一部分垂直地形成在該兩個源極/汲極部件的其中一個與該介電襯層之間。
  5. 如請求項1至4中任一項所述之形成半導體結構的方法，其中該矽化物部件包括矽化鈦(TiSi)、矽化鎳(NiSi)、矽化鎢(WSi)、矽化鎳鉑(NiPtSi)、矽化鎳鉑鍺(NiPtGeSi)、矽化鎳鍺(NiGeSi)、矽化鐿(YbSi)、矽化鉑(PtSi)、矽化銥(IrSi)、矽化鉺(ErSi)、矽化鈷(CoSi)或其組合。
  6. 如請求項1至4中任一項所述之形成半導體結構的方法，其中該抑制劑包括具有兩親性分子(amphiphilic molecules)的有機膜，並且該介電襯層包括La2O3、Al2O3、SiOCN、SiOC、SiCN、SiO2、SiC、ZnO、ZrN、Zr2Al3O9、TiO2、TaO2、ZrO2、HfO2、Si3N4、Y2O3、AlON、TaCN以及ZrSi中的至少一者。
  7. 如請求項1至4中任一項所述之形成半導體結構的方法，其中選擇性去除該抑制劑的步驟使用一蝕刻製程，該蝕刻製程被調整為蝕刻該抑制劑，而不蝕刻或最小程度蝕刻該介電襯層。
  8. 如請求項7所述之形成半導體結構的方法，其中選擇性去除該抑制劑的步驟包括電漿乾式蝕刻、化學乾式蝕刻、灰化、濕式蝕刻或其組合。
  9. 如請求項7所述之形成半導體結構的方法，其中選擇性去除該抑制劑的步驟包括在超過100℃的溫度，以硫酸和過氧化氫的混合物(SPM)清潔溶液進行濕式蝕刻。
  10. 一種形成半導體結構的方法，包括：提供一半導體結構，該半導體結構具有一基板；一半導體鰭片，在該基板上；兩個源極/汲極部件，在該半導體鰭片上；一隔離結構，在該半導體鰭片的側壁上；一介電蓋層，在該半導體鰭片上；一個或多個通道半導體層，在該介電蓋層上；以及一閘極結構，齒合該一個或多個通道半導體層；薄化該半導體結構，直到露出該半導體鰭片；選擇性蝕刻該半導體鰭片以形成一溝槽，其中該溝槽露出該兩個源極/汲極部件的表面、該介電蓋層的表面以及該隔離結構的側壁；在該源極/汲極部件的表面上形成一矽化物部件；沉積一抑制劑在該矽化物部件上，而未在該介電蓋層的表面上以及該隔離結構的側壁上；沉積一介電襯層在該隔離結構的側壁上以及該介電蓋層的表面上，而未在該抑制劑上；選擇性去除該抑制劑；以及在該溝槽中形成一導孔結構。
  11. 一種半導體結構，包括：兩個源極/汲極部件；一個或多個通道半導體層，連接該兩個源極/汲極部件；一閘極結構，齒合該一個或多個通道半導體層，其中該兩個源極/汲極部件、 該一個或多個通道半導體層以及該閘極結構在該半導體結構的一前側；一金屬軌(metal track)，在該半導體結構的一背側；一第一介電層，在該金屬軌與該一個或多個通道半導體層之間；一介電襯層，在該第一介電層的表面上，並且與該兩個源極/汲極部件的其中一個以一第一間隙隔開；以及一導孔結構，連接該金屬軌至該兩個源極/汲極部件的其中一個，其中該導孔結構的一部分設置在該第一間隙中。
  12. 如請求項11所述之半導體結構，其中該介電襯層與該兩個源極/汲極部件的其中另一個以一第二間隙隔開。
  13. 如請求項12所述之半導體結構，更包括：一第二介電層，在該介電襯層上，其中該第二介電層的一部分從該金屬軌延伸至該兩個源極/汲極部件的其中另一個，並填充該第二間隙。
  14. 如請求項11至13中任一項所述之半導體結構，更包括一矽化物部件，在該導孔結構與該兩個源極/汲極部件的該其中一個之間。
  15. 如請求項11所述之半導體結構，更包括一第二介電層，在該介電襯層上，並在該第一介電層與該金屬軌之間。
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