TW202201638A - 半導體結構 - Google Patents

半導體結構 Download PDF

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TW202201638A
TW202201638A TW110121666A TW110121666A TW202201638A TW 202201638 A TW202201638 A TW 202201638A TW 110121666 A TW110121666 A TW 110121666A TW 110121666 A TW110121666 A TW 110121666A TW 202201638 A TW202201638 A TW 202201638A
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Taiwan
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source
drain
layer
dielectric
semiconductor layer
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TW110121666A
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English (en)
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朱峯慶
李威養
林家彬
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台灣積體電路製造股份有限公司
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Publication of TW202201638A publication Critical patent/TW202201638A/zh

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Abstract

一種半導體結構，包括：隔離結構；第一源極/汲極部件（S/D）以及第二源極/汲極部件，在隔離結構上，定義第一方向，在俯視圖中，第一方向從第一源極/汲極部件至第二源極/汲極部件；一個或多個通道層，連接第一源極/汲極部件以及第二源極/汲極部件；閘極結構，在第一源極/汲極部件以及第二源極/汲極部件之間，且齒合每個通道層；以及導孔結構，在第一源極/汲極部件下方，且電性連接至第一源極/汲極部件。在垂直於第一方向的剖面圖中，導孔結構具有輪廓，輪廓沿著由下至上的方向由寬至窄。

Description

半導體結構
本發明實施例係有關於一種半導體結構及其形成方法，且特別關於一種具有背側金屬部件的半導體結構及其形成方法。
常規上，積體電路（IC）是以堆疊的方式建構，其具有處於最低水平處的電晶體以及在電晶體上的互連結構（導孔和導線）以提供電晶體的連接。電源軌（例如電壓源和接地的金屬線）也位於電晶體上方，並且可以是互連結構的一部份。隨著積體電路的不斷微縮化，電源軌也隨之縮小。這不可避免地導致跨電源軌的壓降增加，以及積體電路的功耗增加。因此，儘管半導體製造中現有的方法通常已經足以滿足其預期目的，但是它們並非在所有方面都完全令人滿意。
本揭露一些實施例提供一種半導體結構，包括：隔離結構；第一源極/汲極部件（S/D）以及第二源極/汲極部件，在隔離結構上，定義第一方向，在俯視圖中，第一方向從第一源極/汲極部件至第二源極/汲極部件；一個或多個通道層，連接第一源極/汲極部件以及第二源極/汲極部件；閘極結構，在第一源極/汲極部件以及第二源極/汲極部件之間，且齒合（engaging）每個通道層；以及導孔結構，在第一源極/汲極部件下方，且電性連接至第一源極/汲極部件，其中，在垂直於第一方向的剖面圖中，導孔結構具有輪廓，輪廓沿著由下至上（bottom-up）的方向由寬（widens）至窄（narrows）。
本揭露另一些實施例提供一種形成半導體結構的方法，包括：提供結構，結構具有基板、隔離結構，在基板上、鰭片，從基板延伸且鄰近隔離結構、犧牲閘極結構，設置在鰭片的通道區上、以及閘極間隔物，在犧牲閘極結構的兩側側壁上；對鄰近閘極間隔物的鰭片進行第一蝕刻以形成第一源極/汲極溝槽以及第二源極/汲極溝槽，第一源極/汲極溝槽在犧牲閘極結構的一側上，第二源極/汲極溝槽在犧牲閘極結構的另一側上；形成蝕刻遮罩，蝕刻遮罩露出第一源極/汲極溝槽並覆蓋第二源極/汲極溝槽；透過蝕刻遮罩對鰭片進行第二蝕刻，以深化（deepen）第一源極/汲極溝槽；以及在第二蝕刻之後，橫向蝕刻露出於第一源極/汲極溝槽的下部的隔離結構的部份，得到第一源極/汲極溝槽的擴大的下部。
本揭露又一些實施例提供一種形成半導體結構的方法，包括：提供結構，結構具有基板、隔離結構，在基板上、鰭片，從基板延伸且鄰近隔離結構、犧牲閘極結構，設置在鰭片的通道區上、以及閘極間隔物，在犧牲閘極結構的兩側側壁上；對鄰近閘極間隔物的鰭片進行第一蝕刻以形成第一源極/汲極溝槽以及第二源極/汲極溝槽，第一源極/汲極溝槽在犧牲閘極結構的一側上，第二源極/汲極溝槽在犧牲閘極結構的另一側上；形成蝕刻遮罩，蝕刻遮罩露出第一源極/汲極溝槽並覆蓋第二源極/汲極溝槽；透過蝕刻遮罩對鰭片進行第二蝕刻，以深化（deepen）第一源極/汲極溝槽；在第二蝕刻之後，橫向蝕刻露出於第一源極/汲極溝槽的下部的隔離結構的部份，得到第一源極/汲極溝槽的擴大的下部；至少在第一源極/汲極溝槽的擴大的下部中成長第一半導體層，其中第一半導體層包括不同於鰭片的材料；以及在第一半導體層上磊晶成長第一半導體源極/汲極部件。
以下內容提供了許多不同實施例或範例，以實現本揭露實施例的不同部件。以下描述組件和配置方式的具體範例，以簡化本揭露實施例。當然，這些僅僅是範例，而非意圖限制本揭露實施例。舉例而言，在以下描述中提及於第二部件上方或其上形成第一部件，其可以包含第一部件和第二部件以直接接觸的方式形成的實施例，並且也可以包含在第一部件和第二部件之間形成額外的部件，使得第一部件和第二部件可以不直接接觸的實施例。此外，本揭露實施例可在各個範例中重複參考標號及/或字母。此重複是為了簡化和清楚之目的，其本身並非用於指定所討論的各個實施例及/或配置之間的關係。
再者，其中可能用到與空間相對用詞，例如「在……之下」、「下方」、「較低的」、「上方」、「較高的」等相似用詞，是為了便於描述圖式中一個（些）部件或特徵與另一個（些）部件或特徵之間的關係。空間相對用詞用以包括使用中或操作中的裝置之不同方位，以及圖式中所描述的方位。當裝置被轉向不同方位時（旋轉90度或其他方位），其中所使用的空間相對形容詞也將依轉向後的方位來解釋。此外，此處所使用的用語「約」、「近似」等類似用語描述數字或數字範圍時，該用語意欲涵蓋的數值是在合理範圍內包含所描述的數字，例如在所描述的數字之+/- 10％之內，或本發明所屬技術領域中具有通常知識者理解的其他數值。例如，用語「約5奈米」涵蓋從4.5奈米至5.5奈米、4.0奈米至5.0奈米等的尺寸範圍。
本揭露整體關於半導體結構和製造製程，更詳細而言，關於具有背側電源軌和背側自對準導孔的半導體裝置。如上所述，IC中的電源軌需要進一步改進，以提供所需的性能提升並降低功耗。本揭露的目的包括在包含電晶體（例如，全繞式閘極（gate-all-around, GAA）電晶體及/或FinFET電晶體）的結構的背側提供電源軌（或電源佈線），此外在結構的前側提供互連結構（也可以包括電源軌）。這增加結構中可用於直接連接到源極/汲極接觸件和導孔的金屬軌的數量。與沒有背側電源軌的現有結構相比，還增加閘極密度以實現更大的裝置整合度。背側電源軌的尺寸可以比結構前側的第一層金屬（M0）軌的尺寸更寬，這有利地降低電源軌的電阻。本揭露還提供用於降低背側電源軌以及源極/汲極（S/D）部件（其在裝置的前側）之間的電阻的結構以及方法。源極/汲極部件的尺寸以及源極/汲極部件與背側導孔之間的接觸面積通常受到主動區的寬度限制，例如半導體鰭片的寬度。本揭露的實施例使用額外的橫向蝕刻製程以突破（break through）圍繞半導體鰭片的介電層，從而擴大源極/汲極溝槽的底部。其提供與背側導孔的界面較大的面積，從而有益處地降低源極/汲極部件以及背側電源軌之間的接觸電阻。
以下結合附圖描述本揭露的結構和製造方法的細節，附圖根據一些實施例示出製造GAA裝置的製程。GAA裝置是指具有垂直堆疊的水平取向的多通道電晶體的裝置，例如奈米線電晶體和奈米片電晶體。GAA裝置具有更好的閘極控制能力、更低的漏電流以及完整的FinFET裝置佈局兼容性，因此有望將CMOS推向發展路程圖（roadmap）的下一個階段。為了簡單起見，本揭露使用GAA裝置作為示例。本領域技術人員應該理解，他們可以容易地將本揭露用作設計或修改其他製程和結構（例如FinFET裝置）的基礎，為了實現本揭露介紹的實施例的相同目的及/或實現相同的優點。
第1A、1B以及1C圖係根據本揭露的各種方面，用於製造半導體裝置的方法100的流程圖。本揭露考慮額外的製程。可以在方法100之前、之中以及之後提供其他操作，並且對於方法100的額外實施例，可以移動、替換或消除所描述的一些操作。
根據一些實施例，以下結合第2至21B圖描述方法100，示出根據方法100的各種製造步驟的半導體裝置（或半導體結構）200的各種俯視圖和剖面圖。在一些實施例中，裝置200是IC晶片、晶片上系統（system on chip, SoC）或其部份的一部份，其包括各種被動和主動微電子裝置，例如電阻、電容、電感、二極體、p型場效電晶體（p-type field effect transistors, PFETs）、n型場效電晶體（n-type field effect transistors, NFETs）、鰭式場效電晶體（FinFET）、奈米片FET、奈米線FET、其他類型的多閘極FET、金屬氧化物半導體場效電晶體（metal-oxide semiconductor field effect transistors, MOSFETs）、互補式金屬氧化物半導體（complementary metal-oxide semiconductor, CMOS）電晶體、雙極接面電晶體（bipolar junction transistors, BJTs）、橫向擴散金屬氧化物半導體（laterally diffused MOS, LDMOS）電晶體、高壓電晶體、高頻電晶體、記憶體裝置、其他合適的組件、或其組合。為了清楚起見，已經簡化第2至21B圖以更好地理解本揭露的發明構思。可以在裝置200中增加額外的部件，並且在裝置200的其他實施例中可以替換、修改或消除以下描述的一些部件。
在操作102，方法100（第1A圖）提供半導體結構，半導體結構具有基板201以及建構在基板201之中或之上的各種元件，包括半導體鰭片218、隔離結構230、介電（隔離）鰭片229、犧牲（或虛設）閘極堆疊240、閘極間隔物247以及各種其他元件，例如第2至4C圖中所示。以下參照第2至4C圖進一步討論這些元件及其製造方法。
參考第2圖，在基板201之上的半導體層204之上形成半導體層210和215的堆疊205。在一實施例中，基板201是塊體矽基板（即，包括塊體單晶矽）。在各種實施例中，基板201可以包括其他半導體材料，例如鍺（Ge）、碳化矽（silicon carbide）、砷化鎵（GaAs）、磷化鎵（GaP）、磷化銦（InP）、砷化銦（InAs）、銻化銦（InSb），矽鍺（SiGe）、磷砷化鎵（GaAsP）、砷化鋁銦（AlInAs）、砷化鋁鎵（AlGaAs）、砷化鎵銦（GaInAs）、磷化鎵銦（GaInP）、磷砷化鎵銦（GaInAsP）或其組合。在替代實施例中，基板201是絕緣體上半導體基板、例如絕緣體上矽（silicon-on-insulator, SOI）基板、絕緣體上矽鍺（silicon germanium-on-insulator, SGOI）基板或絕緣體上鍺（germanium-on-insulator, GOI）基板。在一些實施例中，半導體層204可以是矽、矽鍺、鍺或其他合適的半導體，並且可以摻雜n型或p型摻質。
半導體層堆疊205包括以交錯（interleaving）或交替（alternating）配置垂直地（例如，沿著z方向）堆疊的半導體層210以及半導體層215。在一些實施例中，半導體層210和半導體層215以所描繪的交錯和交替配置磊晶成長。半導體層210和半導體層215的磊晶成長可以通過分子束磊晶（molecular beam epitaxy, MBE）製程、化學氣相沉積（chemical vapor deposition, CVD）製程、金屬有機化學氣相沉積（metalorganic chemical vapor deposition, MOCVD）製程、其他合適的磊晶成長製程或其組合實現。半導體層210的組成不同於半導體層215的組成以在後續製程期間實現蝕刻選擇性及/或不同的氧化速率。例如，半導體層210和半導體層215可以包括不同的材料、組成原子百分比、組成重量百分比、厚度及/或特性以實現期望的蝕刻選擇性及/或不同的氧化速率。例如，在一個實施例中，半導體層210可以包括矽鍺並且半導體層215可以包括矽。在一些實施例中，半導體層210和半導體層215可以包括相同的材料但具有不同的組成原子百分比以實現蝕刻選擇性及/或不同的氧化速率。例如，半導體層210和215都可以包括矽鍺，其中半導體層210具有第一矽原子百分比及/或第一鍺原子百分比，並且半導體層215具有不同的第二矽原子百分比及/或第二不同的鍺原子百分比。本揭露也考慮（contemplates）半導體層210和半導體層215包括可以提供期望的蝕刻選擇性、期望的氧化速率差異及/或期望的性能特性（例如，最大化電流的材料）的半導體材料的任何組合，包括本揭露的任何半導體材料。
如以下進一步描述，半導體層215或其部份形成裝置200的通道區。在所描繪的實施例中，半導體層堆疊205包括三個半導體層210和三個半導體層215。經過後續製程後，這樣的配置將得到具有三個通道的裝置200。然而，本揭露也考慮其中半導體層堆疊205包括更多或更少半導體層的實施例，例如，取決於裝置200所需的通道數量。例如，半導體層堆疊205可以包括二到十個半導體層210和二到十個半導體層215。在裝置200是FinFET裝置的替代實施例中，堆疊205只是一層半導體材料，例如一層矽。如以下將討論，方法100將對基板201兩側的膜層進行製程。在本揭露中，將堆疊205所在的基板201的一側稱為前側，而與前側相對的一側稱為背側。
第3A圖繪示具有沿著“x”方向定向的鰭片218的裝置200的俯視圖，並且第3B圖繪示沿著第3A圖中的B-B線的裝置200的部份剖面圖。如第3B圖所示，鰭片218包括圖案化的堆疊205（具有膜層210和215）、圖案化的區域204和一個或多個圖案化的硬遮罩層206。鰭片218可以通過任何合適的方法圖案化。例如，可以使用一種或多種微影製程來圖案化鰭片218，包括雙重圖案化製程或多重圖案化製程。一般來說，雙重圖案化或多重圖案化製程結合了微影製程與自對準製程，以創建出例如，比使用單一、直接微影製程所得的節距（pitch）更小的圖案。例如，在一實施例中，在堆疊205上方形成犧牲層，並使用微影製程對其進行圖案化。使用自對準製程在圖案化的犧牲層旁邊形成間隔物。之後去除犧牲層，然後可以使用剩餘的間隔物或心軸作為遮罩以圖案化鰭片218。例如，遮罩元件可以用於將凹口蝕刻到堆疊205以及基板201之中，從而將鰭片218保留在基板201上。蝕刻製程可以包括乾式蝕刻、濕式蝕刻、反應離子蝕刻（reactive ion etching, RIE）及/或其他合適的製程。例如，乾式蝕刻製程可以實施含氧氣體、含氟氣體（例如，CF4 、SF6 、CH2 F2 、CHF3 及/或C2 F6 ）、含氯氣體（例如，Cl2 、CHCl3 、CCl4 及/或BCl3 ）、含溴氣體（例如，HBr及/或CHBr3 ）、含碘氣體、其他合適的氣體及/或電漿、及/或其組合。例如，濕式刻蝕製程可以包括在稀釋氫氟酸（diluted hydrofluoric acid, DHF）； 氫氧化鉀（KOH）溶液；氨；含有氫氟酸（HF）、硝酸（HNO3 ）及/或乙酸（CH3 COOH）的溶液；或其他合適的濕式蝕刻劑中進行蝕刻。許多其他實施例以形成鰭片218的方法可以是合適的。
第4A圖繪示裝置200的俯視圖，並且第4B和4C圖分別繪示裝置200沿著第4A圖的B-B線和C-C線的部份剖面圖。參考第4A、4B以及4C圖，在鰭片218周圍及/或上方建購各種元件，包括隔離鰭片218底部的隔離結構（或部件）230、隔離結構230上方以及鰭片218的側壁上方的包覆（cladding）層231、隔離結構230上方以及包覆層231的側壁上的介電（或虛設）鰭片229、鰭片218上方的犧牲閘極堆疊240、以及犧牲閘極堆疊240側壁上的閘極間隔物247。
參考第4C圖，隔離部件230形成在基板201上方以隔離裝置200的各種區域。例如，隔離部件230圍繞鰭片218的底部以將鰭片218彼此分開和隔離。隔離部件230可以包括氧化矽、氮化矽、氮氧化矽、其他合適的隔離材料（例如，包括矽、氧、氮、碳或其他合適的隔離成分）或其組合。隔離部件230可以包括不同的結構，例如淺溝槽隔離（shallow trench isolation, STI）結構及/或深溝槽隔離（deep trench isolation, DTI）結構。在一個實施例中，可以通過用絕緣體材料填充鰭片218之間的溝槽（例如，通過使用CVD製程或旋塗玻璃製程），執行化學機械研磨（chemical mechanical polishing, CMP）製程以去除多餘的絕緣體材料及/或平坦化絕緣體材料層的頂表面，並回蝕絕緣體材料層以形成隔離部件230。在一些實施例中，隔離部件230包括多層結構，例如設置在熱氧化物襯層上方的氮化矽層。
包覆層231沉積在鰭片218的側壁表面上方和隔離部件230上方。在一個實施例中，包覆層231包括SiGe。可以使用CVD、物理氣相沉積（physical vapor deposition, PVD）、原子層沉積（atomic layer deposition, ALD）、高密度電漿CVD（high density plasma CVD, HDPCVD）、金屬有機CVD（metal organic CVD, MOCVD）、遠程電漿CVD（remote plasma CVD, RPCVD）、電漿輔助CVD（plasma enhanced CVD, PECVD）、低壓CVD（low-pressure CVD, LPCVD）、原子層CVD（atomic layer CVD, ALCVD）、大氣壓CVD（atmospheric pressure CVD, APCVD）、其他合適的方法或其組合沉積包覆層231。
在本實施例中，介電鰭片229包括介電襯層232、介電填充層233和介電罩（helmet）234。在替代實施例中，介電鰭片229可以具有不同的配置。介電襯層232沉積在包覆層231的側壁上方和隔離部件230的頂表面上，並且介電填充層233沉積在介電襯層232上並填充鰭片218之間的間隙。在一個實施例中，介電襯層232包括低介電常數介電材料，例如包括Si、O、N和C的介電材料。示例的低介電常數介電材料包括摻氟矽酸鹽玻璃（fluoride-doped silicate glass, FSG）、摻碳氧化矽、Black Diamond®（應用材料，加州聖塔克拉拉）、乾凝膠（Xerogel）、氣凝膠（Aerogel）、非晶質氟化碳（amorphous fluorinated carbon）、聚對二甲苯（Parylene）、苯並環丁烯（benzocyclobutene, BCB）、SiLK®（陶氏化學，密西根米特蘭）、聚醯亞胺或其組合。低介電常數介電材料通常是指具有低介電常數的介電材料，例如，介電常數小於氧化矽的介電常數（介電常數約為3.9）。可以使用CVD、PVD、ALD、HDPCVD、MOCVD、RPCVD、PECVD、LPCVD、ALCVD、APCVD、其他合適的方法或其組合沉積介電襯層232。在一實施例中，介電填充層233包括氧化矽、氮化矽、氮氧化矽、四乙基原矽酸鹽（tetraethylorthosilicate, TEOS）氧化物、磷矽酸鹽玻璃（phosphosilicate glass, PSG）、硼磷矽酸鹽玻璃（borophosphosilicate glass, BPSG）、低介電常數介電材料、其他合適的介電材料或其組合。介電填充層233可以使用流動式CVD（flowable CVD, FCVD）製程沉積，其包括，例如，在裝置200上沉積可流動材料（例如液體化合物）並通過合適的技術（例如熱退火及/或紫外線輻射處理）將可流動材料轉化為固體材料。介電填充層233可以使用其他類型的方法沉積。
介電罩234沉積在介電層232和233上方以及鰭片218兩側側壁上的包覆層231之間。在一個實施例中，介電罩234包括高介電常數介電材料，例如HfO2 、HfSiO、HfSiO4 、HfSiON、HfLaO、HfTaO、HfTiO、HfZrO、HfAlOx 、ZrO、ZrO2 、ZrSiO2 、AlO、AlSiO、Al2 O3 、TiO、TiO2 、LaO、LaSiO、Ta2 O3 、Ta2 O5 、Y2 O3 、SrTiO3 、BaZrO、BaTiO3 （BTO）、（Ba、Sr）TiO3 （BST）、Si3 N4 、二氧化鉿-氧化鋁（HfO2 -Al2 O3 ）合金、其他合適的高介電常數介電材料或其組合。高介電常數介電材料通常是指具有高介電常數的介電材料，例如，介電常數大於氧化矽的介電常數（介電常數約為3.9）。介電罩234可以由本揭露所述的任何製程形成，例如ALD、CVD、PVD、基於氧化的沉積製程、其他合適的製程或其組合。在一個實施例中，可以使用選擇性蝕刻製程凹蝕介電層232和233，其製程蝕刻介電層232和233而沒有（或最少地）蝕刻硬遮罩206（第3B圖）和包覆層231。然後，在凹口中沉積一種或多種介電材料，並對一種或多種介電材料進行CMP製程以形成介電罩234。隨後，去除硬遮罩層206，並在鰭片218上方形成犧牲閘極堆疊240。
參考第4B圖，犧牲閘極堆疊240包括虛設閘極介電層235、虛設閘極電極層245和一層或多層硬遮罩層246。在本實施例中，犧牲閘極堆疊240將在後續的製造步驟中被功能性閘極堆疊240’替換。在一些實施例中，虛設閘極介電質235包括介電材料，例如氧化矽、高介電常數介電材料、其他合適的介電材料或其組合；虛設閘極電極層245包括多晶矽或其他合適的材料；以及一個或多個硬遮罩層246包括氧化矽、氮化矽或其他合適的材料。犧牲閘極堆疊240可以通過沉積製程、微影製程、蝕刻製程、其他合適的製程或其組合形成。例如，層235、245和246可以使用CVD、PVD、ALD或其他合適的方法沉積。之後，執行微影圖案化和蝕刻製程以圖案化層235、245和246以形成犧牲閘極堆疊240，如第4B圖所示。微影圖案化製程包括光阻塗佈（例如旋塗）、軟烘烤、遮罩對準、曝光、曝光後烘烤、光阻顯影、沖洗、乾燥（例如，硬烘烤）、其他合適的微影製程或其組合。蝕刻製程包括乾式蝕刻製程、濕式蝕刻製程、其他蝕刻方法或其組合。
繼續參考第4B圖，閘極間隔物247設置在犧牲閘極堆疊240的側壁上。閘極間隔物247可以通過任何合適的製程形成並且包括介電材料。介電材料可以包括矽、氧、碳、氮、其他合適材料或其組合（例如氧化矽、氮化矽、氮氧化矽（SiON）、碳化矽、碳氮化矽（SiCN）、碳氧化矽（SiOC）、碳氮氧化矽（SiOCN））。例如，包括矽和氮的介電層，例如氮化矽層，可以沉積在犧牲閘極堆疊240上，並且隨後被蝕刻（例如，非等向性蝕刻）以形成閘極間隔物247。在一些實施例中，閘極間隔物247包括多層結構，例如包括氮化矽的第一介電層和包括氧化矽的第二介電層。在一些實施例中，與犧牲閘極堆疊240相鄰地形成多於一組的間隔物，例如密封（seal）間隔物、偏置間隔物（offset spacers）、犧牲間隔物、虛設間隔物及/或主要間隔物。
在操作104，方法100（第1A圖）通過蝕刻與閘極間隔物247相鄰的鰭片218以形成源極/汲極（S/D）溝槽250。根據一些實施例，在第5A-5D圖中示出所得結構。第5A圖繪示裝置200的俯視圖，並且第5B、5C和5D圖分別沿著第5A圖中的B-B線、C-C線和D-D線繪示裝置200的部份剖面圖。詳細而言，C-C線切進電晶體的源極區並平行於閘極堆疊240，而D-D線切進電晶體的汲極區並平行於閘極堆疊240。第6A至12A圖、第14A至20A圖中的C-C線和D-D線的配置相似。
在所描繪的實施例中，蝕刻製程完全去除鰭片218的源極/汲極區中的半導體層堆疊205，從而露出源極/汲極區中的鰭片218的半導體層204。源極/汲極溝槽250因此具有由半導體層堆疊205的剩餘部份定義的側壁，以及由半導體層204和隔離結構230定義的底部，所述剩餘部份設置在閘極堆疊240下方的通道區中。在一些實施例中，蝕刻製程去除一些但不是全部的半導體層堆疊205，使得源極/汲極溝槽250具有由源極/汲極區中的半導體層210或半導體層215定義的底部。在一些實施例中，蝕刻製程進一步去除鰭片218的半導體層204的一些但並非全部，使得源極/汲極溝槽250延伸到隔離結構230的最頂表面下方。蝕刻製程可包括乾式蝕刻製程、濕式蝕刻製程、其他合適的蝕刻製程或其組合。在一些實施例中，蝕刻製程是多步驟蝕刻製程。例如，蝕刻製程可以交替蝕刻劑以單獨和交替地去除半導體層210和半導體層215。在一些實施例中，蝕刻製程的參數被配置為選擇性地蝕刻半導體層堆疊，而最少地（至沒有）蝕刻閘極堆疊240及/或隔離部件230。在一些實施例中，執行例如本揭露描述的微影製程以形成覆蓋閘極堆疊240及/或隔離部件230的圖案化的遮罩層，並且蝕刻製程使用圖案化的遮罩層作為蝕刻遮罩。
在操作106，方法100（第1A圖）形成內部間隔物255。在第6A-6D圖中示出所得結構。第6A圖繪示裝置200的俯視圖，並且第6B、6C和6D圖分別沿著第6A圖中的B-B線、C-C線和D-D線繪示裝置200的部份剖面圖。在一個實施例中，執行第一蝕刻製程，其製程選擇性地蝕刻由源極/汲極溝槽250露出的半導體層210，並且最少地（至沒有）蝕刻半導體層215，從而在半導體層215之間以及在閘極間隔物247下方的半導體層215和204之間形成間隙。半導體層215的部份（邊緣）因此懸置（suspended）在閘極間隔物247下方的通道區中。第一蝕刻製程可以是乾式蝕刻製程、濕式蝕刻製程、其他合適的蝕刻製程或其組合。然後進行沉積製程以形成間隔物層，間隔物層部份地（並且在一些實施例中，完全地）填充源極/汲極溝槽250。沉積製程被配置為確保間隔物層填充半導體層215之間以及閘極間隔物247下方的半導體層215和204之間的間隙。之後進行第二蝕刻製程，選擇性地蝕刻間隔物層以形成如第6B圖所示的內部間隔物255，同時最少地（至沒有）蝕刻半導體層215、虛設閘極堆疊240和閘極間隔物247。內部間隔物255包括與半導體層215的材料和閘極間隔物247的材料不同的材料，以在第二蝕刻製程期間實現期望的蝕刻選擇性。間隔物層255可以包括介電材料，其介電材料包括矽、氧、碳、氮、其他合適的材料或其組合（例如，氧化矽、氮化矽、氮氧化矽、碳化矽或氮碳氧化矽）。在一些實施例中，內部間隔物層255包括低介電常數介電材料，例如本揭露所述的低介電常數介電材料。
在操作108，方法100（第1A圖）形成蝕刻遮罩241，其覆蓋一些源極/汲極溝槽250中，並且留下通過蝕刻遮罩241中的開口238露出的其他源極/汲極溝槽250。通過蝕刻遮罩241露出的源極/汲極溝槽250將經歷額外的製程以提供具有擴大底部的源極/汲極部件，以降低與背側電源軌的接觸電阻。第7A圖繪示裝置200的俯視圖，並且第7B、7C和7D圖分別沿著第7A圖中的B-B線、C-C線和D-D線繪示裝置200的部份剖面圖。在本實施例中，電晶體的源極區通過蝕刻遮罩241（第6C圖）露出，電晶體的汲極區被蝕刻遮罩241（第6D圖）覆蓋。在替代實施例中，電晶體的源極區被蝕刻遮罩241覆蓋，並且電晶體的汲極區通過蝕刻遮罩241露出。在一些實施例中，同一電晶體的源極區和汲極區都可以通過蝕刻遮罩241露出。為了討論方便，通過蝕刻遮罩241露出的源極/汲極溝槽250被稱為源極/汲極溝槽250’。在本實施例中，蝕刻遮罩241包括圖案化的硬遮罩236和圖案化的光阻237。在一些實施例中，蝕刻遮罩241可以額外包括位於圖案化的硬遮罩236和圖案化的光阻237之間的底部抗反射塗層（bottom anti-reflective coating, BARC）層。可以通過光阻塗佈（例如旋塗）、軟烘烤、遮罩對準、曝光、曝光後烘烤、光阻顯影、沖洗、乾燥（例如，硬烘烤）、其他合適的微影製程或其組合形成圖案化的光阻237。
在操作110，方法100（第1A圖）蝕刻源極/汲極溝槽250’以將其延伸得更深。在第8A-8D圖中示出所得結構。第8A圖繪示裝置200的俯視圖，並且第8B、8C和8D圖分別沿著第8A圖中的B-B線、C-C線和D-D線繪示裝置200的部份剖面圖。蝕刻製程可包括乾式蝕刻、濕式蝕刻、反應離子蝕刻或其他合適的蝕刻。在此實施例中，蝕刻製程大抵是非等向性蝕刻（即，大抵垂直）。此外，調整蝕刻製程以選擇性地蝕刻半導體層204的材料，並且不（或最少地）蝕刻蝕刻遮罩241、閘極間隔物247、虛設介電鰭片229、閘極硬遮罩層246、內部間隔物255和隔離結構230。在一些實施例中，源極/汲極溝槽250’被延伸使得其底表面在隔離結構230的頂表面之下距離d1。在一些實施例中，距離dl可以在大約30奈米至大約60奈米的範圍內，例如大約40奈米至大約50奈米，取決於半導體層204的厚度。將源極/汲極溝槽250’蝕刻得更深允許源極/汲極部件擴大的底部更靠近背側電源軌。然而，如果源極/汲極溝槽250’太深，則隔離結構230的橫向蝕刻（參見以下的操作112）在一些情況下可能變得困難。例如，使蝕刻劑進入深溝槽並仍然控制蝕刻輪廓可能變得困難。因此，溝槽250’的深度被控制在上述範圍內（例如使其底表面低於隔離結構230的頂表面約30奈米至約60奈米）。
在操作112，方法100（第1A圖）對源極/汲極溝槽250’執行另一蝕刻以特別擴大其被隔離結構230圍繞的底部。在第9A-9D圖中示出所得結構。第9A圖繪示裝置200的俯視圖，並且第9B、9C和9D圖分別沿著第9A圖中的B-B線、C-C線和D-D線繪示裝置200的部份剖面圖。源極/汲極溝槽250’的底部253被擴大以具有沿著“z”方向變寬然後變窄的輪廓。在操作112之前，源極/汲極溝槽250’的底部具有接近垂直的輪廓（參考第8C圖）或沿著“z”方向隨著上升而變得更窄的大抵梯形（trapezoidal）的輪廓（在任何一種情況下，其側壁都是直線性的（linear））。蝕刻製程對隔離結構230的材料具有選擇性，並且不（或最少地）蝕刻閘極間隔物247、虛設介電鰭片229、閘極硬遮罩層246、內部間隔物255、通道層215、以及半導體層204。在各種實施例中，蝕刻製程可以包括乾式蝕刻、濕式蝕刻、反應離子蝕刻或其他合適的蝕刻。詳細而言，蝕刻製程包括橫向蝕刻隔離結構230的等向性蝕刻成分。在一個實施例中，蝕刻製程使用乾式（電漿）蝕刻，其中電漿由NF3 和NH3 氣體或具有氟、氮和氫成分的相似氣體產生。操作112可調整各種蝕刻參數以控制底部253的輪廓（例如垂直延伸（extension）和橫向擴張（expansion）的量）。例如，其可以調整NH3 氣體流量、NH3 氣體流量與NF3 氣體流量的比例、蝕刻時間、蝕刻壓力等。在源極/汲極溝槽250’期望的橫向擴張w3在10奈米至20奈米的實施例中，NH3 氣體流速可以調整在約150sccm至約220sccm的範圍，NH3 氣流與NF3 氣流的比例可以調整在10至20的範圍，蝕刻時間可以調整在約20秒至約40秒的範圍。在一個實施例中，源極/汲極溝槽250’沿著“y”方向橫向（或側向）擴張距離w3進入隔離結構230之中，如在隔離結構230內的源極/汲極溝槽250’的最寬部份處測量。在一些實施例中，距離w3在約5奈米至約25奈米的範圍，例如在約10奈米至約20奈米的範圍。如果距離w3太小（例如小於5奈米），在一些情況下，擴大源極/汲極部件的效果可能不夠顯著。如果距離w3太大（例如超過30奈米），則存在完全突破隔離結構230並使相鄰的源極/汲極部件短路的風險。此外，操作112可以沿著“z”方向更深地延伸源極/汲極溝槽250’。 在操作112完成之後，源極/汲極溝槽250’在隔離結構230的頂表面下方延伸距離d2。在各種實施例中，d2大於d1。例如，d2可以比d1大約10奈米至約40奈米，例如約20奈米至約30奈米。在一些實施例中，源極/汲極溝槽250’正下方的半導體層204的寬度沿著“y”方向具有寬度w4。在一些實施例中，寬度w4可以在大約30奈米到大約40奈米的範圍。在那些實施例中，源極/汲極溝槽250’的底部253具有大約（w4+2
Figure 02_image001
w3）的總寬度w5，其在40至90奈米的範圍。上述範圍的重要性相似於以上關於寬度w3所討論。在一些實施例中，源極/汲極溝槽250’的底部253在介電鰭片229之一或兩者正下方延伸以獲得額外的寬度。易言之，寬度w5大於介電鰭片229之間的間距S1。在那些實施例中，導孔結構（例如第20C圖中的導孔282）具有更大的寬度和更大的體積，以進一步降低電阻。
在操作114，方法100（第1B圖）在去除圖案化的光阻237（例如通過剝離、灰化或其他方法）之後在源極/汲極溝槽250’中形成半導體層239。根據一實施例，在第10A-10D圖中示出所得結構。第10A圖繪示裝置200的俯視圖，並且第10B、10C和10D圖分別沿著第10A圖中的B-B線、C-C線和D-D線繪示裝置200的部份剖面圖。可以使用磊晶成長製程或通過其他合適的製程沉積半導體層239。在一些實施例中，半導體層239的磊晶成長通過分子束磊晶（MBE）製程、化學氣相沉積（CVD）製程、金屬有機化學氣相沉積（MOCVD）製程、其他合適的磊晶成長製程或其組合實現。半導體層239包括與包括在半導體層204中的半導體材料不同的半導體材料以在後續製程期間實現蝕刻選擇性。例如，半導體層239和204可以包括不同的材料、不同的組成原子百分比、不同的組成重量百分比及/或其他特性以在蝕刻製程期間實現期望的蝕刻選擇性。在一個實施例中，半導體層204包括矽並且半導體層239包括矽鍺。在另一個實施例中，半導體層239和204都可以包括矽鍺，但是具有不同的矽原子百分比。本揭露也考慮半導體層239和204包括可以提供期望蝕刻選擇性的半導體材料的任何組合，包括本揭露的任何半導體材料。由於汲極區（第10D圖）被圖案化的硬遮罩層236覆蓋，半導體層239僅沉積在源極區（第10C圖）中。半導體層239沉積的厚度使其靠近堆疊205（第10B圖）的底部並且與隔離部件230（第10C圖）的頂表面大致齊平。如果半導體層239最初成長得比第10B和10C圖所示的水平高，則操作114可以包括蝕刻製程，其蝕刻製程使半導體層239凹陷到第10B和10C圖所示的水平。在沉積半導體層239之後，操作114通過一個或多個蝕刻製程去除圖案化的硬遮罩層236。如以下將討論，在各種實施例中，操作110和112中的額外蝕刻和操作114中的半導體層239的成長可以僅在源極區中進行、僅在汲極區中進行或在源極區和汲極區兩者中進行。
在操作116，方法100（第1B圖）在源極/汲極溝槽250中磊晶成長半導體源極/汲極部件260並且在源極/汲極溝槽250’中磊晶成長半導體源極/汲極部件260’。根據一實施例，在第11A-11D圖中示出所得結構。第11A圖繪示裝置200的俯視圖，並且第11B、11C和11D圖分別沿著第11A圖中的B-B線、C-C線和D-D線繪示裝置200的部份剖面圖。
如第11B、11C和11D圖所示，磊晶源極/汲極部件260從半導體層204和從在源極/汲極溝槽250處的半導體層215成長，磊晶源極/汲極部件260’從半導體層239和從在源極/汲極溝槽250’處的半導體層215成長。磊晶製成可以使用化學氣相沉積（CVD）技術（例如，氣相磊晶（vapor phase epitaxy, VPE）及/或超高真空CVD（ultra-high vacuum CVD, UHV-CVD））、分子束磊晶、其他合適的磊晶成長製程或其組合。磊晶製程可以使用氣態及/或液態前驅物，其與半導體層204、239和215的成分相互作用。磊晶源極/汲極部件260/260’可以對於n型電晶體或p型電晶體分別摻雜有n型摻質或p型摻質。在一些實施例中，對於n型電晶體，磊晶源極/汲極部件260/260’包括矽並且可以摻雜有碳、磷、砷、其他n型摻質或其組合（例如，形成Si：C磊晶源極/汲極部件、Si：P磊晶源極/汲極部件或Si：C：P磊晶源極/汲極部件）。在一些實施例中，對於p型電晶體，磊晶源極/汲極部件260/260’包括矽鍺或鍺，並且可以摻雜有硼、其他p型摻質或其組合（例如，形成Si：Ge：B磊晶源極/汲極部件）。在一些實施例中，磊晶源極/汲極部件260/260’包括多於一個磊晶半導體層，其中磊晶半導體層可以包括相同或不同的材料及/或摻質濃度。此外，在一個實施例中，源極/汲極部件260’（或至少其鄰接半導體層239的部份）包括與半導體層239不同的材料組成以在背側導孔形成製程期間實現蝕刻選擇性。例如，在一個實施例中，半導體層239包括SiGe並且源極/汲極部件260’包括Si（對於n型電晶體）。例如，在另一個實施例中，半導體層239包括具有第一Ge原子百分比的SiGe，並且源極/汲極部件260’包括具有第二Ge原子百分比的SiGe（對於p型電晶體），並且第一和第二Ge原子百分比不同。在一些實施例中，磊晶源極/汲極部件260/260’包括在相應的通道區中實現所需拉伸應力（tensile stress）及/或壓縮應力（compressive stress）的材料及/或摻質。在一些實施例中，磊晶源極/汲極部件260/260’在沉積期間通過對磊晶製程的源材料添加雜質摻雜（即，原位（in situ）摻雜）。在一些實施例中，磊晶源極/汲極部件260/260’在沉積製程之後通過離子佈植製程摻雜。在一些實施例中，執行退火製程（例如，快速熱退火（rapid thermal annealing, RTA）及/或雷射退火）以活化磊晶源極/汲極部件260/260’中的摻質。在一些實施例中，磊晶源極/汲極部件260/260’在單獨的製程順序中形成，包括，例如在n型GAA電晶體區中形成磊晶源極/汲極部件260/260’時遮蔽p型GAA電晶體區，並且在p型GAA電晶體區中形成磊晶源極/汲極部件260/260’時遮蔽n型GAA電晶體區。
此外，如第11C和11D圖所示，源極/汲極部件260/260’在介電鰭片229之間的空間中擴張。上述擴張可能是由不同晶面（crystal facets）的不同成長速率所致。參考第11C圖，源極/汲極部件260’具有沿著“z”方向的高度H1和沿著“y”方向的寬度w1（在源極/汲極部件260’的最寬部份處測量）。在一些實施例中，H1可以在大約40奈米至大約70奈米的範圍，並且w1可以在大約30奈米至大約60奈米的範圍。在一些實施例中，w1與H1的比例可在約0.4至1.5的範。參考第11D圖，源極/汲極部件260具有沿著“z”方向的高度H6和沿著“y”方向的寬度w6（在源極/汲極部件260的最寬部份處測量）。在一些實施例中，H6可以在大約40奈米至大約70奈米的範圍，並且w6可以在大約30奈米至大約60奈米的範圍。在一些實施例中，w6與H6的比例可在約0.4至1.5的範圍。在各種實施例中，源極/汲極部件260和260’的尺寸可以大致相同或不同。在一些情況下，源極/汲極部件260和260’為前側源極/汲極接觸件提供落置區（landing areas）。因此，它們成長到足夠大的體積以提供足夠的落置面積。如果寬度w1和w6及/或高度H1和H6太小（例如小於上述範圍的下限），則源極/汲極部件260/260’的體積可能太小，將負面地影響電晶體性能。在一些實施例中，它們的寬度由介電鰭片229之間的間距限制，並且它們的高度被控制為與介電鰭片229的高度大致相同。擁有上述的配置有助於將相鄰源極/汲極部件短路的風險降至最低。在各種實施例中，半導體層239的寬度w5大於寬度w1。
繼續參考第11D圖，半導體層204在源極/汲極部件260附近具有寬度w2並且具有高度H2。在一些實施例中，寬度w2在約20奈米至約40奈米的範圍，高度H2在約14奈米至約26奈米的範圍。在各種實施例中，w1與w2的比例在1至3的範圍，並且w6與w2的比例在1至3的範圍。如上所述，一般而言希望源極/汲極部件260/260’較寬（例如，為了降低源極/汲極電阻），因此w1和w6大於w2。然而，w1:w2和w6:w2的比例不能太大。首先，寬度w1和w6的上限受到增加裝置整合度的期望的限制。其次，寬度w2不能太小。否則，背側源極/汲極電阻可能過大或背側介電填充製程（替換半導體層204）可能變得困難。
在操作118，方法100（第1B圖）形成接觸蝕刻停止層（contact etch stop layer, CESL）269和層間介電（inter-layer dielectric, ILD）層270。根據一實施例，在第12A-12D圖中示出所得結構。第12A圖繪示裝置200的俯視圖，並且第12B、12C和12D圖分別沿著第12A圖中的B-B線、C-C線和D-D線繪示裝置200的部份剖面圖。
如第12B-12D圖所示，CESL 269沉積在源極/汲極部件260/260’之上，並且ILD層270沉積在CESL 269之上並填充相對的閘極間隔物247之間的空間。CESL 269包括不同於ILD層270且不同於介電層234的材料。CESL 269可以包括La2 O3 、Al2 O3 、SiOCN、SiOC、SiCN、SiO2 、SiC、ZnO、ZrN、Zr2 Al3 O9 、TiO2 、TaO2 、ZrO2 、HfO2 、Si3 N4 、Y2 O3 、AlON、TaCN、ZrSi或其他合適的材料，並且可以通過CVD、PVD、ALD或其他合適的方法形成。ILD層270可以包括四乙基原矽酸鹽（tetraethylorthosilicate, TEOS）氧化物、未摻雜的矽酸鹽玻璃或摻雜的氧化矽，例如硼磷矽酸鹽玻璃（borophosphosilicate glass, BPSG）、摻氟石英玻璃（fluoride-doped silica glass, FSG）、磷矽酸鹽玻璃（phosphosilicate glass, PSG）、摻硼矽玻璃（boron doped silicon glass, BSG）、低介電常數介電材料、其他合適的介電材料或其組合。可以通過PECVD（電漿輔助CVD）、FCVD（流動式CVD）或其他合適的方法形成ILD層270。在沉積CESL 269以及ILD層270之後，可以執行CMP製程及/或其他平坦化製程，直到到達（露出）虛設閘極堆疊240的頂部（或頂表面）。在一些實施例中，平坦化製程去除虛設閘極堆疊240的硬遮罩層246以露出下方的虛設閘極電極245，例如多晶矽閘極電極層。
在操作120，方法100（第1B圖）用功能性閘極堆疊240’（例如高介電常數金屬閘極）替換虛設閘極堆疊240。根據一實施例，在第13A、13B和13C圖中示出所得結構。第13A圖繪示裝置200的俯視圖，並且第13B和13C圖分別沿著第13A圖中的B-B線和C-C線繪示裝置200的部份剖面圖。這涉及以下簡要描述的各種製程。
首先，操作120使用一個或多個蝕刻製程去除虛設閘極堆疊240（虛設閘極電極245和虛設閘極介電層235，參考第4B圖）。其形成閘極溝槽。蝕刻製程可為乾式蝕刻製程、濕式蝕刻製程、其他合適的蝕刻製程或其組合。在一些實施例中，蝕刻製程是多步驟蝕刻製程。例如，蝕刻製程可以交替蝕刻劑以分別去除虛設閘極堆疊240的各個膜層。在一些實施例中，蝕刻製程被配置為選擇性地蝕刻虛設閘極堆疊240，而最少地（至沒有）蝕刻裝置200的其他部件，例如ILD層270、閘極間隔物247、隔離部件230、包覆層231、半導體層215和半導體層210。
接下來，操作120去除在閘極溝槽中露出的包覆層231。蝕刻製程可以選擇性地蝕刻包覆層231，而最少地（至沒有）蝕刻半導體層215、閘極間隔物247和內部間隔物255。
接著，操作120去除在閘極溝槽中露出的半導體層210，留下懸置於半導體層204上方且與源極/汲極部件260/260’連接的半導體層215。其製程也被稱為通道釋出（release）製程並且半導體層215也被稱為通道層。蝕刻製程選擇性地蝕刻半導體層 210，而最少地（至沒有）蝕刻半導體層215，並且在一些實施例中，最少地（至沒有）蝕刻閘極間隔物247及/或內部間隔物255。在裝置200是FinFET的實施例中，因為在通道區中只有通道層215而沒有半導體層210，所以省略通道釋出製程。
接下來，操作120形成包繞（wrap around）每個半導體層215的閘極介電層349，並在閘極介電層349上方形成閘極電極350。功能性閘極堆疊240’包括閘極介電層349和閘極電極350。閘極介電層349可以包括高介電常數介質材料，例如HfO2 、HfSiO、HfSiO4 、HfSiON、HfLaO、HfTaO、HfTiO、HfZrO、HfAlOx 、ZrO、ZrO2 、ZrSiO2 、AlO、AlSiO、Al2 O3 、TiO、TiO2 、LaO、LaSiO、Ta2 O3 、Ta2 O5 、Y2 O3 、SrTiO3 、BaZrO、BaTiO3 （BTO）、（Ba、Sr）TiO3 （BST）、Si3 N4 、二氧化鉿-氧化鋁（HfO2 -Al2 O3 ）合金、其他合適的高介電常數介電材料或其組合。高介電常數介電材料通常是指具有高介電常數的介電材料，例如，介電常數大於氧化矽的介電常數（介電常數約為3.9）。可以通過化學氧化、熱氧化、原子層沉積（ALD）、化學氣相沉積（CVD）及/或其他合適的方法形成閘極介電層349。在一些實施例中，閘極堆疊240’還包括在閘極介電層349和通道層215之間的界面層。界面層可以包括二氧化矽、氮氧化矽或其他合適的材料。在一些實施例中，閘極電極層350包括n型或p型功函數層和金屬填充層。例如，n型功函數層可以包括具有足夠低的有效功函數的金屬，例如鈦、鋁、碳化鉭、氮化碳化鉭、氮化鉭矽或其組合。例如，p型功函數層可以包括具有足夠大的有效功函數的金屬，例如氮化鈦、氮化鉭、釕、鉬、鎢、鉑或其組合。例如，金屬填充層可以包括鋁、鎢、鈷、銅及/或其他合適的材料。可以通過CVD、PVD、電鍍及/或其他合適的製程形成閘極電極層350。由於閘極堆疊240’包括高介電常數介電層和金屬層，因此其也被稱為高介電常數金屬閘極。
在操作122，方法100（第1B圖）執行中段（mid-end-of-line, MEOL）製程和後段（back-end-of-line, BEOL）製程。根據一實施例，在第14A-14D圖中示出所得結構。第14A圖繪示裝置200的俯視圖，並且第14B、14C和14D圖分別沿著第14A圖中的B-B線、C-C線和D-D線繪示裝置200的部份剖面圖。例如，操作122蝕刻源極/汲極接觸孔以露出一些源極/汲極部件260/260’。在一些實施例中，可以部份蝕刻源極/汲極部件260/260’。蝕刻製程可以是乾式蝕刻、濕式蝕刻、反應離子蝕刻或其他蝕刻方法。之後，操作122在源極/汲極部件260/260’上方形成矽化物部件273並在矽化物部件273上方形成源極/汲極接觸件（或導孔）275。由於矽化物部件273和源極/汲極接觸件275形成在裝置200的前側，它們也分別稱為前側矽化物部件273和前側源極/汲極接觸件275。
矽化物部件273可以包括矽化鈦（TiSi）、矽化鎳（NiSi）、矽化鎢（WSi）、矽化鎳鉑（NiPtSi）、矽化鎳鉑鍺（NiPtGeSi）、矽化鎳鍺（NiGeSi）、矽化鐿（YbSi） 、矽化鉑（PtSi）、矽化銥（IrSi）、矽化鉺（ErSi）、矽化鈷（CoSi）或其他合適的化合物。在一實施例中，源極/汲極接觸件275可以包括導電阻障層和在導電阻障層上方的金屬填充層。導電阻擋層可以包括鈦（Ti）、鉭（Ta）、鎢（W）、鈷（Co）、釕（Ru）或導電氮化物，例如氮化鈦（TiN）、氮化鈦鋁（TiAlN）、氮化鎢（WN）、氮化鉭（TaN）或其組合，並且可以通過CVD、PVD、ALD及/或其他合適的製程形成。金屬填充層可以包括鎢（W）、鈷（Co）、鉬（Mo）、釕（Ru）、或其他金屬，並且可以通過CVD、PVD、ALD、電鍍或其他合適的製程形成。在一些實施例中，可以在源極/汲極接觸件275中省略導電阻障層。
操作122可以形成連接到閘極堆疊240’的閘極導孔，形成連接到源極/汲極接觸件275的源極/汲極接觸導孔，以及形成一個或多個互連層，其具有嵌入介電層中的導線和導孔。一個或多個互連層連接各個電晶體的閘極、源極和汲極以及裝置200中的其他電路，以部份或整體形成積體電路。操作122還可以在互連層上方形成鈍化層。在第14B圖所示的示例中，層277用於表示各種介電層和金屬層，包括在裝置200的前側形成在源極/汲極接觸件275上方的互連層和鈍化層。
在操作124，方法100（第1C圖）將裝置200上下顛倒，並將裝置200的前側附接到載體370，例如第15B圖所示。第15A圖繪示裝置200的俯視圖，並且第15B、15C、15D和15E圖分別沿著第15A圖中的B-B線、C-C線、D-D線和E-E線繪示裝置200的部份剖面圖。這使得可以從裝置200的背側進行進一步製程。操作124可以使用任何合適的附接製程，例如直接鍵合、混合鍵合（hybrid bonding）、使用黏著劑或其他鍵合方法。操作124可以進一步包括對準、退火及/或其他製程。在一些實施例中，載體370可以是矽晶圓。在第15B-15E圖中（如同在以下描述的其他圖式中），“z”方向從裝置200的背側指向裝置200的前側，而“-z”方向從裝置200的前側指向裝置200的背側。
在操作126，方法100（第1C圖）從裝置200的背側薄化裝置200，直到半導體層204、半導體層239和隔離結構230從裝置200的背側露出。根據一實施例，第16A-16E圖示出所得的結構。第16A圖繪示裝置200的俯視圖，並且第16B、16C、16D和16E圖分別沿著第16A圖中的B-B線、C-C線、D-D線和E-E線繪示裝置200的部份剖面圖。薄化製程可以包括機械研磨製程及/或化學薄化製程。在機械研磨製程中，可以首先從基板201上去除大量的基板材料。之後，化學薄化製程可以將蝕刻化學品施加到基板201的背側，以進一步薄化基板201。
在操作128，方法100（第1C圖）選擇性地蝕刻半導體層204（以及部份的鰭片218），以在閘極堆疊240’和源極/汲極部件260/260’的背側上形成溝槽272。根據一實施例，第17A-17E圖示出所得的結構。第17A圖繪示裝置200的俯視圖，並且第17B、17C、17D和17E圖分別沿著第17A圖中的B-B線、C-C線、D-D線和E-E線繪示裝置200的部份剖面圖。在本實施例中，操作128應用蝕刻製程，其蝕刻製程被調整為對半導體層204的材料進行選擇性的蝕刻製程，而未（或最少地）蝕刻半導體層239、源極/汲極部件260、閘極堆疊240’和隔離結構230。蝕刻製程可以是乾式蝕刻、濕式蝕刻、反應離子蝕刻或其他蝕刻方法。
在操作130，方法100（第1C圖）形成一個或多個介電層276以填充溝槽272。例如，一個或多個介電層276可以包括介電襯層274以及一個或多個介電層276。根據一實施例，第18A-18E圖示出所得的結構。第18A圖繪示裝置200的俯視圖，並且第18B、18C、18D和18E圖分別沿著第18A圖中的B-B線、C-C線、D-D線和E-E線繪示裝置200的部份剖面圖。在一些實施例中，介電襯層274可以包括La2 O3 、Al2 O3 、SiOCN、SiOC、SiCN、SiO2 、SiC、ZnO、ZrN、Zr2 Al3 O9 、TiO2 、TaO2 、ZrO2 、HfO2 、Si3 N4 、Y2 O3 、AlON、TaCN、ZrSi或其他合適的材料；並且可以使用CVD、PVD、ALD或其他合適的方法形成介電襯層274。在一些實施例中，介電層276可以包括四乙基原矽酸鹽（TEOS）氧化物、未摻雜的矽酸鹽玻璃或摻雜的氧化矽，例如硼磷矽酸鹽玻璃（BPSG）、摻氟石英玻璃（FSG）、磷矽酸鹽玻璃（PSG）、摻硼矽玻璃（BSG）及/或其他合適的介電材料。可以通過PECVD（電漿輔助CVD）、FCVD（流動式CVD）或其他合適的方法形成介電層276。
在操作132，方法100（第1C圖）從裝置200的背側去除半導體層239。根據一實施例，第19A-19E圖示出所得的結構。第19A圖繪示裝置200的俯視圖，並且第19B、19C、19D和19E圖分別沿著第19A圖中的B-B線、C-C線、D-D線和E-E線繪示裝置200的部份剖面圖。在本實施例中，操作132應用蝕刻製程，其蝕刻製程被調整為對半導體層239的材料（在一個實施例中例如為SiGe）具有選擇性，而沒有（或最少）蝕刻介電襯層274、介電層276和隔離部件230。在一些實施例中，蝕刻製程可以不蝕刻源極部件260’，並且在一些替代實施例中可以部份地蝕刻源極部件260’。蝕刻製程產生從裝置200的背側露出源極部件260’的溝槽278。蝕刻製程可以是乾式蝕刻、濕式蝕刻、反應離子蝕刻或其他蝕刻方法。詳細而言，在本實施例中，半導體層239的蝕刻是自對準的。換言之，操作132不需要形成蝕刻遮罩（例如，通過微影製程形成的蝕刻遮罩）以蝕刻半導體層239。相反地，其依賴半導體層239及其周圍膜層中材料的蝕刻選擇性。這有益處地形成與下方的源極部件260’對齊的溝槽278，而不具有未對齊的情況，例如由微影覆蓋偏移（overlay shift）所引起。使用此製程將產生與源極部件260’理想地對齊的背側源極接觸件（或源極導孔），如下所述。此外，由於半導體層239具有擴大的輪廓，而溝槽278也具有擴大的輪廓，這使得在其中形成矽化物部件以及導孔結構時更容易填充金屬材料。
在操作134，方法100（第1C圖）在溝槽（或通孔）278中形成背側源極矽化物部件280和背側接觸件（或導孔或金屬插塞）282。根據一實施例，第20A-20E圖示出所得的結構。第20A圖繪示裝置200的俯視圖，並且第20B、20C、20D和20E圖分別沿著第20A圖中的B-B線、C-C線、D-D線和E-E線繪示裝置200的部份剖面圖。
在一個實施例中，操作134將一種或多種金屬沉積到通孔278中，對裝置200執行退火製程以引起一種或多種金屬與源極/汲極部件260’之間的反應，以產生矽化物部件280，並去除一種或多種金屬的未反應部份，將矽化物部件280留在通孔中。一種或多種金屬可以包括鈦（Ti）、鉭（Ta）、鎢（W）、鎳（Ni）、鉑（Pt）、鐿（Yb）、銥（Ir）、鉺（Er）、鈷（Co）或其組合（例如，兩種或多種金屬的合金），並且可以使用CVD、PVD、ALD或其他合適的方法進行沉積。矽化物部件280可以包括矽化鈦（TiSi）、矽化鎳（NiSi）、矽化鎢（WSi）、矽化鎳鉑（NiPtSi）、矽化鎳鉑鍺（NiPtGeSi）、矽化鎳鍺（NiGeSi）、矽化鐿（YbSi）、矽化鉑（PtSi）、矽化銥（IrSi）、矽化鉺（ErSi）、矽化鈷（CoSi）或其他合適的化合物。
之後，操作134在通孔（via hole）278中沉積導孔（via）282並接觸矽化物部件280。導孔282可以包括導電阻障層和在導電阻障層上方的金屬填充層。導電阻擋層可以包括鈦（Ti）、鉭（Ta）、鎢（W）、鈷（Co）、釕（Ru）或導電氮化物，例如氮化鈦（TiN）、氮化鈦鋁（TiAlN）、氮化鎢（WN）、氮化鉭（TaN）或其組合，並且可以通過CVD、PVD、ALD及/或其他合適的製程形成。金屬填充層可以包括鎢（W）、鈷（Co）、鉬（Mo）、釕（Ru）、或其他金屬，並且可以通過CVD、PVD、ALD、電鍍或其他合適的製程形成。由於通孔278擴大的輪廓，矽化物部件280和導孔282具有擴大的體積，有益處地降低其接觸電阻。在結構200的背側薄化不使半導體層239在其最寬部份下方凹陷的實施例中，導孔282具有沿著“z”方向變寬（widens）然後變窄（narrows）的輪廓，如第20C圖所示。在這樣的實施例中，導孔282具有大於源極部件260’寬度w1的寬度w5（如以上參考第9C圖所討論）。在結構200的背側薄化使半導體層239在其最寬部份下方凹陷的一些實施例中，導孔282具有大致沿著“z”方向變窄的輪廓（未示出）。即使在這些實施例中，導孔282也可以沿著“y”方向比源極部件260’寬。在各種實施例中，導孔282可以沿著“-z”方向在介電鰭片229正上方橫向延伸。換言之，導孔282可以沿著“z”方向在介電鰭片229正下方橫向延伸。這種輪廓在導孔282中提供大體積。在本實施例中，導孔282在x-z平面中具有接近垂直的輪廓，如第20B圖所示。例如，導孔282的側壁可以與垂直方向在+/-10度內。在一些實施例中，導孔282在x-z平面（未示出）中具有一般梯形的輪廓，其一般沿著“z”方向變窄。
在操作136，方法100（第1C圖）對裝置200進行進一步製造。例如，操作136形成背側電源軌284和背側互連286。根據一實施例，第21A-21B圖示出所得的結構。第21A圖繪示裝置200的俯視圖，並且第21B圖沿著第21A圖中的B-B線繪示裝置200的部份剖面圖。如第21B圖所示，背側導孔282電性連接到背側電源軌284。在一個實施例中，可以使用鑲嵌製程、雙鑲嵌製程、金屬圖案化製程或其他合適的製程形成背側電源軌284。背側電源軌284可以包括鎢（W）、鈷（Co）、鉬（Mo）、釕（Ru）、銅（Cu）、鋁（Al）、鈦（Ti）、鉭（Ta）或其他金屬，並且可以通過CVD、PVD、ALD、電鍍或其他合適的製程沉積。儘管在第21B圖中未示出，但是背側電源軌284嵌入在一個或多個介電層中，且背側互連286包括嵌入在一個或多個介電層中的導線以及導孔。在一些實施例中，背側電源軌284被認為是背側互連286的一部份。具有背側電源軌284有益處地增加裝置200中可用於直接連接到源極/汲極接觸件和導孔的金屬軌的數量。與沒有背側電源軌284的其他結構相比，其也增加了閘極密度，以實現更大的裝置整合度。背側電源軌284的尺寸可以比裝置200的前側上的第一層金屬（M0）軌的尺寸更寬，這有益處地減小背側電源軌的電阻。
在上述實施例中，源極部件260形成有前側和背側矽化物部件以及前側和背側接觸件，而汲極部件260形成有前側矽化物部件和前側接觸件，並且與背側電源軌隔離。在替代實施例中，汲極部件260形成有前側和背側矽化物部件以及前側和背側接觸件，而源極部件260形成有前側矽化物部件和前側接觸件，並且與背側電源軌隔離。其可以通過將上述實施例中用於源極區的製程與用於汲極區的製程進行切換來實現。在另一替代實施例中，源極部件260和汲極部件260都可以形成有前側和背側矽化物部件以及前側和背側接觸件。其可以通過將上述實施例中用於源極區的製程用於源極區和汲極區來實現。
儘管不意旨在限制，但是本揭露的實施例提供以下一個或多個益處。例如，本揭露的實施例形成具有擴大輪廓的背側導孔，其有益處地降低背側上源極/汲極的接觸電阻。本揭露的實施例可以容易地整合到現有的半導體製造製程中。
在一個示例方面，本揭露一些實施例提供一種半導體結構，包括：隔離結構；第一源極/汲極部件（S/D）以及第二源極/汲極部件，在隔離結構上，定義第一方向，在俯視圖中，第一方向從第一源極/汲極部件至第二源極/汲極部件；一個或多個通道層，連接第一源極/汲極部件以及第二源極/汲極部件；閘極結構，在第一源極/汲極部件以及第二源極/汲極部件之間，且齒合（engaging）每個通道層；以及導孔結構，在第一源極/汲極部件下方，且電性連接至第一源極/汲極部件，其中，在垂直於第一方向的剖面圖中，導孔結構具有輪廓，輪廓沿著由下至上（bottom-up）的方向由寬（widens）至窄（narrows）。
在一些實施例中，更包括：源極/汲極接觸件，設置在第一源極/汲極部件上並連接至第一源極/汲極部件。
在一些實施例中，更包括矽化物部件，在第一源極/汲極部件以及導孔結構之間。
在一些實施例中，更包括介電部件，在第二源極/汲極部件正下方並接觸第二源極/汲極部件。
在一些實施例中，更包括源極/汲極接觸件，在第二源極/汲極部件上，且電性連接至第二源極/汲極部件。
在一些實施例中，更包括介電鰭片，鄰近第一源極/汲極部件的側壁。
在一些實施例中，導孔結構在介電鰭片中的至少一個的正下方延伸。
在一些實施例中，通道層包括半導體層的堆疊，且閘極結構包繞（wraps around）堆疊的每個半導體層。
在一些實施例中，在剖面圖中，導孔結構比第一源極/汲極部件寬。
在另一個示例方面，本揭露另一些實施例提供一種形成半導體結構的方法，包括：提供結構，結構具有基板、隔離結構，在基板上、鰭片，從基板延伸且鄰近隔離結構、犧牲閘極結構，設置在鰭片的通道區上、以及閘極間隔物，在犧牲閘極結構的兩側側壁上；對鄰近閘極間隔物的鰭片進行第一蝕刻以形成第一源極/汲極溝槽以及第二源極/汲極溝槽，第一源極/汲極溝槽在犧牲閘極結構的一側上，第二源極/汲極溝槽在犧牲閘極結構的另一側上；形成蝕刻遮罩，蝕刻遮罩露出第一源極/汲極溝槽並覆蓋第二源極/汲極溝槽；透過蝕刻遮罩對鰭片進行第二蝕刻，以深化（deepen）第一源極/汲極溝槽；以及在第二蝕刻之後，橫向蝕刻露出於第一源極/汲極溝槽的下部的隔離結構的部份，得到第一源極/汲極溝槽的擴大的下部。
在另一些實施例中，更包括：在橫向蝕刻之後，至少在第一源極/汲極溝槽的擴大的下部中磊晶成長第一半導體層。
在另一些實施例中，更包括：在第一半導體層上磊晶成長第一半導體源極/汲極部件。
在另一些實施例中，更包括：在第一半導體源極/汲極部件上形成接觸部件。
在另一些實施例中，隔離結構設置在基板的前側上，更包括：從基板與前側相對的背側薄化（thinning down）基板，從而從背側露出第一半導體層以及鰭片。
在另一些實施例中，更包括：從背側蝕刻第一半導體層以露出第一半導體源極/汲極部件，得到導孔；以及在導孔中形成金屬插塞。
在另一些實施例中，更包括：在背側上形成金屬軌（track），金屬軌電性連接至金屬插塞。
在又一個示例方面，本揭露又一些實施例提供一種形成半導體結構的方法，包括：提供結構，結構具有基板、隔離結構，在基板上、鰭片，從基板延伸且鄰近隔離結構、犧牲閘極結構，設置在鰭片的通道區上、以及閘極間隔物，在犧牲閘極結構的兩側側壁上；對鄰近閘極間隔物的鰭片進行第一蝕刻以形成第一源極/汲極溝槽以及第二源極/汲極溝槽，第一源極/汲極溝槽在犧牲閘極結構的一側上，第二源極/汲極溝槽在犧牲閘極結構的另一側上；形成蝕刻遮罩，蝕刻遮罩露出第一源極/汲極溝槽並覆蓋第二源極/汲極溝槽；透過蝕刻遮罩對鰭片進行第二蝕刻，以深化（deepen）第一源極/汲極溝槽；在第二蝕刻之後，橫向蝕刻露出於第一源極/汲極溝槽的下部的隔離結構的部份，得到第一源極/汲極溝槽的擴大的下部；至少在第一源極/汲極溝槽的擴大的下部中成長第一半導體層，其中第一半導體層包括不同於鰭片的材料；以及在第一半導體層上磊晶成長第一半導體源極/汲極部件。
在又一些實施例中，更包括：以高介電常數金屬閘極替換犧牲閘極結構。
在又一些實施例中，更包括：在第一半導體源極/汲極部件上形成源極/汲極接觸件。
在又一些實施例中，隔離結構設置在基板的前側上，更包括：從基板相對於前側的背側薄化基板，從而從背側露出第一半導體層以及鰭片；去除鰭片以形成溝槽；在溝槽中沉積一個或多個介電材料；蝕刻第一半導體層以形成導孔；以及在導孔中形成金屬插塞。
以上概述數個實施例之特徵，以使本發明所屬技術領域中具有通常知識者可以更加理解本發明實施例的觀點。本發明所屬技術領域中具有通常知識者應理解，可輕易地以本發明實施例為基礎，設計或修改其他製程和結構，以達到與在此介紹的實施例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應理解，此類等效的結構並無悖離本發明的精神與範圍，且可在不違背本發明之精神和範圍下，做各式各樣的改變、取代和替換。因此，本發明之保護範圍當視後附之申請專利範圍所界定為準。
100:方法 102:操作 104:操作 106:操作 108:操作 110:操作 112:操作 114:操作 116:操作 118:操作 120:操作 122:操作 124:操作 126:操作 128:操作 130:操作 132:操作 134:操作 136:操作 200:半導體裝置 200:半導體結構 201:基板 204:半導體層 204:區域 205:堆疊 206:硬遮罩層 210:半導體層 215:半導體層 218:鰭片 229:介電鰭片 230:隔離結構 231:包覆層 232:介電襯層 233:介電填充層 234:介電罩 235:虛設閘極介電層 236:硬遮罩 237:光阻 238:開口 239:半導體層 240:閘極堆疊 241:遮罩 245:虛設閘極電極層 246:硬遮罩層 247:閘極間隔物 250:溝槽 253:底部 255:內部間隔物 255:內部間隔層 260:源極/汲極部件 260:源極部件 260:汲極部件 269:接觸蝕刻停止層 270:層間介電層 272:溝槽 273:矽化物部件 274:介電襯層 275:源極/汲極接觸件 276:介電層 277:層 278:溝槽 278:通孔 280:矽化物部件 282:接觸件 282:導孔 284:背側電源軌 286:背側互連 349:閘極介電層 350:閘極電極 370:載體 240’:閘極堆疊 250’:溝槽 260’:源極/汲極部件 260’:源極部件 B-B:線 C-C:線 d1:距離 d2:距離 D-D:線 E-E:線 H1:高度 H2:高度 H6:高度 S1:間距 w1:寬度 w2:寬度 w3:距離 w4:寬度 w5:寬度 w6:寬度
以下將配合所附圖示詳述本揭露之各面向。應注意的是，依據在業界的標準做法，各種特徵並未按照比例繪製且僅用以說明例示。事實上，可能任意地放大或縮小單元的尺寸，以清楚地表現出本揭露的特徵。 第1A、1B以及1C圖係根據本揭露各種方面，在各種實施例中，繪示形成擴大的磊晶源極/汲極部件的方法流程圖，其部件得以通過背側電源軌降低電阻。 第2、3A、3B、4A、4B、4C、5A、5B、5C、5D、6A、6B、6C、6D、7A、7B、7C、7D、8A、8B、8C、8D、9A、9B、9C、9D、10A、10B、10C、10D、11A、11B、11C、11D、12A、12B、12C、12D、13A、13B、13C、14A、14B、14C、14D、15A、15B、15C、15D、15E、16A、16B、16C、16D、16E、17A、17B、17C、17D、17E、18A、18B、18C、18D、18E、19A、19B、19C、19D、19E、20A、20B、20C、20D、20E、21A以及21B圖，根據第1A至1C圖的方法實施例的製造的中間步驟，根據一些實施例，繪示半導體裝置的一部份的俯視圖以及剖面圖。
200:半導體裝置
215:半導體層
260’:源極/汲極部件
274:介電襯層
276:介電層
277:膜層
280:矽化物部件
282:導孔
370:載體

Claims (1)

  1. 一種半導體結構，包括： 一隔離結構； 一第一源極/汲極部件（S/D）以及一第二源極/汲極部件，在該隔離結構上，定義一第一方向，在一俯視圖中，該第一方向從該第一源極/汲極部件至該第二源極/汲極部件； 一個或多個通道層，連接該第一源極/汲極部件以及該第二源極/汲極部件； 一閘極結構，在該第一源極/汲極部件以及該第二源極/汲極部件之間，且齒合（engaging）每個通道層；以及 一導孔結構，在該第一源極/汲極部件下方，且電性連接至該第一源極/汲極部件， 其中，在垂直於該第一方向的一剖面圖中，該導孔結構具有一輪廓，該輪廓沿著一由下至上（bottom-up）的方向由寬（widens）至窄（narrows）。
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11532556B2 (en) * 2019-12-29 2022-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and method for transistors having backside power rails
US11799019B2 (en) * 2020-02-27 2023-10-24 Taiwan Semiconductor Manufacturing Co., Ltd. Gate isolation feature and manufacturing method thereof
US11362213B2 (en) * 2020-03-31 2022-06-14 Taiwan Semiconductor Manufacturing Co., Ltd. Method for manufacturing a FinFET device with a backside power rail and a backside self-aligned via by etching an extended source trench
DE102020129842A1 (de) 2020-03-31 2021-09-30 Taiwan Semiconductor Manufacturing Co., Ltd. Finfet-vorrichtungen mit rückseitiger stromschiene und rückseitiger selbstjustierender durchkontaktierung
US11411100B2 (en) * 2020-09-29 2022-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming backside power rails
US20220139911A1 (en) * 2020-10-30 2022-05-05 Intel Corporation Use of a placeholder for backside contact formation for transistor arrangements

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US8816444B2 (en) 2011-04-29 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. System and methods for converting planar design to FinFET design
US8803316B2 (en) 2011-12-06 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. TSV structures and methods for forming the same
US9236267B2 (en) 2012-02-09 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Cut-mask patterning process for fin-like field effect transistor (FinFET) device
US8785285B2 (en) 2012-03-08 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US8860148B2 (en) 2012-04-11 2014-10-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for FinFET integrated with capacitor
US8803292B2 (en) 2012-04-27 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate vias and methods for forming the same
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
US9105490B2 (en) 2012-09-27 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8823065B2 (en) 2012-11-08 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8772109B2 (en) 2012-10-24 2014-07-08 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for forming semiconductor contacts
US9236300B2 (en) 2012-11-30 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Contact plugs in SRAM cells and the method of forming the same
US8802504B1 (en) 2013-03-14 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
US9711555B2 (en) 2013-09-27 2017-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. Dual facing BSI image sensors with wafer level stacking
US9024368B1 (en) * 2013-11-14 2015-05-05 Globalfoundries Inc. Fin-type transistor structures with extended embedded stress elements and fabrication methods
US9136106B2 (en) 2013-12-19 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for integrated circuit patterning
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9425126B2 (en) 2014-05-29 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structure for chip-on-wafer-on-substrate
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
CN205752158U (zh) 2015-01-09 2016-11-30 硅源公司 集成电路装置
US9520482B1 (en) 2015-11-13 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of cutting metal gate
DE112016007504T5 (de) * 2016-12-07 2019-09-26 Intel Corporation Integriertes Schaltungs-Bauelement mit zinnenartigem Metall-Leiterbahn-Layout

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