CN113540087A - 半导体结构 - Google Patents

半导体结构 Download PDF

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Publication number
CN113540087A
CN113540087A CN202110660780.2A CN202110660780A CN113540087A CN 113540087 A CN113540087 A CN 113540087A CN 202110660780 A CN202110660780 A CN 202110660780A CN 113540087 A CN113540087 A CN 113540087A
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China
Prior art keywords
source
drain
layer
dielectric
semiconductor layer
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CN202110660780.2A
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朱峯庆
李威养
林家彬
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN113540087A publication Critical patent/CN113540087A/zh
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Abstract

一种半导体结构，包括：隔离结构；第一源极/漏极部件(S/D)以及第二源极/漏极部件，在隔离结构上，定义第一方向，在俯视图中，第一方向从第一源极/漏极部件至第二源极/漏极部件；一个或多个通道层，连接第一源极/漏极部件以及第二源极/漏极部件；栅极结构，在第一源极/漏极部件以及第二源极/漏极部件之间，且齿合每个通道层；以及导孔结构，在第一源极/漏极部件下方，且电性连接至第一源极/漏极部件。在垂直于第一方向的剖面图中，导孔结构具有轮廓，轮廓沿着由下至上的方向由宽至窄。

Description

半导体结构
技术领域
本发明实施例涉及一种半导体结构及其形成方法，且特别关于一种具有背侧金属部件的半导体结构及其形成方法。
背景技术
常规上，集成电路(IC)是以堆叠的方式建构，其具有处于最低水平处的晶体管以及在晶体管上的互连结构(导孔和导线)以提供晶体管的连接。电源轨(例如电压源和接地的金属线)也位于晶体管上方，并且可以是互连结构的一部分。随着集成电路的不断微缩化，电源轨也随之缩小。这不可避免地导致跨电源轨的压降增加，以及集成电路的功耗增加。因此，尽管半导体制造中现有的方法通常已经足以满足其预期目的，但是它们并非在所有方面都完全令人满意。
发明内容
本公开一些实施例提供一种半导体结构，包括：隔离结构；第一源极/漏极部件(S/D)以及第二源极/漏极部件，在隔离结构上，定义第一方向，在俯视图中，第一方向从第一源极/漏极部件至第二源极/漏极部件；一个或多个通道层，连接第一源极/漏极部件以及第二源极/漏极部件；栅极结构，在第一源极/漏极部件以及第二源极/漏极部件之间，且齿合(engaging)每个通道层；以及导孔结构，在第一源极/漏极部件下方，且电性连接至第一源极/漏极部件，其中，在垂直于第一方向的剖面图中，导孔结构具有轮廓，轮廓沿着由下至上(bottom-up)的方向由宽(widens)至窄(narrows)。
本公开另一些实施例提供一种形成半导体结构的方法，包括：提供结构，结构具有基板、隔离结构，在基板上、鳍片，从基板延伸且邻近隔离结构、牺牲栅极结构，设置在鳍片的通道区上、以及栅极间隔物，在牺牲栅极结构的两侧侧壁上；对邻近栅极间隔物的鳍片进行第一蚀刻以形成第一源极/漏极沟槽以及第二源极/漏极沟槽，第一源极/漏极沟槽在牺牲栅极结构的一侧上，第二源极/漏极沟槽在牺牲栅极结构的另一侧上；形成蚀刻遮罩，蚀刻遮罩露出第一源极/漏极沟槽并覆盖第二源极/漏极沟槽；透过蚀刻遮罩对鳍片进行第二蚀刻，以深化(deepen)第一源极/漏极沟槽；以及在第二蚀刻之后，横向蚀刻露出于第一源极/漏极沟槽的下部的隔离结构的部分，得到第一源极/漏极沟槽的扩大的下部。
本公开又一些实施例提供一种形成半导体结构的方法，包括：提供结构，结构具有基板、隔离结构，在基板上、鳍片，从基板延伸且邻近隔离结构、牺牲栅极结构，设置在鳍片的通道区上、以及栅极间隔物，在牺牲栅极结构的两侧侧壁上；对邻近栅极间隔物的鳍片进行第一蚀刻以形成第一源极/漏极沟槽以及第二源极/漏极沟槽，第一源极/漏极沟槽在牺牲栅极结构的一侧上，第二源极/漏极沟槽在牺牲栅极结构的另一侧上；形成蚀刻遮罩，蚀刻遮罩露出第一源极/漏极沟槽并覆盖第二源极/漏极沟槽；透过蚀刻遮罩对鳍片进行第二蚀刻，以深化(deepen)第一源极/漏极沟槽；在第二蚀刻之后，横向蚀刻露出于第一源极/漏极沟槽的下部的隔离结构的部分，得到第一源极/漏极沟槽的扩大的下部；至少在第一源极/漏极沟槽的扩大的下部中成长第一半导体层，其中第一半导体层包括不同于鳍片的材料；以及在第一半导体层上外延成长第一半导体源极/漏极部件。
附图说明
以下将配合所附图示详述本公开的各面向。应注意的是，依据在业界的标准做法，各种特征并未按照比例绘制且仅用以说明例示。事实上，可能任意地放大或缩小单元的尺寸，以清楚地表现出本公开的特征。
图1A、图1B以及图1C是根据本公开各种方面，在各种实施例中，绘示形成扩大的外延源极/漏极部件的方法流程图，其部件得以通过背侧电源轨降低电阻。
图2、图3A、图3B、图4A、图4B、图4C、图5A、图5B、图5C、图5D、图6A、图6B、图6C、图6D、图7A、图7B、图7C、图7D、图8A、图8B、图8C、图8D、图9A、图9B、图9C、图9D、图10A、图10B、图10C、图10D、图11A、图11B、图11C、图11D、图12A、图12B、图12C、图12D、图13A、图13B、图13C、图14A、图14B、图14C、图14D、图15A、图15B、图15C、图15D、图15E、图16A、图16B、图16C、图16D、图16E、图17A、图17B、图17C、图17D、图17E、图18A、图18B、图18C、图18D、图18E、图19A、图19B、图19C、图19D、图19E、图20A、图20B、图20C、图20D、图20E、图21A以及图21B，根据图1A至图1C的方法实施例的制造的中间步骤，根据一些实施例，绘示半导体装置的一部分的俯视图以及剖面图。
其中，附图标记说明如下：
100：方法
102：操作
104：操作
106：操作
108：操作
110：操作
112：操作
114：操作
116：操作
118：操作
120：操作
122：操作
124：操作
126：操作
128：操作
130：操作
132：操作
134：操作
136：操作
200：半导体装置
200：半导体结构
201：基板
204：半导体层
204：区域
205：堆叠
206：硬遮罩层
210：半导体层
215：半导体层
218：鳍片
229：介电鳍片
230：隔离结构
231：包覆层
232：介电衬层
233：介电填充层
234：介电罩
235：虚设栅极介电层
236：硬遮罩
237：光阻
238：开口
239：半导体层
240：栅极堆叠
241：遮罩
245：虚设栅极电极层
246：硬遮罩层
247：栅极间隔物
250：沟槽
253：底部
255：内部间隔物
255：内部间隔层
260：源极/漏极部件
260：源极部件
260：漏极部件
269：接触蚀刻停止层
270：层间介电层
272：沟槽
273：硅化物部件
274：介电衬层
275：源极/漏极接触件
276：介电层
277：层
278：沟槽
278：通孔
280：硅化物部件
282：接触件
282：导孔
284：背侧电源轨
286：背侧互连
349：栅极介电层
350：栅极电极
370：载体
240’：栅极堆叠
250’：沟槽
260’：源极/漏极部件
260’：源极部件
B-B：线
C-C：线
d1：距离
d2：距离
D-D：线
E-E：线
H1：高度
H2：高度
H6：高度
S1：间距
w1：宽度
w2：宽度
w3：距离
w4：宽度
w5：宽度
w6：宽度
具体实施方式
以下内容提供了许多不同实施例或范例，以实现本公开实施例的不同部件。以下描述组件和配置方式的具体范例，以简化本公开实施例。当然，这些仅仅是范例，而非意图限制本公开实施例。举例而言，在以下描述中提及于第二部件上方或其上形成第一部件，其可以包含第一部件和第二部件以直接接触的方式形成的实施例，并且也可以包含在第一部件和第二部件之间形成额外的部件，使得第一部件和第二部件可以不直接接触的实施例。此外，本公开实施例可在各个范例中重复参考标号及/或字母。此重复是为了简化和清楚的目的，其本身并非用于指定所讨论的各个实施例及/或配置之间的关系。
再者，其中可能用到与空间相对用词，例如「在……之下」、「下方」、「较低的」、「上方」、「较高的」等相似用词，是为了便于描述图式中一个(些)部件或特征与另一个(些)部件或特征之间的关系。空间相对用词用以包括使用中或操作中的装置的不同方位，以及图式中所描述的方位。当装置被转向不同方位时(旋转90度或其他方位)，其中所使用的空间相对形容词也将依转向后的方位来解释。此外，此处所使用的用语「约」、「近似」等类似用语描述数字或数字范围时，该用语意欲涵盖的数值是在合理范围内包含所描述的数字，例如在所描述的数字之+/-10％之内，或本发明所属技术领域中具有通常知识者理解的其他数值。例如，用语「约5纳米」涵盖从4.5纳米至5.5纳米、4.0纳米至5.0纳米等的尺寸范围。
本公开整体关于半导体结构和制造制程，更详细而言，关于具有背侧电源轨和背侧自对准导孔的半导体装置。如上所述，IC中的电源轨需要进一步改进，以提供所需的性能提升并降低功耗。本公开的目的包括在包含晶体管(例如，全绕式栅极(gate-all-around,GAA)晶体管及/或FinFET晶体管)的结构的背侧提供电源轨(或电源布线)，此外在结构的前侧提供互连结构(也可以包括电源轨)。这增加结构中可用于直接连接到源极/漏极接触件和导孔的金属轨的数量。与没有背侧电源轨的现有结构相比，还增加栅极密度以实现更大的装置整合度。背侧电源轨的尺寸可以比结构前侧的第一层金属(M0)轨的尺寸更宽，这有利地降低电源轨的电阻。本公开还提供用于降低背侧电源轨以及源极/漏极(S/D)部件(其在装置的前侧)之间的电阻的结构以及方法。源极/漏极部件的尺寸以及源极/漏极部件与背侧导孔之间的接触面积通常受到主动区的宽度限制，例如半导体鳍片的宽度。本公开的实施例使用额外的横向蚀刻制程以突破(break through)围绕半导体鳍片的介电层，从而扩大源极/漏极沟槽的底部。其提供与背侧导孔的界面较大的面积，从而有益处地降低源极/漏极部件以及背侧电源轨之间的接触电阻。
以下结合附图描述本公开的结构和制造方法的细节，附图根据一些实施例示出制造GAA装置的制程。GAA装置是指具有垂直堆叠的水平取向的多通道晶体管的装置，例如纳米线晶体管和纳米片晶体管。GAA装置具有更好的栅极控制能力、更低的漏电流以及完整的FinFET装置布局兼容性，因此有望将CMOS推向发展路程图(roadmap)的下一个阶段。为了简单起见，本公开使用GAA装置作为示例。本领域技术人员应该理解，他们可以容易地将本公开用作设计或修改其他制程和结构(例如FinFET装置)的基础，为了实现本公开介绍的实施例的相同目的及/或实现相同的优点。
图1A、图1B以及图1C是根据本公开的各种方面，用于制造半导体装置的方法100的流程图。本公开考虑额外的制程。可以在方法100之前、之中以及之后提供其他操作，并且对于方法100的额外实施例，可以移动、替换或消除所描述的一些操作。
根据一些实施例，以下结合图2至图21B描述方法100，示出根据方法100的各种制造步骤的半导体装置(或半导体结构)200的各种俯视图和剖面图。在一些实施例中，装置200是IC芯片、芯片上系统(system on chip,SoC)或其部分的一部分，其包括各种被动和主动微电子装置，例如电阻、电容、电感、二极管、p型场效晶体管(p-type field effecttransistors,PFETs)、n型场效晶体管(n-type field effect transistors,NFETs)、鳍式场效晶体管(FinFET)、纳米片FET、纳米线FET、其他类型的多栅极FET、金属氧化物半导体场效晶体管(metal-oxide semiconductor field effect transistors,MOSFETs)、互补式金属氧化物半导体(complementary metal-oxide semiconductor,CMOS)晶体管、双极接面晶体管(bipolar junction transistors,BJTs)、横向扩散金属氧化物半导体(laterallydiffused MOS,LDMOS)晶体管、高压晶体管、高频晶体管、存储器装置、其他合适的组件、或其组合。为了清楚起见，已经简化图2至图21B以更好地理解本公开的发明构思。可以在装置200中增加额外的部件，并且在装置200的其他实施例中可以替换、修改或消除以下描述的一些部件。
在操作102，方法100(图1A)提供半导体结构，半导体结构具有基板201以及建构在基板201之中或之上的各种元件，包括半导体鳍片218、隔离结构230、介电(隔离)鳍片229、牺牲(或虚设)栅极堆叠240、栅极间隔物247以及各种其他元件，例如图2至图4C中所示。以下参照图2至图4C进一步讨论这些元件及其制造方法。
参考图2，在基板201之上的半导体层204之上形成半导体层210和215的堆叠205。在一实施例中，基板201是块体硅基板(即，包括块体单晶硅)。在各种实施例中，基板201可以包括其他半导体材料，例如锗(Ge)、碳化硅(silicon carbide)、砷化镓(GaAs)、磷化镓(GaP)、磷化铟(InP)、砷化铟(InAs)、锑化铟(InSb)，硅锗(SiGe)、磷砷化镓(GaAsP)、砷化铝铟(AlInAs)、砷化铝镓(AlGaAs)、砷化镓铟(GaInAs)、磷化镓铟(GaInP)、磷砷化镓铟(GaInAsP)或其组合。在替代实施例中，基板201是绝缘体上半导体基板、例如绝缘体上硅(silicon-on-insulator,SOI)基板、绝缘体上硅锗(silicon germanium-on-insulator,SGOI)基板或绝缘体上锗(germanium-on-insulator,GOI)基板。在一些实施例中，半导体层204可以是硅、硅锗、锗或其他合适的半导体，并且可以掺杂n型或p型掺质。
半导体层堆叠205包括以交错(interleaving)或交替(alternating)配置垂直地(例如，沿着z方向)堆叠的半导体层210以及半导体层215。在一些实施例中，半导体层210和半导体层215以所描绘的交错和交替配置外延成长。半导体层210和半导体层215的外延成长可以通过分子束外延(molecular beam epitaxy,MBE)制程、化学气相沉积(chemicalvapor deposition,CVD)制程、金属有机化学气相沉积(metalorganic chemical vapordeposition,MOCVD)制程、其他合适的外延成长制程或其组合实现。半导体层210的组成不同于半导体层215的组成以在后续制程期间实现蚀刻选择性及/或不同的氧化速率。例如，半导体层210和半导体层215可以包括不同的材料、组成原子百分比、组成重量百分比、厚度及/或特性以实现期望的蚀刻选择性及/或不同的氧化速率。例如，在一个实施例中，半导体层210可以包括硅锗并且半导体层215可以包括硅。在一些实施例中，半导体层210和半导体层215可以包括相同的材料但具有不同的组成原子百分比以实现蚀刻选择性及/或不同的氧化速率。例如，半导体层210和215都可以包括硅锗，其中半导体层210具有第一硅原子百分比及/或第一锗原子百分比，并且半导体层215具有不同的第二硅原子百分比及/或第二不同的锗原子百分比。本公开也考虑(contemplates)半导体层210和半导体层215包括可以提供期望的蚀刻选择性、期望的氧化速率差异及/或期望的性能特性(例如，最大化电流的材料)的半导体材料的任何组合，包括本公开的任何半导体材料。
如以下进一步描述，半导体层215或其部分形成装置200的通道区。在所描绘的实施例中，半导体层堆叠205包括三个半导体层210和三个半导体层215。经过后续制程后，这样的配置将得到具有三个通道的装置200。然而，本公开也考虑其中半导体层堆叠205包括更多或更少半导体层的实施例，例如，取决于装置200所需的通道数量。例如，半导体层堆叠205可以包括二到十个半导体层210和二到十个半导体层215。在装置200是FinFET装置的替代实施例中，堆叠205只是一层半导体材料，例如一层硅。如以下将讨论，方法100将对基板201两侧的膜层进行制程。在本公开中，将堆叠205所在的基板201的一侧称为前侧，而与前侧相对的一侧称为背侧。
图3A绘示具有沿着“x”方向定向的鳍片218的装置200的俯视图，并且图3B绘示沿着图3A中的B-B线的装置200的部分剖面图。如图3B所示，鳍片218包括图案化的堆叠205(具有膜层210和215)、图案化的区域204和一个或多个图案化的硬遮罩层206。鳍片218可以通过任何合适的方法图案化。例如，可以使用一种或多种微影制程来图案化鳍片218，包括双重图案化制程或多重图案化制程。一般来说，双重图案化或多重图案化制程结合了微影制程与自对准制程，以创建出例如比使用单一、直接微影制程所得的节距(pitch)更小的图案。例如，在一实施例中，在堆叠205上方形成牺牲层，并使用微影制程对其进行图案化。使用自对准制程在图案化的牺牲层旁边形成间隔物。之后去除牺牲层，然后可以使用剩余的间隔物或心轴作为遮罩以图案化鳍片218。例如，遮罩元件可以用于将凹口蚀刻到堆叠205以及基板201之中，从而将鳍片218保留在基板201上。蚀刻制程可以包括干式蚀刻、湿式蚀刻、反应离子蚀刻(reactive ion etching,RIE)及/或其他合适的制程。例如，干式蚀刻制程可以实施含氧气体、含氟气体(例如，CF4、SF6、CH2F2、CHF3及/或C2F6)、含氯气体(例如，Cl2、CHCl3、CCl4及/或BCl3)、含溴气体(例如，HBr及/或CHBr3)、含碘气体、其他合适的气体及/或等离子体、及/或其组合。例如，湿式刻蚀制程可以包括在稀释氢氟酸(dilutedhydrofluoric acid,DHF)；氢氧化钾(KOH)溶液；氨；含有氢氟酸(HF)、硝酸(HNO3)及/或乙酸(CH3COOH)的溶液；或其他合适的湿式蚀刻剂中进行蚀刻。许多其他实施例以形成鳍片218的方法可以是合适的。
图4A绘示装置200的俯视图，并且图4B和图4C分别绘示装置200沿着图4A的B-B线和C-C线的部分剖面图。参考图4A、图4B以及图4C，在鳍片218周围及/或上方建购各种元件，包括隔离鳍片218底部的隔离结构(或部件)230、隔离结构230上方以及鳍片218的侧壁上方的包覆(cladding)层231、隔离结构230上方以及包覆层231的侧壁上的介电(或虚设)鳍片229、鳍片218上方的牺牲栅极堆叠240、以及牺牲栅极堆叠240侧壁上的栅极间隔物247。
参考图4C，隔离部件230形成在基板201上方以隔离装置200的各种区域。例如，隔离部件230围绕鳍片218的底部以将鳍片218彼此分开和隔离。隔离部件230可以包括氧化硅、氮化硅、氮氧化硅、其他合适的隔离材料(例如，包括硅、氧、氮、碳或其他合适的隔离成分)或其组合。隔离部件230可以包括不同的结构，例如浅沟槽隔离(shallow trenchisolation,STI)结构及/或深沟槽隔离(deep trench isolation,DTI)结构。在一个实施例中，可以通过用绝缘体材料填充鳍片218之间的沟槽(例如，通过使用CVD制程或旋涂玻璃制程)，执行化学机械研磨(chemical mechanical polishing,CMP)制程以去除多余的绝缘体材料及/或平坦化绝缘体材料层的顶表面，并回蚀绝缘体材料层以形成隔离部件230。在一些实施例中，隔离部件230包括多层结构，例如设置在热氧化物衬层上方的氮化硅层。
包覆层231沉积在鳍片218的侧壁表面上方和隔离部件230上方。在一个实施例中，包覆层231包括SiGe。可以使用CVD、物理气相沉积(physical vapor deposition,PVD)、原子层沉积(atomic layer deposition,ALD)、高密度等离子体CVD(high density plasmaCVD,HDPCVD)、金属有机CVD(metal organic CVD,MOCVD)、远程等离子体CVD(remoteplasma CVD,RPCVD)、等离子体辅助CVD(plasma enhanced CVD,PECVD)、低压CVD(low-pressure CVD,LPCVD)、原子层CVD(atomic layer CVD,ALCVD)、大气压CVD(atmosphericpressure CVD,APCVD)、其他合适的方法或其组合沉积包覆层231。
在本实施例中，介电鳍片229包括介电衬层232、介电填充层233和介电罩(helmet)234。在替代实施例中，介电鳍片229可以具有不同的配置。介电衬层232沉积在包覆层231的侧壁上方和隔离部件230的顶表面上，并且介电填充层233沉积在介电衬层232上并填充鳍片218之间的间隙。在一个实施例中，介电衬层232包括低介电常数介电材料，例如包括Si、O、N和C的介电材料。示例的低介电常数介电材料包括掺氟硅酸盐玻璃(fluoride-dopedsilicate glass,FSG)、掺碳氧化硅、Black
Figure BDA0003115184610000111
(应用材料，加州圣塔克拉拉)、干凝胶(Xerogel)、气凝胶(Aerogel)、非晶质氟化碳(amorphous fluorinated carbon)、聚对二甲苯(Parylene)、苯并环丁烯(benzocyclobutene,BCB)、
Figure BDA0003115184610000112
(陶氏化学，密西根米特兰)、聚酰亚胺或其组合。低介电常数介电材料通常是指具有低介电常数的介电材料，例如，介电常数小于氧化硅的介电常数(介电常数约为3.9)。可以使用CVD、PVD、ALD、HDPCVD、MOCVD、RPCVD、PECVD、LPCVD、ALCVD、APCVD、其他合适的方法或其组合沉积介电衬层232。在一实施例中，介电填充层233包括氧化硅、氮化硅、氮氧化硅、四乙基原硅酸盐(tetraethylorthosilicate,TEOS)氧化物、磷硅酸盐玻璃(phosphosilicate glass,PSG)、硼磷硅酸盐玻璃(borophosphosilicate glass,BPSG)、低介电常数介电材料、其他合适的介电材料或其组合。介电填充层233可以使用流动式CVD(flowable CVD,FCVD)制程沉积，其包括，例如，在装置200上沉积可流动材料(例如液体化合物)并通过合适的技术(例如热退火及/或紫外线辐射处理)将可流动材料转化为固体材料。介电填充层233可以使用其他类型的方法沉积。
介电罩234沉积在介电层232和233上方以及鳍片218两侧侧壁上的包覆层231之间。在一个实施例中，介电罩234包括高介电常数介电材料，例如HfO2、HfSiO、HfSiO4、HfSiON、HfLaO、HfTaO、HfTiO、HfZrO、HfAlOx、ZrO、ZrO2、ZrSiO2、AlO、AlSiO、Al2O3、TiO、TiO2、LaO、LaSiO、Ta2O3、Ta2O5、Y2O3、SrTiO3、BaZrO、BaTiO3(BTO)、(Ba、Sr)TiO3(BST)、Si3N4、二氧化铪-氧化铝(HfO2-Al2O3)合金、其他合适的高介电常数介电材料或其组合。高介电常数介电材料通常是指具有高介电常数的介电材料，例如，介电常数大于氧化硅的介电常数(介电常数约为3.9)。介电罩234可以由本公开所述的任何制程形成，例如ALD、CVD、PVD、基于氧化的沉积制程、其他合适的制程或其组合。在一个实施例中，可以使用选择性蚀刻制程凹蚀介电层232和233，其制程蚀刻介电层232和233而没有(或最少地)蚀刻硬遮罩206(图3B)和包覆层231。然后，在凹口中沉积一种或多种介电材料，并对一种或多种介电材料进行CMP制程以形成介电罩234。随后，去除硬遮罩层206，并在鳍片218上方形成牺牲栅极堆叠240。
参考图4B，牺牲栅极堆叠240包括虚设栅极介电层235、虚设栅极电极层245和一层或多层硬遮罩层246。在本实施例中，牺牲栅极堆叠240将在后续的制造步骤中被功能性栅极堆叠240’替换。在一些实施例中，虚设栅极介电质235包括介电材料，例如氧化硅、高介电常数介电材料、其他合适的介电材料或其组合；虚设栅极电极层245包括多晶硅或其他合适的材料；以及一个或多个硬遮罩层246包括氧化硅、氮化硅或其他合适的材料。牺牲栅极堆叠240可以通过沉积制程、微影制程、蚀刻制程、其他合适的制程或其组合形成。例如，层235、245和246可以使用CVD、PVD、ALD或其他合适的方法沉积。之后，执行微影图案化和蚀刻制程以图案化层235、245和246以形成牺牲栅极堆叠240，如图4B所示。微影图案化制程包括光阻涂布(例如旋涂)、软烘烤、遮罩对准、曝光、曝光后烘烤、光阻显影、冲洗、干燥(例如，硬烘烤)、其他合适的微影制程或其组合。蚀刻制程包括干式蚀刻制程、湿式蚀刻制程、其他蚀刻方法或其组合。
继续参考图4B，栅极间隔物247设置在牺牲栅极堆叠240的侧壁上。栅极间隔物247可以通过任何合适的制程形成并且包括介电材料。介电材料可以包括硅、氧、碳、氮、其他合适材料或其组合(例如氧化硅、氮化硅、氮氧化硅(SiON)、碳化硅、碳氮化硅(SiCN)、碳氧化硅(SiOC)、碳氮氧化硅(SiOCN))。例如，包括硅和氮的介电层，例如氮化硅层，可以沉积在牺牲栅极堆叠240上，并且随后被蚀刻(例如，非等向性蚀刻)以形成栅极间隔物247。在一些实施例中，栅极间隔物247包括多层结构，例如包括氮化硅的第一介电层和包括氧化硅的第二介电层。在一些实施例中，与牺牲栅极堆叠240相邻地形成多于一组的间隔物，例如密封(seal)间隔物、偏置间隔物(offset spacers)、牺牲间隔物、虚设间隔物及/或主要间隔物。
在操作104，方法100(图1A)通过蚀刻与栅极间隔物247相邻的鳍片218以形成源极/漏极(S/D)沟槽250。根据一些实施例，在图5A-图5D中示出所得结构。图5A绘示装置200的俯视图，并且图5B、图5C和图5D分别沿着图5A中的B-B线、C-C线和D-D线绘示装置200的部分剖面图。详细而言，C-C线切进晶体管的源极区并平行于栅极堆叠240，而D-D线切进晶体管的漏极区并平行于栅极堆叠240。图6A至图12A、图14A至图20A中的C-C线和D-D线的配置相似。
在所描绘的实施例中，蚀刻制程完全去除鳍片218的源极/漏极区中的半导体层堆叠205，从而露出源极/漏极区中的鳍片218的半导体层204。源极/漏极沟槽250因此具有由半导体层堆叠205的剩余部分定义的侧壁，以及由半导体层204和隔离结构230定义的底部，所述剩余部分设置在栅极堆叠240下方的通道区中。在一些实施例中，蚀刻制程去除一些但不是全部的半导体层堆叠205，使得源极/漏极沟槽250具有由源极/漏极区中的半导体层210或半导体层215定义的底部。在一些实施例中，蚀刻制程进一步去除鳍片218的半导体层204的一些但并非全部，使得源极/漏极沟槽250延伸到隔离结构230的最顶表面下方。蚀刻制程可包括干式蚀刻制程、湿式蚀刻制程、其他合适的蚀刻制程或其组合。在一些实施例中，蚀刻制程是多步骤蚀刻制程。例如，蚀刻制程可以交替蚀刻剂以单独和交替地去除半导体层210和半导体层215。在一些实施例中，蚀刻制程的参数被配置为选择性地蚀刻半导体层堆叠，而最少地(至没有)蚀刻栅极堆叠240及/或隔离部件230。在一些实施例中，执行例如本公开描述的微影制程以形成覆盖栅极堆叠240及/或隔离部件230的图案化的遮罩层，并且蚀刻制程使用图案化的遮罩层作为蚀刻遮罩。
在操作106，方法100(图1A)形成内部间隔物255。在图6A-图6D中示出所得结构。图6A绘示装置200的俯视图，并且图6B、图6C和图6D分别沿着图6A中的B-B线、C-C线和D-D线绘示装置200的部分剖面图。在一个实施例中，执行第一蚀刻制程，其制程选择性地蚀刻由源极/漏极沟槽250露出的半导体层210，并且最少地(至没有)蚀刻半导体层215，从而在半导体层215之间以及在栅极间隔物247下方的半导体层215和204之间形成间隙。半导体层215的部分(边缘)因此悬置(suspended)在栅极间隔物247下方的通道区中。第一蚀刻制程可以是干式蚀刻制程、湿式蚀刻制程、其他合适的蚀刻制程或其组合。然后进行沉积制程以形成间隔物层，间隔物层部分地(并且在一些实施例中，完全地)填充源极/漏极沟槽250。沉积制程被配置为确保间隔物层填充半导体层215之间以及栅极间隔物247下方的半导体层215和204之间的间隙。之后进行第二蚀刻制程，选择性地蚀刻间隔物层以形成如图6B所示的内部间隔物255，同时最少地(至没有)蚀刻半导体层215、虚设栅极堆叠240和栅极间隔物247。内部间隔物255包括与半导体层215的材料和栅极间隔物247的材料不同的材料，以在第二蚀刻制程期间实现期望的蚀刻选择性。间隔物层255可以包括介电材料，其介电材料包括硅、氧、碳、氮、其他合适的材料或其组合(例如，氧化硅、氮化硅、氮氧化硅、碳化硅或氮碳氧化硅)。在一些实施例中，内部间隔物层255包括低介电常数介电材料，例如本公开所述的低介电常数介电材料。
在操作108，方法100(图1A)形成蚀刻遮罩241，其覆盖一些源极/漏极沟槽250中，并且留下通过蚀刻遮罩241中的开口238露出的其他源极/漏极沟槽250。通过蚀刻遮罩241露出的源极/漏极沟槽250将经历额外的制程以提供具有扩大底部的源极/漏极部件，以降低与背侧电源轨的接触电阻。图7A绘示装置200的俯视图，并且图7B、图7C和图7D分别沿着图7A中的B-B线、C-C线和D-D线绘示装置200的部分剖面图。在本实施例中，晶体管的源极区通过蚀刻遮罩241(图6C)露出，晶体管的漏极区被蚀刻遮罩241(图6D)覆盖。在替代实施例中，晶体管的源极区被蚀刻遮罩241覆盖，并且晶体管的漏极区通过蚀刻遮罩241露出。在一些实施例中，同一晶体管的源极区和漏极区都可以通过蚀刻遮罩241露出。为了讨论方便，通过蚀刻遮罩241露出的源极/漏极沟槽250被称为源极/漏极沟槽250’。在本实施例中，蚀刻遮罩241包括图案化的硬遮罩236和图案化的光阻237。在一些实施例中，蚀刻遮罩241可以额外包括位于图案化的硬遮罩236和图案化的光阻237之间的底部抗反射涂层(bottomanti-reflective coating,BARC)层。可以通过光阻涂布(例如旋涂)、软烘烤、遮罩对准、曝光、曝光后烘烤、光阻显影、冲洗、干燥(例如，硬烘烤)、其他合适的微影制程或其组合形成图案化的光阻237。
在操作110，方法100(图1A)蚀刻源极/漏极沟槽250’以将其延伸得更深。在图8A-图8D中示出所得结构。图8A绘示装置200的俯视图，并且图8B、图8C和图8D分别沿着图8A中的B-B线、C-C线和D-D线绘示装置200的部分剖面图。蚀刻制程可包括干式蚀刻、湿式蚀刻、反应离子蚀刻或其他合适的蚀刻。在此实施例中，蚀刻制程大抵是非等向性蚀刻(即，大抵垂直)。此外，调整蚀刻制程以选择性地蚀刻半导体层204的材料，并且不(或最少地)蚀刻蚀刻遮罩241、栅极间隔物247、虚设介电鳍片229、栅极硬遮罩层246、内部间隔物255和隔离结构230。在一些实施例中，源极/漏极沟槽250’被延伸使得其底表面在隔离结构230的顶表面之下距离d1。在一些实施例中，距离dl可以在大约30纳米至大约60纳米的范围内，例如大约40纳米至大约50纳米，取决于半导体层204的厚度。将源极/漏极沟槽250’蚀刻得更深允许源极/漏极部件扩大的底部更靠近背侧电源轨。然而，如果源极/漏极沟槽250’太深，则隔离结构230的横向蚀刻(参见以下的操作112)在一些情况下可能变得困难。例如，使蚀刻剂进入深沟槽并仍然控制蚀刻轮廓可能变得困难。因此，沟槽250’的深度被控制在上述范围内(例如使其底表面低于隔离结构230的顶表面约30纳米至约60纳米)。
在操作112，方法100(图1A)对源极/漏极沟槽250’执行另一蚀刻以特别扩大其被隔离结构230围绕的底部。在图9A-图9D中示出所得结构。图9A绘示装置200的俯视图，并且图9B、图9C和图9D分别沿着图9A中的B-B线、C-C线和D-D线绘示装置200的部分剖面图。源极/漏极沟槽250’的底部253被扩大以具有沿着“z”方向变宽然后变窄的轮廓。在操作112之前，源极/漏极沟槽250’的底部具有接近垂直的轮廓(参考图8C)或沿着“z”方向随着上升而变得更窄的大抵梯形(trapezoidal)的轮廓(在任何一种情况下，其侧壁都是直线性的(linear))。蚀刻制程对隔离结构230的材料具有选择性，并且不(或最少地)蚀刻栅极间隔物247、虚设介电鳍片229、栅极硬遮罩层246、内部间隔物255、通道层215、以及半导体层204。在各种实施例中，蚀刻制程可以包括干式蚀刻、湿式蚀刻、反应离子蚀刻或其他合适的蚀刻。详细而言，蚀刻制程包括横向蚀刻隔离结构230的等向性蚀刻成分。在一个实施例中，蚀刻制程使用干式(等离子体)蚀刻，其中等离子体由NF3和NH3气体或具有氟、氮和氢成分的相似气体产生。操作112可调整各种蚀刻参数以控制底部253的轮廓(例如垂直延伸(extension)和横向扩张(expansion)的量)。例如，其可以调整NH3气体流量、NH3气体流量与NF3气体流量的比例、蚀刻时间、蚀刻压力等。在源极/漏极沟槽250’期望的横向扩张w3在10纳米至20纳米的实施例中，NH3气体流速可以调整在约150sccm至约220sccm的范围，NH3气流与NF3气流的比例可以调整在10至20的范围，蚀刻时间可以调整在约20秒至约40秒的范围。在一个实施例中，源极/漏极沟槽250’沿着“y”方向横向(或侧向)扩张距离w3进入隔离结构230之中，如在隔离结构230内的源极/漏极沟槽250’的最宽部分处测量。在一些实施例中，距离w3在约5纳米至约25纳米的范围，例如在约10纳米至约20纳米的范围。如果距离w3太小(例如小于5纳米)，在一些情况下，扩大源极/漏极部件的效果可能不够显著。如果距离w3太大(例如超过30纳米)，则存在完全突破隔离结构230并使相邻的源极/漏极部件短路的风险。此外，操作112可以沿着“z”方向更深地延伸源极/漏极沟槽250’。在操作112完成之后，源极/漏极沟槽250’在隔离结构230的顶表面下方延伸距离d2。在各种实施例中，d2大于d1。例如，d2可以比d1大约10纳米至约40纳米，例如约20纳米至约30纳米。在一些实施例中，源极/漏极沟槽250’正下方的半导体层204的宽度沿着“y”方向具有宽度w4。在一些实施例中，宽度w4可以在大约30纳米到大约40纳米的范围。在那些实施例中，源极/漏极沟槽250’的底部253具有大约(w4+2×w3)的总宽度w5，其在40至90纳米的范围。上述范围的重要性相似于以上关于宽度w3所讨论。在一些实施例中，源极/漏极沟槽250’的底部253在介电鳍片229之一或两者正下方延伸以获得额外的宽度。易言之，宽度w5大于介电鳍片229之间的间距S1。在那些实施例中，导孔结构(例如图20C中的导孔282)具有更大的宽度和更大的体积，以进一步降低电阻。
在操作114，方法100(图1B)在去除图案化的光阻237(例如通过剥离、灰化或其他方法)之后在源极/漏极沟槽250’中形成半导体层239。根据一实施例，在图10A-图10D中示出所得结构。图10A绘示装置200的俯视图，并且图10B、图10C和图10D分别沿着图10A中的B-B线、C-C线和D-D线绘示装置200的部分剖面图。可以使用外延成长制程或通过其他合适的制程沉积半导体层239。在一些实施例中，半导体层239的外延成长通过分子束外延(MBE)制程、化学气相沉积(CVD)制程、金属有机化学气相沉积(MOCVD)制程、其他合适的外延成长制程或其组合实现。半导体层239包括与包括在半导体层204中的半导体材料不同的半导体材料以在后续制程期间实现蚀刻选择性。例如，半导体层239和204可以包括不同的材料、不同的组成原子百分比、不同的组成重量百分比及/或其他特性以在蚀刻制程期间实现期望的蚀刻选择性。在一个实施例中，半导体层204包括硅并且半导体层239包括硅锗。在另一个实施例中，半导体层239和204都可以包括硅锗，但是具有不同的硅原子百分比。本公开也考虑半导体层239和204包括可以提供期望蚀刻选择性的半导体材料的任何组合，包括本公开的任何半导体材料。由于漏极区(图10D)被图案化的硬遮罩层236覆盖，半导体层239仅沉积在源极区(图10C)中。半导体层239沉积的厚度使其靠近堆叠205(图10B)的底部并且与隔离部件230(图10C)的顶表面大致齐平。如果半导体层239最初成长得比图10B和图10C所示的水平高，则操作114可以包括蚀刻制程，其蚀刻制程使半导体层239凹陷到图10B和图10C所示的水平。在沉积半导体层239之后，操作114通过一个或多个蚀刻制程去除图案化的硬遮罩层236。如以下将讨论，在各种实施例中，操作110和112中的额外蚀刻和操作114中的半导体层239的成长可以仅在源极区中进行、仅在漏极区中进行或在源极区和漏极区两者中进行。
在操作116，方法100(图1B)在源极/漏极沟槽250中外延成长半导体源极/漏极部件260并且在源极/漏极沟槽250’中外延成长半导体源极/漏极部件260’。根据一实施例，在图11A-图11D中示出所得结构。图11A绘示装置200的俯视图，并且图11B、图11C和图11D分别沿着图11A中的B-B线、C-C线和D-D线绘示装置200的部分剖面图。
如图11B、图11C和图11D所示，外延源极/漏极部件260从半导体层204和从在源极/漏极沟槽250处的半导体层215成长，外延源极/漏极部件260’从半导体层239和从在源极/漏极沟槽250’处的半导体层215成长。外延制成可以使用化学气相沉积(CVD)技术(例如，气相外延(vapor phase epitaxy,VPE)及/或超高真空CVD(ultra-high vacuum CVD,UHV-CVD))、分子束外延、其他合适的外延成长制程或其组合。外延制程可以使用气态及/或液态前驱物，其与半导体层204、239和215的成分相互作用。外延源极/漏极部件260/260’可以对于n型晶体管或p型晶体管分别掺杂有n型掺质或p型掺质。在一些实施例中，对于n型晶体管，外延源极/漏极部件260/260’包括硅并且可以掺杂有碳、磷、砷、其他n型掺质或其组合(例如，形成Si：C外延源极/漏极部件、Si：P外延源极/漏极部件或Si：C：P外延源极/漏极部件)。在一些实施例中，对于p型晶体管，外延源极/漏极部件260/260’包括硅锗或锗，并且可以掺杂有硼、其他p型掺质或其组合(例如，形成Si：Ge：B外延源极/漏极部件)。在一些实施例中，外延源极/漏极部件260/260’包括多于一个外延半导体层，其中外延半导体层可以包括相同或不同的材料及/或掺质浓度。此外，在一个实施例中，源极/漏极部件260’(或至少其邻接半导体层239的部分)包括与半导体层239不同的材料组成以在背侧导孔形成制程期间实现蚀刻选择性。例如，在一个实施例中，半导体层239包括SiGe并且源极/漏极部件260’包括Si(对于n型晶体管)。例如，在另一个实施例中，半导体层239包括具有第一Ge原子百分比的SiGe，并且源极/漏极部件260’包括具有第二Ge原子百分比的SiGe(对于p型晶体管)，并且第一和第二Ge原子百分比不同。在一些实施例中，外延源极/漏极部件260/260’包括在相应的通道区中实现所需拉伸应力(tensile stress)及/或压缩应力(compressivestress)的材料及/或掺质。在一些实施例中，外延源极/漏极部件260/260’在沉积期间通过对外延制程的源材料添加杂质掺杂(即，原位(in situ)掺杂)。在一些实施例中，外延源极/漏极部件260/260’在沉积制程之后通过离子布植制程掺杂。在一些实施例中，执行退火制程(例如，快速热退火(rapid thermal annealing,RTA)及/或激光退火)以活化外延源极/漏极部件260/260’中的掺质。在一些实施例中，外延源极/漏极部件260/260’在单独的制程顺序中形成，包括，例如在n型GAA晶体管区中形成外延源极/漏极部件260/260’时遮蔽p型GAA晶体管区，并且在p型GAA晶体管区中形成外延源极/漏极部件260/260’时遮蔽n型GAA晶体管区。
此外，如图11C和图11D所示，源极/漏极部件260/260’在介电鳍片229之间的空间中扩张。上述扩张可能是由不同晶面(crystal facets)的不同成长速率所致。参考图11C，源极/漏极部件260’具有沿着“z”方向的高度H1和沿着“y”方向的宽度w1(在源极/漏极部件260’的最宽部分处测量)。在一些实施例中，H1可以在大约40纳米至大约70纳米的范围，并且w1可以在大约30纳米至大约60纳米的范围。在一些实施例中，w1与H1的比例可在约0.4至1.5的范。参考图11D，源极/漏极部件260具有沿着“z”方向的高度H6和沿着“y”方向的宽度w6(在源极/漏极部件260的最宽部分处测量)。在一些实施例中，H6可以在大约40纳米至大约70纳米的范围，并且w6可以在大约30纳米至大约60纳米的范围。在一些实施例中，w6与H6的比例可在约0.4至1.5的范围。在各种实施例中，源极/漏极部件260和260’的尺寸可以大致相同或不同。在一些情况下，源极/漏极部件260和260’为前侧源极/漏极接触件提供落置区(landing areas)。因此，它们成长到足够大的体积以提供足够的落置面积。如果宽度w1和w6及/或高度H1和H6太小(例如小于上述范围的下限)，则源极/漏极部件260/260’的体积可能太小，将负面地影响晶体管性能。在一些实施例中，它们的宽度由介电鳍片229之间的间距限制，并且它们的高度被控制为与介电鳍片229的高度大致相同。拥有上述的配置有助于将相邻源极/漏极部件短路的风险降至最低。在各种实施例中，半导体层239的宽度w5大于宽度w1。
继续参考图11D，半导体层204在源极/漏极部件260附近具有宽度w2并且具有高度H2。在一些实施例中，宽度w2在约20纳米至约40纳米的范围，高度H2在约14纳米至约26纳米的范围。在各种实施例中，w1与w2的比例在1至3的范围，并且w6与w2的比例在1至3的范围。如上所述，一般而言希望源极/漏极部件260/260’较宽(例如，为了降低源极/漏极电阻)，因此w1和w6大于w2。然而，w1：w2和w6：w2的比例不能太大。首先，宽度w1和w6的上限受到增加装置整合度的期望的限制。其次，宽度w2不能太小。否则，背侧源极/漏极电阻可能过大或背侧介电填充制程(替换半导体层204)可能变得困难。
在操作118，方法100(图1B)形成接触蚀刻停止层(contact etch stop layer,CESL)269和层间介电(inter-layer dielectric,ILD)层270。根据一实施例，在图12A-图12D中示出所得结构。图12A绘示装置200的俯视图，并且图12B、图12C和图12D分别沿着图12A中的B-B线、C-C线和D-D线绘示装置200的部分剖面图。
如图12B-图12D所示，CESL 269沉积在源极/漏极部件260/260’之上，并且ILD层270沉积在CESL 269之上并填充相对的栅极间隔物247之间的空间。CESL 269包括不同于ILD层270且不同于介电层234的材料。CESL 269可以包括La2O3、Al2O3、SiOCN、SiOC、SiCN、SiO2、SiC、ZnO、ZrN、Zr2Al3O9、TiO2、TaO2、ZrO2、HfO2、Si3N4、Y2O3、AlON、TaCN、ZrSi或其他合适的材料，并且可以通过CVD、PVD、ALD或其他合适的方法形成。ILD层270可以包括四乙基原硅酸盐(tetraethylorthosilicate,TEOS)氧化物、未掺杂的硅酸盐玻璃或掺杂的氧化硅，例如硼磷硅酸盐玻璃(borophosphosilicate glass,BPSG)、掺氟石英玻璃(fluoride-dopedsilica glass,FSG)、磷硅酸盐玻璃(phosphosilicate glass,PSG)、掺硼硅玻璃(borondoped silicon glass,BSG)、低介电常数介电材料、其他合适的介电材料或其组合。可以通过PECVD(等离子体辅助CVD)、FCVD(流动式CVD)或其他合适的方法形成ILD层270。在沉积CESL 269以及ILD层270之后，可以执行CMP制程及/或其他平坦化制程，直到到达(露出)虚设栅极堆叠240的顶部(或顶表面)。在一些实施例中，平坦化制程去除虚设栅极堆叠240的硬遮罩层246以露出下方的虚设栅极电极245，例如多晶硅栅极电极层。
在操作120，方法100(图1B)用功能性栅极堆叠240’(例如高介电常数金属栅极)替换虚设栅极堆叠240。根据一实施例，在图13A、图13B和图13C中示出所得结构。图13A绘示装置200的俯视图，并且图13B和图13C分别沿着图13A中的B-B线和C-C线绘示装置200的部分剖面图。这涉及以下简要描述的各种制程。
首先，操作120使用一个或多个蚀刻制程去除虚设栅极堆叠240(虚设栅极电极245和虚设栅极介电层235，参考图4B)。其形成栅极沟槽。蚀刻制程可为干式蚀刻制程、湿式蚀刻制程、其他合适的蚀刻制程或其组合。在一些实施例中，蚀刻制程是多步骤蚀刻制程。例如，蚀刻制程可以交替蚀刻剂以分别去除虚设栅极堆叠240的各个膜层。在一些实施例中，蚀刻制程被配置为选择性地蚀刻虚设栅极堆叠240，而最少地(至没有)蚀刻装置200的其他部件，例如ILD层270、栅极间隔物247、隔离部件230、包覆层231、半导体层215和半导体层210。
接下来，操作120去除在栅极沟槽中露出的包覆层231。蚀刻制程可以选择性地蚀刻包覆层231，而最少地(至没有)蚀刻半导体层215、栅极间隔物247和内部间隔物255。
接着，操作120去除在栅极沟槽中露出的半导体层210，留下悬置于半导体层204上方且与源极/漏极部件260/260’连接的半导体层215。其制程也被称为通道释出(release)制程并且半导体层215也被称为通道层。蚀刻制程选择性地蚀刻半导体层210，而最少地(至没有)蚀刻半导体层215，并且在一些实施例中，最少地(至没有)蚀刻栅极间隔物247及/或内部间隔物255。在装置200是FinFET的实施例中，因为在通道区中只有通道层215而没有半导体层210，所以省略通道释出制程。
接下来，操作120形成包绕(wrap around)每个半导体层215的栅极介电层349，并在栅极介电层349上方形成栅极电极350。功能性栅极堆叠240’包括栅极介电层349和栅极电极350。栅极介电层349可以包括高介电常数介质材料，例如HfO2、HfSiO、HfSiO4、HfSiON、HfLaO、HfTaO、HfTiO、HfZrO、HfAlOx、ZrO、ZrO2、ZrSiO2、AlO、AlSiO、Al2O3、TiO、TiO2、LaO、LaSiO、Ta2O3、Ta2O5、Y2O3、SrTiO3、BaZrO、BaTiO3(BTO)、(Ba、Sr)TiO3(BST)、Si3N4、二氧化铪-氧化铝(HfO2-Al2O3)合金、其他合适的高介电常数介电材料或其组合。高介电常数介电材料通常是指具有高介电常数的介电材料，例如，介电常数大于氧化硅的介电常数(介电常数约为3.9)。可以通过化学氧化、热氧化、原子层沉积(ALD)、化学气相沉积(CVD)及/或其他合适的方法形成栅极介电层349。在一些实施例中，栅极堆叠240’还包括在栅极介电层349和通道层215之间的界面层。界面层可以包括二氧化硅、氮氧化硅或其他合适的材料。在一些实施例中，栅极电极层350包括n型或p型功函数层和金属填充层。例如，n型功函数层可以包括具有足够低的有效功函数的金属，例如钛、铝、碳化钽、氮化碳化钽、氮化钽硅或其组合。例如，p型功函数层可以包括具有足够大的有效功函数的金属，例如氮化钛、氮化钽、钌、钼、钨、铂或其组合。例如，金属填充层可以包括铝、钨、钴、铜及/或其他合适的材料。可以通过CVD、PVD、电镀及/或其他合适的制程形成栅极电极层350。由于栅极堆叠240’包括高介电常数介电层和金属层，因此其也被称为高介电常数金属栅极。
在操作122，方法100(图1B)执行中段(mid-end-of-line,MEOL)制程和后段(back-end-of-line,BEOL)制程。根据一实施例，在图14A-图14D中示出所得结构。图14A绘示装置200的俯视图，并且图14B、图14C和图14D分别沿着图14A中的B-B线、C-C线和D-D线绘示装置200的部分剖面图。例如，操作122蚀刻源极/漏极接触孔以露出一些源极/漏极部件260/260’。在一些实施例中，可以部分蚀刻源极/漏极部件260/260’。蚀刻制程可以是干式蚀刻、湿式蚀刻、反应离子蚀刻或其他蚀刻方法。之后，操作122在源极/漏极部件260/260’上方形成硅化物部件273并在硅化物部件273上方形成源极/漏极接触件(或导孔)275。由于硅化物部件273和源极/漏极接触件275形成在装置200的前侧，它们也分别称为前侧硅化物部件273和前侧源极/漏极接触件275。
硅化物部件273可以包括硅化钛(TiSi)、硅化镍(NiSi)、硅化钨(WSi)、硅化镍铂(NiPtSi)、硅化镍铂锗(NiPtGeSi)、硅化镍锗(NiGeSi)、硅化镱(YbSi)、硅化铂(PtSi)、硅化铱(IrSi)、硅化铒(ErSi)、硅化钴(CoSi)或其他合适的化合物。在一实施例中，源极/漏极接触件275可以包括导电阻障层和在导电阻障层上方的金属填充层。导电阻挡层可以包括钛(Ti)、钽(Ta)、钨(W)、钴(Co)、钌(Ru)或导电氮化物，例如氮化钛(TiN)、氮化钛铝(TiAlN)、氮化钨(WN)、氮化钽(TaN)或其组合，并且可以通过CVD、PVD、ALD及/或其他合适的制程形成。金属填充层可以包括钨(W)、钴(Co)、钼(Mo)、钌(Ru)、或其他金属，并且可以通过CVD、PVD、ALD、电镀或其他合适的制程形成。在一些实施例中，可以在源极/漏极接触件275中省略导电阻障层。
操作122可以形成连接到栅极堆叠240’的栅极导孔，形成连接到源极/漏极接触件275的源极/漏极接触导孔，以及形成一个或多个互连层，其具有嵌入介电层中的导线和导孔。一个或多个互连层连接各个晶体管的栅极、源极和漏极以及装置200中的其他电路，以部分或整体形成集成电路。操作122还可以在互连层上方形成钝化层。在图14B所示的示例中，层277用于表示各种介电层和金属层，包括在装置200的前侧形成在源极/漏极接触件275上方的互连层和钝化层。
在操作124，方法100(图1C)将装置200上下颠倒，并将装置200的前侧附接到载体370，例如图15B所示。图15A绘示装置200的俯视图，并且图15B、图15C、图15D和图15E分别沿着图15A中的B-B线、C-C线、D-D线和E-E线绘示装置200的部分剖面图。这使得可以从装置200的背侧进行进一步制程。操作124可以使用任何合适的附接制程，例如直接键合、混合键合(hybrid bonding)、使用粘着剂或其他键合方法。操作124可以进一步包括对准、退火及/或其他制程。在一些实施例中，载体370可以是硅晶圆。在图15B-图15E中(如同在以下描述的其他图式中)，“z”方向从装置200的背侧指向装置200的前侧，而“-z”方向从装置200的前侧指向装置200的背侧。
在操作126，方法100(图1C)从装置200的背侧薄化装置200，直到半导体层204、半导体层239和隔离结构230从装置200的背侧露出。根据一实施例，图16A-图16E示出所得的结构。图16A绘示装置200的俯视图，并且图16B、图16C、图16D和图16E分别沿着图16A中的B-B线、C-C线、D-D线和E-E线绘示装置200的部分剖面图。薄化制程可以包括机械研磨制程及/或化学薄化制程。在机械研磨制程中，可以首先从基板201上去除大量的基板材料。之后，化学薄化制程可以将蚀刻化学品施加到基板201的背侧，以进一步薄化基板201。
在操作128，方法100(图1C)选择性地蚀刻半导体层204(以及部分的鳍片218)，以在栅极堆叠240’和源极/漏极部件260/260’的背侧上形成沟槽272。根据一实施例，图17A-图17E示出所得的结构。图17A绘示装置200的俯视图，并且图17B、图17C、图17D和图17E分别沿着图17A中的B-B线、C-C线、D-D线和E-E线绘示装置200的部分剖面图。在本实施例中，操作128应用蚀刻制程，其蚀刻制程被调整为对半导体层204的材料进行选择性的蚀刻制程，而未(或最少地)蚀刻半导体层239、源极/漏极部件260、栅极堆叠240’和隔离结构230。蚀刻制程可以是干式蚀刻、湿式蚀刻、反应离子蚀刻或其他蚀刻方法。
在操作130，方法100(图1C)形成一个或多个介电层276以填充沟槽272。例如，一个或多个介电层276可以包括介电衬层274以及一个或多个介电层276。根据一实施例，图18A-图18E示出所得的结构。图18A绘示装置200的俯视图，并且图18B、图18C、图18D和图18E分别沿着图18A中的B-B线、C-C线、D-D线和E-E线绘示装置200的部分剖面图。在一些实施例中，介电衬层274可以包括La2O3、Al2O3、SiOCN、SiOC、SiCN、SiO2、SiC、ZnO、ZrN、Zr2Al3O9、TiO2、TaO2、ZrO2、HfO2、Si3N4、Y2O3、AlON、TaCN、ZrSi或其他合适的材料；并且可以使用CVD、PVD、ALD或其他合适的方法形成介电衬层274。在一些实施例中，介电层276可以包括四乙基原硅酸盐(TEOS)氧化物、未掺杂的硅酸盐玻璃或掺杂的氧化硅，例如硼磷硅酸盐玻璃(BPSG)、掺氟石英玻璃(FSG)、磷硅酸盐玻璃(PSG)、掺硼硅玻璃(BSG)及/或其他合适的介电材料。可以通过PECVD(等离子体辅助CVD)、FCVD(流动式CVD)或其他合适的方法形成介电层276。
在操作132，方法100(图1C)从装置200的背侧去除半导体层239。根据一实施例，图19A-图19E示出所得的结构。图19A绘示装置200的俯视图，并且图19B、图19C、图19D和图19E分别沿着图19A中的B-B线、C-C线、D-D线和E-E线绘示装置200的部分剖面图。在本实施例中，操作132应用蚀刻制程，其蚀刻制程被调整为对半导体层239的材料(在一个实施例中例如为SiGe)具有选择性，而没有(或最少)蚀刻介电衬层274、介电层276和隔离部件230。在一些实施例中，蚀刻制程可以不蚀刻源极部件260’，并且在一些替代实施例中可以部分地蚀刻源极部件260’。蚀刻制程产生从装置200的背侧露出源极部件260’的沟槽278。蚀刻制程可以是干式蚀刻、湿式蚀刻、反应离子蚀刻或其他蚀刻方法。详细而言，在本实施例中，半导体层239的蚀刻是自对准的。换言之，操作132不需要形成蚀刻遮罩(例如，通过微影制程形成的蚀刻遮罩)以蚀刻半导体层239。相反地，其依赖半导体层239及其周围膜层中材料的蚀刻选择性。这有益处地形成与下方的源极部件260’对齐的沟槽278，而不具有未对齐的情况，例如由微影覆盖偏移(overlay shift)所引起。使用此制程将产生与源极部件260’理想地对齐的背侧源极接触件(或源极导孔)，如下所述。此外，由于半导体层239具有扩大的轮廓，而沟槽278也具有扩大的轮廓，这使得在其中形成硅化物部件以及导孔结构时更容易填充金属材料。
在操作134，方法100(图1C)在沟槽(或通孔)278中形成背侧源极硅化物部件280和背侧接触件(或导孔或金属插塞)282。根据一实施例，图20A-图20E示出所得的结构。图20A绘示装置200的俯视图，并且图20B、图20C、图20D和图20E分别沿着图20A中的B-B线、C-C线、D-D线和E-E线绘示装置200的部分剖面图。
在一个实施例中，操作134将一种或多种金属沉积到通孔278中，对装置200执行退火制程以引起一种或多种金属与源极/漏极部件260’之间的反应，以产生硅化物部件280，并去除一种或多种金属的未反应部分，将硅化物部件280留在通孔中。一种或多种金属可以包括钛(Ti)、钽(Ta)、钨(W)、镍(Ni)、铂(Pt)、镱(Yb)、铱(Ir)、铒(Er)、钴(Co)或其组合(例如，两种或多种金属的合金)，并且可以使用CVD、PVD、ALD或其他合适的方法进行沉积。硅化物部件280可以包括硅化钛(TiSi)、硅化镍(NiSi)、硅化钨(WSi)、硅化镍铂(NiPtSi)、硅化镍铂锗(NiPtGeSi)、硅化镍锗(NiGeSi)、硅化镱(YbSi)、硅化铂(PtSi)、硅化铱(IrSi)、硅化铒(ErSi)、硅化钴(CoSi)或其他合适的化合物。
之后，操作134在通孔(via hole)278中沉积导孔(via)282并接触硅化物部件280。导孔282可以包括导电阻障层和在导电阻障层上方的金属填充层。导电阻挡层可以包括钛(Ti)、钽(Ta)、钨(W)、钴(Co)、钌(Ru)或导电氮化物，例如氮化钛(TiN)、氮化钛铝(TiAlN)、氮化钨(WN)、氮化钽(TaN)或其组合，并且可以通过CVD、PVD、ALD及/或其他合适的制程形成。金属填充层可以包括钨(W)、钴(Co)、钼(Mo)、钌(Ru)、或其他金属，并且可以通过CVD、PVD、ALD、电镀或其他合适的制程形成。由于通孔278扩大的轮廓，硅化物部件280和导孔282具有扩大的体积，有益处地降低其接触电阻。在结构200的背侧薄化不使半导体层239在其最宽部分下方凹陷的实施例中，导孔282具有沿着“z”方向变宽(widens)然后变窄(narrows)的轮廓，如图20C所示。在这样的实施例中，导孔282具有大于源极部件260’宽度w1的宽度w5(如以上参考图9C所讨论)。在结构200的背侧薄化使半导体层239在其最宽部分下方凹陷的一些实施例中，导孔282具有大致沿着“z”方向变窄的轮廓(未示出)。即使在这些实施例中，导孔282也可以沿着“y”方向比源极部件260’宽。在各种实施例中，导孔282可以沿着“-z”方向在介电鳍片229正上方横向延伸。换言之，导孔282可以沿着“z”方向在介电鳍片229正下方横向延伸。这种轮廓在导孔282中提供大体积。在本实施例中，导孔282在x-z平面中具有接近垂直的轮廓，如图20B所示。例如，导孔282的侧壁可以与垂直方向在+/-10度内。在一些实施例中，导孔282在x-z平面(未示出)中具有一般梯形的轮廓，其一般沿着“z”方向变窄。
在操作136，方法100(图1C)对装置200进行进一步制造。例如，操作136形成背侧电源轨284和背侧互连286。根据一实施例，图21A-图21B示出所得的结构。图21A绘示装置200的俯视图，并且图21B沿着图21A中的B-B线绘示装置200的部分剖面图。如图21B所示，背侧导孔282电性连接到背侧电源轨284。在一个实施例中，可以使用镶嵌制程、双镶嵌制程、金属图案化制程或其他合适的制程形成背侧电源轨284。背侧电源轨284可以包括钨(W)、钴(Co)、钼(Mo)、钌(Ru)、铜(Cu)、铝(Al)、钛(Ti)、钽(Ta)或其他金属，并且可以通过CVD、PVD、ALD、电镀或其他合适的制程沉积。尽管在图21B中未示出，但是背侧电源轨284嵌入在一个或多个介电层中，且背侧互连286包括嵌入在一个或多个介电层中的导线以及导孔。在一些实施例中，背侧电源轨284被认为是背侧互连286的一部分。具有背侧电源轨284有益处地增加装置200中可用于直接连接到源极/漏极接触件和导孔的金属轨的数量。与没有背侧电源轨284的其他结构相比，其也增加了栅极密度，以实现更大的装置整合度。背侧电源轨284的尺寸可以比装置200的前侧上的第一层金属(M0)轨的尺寸更宽，这有益处地减小背侧电源轨的电阻。
在上述实施例中，源极部件260形成有前侧和背侧硅化物部件以及前侧和背侧接触件，而漏极部件260形成有前侧硅化物部件和前侧接触件，并且与背侧电源轨隔离。在替代实施例中，漏极部件260形成有前侧和背侧硅化物部件以及前侧和背侧接触件，而源极部件260形成有前侧硅化物部件和前侧接触件，并且与背侧电源轨隔离。其可以通过将上述实施例中用于源极区的制程与用于漏极区的制程进行切换来实现。在另一替代实施例中，源极部件260和漏极部件260都可以形成有前侧和背侧硅化物部件以及前侧和背侧接触件。其可以通过将上述实施例中用于源极区的制程用于源极区和漏极区来实现。
尽管不意旨在限制，但是本公开的实施例提供以下一个或多个益处。例如，本公开的实施例形成具有扩大轮廓的背侧导孔，其有益处地降低背侧上源极/漏极的接触电阻。本公开的实施例可以容易地整合到现有的半导体制造制程中。
在一个示例方面，本公开一些实施例提供一种半导体结构，包括：隔离结构；第一源极/漏极部件(S/D)以及第二源极/漏极部件，在隔离结构上，定义第一方向，在俯视图中，第一方向从第一源极/漏极部件至第二源极/漏极部件；一个或多个通道层，连接第一源极/漏极部件以及第二源极/漏极部件；栅极结构，在第一源极/漏极部件以及第二源极/漏极部件之间，且齿合(engaging)每个通道层；以及导孔结构，在第一源极/漏极部件下方，且电性连接至第一源极/漏极部件，其中，在垂直于第一方向的剖面图中，导孔结构具有轮廓，轮廓沿着由下至上(bottom-up)的方向由宽(widens)至窄(narrows)。
在一些实施例中，还包括：源极/漏极接触件，设置在第一源极/漏极部件上并连接至第一源极/漏极部件。
在一些实施例中，还包括硅化物部件，在第一源极/漏极部件以及导孔结构之间。
在一些实施例中，还包括介电部件，在第二源极/漏极部件正下方并接触第二源极/漏极部件。
在一些实施例中，还包括源极/漏极接触件，在第二源极/漏极部件上，且电性连接至第二源极/漏极部件。
在一些实施例中，还包括介电鳍片，邻近第一源极/漏极部件的侧壁。
在一些实施例中，导孔结构在介电鳍片中的至少一个的正下方延伸。
在一些实施例中，通道层包括半导体层的堆叠，且栅极结构包绕(wraps around)堆叠的每个半导体层。
在一些实施例中，在剖面图中，导孔结构比第一源极/漏极部件宽。
在另一个示例方面，本公开另一些实施例提供一种形成半导体结构的方法，包括：提供结构，结构具有基板、隔离结构，在基板上、鳍片，从基板延伸且邻近隔离结构、牺牲栅极结构，设置在鳍片的通道区上、以及栅极间隔物，在牺牲栅极结构的两侧侧壁上；对邻近栅极间隔物的鳍片进行第一蚀刻以形成第一源极/漏极沟槽以及第二源极/漏极沟槽，第一源极/漏极沟槽在牺牲栅极结构的一侧上，第二源极/漏极沟槽在牺牲栅极结构的另一侧上；形成蚀刻遮罩，蚀刻遮罩露出第一源极/漏极沟槽并覆盖第二源极/漏极沟槽；透过蚀刻遮罩对鳍片进行第二蚀刻，以深化(deepen)第一源极/漏极沟槽；以及在第二蚀刻之后，横向蚀刻露出于第一源极/漏极沟槽的下部的隔离结构的部分，得到第一源极/漏极沟槽的扩大的下部。
在另一些实施例中，还包括：在横向蚀刻之后，至少在第一源极/漏极沟槽的扩大的下部中外延成长第一半导体层。
在另一些实施例中，还包括：在第一半导体层上外延成长第一半导体源极/漏极部件。
在另一些实施例中，还包括：在第一半导体源极/漏极部件上形成接触部件。
在另一些实施例中，隔离结构设置在基板的前侧上，还包括：从基板与前侧相对的背侧薄化(thinning down)基板，从而从背侧露出第一半导体层以及鳍片。
在另一些实施例中，还包括：从背侧蚀刻第一半导体层以露出第一半导体源极/漏极部件，得到导孔；以及在导孔中形成金属插塞。
在另一些实施例中，还包括：在背侧上形成金属轨(track)，金属轨电性连接至金属插塞。
在又一个示例方面，本公开又一些实施例提供一种形成半导体结构的方法，包括：提供结构，结构具有基板、隔离结构，在基板上、鳍片，从基板延伸且邻近隔离结构、牺牲栅极结构，设置在鳍片的通道区上、以及栅极间隔物，在牺牲栅极结构的两侧侧壁上；对邻近栅极间隔物的鳍片进行第一蚀刻以形成第一源极/漏极沟槽以及第二源极/漏极沟槽，第一源极/漏极沟槽在牺牲栅极结构的一侧上，第二源极/漏极沟槽在牺牲栅极结构的另一侧上；形成蚀刻遮罩，蚀刻遮罩露出第一源极/漏极沟槽并覆盖第二源极/漏极沟槽；透过蚀刻遮罩对鳍片进行第二蚀刻，以深化(deepen)第一源极/漏极沟槽；在第二蚀刻之后，横向蚀刻露出于第一源极/漏极沟槽的下部的隔离结构的部分，得到第一源极/漏极沟槽的扩大的下部；至少在第一源极/漏极沟槽的扩大的下部中成长第一半导体层，其中第一半导体层包括不同于鳍片的材料；以及在第一半导体层上外延成长第一半导体源极/漏极部件。
在又一些实施例中，还包括：以高介电常数金属栅极替换牺牲栅极结构。
在又一些实施例中，还包括：在第一半导体源极/漏极部件上形成源极/漏极接触件。
在又一些实施例中，隔离结构设置在基板的前侧上，还包括：从基板相对于前侧的背侧薄化基板，从而从背侧露出第一半导体层以及鳍片；去除鳍片以形成沟槽；在沟槽中沉积一个或多个介电材料；蚀刻第一半导体层以形成导孔；以及在导孔中形成金属插塞。
以上概述数个实施例的特征，以使本发明所属技术领域中具有通常知识者可以更加理解本发明实施例的观点。本发明所属技术领域中具有通常知识者应理解，可轻易地以本发明实施例为基础，设计或修改其他制程和结构，以达到与在此介绍的实施例相同的目的及/或优势。在本发明所属技术领域中具有通常知识者也应理解，此类等效的结构并无悖离本发明的精神与范围，且可在不违背本发明的精神和范围下，做各式各样的改变、取代和替换。因此，本发明的保护范围当视后附的权利要求所界定为准。

Claims (1)

1.一种半导体结构，包括：
一隔离结构；
一第一源极/漏极部件以及一第二源极/漏极部件，在该隔离结构上，定义一第一方向，在一俯视图中，该第一方向从该第一源极/漏极部件至该第二源极/漏极部件；
一个或多个通道层，连接该第一源极/漏极部件以及该第二源极/漏极部件；
一栅极结构，在该第一源极/漏极部件以及该第二源极/漏极部件之间，且齿合每个通道层；以及
一导孔结构，在该第一源极/漏极部件下方，且电性连接至该第一源极/漏极部件，
其中，在垂直于该第一方向的一剖面图中，该导孔结构具有一轮廓，该轮廓沿着一由下至上的方向由宽至窄。
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