CN113113490B - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
CN113113490B
CN113113490B CN202011635419.6A CN202011635419A CN113113490B CN 113113490 B CN113113490 B CN 113113490B CN 202011635419 A CN202011635419 A CN 202011635419A CN 113113490 B CN113113490 B CN 113113490B
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silicide
layer
dielectric
source
dielectric layer
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CN113113490A (zh
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黄麟淯
游力蓁
张家豪
庄正吉
程冠伦
王志豪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种形成半导体结构的方法包括提供一种结构，具有衬底、鳍部、源极/漏极(S/D)部件、与鳍部的侧壁相邻的隔离结构、在第一介电层上并且连接S/D部件的一个或多个沟道层以及接合一个或多个沟道层的栅极结构。方法还包括从结构的背面减薄结构直到鳍部被暴露以及选择性地蚀刻鳍部以形成沟槽，沟槽暴露S/D部件的表面、第一介电层和隔离结构。方法还包括在S/D部件上形成硅化物部件以及在硅化物部件上但不在第一介电层和隔离结构的表面上沉积抑制剂，在隔离结构和第一介电层的表面上但不在抑制剂上沉积介电衬垫层，以及选择性地去除抑制剂。本发明的实施例还提供了一种半导体结构。

Description

半导体结构及其形成方法
技术领域
本发明的实施例涉及半导体结构及其形成方法。
背景技术
常规地，集成电路(IC)以堆叠方式构造，具有在最低层级处的晶体管以及在晶体管顶部上的互连件(通孔和引线)以向晶体管提供连接性。电源轨(诸如用于电压源和接地平面的金属线)也在晶体管上并且可以是互连件的一部分。随着集成电路持续缩小，电源轨也缩小。这不可避免地导致跨电源轨的电压降增加，以及集成电路的功耗增加。因此，尽管半导体制造中的现有方法通常适用于其预期目的，但它们并非在所有方面都完全令人满意。一个所关注的领域是如何在IC的背面上以减小的电阻形成电源轨和通孔。
发明内容
根据本发明的一个方面，提供了一种形成半导体结构的方法，包括：提供一种结构，具有正面和背面，结构包括衬底、在衬底上的半导体鳍部、在半导体鳍部上的两个源极/漏极部件、在半导体鳍部上的第一介电层、与半导体鳍部的侧壁相邻的隔离结构、在第一介电层上并且连接两个源极/漏极部件的一个或多个沟道半导体层以及接合一个或多个沟道半导体层的栅极结构，其中，衬底在结构的背面处并且栅极结构在结构的正面处；从结构的背面减薄结构直到半导体鳍部被暴露；从结构的背面选择性地蚀刻半导体鳍部以形成沟槽，其中，沟槽暴露两个源极/漏极部件的表面、第一介电层的表面和隔离结构的侧壁；在源极/漏极部件的表面上形成硅化物部件；在沟槽中选择性地沉积抑制剂，其中，抑制剂沉积在硅化物部件上，但不在第一介电层的表面和隔离结构的侧壁上沉积；在沟槽中选择性地沉积介电衬垫层，其中，介电衬垫层沉积在隔离结构的侧壁和第一介电层的表面上，但不在抑制剂上沉积；以及选择性地去除抑制剂。
根据本发明的另一个方面，提供了一种形成半导体结构的方法，包括：提供一种结构，具有衬底、在衬底上的半导体鳍部、在半导体鳍部上的两个源极/漏极部件、在半导体鳍部的侧壁上的隔离结构、在半导体鳍部上的介电覆盖层、在介电覆盖层上的一个或多个沟道半导体层以及接合一个或多个沟道半导体层的栅极结构；减薄衬底直到半导体鳍部被暴露；选择性地蚀刻半导体鳍部以形成沟槽，其中，沟槽暴露两个源极/漏极部件的表面、介电覆盖层的表面和隔离结构的侧壁；在源极/漏极部件的表面上形成硅化物部件；在硅化物部件上但不在介电覆盖层的表面和隔离结构的侧壁上沉积抑制剂；在隔离结构的侧壁和介电覆盖层的表面上但不在抑制剂上沉积介电衬垫层；选择性地去除抑制剂；以及在沟槽中形成通孔结构。
根据本发明的又一个方面，提供了一种半导体结构，包括：两个源极/漏极部件；连接两个源极/漏极部件的一个或多个沟道半导体层；接合一个或多个沟道半导体层的栅极结构，其中，两个源极/漏极部件、一个或多个沟道半导体层和栅极结构在半导体结构的正面处；在半导体结构的背面处的金属轨道；在金属轨道与一个或多个沟道半导体层之间的第一介电层；在第一介电层的表面上且通过第一间隙与两个源极/漏极部件中的一个源极/漏极部件间隔开的介电衬垫层；以及将金属轨道与两个源极/漏极部件中的一个源极/漏极部件连接的通孔结构，其中，通孔结构的一部分被设置在第一间隙中。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本公开。应该强调，根据工业中的标准实践，各个部件未按比例绘制并且仅用于说明的目的。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1A和图1B示出了根据本公开的各个方面的形成具有背面电源轨和背面通孔的半导体器件的方法的流程图。
图2A、图3A、图4A、图5A、图6A、图7A、图8A、图9A、图10A、图11A、图12A和图13A示出了根据一些实施例的半导体器件的一部分的俯视图。
图2B、图3B、图4B、图5B、图6B、图7B、图8B、图9B、图10B、图11B、图12B和图13B示出了根据一些实施例的分别沿图2A、图3A、图4A、图5A、图6A、图7A、图8A、图9A、图10A、图11A、图12A和图13A中的线B-B的半导体器件的一部分的截面图。
图2C、图4C、图5C、图6C、图7C、图8C、图9C、图10C、图11C、图12C和图13C示出了根据一些实施例的分别沿图2A、图4A、图5A、图6A、图7A、图8A、图9A、图10A、图11A、图12A和图13A中的线C-C的半导体器件的一部分的截面图。
图2D、图4D、图5D、图6D、图7D、图8D、图9D、图10D、图11D、图12D和图13D示出了根据一些实施例的分别沿图2A、图4A、图5A、图6A、图7A、图8A、图9A、图10A、图11A、图12A和图13A中的线D-D的半导体器件的一部分的截面图。
图2E、图4E、图5E、图6E、图7E、图8E、图9E、图10E、图11E、图12E和图13E示出了根据一些实施例的分别沿图2A、图4A、图5A、图6A、图7A、图8A、图9A、图10A、图11A、图12A和图13A中的线E-E的半导体器件的一部分的截面图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本公开。当然，这些仅仅是实例，而并非旨在是限制性的。例如，以下描述中，在第二部件上面或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本公开可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
此外，为了便于描述，本文中可以使用诸如“在……下方”、“在……下面”、“下部”、“在……上面”、“上部”等的间隔关系术语，以描述如图中所示的一个元件或部件与另一个(另一些)元件或部件的关系。除了图中所示的方位外，间隔关系术语旨在包括器件在使用或操作工艺中的不同方位。装置可以以其它方式定位(旋转90度或在其它方位)，并且在本文中使用的间隔关系描述符可以同样地作相应地解释。更进一步，当用“约”、“近似”等描述数字或数字范围时，除非另有说明，否则鉴于本文公开的特定技术，根据本领域技术人员的知识，术语涵盖在数字的某些变型(诸如+/-10％或其它变型)内的数字。例如，术语“约5nm”可以涵盖4.5nm至5.5nm、4.0nm至5.0nm等的尺寸范围。
本申请总体上涉及半导体结构和制造工艺，并且更具体地涉及具有背面电源轨和背面通孔的半导体器件。如上所讨论的，IC中的电源轨需要进一步改进，以便提供所需的性能提升以及降低功耗。本公开的目的包括：除了结构的正侧(或正面)上的互连结构(其也可以包括电源轨)之外，在包含晶体管(诸如全环栅(GAA)晶体管和/或FinFET晶体管)的结构的背侧(或背面)上提供电源轨(或电源布线)。这增加了结构中可用于与源极/漏极接触件(contact，接触件)和通孔直接连接的金属轨道的数量。与没有背面电源轨的现有结构相比，它还提高了栅极密度，实现更高的器件集成度。背面电源轨的尺寸可以比结构的正面上的第一级金属(M0)轨道更宽，这有益地降低了电源轨电阻。本公开还提供了用于将背面电源轨连接到正面上的S/D部件的背面通孔结构。背面通孔结构具有衬垫层，在背面过孔的侧壁上沉积衬垫层，但不在背面过孔的底表面上沉积。这消除了在将导体沉积到背面过孔中时穿透衬垫层的步骤，从而防止对源极/漏极部件的背面的损坏。它还增加了用于硅化的源极/漏极部件的面积，并且总体上增加了源极/漏极接触面积，从而降低了来自晶圆的背面的源极/漏极接触电阻。以下结合附图对本公开的结构和制造方法的细节进行描述，附图示出了根据一些实施例的制造GAA器件的工艺。GAA器件是指具有竖直堆叠的水平取向的多沟道晶体管(诸如纳米线晶体管和纳米片晶体管)的器件。GAA器件由于其更好的栅极控制能力、更低的漏电流和完全FinFET器件布局兼容性而成为将CMOS带到下一级路线图(roadmap)的有前景的候选物。为了简单起见，本公开使用GAA器件作为示例。本领域普通技术人员应当理解，他们可以容易地使用本公开作为设计或修改用于实现本文所介绍的实施例的相同目的和/或实现其相同优点的其它过程和结构(诸如FinFET器件)的基础。
图1A和图1B为根据本公开的不同方面的用于制造半导体器件的方法100的流程图。本公开考虑了附加的处理。可以在方法100之前、期间和之后提供附加操作，并且对于方法100的附加实施例，可以移动、替换或去除所描述的操作中的一些操作。
下面结合图2A至图13E描述方法100，这些图示出了根据一些实施例的在根据方法100的各个制造步骤处的半导体器件(或半导体结构)200的各种俯视图和截面图。在一些实施例中，器件200是IC芯片的一部分、片上系统(SoC)或其一部分，其包括各种无源和有源微电子器件，诸如电阻器、电容器、电感器、二极管、p型场效应晶体管(PFET)、n型场效应晶体管(NFET)、FinFET、纳米片FET、纳米线FET、其它类型的多栅FET、金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极结型晶体管(BJT)、横向扩散MOS(LDMOS)晶体管、高压晶体管、高频晶体管、存储器件、其它合适的组件或其组合。为了清楚起见，图2A至图13E已经被简化以更好地理解本公开的发明概念。在器件200中可以添加附加部件，并且在器件200的其它实施例中可以替换、修改或去除下面描述的部件中的一些部件。
在操作102处，方法100(图1A)提供具有衬底201及构造在衬底201的正面上的晶体管的半导体器件200。图2A示出了器件200的俯视图，图2B、2C、2D和2E分别示出了器件200沿图2A中的线B-B、线C-C、线D-D和线E-E的部分截面图。特别地，线B-B沿半导体鳍部204的长度方向(“X”方向)切割，线C-C沿栅极堆叠件240的长度方向(“Y”方向)切割，线D-D被切割进入晶体管的源极区并平行于栅极堆叠件240，并且线E-E被切割进入晶体管的漏极区并平行于栅极堆叠件240。图3A至图13A中的线B-B、线C-C、线D-D和线E-E被类似地配置。
参考图2A至图2E，半导体器件200包括在其背面处的衬底201和在衬底201的正面上构造的各种元件。这些元件包括在衬底201上的隔离结构230、从衬底201延伸并与隔离结构230相邻的半导体鳍部204、在半导体鳍部204上的两个外延源极/漏极(S/D)部件260、悬置在半导体鳍部204上并连接两个S/D部件260的一个或多个沟道半导体层215、在两个S/D部件260之间并环绕每个沟道层215的栅极堆叠件240以及设置在半导体鳍部204与沟道层215和栅极堆叠件240两者之间的底部自对准覆盖(B-SAC)层203。半导体器件200还包括S/D部件260与栅极堆叠件240之间的内部间隔件255、栅极堆叠件240的侧壁上且在最顶部沟道层215上的(外部)栅极间隔件247、与栅极间隔件247相邻且在外延S/D部件260和隔离结构230上的接触蚀刻停止层(CESL)269、在CESL269上的层间介电(ILD)层270。在栅极堆叠件240上，半导体器件200还包括自对准覆盖层352。在S/D部件260上，半导体器件200还包括硅化物部件273、S/D接触件275、介电S/D覆盖层356和S/D接触通孔358。在所描述的实施例中，S/D覆盖层356设置在源极部件260上，而S/D接触通孔358设置在漏极部件260上。在替代实施例中，S/D覆盖层356可以设置在漏极部件260上，而S/D接触通孔358可以设置在源极部件260上。在一些实施例中，S/D覆盖层356可以设置在源极和漏极部件260两者上。在一些实施例中，S/D接触通孔358可以设置在源极和漏极部件260两者之上。
参考图3A和图3B，半导体器件200还包括一个或多个互连层(用277表示)，其中引线和通孔嵌入在介电层中。一个或多个互连层连接各个晶体管的栅极、源极和漏极电极以及器件200中的其它电路，以部分或全部形成集成电路。半导体器件200还可以包括钝化层、粘附层和/或构造在半导体器件200的正面上的其它层。这些层和一个或多个互连层共同地用标记277表示。注意，在图3B中，半导体器件200被倒置翻转。下面进一步描述半导体器件200的各个元件。
在一种实施例中，衬底201是体硅衬底(即，包括体单晶硅)。在不同实施例中，衬底201可以包括其它半导体材料，诸如锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、锑化铟、SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP或其组合。在替代实施例中，衬底201是绝缘体上半导体衬底，诸如绝缘体上硅(SOI)衬底、绝缘体上硅锗(SGOI)衬底或绝缘体上锗(GOI)衬底。
在实施例中，半导体鳍部204可以包括硅、硅锗、锗或其它合适的半导体，并且可以是掺杂的n型或p型掺杂剂。鳍部204可以通过任何适当的方法来图案化。例如，鳍部204可以使用一个或多个光刻工艺来图案化，包括双重图案化或多重图案化工艺。通常，双重图案化或多重图案化工艺组合光刻和自对准工艺，从而允许产生具有例如比使用单一直接光刻工艺可获得的间距小的间距的图案。例如，在一个实施例中，在衬底上形成牺牲层并且使用光刻工艺对牺牲层进行图案化。使用自对准工艺在被图案化的牺牲层旁边形成间隔件。然后去除牺牲层，并且然后可以将其余的间隔件或芯轴用作用于对鳍部204进行图案化的掩蔽元件。例如，掩蔽元件可以用于蚀刻凹陷进入在衬底201上或中的半导体层，留下衬底201上的鳍部204。蚀刻工艺可以包括干法蚀刻、湿法蚀刻、反应离子蚀刻(RIE)和/或其它合适的工艺。例如，干法蚀刻工艺可以实施含氧气体、含氟气体(例如，CF4、SF6、CH2F2、CHF3和/或C2F6)、含氯气体(例如，Cl2、CHCl3、CCl4和/或BCl3)、含溴气体(例如，HBr和/或CHBr3)、含碘气体其它合适的气体和/或等离子体和/或其组合。例如，湿法蚀刻工艺可以包括在稀释的氢氟酸(DHF)、氢氧化钾(KOH)溶液；氨；包含氢氟酸(HF)、硝酸(HNO3)和/或乙酸(CH3COOH)的溶液；或其它合适的湿蚀刻剂中的蚀刻。形成鳍部204的方法的许多其它实施例可能是合适的。
隔离部件230可以包括氧化硅、氮化硅、氮氧化硅、其它合适的隔离材料(例如，包括硅、氧、氮、碳或其它合适的隔离成分)或其组合。隔离部件230可以包括不同的结构，诸如浅沟槽隔离(STI)结构和/或深沟槽隔离(DTI)结构。在一种实施例中，可以通过用绝缘体材料填充鳍部204之间的沟槽(例如，通过使用CVD工艺或旋涂式玻璃工艺)，执行化学机械抛光(CMP)工艺以去除过量的绝缘体材料和/或平坦化绝缘体材料层的顶表面，以及蚀刻回绝缘体材料层以形成隔离部件230来形成隔离部件230。在一些实施例中，隔离部件230包括多层结构，诸如设置在热氧化物衬垫层上的氮化硅层。
S/D部件260包括外延生长的半导体材料，如外延生长的硅、锗或硅锗。可以通过包括化学气相沉积(CVD)技术(例如，气相外延和/或超高真空CVD)、分子束外延、其它合适的外延生长工艺或其组合等任何外延工艺来形成S/D部件260。S/D部件260可以掺杂有n型掺杂剂和/或p型掺杂剂。在一些实施例中，对于n型晶体管，S/D部件260包括硅，并且可以掺杂有碳、磷、砷、其它n型掺杂剂或其组合(例如，形成Si：C外延S/D部件、Si：P外延S/D部件或Si：C：P外延S/D部件)。在一些实施例中，对于p型晶体管，S/D部件260包括硅锗或锗，并且可以掺杂有硼、其它p型掺杂剂或其组合(例如，形成Si：Ge：B外延S/D部件)。S/D部件260可以包括具有不同掺杂剂密度水平的多个外延半导体层。在一些实施例中，执行退火工艺(例如，快速热退火(RTA)和/或激光退火)以激活外延S/D部件260中的掺杂剂。
在实施例中，沟道层215包括适用于晶体管沟道的半导体材料，如硅、硅锗或(多种)其它半导体材料。在不同实施例中，沟道层215可以是杆、棒、片的形状或其它形状。在一种实施例中，沟道层215最初是包括逐层交替堆叠的沟道层215和其它(牺牲)半导体层的半导体层的堆叠的一部分。牺牲半导体层和沟道层215包括不同的材料成分(诸如不同的半导体材料、不同的组成原子百分比和/或不同的组成重量百分比)以实现蚀刻选择性。在形成栅极堆叠件240的栅极替换工艺期间，牺牲半导体层被选择性地去除，留下悬置在半导体鳍部204上的沟道层215。
在一些实施例中，内部间隔件层255包括介电材料，介电材料包括硅、氧、碳、氮、其它合适的材料或其组合(例如，氧化硅、氮化硅、氮氧化硅、碳化硅或碳氮氧化硅)。在一些实施例中，内部间隔件层255包括低k介电材料，诸如本文中所描述的那些。内部间隔件层255可以通过沉积和蚀刻工艺形成。例如，在S/D沟槽被蚀刻之后并且在S/D部件260从S/D沟槽外延生长之前，可以使用蚀刻工艺使相邻沟道层215之间的牺牲半导体层凹陷，以在相邻沟道层215之间竖直地形成间隙。然后，沉积(例如使用CVD或ALD)一种或多种介电材料以填充间隙。执行另一蚀刻工艺以去除间隙外部的介电材料，从而形成内部间隔件层255。
在一些实施例中，B-SAC层203可以包括以下中的一种或多种：La2O3、Al2O3、SiOCN、SiOC、SiCN、SiO2、ZnO、ZrN、Zr2Al3O9、TiO2、TaO2、ZrO2、HfO2、Si3N4、Y2O3、AlON、TaCN、ZrSi和(多种)其它合适的材料。在一些实施例中，B-SAC层203可以包括低k介电材料，诸如包括Si、O、N和C的介电材料。示例性低k介电材料包括FSG、碳掺杂的氧化硅、Black (加利福尼亚州圣克拉拉的Applied Materials)、干凝胶、气凝胶、无定形氟化碳、帕利灵(Parylene)、BCB、SiLK(密歇根州米德兰的Dow Chemical)、聚酰亚胺或其组合。B-SAC层203可以使用CVD、ALD、PVD或氧化来沉积。在一种实施例中，B-SAC层203最初沉积在半导体鳍部204上并且使用图案化半导体鳍部204的相同工艺来图案化。在另一实施例中，牺牲半导体层(诸如SiGe)最初被沉积在半导体鳍部204上，并且使用对半导体鳍部204进行图案化的相同工艺来进行图案化。在形成栅极堆叠件240的栅极替换过程期间去除牺牲层并且用B-SAC层203来替换牺牲层。B-SAC层203用于将沟道层215和栅极堆叠件240与将在后续工艺中形成的背面通孔隔离。在一些实施例中，B-SAC层203可以具有在0.5nm到约50nm的范围内的厚度d5。在一些实施例中，如果B-SAC层203太薄(诸如，小于0.5nm)，则其可能无法向沟道层215和栅极堆叠件240提供足够的隔离。在一些实施例中，如果B-SAC层203太厚(诸如，大于50nm)，则背面通孔可能较长并且其电阻可能较高，这将在后面进一步讨论。
在所描绘的实施例中，栅极堆叠件240包括栅极介电层349和栅极电极350。栅极介电层349可以包括高k介电材料，诸如HfO2、HfSiO、HfSiO4、HfSiON、HfLaO、HfTaO、HfTiO、HfZrO、HfAlOx、ZrO、ZrO2、ZrSiO2、A10、AlSiO、Al2O3、TiO，TiO2、LaO、LaSiO、Ta2O3、Ta2O5、Y2O3、SrTiO3、BaZrO、BaTiO3(BTO)、(Ba、Sr)TiO3(BST)、Si3N4，二氧化铪-氧化铝(HfO2-Al2O3)合金、其它合适的高k介电材料或其组合。高k介电材料通常是指具有例如大于氧化硅的介电常数(k≈3.9)的高介电常数的介电材料。栅极介电层349可以通过化学氧化、热氧化、原子层沉积(ALD)、化学气相沉积(CVD)和/或其它合适的方法来形成。在一些实施例中，栅极堆叠件240还包括栅极介电层349与沟道层215之间的界面层。界面层可以包括二氧化硅、氮氧化硅或其它合适的材料。在一些实施例中，栅极电极层350包括n型或p型功函数层和金属填充层。例如，n型功函数层可以包括具有足够低的有效功函数的金属，诸如钛、铝、碳化钽、碳化氮化钽、氮化硅钽或其组合。例如，P-型功函数层可以包括具有足够大的有效功函数的金属，诸如氮化钛、氮化钽、钌、钼、钨、钼或其组合。例如，金属填充层可以包括铝、钨、钴、铜和/或其它合适的材料。栅极电极层350可以通过CVD、PVD、电镀和/或其它合适的工艺形成。由于栅极堆叠件240包括高k介电层和(多个)金属层，因此它也被称为高k金属栅极。
在一种实施例中，栅极间隔件247包括介电材料，诸如包括硅、氧、碳、氮、其它合适的材料或其组合的介电材料(例如，氧化硅、氮化硅、氮氧化硅(SiON)、碳化硅、碳氮化硅(SiCN)、碳氧化硅(SiOC)、碳氮氧化硅(SiOCN))。在实施例中，栅极间隔件247可以包括La2O3、Al2O3、SiOCN、SiOC、SiCN、SiO2、SiC、ZnO、ZrN、Zr2Al3O9、TiO2、TaO2、ZrO2、HfO2、Si3N4、Y2O3、AlON、TaCN、ZrSi或(多种)其它合适的材料。例如，包括硅和氮的介电层诸如氮化硅层可以沉积在伪栅极堆叠件(其随后被高k金属栅极240代替)上并且随后被蚀刻(例如，各向异性地蚀刻)以形成栅极间隔件247。在一些实施例中，栅极间隔件247包括多层结构，诸如包括氮化硅的第一介电层和包括氧化硅的第二介电层。在一些实施例中，邻近栅极堆叠件240形成多于一组间隔件，诸如密封间隔件、偏移间隔件、牺牲间隔件、伪间隔件和/或主间隔件。在实施例中，例如，栅极间隔件247可以具有约1nm至约40nm的厚度。
在一些实施例中，SAC层352包括La2O3、Al2O3、SiOCN、SiOC、SiCN、SiO2、SiC、ZnO、ZrN、Zr2Al3O9、TiO2、TaO2、ZrO2、HfO2、Si3N4、Y2O3、AlON、TaCN、ZrSi或(多种)其它合适的材料。SAC层352保护栅极堆叠件240免于用于蚀刻S/D接触孔的蚀刻和CMP工艺。可以通过使栅极堆叠件240凹陷并且可选地使栅极间隔件247凹陷、在凹陷的栅极堆叠件240上并且可选地在凹陷的栅极间隔件247上沉积一种或多种介电材料、以及对一种或多种介电材料执行CMP工艺来形成SAC层352。SAC层352可以具有例如在约3nm到约30nm的范围内的厚度。
在实施例中，CESL 269可以包括La2O3、Al2O3、SiOCN、SiOC、SiCN、SiO2、SiC、ZnO、ZrN、Zr2Al3O9、TiO2、TaO2、ZrO2、HfO2、Si3N4、Y2O3、AlON、TaCN、ZrSi或(多种)其它合适的材料；并且可以通过CVD、PVD、ALD或其它合适的方法来形成。ILD层270可以包括正硅酸四乙酯(TEOS)氧化物、未掺杂硅酸盐玻璃或掺杂氧化硅，诸如硼磷硅酸盐玻璃(BPSG)、氟化物掺杂二氧化硅玻璃(FSG)、磷硅酸盐玻璃(PSG)、硼掺杂硅玻璃(BSG)、低k介电材料、其它合适的介电材料或其组合。可以通过PECVD(等离子体增强CVD)、FCVD(可流动CVD)或其它合适的方法来形成ILD270。
在一些实施例中，硅化物部件273可以包括硅化钛(TiSi)、硅化镍(NiSi)、硅化钨(WSi)、硅化镍-铂(NiPtSi)、硅化镍-铂-锗(NiPtGeSi)、硅化镍-锗(NiGeSi)、硅化镱(YbSi)、硅化铂(PtSi)、硅化铱(IrSi)、硅化铒(ErSi)、硅化钴(CoSi)或其它合适的化合物。
在一种实施例中，S/D接触件275可以包括导电阻挡层和导电阻挡层上的金属填充层。导电阻挡层可以包括钛(Ti)、钽(Ta)、钨(W)、钴(Co)、钌(Ru)或导电氮化物，诸如氮化钛(TiN)、氮化钛铝(TiAlN)、氮化钨(WN)、氮化钽(TaN)或其组合，并且可以通过CVD、PVD、ALD和/或其它合适的工艺来形成。金属填充层可以包括钨(W)、钴(Co)、钼(Mo)、钌(Ru)、镍(Ni)、铜(Cu)或其它金属，并且可以通过CVD、PVD、ALD、电镀或其它合适的工艺来形成。在一些实施例中，在S/D接触件275中省略导电阻挡层。
在一些实施例中，覆盖层356包括La2O3、Al2O3、SiOCN、SiOC、SiCN、SiO2、SiC、ZnO、ZrN、Zr2Al3O9、TiO2、TaO2、ZrO2、HfO2、Si3N4、Y2O3、A1ON、TaCN、ZrSi或(多种)其它合适的材料。覆盖层356保护S/D接触件275免于蚀刻和CMP工艺，并且使S/D接触件275与在其上形成的互连结构隔离。覆盖层356可以具有例如在约3nm到约30nm的范围内的厚度。在一些实施例中，SAC层352和覆盖层356包括不同的材料以例如在形成覆盖层356期间实现蚀刻选择性。
在一种实施例中，S/D接触通孔358可以包括导电阻挡层和导电阻挡层上的金属填充层。导电阻挡层可以包括钛(Ti)、钽(Ta)、钨(W)、钴(Co)、钌(Ru)或导电氮化物，诸如氮化钛(TiN)、氮化钛铝(TiAlN)、氮化钨(WN)、氮化钽(TaN)或其组合，并且可以通过CVD、PVD、ALD和/或其它合适的工艺来形成。金属填充层可以包括钨(W)、钴(Co)、钼(Mo)、钌(Ru)、镍(Ni)、铜(Cu)或其它金属，并且可以通过CVD、PVD、ALD、电镀或其它合适的工艺来形成。在一些实施例中，在S/D接触通孔358中省略导电阻挡层。
在操作104处，方法100(图1A)将器件200倒置翻转并且将器件200的正面附接至载体370，如图3B中所示。这使得器件200可以从器件200的背面接近以进行进一步处理。操作104可以使用任何合适的附接工艺，诸如直接接合、混合接合、使用粘合剂或其它接合方法。操作104还可以包括对准、退火和/或其它工艺。在一些实施例中，载体370可以是硅晶圆。在图2A至图13E中，“z”方向从器件200的背面指向器件200的正面，而“-z”方向从器件200的正面指向器件200的背面。
在操作106处，方法100(图1A)从器件200的背面减薄器件200，直到半导体鳍部204和隔离结构230从器件200的背面被暴露。所得的结构根据一种实施例在图4A至图4E中示出。为了简单起见，图4C、图4D和图4E省略了图4B中已经示出的一些部件，尤其是层277和载体370。减薄工艺可以包括机械研磨工艺和/或化学减薄工艺。在机械研磨工艺期间，可以首先从衬底201去除大量的衬底材料。之后，化学减薄工艺可以向衬底201的背面施加蚀刻化学物，以进一步减薄衬底201。
在操作108处，方法100(图1A)选择性地蚀刻半导体层204，以在栅极堆叠件240和S/D部件260的背面上形成沟槽272。沟槽272从背面暴露S/D部件260的表面。在本实施例中，操作108还在S/D部件260的表面上形成硅化物部件280。所得到的结构根据一种实施例在图5A至图5E中示出。在本实施例中，操作108应用蚀刻工艺，蚀刻工艺被调谐为对半导体层204的材料是选择性的并且对栅极堆叠件240、隔离结构230和B-SAC层203没有(或最小)蚀刻。在本实施例中，蚀刻工艺还蚀刻S/D部件260以使其凹陷到甚至与隔离结构230与CESL269之间的界面一样的水平或在隔离结构230与CESL269之间的界面之下的水平。这是为了准备用于随后的衬垫沉积的沟槽272。在一些实施例中，操作108可以应用多于一种蚀刻工艺。例如，其可以应用第一蚀刻工艺以选择性地去除半导体鳍部204，并且然后应用第二蚀刻工艺以选择性地使S/D部件260凹陷到期望的水平，其中第一和第二蚀刻工艺使用不同的蚀刻参数，诸如使用不同的蚀刻剂。(多种)蚀刻工艺可以是干法蚀刻、湿法蚀刻、反应离子蚀刻或其它蚀刻方法。B-SAC层203保护栅极堆叠件240免受一种或多种蚀刻工艺的影响。在一种实施例中，操作108包括将一种或多种金属沉积到沟槽272中，对器件200执行退火工艺以引起一种或多种金属与S/D部件260之间的反应以产生硅化物部件280，以及去除一种或多种金属的未反应部分，将硅化物部件280留在沟槽272中。一种或多种金属可以包括钛(Ti)、钽(Ta)、钨(W)、镍(Ni)、铂(Pt)、镱(Yb)、铱(Ir)、铒(Er)、钴(Co)或其组合(例如，两种或更多种金属的合金)，并且可以使用CVD、PVD、ALD或其它合适的方法来沉积。硅化物部件280可以包括硅化钛(TiSi)、硅化镍(NiSi)、硅化钨(WSi)、硅化镍-铂(NiPtSi)、硅化镍-铂-锗(NiPtGeSi)、硅化镍-锗(NiGeSi)、硅化镱(YbSi)、硅化铂(PtSi)、硅化铱(IrSi)、硅化铒(ErSi)、硅化钴(CoSi)、其组合或其它合适的化合物。
在操作110处，方法100(图1A)在S/D部件260的背面上，更具体地，在本实施例中，在硅化物部件280上，选择性地沉积抑制剂302。所得的结构根据一种实施例在图6A至图6E中示出。抑制剂302包括有机或有机样膜，膜包括两亲性或两亲性样分子。参见图6B至图6E，在硅化物部件280上沉积抑制剂302，但不在介电层230、203和255上沉积。注意，抑制剂302可以或可以不在S/D部件260和/或硅化物部件280与CESL269和隔离结构230相遇的拐角区域327中接触CESL269和隔离结构230。在一种实施例中，由于硅化物部件280的分子与抑制剂302的分子之间的共价键，抑制剂302沉积在硅化物部件280的表面上。在层230、203和255的介电表面与抑制剂302之间不存在这种共价键。由此，不在这些介电表面上沉积抑制剂302。抑制剂302还具有疏水特性，使得它不可附接至介电材料(即，它排斥介电材料在其上的沉积)，这将参照操作112进一步解释。例如，抑制剂302在一些实施例中可以包括烷基链或羧酸的化合物或在一些实施例中可以具有化学式SHCH2C6H4CH2SH或HS-(CH2)n-COOH。抑制剂302可以使用ALD、PVD、CVD或其它合适的方法来沉积并且可以具有约0.5nm至5nm的厚度(沿着“z”方向)。在本实施例中，抑制剂302仅沉积在选定的表面(即，硅化物部件280的表面)上，而不涉及光刻工艺。由此，操作110是选择性沉积工艺。
在操作112处，方法100(图1A)在结构200的背面上选择性地沉积介电衬垫层304。所得的结构根据一种实施例在图7A至图7E中示出。参见图7A至图7E，在该实施例中，介电衬垫层304被沉积成沿着B-SAC层203、隔离结构230和内部间隔件255的不同表面具有基本均匀的厚度。由于抑制剂302的疏水性质，除了抑制剂302的一些边缘区域(诸如角区域327中的抑制剂302的部分)之外，不在抑制剂302上沉积介电衬垫层304。介电衬垫层304可以或可以不接触抑制剂302的边缘区域。在不同实施例中，介电衬垫层304可以包括La2O3、Al2O3、SiOCN、SiOC、SiCN、SiO2、SiC、ZnO、ZrN、Zr2Al3O9、TiO2、TaO2、ZrO2、HfO2、Si3N4、Y2O3、AlON、TaCN、ZrSi或(多种)其它合适的材料。介电衬垫层304用于隔离稍后将在沟槽272中形成的S/D接触件(背面通孔)(见图12D)。在没有介电衬垫层304的情况下，来自S/D接触件的金属可能随着时间扩散到隔离结构230中，从而导致问题。介电衬垫层304还用于将S/D接触件与附近的栅极堆叠件240隔离。在不同实施例中，介电衬垫层304可以使用ALD、CVD或其它合适的方法来沉积，并且可以具有约1nm至约5nm的厚度(例如，如在B-SAC层203的侧壁上沿着“x”方向测量的)。在本实施例中，介电衬垫层304仅沉积在选定的表面(即，隔离结构230、B-SAC层203和内部间隔件255的表面)上，而不涉及光刻工艺。因此，操作112是选择性沉积工艺。特别地，由于不在抑制剂302上沉积介电衬垫层304，因此不需要用于破坏介电衬垫层304的竖直蚀刻工艺。
在操作114处，方法100(图1B)将抑制剂302从器件200去除，具体地从硅化物部件280的表面去除。所得的结构根据一种实施例在图8A至图8E中示出。参考图8A至图8E，抑制剂302的去除在拐角区域327中产生间隙(或空隙)333。在图8B的截面图中，间隙333直接存在于介电衬垫层304下和S/D部件260和硅化物部件280上，并且暴露内部间隔件255的侧表面的一部分。在图8D和图8E的截面图中，间隙333直接存在于介电衬垫层304下和硅化物部件280上，并且暴露隔离结构230和/或CESL269的侧表面的一部分。在不同实施例中，介电衬垫层304的底表面与硅化物部件280的顶表面之间的距离d2在约0.2nm到约5nm的范围内。距离d2是间隙333的高度。如果距离d2小于0.2nm，则背面S/D接触件(或S/D通孔)(诸如S/D通孔282(见图12D))变得更加难以填充间隙，减小S/D接触件282与S/D部件260(以及硅化物部件280)之间的界面面积，并且增大S/D接触电阻。如果距离d2大于5nm，则在隔离结构230、B-SAC层203和/或内部间隔件255上可能存在未被介电衬垫304充分覆盖的区域，从而导致金属从S/D接触件282扩散到这些介电层中。因此，使距离d2在0.2nm至5nm的范围内实现了在减小S/D接触电阻与改善S/D接触件隔离之间的良好平衡。
在一种实施例中，抑制剂302的去除包括等离子体干法蚀刻工艺、化学干法蚀刻工艺、灰化工艺、湿法蚀刻工艺或其组合。蚀刻和灰化工艺对抑制剂302的材料是选择性的，并且对介电衬垫层304、CESL269、内部间隔件255、隔离结构230、硅化物部件280和S/D部件260没有(或最小)蚀刻。例如，等离子体干法蚀刻工艺可以使用常规的干法蚀刻剂用于介电材料，诸如与H2或O2混合的C4F6，化学干法刻蚀工艺可以使用H2等一种或多种化学物质，灰化工艺可以使用氧或氢灰化，并且湿法刻蚀工艺可以采用热SPM溶液(硫酸和过氧化氢的混合物)，例如，在高于100℃的温度下。
作为操作110、112和114的结果，硅化物部件280的背面表面暴露在沟槽272中，并且介电衬垫层304设置在隔离结构230、B-SAC层203和内部间隔件255的各个表面上。在不使用抑制剂302(即，省略操作110和114)的方法中，介电衬垫层304将不仅沉积在层230、203和255的表面上，而且沉积在硅化物部件280上。为了暴露S/D部件260和/或硅化物部件280以供后续S/D接触件形成，将执行蚀刻工艺以蚀刻介电衬垫层304。有时，为了确保从S/D部件260或硅化物部件280的表面完全去除介电衬垫层304，将执行过蚀刻。过蚀刻可能导致B-SAC层203以及S/D部件260或硅化物部件280的不必要的损失。B-SAC层203的损失或变薄可能导致栅极堆叠件240与背面通孔(诸如图12D中的通孔282)之间的短路。相反，通过使用抑制剂302，根据本实施例的工艺更稳健并且对B-SAC层203的厚度具有更好的控制。此外，由于间隙333的存在，存在更多的用于形成S/D接触件的S/D部件206和硅化物部件280的区域，从而降低了S/D接触电阻。
在操作116处，方法100(图1B)通过一种或多种介电材料沉积介电层276以填充沟槽272。在本实施例中，操作116对介电层276和介电衬垫层304执行CMP工艺以将它们从隔离结构230的顶表面去除。所得的结构根据一种实施例在图9A至图9E中示出。参见图9A至图9E，介电层276沉积在介电衬垫层304和硅化物部件280上，并且填充间隙333。在一些实施例中，介电层276可以包括La2O3、Al2O3、SiOCN、SiOC、SiCN、SiO2、SiC、ZnO、ZrN、Zr2Al3O9、TiO2、TaO2、ZrO2、HfO2、Si3N4、Y2O3、A1ON、TaCN、ZrSi或(多种)其它合适的材料中的一种或多种。此外，在本实施例中，介电层276和介电衬垫304包括不同的材料，以在背面接触孔蚀刻工艺期间实现蚀刻选择性。更进一步地，介电层276和隔离结构230可以包括不同的材料，使得当通过CMP工艺使介电层276平坦化时，隔离结构230可以充当CMP停止件。
在操作118处，方法100(图1B)在结构200的背面上形成蚀刻掩模360。蚀刻掩模360在S/D部件260的背面上设置开口362，开口362将连接至背面通孔。所得的结构根据一种实施例在图10A至图10E中示出。参见图10A至图10E，在所描绘的实施例中，在源极部件260的背面上设置开口362，而漏极部件260和栅极堆叠件240的背面被蚀刻掩模360覆盖。在不同实施例中，开口362可以仅设置在漏极部件的背面上、仅设置在源极部件的背面上或者设置在源极和漏极部件两者的背面上。蚀刻掩模360包括的材料不同于介电层276的材料，以在背面过孔蚀刻期间实现蚀刻选择性。例如，蚀刻掩模360包括抗蚀剂材料(并且因此可以被称为图案化抗蚀剂层和/或图案化光致抗蚀剂层)。在一些实施例中，蚀刻掩模360具有多层结构，诸如设置在抗反射涂布(ARC)层上的抗蚀剂层和/或包括氮化硅或氧化硅的硬掩模层。本公开考虑用于蚀刻掩模360的其它材料，只要在介电层276的蚀刻期间实现蚀刻选择性即可。在一些实施例中，操作118使用光刻工艺，光刻工艺包括在器件200的背面上形成抗蚀剂层(例如，通过旋涂)、执行曝光前烘焙工艺、使用掩模执行曝光工艺、执行曝光后烘焙工艺以及执行显影工艺。在曝光工艺期间，抗蚀剂层暴露于辐射能(例如，UV光、DUV光或EUV光)，其中，取决于掩模的掩模图案和/或掩模类型(例如，二元掩模、相移掩模或EUV掩模)，掩模阻挡、透射和/或反射辐射至抗蚀剂层，使得图像被投射到与掩模图案对应的抗蚀剂层上。由于抗蚀剂层对辐射能量敏感，所以抗蚀剂层的曝光部分化学地改变，并且抗蚀剂层的曝光(或未曝光)部分在显影工艺期间根据抗蚀剂层的特性和在显影工艺中使用的显影液的特性被溶解。在显影之后，被图案化的抗蚀剂层(例如，蚀刻掩模360)包括对应于掩模的抗蚀剂图案。或者，曝光工艺可以由其它方法实施或替代，诸如无掩模光刻、电子束写入、离子束写入或其组合。
在操作120处，方法100(图1B)通过蚀刻掩模360蚀刻介电层276以形成过孔278。随后例如通过抗蚀剂剥离工艺或其它合适的工艺去除蚀刻掩模360。所得的结构根据一种实施例在图11A至图11E中示出。参见图11A至图11E，在所描绘的实施例中，过孔278暴露源极部件260上的硅化物部件280。特别地，间隙333重新出现在过孔278内部的角区域327中。在一种实施例中，蚀刻工艺包括干法(等离子体)蚀刻工艺，干法(等离子体)蚀刻工艺被调谐为选择性地蚀刻介电层276并且对介电衬垫304、隔离结构230、CESL269、内部间隔件255、硅化物部件280和S/D部件260没有(或最小)蚀刻。在替代实施例中，操作120可以使用其它类型的蚀刻(诸如湿法蚀刻或反应离子蚀刻)，只要如上所讨论的实现层之间的蚀刻选择性即可。由于操作120对隔离结构230和介电衬垫304没有蚀刻或具有最小的蚀刻，所以过孔蚀刻在y-z平面中和在x-z平面中与介电衬垫304自对准，从而提高了工艺裕度。
在操作122处，方法100(图1B)在过孔278中形成通孔结构(或通孔或金属插塞)282。所得的结构根据一种实施例在图12A至图12E中示出。参见图12A至图12E，通孔282设置在硅化物部件280上。
在一种实施例中，通孔282可以包括钨(W)、钴(Co)、钼(Mo)、钌(Ru)、铜(Cu)、镍(Ni)、钛(Ti)、钽(Ta)、氮化钛(TiN)、氮化钽(TaN)或其它金属，并且可以通过CVD、PVD、ALD、电镀或其它合适的工艺来形成。操作122可以执行CMP工艺以去除通孔282的过量材料。
在操作124处，方法100(图1B)形成背面电源轨284。所得的结构根据一种实施例在图13A至图13B中示出。如图13B至图13E中所说明的，背面通孔282与背面电源轨284电连接。在一种实施例中，可以使用镶嵌工艺、双镶嵌工艺、金属图案化工艺或其它合适的工艺来形成背面电源轨284。背面电源轨284可以包括钨(W)、钴(Co)、钼(Mo)、钌(Ru)、铜(Cu)、镍(Ni)、钛(Ti)、钽(Ta)、氮化钛(TiN)、氮化钽(TaN)或其它金属，并且可以通过CVD、PVD、ALD、电镀或其它合适的工艺来沉积。尽管图13A至图13E中未示出，但是背面电源轨284嵌入在一个或多个介电层中。具有背面电源轨284有益地增加了器件200中可用于直接连接到源极/漏极接触件和通孔的金属轨道的数量。与没有背面电源轨284的其它结构相比，其也增加了更大的器件集成的栅极密度。背面电源轨284可以具有比器件200的正面上的第一级金属(M0)轨道更宽的尺寸，这有益地降低了背面电源轨电阻。在一种实施例中，背面电源轨284可以具有例如在从约5nm到约40nm的范围内的厚度d1；介电层276可以具有例如在从约3nm到约50nm的范围内的厚度d3；并且B-SAC层203具有在从约0.5nm到约50nm的范围内的厚度d5，如上所讨论的。
在操作126处，方法100(图1B)对器件200执行进一步的制造工艺。例如，其可以在结构200的背面上形成一个或多个互连层，在器件200的背面上形成钝化层，执行其它BEOL工艺，并且去除载体370。
虽然并非旨在进行限制，但本公开的实施例提供了以下优点中的一个或多个。例如，本公开的实施例形成用于背面通孔的衬垫层，其中在过孔的侧壁上选择性地沉积衬垫层，但不在过孔的底部上沉积。这消除了随后在通孔中形成过孔时穿透衬垫的需要，并且有利地降低了将金属栅极与背面通孔短接的风险。此外，本公开的实施例使用自对准工艺形成背面通孔，这最小化了背面通孔短接到包括栅极堆叠件的附近导体的风险。此外，本公开的实施例形成背面电源轨以增加集成电路中可用的金属轨道的数量并且增加用于更大的器件集成的栅极密度。本公开的实施例可以容易地集成到现有半导体制造工艺中。
在一个示例方面中，本公开涉及一种方法，方法包括设置具有正面和背面的结构。结构包括衬底、在衬底上的半导体鳍部、在半导体鳍部上的两个源极/漏极(S/D)部件、在半导体鳍部上的第一介电层、与半导体鳍部的侧壁相邻的隔离结构、在第一介电层上并且连接两个S/D部件的一个或多个沟道半导体层以及接合一个或多个沟道半导体层的栅极结构。衬底在结构的背面处，并且栅极结构在结构的正面处。方法还包括从结构的背面减薄结构直到半导体鳍部被暴露，以及从结构的背面选择性地蚀刻半导体鳍部以形成沟槽。沟槽暴露两个S/D部件的表面、第一介电层的表面和隔离结构的侧壁。方法还包括在S/D部件的表面上形成硅化物部件并在沟槽中选择性地沉积抑制剂。在硅化物部件上沉积抑制剂，但不在第一介电层的表面和隔离结构的侧壁上沉积。方法还包括在沟槽中选择性地沉积介电衬垫层。在隔离结构的侧壁和第一介电层的表面上沉积介电衬垫层，但不在抑制剂上沉积。方法还包括选择性地去除抑制剂。
在一种实施例中，方法还包括：沉积第二介电层以填充沟槽；蚀刻第二介电层以形成过孔，过孔暴露两个S/D部件中的一个S/D部件上的硅化物部件和介电衬垫层；以及在过孔内形成通孔结构。在另一实施例中，在第二介电层的蚀刻之前，方法包括在结构的背面上形成蚀刻掩模。蚀刻掩模在第二介电层的位于两个S/D部件中的一个S/D部件下的部分上提供开口，其中通过开口执行对第二介电层的蚀刻。在另一实施例中，在两个S/D部件中的一个S/D部件与介电衬垫层之间竖直地形成通孔结构的至少一部分。
在方法的一些实施例中，硅化物部件包括硅化钛(TiSi)、硅化镍(NiSi)、硅化钨(WSi)、硅化镍-铂(NiPtSi)、硅化镍-铂-锗(NiPtGeSi)、硅化镍-锗(NiGeSi)、硅化镱(YbSi)、硅化铂(PtSi)、硅化铱(IrSi)、硅化铒(ErSi)、硅化钴(CoSi)或其组合。
在方法的一些实施例中，抑制剂包括具有两亲性分子的有机膜，并且介电衬垫层包括La2O3、Al2O3、SiOCN、SiOC、SiCN、SiO2、SiC、ZnO、ZrN、Zr2Al3O9、TiO2、TaO2、ZrO2、HfO2、Si3N4、Y2O3、AlON、TaCN和ZrSi中的至少一种。
在方法的一些实施例中，抑制剂的选择性去除使用蚀刻工艺，蚀刻工艺被调谐成蚀刻抑制剂，而对介电衬垫层没有蚀刻或具有最小的蚀刻。在另一实施例中，抑制剂的选择性去除包括等离子体干法蚀刻、化学干法蚀刻、灰化、湿法蚀刻或其组合。在另一实施例中，抑制剂的选择性去除包括在超过100℃的温度下使用SPM清洁溶液的湿法蚀刻。
在另一示例方面，本公开涉及一种方法，方法包括：提供一种结构，结构具有衬底、在衬底上的半导体鳍部、在半导体鳍部上的两个源极/漏极(S/D)部件、在半导体鳍部的侧壁上的隔离结构、在半导体鳍部上的介电覆盖层、在介电覆盖层上的一个或多个沟道半导体层以及接合一个或多个沟道半导体层的栅极结构。方法还包括减薄衬底直到半导体鳍部被暴露以及选择性地蚀刻半导体鳍部以形成沟槽。沟槽暴露两个S/D部件的表面、介电覆盖层的表面和隔离结构的侧壁。方法还包括在S/D部件的表面上形成硅化物部件；在硅化物部件上但不在介电覆盖层的表面和隔离结构的侧壁上沉积抑制剂；在隔离结构的侧壁和介电覆盖层的表面上但不在抑制剂上沉积介电衬垫层；选择性地去除抑制剂；以及在沟槽中形成通孔结构。
在一种实施例中，在抑制剂的选择性去除之后并且在通孔结构的形成之前，方法还包括沉积介电层以填充沟槽以及蚀刻介电层以形成过孔。过孔暴露两个S/D部件中的一个S/D部件上的硅化物部件，并且通孔结构形成在过孔中。在另一实施例中，在介电层的蚀刻之前，方法包括在结构的背面上形成蚀刻掩模。蚀刻掩模在介电层的一部分上提供开口，并且通过开口执行介电层的蚀刻。
在方法的一种实施例中，硅化物部件包括硅化钛(TiSi)、硅化镍(NiSi)、硅化钨(WSi)、硅化镍-铂(NiPtSi)、硅化镍-铂-锗(NiPtGeSi)、硅化镍-锗(NiGeSi)、硅化镱(YbSi)、硅化铂(PtSi)、硅化铱(IrSi)、硅化铒(ErSi)和硅化钴(CoSi)或其组合。
在方法的一些实施例中，抑制剂包括具有两亲性分子的有机膜，并且介电衬垫层包括La2O3、Al2O3、SiOCN、SiOC、SiCN、SiO2、SiC、ZnO、ZrN、Zr2Al3O9、TiO2、TaO2、ZrO2、HfO2、Si3N4、Y2O3、AlON、TaCN、和ZrSi中的至少一种。
在方法的一些实施例中，抑制剂的选择性去除包括等离子体干法蚀刻、化学干法蚀刻、灰化、湿法蚀刻或其组合。
在又一示例方面中，本公开涉及一种半导体结构。半导体结构包括：两个源极/漏极(S/D)部件；连接两个S/D部件的一个或多个沟道半导体层；以及接合一个或多个沟道半导体层的栅极结构。两个S/D部件、一个或多个沟道半导体层和栅极结构在半导体结构的正面处。半导体结构还包括在半导体结构的背面处的金属轨道；在金属轨道与一个或多个沟道半导体层之间的第一介电层；在第一介电层的表面上且通过第一间隙与两个S/D部件中的一个S/D部件间隔开的介电衬垫层；以及将金属轨道与两个S/D部件中的一个S/D部件连接的通孔结构，其中，通孔结构的一部分被设置在第一间隙中。
在半导体结构的一种实施例中，介电衬垫层通过第二间隙与两个S/D部件中的另一个S/D部件间隔开。在另一实施例中，半导体结构包括在介电衬垫层上的第二介电层，其中第二介电层的一部分从金属轨道延伸至两个S/D部件中的另一个S/D部件并填充第二间隙。
在一种实施例中，半导体结构还包括在通孔结构与两个S/D部件中的一个S/D部件之间的硅化物部件。在另一实施例中，半导体结构还包括在介电衬垫层上且在第一介电层与金属轨道之间的第二介电层。
上述概述了几个实施例的特征，以便本领域技术人员可以更好地理解本公开的各个方面。本领域普通技术人员应当理解，他们可以容易地使用本公开作为设计或修改用于实现本文所介绍的实施例的相同目的和/或实现其相同优点的其它过程和结构的基础。本领域普通技术人员还应当认识到，此类等效结构不背离本公开的精神和范围，并且它们可以在不背离本公开的精神和范围的情况下在本公开中进行各种改变、替换以及改变。

Claims (20)

1.一种形成半导体结构的方法，包括：
提供一种结构，具有正面和背面，所述结构包括衬底、在所述衬底上的半导体鳍部、在所述半导体鳍部上的两个源极/漏极部件、在所述半导体鳍部上的第一介电层、与所述半导体鳍部的侧壁相邻的隔离结构、在所述第一介电层上并且连接所述两个源极/漏极部件的一个或多个沟道半导体层以及接合所述一个或多个沟道半导体层的栅极结构，其中，所述衬底在所述结构的背面处并且所述栅极结构在所述结构的所述正面处；
从所述结构的所述背面减薄所述结构直到所述半导体鳍部被暴露；
从所述结构的所述背面选择性地蚀刻所述半导体鳍部以形成沟槽，其中，所述沟槽暴露所述两个源极/漏极部件的表面、所述第一介电层的表面和所述隔离结构的侧壁；
在所述源极/漏极部件的所述表面上形成硅化物部件；
在所述沟槽中选择性地沉积抑制剂，其中，所述抑制剂沉积在所述硅化物部件上，但不在所述第一介电层的所述表面和所述隔离结构的所述侧壁上沉积；
在所述沟槽中选择性地沉积介电衬垫层，其中，所述介电衬垫层沉积在所述隔离结构的侧壁和所述第一介电层的所述表面上，但不在所述抑制剂上沉积；以及
选择性地去除所述抑制剂。
2.根据权利要求1的方法，还包括：
沉积第二介电层以填充所述沟槽；
蚀刻所述第二介电层以形成通孔，所述通孔暴露所述两个源极/漏极部件中的一个源极/漏极部件上的所述硅化物部件和所述介电衬垫层；以及
在所述通孔内形成通孔结构。
3.根据权利要求2的方法，在所述第二介电层的所述蚀刻之前，还包括：
在所述结构的所述背面上形成蚀刻掩模，所述蚀刻掩模在所述第二介电层的在所述两个源极/漏极部件中的一个源极/漏极部件下面的部分上提供开口，其中，通过所述开口进行对所述第二介电层的所述蚀刻。
4.根据权利要求2的方法，其中，在所述两个源极/漏极部件中的一个源极/漏极部件与所述介电衬垫层之间竖直地形成所述通孔结构的至少一部分。
5.根据权利要求1的方法，其中，所述硅化物部件包括硅化钛(TiSi)、硅化镍(NiSi)、硅化钨(WSi)、硅化镍-铂(NiPtSi)、硅化镍-铂-锗(NiPtGeSi)、硅化镍-锗(NiGeSi)、硅化镱(YbSi)、硅化铂(PtSi)、硅化铱(IrSi)、硅化铒(ErSi)、硅化钴(CoSi)或其组合。
6.根据权利要求1的方法，其中，所述抑制剂包括具有两亲性分子的有机膜，并且所述介电衬垫层包括La2O3、Al2O3、SiOCN、SiOC、SiCN、SiO2、SiC、ZnO、ZrN、Zr2Al3O9、TiO2、TaO2、ZrO2、HfO2、Si3N4、Y2O3、AlON、TaCN和ZrSi中的至少一种。
7.根据权利要求1的方法，其中，所述抑制剂的所述选择性去除使用蚀刻工艺，所述蚀刻工艺被调谐成蚀刻所述抑制剂，而对所述介电衬垫层没有蚀刻或具有最小的蚀刻。
8.根据权利要求7的方法，其中，所述抑制剂的所述选择性去除包括等离子体干法蚀刻、化学干法蚀刻、灰化、湿法蚀刻或其组合。
9.根据权利要求7的方法，其中，所述抑制剂的所述选择性去除包括在超过100℃的温度下使用SPM清洁溶液的湿法蚀刻。
10.一种形成半导体结构的方法，包括：
提供一种结构，具有衬底、在所述衬底上的半导体鳍部、在所述半导体鳍部上的两个源极/漏极部件、在所述半导体鳍部的侧壁上的隔离结构、在所述半导体鳍部上的介电覆盖层、在所述介电覆盖层上的一个或多个沟道半导体层以及接合所述一个或多个沟道半导体层的栅极结构；
减薄所述衬底直到所述半导体鳍部被暴露；
选择性地蚀刻所述半导体鳍部以形成沟槽，其中，所述沟槽暴露所述两个源极/漏极部件的表面、所述介电覆盖层的表面和所述隔离结构的侧壁；
在所述源极/漏极部件的所述表面上形成硅化物部件；
在所述硅化物部件上但不在所述介电覆盖层的所述表面和所述隔离结构的所述侧壁上沉积抑制剂；
在所述隔离结构的所述侧壁和所述介电覆盖层的所述表面上但不在所述抑制剂上沉积介电衬垫层；
选择性地去除所述抑制剂；以及
在所述沟槽中形成通孔结构。
11.根据权利要求10的方法，在所述抑制剂的所述选择性去除和所述通孔结构的所述形成之前，还包括：
沉积介电层以填充所述沟槽；以及
蚀刻所述介电层以形成通孔，所述通孔暴露所述两个源极/漏极部件中的一个源极/漏极部件上的所述硅化物，其中，在所述通孔中形成所述通孔结构。
12.根据权利要求11的方法，在所述介电层的所述蚀刻之前，还包括：
在所述结构的背面上形成蚀刻掩模，所述蚀刻掩模在所述介电层的一部分上设置开口，其中，通过所述开口进行所述介电层的所述蚀刻。
13.根据权利要求10的方法，其中，所述硅化物部件包括硅化钛(TiSi)、硅化镍(NiSi)、硅化钨(WSi)、硅化镍-铂(NiPtSi)、硅化镍-铂-锗(NiPtGeSi)、硅化镍-锗(NiGeSi)、硅化镱(YbSi)、硅化铂(PtSi)、硅化铱(IrSi)、硅化铒(ErSi)、硅化钴(CoSi)或其组合。
14.根据权利要求10的方法，其中，所述抑制剂包括具有两亲性分子的有机膜，并且所述介电衬垫层包括La2O3、Al2O3、SiOCN、SiOC、SiCN、SiO2、SiC、ZnO、ZrN、Zr2Al3O9、TiO2、TaO2、ZrO2、HfO2、Si3N4、Y2O3、AlON、TaCN和ZrSi中的至少一种。
15.根据权利要求10的方法，其中，所述抑制剂的所述选择性去除包括等离子体干法蚀刻、化学干法蚀刻、灰化、湿法蚀刻或其组合。
16.一种半导体结构，包括：
两个源极/漏极部件；
连接所述两个源极/漏极部件的一个或多个沟道半导体层；
接合一个或多个沟道半导体层的栅极结构，其中，所述两个源极/漏极部件、所述一个或多个沟道半导体层和所述栅极结构在所述半导体结构的正面处；
在所述半导体结构的背面处的金属轨道；
在所述金属轨道与所述一个或多个沟道半导体层之间的第一介电层；
在所述第一介电层的表面上且通过第一间隙与所述两个源极/漏极部件中的一个源极/漏极部件间隔开的介电衬垫层；以及
将所述金属轨道与所述两个源极/漏极部件中的一个源极/漏极部件连接的通孔结构，其中，所述通孔结构的一部分被设置在所述第一间隙中。
17.根据权利要求16所述的半导体结构，其中，所述介电衬垫层通过第二间隙与所述两个源极/漏极部件中的另一个源极/漏极部件间隔开。
18.根据权利要求17所述的半导体结构，还包括：
所述介电衬垫层上的第二介电层，其中，所述第二介电层的一部分从所述金属轨道延伸至所述两个源极/漏极部件中的另一个源极/漏极部件并填充所述第二间隙。
19.根据权利要求16所述的半导体结构，还包括在所述通孔结构与所述两个源极/漏极部件中的一个源极/漏极部件之间的硅化物部件。
20.根据权利要求16所述的半导体结构，还包括在所述介电衬垫层上并且在所述第一介电层与所述金属轨道之间的第二介电层。
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