TWI761466B - 含鈷合金之半導體裝置及其製造方法 - Google Patents

含鈷合金之半導體裝置及其製造方法 Download PDF

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TWI761466B
TWI761466B TW107108173A TW107108173A TWI761466B TW I761466 B TWI761466 B TW I761466B TW 107108173 A TW107108173 A TW 107108173A TW 107108173 A TW107108173 A TW 107108173A TW I761466 B TWI761466 B TW I761466B
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barrier layer
cobalt
contact
semiconductor device
layer
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TW107108173A
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TW201926620A (zh
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小池淳一
雷莎 亞哈汎尼
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國立大學法人東北大學
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Abstract

一種半導體裝置，其包括基板、包含鈷或銅且電連接至該基板之導電佈線、將該導電佈線與鄰近佈線電隔離之絕緣材料及包含第一鈷合金且安置於該導電佈線與該絕緣材料之間的第一障壁層。

Description

含鈷合金之半導體裝置及其製造方法
本發明大體上係關於半導體裝置及其製造方法，且更特定言之，係關於利用鈷基金屬合金之新系列裝置及其製造方法。
在邏輯技術中，三維(3-D)三閘或鰭式場效電晶體(Fin Field-Effect Transistor，FinFET)之優良電氣效能已允許在製造中將邏輯技術縮放至10 nm節點，在開發中縮放至7-5 nm節點，及在研究及開發中縮放至3 nm節點。基於FinFET之處理器及裝置以22 nm與14 nm節點技術生產。在10 nm節點技術下，歸因於電晶體及互連線尺寸之急劇縮放，報導之晶粒面積約為7.6 mm2 。此類急劇幾何縮放對技術節點之進一步縮放產生兩個瓶頸：(1)金屬化加工後段製程(BEOL)及中段製程(MOL)互連線及垂直互連通道(通孔(VIA或通孔))之電阻顯著提高，由此增加電線或電路之電阻-電容(RC)信號延遲；及(2)電晶體非本徵電阻(亦稱作R-外部)顯著提高，其中存取電晶體係電阻性的。因此，在急劇微型化之裝置中需要低電阻接觸通孔。
為滿足上文所提及之需要，提供各種實施例，包括以下。 第一實施例係一種半導體裝置，其包含： 基板； 導電佈線，其包含鈷或銅且電連接至該基板； 絕緣材料，其將該導電佈線與鄰近佈線電隔離；及 第一障壁層，其包含第一鈷合金且安置於該導電佈線與該絕緣材料之間。 第二實施例係根據第一實施例之半導體裝置，其中該導電佈線包含鈷。 第三實施例係根據第二實施例之半導體裝置，其進一步包含第二障壁層，該第二障壁層包括第二鈷合金且安置於該導電佈線與該基板之間。 第四實施例係根據第二實施例之半導體裝置，其中該鈷合金包含鈷及鉿(Hf)、鉭(Ta)及鈦(Ti)中之至少一種。 第五實施例係根據第二實施例之半導體裝置，其中該第一障壁層及該第二障壁層中之至少一種包含非晶形結構。 第六實施例係根據第二實施例之半導體裝置，其中該第一障壁層及該第二障壁層中之至少一種進一步包含矽(Si)、碳(C)、氮(N)及氧(O)中之至少一種。 第七實施例係根據第二實施例之半導體裝置，其中： 該第一障壁層包含鉿(Hf)、鉭(Ta)及鈦(Ti)中之至少一種及矽(Si)、碳(C)、氮(N)及氧(O)中之至少一種，及 該第二障壁層包含鈷及矽、SiGe、SiC及InGaAs中之至少一種。 第八實施例係根據第二實施例之半導體裝置，其中該第一障壁層由具有結晶結構且與該基板具有外延結晶關係之矽化鈷形成。 第九實施例係根據第二實施例之半導體裝置，其中該第一障壁層之厚度在1 nm至30 nm之範圍內。 第十實施例係根據第二實施例之半導體裝置，其中該第二障壁層包含氧化鉿、氧化鉭及氧化鈦中之至少一種且具有非晶形結構。 第十一實施例係根據第二實施例之半導體裝置，其中該第二障壁層之厚度在0.5 nm至5 nm之範圍內。 第十二實施例係根據第二實施例之半導體裝置，其中該第二障壁層進一步包含碳及氮。 第十三實施例係一種平面電晶體，其包含第二實施例之半導體裝置且包括源極接觸及汲極接觸，其中該源極接觸及該汲極接觸各自包含該半導體裝置之該導電佈線及該第一障壁層。 第十四實施例係一種FinFET電晶體，其包含第三實施例之半導體裝置且包括源極接觸及汲極接觸，其中該源極接觸及該汲極接觸各自包含該半導體裝置之該導電佈線及該第一障壁層。 第十五實施例係一種3-D V-NAND記憶體裝置，其包含第二實施例之半導體裝置且包括： 選擇閘極， 字線階梯式接觸，及 源極線接觸， 其中該選擇閘極、字線階梯式接觸及源極線接觸各自包含該半導體裝置之該導電佈線及該第一障壁層。 第十六實施例係一種形成用於第二實施例之半導體裝置之半導體金屬化互連件的方法，其包含： 形成至少一種鈷含量在30%至99%範圍內之鈷合金；及 在局部互連(Local-Inter-Connect)蝕刻或局部互連清潔之後將該至少一種鈷合金沈積至源極區及汲極區上以充當金氧半導體場效電晶體(Metal-Oxide-Semiconductor Field Effect Transistor，MOSFET)之源極區及汲極區之低電阻金屬接觸， 其中該源極區及該汲極區包含Si、Ge、SiGe、SiC及III-V類半導體中之至少一種， 其中Co-Ti合金中之Ti與該源極區及該汲極區之原子相互作用形成擴散障壁以阻斷金屬隨後滲透進入該源極區及該汲極區，及 其中降低基本金屬-半導體接面肖特基(Schottky)障壁之高度以降低對MOSFET之通道至該接觸或該局部互連之電流的基本金屬-半導體接面肖特基障壁。 第十七實施例係根據第十六實施例之方法，其中該至少一種鈷合金包含鉿(Hf)、鉭(Ta)及鈦(Ti)中之至少一種。 第十八實施例係一種半導體裝置，其為三維垂直反及(three-dimensional Vertical-NOT-AND，3-D V-NAND)或動態隨機存取記憶體(Dynamic Random Access Memory，DRAM)且包含藉由第十六實施例之方法製造之前段製程(FEOL)、中段製程(MOL)及後段製程(BEOL)半導體金屬化互連件中的至少一種。 第十九實施例係一種控制用於第二實施例之半導體裝置的半導體金屬化互連件之功函數的方法，其包含： 將至少一種鈷合金沈積至NMOS電晶體之閘極介電層上，其中該至少一種鈷合金充當該NMOS電晶體之功函數閘電極； 將至少一種鈷合金沈積至PMOS電晶體之閘極介電層上，其中該至少一種鈷合金充當該PMOS電晶體之功函數閘電極；及 將至少一種鈷合金以內襯形式沈積至該等功函數閘電極中之各者上以包圍核心空間且以鈷填充該核心空間，形成包括填充有鈷之該核心及該內襯之該半導體金屬化互連件， 其中該半導體金屬化互連件之該功函數經控制為在4.2 eV至5.2 eV之範圍內的值。 第二十實施例係第十九實施例之方法，其中該鈷合金包含鉿(Hf)、鉭(Ta)及鈦(Ti)中之至少一種。 本發明概念之一些實例實施例藉由提供適應不同類型之半導體裝置的用於互連件之鈷基金屬合金內襯之設計解決上述習知技術之缺點。在一些實例實施例中，鈷填充在該等金屬內襯形成之後進行。在一些實例實施例中，銅填充在該等金屬內襯形成之後進行。 在一些實例實施例中，製造一種具有改進電學性質(諸如速度、存取時間及較低功率)之新裝置，其用於在動態隨機存取記憶體(DRAM)、三維垂直反及(3-D V-NAND)記憶體及金氧半導體場效電晶體(MOSFET)中之微電子應用。 在一些實例實施例中，揭示一種包含基板及導電佈線之半導體裝置。該導電佈線包含鈷且電連接至該基板。絕緣層將該導電佈線與鄰近佈線電隔離，且包含第一鈷合金之第一障壁層安置於該導電佈線與該絕緣層之間。 在一些實例實施例中，該半導體裝置進一步包含第二障壁層，該第二障壁層包含第二鈷合金。該第二障壁層安置於該導電佈線與該基板之間。 在一些實例實施例中，該鈷合金包含鈷及由鉿(Hf)、鉭(Ta)及鈦(Ti)組成之群中之至少一種。在一些實例實施例中，該第一障壁層及該第二障壁層中之至少一種包含非晶形結構。在一些實例實施例中，該第一障壁層及該第二障壁層中之至少一種進一步包含矽(Si)、碳(C)、氮(N)及氧(O)中之至少一種。在一些實例實施例中，該第一障壁層包含由鉿(Hf)、鉭(Ta)及鈦(Ti)組成之群中之至少一種及由組成矽(Si)、碳(C)、氮(N)及氧(O)之群中之至少一種。在一些實例實施例中，該第二障壁層包含鈷及由矽、SiGe、SiC及InGaAs組成之群中之至少一種。 在一些實例實施例中，該第一障壁層由具有結晶結構且與該基板具有外延結晶關係之矽化鈷形成。在一些實例實施例中，該第一障壁層之厚度在1 nm至30 nm之範圍內。在一些實例實施例中，該第二障壁層包含氧化鉿、氧化鉭及氧化鈦中之至少一種且具有非晶形結構。在一些實例實施例中，該第二障壁層之厚度在0.5 nm至5 nm之範圍內。在一些實例實施例中，該第二障壁層進一步包含碳及氮。 在一些實例實施例中，該半導體裝置係包括源極接觸及汲極接觸之平面電晶體。在一些實例實施例中，該半導體裝置係包括源極接觸及汲極接觸之FinFET電晶體。在一些實例實施例中，該半導體裝置係包括選擇閘極、字線階梯式接觸及源極線接觸之3-D V-NAND記憶體裝置。 在一些實例實施例中，揭示一種形成半導體裝置之方法。該方法包含以下加工步驟：形成至少一種鈷組成在30%至99%範圍內之鈷合金，且在局部互連蝕刻或局部互連清潔之後將該至少一種鈷合金沈積至源極區及汲極區上以充當MOSFET之源極區及汲極區之低電阻金屬接觸。在一些實例實施例中，該源極區及該汲極區包含Si、Ge、SiGe、SiC及III-V類半導體中之至少一種。 在一些實例實施例中，該至少一種鈷合金包含Co-Ti合金。Co-Ti合金中之Ti與該源極區及該汲極區之原子相互作用形成擴散障壁以阻斷金屬隨後滲透進入該源極區及該汲極區。在一些實例實施例中，降低基本金屬-半導體接面肖特基障壁之高度以降低對MOSFET之通道至該接觸或該局部互連之電流的基本金屬-半導體接面肖特基障壁。 在一些實例實施例中，該至少一種鈷合金包含鉿(Hf)、鉭(Ta)及鈦(Ti)中之至少一種。在一些實例實施例中，該方法用於製造FinFET、3-D V-NAND或DRAM之前段製程(FEOL)、中段製程(MOL)及後段製程(BEOL)半導體金屬化互連件中之至少一種。 在一些實例實施例中，揭示一種控制半導體金屬化互連件之功函數之方法。該方法包含將至少一種鈷合金沈積至NMOS電晶體之閘極介電層上之加工步驟。該至少一種鈷合金充當該NMOS電晶體之功函數閘電極。該方法進一步包含將至少一種鈷合金沈積至PMOS電晶體之閘極介電層上之步驟。該至少一種鈷合金充當該PMOS電晶體之功函數閘電極。該方法進一步包含將至少一種鈷合金以內襯形式沈積至該等功函數閘電極中之各者上以包圍核心空間且以鈷填充該核心空間，形成包括該以鈷填充之核心及該內襯之該半導體金屬化互連件的步驟。該半導體金屬化互連件之功函數經控制為在4.2 eV至5.2 eV之範圍內的值。在一實例實施例中，該鈷合金包含鉿(Hf)、鉭(Ta)及鈦(Ti)中之至少一種。在一實例實施例中，該方法用於製造FinFET、3-D V-NAND或DRAM金屬化互連件。 根據以下本發明之各種態樣之詳細描述結合參考圖式，本發明之目標、特徵及優點將顯而易知。以下主題以詳細解釋之各種特定實例實施例之方式教示且在圖式中說明。
本發明係關於在半導體工業晶圓加工中利用新系列金屬合金之新系列裝置。提供以下說明書以使得一般技術者能夠製造及使用本發明且將其併入特定應用之上下文中。各種修改以及在不同應用中之各種用途將對熟習此項技術者而言為顯而易見的，且本文所定義之一般原理可應用於廣泛範圍之實施例。因此，本發明並不意欲限於本文中所呈現之實施例，而應符合與本文中所揭示之原理及新穎特徵相一致的最廣泛範疇。 一種具有改進驅動電流、存取時間及降低之功率消耗的裝置可藉由減少設計為接入其之接觸及線路電阻而實現。舉例而言，靜態隨機存取記憶體(SRAM)係在邏輯技術中定義「0」及「1」之依電性(當外加功率斷開時抹除資料)通用資料儲存單元。典型的SRAM由用局部互連(LIC)金屬化連線在一起之六個電晶體組成。存取單個電晶體係經由通孔與閘極之接觸、與源極之接觸、與汲極之接觸及與基板之接觸。形成SRAM電路之電晶體存取接觸及局部互連佈線之電阻直接決定電路之最終效能。大體而言，在FEOL中此電阻由電晶體存取接觸定義且在MOL中由局部互連佈線定義。在FEOL/MOL中當前金屬化技術包括高電阻鈦、氮化鈦、接著較低電阻鎢之沈積(Ti/TiN/W)。在一些情況下最小間距BEOL金屬線之電阻顯著促進電晶體存取。在BEOL最小間距金屬線中當前金屬化技術包括高電阻氮化鉭(TaN)、鉭(Ta)及較低電阻銅填充物(TaN/Ta/Cu)。 在FEOL及MOL低於14 nm邏輯技術節點中，接觸之閘極間距小至60 nm，具有小於15 nm之接觸臨界尺寸(CD)。由此小接觸孔/溝槽體積使得高電阻Ti及TiN決定最終接觸之電阻率(其佔據較大接觸孔/溝槽體積)而非W填充物部分(其佔據較小接觸孔/溝槽體積)。類似地，在BEOL中通孔及前幾個金屬層具有小至50 nm之間距及小於15 nm之CD。由此小通孔/溝槽金屬孔體積使得高電阻TaN及Ta最終決定金屬電阻率(其佔據較大通孔/金屬孔/溝槽體積)而非Cu填充物(其佔據較小通孔/溝槽體積)。 可經優化以降低此等電阻之多個關鍵因素包括(但不限於)以下： 界面電阻-一般而言金屬界面與半導體界面形成電流之障壁，稱作肖特基障壁。此障壁之高度取決於金屬及半導體之特性。 金屬內襯電阻-在微電子應用中通常使用之金屬(鎢及銅)為求黏著及擴散特性而需要內襯金屬。在鎢之情況下內襯金屬為高電阻Ti/TiN且在銅之情況下為高電阻TaN/Ta。在低於14 nm節點邏輯技術中此等金屬決定接觸/通孔/線之淨電阻，因為其佔據孔/溝槽之大部分體積。 塊體金屬填充物電阻-在內襯金屬(一般而言其具有高電阻)後之空白空間以較低電阻金屬填充。在FEOL及MOL中，此主導金屬為鎢且在BEOL中其為銅。然而，在間距極小之技術中(例如低於14 nm節點邏輯節點)，孔/溝槽之大部分體積由高電阻內襯金屬佔據。 圖1展示相關技術之MOSFET沿源極-汲極方向，亦即y 方向之橫截面圖。出於說明之目的，展示平面電晶體。圖1之平面電晶體包括基板100、閘極介電層110、閘電極或閘金屬120、源極區130a及汲極區130b、側壁間隔物140、第二障壁層150、第一障壁層160及接觸170。第二障壁層150接觸源極區130a或汲極區130b。第一障壁層160將接觸170與閘電極120分隔。接觸170由絕緣材料層180彼此電隔離。第一障壁層160安置於導電佈線170與絕緣材料層180之間。金屬化方法包括在平面電晶體之源極區或汲極區上之通孔中形成Ti/TiN高電阻率金屬內襯。此電阻率可高達100 µW-cm。內襯形成之後為使用鎢填充由內襯包圍之空間之製程，該空間接觸平面電晶體之源極區或汲極區。 在一些相關技術中，閘電極亦由鎢形成。儘管鎢電阻率為大約8 µW-cm，但通孔之大部分體積由具有內襯厚度D之高電阻Ti/TiN金屬填充，且接觸170之鎢並不佔據通孔之大部分體積。此係因為在低於22 nm邏輯技術節點中源極區或汲極區上接觸區之臨界尺寸(CD)低至10 nm。內襯160亦稱作第一障壁層，其用以避免金屬自接觸170擴散進入絕緣材料層180而形成漏電流路徑或簡單地使裝置短路，造成故障發生。 此金屬化方案整體上提供高電阻互連件，阻礙理想的裝置效能。圖1中之平面裝置之高至不可接受的淨電阻歸因於在通孔之大部分體積中占主導之內襯金屬的高電阻，且此示於以下等式(1)中。
Figure 02_image001
…等式(1) 其中： R(當前技術)=接觸孔或溝槽至MOSFET源極及汲極之近似總電阻。 R(界面)=由第一金屬接觸(在此情況下Ti)與MOSFET之源極及汲極之大量摻雜凹穴產生的電阻。此電阻通常稱為肖特基障壁。 R(障壁(Ti+TiN))=在接觸孔/溝槽之底部及側壁內襯之Ti+TiN電阻。 R(W填充物)=填充接觸孔/溝槽之鎢之電阻。 在相關技術中，由於R(障壁(Ti+TiN))比R(W填充物)大得多，因此障壁電阻在整個電阻中占主導。 圖2顯示根據一些實例實施例之MOSFET沿源極-汲極方向，亦即y 方向之橫截面圖。出於說明之目的，展示平面電晶體。圖2之平面電晶體包括基板200、閘極介電層210、閘電極或閘金屬220、源極區230a及汲極區230b、側壁間隔物240、第二障壁層250、第一障壁層260及接觸或導電佈線270。第二障壁層250安置於基板200與接觸270之間。在一些實施例中第二障壁層250接觸源極區230a或汲極區230b。第一障壁層260將接觸270與閘電極220分隔。接觸270由絕緣材料層280彼此電隔離。 基板200可包括單晶半導體材料，諸如但不限於Si、Ge、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb及InP。在一些實例實施例中，基板200由晶態矽組成。 閘極介電層210形成於基板200上且包含高k介電材料，該高k介電材料包括HfO2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化鋯、氧化鋁、氧化鈦、二氧化鉿-氧化鋁(HfO2 -Al2 O3 )合金、其他合適高k介電材料及/或其組合。在一些實例實施例中，閘極介電層210包括形成於基板200之通道層與閘極介電層210之介電材料之間的界面層(未圖示)。 閘電極220包含一或多層導電材料，諸如多晶矽、鋁、銅、鈦、鉭、鎢、鈷、鉬、氮化鉭、矽化鎳、矽化鈷、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金屬合金、其他合適材料及/或其組合。閘電極220在藉由使用離子植入或原位沈積之方法摻雜形成源極區230a/汲極區230b期間用作光罩。 側壁間隔物240包含Si3 N4 、SiON、SiCN、SiCO、SiOCN或任何其他合適介電材料中之一或多種。側壁間隔物240之厚度在約5 nm至約20 nm之範圍內。 第二障壁層250形成於源極區230a或汲極區230b上。第二障壁層250包含鈷合金且安置於導電佈線270與基板200之間。在一些實例實施例中，第二障壁層250係視情況選用的。 第一障壁層或內襯260包含由鉿(Hf)、鉭(Ta)及鈦(Ti)組成之群中之至少一種及由矽(Si)、碳(C)、氮(N)及氧(O)組成之群中之至少一種。在一些實例實施例中，第一障壁層260包括鈷合金。在一些實例實施例中，第一障壁層260具有非晶形結構。通孔(未圖示)形成於源極區230a或汲極區230b上。第一障壁層260形成於通孔之內表面上以包圍空間。第一障壁層260安置於接觸270與絕緣材料層280之間。 在一些實施例中，第一障壁層260由超薄(厚度小於2 nm)鈷合金層形成作為低電阻內襯且電阻率可低至10 µW-cm。第一障壁層260形成之後為使用塊體鈷填充由第一障壁層260包圍之空間，用於與源極區230a或汲極區230b接觸。在一實例實施例中，閘電極220自身亦為鈷基。與在圖1中之相關技術中的接觸170中之鎢相比，在接觸270中之鈷具有大約8 µW-cm之電阻率且佔據通孔之大部分體積。此金屬化方案整體上提供較低電阻之互連件且顯著改善裝置效能。 在一些實例實施例中，鈷合金內襯或第一障壁層260及/或在接觸270中之鈷金屬藉由物理氣相沈積(Physical Vapor Deposition，PVD)、化學氣相沈積(Chemical Vapor Deposition，CVD)、金屬-有機化學氣相沈積(Metal-Organic Chemical Vapor Deposition，MOCVD)、原子層沈積(Atomic Layer Deposition，ALD)或此等技術之組合及變化形式沈積。然而，用於形成鈷內襯及/或鈷金屬之方法之選擇不限於上述沈積法。使用任何其他類型薄膜沈積法用於鈷合金內襯及鈷金屬填充均在本發明概念內。 根據以下導出之第一主要計算，圖2之實施例之益處係明顯的：在圖2之實施例中金屬之淨電阻顯著小於圖1中之實施例中金屬之淨電阻(如以下等式暗示)，此係由於在通孔體積中占主導之高電阻內襯或障壁金屬的消除。等式2顯示：
Figure 02_image003
…等式(2) 其中： R(所提出之技術)=接觸孔或溝槽至MOSFET之源極及汲極之近似總電阻。 R(界面)=由第一金屬接觸(在此情況下Co-Ti)與MOSFET之源極區及汲極區之大量摻雜凹穴產生之電阻。此電阻通常稱為肖特基障壁。圖2之實施例顯著降低對電流之此肖特基障壁。此界面電阻率由等式(3)給出：
Figure 02_image007
…等式(3) R(障壁(Co合金))=在接觸孔/溝槽底部及側壁內襯之Co合金電阻。 R(Co填充物)=填充接觸孔/溝槽之鈷的電阻。 此淨電阻改善直接轉化成在邏輯及記憶體產品中電路之RC延遲之改善。 基於以上推導，在半導體裝置中，由鈷(Co)組成之導電佈線270由絕緣材料層280與鄰近佈線電隔離且電連接至由例如矽(Si)、SiGe、SiC或InGaAs構成之半導體基板200。在導電佈線270與絕緣體材料層280之間的第一界面及在導電佈線270與半導體基板200之間的第二界面處存在由包括Hf、Ta及Ti中之至少一種元素之Co合金構成的障壁層(亦即第一障壁層260及第二障壁層250)。第二障壁層250及第一障壁層260具有非晶形結構且進一步由來自矽(Si)、碳(C)、氮(N)及氧(O)中之至少一種元素組成。在一些實例實施例中，第一障壁層260及第二障壁層250具有相同結構及組成。在一些實例實施例中，第一障壁層260及第二障壁層250不具有相同組成。 在一些實例實施例中，在佈線270與基板200之間的第二界面處之第二障壁層250由兩個層(未圖示)組成。與基板接觸之第一層由Co及半導體(諸如SiGe、SiC或InGaAs)構成且與導電佈線270接觸之第二層由來自Hf、Ta及Ti之第一組之至少一種元素及來自C、N及O之至少一種元素構成。第一層係矽化鈷，其具有結晶結構且與半導體基板200具有外延結晶關係，且其厚度在1 nm至30 nm之範圍內。第二層由氧化鉿、氧化鉭或氧化鈦組成且具有非晶形結構，厚度在0.5 nm至5 nm之範圍內。第二層進一步含有C及N。 具有Co之導電佈線270及在其與絕緣材料層280之界面處包圍導電佈線270之第一障壁層260可於MOSFET之源極/汲極、電極及局部互連或最小間距金屬線中實施以降低電路之RC延遲。在DRAM與3-D V-NAND中此障壁與金屬之堆疊將減少裝置存取時間且因此改善其讀取及寫入特性。 圖3展示根據一些實例實施例之具有FinFET結構之MOSFET沿源極-汲極方向，亦即y 方向的橫截面圖。圖3之FinFET包括基板或鰭片300、閘極介電層310、閘電極或閘金屬320、源極區330a及汲極區330b、側壁間隔物340、第二障壁層350、第一障壁層360及接觸或導電佈線370。第二障壁層350安置於基板或鰭片300與接觸370之間。在一些實施例中，第二障壁層350接觸源極區330a或汲極區330b。第一障壁層360將接觸370與閘電極320分隔。 基板或鰭片300可包括單晶半導體材料，諸如但不限於Si、Ge、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb及InP。在一些實例實施例中，基板或鰭片300由晶態矽組成。 閘極介電層310形成於基板或鰭片300上且包括高k介電材料，該高k介電材料包括HfO2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化鋯、氧化鋁、氧化鈦、二氧化鉿-氧化鋁(HfO2 -Al2 O3 )合金、其他合適高k介電材料及/或其組合。在一些實例實施例中，閘極介電層310包括形成於基板或鰭片300之通道層與閘極介電層310之介電材料之間的界面層(未圖示)。 閘電極320包含一或多層導電材料，諸如多晶矽、鋁、銅、鈦、鉭、鎢、鈷、鉬、氮化鉭、矽化鎳、矽化鈷、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金屬合金、其他合適材料及/或其組合。閘電極320在藉由使用離子植入或原位沈積之方法摻雜形成源極區330a/汲極區330b期間用作光罩。 側壁間隔物340包含Si3 N4 、SiON、SiCN、SiCO、SiOCN或任何其他合適介電材料中之一或多種。側壁間隔物340之厚度在約5 nm至約20 nm之範圍內。 第二障壁層350形成於源極區330a或汲極區330b上。第二障壁層350包含鈷合金且安置於導電佈線370與基板或鰭片300之間。在一些實例實施例中，第二障壁層350係視情況選用的。 第一障壁層或內襯360包括由鉿(Hf)、鉭(Ta)及鈦(Ti)組成之群中之至少一種及由矽(Si)、碳(C)、氮(N)及氧(O)組成之群中之至少一種。在一些實例實施例中，第一障壁層360包括鈷合金。在一些實例實施例中，第一障壁層360具有非晶形結構。通孔(未圖示)形成於源極區或汲極區330a或330b上。第一障壁層360形成於通孔之內表面上以包圍空間。 在一些實施例中，第一障壁層360由超薄(厚度小於2 nm)鈷合金層形成作為低電阻內襯且電阻率可低至10 µW-cm。第一障壁層360形成之後為使用塊體鈷填充由第一障壁層360包圍之空間，用於與源極區330a或汲極區330b接觸。在一實例實施例中，閘電極320自身亦為鈷基。與圖1中之先前技術中接觸170中之鎢相比，在接觸370中之鈷具有大約8 µW-cm之電阻率且佔據通孔之大部分體積。此金屬化方案整體上提供較低電阻互連件，顯著提高裝置效能。 在一些實例實施例中，鈷合金內襯或第一障壁層360及/或在接觸370中之鈷金屬藉由物理氣相沈積(PVD)、化學氣相沈積(CVD)、金屬-有機化學氣相沈積(MOCVD)、原子層沈積(ALD)或此等技術之組合及變化形式沈積。然而，用於形成鈷內襯及/或鈷金屬之方法之選擇不限於上述沈積法。使用任何其他類型薄膜沈積法用於鈷合金內襯及鈷金屬填充均在本發明概念內。 與圖1中之平面電晶體相比，圖3中之FinFET的包括第一障壁層360及接觸370之三維結構及接觸結構提供較佳裝置效能。相關技術藉由降低FinFET裝置之外部電阻而非FinFET中之電阻或FinFET中之接觸結構中之電阻，製造出具有較高效能之FinFET。圖3之FinFET之金屬化製程包括超薄(厚度小於2 nm)鈷合金作為內襯或第一障壁層360中之低電阻內襯金屬。在一些實例實施例中，FinFET中之內襯之電阻率低至10 µW-cm。鈷金屬加工之後為使用塊體形式鈷填充由內襯360包圍之空間，用於接觸FinFET之源極區330a或汲極區330b。在一些實例實施例中，閘電極320自身亦可為鈷基。在一些實例實施例中，鈷電阻率為大約8 µW-cm，且鈷填充源極區330a或汲極區330b上接觸結構之通孔之大部分體積，甚至在低於22 nm邏輯技術節點中接觸臨界尺寸(CD)低至10 nm的情況下。此金屬化方案整體上提供較低電阻互連件，由此顯著提高裝置效能。 在一些實例實施例中，FinFET之鈷合金內襯及/或鈷金屬藉由物理氣相沈積(PVD)、化學氣相沈積(CVD)、金屬-有機化學氣相沈積(MOCVD)、原子層沈積(ALD)或此等技術之組合及變化形式沈積。然而，用於形成鈷內襯及/或鈷金屬之方法之選擇不限於上述沈積法。使用任何其他類型薄膜沈積法用於鈷合金內襯及鈷金屬填充均在本發明概念內。 圖4展示相關技術之3-D V-NAND記憶體單元。出於說明之目的，僅展示五層。亦即，包括選擇閘極(SL)之層403及412、包括控制閘極(字線)之層404及411、包括控制閘極(字線)之層405及410、包括控制閘極(字線)之層406及409以及包括選擇閘極(SL)之層407及408。此五層電連接(例如經由介電質堆疊)至定位於介電層上之通道401。在通道401及412、411、410、409及408五層之階梯結構之端區上分別形成線接觸402、413、414、415、416、417及418。線接觸402係位元線且其他線係字線及源極線。在一個步驟中加工具有大於30:1至大於80:1之可變縱橫比之階梯式接觸孔(未圖示)。 類似於邏輯技術，金屬化製程包括Ti/TiN作為穿孔中之高電阻內襯金屬，亦即接觸線402、413、414、415、416、417及418之內襯為Ti/TiN層。隨後，Ti/TiN加工之後為使用塊體鎢填充由Ti/TiN之內襯包圍之空間，用於與擴散線及字線接觸之製程。歸因於接觸孔之極高縱橫比，此製程遭受高電阻及跨接觸及接觸至接觸之長度之電阻變化的問題。此金屬化方案整體上提供高電阻互連件，阻礙理想的裝置效能。 圖5展示根據一些實例實施例包括鈷合金內襯及鈷金屬填充之3-D V-NAND。出於說明之目的，僅展示五層。亦即，包括選擇閘極(SL)之層503及512、包括控制閘極(字線)之層504及511、包括控制閘極(字線)之層505及510、包括控制閘極(字線)之層506及509以及包括選擇閘極(SL)之層507及508。此五層電連接(例如經由介電質堆疊)至定位於介電層上之通道501。在通道501及512、511、510、509及508五層之階梯結構之端區上分別形成線接觸502、513、514、515、516、517及518。線接觸502係位元線且其他線係字線及源極線。在一個步驟中加工具有大於30:1至大於80:1之可變縱橫比之階梯式接觸孔(未圖示)。 在一些實例實施例中，金屬化製程包括超薄(厚度小於2 nm)鈷合金作為低電阻內襯金屬。接觸線之電阻率可低至10 µW-cm。鈷金屬加工之後為使用塊體鈷填充由內襯包圍之空間，用於與擴散線及字線之接觸的製程。鈷電阻率為大約8 µΩ-cm，且鈷而非內襯材料目前填充穿孔之大部分體積。此金屬化方案整體上提供較低電阻互連件，因此顯著提高裝置效能。 在一些實例實施例中，3-D V-NAND之鈷合金內襯及/或鈷金屬藉由物理氣相沈積(PVD)、化學氣相沈積(CVD)、金屬-有機化學氣相沈積(MOCVD)、原子層沈積(ALD)或此等技術之組合及變化形式沈積。然而，用於形成鈷內襯及/或鈷金屬之方法之選擇不限於上述沈積法。使用任何其他類型薄膜沈積法用於鈷合金內襯及鈷金屬填充均在本發明概念內。 圖6展示在圖5中標記為A之放大區域。在放大區域A中，選擇閘極(SL) 508具有鈷合金層610及620及鈷層630。線517及518中之各者具有鈷合金層640及鈷填充660或鈷合金層650及鈷填充670。此結構使內襯材料層640及650變窄且增加由具有小於Ti/TiN/W堆疊之電阻率之低電阻接觸金屬鈷佔據的體積。 圖7顯示說明在一實例實施例中形成MOSFET局部互連之方法的流程圖。根據本發明之一實施例，在製程流程中，步驟S701、S702、S703、S704、S705、S706及S707係用於製造PMOS電晶體之加工步驟。加工步驟S708、S709、S710、S711、S712、S713及S714係用於製造NMOS電晶體之加工步驟。在一些實例實施例中，兩組步驟可同時進行。在一些實例實施例中，其獨立進行。當加工PMOS時，NMOS區由包括抗蝕劑及硬遮罩材料之保護層覆蓋。當在PMOS區中之加工步驟完成時，移除覆蓋NMOS區之保護層且進行用於製造NMOS電晶體之步驟(亦即S708、S709、S710、S711、S712、S713及S714)。在PMOS及NMOS製造步驟之後，進行製造整體裝置之步驟(亦即步驟S715、S716、S717、S718、S719及S720)。 首先，形成保護層以僅覆蓋NMOS區且不覆蓋PMOS區。進行光微影及蝕刻方法以執行步驟S701及S702。在步驟S701中，光阻劑層藉由旋轉或沈積法形成於基板上。光罩定位於基板上。在一些實例實施例中，進行UV光微影術。光罩提供開口以允許UV電磁波穿過至光阻劑，從而使光阻劑發生化學變化。隨後進行顯影製程以形成光阻劑圖案。使用光阻劑圖案，使用HCl或其他合適蝕刻劑藉由濕式蝕刻或乾式蝕刻進行基板蝕刻。在步驟S703中，進行清潔製程以清潔基板中源極區或汲極區中之蝕刻凹部。在步驟S704中，凸起之外延SiGe層形成於源極區或汲極區中之蝕刻凹部中，且SiGe原位摻雜。在步驟S705中，進行離子植入以摻雜所形成之凸起之外延SiGe層，從而提高量子井中電荷載流子之量。在步驟S708中，摻雜之外延SiGe層藉由雷射退火以便活化摻雜物且將由此層所引起之應變/應力完全轉移至電晶體之通道。在步驟S707中，沈積介電間層以將摻雜源極/汲極區彼此電隔離。隨後移除覆蓋NMOS區之保護層，且PMOS區由保護層覆蓋。 進行光微影及蝕刻方法以執行步驟S708及S709。在步驟S708中，光阻劑層藉由旋轉或沈積法形成於基板上。光罩定位於基板上。在一些實例實施例中，進行UV光微影術。光罩提供開口以允許UV電磁波穿過至光阻劑，從而使光阻劑發生化學變化。隨後進行顯影製程以形成光阻劑圖案。使用光阻劑圖案，使用HCl或其他合適蝕刻劑藉由濕式蝕刻或乾式蝕刻進行基板蝕刻。在步驟S710中，進行清潔製程以清潔基板中源極區或汲極區中之蝕刻凹部。在步驟S711中，凸起之外延SiC層形成於源極區或汲極區中之蝕刻凹部中，且SiC原位摻雜。在步驟S712中，進行離子植入以摻雜所形成之凸起之外延SiC層以提高量子井中之電荷載流子之量。在步驟S713中，摻雜之外延SiC層藉由雷射退火以便活化摻雜物且將由此層所引起之應變/應力完全轉移至電晶體之通道。在步驟S714中，沈積介電間層以將摻雜源極/汲極區彼此電隔離。隨後，移除覆蓋PMOS之保護層。 在步驟S715中，進行自對準或非自對準介電間層接觸圖案化之製程。在步驟S716中，進行接觸清潔。在一些實施例中，在步驟S717中進行潛在的額外NMOS/PMOS摻雜，但此步驟係視情況選用的。在一些實例實施例中，在步驟S718中形成至少一種鈷組成在30%至99%範圍內之鈷合金。步驟S718包括在局部互連蝕刻或局部互連清潔之後將至少一種鈷合金沈積至源極區及汲極區上以充當MOSFET之源極區及汲極區之低電阻金屬接觸。在一些實例實施例中，源極區及汲極區包含Si、Ge、SiGe、SiC及III-V類半導體中之至少一種。在一些實例實施例中，Co-Ti合金中之Ti與源極區及汲極區之原子相互作用形成擴散障壁以阻斷金屬隨後滲透進入源極區及汲極區。在一些實例實施例中，降低基本金屬-半導體接面肖特基障壁之高度以降低對MOSFET之通道至接觸或局部互連之電流的基本金屬-半導體接面肖特基障壁。在一些實例實施例中，至少一種鈷合金包含鉿(Hf)、鉭(Ta)及鈦(Ti)中之至少一種。在步驟S719中，藉由諸如化學氣相沈積CVD、諸如濺鍍或脈衝雷射沈積之物理氣相沈積之沈積方法以鈷填充由鈷合金內襯包圍之核心空間。在步驟S720中，進行化學及機械拋光(CMP)以使表面平坦。 在一些實例實施例中，凹入/凸起源極/汲極可為Si、SiGe或SiC基材料。在某些情況下諸如InGaAs之小帶隙半導體材料之薄層可在接觸金屬化之前沈積。此進一步允許在金屬化之後的較低電阻路徑。在接觸蝕刻及清潔之後，金屬化由超薄(厚度小於2 nm)鈷合金組成作為低電阻內襯金屬，隨後填充鈷金屬。 在一些實例實施例中，步驟S718及S719亦用於製備FinFET、3-D V-NAND或DRAM之FEOL、MOL及BEOL半導體金屬化互連件。 在一些實例實施例中，以上方法用於控制半導體金屬化互連件中金屬之功函數。亦即，該方法包括將至少一種鈷合金沈積至後閘極介電質上以充當NMOS電晶體之功函數閘電極，將至少一種鈷合金沈積至後閘極介電質上以充當PMOS電晶體之功函數閘電極及將至少一種鈷合金沈積至後功函數閘電極上及以鈷填充閘電極溝槽中之剩餘空隙。金屬之功函數經控制為在4.2 eV至5.2 eV之範圍內的值。鈷合金包含鉿(Hf)、鉭(Ta)及鈦(Ti)中之至少一種。在一些實例實施例中，此方法亦用於製造FinFET、3-D V-NAND或DRAM金屬化互連件。 在一些實例實施例中，與利用W/Ti/TiN結構之習知技術相比，以Co合金層之單層沈積替換高電阻Ti/TiN之雙層沈積，且消除W晶核層之沈積。在一實例實施例中，Co合金層為非晶形層。在一實例實施例中，Co合金層之厚度為約1 nm。在一實例實施例中，Co合金為Co-Ti二元合金。Co合金層延緩矽化物生長，且其亦防止矽化物橫向生長超出接觸區以及超出高度摻雜外延區域。 圖8顯示半導體工業中所用之材料之典型體電阻值的表。在典型10 nm接觸臨界尺寸(CD)上之Ti/TiN/W結構產生接近100 µΩ-cm之電阻率。此高電阻率使裝置效能劣化。此高電阻率係因為如下事實：在歸因於有限CD之接觸通孔體積之狹窄尺寸下，通孔之大部分體積以Ti/TiN內襯(根據圖8電阻率為54或13-130 µΩ-cm)而非W接觸金屬(根據圖8電阻率為約5.28 µΩ-cm)填充。 實例 實例1 具有0.5 nm至5 nm厚度之Co合金之界面層藉由共濺鍍Co之純金屬靶與合金元素金屬而沈積，在SiO2 基板上作為絕緣體材料或在Si基板上作為半導體基板。此後將作為導電佈線之Co層濺鍍沈積至150 nm之厚度。在高溫下在真空中對一些樣品進行熱退火。以下實驗結果之描述為Co-25 at.% Ti (25原子百分比)合金作為界面層之實例。應注意在其他二元Co合金中獲得相同傾向，該等其他二元Co合金具有Ti、Ta及Hf作為合金元素，該等合金元素濃度範圍為Ti 10至80 at.%、Ta 3至25 at.%及Hf 2至25 at.%。藉由膠帶測試研究Co層在SiO2 及Si上之黏著性。測試藉由以下進行：使用剃刀切割機將Co表面剪切成間距為1 mm之10×10方塊，將透明膠帶置於Co層上，用手指輕快地摩擦膠帶表面，及將膠帶自Co層剝離及對Co層剩餘方塊計數。使用Co/Co合金/SiO2 /p型Si/鋁之層堆疊結構研究在Co與SiO2 之間的界面層之擴散障壁特性。在Si基板背側上之鋁(Al)電極膜藉由濺鍍沈積且在真空中在350℃下退火10分鐘以獲得良好低電阻率(歐姆)接觸。在300℃下在3 MV/cm場強度下持續不同時間進行偏壓熱退火(BTA)之前及之後獲得電容-電壓曲線。平帶偏移之量值用作陽性金屬離子擴散進入SiO2 之定量量度。藉由使用傳輸線圓圖法(CTLM)量測接觸電阻率研究Si上Co之電接觸特性。藉由使用光微影法將Co/Co合金層圖案化成圓形圖案來製備樣品。所使用之Si基板為具有在距Si表面30 nm深度內1021 /cm3 表面磷密度之p型Si (001)定向單晶晶圓。藉由聚焦離子束顯微鏡製備截面樣品。藉由高解析度穿透電子顯微術(HR-TEM)觀測經沈積及退火樣品之微觀結構。藉由X射線能量分散光譜學(EDS)量測化學組成分佈。 實例2 將Co-Ti合金薄膜之不同組合物藉由共濺鍍沈積至熱SiO2 /Si基板上。藉由穿透電子顯微術及電子繞射發現非晶相之實驗組成範圍為Co-(22至80) at.% Ti。經沈積薄膜之電阻率藉由四點探針法量測。對於其他實驗採用Co-25 at.% Ti。藉由TEM-EDS研究非晶相之結構及組成分佈。使用在th-SiO2 /p-Si/Al上具有圖案化頂部電極之MOS樣品，在不同溫度下熱退火(TA) 10分鐘及在3 MV/cm下偏壓熱退火(BTA)之前/之後使用光微影法獲得電容-電壓曲線。藉由繪製1/C2 對V之圖推斷平帶電壓。對於接觸特性研究，形成Co (200 nm)/Co-25Ti (1、2、3 nm)/p+ -Si或n+ -Si樣品且退火至多400℃，持續1 min。應注意所有厚度均為標稱值。p+ -Si及n+ -Si摻雜劑濃度分別為3至5×1018 cm-3 及1021 cm-3 。一些樣品退火30 min。採用圓形TLM方法以獲得接觸電阻率。此外檢查退火之前/之後的微觀結構及組成分佈。 實例3 基板為塗佈有40 nm厚熱生長SiO2 膜之p型Si晶圓。在6×10-1 Pa工作壓力及15 sccm 99.99%純度級Ar氣流下藉由在濺鍍150 nm厚Cu膜後將Co與Ti靶共濺鍍將膜沈積於基板上。濺鍍腔室之基礎壓力保持在10-5 Pa以下。Cu (150 nm)/CoTi x (3 nm)堆疊之結構及形態藉由配備有能量分散X射線(EDX)光譜儀之HRTEM表徵。 實例4 在6×10-1 Pa之工作壓力及15 sccm 99.9999%純度級Ar氣流下藉由共濺鍍兩種純金屬靶將Co膜(150 nm)及CoTi x 薄膜(3 nm)沈積於SiO2 /p型Si晶圓上。藉由四點探針法量測膜電阻率。 下文討論來自各種實例之結果。 圖9顯示根據本發明之實例實施例，Co/CoTi/SiO2 微結構經沈積或「經沈積(As-dep)」(頂部圖像)、400℃退火(中間圖像)及600℃(底部圖像)之穿透電子顯微術(TEM)橫截面圖像。圖9之頂部圖顯示具有約150 nm厚Co層之經沈積樣品。在退火之前，圖9之頂部圖指示約3 nm厚之CoTi x 層具有原子排列雜亂之非晶形結構。圖9之中間圖及底部圖分別顯示400℃及600℃下退火10分鐘之Co/CoTi/SiO2 樣品。在400℃下退火之後(圖9之中間圖)，CoTi x 層保持非晶形，具有連續層結構。經沈積及400℃退火樣品的組成分佈(圖10之頂部圖及中間圖)顯示Co及Ti位於界面層中。在600℃下進一步退火引起Co-Ti層之厚度減小以及自非晶形區域形成結晶區域(圖9及圖10之底部圖)。 圖10顯示根據本發明之實例實施例，Co (150 nm)/Co-Ti (3 nm)/SiO2 樣品結構經沈積(頂部圖像)、400℃退火(中間圖像)及600℃退火(底部圖像)之能量分散光譜學(EDS)強度分佈。Ti分佈向SiO2 側移動，其伴有O自SiO2 分離。界面層主要由鈷及鈦組成，連同少量矽及氧。對於Co分佈，其在退火之前起初較寬，因為在具有頂部Co膜之CoTi x 層中Co之分佈重疊。在提高退火溫度之情況下，Co強度顯示自界面向頂部Co膜急劇增加，表明Co自CoTi x 層分離且與頂部Co膜合併。在600℃退火之後界面層不再明顯標識。基於EDS結果，鈷與界面層分離且與鈷覆蓋層合併。此等結果表明在600℃以上鈷合金界面層之非晶形結構及化學組成變得不穩定。 圖11顯示在熱退火之前及之後的電容-電壓(C-V)裝置曲線。在10分鐘熱退火之後經沈積樣品之平帶電壓稍微移至正側。然而，藉由增加熱退火時間至20或45分鐘，未觀測到進一步移動。初始移動可能歸因於氧化物(SiO2 )中之缺陷電荷。在熱退火之後無進一步移動表明鈷或合金元素之金屬離子未擴散進入SiO2 。此表明鈷合金界面層之良好擴散障壁特性。 圖12顯示在低放大率及高放大率下在Co與Si之間的界面區之橫截面圖像(分別為左圖及右圖)。樣品在200℃下退火10分鐘。在圖12之左圖中低放大率橫截面圖中明亮對比度之帶對應於氧化鈦形成。放大圖像(亦即圖12之右圖)顯示Co側上氧化鈦及Si側上Co矽化物之兩層結構。 圖13顯示在鈷合金層之整個厚度中Si、Co及Ti之組成分佈，表明Co未滲透至矽層，因為Si區不含任何量之Co。此顯示鈷合金係防止鈷滲透進入矽層之障壁層。 圖14、圖15(a)及圖15(b)顯示藉由傳輸線圓圖法收集之實驗接觸電阻率裝置資料。其顯示具有或不具有Co-(25 at.% Ti)合金層之Co/Si的量測之接觸電阻率。經沈積狀態之Co及Co-Ti合金之厚度分別為150 nm及2 nm。在200℃下退火之後，測得接觸電阻率為2.4×10-9 µΩ-cm2 。在提高退火溫度至300℃且進一步至400℃之情況下，接觸電阻率逐漸提高。此提高可能歸因於磷摻雜物自Si之n+ 區域至矽化物區域再分佈。取決於Co-Ti合金界面層之初始厚度及組成，針對氧化鈦厚度、Co矽化物厚度及接觸電阻率獲得不同值。儘管如此，當氧化鈦層厚度在0.5 nm至5 nm之範圍內，且Co矽化物厚度在1 nm至10 nm之範圍內時，可獲得大約10-9 µΩ-cm2 之低接觸電阻率。 圖16(a)及圖16(b)顯示在經受250℃下3 MV/cm下(a)熱應力及(b)偏壓熱應力之後具有Co及Co/CoTi x 閘極之MOS電容器的平帶電壓值(Vfb)。圖16(a)及圖16(b)顯示在所有溫度下，具有CoTi x 障壁層之Co/CoTi x /SiO2 /Si結構顯示平帶電壓正向移動，而不具有CoTi x 障壁層之Co/SiO2 /Si結構顯示平帶電壓負向移動。此證實具有CoTi x 障壁層之Co/CoTi x /SiO2 /Si結構歸因於較佳界面而允許較佳裝置控制，且無Co金屬滲透進入SiO2 層。 圖17(a)、圖17(b)、圖17(c)及圖17(d)顯示在圖17(a)之經沈積樣品中、在圖17(b)之400℃退火樣品中、在圖17(c)之500℃退火樣品中及在圖17(d)之600℃樣品中SiO2 /CoTi x /Cu結構之組成分佈。當使用以銅作為共同接觸金屬之CoTi x 合金層時，圖17(a)、圖17(b)、圖17(c)及圖17(d)顯示在所有溫度下(亦即經沈積、400℃退火、500℃退火及600℃退火)，銅(Cu)並不穿過CoTi x 層滲透進入氧化矽層而劣化矽層。 圖18顯示具有Co/SiO2 /p-Si及Co/CoTi x /SiO2 /Si結構之樣品的電阻率隨溫度之變化。與不具有CoTi x 層作為障壁層以避免Co金屬與SiO2 層之間相互滲透之Co/SiO2 /p-Si結構相比，具有CoTi x 層之樣品大體上具有較低電阻率。此證實藉由避免Co金屬與SiO2 層之間相互滲透(尤其閘極間隔件區及互連件區)，CoTi x 障壁層有益於結構。此外，在700-800℃下高溫區中，不具有CoTi x 層之Co/SiO2 /p-Si結構之電阻率顯著提高，證實在高溫下Co金屬與SiO2 層之間相互滲透。在700-800℃下高溫區中，具有CoTi x 層之Co/CoTi x /SiO2 /Si之電阻率保持較低而電阻率無任何提高，且此證實CoTi x 層之功能可有利地避免Co及SiO2 層因相互滲透而劣化。 具體實例僅為了解釋而非以限制之方式提及。因此應瞭解在本說明書中，鈷合金內襯及/或金屬鈷亦建構用於具有互連件之任何類型裝置。金屬銅或金屬鎢與鈷合金內襯之組合使用亦在本發明概念內。 在FEOL 10 nm技術節點中，預期鰭片間距約34 nm且鰭片高度約53 nm。寄生非本徵電阻(亦稱作寄生外部電阻或R-外部)防止在提高電晶體通道中電荷遷移率方面行業已實現之增加轉換成MOSFET驅動電流提高。此遷移率增加決定電晶體開啟及關閉有多快。換言之，非本徵電阻抵消工業已實現以提高通道電荷遷移率之諸如工程應變之創新。接觸及矽化物金屬化占非本徵電阻超過60%。FEOL金屬化包括用於接觸及局部互連之Ti/TiN/W。鈦(Ti)及氮化鈦(TiN)內襯之擴散及黏著特性允許接觸及局部互連之鎢(W)填充。用於與PMOS接觸之矽化鈦(TiSi)、鈦鍺矽化物(TiGeSi)及用於與NMOS接觸之矽化鈦(TiSi)、鈦碳矽化物(TiSiC)係在微電子工業中典型之金屬矽化物。當與半導體源極及汲極接觸時，其產生對電荷流之高障壁特性。本發明以鈷金屬合金內襯繼之以鈷填充代替此金屬系統，降低對電荷流之障壁。 在FEOL 10 nm技術節點中，閘極間距預期為約54 nm。金屬閘極預期具有TaN、TiAlN、TiN及W之複雜堆疊。此金屬系統調節用於PMOS及NMOS電晶體之金屬之功函數。本發明以鈷金屬合金內襯繼之以鈷填充代替此金屬系統。 在MOL 10 nm技術節點中，接觸閘極間距據報導為54 nm。接觸及局部互連(LIC)臨界尺寸(CD)估計小於15 nm。MOL金屬化包括用於接觸及局部互連之Ti/TiN/W。高電阻鈦(Ti)及氮化鈦(TiN)內襯之擴散及黏著特性允許接觸及局部互連之鎢(W)填充。本發明以較低電阻鈷金屬合金內襯繼之以鈷填充代替此金屬系統。其由此產生具有顯著提高之效能之新裝置。 在BEOL 10 nm技術節點中，最小金屬間距據報導為36 nm。高電阻氮化鉭(TaN)及鉭(Ta)內襯經沈積以避免隨後銅晶種及銅填充物擴散進入鄰近低介電常數層間介電質。執行雙鑲嵌製程以在單步製程中蝕刻、清潔及用金屬填充通孔與用於金屬線之溝槽。在10 nm節點技術中最小間距金屬線之臨界尺寸小於20 nm。因此，通孔及溝槽之大部分體積由相對於低電阻銅金屬之高電阻TaN及Ta金屬填充。此引起線路電阻顯著提高且因此增加電線或電路之RC信號延遲。本發明以鈷金屬合金內襯(兩步鈷合金/Co接觸)代替此金屬系統，由此顯著降低線路電阻。因此，其亦降低傳統銅/障壁-晶種加工之電線或電路的RC(電阻-電容)信號延遲。 在記憶體技術中3-D V-NAND之特徵在於具有64堆疊字線(WL)控制閘極(CG)之512 Gb快閃記憶體。128.5 mm2 尺寸之晶粒在生產中且128堆疊WL及CG在開發中。相對於其中個別晶胞相互緊靠地安置於一層中的2-D NAND，3-D V-NAND允許較小佔據面積及較高密度。其亦消除2-D NAND之大部分瓶頸，亦即晶胞對晶胞之干擾及在圖案化中之限制。3-D V-NAND之典型加工以堆疊對(64堆疊對在生產中及128堆疊對在開發中)膜之層膜沈積開始。隨後為高縱橫比通道、階梯及縫隙蝕刻。典型通道間距小於200 nm，直徑小於50 nm。此等結構之縱橫比大於30:1及60:1，等待蝕刻指示。在一個步驟中加工具有類似尺寸但可變縱橫比大於30:1至大於80:1之階梯式接觸孔。階梯式蝕刻亦定義用於高縱橫比接觸著陸之墊，避免用於接觸加工之複雜額外光刻步驟。字線(WL)控制閘極(CG)接觸一般利用典型邏輯鎢加工(Ti/TiN/W)。歸因於接觸孔之極高縱橫比，此過程遭受高電阻及跨接觸及接觸至接觸之長度的電阻變化問題。本發明以鈷金屬合金繼之以鈷填充或銅填充代替此金屬系統。 本發明之實施例係關於在半導體工業晶圓加工中製造利用新系列金屬合金之新系列裝置。開發鈷金屬合金系統用於在FEOL、MOL及BEOL半導體金屬化互連件加工中之應用以製造具有較高效能之裝置。在FEOL加工中，具有小於2 nm之厚度與恰當調節之合金組成的鈷合金層實現以較低淨電阻鈷合金/Co接觸替代與源極、汲極及閘極之高淨電阻Ti/TiN/W接觸。其進一步降低在具有金屬接觸之半導體裝置之凹入/凸起源極/汲極之間的界面電阻。在MOL中其實現以較低電阻鈷合金/Co替代高電阻Ti/TiN/W局部互連。此組合顯著降低裝置之外部電阻(R-外部)，提高裝置速度且允許製造新系列低功率裝置。在BEOL加工中其允許非可縮放TaN/Ta/銅晶種/銅填充加工之替代。然而，兩步鈷合金/Co顯著降低線路電阻且因此亦降低傳統銅/障壁-晶種加工之電線或電路之RC (電阻-電容)信號延遲。本發明允許製造具有顯著較低存取電阻之新一代3-D V-NAND及DRAM。 應瞭解本文所闡述之實例方法之步驟不一定需要按所描述之次序進行，且此類方法之步驟次序應理解為僅為實例。同樣地，額外步驟可包含於此類方法中，且在與各種實施例一致之方法中某些步驟可忽略或組合。 應瞭解所描述之實施例並非互斥，且結合一個實例實施例描述之元件、組件、材料或步驟可以合適方式與其他實施例組合或自其他實施例去除以實現所需設計目標。 在本文中提及「一個實例實施例」或「一實例實施例」意謂結合該實施例描述之特定特徵、結構或特性可包含於至少一個實施例中。在本說明書中不同位置出現詞組「在一個實例實施例中」並不一定指代同一實施例，獨立或替代實施例亦不一定與其他實施例互斥。此適用於術語「實施」及該術語之變化形式。 如本申請案中所使用，詞語「實例」在本文中用以意謂充當實例、例子或說明。不必將本文中描述為「實例」或「例示性」之任何態樣或設計理解為比其他態樣或設計較佳或有利。實情為，使用該詞語意欲以具體方式呈現概念。 此外，術語「或」欲意謂包括性「或」而非排它性「或」。亦即，除非另外規定或根據上下文清楚可見，否則「X使用A或B」欲意謂自然包括性排列中之任一者。亦即，若X使用A；X使用B；或X使用A及B兩者，則「X使用A或B」在前述個例中之任一者下被滿足。另外，除非另外規定或根據上下文清楚可見係針對單數形式，否則如本申請案及所附申請專利範圍中所使用，冠詞「一(a/an)」通常應被解釋為意謂「一或多個」。 儘管在任何以下方法項中要素以特定序列敍述，但除非該方法項之敍述以其他方式暗示用於實施彼等要素中之一些或全部之特定順序，否則彼等要素不一定意欲限於以該特定序列實施。 在本文中申請專利範圍之要素不應依據條款35 U.S.C. § 112(f)理解，除非該要素使用詞組「用於……之構件」或「用於……之步驟」明確地敍述。 進一步瞭解熟習此項技術者可在已描述且說明以解釋所描述之實施例之性質的細節、材料及佈置之部分中作出各種變化而不背離如以下申請專利範圍中表示之範疇。
100‧‧‧基板110‧‧‧閘極介電層120‧‧‧閘電極或閘金屬130a‧‧‧源極區130b‧‧‧汲極區140‧‧‧側壁間隔物150‧‧‧第二障壁層160‧‧‧第一障壁層170‧‧‧接觸180‧‧‧絕緣材料層200‧‧‧基板210‧‧‧閘極介電層220‧‧‧閘電極或閘金屬230a‧‧‧源極區230b‧‧‧汲極區240‧‧‧側壁間隔物250‧‧‧第二障壁層260‧‧‧第一障壁層270‧‧‧接觸或導電佈線280‧‧‧絕緣材料層300‧‧‧基板或鰭片310‧‧‧閘極介電層320‧‧‧閘電極或閘金屬330a‧‧‧源極區330b‧‧‧汲極區340‧‧‧側壁間隔物350‧‧‧第二障壁層360‧‧‧第一障壁層370‧‧‧接觸或導電佈線401‧‧‧定位於介電質層上之通道402‧‧‧線接觸403‧‧‧包括選擇閘極(SL)之層404‧‧‧包括控制閘極(字線)之層405‧‧‧包括控制閘極(字線)之層406‧‧‧包括控制閘極(字線)之層407‧‧‧包括選擇閘極(SL)之層408‧‧‧包括選擇閘極(SL)之層409‧‧‧包括控制閘極(字線)之層410‧‧‧包括控制閘極(字線)之層411‧‧‧包括控制閘極(字線)之層412‧‧‧包括選擇閘極(SL)之層413‧‧‧線接觸414‧‧‧線接觸415‧‧‧線接觸416‧‧‧線接觸417‧‧‧線接觸418‧‧‧線接觸501‧‧‧定位於介電質層上之通道502‧‧‧線接觸503‧‧‧包括選擇閘極(SL)之層504‧‧‧包括控制閘極(字線)之層505‧‧‧包括控制閘極(字線)之層506‧‧‧包括控制閘極(字線)之層507‧‧‧包括選擇閘極(SL)之層508‧‧‧包括選擇閘極(SL)之層509‧‧‧包括控制閘極(字線)之層510‧‧‧包括控制閘極(字線)之層511‧‧‧包括控制閘極(字線)之層512‧‧‧包括選擇閘極(SL)之層513‧‧‧線接觸514‧‧‧線接觸515‧‧‧線接觸516‧‧‧線接觸517‧‧‧線接觸518‧‧‧線接觸610‧‧‧鈷合金層620‧‧‧鈷合金層630‧‧‧鈷層640‧‧‧鈷合金層650‧‧‧鈷合金層660‧‧‧鈷填充670‧‧‧鈷填充S701‧‧‧步驟S702‧‧‧步驟S703‧‧‧步驟S704‧‧‧步驟S705‧‧‧步驟S706‧‧‧步驟S707‧‧‧步驟S708‧‧‧步驟S709‧‧‧步驟S710‧‧‧步驟S711‧‧‧步驟S712‧‧‧步驟S713‧‧‧步驟S714‧‧‧步驟S715‧‧‧步驟S716‧‧‧步驟S717‧‧‧步驟S718‧‧‧步驟S719‧‧‧步驟S720‧‧‧步驟
圖1展示相關技術之MOSFET沿源極-汲極方向，亦即y 方向之橫截面圖。 圖2展示根據一些實例實施例之MOSFET沿源極-汲極方向，亦即y 方向之橫截面圖。 圖3展示根據一些實例實施例之具有FinFET結構之MOSFET沿源極-汲極方向，亦即y 方向的橫截面圖。 圖4展示相關技術之3-D V-NAND記憶體單元。 圖5展示根據一些實例實施例之3-D V-NAND記憶體單元。 圖6展示在圖5中標記為A之放大區域。 圖7顯示一種根據一些實例實施例形成MOSFET之方法。 圖8顯示在半導體工業中所用之材料之典型電阻的表。 圖9顯示根據一些實例實施例，Co/CoTi/SiO2 之微觀結構經沈積(頂部圖像)、400℃退火(中間圖像)及600℃退火(底部圖像)的穿透電子顯微術(TEM)橫截面圖像。 圖10顯示根據一些實例實施例，Co (150 nm)/Co-Ti (3 nm)/SiO2 樣品結構之鈷合金障壁層經沈積(頂部圖像)、400℃退火(中間圖像)及600℃退火(底部圖像)的能量分散光譜學(EDS)強度分佈。 圖11顯示根據一些實例實施例，經沈積(在圖13之圖例中簡稱為「經沈積(as dep)」)、300℃退火10分鐘、300℃退火20分鐘、300℃退火30分鐘及300℃退火45分鐘之Co/Co-Ti/SiO2 結構的電容-電壓(C-V)裝置量測值。 圖12顯示根據一些實例實施例，與矽介接之障壁層Co/Co-Ti/Si之TEM橫截面圖像(左側圖像具有20 nm比例尺且右側圖像具有5 nm比例尺)。 圖13顯示根據一些實例實施例在整個鈷合金層之厚度中Si、Co及Ti之組成分佈。 圖14顯示藉由使用傳輸線圓圖法(Circular Transmission Line Method，CTLM)在根據本發明之一實例實施例之Co-Ti鈷合金上進行之電阻率量測所收集的實驗接觸電阻率裝置資料。 圖15(a)及圖15(b)顯示藉由使用傳輸線圓圖法(CTLM)在根據本發明之一實例實施例之Co-Ti鈷合金上進行之電阻率量測所收集的實驗接觸電阻率設備資料。 圖16(a)及圖16(b)顯示根據一些實例實施例具有Co及Co/CoTi x 閘極之MOS電容器在250℃下在3 MV/cm下經受(a)熱應力及(b)偏壓熱應力之後的平帶電壓值(Vfb)。 圖17(a)、圖17(b)、圖17(c)及圖17(d)顯示根據一些實例實施例在圖17(a)之經沈積樣品中、在圖17(b)之400℃退火樣品中、在圖17(c)之500℃退火樣品中及在圖17(d)之600℃退火樣品中SiO2 /CoTi x /Cu結構之組成分佈。 圖18顯示根據一些實例實施例具有Co/SiO2 /p-Si及Co/CoTi x /SiO2 /Si結構之樣品的電阻率隨溫度之變化。

Claims (19)

  1. 一種半導體裝置，其包含：基板；導電佈線，其包含鈷或銅且電連接至該基板；絕緣材料，其將該導電佈線與鄰近佈線電隔離；第一障壁層，其包含第一鈷合金且安置於該導電佈線與該絕緣材料之間；及第二障壁層，其包括第二鈷合金且安置於該導電佈線與該基板之間；其中該第一障壁層不具有與該第二障壁層相同之組成；且其中該第一障壁層與該第二障壁層皆與該導電佈線接觸。
  2. 如請求項1之半導體裝置，其中該導電佈線包含鈷。
  3. 如請求項2之半導體裝置，其中該鈷合金包含鈷及鉿(Hf)、鉭(Ta)及鈦(Ti)中之至少一種。
  4. 如請求項1之半導體裝置，其中該第一障壁層及該第二障壁層中之至少一種包含非晶形結構。
  5. 如請求項1之半導體裝置，其中該第一障壁層及該第二障壁層中之至少一種進一步包含矽(Si)、碳(C)、氮(N)及氧(O)中之至少一種。
  6. 如請求項1之半導體裝置，其中：該第一障壁層包含鉿(Hf)、鉭(Ta)及鈦(Ti)中之至少一種及矽(Si)、碳(C)、氮(N)及氧(O)中之至少一種，及該第二障壁層包含鈷及矽、SiGe、SiC及InGaAs中之至少一種。
  7. 如請求項2之半導體裝置，其中該第一障壁層由具有結晶結構且與該基板具有外延結晶關係之矽化鈷形成。
  8. 如請求項2之半導體裝置，其中該第一障壁層之厚度在1nm至30nm之範圍內。
  9. 如請求項1之半導體裝置，其中該第二障壁層包含氧化鉿、氧化鉭及氧化鈦中之至少一種且具有非晶形結構。
  10. 如請求項1之半導體裝置，其中該第二障壁層之厚度在0.5nm至5nm之範圍內。
  11. 如請求項1之半導體裝置，其中該第二障壁層進一步包含碳及氮。
  12. 一種平面電晶體，其包含如請求項2之半導體裝置且包括源極接觸及汲極接觸，其中該源極接觸及該汲極接觸各自包含該半導體裝置之該導電佈線及該第一障壁層。
  13. 一種FinFET電晶體，其包含如請求項1之半導體裝置且包括源極接觸及汲極接觸，其中該源極接觸及該汲極接觸各自包含該半導體裝置之該導電佈線及該第一障壁層。
  14. 一種3-D V-NAND記憶體裝置，其包含如請求項2之半導體裝置且包括：選擇閘極，字線階梯式接觸，及源極線接觸，其中該選擇閘極、字線階梯式接觸及源極線接觸各自包含該半導體裝置之該導電佈線及該第一障壁層。
  15. 一種形成用於如請求項2之半導體裝置之半導體金屬化互連件的方法，其包含：形成至少一種鈷含量在30%至99%範圍內之鈷合金；及在局部互連(Local-Inter-Connect)蝕刻或局部互連清潔之後將該至少一種鈷合金沈積至源極區及汲極區上以充當金氧半導體場效電晶體(MOSFET)之源極區及汲極區之低電阻金屬接觸，其中該源極區及該汲極區包含Si、Ge、SiGe、SiC及III-V類半導體中之至少一種，其中Co-Ti合金中之Ti與該源極區及該汲極區之原子相互作用形成擴散障壁以阻斷金屬隨後滲透進入該源極區及該汲極區，及 其中降低基本金屬-半導體接面肖特基障壁之高度以降低對該MOSFET之通道至該接觸或該局部互連之電流的該基本金屬-半導體接面肖特基障壁。
  16. 如請求項15之方法，其中該至少一種鈷合金包含鉿(Hf)、鉭(Ta)及鈦(Ti)中之至少一種。
  17. 一種半導體裝置，其為三維垂直反及(3-D V-NAND)或動態隨機存取記憶體(DRAM)且包含藉由如請求項15之方法製造之前段製程(FEOL)、中段製程(MOL)及後段製程(BEOL)半導體金屬化互連件中的至少一種。
  18. 一種控制用於如請求項2之半導體裝置之半導體金屬化互連件的功函數之方法，其包含：將至少一種鈷合金沈積至NMOS電晶體之閘極介電層上，其中該至少一種鈷合金充當該NMOS電晶體之功函數閘電極；將至少一種鈷合金沈積至PMOS電晶體之閘極介電層上，其中該至少一種鈷合金充當該PMOS電晶體之功函數閘電極；及將至少一種鈷合金以內襯形式沈積至該等功函數閘電極中之各者上以包圍核心空間且以鈷填充該核心空間，形成包括填充有鈷之該核心及該內襯之該半導體金屬化互連件，其中該半導體金屬化互連件之該功函數經控制為在4.2eV至5.2eV之範圍內的值。
  19. 如請求項18之方法，其中該鈷合金包含鉿(Hf)、鉭(Ta)及鈦(Ti)中之至少一種。
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