CN107785249B - 制造半导体装置的方法 - Google Patents
制造半导体装置的方法 Download PDFInfo
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- CN107785249B CN107785249B CN201710385165.9A CN201710385165A CN107785249B CN 107785249 B CN107785249 B CN 107785249B CN 201710385165 A CN201710385165 A CN 201710385165A CN 107785249 B CN107785249 B CN 107785249B
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
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Abstract
一种制造半导体装置的方法,包含下列步骤。在半导体基板上形成第一金属层,并在第一金属层上形成第二金属层。第二金属层由与第一金属层不同的金属形成。施加微波辐射于半导体基板、第一金属层和第二金属层,以形成包含第一金属层、第二金属层和半导体基板的成分的合金。
Description
技术领域
本揭露是关于制造半导体集成电路的方法,更具体地涉及制造具有场效晶体管(field effect transistor,FET)结构的半导体装置。
背景技术
随着半导体工业引入具有更高性能和更大功能性的新一代集成电路(integratedcircuits,ICs),导致集成电路的元件的密度增加,并且金属触点和布线的尺寸减小,进而增加电路的电阻。因此,半导体业界皆期望减小接触区域处的电阻以在集成电路中提供进一步的改进。
发明内容
根据本揭露的一方面是提供一种制造半导体装置的方法,包含下列步骤。先形成第一金属层于半导体基板上,再形成第二金属层于第一金属层上,其中第二金属层由与第一金属层不同的金属形成。接着,施加微波辐射于半导体基板、第一金属层以及第二金属层,以形成合金,其包含第一金属层、第二金属层以及半导体基板的成分,其中微波辐射以0.6kW至4.4kW的功率施加40秒至240秒,合金是NiGePt2三元合金。
本揭露的另一方面是提供一种制造半导体装置的方法,包含下列步骤。先形成栅极结构于半导体基板的第一区域,接着,形成源极/漏极区域于半导体基板的第二区域,其中第二区域位于第一区域的相对侧上。然后,形成第一金属层于源极/漏极区域,之后,形成第二金属层于第一金属层上,其中第二金属层由与第一金属层不同的金属形成。最后,施加微波辐射于半导体基板、第一金属层以及第二金属层,以形成合金,其包含第一金属层、第二金属层以及半导体基板的成分,其中微波辐射以1.2kW至4.4kW的功率施加40秒至240秒,合金是NiGePt2三元合金。
本揭露的另一方面是提供一种制造半导体装置的方法,包含下列步骤。首先,在半导体基板中形成一对间隔开的源极/漏极区域。接着,在源极/漏极区域上形成第一金属层,之后,在第一金属层上形成第二金属层,其中,第二金属层由与第一金属层不同的金属形成。施加微波辐射于半导体基板、第一金属层和第二金属层,以在源极/漏极区域上形成包含第一金属层、第二金属层和半导体基板的成分的合金之后,在半导体基板上方形成高介电绝缘层,并且在间隔开的源极/漏极区域之间的区域中的高介电绝缘层上方形成导电金属层。接着,在源极/漏极区域上形成导电接触。合金是NiGePt2三元合金。
附图说明
当以下详细描述与附图一起阅读时,可以最好地理解本揭露。要强调的是,根据工业中的标准实践,各种特征不是按比例绘制的,并且仅用于说明目的。实际上,为了清楚地讨论,可以任意地增加或减少各种特征的尺寸。
图1绘示根据本揭露部分实施方式中,制造半导体装置的方法的流程图;
图2-图12绘示根据本揭露部分实施方式中,制造半导体装置的方法;
图13绘示根据本揭露部分实施方式中,制造半导体装置的方法的流程图;
图14绘示根据本揭露部分实施方式中,制造半导体装置的方法的流程图;
图5-图23绘示根据本揭露部分实施方式中,制造场效晶体管半导体装置的方法;
图24-图31绘示根据本揭露部分实施方式中,制造场效晶体管半导体装置的方法;
图32A-图34B绘示根据本揭露部分实施方式中,制造场效晶体管半导体装置的方法;
图35绘示根据本揭露部分实施方式中,将微波辐射施加到半导体装置的微波系统。
具体实施方式
应当理解,以下提供了用于实现本揭露不同特征的许多实施例或示例。以下描述的元件和实施例或示例是用以简化本揭露。当然,这些仅是示例并且不旨在限制。例如,元件的尺寸不限于所揭露的范围或值,而是可以取决于制成条件和/或装置的期望特性。此外,在以下描述中在第一特征之上形成第二特征,可以包含第一特征和第二特征以直接接触形成的实施例,并且还可以包含形成介于第一特征和第二特征之间的额外特征的实施例,使得第一特征和第二特征可以不直接接触。为了简单和清楚,可以不同的比例任意地绘制各种特征。
此外,在本文中使用空间相对术语,诸如“下”或“底部”与“上”或“顶部”等,以便于描述如图中所示的一个元件或特征与另一元件或特征的关系。空间相对术语旨在涵盖除了图中所示的方位之外,其它使用或操作中,装置的不同方位。装置可以以其他方式定向(旋转90度或在其它方向),并且本文使用的空间相对描述可以相应地解释。此外,术语“由...构成”可以表示“包含”或“由...组成”。
可受益于本揭露的一个或一个以上实施例的装置的实例为肖特基势垒二极管(Schottky barrier diodes)和具有场效晶体管(FET)的半导体装置。示例性场效晶体管包含金属氧化物半导体(metal-oxide-semiconductor,MOS)场效晶体管,例如具有掺杂有p型掺杂剂(例如硼或二氟化硼)的p型场效晶体管(PFET)或具有掺杂有n型掺杂剂(例如磷或砷)的n型场效晶体管(NFET)。场效晶体管可以是平面装置或三维(3D)鳍式场效晶体管(fin-type field effect transistors,finFET),本文中称为鳍式场效晶体管装置。平面装置是指非鳍式场效晶体管装置。鳍式场效晶体管可以是多栅极晶体管,例如双栅极装置,三栅极装置和/或其他配置。所述装置可包含于例如微处理器、存储器装置和/或其它集成电路中。本领域通常知识者可了解到其它实施例的半导体装置可受益于本揭露。
本文提供一种或一种以上用于形成半导体装置的技术及由此形成的所得结构。
在图1中绘示根据本揭露部分实施例的制造半导体装置的方法的流程图。在操作S201中,在半导体基板上形成包含第一金属的第一金属层。在操作S202中,在第一金属层上形成包含不同于第一金属的第二金属的第二金属层。在操作S203中,对半导体基板、第一金属层和第二金属层施加微波辐射以形成包含第一金属层、第二金属层和半导体基板的成分的合金。
图2-图12绘示根据本揭露的部分实施例中,用于制造半导体装置10的方法。在一些实施例中,透过本方法形成的半导体装置10是肖特基势垒二极管。
如图2所示,在半导体基板12上形成遮罩层14。半导体基板12可以包含单晶半导体材料,例如但不限于硅(Si)、锗(Ge)、硅化锗(SiGe)。在部分实施例中,半导体基板12是由锗制成。在部分实施例中,对半导体基板12进行清洁操作,例如暴露即将沉积遮罩的半导体基板12的表面于稀释氢氟酸(dilute hydrofluoric acid,DHF)。
遮罩层14可以是任何合适的遮罩材料,包含光阻(photoresist)或硬遮罩材料,例如氧化物或氮化物。氧化物或氮化物硬遮罩材料可以透过合适的沉积技术沉积,例如化学气相沉积(chemical vapor deposition,CVD),包含低压化学气相沉积(low pressurechemical vapor deposition,LPCVD)、等离子体增强化学气相沉积(plasma enhancedchemical vapor deposition,PECVD)、物理气相沉积(physical vapor deposition,PVD)和原子层沉积(atomic layer deposition,ALD)。如图3所示,随后在遮罩层14中形成开口16,透过合适的光刻和蚀刻操作暴露半导体基板12的一部分。
参考图4,在遮罩层14和半导体基板12上沉积光阻层15,并且使用光刻操作对光阻层15进行图案化,以暴露开口16中的半导体基板12。在一些实施例中,光阻层15是正性光阻,在其他实施例中为负性光阻。
如图5所示,透过合适的沉积技术,例如溅射(sputtering)或物理气相沉积,在半导体基板12和光阻层15的暴露部分上形成第一金属层18。在一些实施例中,第一金属层18形成为约3纳米(nm)至约30纳米(nm)的厚度。在部分实施例中,第一金属层18的厚度在约6纳米至约14纳米的范围内。在一些实施例中,第一金属层18是选自由镍(Ni)、铂(Pt)、金(Au)、钽(Ta)、钆(Gd)、钛(Ti)和锗(Ge)组成的群组中的至少一种。在另一实施例中,第一金属层18是由硅组成。
如图6所示,透过合适的沉积技术,例如溅射或物理气相沉积,在第一金属层18上形成第二金属层20。在一些实施例中,第二金属层20形成为约3奈至约30纳米的厚度。在部分实施例中,第二金属层20的厚度为约5纳米至约15纳米。在一些实施例中,第二金属层20是选自由镍、铂、金、钽、钆、钛和锗组成的群组中的至少一种。在另一实施例中,第二金属层20是由硅组成。第二金属是与第一金属不同的金属。
参考图7,在一些实施例中,在沉积第二金属层之后,使用适当的光阻溶剂(例如丙酮)透过剥离操作(lift-off operation)去除光阻层15以及覆盖于光阻层15上的第一金属层18和第二金属层20。遮罩层14也一并去除,并且执行微波激活退火操作(microwave-actived annealing operation)以形成与半导体基板12接触的合金。如图7所示,微波激活退火操作包含将微波辐射72施加到半导体基板12、第一金属层18和第二金属层20。在一些实施例中,微波辐射在约1GHz至约30GHz的频率范围和约0.6kW至约4.4kW的功率下施加约40秒至约240秒。在其它实施例中,微波辐射以约1.2kW至约2.2kW的功率施加约80秒至约120秒。在部分实施例中,半导体装置10在惰性气体(例如氮气气体)中暴露于微波辐射。
将微波辐射施加到半导体装置10导致半导体装置10的局部加热,其包含第一金属层18和第二金属层20。在一些实施例中,第一金属层18和第二金属层20的温度从环境温度升高至暴露于微波辐射期间约200℃至约600℃的温度。在其它实施例中,在暴露于微波辐射期间,第一金属层18和第二金属层20的温度增加至约300℃至约500℃的温度范围。如图8所示,第一金属层18和第二金属层20的加热使得第一金属层18的金属和第二金属层20的金属扩散到半导体基板12中,并且与半导体基板12形成合金层22。在特定实施例中,形成三元合金层22。
在部分实施例中,在锗基板12上,第一金属层18是6纳米至14纳米厚的镍溅射沉积层,第二金属层20是5纳米至15纳米厚的铂物理气相沉积层。在部分实施例中,第一金属层18和第二金属层20各自具有约10纳米的厚度。在一些实施例中,合金层22包含镍、锗和铂的三元合金(NiGePt)。在部分实施例中,三元合金层包含NiGePt2。
取决于金属材料,第一金属层18的厚度将影响当第一金属层18与第二金属层20暴露于微波辐射时,三元合金是否会形成。例如,当第一金属层18是铂并且第二金属层20是镍时,如果第一金属层18的厚度小于6纳米或大于14纳米,则不会形成三元合金层22。如果第一金属层18是铂并且厚度小于6纳米,第二金属层20是镍,则镍将容易透过铂进入半导体基板12,并且不会形成三元合金层22。另一方面,如果第一金属层是铂且厚度大于14纳米,则镍将不能充分地扩散到半导体基板12中以形成三元合金层22。当第一金属层18是铂并且厚度在5纳米和14纳米之间,在部分实施例中,铂和镍都充分地扩散到半导体基板12中,并且有足够的热在半导体基板12中积累以形成包含铂、镍和锗的三元合金层22。
在一些实施例中,三元合金层22的厚度为约15纳米至约70纳米。在其他实施例中,三元合金层22的厚度为约25纳米至约60纳米。
在一些实施例中,镍锗铂(NiGePt)三元合金层22中的镍/铂的原子比为约3.5至约1.1。
如图9所示,之后,在一些实施例中形成具有暴露三元合金层22的第二开口26的绝缘层24。绝缘层24是氧化物或氮化物,例如在一些实施例中是氧化硅或氮化硅。绝缘层24可以透过任何合适的沉积操作形成,包含化学气相沉积、低压化学气相沉积、等离子体增强化学气相沉积和原子层沉积。透过光刻和蚀刻操作图案化绝缘层24以形成开口26。
参考图10,在绝缘层24上形成第二光阻层28。如图11所示,使用光刻操作对第二光阻层28进行图案化以暴露三元合金层22的一部分,并且形成上接触层33与三元合金层22接触。上接触层33由例如金属的导电材料所形成。在一些实施例中,金属是选自由铝(Al)、铜(Cu)、钛(Ti)和钨(W)组成的群组中的至少一种。如图11所示,在一些实施例中,上接触层33包含多个接触层(第一接触层30与第二接触层32)。在一些实施例中,上接触层33包含双层,其包含由钛组成的第一接触层30和由铝组成的第二接触层32。在一些实施例中,第一接触层30的厚度为约10纳米至约50纳米,第二接触层32的厚度为约20纳米至约60纳米。在部分实施例中,整个上接触层33的厚度为约30纳米至约110纳米。
参考图12,在一些实施例中,在沉积上接触层33之后,使用适当的光阻溶剂透过剥离操作去除第二光阻层28和覆盖在第二光阻层28上的第一接触层30和第二接触层32。如图12所示,在部分实施例中,下接触层37形成在与半导体基板12上接触层33相对的表面上。下接触层37由导电材料形成,例如金属。在一些实施例中,金属选自由铝、铜、钛和钨组成的群组。如图12所示,在一些实施例中,下接触37包含多个接触层(第一接触层34和第二接触层36)。在一些实施例中,下接触37包含双层,其包含由钛组成的第一接触层34和由铝组成的第二接触层36。金属接触层(第一接触层30、34和第二接触层32、36)可以透过任何合适的技术形成,包含化学气相沉积、低压化学气相沉积、等离子体增强化学气相沉积、物理气相沉积和原子层沉积、溅射和电镀。在一些实施例中,第一接触层30的厚度为约10纳米至约50纳米,第二接触层32的厚度为约20纳米至约60纳米。在某些实施例中,整个上接触层33的厚度为约30纳米至约110纳米。在一些实施例中,第一接触层34的厚度为约10纳米至约50纳米,第二接触层36的厚度为约20纳米至约60纳米。在某些实施例中,整个下接触层37的厚度为约30纳米至约110纳米。
如图13所示,根据本揭露部分实施例的制造半导体装置的另一种方法,包含,在半导体基板上形成栅极结构的操作S301,和在半导体基板上形成源极/漏极区域的操作S302。在本揭露部分实施例中,源极和漏极可互换地使用,并且其结构基本上相同。在操作S303中,在源极/漏极区域上形成第一金属层,并且在操作S304中,在第一金属层上形成第二金属层。随后,在操作S305中,将微波辐射施加到半导体基板、第一金属层和第二金属层。
如图14所示,根据本揭露的部分实施例的制造半导体装置的另一种方法,包含,在半导体基板上形成源极/漏极区域的操作S401和在源极/漏极区域上形成第一金属层的操作S402。在操作S403中,在源极/漏极区域上形成第二金属层,随后在操作S404中,将微波辐射施加到半导体基板、第一金属层和第二金属层。在操作S405中,在半导体基板上形成高介电绝缘层(high-k insulating layer),并且在操作S406中,在源极/漏极区域之间的区域中,形成导电金属层于高介电绝缘层上。在操作S407中,在源极/漏极区域上形成导电接触。
图5-图23绘示根据本揭露的部分实施例的制造场效晶体管半导体装置100的方法。如图12所示,在半导体基板40上形成栅极介电层42,并且在栅极介电层42上形成栅极电极层44。
在一些实施例中,半导体基板40可以包含单晶半导体材料,例如但不限于硅、锗和硅锗。在部分实施例中,半导体基板40由锗制成。在部分实施例中,对半导体基板40进行清洁操作,例如暴露即将沉积遮罩的半导体基板40的表面于稀释氢氟酸。
半导体基板40可以在其表面区域中包含一个或多个缓冲层(未绘示)。缓冲层可用于将晶格常数从基板的晶格常数逐渐改变为源极/漏极区域的晶格常数。缓冲层可以由外延生长的单晶半导体材料形成,例如但不限于硅(Si)、锗(Ge)、锗锡(GeSn)、硅锗(SiGe)、镓砷(GaAs)、铟鍗(InSb)、镓磷(GaP)、镓鍗(GaSb)、铟铝砷(InAlAs)、铟镓砷(InGaAs)、镓鍗磷(GaSbP)、镓砷鍗(GaAsSb)、镓氮(GaN)、镓磷(GaP)和铟磷(InP)。在特定实施例中,半导体基板40的最上层由锗制成,并且缓冲层是在硅基层上外延生长的硅锗。硅锗缓冲层的锗浓度可以从最底部缓冲层的30原子百分比增加到最顶层缓冲层的70原子百分比。
栅极介电层42由半导体基板材料的氧化物或氮化物形成,例如在一些实施例中为氧化硅或氧化锗。在一些实施例中,透过热氧化半导体基板的上表面形成氧化物,而在其他实施例中,透过包含化学气相沉积、低压化学气相沉积、等离子体增强化学气相沉积、物理气相沉积和原子层沉积的沉积操作形成氧化物。在一些实施例中,栅极介电层42包含一层或多层高介电材料(high-k dielectric material)。高介电材料包含二氧化铪(HfO2)、硅氧化铪(HfSiO)、氮氧硅化铪(HfSiON)、钽氧化铪(HfTaO)、钛氧化铪(HfTiO)、锆氧化铪(HfZrO)、氧化锆(zirconium oxide)、氧化铝(aluminum oxide)、氧化钛(titaniumoxide)、二氧化铪-氧化铝(HfO2-Al2O3)合金,其它合适的高介电材料和/或透过沉积操作形成的其组合,其中,沉积操作包含化学气相沉积、低压化学气相沉积和等离子体增强化学气相沉积。在一些实施例中,栅极介电层42包含形成在半导体基板40和介电材料之间的界面层(未绘示)。
在部分实施例中,源极/漏极区域包含含有掺杂剂浓度大于1020原子·厘米-3(1020atoms·cm-3)的重掺杂区。在部分实施例中,源极/漏极区域是透过外延形成。
在一些实施例中,栅极电极层44包含一个或多个导电材料层,例如多晶硅(polysilicon)、铝(Al)、铜(Cu)、钛(Ti)、钽(Ta)、钨(W)、钴(Co)、钼(Mo)、氮化钽(TaN)、硅化镍(NiSi)、硅化钴(CoSi)、氮化钛(TiN)、WN(氮化钨)、TiAl(铝化钛)、TiAlN(氮化铝钛)、TaCN(氮化碳钽)、TaC(碳化钽)、TaSiN(氮化硅钽)、金属合金或其它合适的材料和/或其组合。
栅极电极层44可以透过化学气相沉积、低压化学气相沉积、等离子体增强化学气相沉积、物理气相沉积、原子层沉积、电子束蒸发、电镀或其他合适的方法形成。
在本揭露的某些实施例中,一个或多个功函数调整层(未绘示)位于栅极介电层42和栅极电极层44之间。功函数调整层由导电材料制成,例如单层氮化钛(TiN)、氮化钽(TaN)、氮化铝钽(TaAlN)、碳化铝钽(TaAlC)、碳化钛(TiC)、碳化钽(TaC)、钴(Co)、铝(Al)、铝化钛(TiAl)、钛化铪(HfTi)、硅化铪(TiSi)、硅化钽(TaSi)或碳化铝钛(TiAlC),或这些材料中的两种或更多种的多层。功函数调整层可以透过化学气相沉积、物理气相沉积、原子层沉积和电子束蒸发或其他合适的制程形成。
在一些实施例中,半导体基板40由锗制成,栅极介电层42是双层,其包含设置在半导体基板40上由二氧化锗(GeO2)形成的第一层和设置在第一层上由三氧化二铝(Al2O3)形成的第二层,且栅极电极层44是铝。
如图16所示,使用光刻和蚀刻操作来图案化栅极介电层42和栅极电极层44,以形成包含栅极介电层42和栅极电极45的闸电极结构41。如图17所示,使用图案化的栅极介电层42和栅极电极45作为遮罩,掺杂剂注入到半导体基板40中以形成源极/漏极区域46。如图18所示,在栅极介电层42和栅极电极45的侧壁上形成的栅极绝缘侧壁48随后被添加到栅极电极结构41中,并且将额外的掺杂剂注入到源极/漏极区域46中以增加掺杂剂浓度并且扩展源极/漏极区域46。在一些实施例中,栅极绝缘侧壁48包含一个或多个绝缘氧化物和/或氮化物层。在一些实施例中,源极/漏极区域46包含掺杂剂,其浓度大于1020原子·厘米-3(1020atoms·cm-3)。
参考图19,透过合适的沉积技术,例如溅射或物理气相沉积,在源极/漏极区域46上形成第一金属层50。在一些实施例中,第一金属层50形成为约3纳米至约30纳米的厚度。在某些实施例中,第一金属层50的厚度在约6纳米至约14纳米的范围内。在一些实施例中,第一金属层50是选自由镍、铂、金、钽、钆、钛、锗和硅所组成的群组中的至少一种。
透过合适的沉积技术,例如溅射或物理气相沉积,在第一金属层50上形成第二金属层52。在一些实施例中,第二金属层52形成为约3纳米至约30纳米的厚度。在某些实施例中,第二金属层52的厚度范围为约5纳米至约15纳米。在一些实施例中,第二金属层52是选自由镍、铂、金、钽、钆、钛、锗和硅组成的群组中的至少一种。第二金属是与第一金属不同的金属。
透过光刻和蚀刻操作去除沉积在栅极电极45上以及沉积在栅极绝缘侧壁48上表面的部分第一金属层50和部分第二金属层52,从而将第一金属层50和第二金属层52限制为覆盖源极/漏极区域46上。
如图20所示,在沉积第二金属层之后,执行微波激活退火操作以形成与源极/漏极区域46接触的合金。微波激活退火操作包含将微波辐射72施加到半导体基板40、第一金属层50和第二金属层52。在一些实施例中,微波辐射在约1GHz至约30GHz的频率范围和约0.6kW至约4.4kW的功率下施加约40秒至约240秒。在其它实施例中,以约1.2kW至约2.2kW的功率施加约80秒至约120秒。在部分实施例中,半导体装置40在惰性气体(例如氮气气体)中暴露于微波辐射。
如图21所示,将微波辐射施加到半导体装置100引起半导体装置100的局部加热,包含第一金属层50和第二金属层52,如本文关于第7-8图所述,以产生三元合金层54。
在一些实施例中,在暴露于微波辐射期间,第一金属层50、第二金属层52和源极/漏极区域46的温度从环境温度增加到范围从约200℃至约600℃的温度。在其它实施例中,在暴露于微波辐射期间,温度增加至约300℃至约500℃。当局部加热达到小于或等于约600℃的温度时,源极/漏极区域46中的掺杂剂不容易扩散。
在一些实施例中,在栅极电极45和第三合金层54上形成层间介电质56(interlayer dielectric,ILD),如图22所示。用于形成层间介电质56的材料包含硅(Si)、氧(O)、碳(C)和/或氢(H)的化合物,例如碳硅氧化物(SiCOH)和碳氧化硅(SiOC)。有机材料,例如聚合物,可用于形成层间介电质56。层间介电质56可以透过低压化学气相沉积、等离子体增强化学气相沉积或可流动化学气相沉积(flowable chemical vapor deposition,FCVD)形成。在可流动化学气相沉积中,在基板上沉积可流动介电材料而非氧化硅。可流动介电质前驱物,特别是可流动氧化硅前驱物的例子包含硅酸盐、硅氧烷、甲基倍半硅氧烷(methyl silsesquioxane,MSQ)、氢倍半硅氧烷(hydrogen silsesquioxane,HSQ)、甲基倍半硅氧烷/氢倍半硅氧烷(MSQ/HSQ)、全氢硅氮烷(perhydrosilazane,TCPS)、全氢聚硅氮烷(perhydro-polysilazane,PSZ)、正硅酸乙酯(tetraethyl orthosilicate,TEOS)或甲硅烷基胺(silyl-amine),例如三甲硅烷基胺(trisilylamine,TSA)。这些前驱物可以与气体例如氧(O2)、臭氧(O3)、氮(N2)、氩(Ar)、氢(H2)、氦(He)和/或(NH3)组合。等离子体化学气相沉积(plasma-CVD)可用于可流动化学气相沉积。
如图23所示,在一些实施例中,使用光刻和蚀刻操作,在层间介电质56中且在三元合金层54和栅极电极45上方,形成开口,并且用导电材料(例如金属)填充开口以形成源极/漏极接触58和栅极电极60接触。在一些实施例中,源极/漏极接触58和栅极电极接触60包含选自铝、铜、钛和钨的一种或多种金属。在一些实施例中,在沉积接触金属前形成阻挡层于开口中。
图24-图31绘示根据本揭露的部分实施例的制造场效晶体管半导体装置200的另一种方法。用于形成根据本实施例的场效晶体管的许多操作与图5-图23中描述的方法相同或类似。主要区别在于,图5-图23绘示先形成栅极的方法,图24-图31绘示后形成栅极的方法。
如图24所示,使用沉积、光刻和蚀刻操作在半导体基板40上形成遮罩70。可以透过沉积遮罩材料层(例如氧化硅和/或氮化硅)并且图案化沉积的遮罩材料层来形成遮罩。半导体基板40可以由本文揭露的任何材料形成。
如图25所示,透过将掺杂剂注入到半导体基板40中,分别在遮罩70相对两侧上形成间隔开的源极/漏极区域46。在一些实施例中,源极/漏极区域46包含浓度大于1020原子·厘米-3(1020atoms·cm-3)的掺杂剂。
参考图26,在源极/漏极区域46上形成厚度为约3纳米至约30纳米的第一金属层50。在部分实施例中,第一金属层50的厚度在约6纳米至约14纳米的范围内。在一些实施例中,第一金属层50是选自由镍、铂、金、钽、钆、钛、锗和硅组成的群组中的至少一种。
在第一金属层50上形成第二金属层52,其厚度约为3纳米至约30纳米。在部分实施例中,第二金属层52的厚度范围为约5纳米至约15纳米。在一些实施例中,第二金属层52是选自由镍、铂、金、钽、钆、钛、锗和硅组成的群组中的至少一种。第二金属是与第一金属不同的金属。
在一些实施例中,透过光刻和蚀刻操作去除沉积在遮罩70上表面上的部分的第一金属层50和部分的第二金属层52,从而将第一金属层50和第二金属层52限制为覆盖于源极/漏极区域46之上。
如图27所示,在一些实施例中,在沉积第二金属层之后,执行微波激活退火操作以形成与源极/漏极区域46接触的合金。微波激活退火操作包含将微波辐射72施加到半导体基板40、第一金属层50和第二金属层52。在一些实施例中,微波辐射在约1GHz至约30GHz的频率范围和约0.6kW至约4.4kW的功率下施加约40秒至约240秒。在其它实施例中,微波辐射以约1.2kW至约2.2kW的功率施加约80秒至约120秒。在部分实施例中,半导体装置200在惰性气体(例如氮气气体)中暴露于微波辐射。
如图28所示,将微波辐射施加到半导体装置200导致半导体装置200(包含第一金属层50和第二金属层52)的局部加热,如本文关于图7、图8、图20和图21所示,以产生三元合金层54。
如图29所示,去除遮罩70,并且在半导体基板40上形成栅极介电层42和栅极电极45。透过适当的图案化操作对栅极电极45进行图案化,包含光刻和蚀刻操作以形成栅极电极。
栅极介电层42由半导体基板材料的氧化物或氮化物形成,例如在一些实施例中为氧化硅或氧化锗。在一些实施例中,透过热氧化半导体基板的上表面形成氧化物,而在其他实施例中,透过包含化学气相沉积、低压化学气相沉积、等离子体增强化学气相沉积的沉积操作形成氧化物。在一些实施例中,栅极介电层42包含一层或多层高介电材料。高介电材料,例如,包含二氧化铪(HfO2)、硅氧化铪(HfSiO)、氮氧硅化铪(HfSiON)、钽氧化铪(HfTaO)、钛氧化铪(HfTiO)、锆氧化铪(HfZrO)、氧化锆(zirconium oxide)、氧化铝(aluminum oxide)、氧化钛(titanium oxide)、二氧化铪-氧化铝(HfO2-Al2O3)合金,其它合适的高介电材料和/或透过沉积操作形成的其组合,其中,沉积操作包含化学气相沉积、低压化学气相沉积、等离子体增强化学气相沉积。在一些实施例中,栅极介电层42包含在通道层和介电材料之间形成的界面层(未绘示)。
在一些实施例中,栅极电极45包含一个或多个导电材料层,例如多晶硅(polysilicon)、铝(Al)、铜(Cu)、钛(Ti)、钽(Ta)、钨(W)、钴(Co)、钼(Mo)、氮化钽(TaN)、硅化镍(NiSi)、硅化钴(CoSi)、氮化钛(TiN)、氮化钨(WN)、铝化钛(TiAl)、氮化铝钛(TiAlN)、氮化碳钽(TaCN)、碳化钽(TaC)、氮化硅钽(TaSiN)、金属合金或其它合适的材料和/或其组合。
在本揭露的部分实施例中,一个或多个功函数调整层(未绘示)位于栅极介电层42和栅极电极45之间。
如图30所示,在一些实施例中,在栅极电极45和源极/漏极区域46上形成层间介电质56。
如图31所示,在一些实施例中,使用光刻和蚀刻操作形成开口于层间介电质56和栅极介电层42中,并于三元合金层54上方,且形成开口在栅极电极45上方,其中,开口是用导电材料填满,使用例如形成源极/漏极接触58和栅极电极60接触的金属。在一些实施例中,源极/漏极接触58和栅极电极60包含从由铝、铜、钛和钨组成的群组中的一种或多种金属。在一些实施例中,在沉积接触金属之前,于开口中形成阻挡层。
本揭露部分实施例的方法适用于平面晶体管装置和鳍式场效晶体管装置。图32A-图34B绘示根据本揭露部分实施例的制造鳍式场效晶体管装置300的方法。
在图32A中绘示鳍式场效晶体管装置300的平面图(俯视图)。鳍式场效晶体管装置300包含设置在鳍状结构80上的栅极电极结构85。图32B是对应于图32A中A-A'线的剖视图。图32C是对应于图32中B-B'线的剖视图。图32D是对应于图32中C-C'线的剖视图。
如图32A-图32D所示,栅极电极结构85包含栅极电极84、绝缘栅极侧壁86和栅极介电层88。鳍状结构80从层间介电质90中突出。在部分实施例中,鳍状结构80是透过图案化半导体基板92而形成。鳍状结构80包含在栅极电极结构85的相对侧上的源极/漏极区域82和在栅极电极结构85下面的通道区域83。透过光刻和蚀刻操作去除沉积在栅极电极84上和沉积在栅极绝缘侧壁86上表面的部分第一金属层94和部分第二金属层96,从而将第一金属层94和第二金属层96限制为覆盖在源极/漏极区域82上。通道区域83是从层间介电层90中突出的鳍状结构80的一部分。
在源极/漏极区域82上形成第一金属层94,在第一金属层94上形成第二金属层96。如图19和图26所描述,在部分实施例中,第一金属层94形成为约3纳米至约30纳米的厚度,并且在其他实施例中,第一金属层94的厚度在约6纳米至约14纳米的范围内。在一些实施例中,第一金属层94是选自由镍、铂、金、钽、钆、钛、锗和硅组成的群组中的至少一种。第二金属层96在第一金属层94上形成为约3纳米至约30纳米的厚度。在某些实施例中,第二金属层96的厚度在约5纳米至约15纳米的范围内。在一些实施例中,第二金属层96是选自由镍、铂、金、钽、钆、钛、锗和硅组成的群组中的至少一种。第二金属是与第一金属不同的金属。
图33A是对应于图32A中B-B'线的剖面图。图33B是对应于图32A中的C-C'线的剖视图,执行微波激活退火操作以形成与源极/漏极区域82接触的合金。微波激活退火操作包含将微波辐射72施加到鳍状结构80、第一金属层94和第二金属层96。在一些实施例中,微波辐射在约1GHz至约30GHz的频率范围以及约0.6kW至约4.4kW的功率下施加约40秒至约240秒。在其它实施例中,以约1.2kW至约2.2kW的功率施加约80秒至约120秒。在某些实施例中,鳍式场效晶体管装置300在惰性气体(例如氮气气体)中暴露于微波辐射。
如图34A、图34B所示,将微波辐射施加到鳍式场效晶体管装置300会引起鳍式场效晶体管装置300(包含第一金属层94和第二金属层96)的局部加热,如本文关于图20、图21、图27和图28所述,以产生三元合金层98。图34A对应于图32A的B-B'线。图34B对应于图32A的C-C'线。
应当理解,可以在本文描述的过程之前,期间和之后提供附加操作,并且对于该方法的附加实施例,可以替换或消除上述操作中的一些操作。操作/过程的顺序可以是可互换的。还应当理解,所示的装置经历进一步处理以形成各种特征,例如互连金属层,介电质层,钝化层等。
在一些实施例中,当半导体装置10、100、200和鳍式场效晶体管装置300暴露于微波激活退火时,半导体装置10、100、200和鳍式场效晶体管装置300是设置在半导体晶片400上。如图35所示,在部分实施例中,半导体晶片400设置在微波系统410中。微波系统410可以包含微波发生器420,微波发生器420以约0.6kW至约4.4kW的功率产生在约1GHz至约30GHz范围内的频率的微波460,以及处理室430,其使半导体晶片400暴露于微波辐射。处理室430包含设置在半导体晶片400的相对侧上的多个感受板440和石英板450。在一些实施例中,感受板440由诸如掺杂硅或掺杂碳化硅的半导体材料形成。
快速热退火可以降解金属表面以及合金接触和半导体基板之间的界面。依据本揭露部分实施例的微波活化退火可以防止由快速热退火引起的界面粗糙度和严重的附聚作用(agglomeration)。根据本揭露部分实施例的微波激活退火提供比快速热退火在更低的温度下均匀加热。微波激活退火可以提供具有改进的接面界面、表面品质和降低的接触电阻的浅接面。与快速热退火相比,微波激活退火的相对低的温度还抑制从源极/漏极区域的掺杂剂扩散。
在某些实施例中,根据本揭露的微波激活退火可以改善p型场效晶体管装置中的硅、锗、硅锗半导体基板上的肖特基接触,并且可以改善n型场效晶体管(NFET)中的硅、锗、硅锗半导体基板上的欧姆接触。
本揭露的一方面是提供一种制造半导体装置的方法,包含下列步骤。先形成第一金属层于半导体基板上,再形成第二金属层于第一金属层上,其中第二金属层由与第一金属层不同的金属形成。之后,施加微波辐射于半导体基板、第一金属层以及第二金属层,以形成合金,其包含第一金属层、第二金属层以及半导体基板的成分。
在本揭露制造方法的一实施例中,其中半导体基板更包含彼此间隔开的一对源极/漏极区域,并且在形成第一金属层时,第一金属层是设置在源极/漏极区域上。
在本揭露制造方法的一实施例中,其中微波辐射以约0.6kW至约4.4kW的功率施加约40秒至约240秒。
在本揭露制造方法的一实施例中,其中微波辐射以约1.2kW至约2.2kW的功率施加约80秒至约120秒。
在本揭露制造方法的一实施例中,其中半导体基板包括硅、锗和硅锗。
在本揭露制造方法的一实施例中,其中第一金属层和第二金属层选自镍、铂、金、钽、钆、钛、锗和硅及其组合。
在本揭露制造方法的一实施例中,其中第一金属层包含铂,第二金属层包括镍。
本揭露的另一方面是提供一种制造半导体装置的方法,包含下列步骤。先形成栅极结构于半导体基板的第一区域,接着,形成源极/漏极区域于半导体基板的第二区域,其中第二区域位于第一区域的相对侧上。然后,形成第一金属层于源极/漏极区域,之后,形成第二金属层于第一金属层上,其中第二金属层由与第一金属层不同的金属形成。最后,施加微波辐射于半导体基板、第一金属层以及第二金属层,以形成合金,其包含第一金属层、第二金属层以及半导体基板的成分。
在本揭露制造方法的一实施例中,其中第一金属层透过溅射操作形成。
在本揭露制造方法的一实施例中,其中第一金属层包含厚度为约6纳米至约14纳米的层。
在本揭露制造方法的一实施例中,其中第二金属层透过物理气相沉积操作形成。
在本揭露制造方法的一实施例中,其中所述第二金属层包含厚度为约5纳米至约15纳米的层。
在本揭露制造方法的一实施例中,其中合金是NiGePt2三元合金。
在本揭露制造方法的一实施例中,其中场效应晶体管是平面场效应晶体管。
在本揭露制造方法的一实施例中,其中半导体基板包含形成在其上的至少一个鳍,源极/漏极区域形成在至少一个鳍上,并且栅极结构覆盖至少一个鳍。
本揭露的另一方面是提供一种制造半导体装置的方法,包含下列步骤。首先,在半导体基板中形成一对间隔开的源极/漏极区域。接着,在源极/漏极区域上形成第一金属层,之后,在第一金属层上形成第二金属层,其中,第二金属层由与第一金属层不同的金属形成。施加微波辐射于半导体基板、第一金属层和第二金属层,以在源极/漏极区域上形成包含第一金属层、第二金属层和半导体基板的成分的合金。之后,在半导体基板上方形成高介电绝缘层,并且在间隔开的源极/漏极区域之间的区域中的高介电绝缘层上方形成导电金属层。接着,在源极/漏极区域上形成导电接触。
在本揭露制造方法的一实施例中,其中导电接触包含从由铝、铜、钛和钨组成的组中选择的至少一种金属。
在本揭露制造方法的一实施例中,其中微波辐射以约0.6kW至约4.4kW的功率施加约40秒至约240秒。
在本揭露制造方法的一实施例中,其中透过溅射沉积铂至约6纳米至约14纳米的厚度来形成第一金属层。
在本揭露制造方法的一实施例中,其中第二金属层透过物理气相沉积沉积镍至约5纳米至约15纳米的厚度形成。
前述概述了几个实施例或示例的特征,使得本领域具通常知识者可以更好地理解本揭露的方面。本领域具通常知识者应当理解,他们可以容易地使用本揭露作为设计或修改,以用于实现与本文介绍的实施例或示例的相同目和/或实现相同优点的其他过程和结构的基础。本领域具通常知识者还应当认识到,这样的等同结构不脱离本揭露的精神和范围,并且在不脱离本揭露的精神和范围的情况下,它们可以进行各种改变,替换和更改。
Claims (14)
1.一种制造半导体装置的方法,其特征在于,包含:
形成一第一金属层于一半导体基板上,其中该第一金属层包含厚度为6纳米至14纳米的铂;
形成一第二金属层于该第一金属层上,其中该第二金属层包含厚度为5纳米至15纳米的镍;以及
施加微波辐射于该半导体基板、该第一金属层以及该第二金属层,导致该第一金属层以及该第二金属层的局部加热,使得该第一金属层的金属和该第二金属层的金属扩散到该半导体基板以形成一合金,该合金包含该第一金属层、该第二金属层以及该半导体基板的成分,
其中该微波辐射以0.6kW至4.4kW的功率施加40秒至240秒,该合金是NiGePt2三元合金。
2.如权利要求1所述的方法,其中该半导体基板还包含彼此间隔开的一对源极/漏极区域,并且在形成该第一金属层时,该第一金属层是设置在该对源极/漏极区域上。
3.如权利要求1所述的方法,其中该微波辐射施加80秒至120秒。
4.如权利要求1所述的方法,其中该半导体基板包括锗或硅锗。
5.如权利要求1所述的方法,其中该第一金属层透过溅射操作形成。
6.如权利要求1所述的方法,其中该微波辐射以1.2kW至2.2kW的功率施加。
7.一种制造场效应晶体管的方法,其特征在于,包含:
形成一栅极结构于一半导体基板的一第一区域;
形成多个源极/漏极区域于该半导体基板的一第二区域,其中该第二区域位于该第一区域的相对侧上;
形成一第一金属层于所述多个源极/漏极区域,其中该第一金属层包含厚度为6纳米至14纳米的铂;
形成一第二金属层于该第一金属层上,其中该第二金属层包含厚度为5纳米至15纳米的镍;以及
施加微波辐射于该半导体基板、该第一金属层以及该第二金属层,导致该第一金属层以及该第二金属层的局部加热,使得该第一金属层的金属和该第二金属层的金属扩散到该半导体基板以形成合金,该合金包含该第一金属层、该第二金属层以及该半导体基板的成分,
其中该微波辐射以1.2kW至4.4kW的功率施加40秒至240秒,该合金是NiGePt2三元合金。
8.如权利要求7所述的方法,其中该第一金属层透过溅射操作形成。
9.如权利要求7所述的方法,其中该第二金属层透过物理气相沉积操作形成。
10.如权利要求7所述的方法,其中该场效应晶体管是平面场效应晶体管。
11.如权利要求7所述的方法,其中该半导体基板包含形成在其上的至少一个鳍,所述多个源极/漏极区域形成在至少一个鳍上,并且该栅极结构覆盖该至少一个鳍。
12.一种制造半导体装置的方法,其特征在于,包含:
在一半导体基板中形成一对间隔开的源极/漏极区域;
在该对源极/漏极区域上形成一第一金属层,其中该第一金属层包含厚度为6纳米至14纳米的铂;
在该第一金属层上形成一第二金属层,其中该第二金属层包含厚度为5纳米至15纳米的镍;
施加微波辐射于该半导体基板、该第一金属层和该第二金属层,导致该第一金属层以及该第二金属层的局部加热,使得该第一金属层的金属和该第二金属层的金属扩散到该半导体基板,以在该对源极/漏极区域上形成包含该第一金属层、该第二金属层和该半导体基板的成分的一合金;
在该半导体基板上方形成一高介电绝缘层,并且在间隔开的该对源极/漏极区域之间的区域中的该高介电绝缘层上方形成一导电金属层;以及
在该对源极/漏极区域上形成一导电接触,
其中该微波辐射以1.2kW至4.4kW的功率施加40秒至240秒,该合金是NiGePt2三元合金。
13.如权利要求12所述的方法,其中该导电接触包含从由铝、铜、钛和钨组成的组中选择的至少一种金属。
14.如权利要求12所述的方法,其中该微波辐射施加80秒至120秒。
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