TWI751272B - 用於基板偏壓原子層沉積之具有增強電絕緣的沉積方法以及晶圓卡盤系統 - Google Patents
用於基板偏壓原子層沉積之具有增強電絕緣的沉積方法以及晶圓卡盤系統 Download PDFInfo
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Abstract
一種用以執行在基板上形成導電膜之基板偏壓原子層沉積製程的晶圓卡盤系統，其包含設置以承載基板之一導電基板載台，以及包含承載基板載台之一導電基座。一電絕緣層係如三明治般夾在導電基板載台與導電基座之間。電絕緣層具有一外緣以及形成於外緣並沿著外緣延伸之一邊緣凹部。邊緣凹部的尺寸被設置以防止導電膜鍍覆邊緣凹部的整個內部，藉此保持導電基板載台與導電基座之間的電絕緣。
Description
本發明是關於原子層沉積(ALD)，特別是關於用於基板偏壓原子層沉積之具有增強電絕緣的沉積方法以及晶圓卡盤系統。
原子層沉積(ALD)是一種薄膜沉積技術，其將基板依序暴露於多個不同的化學及/或高能環境以於基板的表面形成薄膜。ALD製程的概述係描述於George所著之一篇名為“Atomic Layer Deposition：an Overview,”Chem.Rev.2010,110,pp 111-113的文章中(2009年11月20日發表於網路)，且該文於此被引用。ALD製程也描述在美國專利公告本第7,128,787號中，該專利於此被引用。一例示的ALD系統也揭露在美國專利公開本第2006/0021573號、美國專利公告本第8,202,575號以及PCT公開本第WO 2015/080979號中，上述專利於此亦被引用。
典型的ALD製程包含承載一基板於位於反應腔室內之一卡盤上。ALD製程包含對反應腔室抽真空，然後導入一前驅物氣體。一例示的前驅物氣體係包含金屬。所述金屬係化學吸附於基板表面上之預先存在的化學部分。吹掃循環(例如以惰性氣體)隨後被用來移除過量的前驅物氣體以及反應
產物。第二前驅物隨後被導入反應腔室，其中第二前驅物係對第一反應物之化學吸附部分具有反應性。第二吹掃循環移除過量的第二前驅物氣體以及反應產物。此製程可以重複進行以緩慢地在基板表面上逐層地建構起所述薄膜。ALD製程可被控制到次原子層(sub-atomic layer)厚度。
ALD製程是具有高度保形性的(conformal)，意指膜層會緊密地跟隨基板表面的形貌。這在很多應用中是很重要的特性，例如半導體製程，其中基板在形貌上可以有很大的變化，包含可以有高特徵比的溝槽。
ALD製程可以被用來沉積不同形式的導電膜。對於一給定的導電膜而言，沉積製程可以利用RF電壓對基板施加偏壓來調整，以增加沉積速率。所述偏壓典型地係透過使用反應腔室內承載基板之一導電基板載台以及提供導電基板載台一偏壓來實現。
不幸地，導電膜會沉積在導電基板載台以及電絕緣層的側邊，而在導電基板載台與卡盤的主體之間形成短路。
本發明的其中一概念為一種晶圓卡盤系統，適用於執行形成一導電膜於一基板上之一基板偏壓原子層沉積(ALD)製程。該晶圓卡盤系統包含：一導電基板載台，設置以承載該基板；一導電基座；及一電絕緣層，如三明治般夾於該導電基板載台與該導電基座之間，且具有一外緣，至少一邊緣凹部形成於該外緣且沿該外緣延伸，該至少一邊緣凹部具有一內部，且該至少一邊緣凹部的尺寸係足以在基板偏壓ALD製程中防止該導電膜鍍覆該至少一邊緣凹部之該內部的整體。
本發明的另一概念為包含上述晶圓卡盤系統之一ALD系統，其更包含一具有一內部之一反應腔室，其中，該晶圓卡盤系統係配置於反應腔室之內部。
本發明的另一概念為一種電絕緣層，適用於一晶圓卡盤系統，該晶圓卡盤系統用以執行基板偏壓ALD製程以沉積一導電膜。該絕緣層包含：一體成形之一碟體，由單一電絕緣材料所製成，該碟體具有一外緣以及具有一厚度TH，且2.5mm
TH
12.7mm；及一凹部，形成於該外緣內並沿該外緣延伸，該邊緣凹部具有一高度尺寸h，且0.25mm
h
1.27mm，該邊緣凹部具有一深度尺寸d，且5.1mm
d
101.6mm，同時d/h的條件為20
d/h
100。
本發明的另一概念為一種電絕緣層，適用於一晶圓卡盤系統，該晶圓卡盤系統用以執行一基板偏壓原子層沉積(ALD)製程以沉積一導電膜，該絕緣層包含：一上片體，由電絕緣材料或導電材料所製成；一下片體，由電絕緣材料或導電材料所製成；及一中片體，由電絕緣材料所製成，且如三明治般夾於該上片體與該下片體之間以定義具有一外緣之一層狀結構，其中，該中片體的尺寸被設置以能定義一邊緣凹部於該外緣內，且該邊緣凹部沿該外緣延伸；其中，該邊緣凹部具有一高度尺寸h，且0.25mm
h
1.27mm，該邊緣凹部具有一深度尺寸d，且5.1mm
d
101.6mm，同時d/h的條件為20
d/h
100。
附加的特徵和優點在以下的實施方式中進行描述，並且對於本領域的技術人員來說從說明書中部分將是顯而易見的，或者透過將在說明書、申請專利範圍以及圖式中所描述的實施例實現。應能理解的是，以上的總體描述以及以下的實施方式僅僅是例示性的，並且旨在提供一種用來理解申請專利範圍本質的概述或框架。
10:ALD系統
14:反應腔室
16:側壁
18:內部
100:晶圓卡盤系統
110:基板載台
112:上表面
114:下表面
116:外緣
120:基座
122:上表面
124:下表面
126:外緣
130:加熱器
150:電絕緣層
151:本體
152:上表面
154:下表面
156:外緣
160:凹部/邊緣凹部
161:分支
162:上壁
164:下壁
166:端壁
167:內部/凹部內部
168:角落
170:未鍍覆部分
172:間隙
182:上片體
183:中片體
184:下片體
186:中心片體
187:周緣
188:外環片體
189:內緣
190:接合特徵
192:黏著劑
200:電壓源
202:電壓訊號
20:電漿源
22:電漿
40:基板
42:上表面
50:導電膜/ALD膜
60:前驅物氣體源
62:前驅物氣體/第一前驅物氣體
80:前驅物氣體源
82:前驅物氣體/第二前驅物氣體
90:惰性氣體源
91:氣體管線
92:惰性氣體
96:真空系統
A1:中心軸
A2:中心軸
CH:中心孔洞
D:直徑
TH:厚度
圖1為適用於執行基板偏壓原子層沉積(ALD)之一例示原子層沉積系統的示意圖；圖2A為本發明之一例示晶圓卡盤系統之俯視圖；圖2B為圖2A之例示晶圓卡盤系統之側視圖；圖3A為使用於圖2A與圖2B之晶圓卡盤系統之本發明的一例示電絕緣層的上方等角視圖；圖3B為電絕緣層之一邊緣部分的一放大剖面視圖，繪示出邊緣凹部之一例示的剖面結構；圖3C為晶圓卡盤系統之一邊緣部分的一放大剖面視圖，繪示出ALD導電膜究竟是如何鍍覆於晶圓卡盤系統上，以及電絕緣層中之邊緣凹部究竟是如何作用以於導電膜中形成斷路來維持導電基板載台與卡盤基座之間的電絕緣；圖4A與圖4B類似圖3A與圖3B，其繪示出包含多個邊緣凹部之電絕緣層的一實施例；圖5A至圖5D類似圖3B，其繪示出形成於電絕緣層中之邊緣凹部的其他例示結構；圖6為形成自以層狀結構配置之三片體之一例示電絕緣層；圖7A為形成自二片體之一例示電絕緣層的俯視圖，二片體係指一外環片體與一中心片體，其並排地顯示出所述二片體；圖7B為外環片體與中心片體的邊緣部分的放大剖面視圖；
圖8類似圖3，其繪示出一實施例，邊緣凹部氣動地耦合至惰性氣體源，因而惰性氣體可以自邊緣凹部徑向地向外流動。
現請參考本發明之各個不同的實施例，其也在附圖中予以繪示說明。無論何時，在所有圖式中相同或相似元件符號及標記係用以意指相同或相似部件。圖式並非以原比例繪示，且所屬技術領域中具有通常知識者將能理解圖式已經被簡化以繪示本發明之重要概念。
以下所提出的申請專利範圍係構成實施方式的一部份。
ALD系統
圖1為一例示原子層沉積(ALD)系統10的示意圖，ALD系統10包含於此所揭露且以下會詳加描述之晶圓卡盤系統100。晶圓卡盤系統100適用於承載具有上表面42之基板40。一例示的ALD系統10係座落於麻薩諸塞州沃爾瑟姆市之美商精微超科技公司(Ultratech,Inc.,Waltham,Massachusetts)所提供之Fiji系列模組化之高真空電漿基礎ALD系統的其中一種。晶圓卡盤系統100也可以用在其他形式的ALD系統，例如非電漿ALD系統。晶圓卡盤系統100包含電壓源200，當使用ALD系統10來執行ALD製程以沉積導電膜50，其提供偏壓至基板40。例示的導電膜包含W、TiN、TaN、MoN、NbN、ZnO以及其他類似薄膜。對基板40施加一偏壓的ALD製程於此係稱為「基板偏壓ALD」或「偏壓ALD」。
ALD系統10包含具有沿Z軸方向延伸之中心軸A1之一反應腔室14。反應腔室14係由至少一側壁16所定義。反應腔室14包含一腔室內部(以下
統稱內部)18。ALD系統10可以包含一電漿源20，其可操作地相對於反應腔室14設置並形成電漿22。
ALD系統10也包含前驅物氣體源60以及80，其個別設置以提供(例如：導入)前驅物氣體62以及82。在一實施例中，前驅物氣體62與82的導入可以藉由一控制器(圖未示)的操作來管理，或者可以透過手動方式來實現。ALD系統10也包含一惰性氣體源90，其提供一惰性氣體92(例如：氮氣、氬氣等)以吹掃內部18。
ALD系統10也包含真空系統96以淨空內部18以初始化以ALD為基礎的方法，以及在不同的ALD步驟中幫助移除過量的前驅物氣體62與82。
晶圓卡盤系統
圖2A與圖2B分別為本發明之一例示晶圓卡盤系統100的俯視圖與側視圖。晶圓卡盤系統100包含沿Z軸方向延伸之中心軸A2，且在一實施例中，其係與反應腔室14之中心軸A1同軸。
在一實施例中，晶圓卡盤系統100包含基板載台110，其具有上表面112、下表面114以及外緣116。基板載台110之上表面112用以承載基板40。基板載台110由導電材料所製成(例如：銅、不銹鋼等)，且電性連接於電壓源200。電壓源200提供電壓訊號202至基板載台110進而傳達至基板40，藉此對基板40相對於地施以偏壓。
對於某些形式的ALD反應來說，基板40之偏壓可以用來吸引前驅物氣體中的選定離子，以增強ALD製程(例如增加沉積速率)及/或改變膜的特性，例如改變導電度、改變膜的密度、改變膜的內應力、或者改變膜的超導特性。基板載台110的尺寸被調整以可操作地承載不同尺寸的基板，包含傳統100
mm、200mm、或300mm甚至更大的半導體晶圓。在一實施例中，基板載台110可以具有大約6.4mm的厚度。
晶圓卡盤系統100也包含一基座120，其具有一上表面122、一下表面124與一外緣126。基座120典型地是由導電材料所製成。在一實施例中，基座120包含加熱器130，用來加熱基座120以及基板載台110，藉此加熱基板40至適合ALD製程之一初始溫度。基座120以及反應腔室14係電性接地。在一實施例中，基座120可以具有6.4mm至76.2mm的厚度，且具有和基板載台110實質相匹配的直徑。基座120可以由銅、不銹鋼或者類似的導電材料所製成。
晶圓卡盤系統110也包含電絕緣層150，其如三明治般夾於基座120與基板載台110之間，且令導電的基座120電絕緣於導電的基板載台110。電絕緣層150具有一本體151、一上表面152、一下表面154以及一外緣156。在一實施例中，電絕緣層150係為平面且具有厚度TH與直徑D。在一實施例中，厚度TH滿足2.5mm
TH
12.7mm。
用以形成電絕緣層150的材料有兩個主要要求，其一為電絕緣，其二為能夠承受給定ALD製程的高溫，典型地係在25℃至500℃。電絕緣層150的例示材料包含玻璃、陶瓷、塑膠、熱塑性塑膠、聚醯胺(尼龍/nylon)、聚亞醯胺(凱通/Kapton)、環氧樹脂、高分子以及聚碳酸酯。在一實施例中，電絕緣層150係為一薄碟形體。在一實施例中，電絕緣層係為一體成形，亦即由單一材料所製成的單一片體。在其他以下所討論的實施例中，電絕緣層係形成自二個或更多的個別片體，包含由不同材料所製程的片體。
圖3A為一例示電絕緣層150的上方視圖，圖3B為電絕緣層150之一邊緣部分的一放大剖面視圖。電絕緣層150包含至少一凹部160，其形成於外緣
156中，因此在此稱為「邊緣凹部」。在一實施例中，所述至少一邊緣凹部160徑向地朝內並朝向中心軸A2。在一實施例中，所述至少一邊緣凹部160具有一方向分量徑向地朝內並朝向中心軸A2。除非特別註明，否則為了方便討論，以下係以單一邊緣凹部160來進行說明。
邊緣凹部160沿著整個外緣156延伸，如圖2A中的虛線所標示同時也顯示於圖3A中。如圖3B的放大x-z剖面視圖，在邊緣凹部160的一實施例中，其具有一矩形截面。在一實施例中，邊緣凹部160具有定義出凹部內部167之一上壁162、一下壁164以及一端壁166。邊緣凹部160具有自外緣156徑向地向內量測而得的一深度尺寸d。邊緣凹部160也具有言z軸方向量測的一高度尺寸h。如以下所討論，在其他實施例中，深度尺寸與高度尺寸(d,h)可以隨著位置而改變，亦即不需要保持固定不變。在此等實施例中，深度尺寸與高度尺寸(d,h)可以視為是最小的尺寸。
如以上所述，ALD製程具有高度的保形性。ALD製程的結果也不只是在基板的上表面42上進行鍍覆。因此，實際上，ALD製程將不僅僅是沉積ALD膜50於基板的上表面42，同時也會將ALD膜50鍍覆在裸露的基板載台110的上表面112、基板載台110的外緣116、電絕緣層150的外緣156、以及基座120的外緣126上。當ALD膜50可以導電，ALD膜50可以在導電的基板載台110以及導電的基座120之間透過電絕緣層150的外緣156提供一電子路徑，因而產生短路，其對於偏壓ALD的應用會造成問題。
因為ALD製程具有保形性，且可以覆蓋高特徵比的結構，因此邊緣凹部160必須具有足夠高的特徵比AR=d/h，始足以讓ALD膜50無法鍍覆整個邊緣凹部的上壁162、下壁164以及端壁166。如果此種鍍覆的情況發生的話，那麼
如同上述，導電的ALD膜50將能夠在基板載台110與基座120之間定義出一電子路徑而在電絕緣層150的周遭產生短路。因此，在一實施例中，邊緣凹部160具有特徵比AR=d/h，其大小足以令給定的ALD製程能夠防止短路的情況形成。
特徵比AR=d/h對於簡單的矩形凹部160是最合適的。更複雜的邊緣凹部可以使用等效特徵比ARE，其可以透過模擬或者實驗而憑經驗推導出來。
圖3C類似圖3B，其顯示出邊緣凹部160在晶圓卡盤系統100上之一導電ALD膜50之沉積過程中所發揮出的功效。導電的ALD膜50(或者是其經修飾後的變形體)鍍覆裸露的基板載台110的上表面112、基板載台110的外緣116、電絕緣層150的外緣、以及基座120的外緣126。導電的ALD膜50也會試圖鍍覆邊緣凹部160的內部167，亦即鍍覆內部的上壁162、下壁164以及端壁166。然而，因為邊緣凹部160的特徵比AR足夠大，導電的ALD膜50僅能夠朝端壁166而延伸入凹部內部167的部分路徑上，而在凹部內部167留下一未鍍覆部分170，其在導電的ALD膜50中定義出一間隙172。導電的ALD膜50中的間隙172防止了導電的基板載台110與導電的基座120之間經由絕緣層150而發展出短路。
實驗證明，對大多數形成導電的ALD膜50的ALD製程來說，適當的特徵比AR為AR
50。而對於某些膜來說，AR
50是適當的。在其他實施例中，特徵比可以被設定為AR
100。因此，在不同的實施例中，特徵比的範圍可以是20
AR
100或者50
AR
100。
在一實施例中，高度尺寸h的範圍為0.25mm
h
1.27mm，深度尺寸d的範圍為5.1mm
d
152.4mm或者是5.1mm
d
101.6mm或者是5.1mm
d
25.4mm。因此，在一實施例中，h=2.5mm且d=50h=12.7mm。
特徵比AR的上限至少在某種程度上可能會受限於邊緣凹部160會對從基座120經由電絕緣層150至基板載台110的熱傳導造成影響。一般較佳地是希望基板40具有實質均勻的溫度，例如在5%的差異內或者更佳的是在2%或者1%的差異內。已證實，此種均溫性要求並不會顯著地限制邊緣凹部160的尺寸與形狀。
當邊緣凹部160的深度尺寸d非常大時，特徵比AR的上限至少在某種程度上也可能會受限於基板載台110的物理穩定度。此外，特徵比AR的上限也可能被既要讓邊緣凹部160非常薄(小h)同時又不能讓上壁162與下壁164相接觸的技術能力(亦即製造能力限制)所限制。
圖4A與圖4B類似圖3A與圖3B，繪示出包含多個邊緣凹部160之電絕緣層150的一實施例，四個邊緣凹部160係為例示。多個邊緣凹部160提供額外的電絕緣。
圖5A至圖5D類似圖3B，其繪示出形成於電絕緣層150中之邊緣凹部160的其他例示結構。圖5A繪示出邊緣凹部160的例示配置，其在徑向地相對於電絕緣層150具有T形截面，這使得導電的ALD膜50更難以沉積在邊緣凹部160內，因為ALD沉積必須穿過兩個角落168並進入邊緣凹部160的兩個不同分支61。圖5B和5C類似於圖5A，並且分別繪示出邊緣凹部160的兩個複雜結構，其各包含額外的角落168，所述額外的角落168定義額外的分支161，這使得導電的ALD膜50在個別邊緣凹部160的內部167內深入沉積變得更加困難。
圖5D繪示出一例示的邊緣凹部160，其包含彎曲的上、下壁162、164以及彎曲的端壁166。
一般而言，邊緣凹部160的截面可以具有任何合理的配置。在一實施例中，電絕緣層150係使用傳統三維列印技術的三維列印製程所形成。目前三維列印技術已能夠定義十分複雜以及如同迷宮般的邊緣凹部160，例如，包含多個分支的配置。在使用傳統研磨技術所形成的邊緣凹部160的實施例中，可能較適合使用簡單的邊緣凹部的配置，例如圖3B所示地矩形截面形狀。
圖6為一例示電絕緣層150，其係由三個分離的片體所組成，亦即上片體182、下片體184、以及如三明治般夾於上遍體182與下片體184之間的中片體183。在一實施例中，至少中片體183是由電絕緣材料所製成。邊緣凹部160可以透過讓中片體183小於上片體182與下片體184(亦即具有較小的直徑)來定義。在一實施例中，上片體182與下片體184並不需要絕緣，例如可以是由鋁或者不銹鋼所製成。在一實施例中，上片體1182、中片體183與下片體184透過耐高溫的黏著劑而固定而形成一層狀結構。在另一實施例中，上片體182、中片體183與下片體184可以透過螺絲或者其他固定手段來固定。
圖7A為由二片體所形成之另一例示電絕緣層150的俯視圖，二片體係指具有周緣187之中心片體186以及具有內緣189之外環片體188。內緣189定義一中心孔洞CH，中心孔洞CH的尺寸恰可容置中心片體186，中心片體186的周緣187位於最靠近(亦即接觸)外環片體188之內緣189之處。
外環片體188是由絕緣材料製成且包含內緣189，並且也定義出邊緣凹部160形成於其中的外緣156。在一實施例中，中心片體186可以是由導電材料所製成的碟形體，例如鋁或不銹鋼。中心片體186也可以是由電絕緣材料所製成。請參照圖7B為的放大剖面視圖，外環片體188以及中心片體186可以包含互補的接合特徵190，其透過黏著劑192增進了片體彼此間的接合與固定。
圖8類似圖3，其繪示出電絕緣層150之一實施例，其中邊緣凹部160藉由氣體管線91氣動地連接至惰性氣體源90。氣體管線91讓惰性氣體92能夠在端壁166或者是接近端壁166的地方流入邊緣凹部160。由於反應腔室14之內部18的真空，惰性氣體92會流入凹部內部167，然後徑向地向外流動直到在邊緣156處離開邊緣凹部160為止。惰性氣體92的流動實質上防止了ALD氣體進入邊緣凹部160及沉積在內壁上。在這個電絕緣層150「被加壓的」實施例中，邊緣凹部160可具有小於「沒有被加壓的」實施例的特徵比AR。
例示的ALD製程
本發明的其中一概念為使用圖1所示的ALD系統10以及晶圓卡盤系統100來形成導電的ALD膜50。ALD製程包含可操作地承載基板40於位於反應腔室14內之晶圓卡盤系統100之基板載台110上，然後抽真空。所述方法可以包含透過加熱器130加熱基板40至一初始製程溫度。例示的初始溫度可以在20℃至500℃之範圍間。
然後一偏壓透過來自電壓源200之偏壓訊號200而被施加於基板載台110。例示的偏壓可以是直流電壓-100V至+100V，或者是一RF交流電壓。RF電壓可以具有範圍在10KHz至100MHz之間的頻率。RF訊號之峰對峰電壓係由功率設定(0瓦至300瓦)來決定，且可以在0瓦至600瓦的範圍間。偏電壓被設定為只有峰對峰電壓的一半。
然後，所述製程包含導入第一前驅物氣體62至腔室內部18，其中第一前驅物氣體包含金屬M。用ALD之包含金屬之前驅物氣體在本技術領域中係廣為人知，且可以包含例如鎢或鈦等金屬。第一前驅物氣體中的金屬M附著於基板的上表面42，亦即金屬M係化學吸附於基板表面上之預先存在的化學部分。
然後，所述製程包含使用吹掃氣體92而自腔室內部18中排出第一前驅物氣體。然後，所述製程包含導入可以和基板的上表面42上之化學吸附金屬相互反應之第二前驅物氣體82至腔室內部18中，以形成導電膜50之第一原子層。然後，上述製程被重複以逐層建構起導電膜50。所述製程也可以包含使用額外的前驅物氣體(亦即兩種以上的前驅物氣體)與吹掃步驟。
所述製程還包含沉積導電的ALD膜50於晶圓卡盤系統100之外緣上，其中包含沉積於電絕緣層150之外緣156且僅沉積於邊緣凹部160之內部的一部分，而於邊緣凹部160中留下一未鍍覆部分170以於導電膜50中定義一間隙172(例如，見圖3C)。間隙172用以於ALD製程中，維持基板載台110與基座120之間的電絕緣。
在一實施例中，所述製程可以包含讓吹掃氣體92自邊緣凹部160徑向地向外流動以避免前驅物氣體62與82進入邊緣凹部160中。
雖然本發明已以實施例揭露如上然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之專利申請範圍所界定者為準。
150‧‧‧電絕緣層
152‧‧‧上表面
154‧‧‧下表面
156‧‧‧外緣
160‧‧‧凹部/邊緣凹部
Claims (32)
- 一種晶圓卡盤系統，適用於執行形成一導電膜於一基板上之一基板偏壓原子層沉積(ALD)製程，該晶圓卡盤系統包含：一導電基板載台，設置以承載該基板；一導電基座；及一電絕緣層，如三明治般夾於該導電基板載台與該導電基座之間且具有一外緣，至少一邊緣凹部形成於該外緣且沿該外緣延伸，該至少一邊緣凹部具有一內部，且該至少一邊緣凹部的尺寸係足以在基板偏壓ALD製程中防止該導電膜鍍覆該至少一邊緣凹部之該內部的整體。
- 如請求項1所述之晶圓卡盤系統，其中該至少一邊緣凹部具有一高度尺寸h，且0.25mmh
1.27mm。
- 如請求項1所述之晶圓卡盤系統，其中該至少一邊緣凹部具有一深度尺寸d，且5.1mmd
101.6mm。
- 如請求項1所述之晶圓卡盤系統，其中該至少一邊緣凹部具有一特徵比AR，且AR20。
- 如請求項1所述之晶圓卡盤系統，其中該至少一邊緣凹部具有一特徵比AR，且50AR
100。
- 如請求項1所述之晶圓卡盤系統，其中該至少一邊緣凹部具有矩形截面。
- 如請求項1所述之晶圓卡盤系統，其中該電絕緣層具有一厚度TH，且2.5mmTH
12.7mm。
- 如請求項1所述之晶圓卡盤系統，其中該電絕緣層為一體成形且由單一電絕緣材料所製成。
- 如請求項1所述之晶圓卡盤系統，其中該至少一邊緣凹部包含至少一分枝。
- 如請求項1所述之晶圓卡盤系統，其中該電絕緣層係形成自一第一片體與一第二片體，該第一片體與該第二片體係由不同材料所製成，其中該不同材料的至少其中一者為電絕緣材料。
- 如請求項1所述之晶圓卡盤系統，其中該電絕緣層係形成自一第一片體、一第二片體與一第三片體，其中該第一片體、該第二片體與該第三片體的至少其中一者係由電絕緣材料所製成。
- 如請求項1所述之晶圓卡盤系統，其中該電絕緣層係選自一材料群組中的至少一種所製成，該材料群組包含：玻璃、陶瓷、塑膠、熱塑性塑膠、聚醯胺(尼龍/nylon)、聚亞醯胺(凱通/Kapton)、環氧樹脂、高分子及聚碳酸酯。
- 如請求項1所述之晶圓卡盤系統，其中該至少一邊緣凹部係為多個邊緣凹部。
- 如請求項1所述之晶圓卡盤系統，更包含：一惰性氣體源；及一氣體管線，將該惰性氣體源氣動連接於該至少一邊緣凹部的該內部。
- 一種原子層沉積(ALD)系統，包含：如請求項1所述之晶圓卡盤系統；及 一反應腔室，具有一內部，其中該晶圓卡盤系統係配置於該反應腔室之該內部。
- 一種電絕緣層，適用於一晶圓卡盤系統，該晶圓卡盤系統用以執行基板偏壓原子層沉積製程以沉積一導電膜，該絕緣層包含：一體成形之一碟體，由單一電絕緣材料所製成，該碟體具有一外緣以及具有一厚度TH，且2.5mmTH
12.7mm；及一邊緣凹部，形成於該外緣內並沿該外緣延伸，該邊緣凹部具有一高度尺寸h，且0.25mm
h
1.27mm，該邊緣凹部具有一深度尺寸d，且5.1mm
d
101.6mm，同時d/h的條件為20
d/h
100。
- 如請求項16所述之電絕緣層，其中該邊緣凹部包含複數分支。
- 如請求項16所述之電絕緣層，其中該邊緣凹部具有矩形截面形狀。
- 如請求項16所述之電絕緣層，其中該單一絕緣材料係選自一材料群組中的至少一種所製成，該材料群組包含：玻璃、陶瓷、塑膠、熱塑性塑膠、聚醯胺(尼龍/nylon)、聚亞醯胺(凱通/Kapton)、環氧樹脂、高分子及聚碳酸酯。
- 一種電絕緣層，適用於一晶圓卡盤系統，該晶圓卡盤系統用以執行一基板偏壓原子層沉積(ALD)製程以沉積一導電膜，該絕緣層包含：一上片體，由電絕緣材料或導電材料所製成；一下片體，由電絕緣材料或導電材料所製成；及 一中片體，由電絕緣材料所製成，且如三明治般夾於該上片體與該下片體之間以定義具有一外緣之一層狀結構，其中，該中片體的尺寸被設置以能定義一邊緣凹部於該外緣內，且該邊緣凹部沿該外緣延伸；其中，該邊緣凹部具有一高度尺寸h，且0.25mmh
1.27mm，該邊緣凹部具有一深度尺寸d，且5.1mm
d
101.6mm，同時d/h的條件為20
d/h
100。
- 如請求項20所述之電絕緣層，其中該上片體與該下片體係由導電材料所製成。
- 如請求項20所述之電絕緣層，其中該上片體、該中片體與該下片體係個別由電絕緣材料所製成。
- 如請求項22所述之電絕緣層，其中該上片體、該中片體與該下片體係由相同的電絕緣材料所製成。
- 一種電絕緣層，適用於一晶圓卡盤系統，該晶圓卡盤系統用以執行一基板偏壓原子層沉積(ALD)製程以沉積一導電膜，該絕緣層包含：一中心片體，由一電絕緣材料或一導電材料所製成，且具有一周緣；一外環片體，由一電絕緣材料所製成，且具有一內緣與一外緣，其中，該內緣定義一中心孔洞，該中心孔洞的尺寸恰可容置該中心片體以使該中心片體的周緣位於最靠近該外環片體之該內緣之處；及其中，一邊緣凹部形成於該外緣且沿該外緣延伸，該邊緣凹部具有一高度尺寸h，且0.25mmh
1.27mm，該邊緣凹部具有一深度尺寸d，且5.1mm
d
101.6mm，同時d/h的條件為20
d/h
100。
- 如請求項24所述之電絕緣層，其中該中心片體係由不銹鋼或鋁所製成。
- 一種原子層沉積(ALD)製程，適用於在一基板之一上表面形成一導電膜，該原子層沉積製程包含：於一ALD系統之一反應腔室內承載該基板於一晶圓卡盤系統上，該晶圓卡盤系統具有一導電基板載台、一導電基座以及一電絕緣層，該導電基板載台承載該基板，該電絕緣層如三明治般夾於該導電基板載台與該導電基座之間且具有一外緣，該電絕緣層還具有至少一凹部形成於該外緣，該至少一凹部具有一內部，且該至少一凹部的尺寸係足以防止該導電膜鍍覆該內部的整體；施加一偏壓於該導電基板載台，藉以給予該基板一偏壓；及交替地導入一第一前驅氣體與一第二前驅氣體，並且在導入該第一前驅氣體與該第二前驅氣體之間還加入一吹掃步驟，以於該基板之該上表面形成該導電膜，其中該導電膜也沉積於該電絕緣層之該外緣且僅沉積於該內部的一部分藉此在位於該凹部內之該導電膜中定義出一間隙，且該間隙位於該導電基板載台與該導電基座之間。
- 如請求項26所述之原子層沉積製程，其中該至少一凹部係為複數凹部。
- 如請求項26所述之原子層沉積製程，其中該至少一凹部具有一高度尺寸h，且0.25mmh
1.27mm，該凹部具有一深度尺寸d，且5.1mm
d
101.6mm，同時d/h的條件為20
d/h
100。
- 如請求項26所述之原子層沉積製程，更包含提供一惰性氣體至該至少一凹部之該內部中，使該惰性氣體流過位於該電絕緣層之該外緣之該至少一凹部之該內部。
- 如請求項26所述之原子層沉積製程，更包含自一單一電絕緣材料以一體成形的方式形成該電絕緣層。
- 如請求項26所述之原子層沉積製程，更包含自至少二片體形成該電絕緣層。
- 如請求項26所述之原子層沉積製程，更包含使用一三維列印製程來形成該電絕緣層。
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| CN (1) | CN110225997A (zh) |
| SG (1) | SG11201906817TA (zh) |
| TW (1) | TWI751272B (zh) |
| WO (1) | WO2018140394A1 (zh) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| EP3950211B1 (en) * | 2020-08-03 | 2024-05-15 | Toyota Jidosha Kabushiki Kaisha | Method of manufacturing a metal member |
| US20220208592A1 (en) * | 2020-12-31 | 2022-06-30 | Entegris, Inc. | Electrostatic chuck prepared by additive manufacturing, and related methods and structures |
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| TW200707695A (en) * | 2005-05-24 | 2007-02-16 | Toto Ltd | Electrostatic chuck |
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| GB2109010B (en) * | 1981-11-12 | 1985-11-20 | Advanced Semiconductor Mat | Spacer for conductive plase in rf plasma reactor used in chemical vapour deposition |
| EP0669644B1 (en) * | 1994-02-28 | 1997-08-20 | Applied Materials, Inc. | Electrostatic chuck |
| US5969934A (en) * | 1998-04-10 | 1999-10-19 | Varian Semiconductor Equipment Associats, Inc. | Electrostatic wafer clamp having low particulate contamination of wafers |
| US20020197402A1 (en) * | 2000-12-06 | 2002-12-26 | Chiang Tony P. | System for depositing a film by modulated ion-induced atomic layer deposition (MII-ALD) |
| US7871676B2 (en) | 2000-12-06 | 2011-01-18 | Novellus Systems, Inc. | System for depositing a film by modulated ion-induced atomic layer deposition (MII-ALD) |
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| US7592254B2 (en) | 2005-11-01 | 2009-09-22 | The Board Of Trustees Of The University Of Illinois | Methods for coating and filling high aspect ratio recessed features |
| JP5060324B2 (ja) | 2008-01-31 | 2012-10-31 | 株式会社日立国際電気 | 基板処理装置、半導体装置の製造方法及び処理容器 |
| JP4879929B2 (ja) * | 2008-03-26 | 2012-02-22 | 日本碍子株式会社 | 静電チャック及びその製造方法 |
| WO2010021890A2 (en) * | 2008-08-19 | 2010-02-25 | Lam Research Corporation | Edge rings for electrostatic chucks |
| US8425987B2 (en) | 2008-12-31 | 2013-04-23 | Intel Corporation | Surface charge enhanced atomic layer deposition of pure metallic films |
| JP5207996B2 (ja) * | 2009-01-20 | 2013-06-12 | 東京エレクトロン株式会社 | 基板載置台及び基板処理装置 |
| KR101986547B1 (ko) * | 2012-12-17 | 2019-06-07 | 삼성전자주식회사 | 정전척 및 이를 포함하는 기판 처리 장치 |
| JP6026306B2 (ja) * | 2013-02-05 | 2016-11-16 | 株式会社東栄科学産業 | 磁気メモリ用プローバチャック及びそれを備えた磁気メモリ用プローバ |
| TWI588286B (zh) | 2013-11-26 | 2017-06-21 | 烏翠泰克股份有限公司 | 經改良的電漿強化原子層沉積方法、周期及裝置 |
| CN107078086B (zh) | 2014-02-07 | 2021-01-26 | 恩特格里斯公司 | 静电夹具以及制造其之方法 |
| CN104878363B (zh) * | 2014-02-28 | 2017-07-21 | 北京北方微电子基地设备工艺研究中心有限责任公司 | 机械卡盘及等离子体加工设备 |
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2018
- 2018-01-23 US US15/877,809 patent/US10844488B2/en active Active
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- 2018-01-23 JP JP2019540422A patent/JP7111727B2/ja active Active
- 2018-01-23 KR KR1020197021696A patent/KR20190104040A/ko unknown
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- 2018-01-23 CN CN201880008633.3A patent/CN110225997A/zh active Pending
- 2018-01-23 SG SG11201906817TA patent/SG11201906817TA/en unknown
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| TW200707695A (en) * | 2005-05-24 | 2007-02-16 | Toto Ltd | Electrostatic chuck |
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|---|---|
| SG11201906817TA (en) | 2019-08-27 |
| US10844488B2 (en) | 2020-11-24 |
| EP3574126A4 (en) | 2020-10-28 |
| JP2020505515A (ja) | 2020-02-20 |
| US20180216229A1 (en) | 2018-08-02 |
| TW201840899A (zh) | 2018-11-16 |
| WO2018140394A1 (en) | 2018-08-02 |
| JP7111727B2 (ja) | 2022-08-02 |
| KR20190104040A (ko) | 2019-09-05 |
| CN110225997A (zh) | 2019-09-10 |
| EP3574126A1 (en) | 2019-12-04 |
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