TWI744220B - 用於接合應用的經塗佈銅(Cu)線 - Google Patents

用於接合應用的經塗佈銅(Cu)線 Download PDF

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TWI744220B
TWI744220B TW104140498A TW104140498A TWI744220B TW I744220 B TWI744220 B TW I744220B TW 104140498 A TW104140498 A TW 104140498A TW 104140498 A TW104140498 A TW 104140498A TW I744220 B TWI744220 B TW I744220B
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wire
core
coating
bonding
range
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TW104140498A
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TW201633481A (zh
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廖金枝
穆拉里 沙蘭加帕尼
平熹 楊
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新加坡商新加坡賀利氏材料私人有限公司
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Abstract

本發明係關於一種電線及一種製造之方法,該電線包含:至少一芯,其包含銅及元素磷;第一塗層,其由選自包含鈀、鉑及銀之群組的至少一種元素構成;另外塗層,其由選自銀及金之至少一種元素構成;其特徵在於符合以下條件中之至少一者:A1)該芯中的晶粒之平均粒度與該電線之直徑之比率在自0.14至0.28之範圍中且該平均粒度之相對標準差RSD小於0.9;或A2)該芯中的該等晶粒之再結晶度在自50%至95%之範圍中;或A3)孿晶間界之分率在自2%至25%之範圍中;或A4)該電線之該等晶粒中之18%至42%定向於<100>方向上且該電線之該等晶粒中之27%至38%定向於<111>方向上。

Description

用於接合應用的經塗佈銅(Cu)線
本發明係關於一種電線,其具有在自8μm至80μm之範圍中的一平均直徑,其中該電線包含具有一表面之至少一芯、具有一層表面之一第一塗層及一另外塗層,其中A)該芯包含銅及元素磷;B)該第一塗層由選自包含鈀、鉑及銀之群組的至少一種元素構成,其中該第一塗層疊加於該芯之該表面上;C)該另外塗層疊加於芯之該第一塗層之該層表面上,其中該另外塗層由選自銀及金之至少一種元素構成,且其中該另外塗層之組成不同於該第一塗層之組成;其特徵在於符合以下條件中之至少一個、兩個、三個或所有:A1)在縱向方向上量測的該芯中的晶粒之平均粒度與該電線之直徑之比率在自0.14至0.28(μm/μm)之範圍中,且該平均粒度之相對標準差小於0.9;或A2)在縱向方向上量測的該芯中的該等晶粒之再結晶度在自50%至95%之範圍中;或A3)在縱向方向上量測的孿晶間界(twin boundary)之分率在自2%至25%之範圍中;或A4)該電線之該等晶粒中之18%至42%定向於<100>方向上且該電線之該等晶粒中之27%至38%定向於<111>方向上,每一%係相對於具有平行於該電線之牽拉方向之定向的晶體之總數。本發明進一步係關於一種用於製造如前述之電線之方法,及係關於一種包含本發明之電線之電裝置。
在用於於半導體裝置製造期間電互連積體電路與印刷電路板的半導體裝置之製造中使用接合線。另外,接合線用於動力電子應用中以將電晶體、二極體及類似者與外殼之襯墊或接腳電連接。雖然接合線在一開始自金製造,但當今使用不太昂貴之材料,諸如,銅。雖然銅線提供非常良好的電及熱導率,但銅線之球接合以及楔形接合具有其難題。此外,銅線易受氧化。
關於電線幾何形狀,最常見的為圓形橫截面之接合線及具有或多或少矩形橫截面之接合帶。兩個類型之電線幾何形狀具有使其適用於特定應用之其優勢。因此,兩個類型之幾何形狀具有其市場份額。舉例而言,對於給定橫截面積,接合帶具有較大接觸面積。然而,帶之彎曲受到限制,且當接合時必須觀測到帶之定向,以便達成該帶與其接合至之元件之間的可接受之電接觸。轉至接合線,此等對彎曲更有可撓性。然而,接合涉及電線在接合製程中之焊接及/或較大變形,此可造成傷害或甚至毀壞接合墊及接合至其的元件之底層電結構。
一些最近發展係有關具有銅芯及保護塗層之接合線。作為芯材料,銅因高電導率而被選擇。關於塗層,鈀為可能的選擇。此等經塗佈接合線組合銅線之優勢與對氧化之較少敏感度。
然而,關於接合線自身及接合製程,存在對於進一步改良接合線技術之進行中的需求。
因此,本發明之一目標為提供改良之接合線。
本發明之另一目標為提供一種具有良好處理性質且當互連 時不具有特定需求之接合線。
本發明之另一目標為提供一種具有優異電及熱導率之接合線。
本發明之另一目標為提供一種展現改良之可靠性之接合線。
本發明之另一目標為提供一種展現優異黏結性之接合線。
本發明之另一目標為提供一種展示關於訂合式接合的改良之黏結性之接合線。
本發明之另一目標為提供一種展示關於為訂合式接合之第二接合的改良之黏結性同時針對為球接合之第一接合的接合效能至少足夠之接合線。
本發明之另一目標為提供一種具有改良之耐腐蝕性及/或耐氧化性之接合線。
本發明之另一目標為提供一種用於接合一電子裝置之系統,該電子裝置可供標準晶片及接合技術使用,該系統展示至少關於第二接合的減小之故障率。
本發明之另一目標為提供一種用於製造一本發明之接合線之方法,藉以與已知方法相比,該方法基本上不展示製造成本之增加。
已發現本發明之電線解決以上提到的目標中之至少一者。另外,已發現克服製造電線之難題中之至少一者的用於製造此等電線之製程。另外,發現包含本發明之電線之電裝置在根據本發明之電線與其他電元件(例如,印刷電路板、襯墊/接腳等)之間的界面處以及在電裝置內之界面處更可靠,其中接合線連接至因此構成電裝置之其他電或電子零件。
由種類形成申請專利範圍之標的物提供對以上目標中之至少一者之解決方案的影響。種類形成申請專利範圍之附屬子申請專利範圍表示本發明之較佳具體實例,其標的物亦對解決以上提到的目標中之至少一者有影響。
本發明之第一態樣為一種電線,其包含具有一表面之至少一芯、具有一層表面之一第一塗層及一另外塗層,其中A)該芯包含銅及元素磷;B)該第一塗層由選自包含鈀、鉑及銀之群組之至少一種元素構成,其中該第一塗層疊加於該芯之該表面上,C)該另外塗層疊加於芯之該第一塗層之該層表面上;其中該另外塗層由選自銀及金之至少一種元素構成,且其中該另外塗層之組成不同於該第一塗層之組成;其中該電線具有在自8μm至80μm之範圍中的一平均直徑。
其特徵在於符合以下條件中之至少一個、兩個、三個或所有:A1)在縱向方向上量測的該芯中的晶粒之平均粒度與該電線之直徑之比率在自0.14至0.28(μm/μm)之範圍中,更佳地在自0.17至0.24之範圍中,或在自0.17至0.20之範圍中,且該平均粒度之相對標準差(RSD)小於0.9;或A2)在縱向方向上量測的該芯中的該等晶粒之再結晶度在自50%至95%之範圍中,更佳地在自80%至90%之範圍中;或A3)在縱向方向上量測的孿晶間界之分率在自2%至25%之範圍中,更佳地在自15%至20%之範圍中;或 A4)該電線之該等晶粒中之18%至42%定向於<100>方向上且該電線之該等晶粒中之27%至38%定向於<111>方向上,每一%係相對於具有平行於該電線之牽拉方向之定向的晶體之總數。又更佳地,該電線之該等晶粒中之35%至42%定向於<100>方向上且該電線之該等晶粒中之30%至38%定向於<111>方向上。若晶粒之方向偏離小於自-15°至+15°,則在指定方向上定向電線之晶粒,藉以,將電線之牽拉方向用作參考定向。藉由計數具有<100>的晶體之數目及具有<111>定向的晶體之數目來計算<100>及<111>紋理百分比。此等數目由<100>及<111>兩者之總和相除,此係由於通常未識別到具有定向<010>之晶粒。
該電線較佳地為用於在微電子中接合之接合線。該電線較佳地為單件式物件。眾多形狀係已知的且顯得適用於本發明之電線。較佳形狀為(在橫截面圖中)圓形、橢圓形及矩形形狀。
在本發明之上下文中,以μm表達指芯中的電線及晶體粒度之直徑的所有值。根據以下計算大小x之相對標準差RSD
RSD=標準差(x)/算術平均值(x)。
在本發明之上下文中的「孿晶間界(twin boundary)」藉由在電線芯中之晶粒內的切變晶格分開兩個晶粒或晶疇,其中,圍繞相鄰結晶晶疇或晶粒之間的定向之<111>平面的60°旋轉。
在本發明之上下文中「再結晶(Recrystallization)」描述在退火期間於銅線中配置的晶體之修改。在此退火階段中,新的無應變晶粒成核且生長以用殘餘應力代替彼等變形之晶粒。
「再結晶度(the degree of recrystallization)」指關於晶粒之總數的經再結晶晶粒之量。
在本發明之上下文中的術語「疊加(superimposed)」用以描述第一物品(例如,銅芯)關於第二物品(例如,塗層)之相對位置。「疊加」之特徵為諸如中間層之另外物品可(但不需要)配置於第一物品與第二物品之間。較佳地,第二物品至少部分疊加於第一物品上,例如,至少30%、50%、70%,或至少90%,每一者係相對於第一物品之全部表面。最佳地,第二物品完全疊加於第一物品上。
在本發明之上下文中的術語「中間層(intermediate layer)」指銅芯與塗層之間的電線之區域。在此區域中,存在芯與塗層兩者的材料之組合。
在本發明之上下文中的術語「厚度(thickness)」用以定義層在垂直於銅芯之縱向軸線之方向上的大小,該層至少部分疊加於銅芯之表面上。
平均直徑係藉由「定大小方法(sizing method)」獲得。根據此方法,判定對於定義之長度的電線之實體重量。基於此重量,使用電線 材料之密度(銅之密度:ρCu=8.92g/cm3)計算電線之直徑。將平均直徑計算為特定銅線之五個切割上的五個量測結果之算術平均值。
對於本發明,術語接合線包含所有橫截面形狀及所有通常電線直徑,但具有圓形橫截面且薄直徑之接合線為較佳的。
此薄電線大部分但未必具有基本上呈圓形狀之橫截面圖。在本上下文中之術語「橫截面圖(a cross-sectional view)」指穿過電線之切割之視圖,其中切割之平面垂直於電線之縱向延伸。可在電線之縱向延伸上之任何位置處發現橫截面圖。在橫截面中穿過電線之「最長路徑(longest path)」為在橫截面圖之平面內可穿過電線之橫截面放下的最長弦。橫截面中穿過電線之「最短路徑(shortest path)」為垂直於上文所定義之橫截面圖之平面內的最長路徑之最長弦。若電線具有完美的圓形橫截面,則最長路徑與最短路徑變得不可區分且共用同一值。術語「直徑(diameter)」為任一平面且在任一方向上的所有幾何直徑之算術平均值,其中所有平面垂直於電線之縱向延伸。
本上下文中的電線之芯經定義為塊狀材料之均質區域。由於任何塊狀材料始終具有可在一定程度上展現不同性質之表面區域,因此將電線之芯之性質理解為塊狀材料的均質區域之性質。就形態、組成(例如,氧含量)及其他特徵而言,塊狀材料區域之表面可不同。在較佳具體實例中,表面可為本發明之外表面。在另外具體實例中,電線芯之表面可為電線芯與疊加於電線芯上之塗層之間的界面區域。
本發明之一較佳具體實例為一種如上所述之電線,其中符合以下條件中之至少一個、兩個或所有:
2.1)芯中的銅之量為至少99.95wt.%;或在自99.98wt.%至99.95wt.%之範圍中,或在自99.98wt.%至99.99 wt.%之範圍中;通常,芯中的銅之量不大於99.995wt.%。如在此章節中定義之銅含量歸因於高純度規格,允許使用銅材料之普通供應以用於線接合,而無極其高的成本。
2.2)芯中的元素磷之量在自20ppm至300ppm之範圍中,又更佳地,在自20ppm至100ppm或自40ppm至80ppm之範圍中,每一者係基於芯之總重量;或2.3)芯中的元素銀之量在自2ppm至250ppm之範圍中,又更佳地在自2ppm至50ppm之範圍中,或在自2ppm至15ppm之範圍中,其中所有wt.%及ppm值係基於該芯之總重量。
在一較佳具體實例中,本發明之電線之芯一共包含在自0至100ppm之範圍中、較佳地小於30ppm之另外組分。此等另外組分之低量確保電線性質之良好再現性。在本上下文中,常亦被稱作「不可避免的雜質(inevitable impurities)」之另外組分為源自存在於使用之原材料中或來自生產電線之製造製程中的雜質之少量化學元素及/或化合物。此等另外組分之實例為:Ni、Mn、Pt、Cr、Ca、La、Al、B、Zr、Ti、Fe。通常不分開來添加存在於芯中之另外組分。另外組分之存在源自組分a)、b)及c)中之一或多者中存在的雜質。
在一較佳具體實例中,本發明之電線之芯包含小於以下量之另外組分:a)各<15ppm的Ni、Mn中之任一者;b)以下中之任一者:各<2ppm的Pt、Cr、Ca、La、Al、B、Zr、Ti; c)各<10ppm的S、Fe中之任一者。
形成芯之材料符合前述限制中之更佳的至少兩者,形成芯之材料符合最佳的所有限制。
本發明之再一較佳具體實例為一種電線,其中該第一塗層具有在自40nm至小於0.5μm之範圍中、較佳地在自40nm至200nm之範圍中或在自40nm至80nm之範圍中的一厚度。
結果,該第一塗層由鈀構成,本發明之再一具體實例具有第一塗層,其具有小於0.5μm之一厚度。又更佳地,另外塗層具有小於0.05μm之一厚度。一充分薄之另外塗層僅造成對總體電線之多數性質的極小改變。然而,一些性質明顯地改良,詳言之,關於接合製程。
關於第一塗層之組成,該層之鈀含量為至少50wt.%,更佳地至少95wt.%,每一wt.%係基於第一塗層之總重量。尤佳地,該塗層由純鈀組成。純鈀通常具有相對於第一塗層中的鈀之總量的小於1wt.%之另外組分。在再一較佳具體實例中,存在於第一塗層中之另外組分為貴金屬。
在本發明之另一較佳具體實例中,,該電線之該另外塗層具有在自1.0nm至小於50nm之範圍中、較佳地在自1.0nm至40nm或自1.0nm至25nm之範圍中的一厚度。
在本發明之再一較佳具體實例中,該電線之該芯具有在5ppm至10000ppm之範圍中、較佳地在5ppm至1000ppm之範圍中、又更佳地在200ppm至250ppm之範圍中的銀或金之一含量。觀測到,至少少量銀之存在改良機械性質,例如,對電線給予一些柔軟度。
在本發明之再一較佳具體實例中,電線上的另外塗層中的至 少一種元素之含量為至少50wt.%,更佳地至少95wt.%,每一者係基於該另外塗層之總量wt.%。尤佳地,該另外塗層由純金或純銀組成。純金通常具有相對於該另外塗層中的金之總量的小於1wt.%之另外組分。
本發明之第二態樣為一種用於製造一電線之方法,包含至少以下步驟
i.提供包含至少銅及元素磷之一前驅體物品;ii.將該前驅體物品牽拉成一芯前驅體;iii.用選自由鈀、鉑或銀組成之群組的至少一種元素塗佈該芯前驅體,藉以形成在該芯前驅體上之一第一塗層;iv.在於步驟iii.中獲得的芯前驅體之第一塗層上用選自銀及金之至少一種元素進一步塗佈;藉以該另外塗層之組成不同於該第一塗層之組成,藉以形成一另外塗層;v.將自步驟iv.獲得之該經塗佈芯前驅體牽拉至8μm至80μm之一最終直徑;vi.使在步驟v.中製備之產品退火;藉以獲得該電線(1),其中該電線(1)具有在自8μm至80μm之範圍中的一平均直徑,其特徵在於符合以下條件中之至少一個、兩個、三個或所有:A1)在縱向方向上量測的該芯中的晶粒之平均粒度與該電線之直徑之比率在自0.14至0.28(μm/μm)之範圍中,更佳地在自0.17至0.24之範圍中,或在自0.17至0.20之範圍中,且該平均粒度之相對標準差RSD小於0.9; 或A2)在縱向方向上量測的該芯中的該等晶粒之再結晶度在自50%至95%之範圍中,更佳地在自80%至90%之範圍中;或A3)在縱向方向上量測的孿晶間界之分率在自2%至25%之範圍中,更佳地在自15%至20%之範圍中;或A4)該電線之該等晶粒中之18%至42%定向於<100>方向上且該電線之該等晶粒中之27%至38%定向於<111>方向上,每一%係相對於具有平行於該電線(1)之牽拉方向之定向的晶體之總數。又更佳地,該電線之該等晶粒中之35%至42%定向於<100>方向上且該電線之該等晶粒中之30%至38%定向於<111>方向上。若晶粒之方向偏離小於自-15°至+15°,則在指定方向上定向電線之晶粒,藉以,將電線之牽拉方向用作參考定向。藉由計數具有<100>的晶體之數目及具有<111>定向的晶體之數目來計算<100>及<111>紋理百分比。此等數目由<100>及<111>兩者之總和相除,此係由於通常未識別到具有定向<010>之晶粒。
本發明之第二態樣之較佳具體實例為已在上文針對本發明之第一態樣描述的具體實例。可藉由用適量元素磷摻雜銅,視情況藉由用另外元素摻雜,獲得如在步驟i.中之前驅體物品。可藉由生成該等組分及銅之熔化物且冷卻熔化物以形成基於銅之前驅體物品的均質段來實現摻雜。
在本發明之第一較佳具體實例至第二態樣中,在至少400℃、較佳地至少430℃或至少540℃之溫度下執行在該方法之步驟vi.中的產品之退火。較高退火溫度可提供電線之伸長率的較高值。
關於用於退火之另外參數,詳言之,不需要長期將薄電線曝 露於退火溫度。在多數情況下,藉由以給定速度拉動電線穿過給定長度且具有定義之溫度分佈的退火烘箱來進行退火。薄電線至退火溫度之曝露時間典型地在0.1秒至10秒之範圍中。
本發明之第三態樣為一種用於連接一電裝置之方法,其包含以下步驟
I.提供如針對本發明之第一態樣或其具體實例中之一者所描述的一電線,或藉由根據本發明之第二態樣或其具體實例中之一者的方法獲得之一電線;II.藉由球接合或楔形接合將在步驟I.中提供之電線接合至該裝置之第一接合墊;及III.藉由楔形接合將接合至第一接合墊的步驟I.之電線接合至該裝置之第二接合墊;其中在不使用一形成氣體之情況下執行步驟III.;且其中在存在一惰性氣體或形成氣體之情況下執行步驟II.。
在本發明之第三態樣之第一具體實例中,在步驟II.中藉由球接合及在步驟III.中藉由楔形接合來接合電線。
根據本發明之第三態樣或根據其具體實例之電線具有關於氧化效應之優異性質。甚至藉由用鈀塗層上之薄金完整囊封芯來達成針對銅芯之氧化的更好保護,該鈀塗層與芯材料中的一定量之銀及/或磷一起存在。所得性質允許藉由淨化形成氣體來處理電線,且因此導致清潔、軸對稱自由空氣球形式。形成氣體在此項技術中被稱為如氮之惰性氣體與氫之混合物,其中氫含量可提供經氧化電線材料之還原反應。在本發明之意義 上,形成氣體之省略意謂未使用如氫之反應性化合物。然而,如氮的惰性氣體之使用可仍有利。
本發明之第四態樣為一種用於製造根據本發明之一電線之方法,包含以下步驟:a.提供如在本發明之第二態樣中的一銅芯前驅體物品;b.牽拉該前驅體,直至達到該電線芯之一最終直徑;c.在步驟b牽拉該前驅體前或後,用該第一及該另外塗層之材料塗佈該銅芯;d.在一最小時間內,在一定義之溫度下使該經塗佈且牽拉之電線退火。
關於步驟b至c,該製造方法在此項技術中通常已知。指出,可藉由如機械塗佈、電解鍍覆、無電極鍍覆、物理氣相沈積(PVD)、化學氣相沈積(CVD)及更多之任何已知或合適方法來塗覆塗層。可在電線之牽拉前或後進行塗佈,此可取決於各別塗層及塗佈法之性質。詳言之,可在中間步驟執行塗佈,其中電線或前驅體之牽拉發生在塗佈步驟前以及後。
關於步驟d,如此項技術中已知,以受控制方式來執行退火,以便達成電線之軟化及/或根據各別需求最佳化電線之晶體結構。較佳地,當電線經移動穿過退火烘箱且在已離開烘箱後纏繞至線軸上時,動態進行退火。
本發明之第五態樣為一種電裝置,其包含一第一接合墊及一第二接合墊,及根據本發明之第一態樣或其一具體實例之一電線,或藉由根據本發明之第二態樣或其具體實例中之一者的方法獲得之一電線,其中使用球-楔形接合將該電線連接至該等接合墊中之至少一者。本上下文中之 一電裝置包含電子裝置。電子裝置為包含半導體元件之裝置。
第五態樣之一具體實例為一種電裝置,其中藉由球-楔形接合將該電線連接至兩個襯墊。
本發明之第六態樣為一種用於接合一電子裝置之系統,其包含一第一接合墊、一第二接合墊及根據本發明之一電線,其中藉由訂合式接合將該電線連接至該等接合墊中之至少一者。在一系統中的本發明之電線之此組合係較佳的,此歸因於電線具有關於訂合式接合尤其有益的性質之事實。
在本發明之第五及第六態樣之一具體實例中,為一種方法,其中對於具有18μm之一直徑的一電線,用於至金接合墊之至少一個訂合式接合的製程窗具有至少10450mA*g之一值。
用於接合線的製程窗區之界定在此項技術中已知且廣泛地用以比較不同電線。原則上,其為在接合中使用的超音波能量之接合窗與在接合中使用的力之接合窗之乘積,其中所得接合必須符合某些拉動測試規範,例如,2.5公克之拉力、無引腳脫落等。給定電線之製程窗區之實際值進一步取決於電線直徑以及接合墊材料。為了給出本發明之電線之性質的特定定義,主張之製程窗值係基於18μm=0.7密耳之電線直徑,其中接合墊由金組成。本發明之系統之範圍不限於此直徑之電線及由金製成之接合墊,而僅為了定義目的對此資料命名。
本發明進一步藉由實施例舉例說明。此等實施例用於本發明之例示性闡明,且無論如何並不意欲限制本發明或申請專利範圍之範圍。
測試方法
1.電子後向散射繞射圖案分析
用以量測電線紋理之主要步驟為樣本製備,從而得到良好菊池(Kikuchi)圖案及組分計算;
(a)接合線首先經使用環氧樹脂罐封且按照標準金相技術拋光。在最終樣本製備步驟中應用離子研磨以移除電線表面之任何機械變形、污染及氧化層。藉由金濺鍍經離子研磨之橫截面樣本表面。接著針對兩個另外回合進行離子研磨及金濺鍍。不進行化學蝕刻或離子蝕刻。
(b)在具有與正常FESEM(場發射掃描電子顯微鏡)樣本固持台表面70°角之固持器的FESEM中載入樣本。FESEM進一步裝備有電子回散射繞射(EBSD)偵測器。獲得含有電線結晶資訊之電子回散射圖案(EBSP)。
(c)進一步針對晶粒定向分率、粒度等分析此等圖案(使用由牛津儀器(Oxford Instruments)開發且可購自其的叫作EBSD程式之軟體)。類似定向之點經分群在一起以形成紋理組分。為了區分不同紋理組分,使用15°之最大公差角度。將電線牽拉方向設定為參考定向。藉由具有平行於參考定向之<100>及<111>定向的晶體之百分比之量測計算<100>及<111>紋理百分比。通常不存在<010>組分。
分析定義大於最小值(本文中,10°)之相鄰柵格點之間的結晶定向的晶體粒度,以判定晶界之位置。EBSD軟體計算每一晶粒之面積,且將其轉換至等效圓直徑,將等效圓直徑定義為「晶體粒度(crystal grain size)」。對在~100μm之長度的電線之縱向方向的所有晶粒經計數以判定晶體粒度之平均值及標準差。
在粒度計算中不包括孿晶間界(亦叫作Σ 3 CSL孿晶間 界)。孿晶間界由圍繞相鄰結晶晶疇之間的<111>定向平面之60°旋轉描述。
此外,將類似定向之點分群在一起以形成紋理組分。為了區分不同紋理組分,使用15°之最大公差角度。藉由具有平行於參考定向之此等(<100>、<101>及<111>)定向的晶體之百分比之量測來計算<100>、<101>及<111>紋理百分比。將電線牽拉方向(電線軸線)設定為參考定向。
亦使用EBSD軟體量測經退火之電線之再結晶程度。該軟體量測晶粒中的任兩個點之間的最大定向錯誤,且接著根據定向錯誤值對該晶粒加權。將平均定向錯誤定義為θ。此為計算給定點/像素與其第一個最鄰近點之間的定向錯誤之平均值的基於像素之量測。點之數目取決於步長,其小於平均晶體粒度之1/5。
基於EBSD軟體分析,將電線微結構分類成三個類型:1)經變形,2)經子結構化,及3)再結晶之晶粒。當不存在子晶粒且在晶粒內之平均定向錯誤>2°時,將晶粒定義為經變形。此外,當在晶粒中存在子晶粒且在子晶粒內平均定向錯誤<2°且每一子晶粒之間的定向錯誤>2°時,將晶粒結構定義為子結構。除了經變形及經子結構化之晶粒結構外,將電線晶粒結構之其餘定義為再結晶之晶粒。經變形區域經強地錯誤定向。再結晶之區域無應變,且多數揭露高角度再結晶邊界。
2.電線處理
4N純度之銅用以製備合金且熔化於真空感應爐中。使用Cu-0.5wt%P母合金(Cu-0.5wt%P母合金之組成:99.5wt.% Cu及0.5wt.% P)將磷添加至熔化物內。固持熔化物達幾分數以允許澈底溶解。以慢的速度將合金連續地鑄造成2mm至25mm棒。未觀測到摻雜劑添加中之顯著損 失。此等棒為在室溫(25℃)下牽拉之電線。使用碳化鎢晶粒牽拉重電線且將金剛石晶粒用於進一步減小。以15m/s或更小之牽拉速度在兩個階段中對其牽拉。晶粒減小率對於厚電線為大約14%至18%,且對於薄大小,為大約4%至12%。在冷牽拉期間,使電線潤滑。
對具有6密耳至15密耳之直徑的薄電線成行地脫脂,鈀電鍍,接著為金電鍍,最後沖洗且纏繞以供最終電線牽拉。在電鍍期間,將電線速度維持在5m/min.至25m/min.,施加在1V與8V之間的電壓,施加自0.05A至5A的電流。將鈀鍍覆浴之pH值維持在7與10之間,且將金鍍覆維持在自4至6之範圍中。在40℃至60℃下處理鍍覆。
將經電鍍之電線牽拉至0.5密耳至2密耳之最終大小。最後,經牽拉電線經帶材退火,纏繞於清潔的陽極化(經鍍覆)鋁線軸上,經真空裝填及儲存。
芯中的晶粒之平均粒度與電線之直徑之比率在0.14至0.28之範圍中且具有~0.9之標準差。此係藉由在470℃至520℃之溫度範圍中使電線退火來達成(實施例:見圖5,針對0.7密耳電線)。在以上提到的值之外範圍中的平均晶體粒度比率係藉由在420℃至470℃之範圍中使電線退火來達成。
3.球-楔形接合參數定義
使用KNS-iConn接合機來接合電線。在20℃下執行電線至經鍍覆表面之接合。首先,藉由電火炬點火形成自由空氣球以用於在3V至5V之範圍中變化電流。另外,將自由空氣球接合至IC(積體晶片)上之接合墊。藉由組成物Al-0.5Cu(99.5wt.% Al及0.5wt.% Cu)來使接合墊 中之多數金屬化。一些接合墊經金屬化具有金表面。在形成電線與接合墊之間的第一球接合後,電線經訂合式(楔形),其第二端至基板引線指狀物,其中將接合應用於BGA基板中之金指狀物表面、引線框中之銀指狀物表面。一些引線指狀物表面亦鍍有鈀或鎳。電線之兩個端部之間的接合之距離在自5mm至20mm之範圍中。此距離經選擇以便確保電線與基板之間呈楔形的45°之角度。在訂合式接合期間,將在60kHz至140kHz之範圍中的頻率之超音波聲音施加至接合工具達40毫秒至500毫秒。在LEO-1450VP掃描電子顯微鏡(SEM)中針對良好循環、第一接合頸區、第二接合跟及訂合式、工具標記等觀測接合之電線。
4.自由空氣球
電火炬(EFO)電流及時間定義FAB之規格。在EFO點火後,斷裂之Cu電線的尖端熔化且形成軸對稱球形FAB,進一步訂合式引線框上之電線使得FAB立於空氣中。此接合模式被稱作櫻桃核。該程序描述於針對自由空氣球之KNS製程使用者指南(Kulicke & Soffa工業公司,Fort Washington,PA,美國,2002,2009年5月31日)中。使用光學顯微鏡在200X至500X放大率下按微米標度量測FAB直徑。使用掃描電子顯微鏡(SEM)觀測FAB之形態。
5.製程窗區
藉由標準程序進行球接合製程窗區之量測。使用KNS-iConn接合機工具(Ku1icke & Soffa工業公司,Fort Washington,PA,美國)接合測試電線。用於接合線的第2接合製程窗區之定義在此項技術中已知且廣泛地用以比較不同電線。原則上,其為摩擦振幅與在接合中使用之力之乘 積,其中所得接合必須符合某些拉動測試規範,例如,2.5公克之拉力、無引腳脫落等。給定電線之第2接合製程窗區之實際值進一步取決於電線直徑以及引線指狀物鍍覆材料。為了給出本發明之電線之性質的特定定義,製程窗值係基於18μm=0.7密耳之電線直徑,其中引線指狀物由銀組成。
製程窗之四個角係藉由克服兩個主要故障模式而導出:(1)過低力之供應及摩擦振幅導致電線之引腳脫落(NSOL),及(2)過高力之供應及摩擦振幅導致短尾(SHTL)。
本發明之系統之範圍不限於此直徑之電線及由銀製成之引線指狀物,而僅為了定義目的對此資料命名。
1:電線
2:芯
2a:芯前驅體
3:塗層
5:前驅體物品
6:電裝置
10:電裝置
11:接合墊
15:表面
21:表面
31:層表面
32:電線之中心
41:另外塗層
42:另外塗層之表面
L:穿過電線橫截面之假想線
本發明之標的物舉例說明於圖中。然而,該等圖無論如何並不意欲限制本發明或申請專利範圍之範圍。
在圖1中,描繪電線1。
圖2展示電線1之橫截面圖。在該橫截面圖中,銅芯2處於橫截面圖之中間中。銅芯2由鈀塗層3涵蓋。鈀塗層3由薄金塗層41涵蓋。銅芯之表面15位於銅線2之界限上。鈀塗層之表面42位於鈀塗層3之界限上。在經由電線1之中心23的線L上,將銅芯2之直徑展示為線L與表面15之交叉點之間的端至端距離。電線1之直徑為經由中心23之線L與電線1之外界限之交叉點之間的端至端距離。此外,描繪塗層3及41之厚度。
圖3展示用於製造根據本發明之電線之製程。
圖4描繪電裝置10,其包含兩個元件11及一電線1。電線1電連接兩個元件11。虛線意謂將元件11與包圍元件11的封裝裝置之外部佈線連接 之另外連接或電路。元件11可包含接合墊、引線指狀物、積體電路、LED或類似者。
圖5描繪0.7密耳電線之退火曲線。在不同退火溫度下使此電線之多條退火。將基於退火前的電線之長度的以%計的伸長率之值記錄為退火溫度之函數。區域A表示再結晶之開始;區域B表示晶粒生長之開始;區域C表示過退火之開始。
圖6描繪四個項目:項目(a)為反極圖。此圖藉由由色彩鍵定義之色彩對比度說明晶粒至某些平面之定向,藉以在電線芯之縱向方向上判定角度。預期銅線定向至三個主要方向平面[111]、[101]、[100]。低角度晶界(LAGB)具有在自2°<θ
Figure 104140498-A0305-02-0009-2
10°之範圍中的角度,高角度晶界(HAGB)具有在自10°<θ之範圍中的角度。當<111>>60°時,存在孿晶間界(TB)。
項目(b)為晶界圖。此圖說明晶界之存在。灰線之邊界為低角度晶界,且淺灰線之邊界為孿晶間界。深灰線表示高角度晶界。
項目(c)為反極圖。此圖將晶粒至某些平面之定向說明為點,點之數目愈多,則晶粒愈高度定向至該方向平面,藉以在電線芯之縱向方向上判定角度。預期銅線主要由三個方向平面<111>、<101>、<100>定向。
項目(d)為0.7密耳成品Cu線之色彩鍵。色彩鍵定義每一定向平面之色彩(三個主要方向<111>、<101>、<100>且將由每一晶粒色彩及其沿著縱向方向在橫截面電線芯中之定向來反映)。
圖7展示反映0至7密耳Cu線之粒度分佈之圖表。
圖8由三個項目組成。項目(a)為再結晶圖。深色區表示再結晶晶粒,淺色區為經子結構化及變形之晶粒。黑線為晶粒之間的邊界。項目(b)為 提供關於0.7密耳成品Cu線之分率的定量資料之再結晶圖表。「成品(finished)」意謂最終電線經牽拉及退火。記錄關於電線縱向方向之量測結果。根據該圖表,藉由量測來調查的晶粒中之約85%經再結晶,且該等晶粒中之約15%經子結構化。該等晶粒中之約1%經變形。
經變形晶粒描述通常在未退火之經牽拉電線(無高溫退火)中發現的情形,其中沿著變形方向(電線軸線)存在高度定向之晶體。在退火後,一些「經變形(deformed)」晶粒可保留。
在使經牽拉電線退火後,一些晶粒在再結晶之晶粒內部成核。此效應可取決於變形之程度、退火之時間及溫度。在再結晶之晶粒內部成核的晶粒被稱為「子晶粒(sub-grains)」。微結構被稱作「子結構(sub-structure)」。
圖9由2個項目組成。項目(a)為晶界圖(見圖6(a))。項目(b)為展示0.7密耳成品(經牽拉及退火之最終電線)Cu線之定向錯誤角度分佈之圖表。根據該圖表,定向錯誤之程度係針對1%與3%之間的多數角度。對於2°之角度,定向錯誤為20%,且對於60°之角度,定向錯誤為約16%。記錄關於電線縱向方向之量測結果。
實施例
本發明進一步藉由實施例舉例說明。此等實施例用於本發明之例示性闡明,且無論如何並不意欲限制本發明或申請專利範圍之範圍。
實施例1
樣本1及比較樣本電線之典型ICP分析提供於表1中。樣本1芯材料摻雜有「P」。電線之Au閃光之經預測厚度靠近約3nm。電線之Pd塗層之經預測厚度為約63nm。本發明之電線樣本1揭露10450mA*g之寬的第2接合窗,其與約8100mA*g之裸4N Cu相比很高(表1)具有靠近樣本1之組成的競爭電線亦已展示寬的第2接合窗(比較實例)。
Figure 104140498-A0305-02-0025-1
自反極圖,樣本1之細牽拉及退火之電線之紋理展示於圖6中,其係在縱向方向上量測。觀測兩個纖維組分<111>+<100>。明顯地,<100>比<111>相對更強(圖6c)。通常,具有<101>定向之晶粒不存在。
自低及高角度晶界之晶界圖,計算電線晶粒形態及大小。針對粒度量測,不包括CSL Σ3邊界(亦被稱作:孿晶間界)。晶體粒度具有正態分佈(圖7)。平均晶體粒度為大約3.49μm,且標準差為大約3.05μm。芯中的晶粒之平均粒度與電線之直徑之比率在0.14至0.28、較佳地0.17至0.24之範圍中,且其中相對標準差RSD小於0.9。(見圖7,在縱向方向上量測)。
實施例2
樣本1經牽拉且退火之電線之典型再結晶圖展示於圖8中,在縱向方向上量測。芯中的晶粒之再結晶分率大於50%(圖8b)。
實施例3
針對樣本1計算的CSL Σ3孿晶間界<111>60°之典型分率低於25%。針對0.7密耳電線,此展示於圖9b中。
本發明之具體實例
I)一種電線(1),其包含具有一表面(21)之至少一芯(2)、具有一層表面(31)之一第一塗層(3)及一另外塗層(4),其中A)該芯(2)包含銅及元素磷;B)該第一塗層(3)由選自包含鈀、鉑及銀之群之至少一種元素構成,其中該第一塗層(3)疊加於該芯(2)之該表面(21)上;C)該另外塗層(4)疊加於芯(2)之該第一塗層(3)之該層表面(31)上;其中該另外塗層(4)由選自銀及金之至少一種元素構成,且其中該另外塗層(4)之組成不同於該第一塗層(3)之組成;其中該電線(1)具有在自8μm至80μm之範圍中的一平均直徑;其特徵在於符合以下條件中之至少一個、兩個、三個或所有:A1)在縱向方向上量測的該芯中的晶粒之平均粒度與該電線之直徑之比率在自0.14至0.28(μm/μm)之範圍中,且該平均粒度之相對標準差小於0.9;或A2)在縱向方向上量測的該芯中的該等晶粒之再結晶度在自50%至95%之範圍中;或A3)在縱向方向上量測的孿晶間界之分率在自2%至25%之範圍中;或A4)該電線之該等晶粒中之18%至42%定向於<100>方向上且該電線之該等晶粒中之27%至38%定向於<111>方向上,每一%係相對於具有平行於該電線(1)之牽拉方向之定向的晶體之總數。
II)根據具體實例I)之電線(1),其中符合以下條件中之至少一個、兩個或所有: 2.1)芯(2)中的銅之量為至少99.95wt.%;或2.2)芯(2)中的元素磷之量在自20ppm至300ppm之範圍中,每一者係基於該芯(2)之總重量;或2.3)芯(2)中的元素銀之量在自2ppm至250ppm之範圍中;其中所有wt.%及ppm值係相對於芯(2)之該總重量給出。
III)根據先前具體實例中任一者之電線(1),其中該第一塗層(3)具有在自40nm至小於0.5μm之範圍中的一厚度。
IV)根據先前具體實例中任一者之電線(1),其中該另外塗層(4)具有在自1.0nm至小於50nm之範圍中的一厚度。
V)一種用於製造一電線(1)之方法,其至少包含以下步驟i.提供包含至少銅及元素磷之一前驅體物品(5);ii.將該前驅體物品(5)牽拉成一芯前驅體(2a);iii.用選自由鈀、鉑或銀組成之群組的至少一種元素塗佈該芯前驅體(2a),藉以形成在該芯前驅體(2a)上之一第一塗層(3);iv.在於步驟iii.中獲得的該芯前驅體(2a)之該第一塗層(3)上用選自銀及金之至少一種元素進一步塗佈;藉以該另外塗層(4)之組成不同於該第一塗層(3)之組成,藉以形成一另外塗層(4);v.將自步驟iv.獲得之該經塗佈芯前驅體牽拉至8μm至80μm之一最終直徑;vi.使在步驟v.中製備之產品退火; 藉以獲得該電線(1),其中該電線(1)具有在自8μm至80μm之範圍中的一平均直徑,其特徵在於符合以下條件中之至少一個、兩個、三個或所有:A1)在縱向方向上量測的該芯中的晶粒之平均粒度與該電線之直徑之比率在自0.14至0.28(μm/μm)之範圍中,且該平均粒度之相對標準差小於0.9;或A2)在縱向方向上量測的該芯中的該等晶粒之再結晶度在自50%至95%之範圍中;或A3)在縱向方向上量測的孿晶間界之分率在自2%至25%之範圍中;或A4)該電線之該等晶粒中之18%至42%定向於<100>方向上且該電線之該等晶粒中之27%至38%定向於<111>方向上,每一%係相對於具有平行於該電線(1)之牽拉方向之定向的晶體之總數。
VI)具體實例V)之方法,其中在步驟vi.中的該產品之該退火係在至少400℃之一溫度下執行。
VII)一種用於連接一電裝置(6)之方法,其包含以下步驟I.提供根據具體實例I)至IV)中任一者之一電線(1),或藉由根據具體實例V)至VI)中任一者之一方法獲得的一電線,II.藉由球接合或楔形接合將該電線(1)接合至該裝置之一第一接合墊(61);及III.藉由楔形接合將該電線(1)接合至該裝置之一第二接合墊(62);其中在不使用一形成氣體之情況下執行步驟III.;且其中在存在一惰性氣體或形成氣體之情況下執行步驟II.。
VIII)一種電裝置(10),其包含一第一接合墊及一第二接合墊(11、11),及根據具體實例I)至IV)中任一者之一電線(1),或藉由根據具體實例V)至VI)中任一者之一方法獲得的一電線,其中該電線(1)係使用球-楔形接合連接至該等接合墊(11、11)中之至少一者。
IX)根據具體實例VIII)之電裝置(10),其中在該電線(1)具有18μm之一直徑的條件下,用於至一金接合墊之至少一個訂合式接合的製程窗具有至少10450mA*g之一值。

Claims (9)

  1. 一種電線(1),其包含具有表面(21)之至少一芯(2)、具有層表面(31)之第一塗層(3)及另外塗層(4),其中A)該芯(2)包含銅及元素磷;B)該第一塗層(3)由選自包含鈀、鉑及銀之群之至少一種元素構成,其中該第一塗層(3)疊加於該芯(2)之該表面(21)上;C)該另外塗層(4)疊加於芯(2)之該第一塗層(3)之該層表面(31)上;其中該另外塗層(4)由選自銀及金之至少一種元素構成,且其中該另外塗層(4)之組成不同於該第一塗層(3)之組成;其中該電線(1)具有在自8μm至80μm之範圍中的平均直徑;其中A1)在縱向方向上量測的該芯中的晶粒之平均粒度與該電線之直徑之比率在自0.14至0.28(μm/μm)之範圍中,且該平均粒度之相對標準差小於0.9;其特徵在於符合以下條件中之至少一個、兩個或所有:A2)在縱向方向上量測的該芯中的該等晶粒之再結晶度在自50%至95%之範圍中;或A3)在縱向方向上量測的孿晶間界(twin boundary)之分率在自2%至25%之範圍中;或A4)該電線之該等晶粒中之18%至42%定向於<100>方向上且該電線之該等晶粒中之27%至38%定向於<111>方向上,每一%係相對於具有平行於該電線(1)之牽拉方向之定向的晶體之總數。
  2. 如申請專利範圍第1項之電線(1),其中符合以下條件中之至少一個、兩個或所有:2.1)芯(2)中的銅之量為至少99.95wt.%;或2.2)芯(2)中的元素磷之量在自20ppm至300ppm之範圍中,每一者係基於該芯(2)之總重量;或2.3)芯(2)中的元素銀之量在自2ppm至250ppm之範圍中;其中所有wt.%及ppm值係相對於芯(2)之總重量給出。
  3. 如申請專利範圍第1項和第2項中任一項之電線(1),其中該第一塗層(3)具有在自40nm至小於0.5μm之範圍中的厚度。
  4. 如申請專利範圍第1項之電線(1),其中該另外塗層(4)具有在自1.0nm至小於50nm之範圍中的厚度。
  5. 一種用於製造電線(1)之方法,其至少包含以下步驟i 提供包含至少銅及元素磷之前驅體物品(5);ii 將該前驅體物品(5)牽拉成芯前驅體(2a);iii 用選自由鈀、鉑或銀組成之群組的至少一種元素塗佈該芯前驅體(2a),藉以形成在該芯前驅體(2a)上之第一塗層(3);iv 在於步驟iii.中獲得的該芯前驅體(2a)之該第一塗層(3)上用選自銀及金之至少一種元素進一步塗佈;藉以該另外塗層(4)之組成不同於該第一塗層(3)之組成,藉以形成一另外塗層(4);v 將自步驟iv.獲得之該經塗佈芯前驅體牽拉至8μm至80μm之最終直徑; vi 使在步驟v.中製備之產品退火;藉以獲得該電線(1),其中該電線(1)具有在自8μm至80μm之範圍中的平均直徑,其特徵在於符合以下條件中之至少一個、兩個、三個或所有:A1)在縱向方向上量測的該芯中的晶粒之平均粒度與該電線之直徑之比率在自0.14至0.28(μm/μm)之範圍中,且該平均粒度之標準差RSD小於0.9;或A2)在縱向方向上量測的該芯中的該等晶粒之再結晶度在自50%至95%之範圍中;或A3)在縱向方向上量測的孿晶間界之分率在自2%至25%之範圍中;或A4)該電線之該等晶粒中之18%至42%定向於<100>方向上且該電線之該等晶粒中之27%至38%定向於<111>方向上,每一%係相對於具有平行於該電線(1)之牽拉方向之定向的晶體之總數。
  6. 如申請專利範圍第5項之方法,其中在步驟vi.中的該產品之該退火係在至少400℃之溫度下執行。
  7. 一種用於連接電裝置(6)之方法,其包含以下步驟I.提供如申請專利範圍第1項至第4項中任一項之電線(1),或藉由如申請專利範圍第5項至第6項中任一項之方法獲得的電線,II.藉由球接合或楔形接合將該電線(1)接合至該裝置之第一接合墊(61);及III.藉由楔形接合將該電線(1)接合至該裝置之第二接合墊(62);其中在不使用形成氣體之情況下執行步驟III.;且 其中在存在惰性氣體或形成氣體之情況下執行步驟II.。
  8. 一種包含電線的電裝置(10),其包含第一接合墊及第二接合墊(11、11),及如申請專利範圍第1項至第4項中任一項之電線(1),或藉由如申請專利範圍第5項至第6項中任一項之方法獲得的電線,其中該電線(1)係使用球-楔形接合連接至該等接合墊(11、11)中之至少一者。
  9. 如申請專利範圍第8項之電裝置(10),其中在該電線(1)具有18μm之直徑的條件下,用於至金接合墊之至少一個訂合式接合的製程窗具有至少10450mA*g之值。
TW104140498A 2014-12-11 2015-12-03 用於接合應用的經塗佈銅(Cu)線 TWI744220B (zh)

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WO2016088888A1 (ja) * 2014-12-05 2016-06-09 古河電気工業株式会社 アルミニウム合金線材、アルミニウム合金撚線、被覆電線およびワイヤーハーネス、ならびにアルミニウム合金線材の製造方法
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102422404A (zh) * 2009-07-30 2012-04-18 新日铁高新材料株式会社 半导体用接合线
TW201315821A (zh) * 2011-12-21 2013-04-16 Tanaka Electronics Ind 包鈀(Pd)銅球銲接合線
CN103219312A (zh) * 2013-03-01 2013-07-24 溧阳市虹翔机械制造有限公司 一种镀钯镀金的双镀层键合铜丝
TW201430977A (zh) * 2013-01-23 2014-08-01 Heraeus Materials Tech Gmbh 用於接合應用的經塗覆線材
EP2768019A2 (en) * 2013-02-15 2014-08-20 Heraeus Materials Singapore Pte. Ltd. Copper bond wire and method of making the same
WO2014137288A1 (en) * 2013-03-05 2014-09-12 Heraeus Materials Singapore Pte.Ltd. Palladium coated copper wire for bonding applications

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG2013016415A (en) * 2013-03-05 2014-10-30 Heraeus Materials Singapore Pte Ltd Coated copper wire for bonding applications

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102422404A (zh) * 2009-07-30 2012-04-18 新日铁高新材料株式会社 半导体用接合线
TW201315821A (zh) * 2011-12-21 2013-04-16 Tanaka Electronics Ind 包鈀(Pd)銅球銲接合線
TW201430977A (zh) * 2013-01-23 2014-08-01 Heraeus Materials Tech Gmbh 用於接合應用的經塗覆線材
EP2768019A2 (en) * 2013-02-15 2014-08-20 Heraeus Materials Singapore Pte. Ltd. Copper bond wire and method of making the same
CN103219312A (zh) * 2013-03-01 2013-07-24 溧阳市虹翔机械制造有限公司 一种镀钯镀金的双镀层键合铜丝
WO2014137288A1 (en) * 2013-03-05 2014-09-12 Heraeus Materials Singapore Pte.Ltd. Palladium coated copper wire for bonding applications

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