TWI738923B - 半導體結構及其製作方法 - Google Patents

半導體結構及其製作方法 Download PDF

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TWI738923B
TWI738923B TW106139721A TW106139721A TWI738923B TW I738923 B TWI738923 B TW I738923B TW 106139721 A TW106139721 A TW 106139721A TW 106139721 A TW106139721 A TW 106139721A TW I738923 B TWI738923 B TW I738923B
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Taiwan
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substrate
isolation layer
die
sidewall
conductive bump
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TW106139721A
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TW201916267A (zh
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游濟陽
張建國
林志豪
鄭榮宗
何冠霖
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台灣積體電路製造股份有限公司
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Abstract

根據本發明之一些實施例，一種半導體結構包括基板，其包括第一表面、與該第一表面相對之第二表面、大體上正交於該第一表面及該第二表面之第一側壁；隔離層，其圍繞並接觸該基板之該第一側壁；晶粒，其安置在該基板之該第二表面上方；第一導電凸塊，其安置在該基板之該第一表面處；及第二導電凸塊，其安置在該基板與該晶粒之間。

Description

半導體結構及其製作方法
本發明實施例係關於半導體結構及其製作方法。
使用半導體裝置之電子裝備對許多現代應用至關重要。隨著電子技術的進步，半導體裝置的大小越來越小，同時具有更大的功能性及更大量的積體電路。歸因於半導體裝置之尺度小型化，封裝被廣泛用於其低成本及相對簡單的製作操作。在封裝操作期間，數個半導體組件組裝在半導體裝置上。此外，在此小型半導體裝置內實施眾多製作操作。 然而，半導體裝置之製作操作涉及在此小型及薄型半導體裝置上之許多步驟及操作。小型化尺度的半導體裝置製作變得更加複雜。製作半導體裝置之複雜性的增加可能導致例如碎屑、裂紋之顯露、組件之分層或半導體裝置之高收得率損失的缺陷。半導體裝置產生不合期望的組態，此將進一步加劇材料浪費，並因此增加製作成本。因而，修改半導體裝置之結構及改進製作操作存在許多挑戰。
本發明之實施例係關於一種半導體結構，其包括：基板，其包括第一表面、與該第一表面相對之第二表面、大體上正交於該第一表面及該第二表面之第一側壁；隔離層，其圍繞並接觸該基板之該第一側壁；晶粒，其安置在該基板之該第二表面上方；第一導電凸塊，其安置在該基板之該第一表面處；及第二導電凸塊，其安置在該基板與該晶粒之間。 本發明之實施例係關於一種半導體結構，其包括：基板，其包括第一表面及與該第一表面相對之第二表面；電介質層，其安置在該第二表面上方或該第一表面下方；聚合物層，其安置在該電介質層上方或下方；隔離層，其圍繞並接觸該基板、該電介質層及該聚合物層；晶粒，其安置在該聚合物層上方；第一導電凸塊，其安置在該基板之該第一表面下方；及第二導電凸塊，其安置在該基板之該第二表面與該晶粒之間。 本發明之實施例係關於一種製作半導體結構之方法，其包括：提供基板，其包括第一表面、與該第一表面相對之第二表面、大體上正交於該第一表面及該第二表面之側壁；安置圍繞並接觸該基板之該側壁之隔離層；藉由第二導電凸塊將晶粒結合在該基板之該第二表面上方；以及將第一導電凸塊安置在該基板之該第一表面處。
下文揭示內容提供用於實施所提供標的物之不同特徵之許多不同實施例或實例。以下描述組件及配置的特定實例以簡化本發明實施例。此等組件及配置當然僅為實例，並且不希望為限制性的。舉例而言，在接下來的描述中在第二特徵上方或之上形成第一特徵可包括其中第一特徵及第二特徵直接接觸形成之實施例，並且亦可包括其中額外特徵可能形成在第一特徵與第二特徵之間使得第一特徵及第二特徵可能未直接接觸之實施例。另外，在各種實例中，本發明實施例可重複參考數字及/或字母。此重複係為了簡單及清楚的目的，並且其本身並不規定所論述的各種實施例及/或組態之間的關係。 此外，為便於描述如圖式中所說明的一個元件或特徵與另外的元件或特徵之關係，在本文中可使用例如」「下面」，「下方」，「下」，「上」，「上面」或類似者的空間相對術語。空間相對術語希望涵蓋除圖式中所描繪的定向之外的使用或操作中的裝置的不同定向。設備可以其他方式定向(旋轉90度或在其他定向上)，並且本文中使用的空間相對描述符同樣可相應地進行解釋。 在此文獻中，術語「耦合」亦可被稱為」「電耦合」，且術語」「連接」可被稱為」「電連接」。「耦合」及」「連接」亦可用於指示兩個或更多個元件彼此協作或相互作用。 亦可包括其他特徵及程序。舉例而言，可包括測試結構以輔助3D封裝或3DIC裝置之驗證測試。舉例而言，測試結構可包括形成在再分配層中或在基板上之測試墊，其允許3D封裝或3DIC之測試、探針及/或探針卡之使用及類似者。驗證測試可在中間結構以及最終結構上執行。另外，本文揭示之結構及方法可與併入已知良好晶粒的中間驗證的測試方法結合使用以增加良率並降低成本。 藉由數種操作製作半導體結構。藉由切割基板並將組件安置在基板上來製作半導體結構。在切割基板時容易顯露裂紋。裂紋的存在將導致基板內具有高應力，並且裂紋可能朝向基板之中心部分蔓延，以進一步削弱基板或半導體結構。 此外，在切割基板期間產生小的碎屑或碎片。在切割操作期間自基板剝離的彼等小碎屑將臨時附接在鋸片上或者安置在基板之側壁上，此將進一步引起在基板之側壁上產生裂紋。當裂紋顯露或碎屑安置在基板上方時，基板上之部件可能易於自基板分層。半導體結構之可靠性及效能將受到不利影響。 在本發明實施例中，揭示一種半導體結構。半導體結構包括由隔離層圍繞之基板。隔離層覆蓋基板之側壁以保護基板及基板上之組件。因而，可最小化或防止組件自基板分層及裂紋蔓延至基板中。半導體結構之可靠性及效能得以改進。 圖1為根據本發明之一些實施例的半導體結構100之示意性橫截面圖。在一些實施例中，半導體結構100包括基板101、圍繞基板101之隔離層102及安置在基板101上方之晶粒103。 在一些實施例中，半導體結構100為半導體封裝。在一些實施例中，半導體結構100為倒裝晶片封裝。在一些實施例中，半導體結構100為倒裝晶片球閘陣列(FCBGA)。在一些實施例中，半導體結構100為晶圓上晶片(CoW)結構。在一些實施例中，半導體結構100為三維積體電路(3D IC)。 在一些實施例中，在基板101上方用預定功能電路製造基板101。在一些實施例中，基板101包括若干導線，以及由導線連接之若干電組件，例如電晶體，二極體等等。在一些實施例中，基板101為半導電基板。在一些實施例中，基板101包括例如矽、鍺、鎵、砷或其組合之半導電材料。在一些實施例中，基板101為芯基板。在一些實施例中，基板101包括有機材料。在一些實施例中，基板101包括環氧樹脂、樹脂或玻璃纖維。在一些實施例中，基板101之橫截面區域為四邊形、矩形、正方形、多邊形或任何其他合適形狀。 在一些實施例中，基板101包括第一表面101a、與第一表面101a相對之第二表面101b，及大體上正交於第一表面101a及第二表面101b之第一側壁101c。在一些實施例中，第一側壁101c在第一表面101a與第二表面101b之間延伸。在一些實施例中，第一表面101a大體上平行於第二表面101b。 在一些實施例中，若干突出部或若干凹部安置在基板101之第一側壁101c上。在一些實施例中，突出部及凹部安置在第一側壁101c之一部分上方。在一些實施例中，突出部自第一側壁101c橫向突出。在一些實施例中，凹部橫向凹入基板101。在一些實施例中，安置在第一側壁101c上之突出部及凹部為在基板101之製造(例如單切割、切割、鋸切等)期間顯露的裂紋。在一些實施例中，安置在第一側壁101c上之突出部及凹部藉由在基板101的製造(例如單切割、切割、鋸切等)期間形成之碎屑來顯露。 在一些實施例中，第一側壁101c之粗糙度大體上大於第一表面101a之粗糙度及基板101之第二表面101b之粗糙度。在一些實施例中，第一側壁101c之粗糙度大體上不同於第一表面101a之粗糙度及基板101之第二表面101b之粗糙度。 在一些實施例中，第一導電凸塊101d安置在基板101之第一表面101a處。在一些實施例中，第一導電凸塊101d安置在第一基板101的下方。在一些實施例中，第一導電凸塊101d自基板101之第一表面101a突出。在一些實施例中，第一導電凸塊101d經組態以與導電結構結合。在一些實施例中，第一導電凸塊101d與基板101電連接。在一些實施例中，第一導電凸塊101d包括低溫可回流材料，例如焊料、無鉛焊料等等。在一些實施例中，第一導電凸塊101d包括鉛、錫、銅、金、鎳或類似者或其組合。在一些實施例中，第一導電凸塊101d為焊球、球閘陣列(BGA)球、受控塌陷晶片連接(C4)凸塊、微凸塊、柱或類似者。在一些實施例中，第一導電凸塊101d為球形或半球形。 在一些實施例中，隔離層102圍繞基板101。在一些實施例中，隔離層102安置在基板101之一側處。在一些實施例中，隔離層102與基板101接觸。在一些實施例中，隔離層102與基板101之第一側壁101c接觸。在一些實施例中，隔離層102沿基板101之第一側壁101c延伸並且安置成與基板101之第一側壁101c共形。在一些實施例中，隔離層102沿基板101之厚度延伸。在一些實施例中，隔離層102垂直延伸。在一些實施例中，基板101之第一側壁101c完全由隔離層102覆蓋。在一些實施例中，隔離層102安置在第一表面101a之一部分或第二表面101b之一部分上方以覆蓋基板101之隅角。 在一些實施例中，隔離層102經組態以保護基板101不受損壞、碎屑或其他污染。在一些實施例中，隔離層102經組態以密封在基板101之第一側壁101c處顯露的裂紋或者防止裂紋蔓延至基板101中。在一些實施例中，隔離層102經組態以密封突出部之間或凹部之間的間隙。 在一些實施例中，隔離層102包括聚合物材料、金屬材料或導電材料。在一些實施例中，隔離層102包括焊料遮罩、阻焊劑，環氧樹脂、聚醯亞胺(PI)、聚苯并噁唑(PBO)、模塑膠或類似者。在一些實施例中，隔離層102包括鋁、銅、鎳、金、銀或類似者。在一些實施例中，隔離層102為聚合物膜。在一些實施例中，隔離層102為用於將基板101與周圍環境電磁隔離之電磁屏蔽。 在一些實施例中，隔離層102包括第三表面102a及大體上正交於第三表面102a之第二側壁102b。在一些實施例中，第三表面102a與基板101之第一表面101a或第二表面101b大體上共面。在一些實施例中，第二側壁102b大體上平行於基板101之第一側壁101c。在一些實施例中，基板101與隔離層102之間的界面大體上平行於隔離層102之第二側壁102b。 在圖2中所展示之一些實施例中，隔離層102為條狀或框架狀。在一些實施例中，隔離層102沿著基板101之邊緣安置並與其接觸。在一些實施例中，基板101由隔離層102圍封。 返回參考圖1，在一些實施例中，晶粒103安置在基板101上方。在一些實施例中，晶粒103安置在基板101之第二表面101b上方。在一些實施例中，晶粒103包括面向基板101之第二表面101b之第四表面103a、與第四表面103a相對之第五表面103b，及大體上正交於第四表面103a及第五表面103b之第三側壁103c。在一些實施例中，第三側壁103c在第四表面103a與第五表面103b之間延伸。在一些實施例中，第四表面103a大體上平行於第五表面103b。 在一些實施例中，晶粒103用在晶粒103內的預定功能電路製造。在一些實施例中，藉由機械或雷射刀片使晶粒103自半導體晶圓分離。在一些實施例中，晶粒103包含適用於特定應用的各種電路。在一些實施例中，電路包括各種裝置，例如電晶體、電容器、電阻器、二極體及/或類似者。在一些實施例中，晶粒103為邏輯裝置晶粒、圖形處理單元(GPU)晶粒、應用處理(AP)晶粒、記憶體晶粒、高頻寬記憶體(HBM)晶粒或類似者。在一些實施例中，晶粒103為晶片或封裝。在一些實施例中，晶粒103具有四邊形，矩形或正方形的頂部橫截面(來自圖1中所展示之半導體結構100之頂視圖的橫截面)。 在一些實施例中，第二導電凸塊103d安置在基板101與晶粒103之間。在一些實施例中，晶粒103藉由第二導電凸塊103d結合在基板101上方。在一些實施例中，第二導電凸塊103d安置在晶粒103之第四表面103a及基板101之第二表面101b處。在一些實施例中，第二導電凸塊103d自晶粒103之第四表面103a突出。在一些實施例中，第二導電凸塊103d經組態以與導電結構結合。在一些實施例中，第二導電凸塊103d與晶粒103電連接。在一些實施例中，晶粒103藉由第二導電凸塊103d電連接至基板101。 在一些實施例中，第二導電凸塊103d包括低溫可回流材料，例如焊料、無鉛焊料等等。在一些實施例中，第二導電凸塊103d包括鉛、錫、銅、金、鎳或類似者或其組合。在一些實施例中，第二導電凸塊103d為焊球、倒裝晶片凸塊、球閘陣列(BGA)球、受控塌陷晶片連接(C4)凸塊、微凸塊、柱或類似者。在一些實施例中，第二導電凸塊103d為球形或半球形。 在一些實施例中，底部填充材料104安置在晶粒103及基板101之間。在一些實施例中，底部填充材料104圍繞第二導電凸塊103d及晶粒103的一部分。在一些實施例中，底部填充材料104與晶粒103之第三側壁103c、基板101之第二表面及第二導電凸塊103d接觸。在一些實施例中，底部填充材料104填充兩個鄰近第二導電凸塊103d之間的間隔。在一些實施例中，底部填充材料104為用於保護第二導電凸塊103d或固定晶粒103與基板101之間的結合之電絕緣黏合劑。在一些實施例中，底部填充材料104包括環氧樹脂、樹脂、環氧樹脂模塑膠等等。 圖3為根據本發明之一些實施例之半導體結構200的示意性橫截面圖。在一些實施例中，半導體結構200包括基板101、圍繞基板101之隔離層102及安置在基板101上方之晶粒103，其具有與上文描述或圖1中說明之晶粒類似的組態。 在一些實施例中，通路101e安置在基板101內。在一些實施例中，通路101e延伸通過基板101。在一些實施例中，通路101e在基板101之第一表面101a與第二表面101b之間延伸。在一些實施例中，通路101e包括導電材料，例如銅、銀、金、鋁等等。在一些實施例中，通路101e為穿基板通路或穿矽通路(TSV)。在一些實施例中，通路101e由隔離層102圍繞。在一些實施例中，通路101e電連接至第一導電凸塊101d、第二導電凸塊103d或晶粒103。 在一些實施例中，電介質層101f安置在第二表面101b的上方或基板101之第一表面101a下方。在一些實施例中，電介質層101f包括一者安置或堆疊在另一者上方之電介質材料的一或多個層。在一些實施例中，電介質層101f包括電介質材料，例如氧化矽、碳化矽、氮氧化矽、氮化矽或類似者。 在一些實施例中，電介質層101f由隔離層102圍繞。在一些實施例中，隔離層102與電介質層101f接觸。在一些實施例中，隔離層102與電介質層101f之第四側壁101g接觸。在一些實施例中，第四側壁101g與基板之第一側壁101c大體上共面。在一些實施例中，第四側壁101g大體上平行於隔離層102之第二側壁102b。在一些實施例中，隔離層102經組態以保護電介質層101f免受損壞或污染並且防止電介質層101f之分層。 在一些實施例中，若干突出部或若干凹部安置在電介質層101f之第四側壁101g上。在一些實施例中，突出部及凹部安置在第四側壁101g之一部分上方。在一些實施例中，突出部自第四側壁101g橫向突出。在一些實施例中，凹部橫向凹入電介質層101f。在一些實施例中，突出部及凹部為在半導體結構200之製造(例如單切割、切割、鋸切等等)期間顯露的裂紋。在一些實施例中，突出部及凹部由在半導體結構200之製造(例如單切割、切割、鋸切等等)期間形成之碎屑顯露。 在一些實施例中，聚合物層101h安置在電介質層101f的上方或下方。在一些實施中，聚合物層101h包括聚合物材料，例如焊料遮罩、阻焊劑、環氧樹脂、聚醯亞胺(PI)、聚苯并噁唑(PBO)或類似者。在一些實施例中，聚合物層101h為用於圍繞第一導電凸塊101d或第二導電凸塊103d之焊料遮罩。在一些實施例中，暴露聚合物層101h。 在一些實施例中，聚合物層101h由隔離層102圍繞。在一些實施例中，隔離層102與聚合物層101h接觸。在一些實施例中，隔離層102圍繞並接觸基板101、電介質層101f及聚合物層101h。在一些實施例中，隔離層102與聚合物層101h之第五側壁101i接觸。在一些實施例中，隔離層102圍繞並接觸基板101之第一側壁101c、電介質層101f之第四側壁101g及聚合物層101h之第五側壁101i。在一些實施例中，晶粒103安置在聚合物層101h的上方。在一些實施例中，隔離層102經組態以保護聚合物層101h免受損傷或污染並防止聚合物層101h之分層。 在一些實施例中，隔離層102完全覆蓋基板101之第一側壁101c、電介質層101f之第四側壁101g及聚合物層101h之第五側壁101i。在一些實施例中，第五側壁101i大體上與基板之第一側壁101c及電介質層101f之第四側壁101g共面。在一些實施例中，聚合物層101h大體上平行於隔離層102之第二側壁102b。在一些實施例中，隔離層102、基板101、電介質層101f及聚合物層101h之間的界面大體上正交於基板101之第一表面101a或第二表面101b。 在一些實施例中，若干突出部或若干凹部安置在聚合物層101h之第五側壁101i上。在一些實施例中，突出部及凹部安置在第五側壁101i之一部分上方。在一些實施例中，突出部自第五側壁101i橫向突出。在一些實施例中，凹部橫向凹入聚合物層101h。在一些實施例中，安置在第五側壁101i上之突出部及凹部為在半導體結構200之製造(例如單切割、切割、鋸切等等)期間顯露的裂紋。在一些實施例中，安置在第五側壁101i上之突出部及凹部由在半導體結構200之製造(例如單切割、切割、鋸切等等)期間形成的碎屑顯露。 在一些實施例中，第四側壁101g之粗糙度大體上大於第一表面101a之粗糙度、基板101之第二表面101b之粗糙度或電介質層101f與聚合物層101h之間的電介質層101f之表面之粗糙度。在一些實施例中，第四側壁101g之粗糙度大體上不同於第一表面101a之粗糙度、基板101之第二表面101b之粗糙度或電介質層101f與聚合物層101h之間的電介質層101f之表面之粗糙度。 在一些實施例中，第五側壁101i之粗糙度大體上大於第一表面101a之粗糙度、基板101之第二表面101b之粗糙度、電介質層101f與聚合物層101h之間的電介質層101f之表面之粗糙度或自底部填充材料104暴露的聚合物層101h之表面之粗糙度。在一些實施例中，第五側壁101i之粗糙度大體上不同於基板101之第二表面101b之粗糙度、電介質層101f與聚合物層101h之間的電介質層101f之表面之粗糙度或自底部填充材料104暴露的聚合物層101h之表面之粗糙度。 在一些實施例中，導電部件101j由電介質層101f或聚合物層101h圍繞。在一些實施例中，導電部件101j在電介質層101f內或聚合物層101h內延伸。在一些實施例中，導電部件101j電連接至第一導電凸塊101d或第二導電凸塊103d。在一些實施例中，導電部件101j與通路101e電連接。在一些實施例中，導電部件101j安置在通路101e的上方或下方。在一些實施例中，第一導電凸塊101d安置在導電部件101j的上方或下方。在一些實施例中，第二導電凸塊103d安置在導電部件101j的上方。在一些實施例中，晶粒103電連接至第一導電凸塊101d、導電部件101j、第二導電凸塊103d或通路101e。在一些實施例中，導電部件101j為導電墊、導線、凸塊墊、互連結構或類似者。 在一些實施例中，散熱部件105安置在晶粒103、基板101及隔離層102上方。在一些實施例中，散熱部件105安置在聚合物層101h的至少一部分及電介質層101f的至少一部分上方。在一些實施例中，散熱部件105圍封晶粒103。在一些實施例中，散熱部件105藉由黏合劑106附接至隔離層102。在一些實施例中，散熱部件105藉由黏合劑106附接至隔離層102的一部分及聚合物層101h的一部分。在一些實施例中，散熱部件105藉由黏合劑106附接至聚合物層101h。在一些實施例中，散熱部件105經組態以使熱量自晶粒103消散至周圍環境。在一些實施例中，散熱部件105包括例如鋁、銅等等的導熱材料。在一些實施例中，散熱部件105為散熱器或散熱片。 在一些實施例中，熱界面材料(TIM) 107安置在散熱部件105與晶粒103之間。在一些實施例中，TIM 107安置在晶粒103之第五表面103b上。在一些實施例中，TIM 107經組態以將熱量自晶粒103傳遞至散熱部件105。在一些實施例中，TIM 107為熱黏合劑、熱凝膠、熱膠帶或類似者。 在一些實施例中，藉由方法300形成半導體結構100。方法300包括多個操作，並且描述及說明不被認為是對操作序列的限制。圖4為製作半導體結構100之方法300的實施例。方法300包括數個操作(301、302、303及304)。 在操作301中，如圖5A所展示，接納或提供基板101。在一些實施例中，基板101為半導電基板。在一些實施例中，基板101包括例如矽、鍺、鎵、砷或其組合之半導電材料。在一些實施例中，基板101為芯基板。在一些實施例中，基板101包括有機材料。在一些實施例中，基板101包括環氧樹脂、樹脂或玻璃纖維。 在一些實施例中，基板101包括第一表面101a、與第一表面101a相對之第二表面101b及大體上正交於第一表面101a及第二表面101b之第一側壁101c。在一些實施例中，第一側壁101c在第一表面101a與第二表面101b之間延伸。在一些實施例中，基板101具有與上文描述或圖1、圖2或圖3中所說明之基板類似的組態。 在一些實施例中，藉由單切割、切割、鋸切或其他類似操作形成基板101。在一些實施例中，鋸切基板101以形成第一側壁101c。在一些實施例中，在單切割、切割或鋸切操作之後，在基板101之第一側壁101c上形成若干突出部或若干凹部。在一些實施例中，突出部及凹部形成在第一側壁101c的一部分上方。在一些實施例中，形成在第一側壁101c上之突出部及凹部為在基板101之製造(例如單切割、切割、鋸切或其他類似操作)期間顯露的裂紋。在一些實施例中，在基板101之製造(例如單切割、切割、鋸切或其他類似操作)期間形成碎屑，並且彼等碎屑與基板101碰撞從而在基板101上形成裂紋。 在一些實施例中，因為第一側壁101c經歷切割操作，所以第一側壁101c之粗糙度大體上大於第一表面101a之粗糙度及基板101之第二表面101b之粗糙度。在一些實施例中，第一側壁101c之粗糙度大體上不同於第一表面101a之粗糙度及基板101之第二表面101b之粗糙度。 在操作302中，如圖5B中所展示，安置隔離層102。在一些實施例中，隔離層102圍繞並接觸基板101之第一側壁101c。在一些實施例中，隔離層102沿基板101之第一側壁101c延伸並且安置成與基板101之第一側壁101c共形。在一些實施例中，隔離層102沿基板101之厚度延伸。在一些實施例中，隔離層102垂直延伸。在一些實施例中，基板101之第一側壁101c完全由隔離層102覆蓋。在一些實施例中，藉由塗覆、滾壓、黏貼、模製或任何其他合適操作來安置隔離層102。在一些實施例中，隔離層102塗覆在第一側壁101c上或附接至第一側壁101c。在一些實施例中，沿著基板101之所有邊緣模製隔離層102。在一些實施例中，在安置隔離層102之前執行基板101之切割及基板101之第一側壁101c的形成。 在一些實施例中，隔離層102經組態以保護基板101免受損壞、碎屑或其他污染。在一些實施例中，隔離層102經組態以密封在基板101之第一側壁101c處顯露的裂紋或者防止裂紋蔓延至基板101中。在一些實施例中，隔離層102經組態以密封突出部之間或凹部之間的間隙。 在一些實施例中，隔離層102包括聚合物材料、金屬材料或導電材料。在一些實施例中，隔離層102包括焊料遮罩、阻焊劑、環氧樹脂、聚醯亞胺(PI)、聚苯并噁唑(PBO)、模塑膠或類似者。在一些實施例中，隔離層102包括鋁、銅、鎳、金、銀或類似者。在一些實施例中，隔離層102為聚合物膜。在一些實施例中，隔離層102為用於將基板101與周圍環境電磁隔離之電磁屏蔽。 在一些實施例中，隔離層102包括第三表面102a及大體上正交於第三表面102a之第二側壁102b。在一些實施例中，第三表面102a與基板101之第一表面101a或第二表面101b大體上共面。在一些實施例中，第二側壁102b大體上平行於基板101之第一側壁101c。在一些實施例中，基板101與隔離層102之間的界面大體上平行於隔離層102之第二側壁102b。在一些實施例中，隔離層102具有與上文描述或圖1、圖2或圖3中所說明之基板類似的組態。 在操作303中，如圖5C中所展示，將晶粒103結合在基板101上方。在一些實施例中，晶粒103為邏輯裝置晶粒、圖形處理單元(GPU)晶粒、應用處理(AP)晶粒、記憶體晶粒、高頻寬記憶體(HBM)晶粒或類似者。在一些實施例中，晶粒103為晶片或封裝。在一些實施例中，晶粒103包括面向基板101之第二表面101b之第四表面103a、與第四表面103a相對之第五表面103b，及大體上正交於第四表面103a及第五表面103b之第三側壁103c。在一些實施例中，第三側壁103c在第四表面103a與第五表面103b之間延伸。在一些實施例中，晶粒103具有與上文描述或圖1、圖2或圖3中所說明之晶粒類似的組態。 在一些實施例中，晶粒103藉由第二導電凸塊103d結合在基板101之第二表面101b上方。在一些實施例中，晶粒103藉由第二導電凸塊103d電連接至基板101。在一些實施例中，第二導電凸塊103d安置在晶粒103之第四表面103a及基板101之第二表面101b處。在一些實施例中，晶粒103藉由第二導電凸塊103d電連接至基板101。在一些實施例中，第二導電凸塊103d包括低溫可回流材料，例如焊料、無鉛焊料等等。在一些實施例中，第二導電凸塊103d包括鉛、錫、銅、金、鎳或類似者或其組合。在一些實施例中，第二導電凸塊103d為焊球、倒裝晶片凸塊、球閘陣列(BGA)球、受控塌陷晶片連接(C4)凸塊、微凸塊，柱或類似者。在一些實施例中，藉由球安裝、模板黏貼或任何其他合適操作來安置第二導電凸塊103d。在一些實施例中，第二導電凸塊103d具有與上文描述或圖1、圖2或圖3中所說明之導電凸塊類似的組態。 在一些實施例中，底部填充材料104安置在基板101上方並且圍繞晶粒103及第二導電凸塊103d。在一些實施例中，底部填充材料104與晶粒103之第三側壁103c、基板101之第二表面及第二導電凸塊103d接觸。在一些實施例中，底部填充材料104填充兩個鄰近第二導電凸塊103d之間的間隔。在一些實施例中，底部填充材料104為用於保護第二導電凸塊103d或固定晶粒103與基板101之間的結合之電絕緣黏合劑。在一些實施例中，底部填充材料104包括環氧樹脂、樹脂、環氧樹脂模塑膠等等。在一些實施例中，藉由流動，注射或任何其他合適操作來安置底部填充材料104。在一些實施例中，底部填充材料104具有與上文描述或圖1、圖2或圖3中所說明之底部填充材料類似的組態。在一些實施例中，形成半導體結構100。 在操作304中，如圖5D中所展示，第一導電凸塊101d安置在基板101之第一表面101a處。在一些實施例中，第一導電凸塊101d電連接至基板101。在一些實施例中，第一導電凸塊101d經組態以與導電結構結合。在一些實施例中，第一導電凸塊101d包括低溫可回流材料，例如焊料，無鉛焊料等等。在一些實施例中，第一導電凸塊101d包括鉛、錫、銅、金、鎳或類似者或其組合。在一些實施例中，第一導電凸塊101d為焊球、球閘陣列(BGA)球、受控塌陷晶片連接(C4)凸塊、微凸塊、柱或類似者。在一些實施例中，藉由球安裝、模板黏貼或任何其他合適操作來安置第一導電凸塊101d。在一些實施例中，第一導電凸塊101d具有與上文描述或圖1、圖2或圖3中所說明之導電凸塊類似的組態。 在一些實施例中，藉由方法400形成半導體結構200。方法400包括數個操作，並且描述及說明不被認為是對操作序列的限制。圖6為製作半導體結構200之方法400的實施例。方法400包括數個操作(401、402、403、404及405)。 在操作401中，如圖7A中所展示，接納或提供基板101。在一些實施例中，操作401類似於操作301。在一些實施例中，基板101包括第一表面101a、與第一表面101a相對之第二表面101b。 在一些實施例中，通路101e形成在基板101內。在一些實施例中，通路101e延伸穿過基板101。在一些實施例中，通路101e在基板之第一表面101a與第二表面101b之間延伸。在一些實施例中，藉由去除基板101之一部分以形成開口並且將導電材料安置至開口中而形成通路101e。在一些實施例中，去除基板101的部分包括微影、蝕刻或任何其他合適操作。在一些實施例中，導電材料之安置包括電鍍、濺射或任何其他合適操作。在一些實施例中，導電材料包括銅、銀、金、鋁等等。在一些實施例中，通路101e為穿基板通路或穿矽通路(TSV)。在一些實施例中，通路101e具有與上文描述或圖3中所說明之通路類似的組態。 在操作402中，如圖7B中所展示，電介質層101f安置在基板101的上方或下方。在一些實施例中，電介質層101f安置在第二表面101b上方或基板101之第一表面101a下方。在一些實施例中，電介質層101f包括電介質材料，例如氧化矽、碳化矽、氮氧化矽、氮化矽或類似者。在一些實施例中，藉由任何合適操作(例如化學氣相沈積(CVD)、旋塗、氧化或類似者)來安置電介質層101f。在一些實施例中，電介質層101f具有與上文描述或圖3中所說明之電介質層類似的組態。 在操作403中，如圖7B中所展示，聚合物層101h安置在電介質層101f上方或下方。在一些實施中，聚合物層101h包括聚合物材料，例如焊料遮罩、阻焊劑、環氧樹脂、聚醯亞胺(PI)、聚苯并噁唑(PBO)或類似者。在一些實施中，藉由旋塗、篩選或任何其他合適操作來安置聚合物層101h。在一些實施例中，聚合物層101h具有與上文描述或圖3中所說明之聚合物層類似的組態。 在一些實施例中，鋸切電介質層101f以形成第四側壁101g。在一些實施例中，在單切割、切割或鋸切操作之後，在電介質層101f之第四側壁101g上形成若干突出部或若干凹部。在一些實施例中，突出部及凹部形成在第四側壁101g的一部分上方。在一些實施例中，形成在第四側壁101g上之突出部及凹部為在單切割、切割或鋸切操作期間顯露的裂紋。在一些實施例中，在單切割、切割或鋸切操作期間形成碎屑，並且彼等碎屑與電介質層101f碰撞以在電介質層101f上形成裂紋。 在一些實施例中，第四側壁101g之粗糙度大體上大於第一表面101a之粗糙度、基板101之第二表面101b之粗糙度，或電介質層101f與聚合物層101h之間的電介質層101f之表面之粗糙度，此係因為第四側壁101g已經歷單切割、切割或鋸切操作。在一些實施例中，第四側壁101g之粗糙度大體上不同於第一表面101a之粗糙度、基板101之第二表面101b之粗糙度，或電介質層101f與聚合物層101h之間的電介質層101f之表面之粗糙度。 在一些實施例中，鋸切聚合物層101h以形成第五側壁101i。在一些實施例中，在單切割、切割或鋸切操作之後，在聚合物層101h之第五側壁101i上形成若干突出部或若干凹部。在一些實施例中，突出部及凹部形成在第五側壁101i的一部分上方。在一些實施例中，形成在第五側壁101i上之突出部及凹部為在單切割、切割或鋸切操作期間顯露的裂紋。在一些實施例中，在單切割、切割或鋸切操作期間形成碎屑，並且彼等碎屑與聚合物層101h碰撞從而在聚合物層101h上形成裂紋。 在一些實施例中，第五側壁101i之粗糙度大體上大於第一表面101a之粗糙度、基板101之第二表面101b之粗糙度或聚合物層101h之暴露表面之粗糙度，此係因為第五側壁101i已經歷單切割、切割或鋸切操作。在一些實施例中，第五側壁101i之粗糙度大體上不同於第一表面101a之粗糙度、基板101之第二表面101b之粗糙度，或聚合物層101h之暴露表面之粗糙度。 在一些實施例中，如圖7B中所展示，在電介質層101f及聚合物層101h內形成導電部件101j。在一些實施例中，導電部件101j由電介質層101f或聚合物層101h圍繞。在一些實施例中，導電部件101j在電介質層101f內或聚合物層101h內延伸。在一些實施例中，導電部件101j與通路101e電連接。在一些實施例中，導電部件101j安置在通路101e上方或下方。在一些實施例中，導電部件101j為導電墊、導線、凸塊墊、互連結構或類似者。 在一些實施例中，藉由去除電介質層101f的一部分或聚合物層101h的一部分以形成開口，且接著將導電材料安置至開口中而形成導電部件101j。在一些實施例中，去除電介質層101f或聚合物層101h的部分包括微影、蝕刻或任何其他合適操作。在一些實施例中，導電材料之安置包括電鍍、濺射或任何其他合適操作。在一些實施例中，導電材料包括銅、銀、金、鋁等等。在一些實施例中，導電部件101j具有與上文描述或圖3中所說明之導電部件類似的組態。 在操作404中，如圖7C中所展示，安置隔離層102。在一些實施例中，隔離層102圍繞並接觸基板101、電介質層101f及聚合物層101h。在一些實施例中，藉由塗覆、滾壓、黏貼、模製或任何其他合適操作來安置隔離層102。在一些實施例中，隔離層102經組態以保護基板101、電介質層101f及聚合物層101h免受損壞、碎屑或其他污染。在一些實施例中，隔離層102經組態以防止裂紋蔓延至基板101、電介質層101f及聚合物層101h中。在一些實施例中，隔離層102經組態以密封形成在基板101、電介質層101f或聚合物層101h上之裂紋。 在一些實施例中，隔離層102包括聚合物、金屬或導電材料。在一些實施例中，隔離層102包括焊料遮罩、阻焊劑、環氧樹脂、聚醯亞胺(PI)、聚苯并噁唑(PBO)、模塑膠或類似者。在一些實施例中，隔離層102包括鋁、銅、鎳、金、銀或類似者。在一些實施例中，隔離層102為聚合物膜。在一些實施例中，隔離層102具有與上文描述或圖1、圖2或圖3中所說明之隔離層類似之組態。 在操作405中，如圖7D中所展示，晶粒103安置在基板101上方。在一些實施例中，操作405與操作303相同。在一些實施例中，晶粒103藉由第二導電凸塊103d結合在基板101上方。在一些實施例中，晶粒103及第二導電凸塊103d具有與上文描述或圖1、圖2或圖3中所說明之彼等晶粒及導電凸塊類似之組態。 在一些實施例中，如圖7E中所展示，第一導電凸塊101d安置在導電部件101j上方或下方。在一些實施例中，第一導電凸塊101d之安置類似於操作304。在一些實施例中，第一導電凸塊101d自聚合物層101h突出。在一些實施例中，晶粒103藉由第二導電凸塊103d、通路101e及導電部件101j電連接至第一導電凸塊101d。 在圖7E中所展示之一些實施例中，散熱部件105安置在晶粒103、基板101及隔離層102上方。在一些實施例中，散熱部件105藉由黏合劑106附接至隔離層102。在一些實施例中，散熱部件105藉由黏合劑106附接至隔離層102的一部分及聚合物層101h的一部分。在一些實施例中，散熱部件105藉由黏合劑106附接至聚合物層101h。在一些實施例中，散熱部件105為散熱器或散熱片。在一些實施例中，散熱部件105具有與上文描述或圖3中所說明之散熱部件類似之組態。 在一些實施例中，熱界面材料(TIM) 107安置在散熱部件105與晶粒103之間。在一些實施例中，TIM 107為熱黏合劑、熱凝膠，熱膠帶或類似者。在一些實施例中，藉由流動、注射或任何其他合適的操作來安置TIM 107。在一些實施例中，TIM 107具有與上文描述或圖3中所說明之TIM類似之組態。 在本發明實施例中，半導體結構包括安置在基板之側壁上方的隔離層。基板在製造時鋸切，並因此裂紋在側壁處形成或碎屑形成並在製造時與基板碰撞。基板之側壁由隔離層覆蓋，使得裂紋將不會蔓延至基板中，並且碎屑或其他污染物將不會進入基板或與基板碰撞。因此，可最小化或防止基板上之損壞、基板上之組件分層及裂紋蔓延至基板中。 在一些實施例中，半導體結構包括：基板，其包括第一表面、與第一表面相對之第二表面、大體上正交於第一表面及第二表面之第一側壁；圍繞並接觸基板之第一側壁之隔離層；安置在基板之第二表面上方的晶粒；安置在基板之第一表面處之第一導電凸塊；以及安置在基板與晶粒之間的第二導電凸塊。 在一些實施例中，隔離層完全覆蓋基板之第一側壁。在一些實施例中，隔離層包括聚合物材料或金屬材料。隔離層係條狀或框架狀。在一些實施例中，隔離層包括第三表面及大體上正交於第三表面之第二側壁，第三表面與基板之第一表面或第二表面大體上共面，並且第二側壁大體上平行於基板之第一側壁。 在一些實施例中，半導體結構包括：基板，其包括第一表面及與第一表面相對之第二表面；安置在第二表面上方或第一表面下方的電介質層；安置在電介質層上方或下方的聚合物層；圍繞並接觸基板、電介質層及聚合物層之隔離層；安置在聚合物層上方的晶粒；安置在基板之第一表面下方的第一導電凸塊；以及安置在基板之第二表面與晶粒之間的第二導電凸塊。 在一些實施例中，隔離層圍繞並接觸基板之側壁、電介質層及聚合物層。在一些實施例中，隔離層完全覆蓋基板之側壁、電介質層及聚合物層。在一些實施例中，基板之側壁、電介質層及聚合物層大體上彼此共面。在一些實施例中，隔離層、基板、電介質層及聚合物層之間的界面大體上正交於基板之第一表面或第二表面。在一些實施例中，半導體結構進一步包括安置在晶粒、基板及隔離層上方的散熱部件。在一些實施例中，散熱部件安置在聚合物層的至少一部分及電介質層的至少一部分的上方。在一些實施例中，散熱部件藉由黏合劑附接至隔離層或聚合物層。在一些實施例中，半導體結構進一步包括安置在散熱部件與晶粒之間的熱界面材料(TIM)。在一些實施例中，半導體結構進一步包括由聚合物層或電介質層圍繞之導電部件，其中導電部件電連接至第一導電凸塊或第二導電凸塊。在一些實施例中，半導體結構進一步包括延伸穿過基板之通路，其中通路由隔離層圍繞，並且電連接至第一導電凸塊、第二導電凸塊或晶粒。在一些實施例中，半導體結構進一步包括圍繞第二導電凸塊及晶粒的一部分之底部填充材料。 在一些實施例中，一種製作半導體結構之方法包括：提供基板，該基板包括第一表面、與第一表面相對之第二表面、大體上正交於第一表面及第二表面之側壁；安置圍繞並接觸基板之側壁之隔離層；藉由第二導電凸塊將晶粒結合在基板之第二表面上方；以及將第一導電凸塊安置在基板之第一表面處。 在一些實施例中，隔離層之安置包括塗覆、滾壓，黏貼或模製操作。在一些實施例中，該方法進一步包括在安置隔離層之前切割基板以形成基板之側壁。 上述概述若干實施例之特徵，使得熟習此項技術者可更好地理解本發明實施例之態樣。熟習此項技術者應瞭解，其可容易地將本發明實施例用作設計或修改用於實行本文介紹的實施例之相同目的及/或實現本文介紹之實施例的相同優點的其他程序及結構之基礎。熟習此項技術者亦應該認識到，此類等效構造不脫離本發明實施例之精神及範疇，並且在不脫離本發明實施例之精神及範疇的情況下，其可在本文進行各種改變、替換及變更。
100‧‧‧半導體結構101‧‧‧基板101a‧‧‧第一表面101b‧‧‧第二表面101c‧‧‧第一側壁101d‧‧‧第一導電凸塊101e‧‧‧通路101f‧‧‧電介質層101g‧‧‧第四側壁101h‧‧‧聚合物層101i‧‧‧第五側壁101j‧‧‧導電部件102‧‧‧隔離層102a‧‧‧第三表面102b‧‧‧第二側壁103‧‧‧晶粒103a‧‧‧第四表面103b‧‧‧第五表面103c‧‧‧第三側壁103d‧‧‧第二導電凸塊104‧‧‧底部填充材料105‧‧‧散熱部件106‧‧‧黏合劑107‧‧‧熱界面材料(TIM)200‧‧‧半導體結構300‧‧‧方法301‧‧‧操作302‧‧‧操作303‧‧‧操作304‧‧‧操作400‧‧‧方法401‧‧‧操作402‧‧‧操作403‧‧‧操作404‧‧‧操作405‧‧‧操作
當與附圖一起閱讀時，從以下詳細描述中可最好地理解本發明實施例之態樣。要強調的是，根據行業中之標準實踐，未按比例繪製各種特徵。事實上，為清楚地論述，可任意地增加或減小各種特徵之尺寸。 圖1為根據本發明之一些實施例之半導體結構的示意性橫截面圖。 圖2為沿AA'之圖1之半導體結構的示意性頂部橫截面圖。 圖3為根據本發明之一些實施例之半導體結構的示意性橫截面圖。 圖4為根據本發明之一些實施例之製作半導體結構的方法之流程圖。 圖5A至圖5D為根據本發明之一些實施例之由圖4的方法製作半導體結構之示意圖。 圖6為根據本發明之一些實施例的製作半導體結構之方法的流程圖。 圖7A至圖7E為根據本發明之一些實施例之由圖6的方法製作半導體結構之示意圖。
100‧‧‧半導體結構
101‧‧‧基板
101a‧‧‧第一表面
101b‧‧‧第二表面
101c‧‧‧第一側壁
101d‧‧‧第一導電凸塊
102‧‧‧隔離層
102a‧‧‧第三表面
102b‧‧‧第二側壁
103‧‧‧晶粒
103a‧‧‧第四表面
103b‧‧‧第五表面
103c‧‧‧第三側壁
103d‧‧‧第二導電凸塊
104‧‧‧底部填充材料

Claims (10)

  1. 一種半導體結構，其包含：基板，其包括第一表面、與該第一表面相對之第二表面、大體上正交於該第一表面及該第二表面之第一側壁；隔離層，其圍繞並接觸該基板之該第一側壁；晶粒，其安置在該基板之該第二表面上方；第一導電凸塊，其安置在該基板之該第一表面處；及第二導電凸塊，其安置在該基板與該晶粒之間，其中，該隔離層包括第一暴露表面和與該第一暴露表面相對之第二暴露表面，該第一暴露表面與該基板的該第一表面大致上共面的，該第二暴露表面與該基板的該第二表面大致上共面的。
  2. 如請求項1之半導體結構，其中該隔離層完全覆蓋該基板之該第一側壁。
  3. 如請求項1之半導體結構，其中該隔離層包含與該第一暴露表面及該第二暴露表面大體上正交之一第二側壁，該第二側壁大體上平行於該基板之該第一側壁。
  4. 一種半導體結構，其包括：一基板，其包含一第一表面及與該第一表面相對之一第二表面；一電介質層，其安置在該第二表面上方或該第一表面下方； 一聚合物層，其安置在該電介質層上方或下方；一隔離層，其圍繞並接觸該基板、該電介質層及該聚合物層；一晶粒，其安置在該聚合物層上方；一第一導電凸塊，其安置在該基板之該第一表面下方；及一第二導電凸塊，其安置在該基板之該第二表面與該晶粒之間。
  5. 如請求項4之半導體結構，其中該隔離層圍繞並接觸該基板、該電介質層及該聚合物層之一側壁。
  6. 如請求項4之半導體結構，其中該隔離層、該基板、該電介質層及該聚合物層之間之一界面大體上正交於該第一基板之該第一表面或該第二表面。
  7. 如請求項4之半導體結構，其進一步包括安置在該晶粒、該基板及該隔離層上方之一散熱部件。
  8. 一種製作半導體結構之方法，其包括：提供一基板，該基板包含一第一表面、與該第一表面相對之一第二表面、大體上正交於該第一表面及該第二表面之一側壁；安置圍繞並接觸該基板之該側壁之一隔離層；藉由一第二導電凸塊將一晶粒結合在該基板之該第二表面上方；及將一第一導電凸塊安置在該基板之該第一表面處，其中，該隔離層包括第一暴露表面和與該第一暴露表面相對之第二 暴露表面，該第一暴露表面與該基板的該第一表面大致上共面的，該第二暴露表面與該基板的該第二表面大致上共面的。
  9. 如請求項8之方法，其中該隔離層之該安置包含塗覆、滾壓、黏貼或模製操作。
  10. 如請求項8之方法，其進一步包括在該隔離層之該安置之前切割該基板以形成該基板之該側壁。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130299976A1 (en) * 2012-01-09 2013-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Die Connection System and Method
US20160204073A1 (en) * 2015-01-09 2016-07-14 Samsung Electronics Co., Ltd. Semiconductor Package and Method of Manufacturing the Same
US20170125387A1 (en) * 2013-10-16 2017-05-04 Samsung Electronics Co., Ltd. Chip-stacked semiconductor package and method of manufacturing the same

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09260436A (ja) * 1996-03-27 1997-10-03 Mitsubishi Electric Corp 半導体装置
CN100461433C (zh) * 2007-01-04 2009-02-11 北京京东方光电科技有限公司 一种tft阵列结构及其制造方法
CN101471307B (zh) * 2007-12-29 2012-07-04 三星电子株式会社 半导体封装体及其制造方法
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US8803316B2 (en) 2011-12-06 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. TSV structures and methods for forming the same
US8803292B2 (en) 2012-04-27 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate vias and methods for forming the same
US20130341807A1 (en) * 2012-06-25 2013-12-26 Po-Chun Lin Semiconductor package structure
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
US8802504B1 (en) 2013-03-14 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
US9412662B2 (en) * 2014-01-28 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and approach to prevent thin wafer crack
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US10056267B2 (en) * 2014-02-14 2018-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9331021B2 (en) * 2014-04-30 2016-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-wafer package and method of forming same
US9425126B2 (en) 2014-05-29 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structure for chip-on-wafer-on-substrate
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
CN105321933B (zh) * 2014-08-01 2019-08-09 乾坤科技股份有限公司 具有顺形电磁屏蔽结构的半导体封装件及其制造方法
US20160068945A1 (en) * 2014-09-10 2016-03-10 Hitec (Tong Xiang) Glass & Mirror Co., Ltd. Method for beautifying surface of reinforced glass
KR102397907B1 (ko) * 2015-08-12 2022-05-16 삼성전자주식회사 광원 모듈 및 이를 포함하는 조명 장치
CN205789957U (zh) * 2016-06-01 2016-12-07 爱普科斯科技（无锡）有限公司 一种射频滤波模块的封装结构

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130299976A1 (en) * 2012-01-09 2013-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Die Connection System and Method
US20170125387A1 (en) * 2013-10-16 2017-05-04 Samsung Electronics Co., Ltd. Chip-stacked semiconductor package and method of manufacturing the same
US20160204073A1 (en) * 2015-01-09 2016-07-14 Samsung Electronics Co., Ltd. Semiconductor Package and Method of Manufacturing the Same

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