TWI730389B - 在晶粒接合期間用於自對準之晶粒特徵 - Google Patents

在晶粒接合期間用於自對準之晶粒特徵 Download PDF

Info

Publication number
TWI730389B
TWI730389B TW108131230A TW108131230A TWI730389B TW I730389 B TWI730389 B TW I730389B TW 108131230 A TW108131230 A TW 108131230A TW 108131230 A TW108131230 A TW 108131230A TW I730389 B TWI730389 B TW I730389B
Authority
TW
Taiwan
Prior art keywords
semiconductor device
dummy
pad
substrate
electrical
Prior art date
Application number
TW108131230A
Other languages
English (en)
Other versions
TW202021025A (zh
Inventor
伯德 Ｋ 史崔特
衛 周
克里斯多夫 J 甘畢
強納森 S 海克
羅時劍
Original Assignee
美商美光科技公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美商美光科技公司 filed Critical 美商美光科技公司
Publication of TW202021025A publication Critical patent/TW202021025A/zh
Application granted granted Critical
Publication of TWI730389B publication Critical patent/TWI730389B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67288—Monitoring of warpage, curvature, damage, defects or the like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13013—Shape in top view being rectangular or square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13014—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/1319—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1405—Shape
    • H01L2224/14051—Bump connectors having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/14135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1415—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/14151—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry being uniform, i.e. having a uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1415—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/14154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/14156—Covering only the central area of the surface to be connected, i.e. central arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/14177—Combinations of arrays with different layouts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1751—Function
    • H01L2224/17515—Bump connectors having different functions
    • H01L2224/17517—Bump connectors having different functions including bump connectors providing primarily mechanical support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29012—Shape in top view
    • H01L2224/29013—Shape in top view being rectangular or square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/301—Disposition
    • H01L2224/3012—Layout
    • H01L2224/3015—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/30154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/30155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32227—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/759—Means for monitoring the connection process
    • H01L2224/7592—Load or pressure adjusting means, e.g. sensors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81002—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a removable or sacrificial coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81143—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81444—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81455—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83002—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a removable or sacrificial coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83143—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83444—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83455—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/83815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06593—Mounting aids permanently on device; arrangements for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

本發明提供一半導體裝置總成，其包含具有一第一側及一第二側之一基板，該第一側具有至少一個虛設墊及至少一個電墊。該半導體裝置總成包含具有一第一側及一第二側之一第一半導體裝置以及自該第二側延伸之至少一個電柱。該電柱經由焊料連接至該電墊以形成一電互連件。該半導體裝置總成包含自該第一半導體裝置之該第二側延伸之至少一個虛設柱及定位於該虛設柱之一端與該虛設墊之間的一液體。該液體之該表面張力將該虛設柱拉向該虛設墊。該表面張力可減少或最小化該半導體裝置總成之一翹曲及/或使該虛設柱及該虛設墊對準。

Description

在晶粒接合期間用於自對準之晶粒特徵
本文中所描述之實施例係關於使用可為焊料之一液體之表面張力來縮減或最小化一半導體裝置總成之翹曲及/或對準一半導體裝置總成之組件。
半導體處理及封裝技術不斷演進以滿足對增大效能及縮減尺寸之業界需求。電子產品(諸如蜂巢式電話、智慧型電話、平板電腦、個人數位助理、膝上型電腦以及其他電子裝置)需要具有高裝置密度同時具有一相對小佔用面積之封裝式半導體總成。例如，可用於記憶體裝置、處理器及其他裝置之空間在電子產品中不斷減小，從而需要增大半導體裝置之密度。半導體裝置之厚度不斷減小以縮減半導體裝置封裝之尺寸。一種增大半導體裝置之密度之方法係堆疊半導體裝置以形成一半導體裝置總成。
在形成一半導體裝置總成之程序期間，該總成可經歷具有一高溫之各種程序。例如，一回流程序期間在半導體裝置之間產生焊料接點或互連件之溫度可達到一高溫，諸如攝氏260度。一般技術者將明白，高溫可取決於半導體裝置總成之組件以及用來形成該總成之程序而變化。
一半導體裝置總成可包括各種組件，諸如但不限於一基板、半導體裝置及模塑化合物。該等組件之各者可能具有不同熱膨脹係數(CTE)，此可能產生潛在問題。當半導體裝置總成經受一高溫時，半導體裝置總成可能歸因於該總成之個別組件之不同CTE而經歷翹曲。翹曲可能對該總成之組件提供大量應力。若翹曲太大，則翹曲可能在一半導體裝置總成內產生互連件之可靠性問題。例如，大於但不限於50微米之一翹曲可能導致焊料接頭之可靠性問題。
翹曲可能在將一半導體裝置連接至一板、基板或另一半導體裝置時產生問題。翹曲可能使連接兩個半導體裝置變得非常困難。例如，若翹曲增大兩個半導體裝置之間的距離，則翹曲可能致使兩個半導體裝置之間的互連件斷裂。相反，若翹曲減小兩個半導體裝置之間的距離，則翹曲可能致使兩個相鄰互連件之間的一短路。如受益於本發明之一般技術者將明白，距離減小可能致使可為焊料之互連件材料橫向地朝向一相鄰互連件擴展。另外，翹曲可能致使待連接在一起之兩個半導體裝置之組件未對準。
可能存在其他缺陷及缺點。
本發明之一實施例係一種半導體裝置總成，其包括具有一第一側及一第二側之一基板，該第一側具有至少一個虛設墊及至少一個電墊。該半導體裝置總成包括：一第一半導體裝置，其具有一第一側及一第二側；及至少一個電柱，其自該第一半導體裝置之該第二側延伸。該至少一個電柱經由焊料連接至該至少一個電墊以在該第一半導體裝置與該基板之間形成一電互連件。該半導體裝置總成包括：至少一個虛設柱，其自該第一半導體裝置之該第二側延伸；及一第一液體，其經定位於該至少一個虛設柱之一端與該至少一個虛設墊之間。該第一液體之表面張力將該至少一個虛設柱拉向該至少一個虛設墊。
本發明之一實施例係一種半導體裝置，其包括具有一第一側及一第二側之一基板，該第一側具有一面積。該半導體裝置包括該第一側上之複數個電墊，其中該複數個電墊之各者經組態以連接至電柱以形成電連接件。該半導體裝置包括該第一側上之複數個虛設墊，其中該複數個虛設墊之各者經組態以經由待定位於該複數個虛設墊之各者與該複數個虛設柱之一對應柱之間的一流體之表面張力與複數個柱對準。該複數個虛設墊可具有係該基板之該第一側之該面積之至少1/8大之一組合面積。
本發明之一實施例係一種製造一半導體裝置總成之方法。該方法包括提供具有一第一表面及與該第一表面相對之一第二表面之一基板，其中至少一個虛設墊在該第一表面上。該方法包括提供具有一第一表面及與該第一表面相對之一第二表面之一第一半導體裝置，其中至少一個虛設柱自該第二表面延伸。該方法包括將該至少一個虛設柱定位於該至少一個虛設墊附近，其中定位於該至少一個虛設柱與該至少一個虛設墊之間的一流體之一表面張力施加將該至少一個虛設柱及該至少一個虛設墊拉向彼此之力。
在本發明中，論述眾多特定細節以提供對本發明之實施例之一透徹及可行之描述。一般技術者將認知，可在無一或多個特定細節之情況下實踐本發明。可能未展示及/或可能未詳細描述通常與半導體裝置及半導體裝置封裝相關聯之熟知結構及/或操作以避免模糊本發明之其他態樣。通常，應理解，除本文中所揭示之彼等特定實施例以外之各種其他裝置、系統及/或方法可在本發明之範疇內。
術語「半導體裝置總成」可指代一或多個半導體裝置、半導體裝置封裝及/或基板之一總成，其等可包含中介層、支撐件及/或其他合適基板。半導體裝置總成可被製造為但不限於離散封裝形式、條帶或矩陣形式及/或晶圓面板形式。術語「半導體裝置」通常指代包含半導體材料之一固態裝置。一半導體裝置可包含例如一半導體基板、晶圓、面板、或來自一晶圓或基板之單個晶粒。一半導體裝置在本文中可指代一半導體晶粒，但半導體裝置不限於半導體晶粒。
如本文中所使用，術語「垂直」、「橫向」、「上」及「下」可指代圖中所展示之半導體裝置及/或半導體裝置總成中之特徵之相對方向或位置。例如，「上」或「最上」可指代一特徵比另一特徵更靠近一頁面之頂部定位。然而，此等術語應被廣義地解釋為包含具有其他定向之半導體裝置及/或半導體裝置總成，諸如倒置或傾斜定向，其中頂部/底部、上方/下方、上方/下面、上/下及左/右可取決於定向互換。
本發明之各項實施例涉及半導體裝置、半導體裝置總成、半導體封裝、半導體裝置封裝、及製造及/或操作半導體裝置之方法。
圖1係一半導體裝置110之一實施例之一仰視示意圖。半導體裝置110具有一第一或頂部側111 (圖2中最佳地展示)及一第二或底部側112。圖2係半導體裝置110之一側視示意圖。複數個電柱120自半導體裝置110之第二側112延伸。電柱經組態以與一相鄰半導體裝置之一第一或頂部側之一相鄰基板140 (圖3或圖4中所展示)之一第一或頂部側141 (圖4中所展示)上之一對應電墊150配合(如圖3及圖4中所展示)，如本文中所論述。電柱包括自半導體裝置110之第二側112延伸之柱121，其中焊料122經定位於各柱121之端上。電柱120及對應電墊150經組態以在半導體裝置110與相鄰基板140或相鄰半導體裝置之間形成一電互連件。如受益於本發明之一般技術者將明白，相鄰基板可為一半導體裝置。如受益於本發明之一般技術者將明白，電柱120之數目、位置、尺寸及/或組態係出於繪示性目的而展示且可取決於應用而變化。
複數個虛設柱130自半導體裝置110之第二側112延伸。流體135經定位於各虛設柱130之端上。在一實施例中，流體135可為但不限於焊料。虛設柱130經組態以接合定位於相鄰基板140之第一或頂部側141上或相鄰半導體裝置之一第一或頂部側上之一虛設墊160 (圖3及圖4中所展示)。如上文所論述，基板140可為一半導體裝置。流體135之一表面張力可用來使虛設柱130與虛設墊160自對準，如本文中所論述。同樣地，流體135之表面張力可用來將虛設柱130拉向虛設墊160，如本文中所論述。流體135之表面張力之拉力可用來最小化或縮減半導體裝置110之翹曲及/或基板140之翹曲，如本文中所論述。
虛設墊160及虛設柱130可經組態以縮減半導體裝置110及/或基板140之翹曲。虛設墊160及虛設柱130可基於翹曲組態成一圖案。例如，圖案可將虛設柱130及虛設墊160定位於兩個裝置之周邊處。如受益於本發明之一般技術者將明白，可取決於裝置之翹曲使用虛設柱130及虛設墊160之各種組態。
如本文中所使用，術語虛設意謂著柱及/或墊未經組態以在半導體裝置110與相鄰基板或半導體裝置之間形成一電互連件。如受益於本發明之一般技術者將明白，虛設柱130及/或流體135之數目、位置、尺寸及/或組態係出於繪示性目的而展示且可取決於應用而變化。例如，在一些實施例中，在將虛設柱130連接至虛設墊160之前，流體135可經定位於虛設墊160而非定位於虛設柱130之端上。
圖3係一基板140之一實施例之一俯視示意圖。基板裝置140具有一第一或頂部側141及一第二或底部側142 (圖4中最佳地展示)。圖4係基板140之一側視示意圖。基板140之第一側141包含組態有電柱120以在半導體裝置110與基板140之間形成電互連件之複數個電墊150，如上文所論述。一焊料遮罩145可經定位於基板140之第一表面141上且電墊150可經定位於焊料遮罩145之開口內，從而產生一凹部或空腔147。基板140之第一側141亦包含經組態以與自半導體裝置110之第二側112延伸之虛設柱130配合之複數個虛設墊160。
如本文中所論述，虛設柱130及虛設墊160未在半導體裝置110與基板140之間形成電互連件。虛設墊160可經定位於焊料遮罩145之開口內，從而在虛設墊160上方產生一凹部或空腔146。凹部或空腔146可用來保持定位於虛設柱130與虛設墊160之間的流體135。如受益於本發明之一般技術者將明白，焊料遮罩145、電墊150及/或虛設墊160之數目、位置、尺寸及/或組態係出於繪示性目的而展示且可取決於應用而變化。
圖5展示在形成一半導體裝置總成100之程序中半導體裝置110經定位於基板140附近之一側視示意圖(圖6中最佳地展示)。隨著將半導體裝置110及基板140放在一起，定位於各虛設柱130與對應虛設墊160之間的流體135之表面張力將虛設柱130及虛設墊160拉到一起。流體135之拉力可用來使虛設柱130與虛設墊160自對準。
圖6展示包括連接至基板140之半導體裝置110之半導體裝置總成100之一側視示意圖。電柱120及電墊150在半導體裝置110與基板140之間提供電互連件。若半導體裝置110及基板140之表面112、141上方之流體135之面積足夠大，則隨著半導體裝置總成100在形成程序期間經受高溫，流體135之表面張力能夠縮減或最小化半導體裝置110及/或基板140之一翹曲。例如，若虛設墊160之總面積及因此流體135之總面積係半導體裝置110之第二表面112之總面積之至少1/8大，則由流體135之表面張力藉由虛設柱130施加至半導體裝置110之力可足以縮減或最小化半導體裝置110之翹曲。
在一項實施例中，流體135可為焊料且虛設柱130及虛設墊160可包括金屬。如受益於本發明之一般技術者將明白，可使用使表面張力能夠使虛設柱130與虛設墊160可能自對準及/或最小化一半導體裝置總成之一組件之翹曲之其他流體及材料。虛設墊160及虛設柱130可包括但不限於銅、鎳、金或其等組合。流體135可包括但不限於水、甘油、二碘甲烷、甲醯胺、錫焊料、錫銀焊料、銦焊料、環氧樹脂或其等組合。半導體裝置110及/或基板140之(若干)表面112、141及/或虛設柱130及虛設墊160可能需要在形成半導體裝置總成100之前進行處理以充分確保流體135之表面張力賦予一足夠力用於對準目的及/或縮減翹曲。
為了改變透過表面張力產生之自對準力，可在將虛設柱130連接至虛設墊160之前利用各種表面狀況處理。如受益於本發明之一般技術者將明白，可使用各種表面狀況處理來改變一或若干組件之表面化學性質，使得調整表面能量以獲得最佳程序條件，從而增強可用於自對準之表面張力。例如，表面狀況處理可為但不限於對一或多個表面施加液體、施加蒸汽及/或施加電漿以更好地使表面張力能夠將組件(諸如虛設柱130)自對準至虛設墊160及/或縮減翹曲。
圖7A係具有一第一翹曲之一半導體裝置210之一實施例之一示意圖且圖7B係具有一第二翹曲之一半導體裝置210之一實施例之一示意圖。出於繪示性目的而展示第一翹曲及第二翹曲。如受益於本發明之一般技術者將明白，翹曲可為凸形、凹形或一不同形狀。半導體裝置210包含自半導體裝置210之一第二表面212延伸之複數個虛設柱230。第二表面212與半導體裝置210之一第一表面211相對。流體235經定位於虛設柱230中自半導體裝置210之第二表面212延伸之端上。
圖8係一半導體裝置總成200之一實施例之一示意圖，半導體裝置總成200包括連接至一基板240之一第一表面241之半導體裝置210，第一表面241與基板240之一第二表面242相對。流體235經定位一虛設柱230與在基板240之第一表面241上之一對應虛設墊260之間。與圖7A及圖7B相比，流體235之表面張力已縮減或最小化半導體裝置210之翹曲。如圖8中所展示，基板240之第一表面241可不包含由一焊料遮罩中開口產生之凹部。
圖9係一半導體裝置310之一實施例之一示意圖。半導體裝置310可包含半導體裝置310之一第二表面312上之複數個電互連件320。複數個虛設柱330可自半導體裝置310之第二或底部表面312延伸。流體335可經定位於虛設柱330之各者之端上。虛設柱330可為縱向形狀且延伸達近似第二表面312之一長度。與沿第二表面312展開之較大量虛設柱330相比，使用幾個縱向虛設柱330更可使流體335之表面張力能夠更好地縮減或最小化半導體裝置310之翹曲。
圖10係一半導體裝置410之一實施例之一示意圖。半導體裝置410可包含半導體裝置410之一第二表面412上之複數個電互連件420。複數個虛設柱430可自半導體裝置410第二或底部表面412延伸。流體435可經定位於虛設柱430之各者之端上。虛設柱430可沿第二表面412配置成一圖案以更好地使流體435之表面張力能夠縮減或最小化半導體裝置410之翹曲。虛設柱430可為延伸達近似第二表面312之一長度之長縱向形狀柱連同更短更離散柱430之組合，如圖10中所展示。
圖11係一第一半導體裝置510A、一第二半導體裝置510B及一基板540之一側視示意圖。第一半導體裝置510A具有一第一或頂部側511A及一第二或底部側512A。同樣地，第二半導體裝置510B具有一第一或頂部側511B及一第二或底部側512B。包括柱521A及焊料522A之複數個電柱520A自第一半導體裝置510A之第二側512A延伸，且包括柱521B及焊料522B之複數個電柱520B自第二半導體裝置510B之第二側512B延伸。如本文中所論述，電柱520A、520B經組態以在相鄰半導體裝置及/或基板之間形成電互連件。複數個虛設柱530A自第一半導體裝置510A之第二側512A延伸，且複數個虛設柱530B自第二半導體裝置510B之第二側512B延伸，其中對應流體535A、535B經定位於各虛設柱530A、530B之端上。如本文中所論述，流體535A、535B之表面張力可用來在形成一半導體裝置總成時對準組件及/或縮減翹曲。
第一半導體裝置510A之第一或頂部側511A包含複數個電墊550A及虛設墊560A。同樣地，第二半導體裝置510B之第一或頂部側511B包含複數個電墊550B及虛設墊560B。如受益於本發明之一般技術者將明白，電柱520A、520B，虛設柱530A、530B，流體535A、535B，電墊550A、550B及虛設墊560A、560B之數目、位置、尺寸及/或組態係出於繪示性目的而展示且可取決於應用而變化。
基板540具有一第一或頂部側541及一第二或底部側542。基板540之第一側541包含經組態以在基板540與一相鄰半導體裝置基板之間形成電互連件之複數個電墊550，如上文所論述。一焊料遮罩545可經定位於基板540之第一表面541上且電墊550可經定位於焊料遮罩545之開口內，從而產生一凹部或空腔547。基板540之第一側541亦包含經組態以與自第一半導體裝置510A之第二側512A延伸之虛設柱530A配合之複數個虛設墊560。如本文中所論述，虛設柱530A及虛設墊560未在第一半導體裝置510A與基板540之間形成電互連件。虛設墊560可經定位於焊料遮罩545之開口內，從而在虛設墊560上方產生一凹部或空腔546。凹部或空腔546可用來保持定位於虛設柱530A與虛設墊560之間的流體535A。如受益於本發明之一般技術者將明白，焊料遮罩545、電墊550及/或虛設墊560之數目、位置、尺寸及/或組態係出於繪示性目的而展示且可取決於應用而變化。
圖12展示包括連接至基板540之第一半導體裝置510A之半導體裝置總成500之一側視示意圖。第一半導體裝置510A經連接至第二半導體裝置510B且第二半導體裝置510B經連接至第三半導體裝置510C。一般技術者將明白，半導體裝置510A、510B、510C之數目可多於或少於三個，如圖12中所展示。
第三半導體裝置510C具有一第一或頂部側511C及一第二或底部側512C。電柱520A、520B、520C及電墊550、550A、550B在半導體裝置總成500之半導體裝置510A、510B、510C與基板540之間提供電互連件。如本文中所論述，隨著半導體裝置總成在形成程序期間經受高溫，虛設柱530A、530B、530C與虛設墊560、560A、560B之間的流體535A、535B、535C之表面張力可能夠對準各自組件及/或縮減半導體裝置總成500之組件之翹曲。
圖13係製造一半導體裝置總成之一方法600之一實施例之一流程圖。方法600包括在610處提供具有一第一表面及與第一表面相對之一第二表面之一基板，其中至少一個虛設墊在第一表面上。例如，基板140可包含基板140之第一表面141上之複數個虛設墊160。虛設墊160可經定位於第一表面141上之一焊料遮罩145中之一開口內。
方法600包括在620處提供具有一第一表面及與第一表面相對之一第二表面之一第一半導體裝置，其中至少一個虛設柱自第二表面延伸。方法600包括在630處將至少一個虛設柱定位於至少一個虛設墊附近，其中定位於至少一個虛設柱與至少一個虛設墊之間的一流體之一表面張力施加將至少一個虛設柱及至少一個虛設墊拉向彼此之一力。如本文中所論述，流體可最初定位於虛設柱之端上或可經定位於虛設墊上。
方法600可包括在640處利用流體之表面張力使至少一個虛設柱與至少一個虛設墊對準。流體之表面張力可使虛設柱與虛設墊對準，如本文中所論述。方法600可包括在650處利用流體之表面張力縮減第一半導體裝置之一翹曲。流體之表面張力可能夠縮減或最小化半導體裝置在一高溫下之翹曲。
方法600可包括在660處將第一半導體裝置電連接至基板；及在已將第一半導體裝置電連接至基板之後使流體自至少一個虛設柱與至少一個虛設墊之間蒸發。在已將第一半導體裝置電連接至基板之後，定位於虛設柱與虛設墊之間的流體可取決於所使用流體而自半導體裝置總成蒸發。例如，若使用水來在虛設墊與虛設柱之間施加力，則一旦半導體裝置及基板連接在一起，流體隨即可自半導體裝置總成蒸發。如受益於本發明之一般技術者將明白，可使用一旦半導體裝置及基板連接在一起隨即可蒸發之各種流體來在虛設墊與虛設柱之間施加力，例如但不限於甘油、二碘甲烷及甲醯胺。替代地，一旦半導體裝置及基板連接在一起，用來在虛設墊與虛設柱之間施加力之流體隨即可自半導體裝置總成洗掉。例如，一旦半導體裝置及基板連接在一起，隨即可將水或一有機溶劑施加至半導體裝置總成以移除流體。
方法600可包括在670處提供具有一第一表面及與第一表面相對之一第二表面之一第二半導體裝置，其中至少一個虛設柱自第二表面延伸。方法600可包括在680處將自第二半導體裝置之第二表面延伸之至少一個虛設柱定位於第一半導體裝置之第一表面上之至少一個虛設墊附近，其中定位於自第二半導體裝置之第二表面延伸之至少一個虛設柱與第一半導體裝置之第一表面上之至少一個虛設墊之間的一流體之一表面張力施加將至少一個虛設柱及至少一個虛設墊拉向彼此之一力。
圖14展示在形成一半導體裝置總成700之程序中半導體裝置710經定位於基板740附近之一側視示意圖。半導體裝置710包含一第一側711及一第二側712。包括柱721及焊料722之電柱720自半導體裝置710之第二側712延伸。電柱720經組態以接合基板740之第一側741上之電墊750以在半導體裝置710與基板740之間形成電互連件，如本文中所論述。半導體裝置710包含自半導體裝置710之第二表面712延伸之虛設柱730。
基板740包含一第一側741及與該第一側相對之一第二側742。基板740包含定位於第一側711上之一焊料遮罩745中之開口內之電墊750及亦定位於焊料遮罩745中之開口內之虛設墊760。流體735經定位於虛設墊760上。隨著將半導體裝置710及基板740放在一起，定位於各虛設墊760上之流體735之表面張力將虛設柱730及對應虛設墊760拉到一起。流體735之拉力可用來使虛設柱730與對應虛設墊760對準及/或可縮減半導體裝置710及/或基板740之一翹曲。
儘管已關於特定實施例描述本發明，但對於一般技術者顯而易見之其他實施例(包含不提供本文中所論述之所有特徵及優點之實施例)亦在本發明之範疇內。本發明可涵蓋本文中未明確展示或描述之其他實施例。據此，僅藉由參考隨附申請專利範圍及其等效物界定本發明之範疇。
100:半導體裝置總成 110:半導體裝置 111:第一或頂部側 112:第二或底部側 120:電柱 121:柱 122:焊料 130:虛設柱 135:流體 140:基板 141:第一或頂部側 142:第二或底部側 145:焊料遮罩 146:凹部或空腔 147:凹部或空腔 150:電墊 160:虛設墊 200:半導體裝置總成 210:半導體裝置 211:第一表面 212:第二表面 230:虛設柱 235:流體 240:基板 241:第一表面 242:第二表面 260:虛設墊 310:半導體裝置 312:第二表面 320:電互連件 330:虛設柱 335:流體 410:半導體裝置 412:第二表面 420:電互連件 430:虛設柱 435:流體 510A:第一半導體裝置 510B:第二半導體裝置 510C:第三半導體裝置 511A:第一或頂部側 511B:第一或頂部側 511C:第一或頂部側 512A:第二或底部側 512B:第二或底部側 512C:第二或底部側 520A:電柱 520B:電柱 521A:柱 521B:柱 522A:焊料 522B:焊料 530A:虛設柱 530B:虛設柱 535A:流體 535B:流體 540:基板 541:第一或頂部側 542:第二或底部側 545:焊料遮罩 546:凹部或空腔 547:凹部或空腔 550:電墊 550A:電墊 550B:電墊 560:虛設墊 560A:虛設墊 560B:虛設墊 600:方法 610:步驟 620:步驟 630:步驟 640:步驟 650:步驟 660:步驟 670:步驟 680:步驟 700:半導體裝置總成 710:半導體裝置 711:第一側 712:第二側 720:電柱 721:柱 722:焊料 730:虛設柱 735:流體 740:基板 741:第一側 742:第二側 745:焊料遮罩 750:電墊 760:虛設墊
圖1係一半導體裝置之一實施例之一仰視示意圖。
圖2係圖1之半導體裝置之側視示意圖。
圖3係一基板之一實施例之一俯視示意圖。
圖4係圖3之基板之一側視示意圖。
圖5係彼此相鄰定位以形成一半導體裝置總成之一半導體裝置及一基板之一實施例之一示意圖。
圖6係圖5之半導體裝置總成之一示意圖，其中半導體裝置經連接至基板。
圖7A係具有一第一翹曲之一半導體裝置之一實施例之一示意圖。
圖7B係具有一第二翹曲之一半導體裝置之一實施例之一示意圖。
圖8係一半導體裝置總成之一實施例之一示意圖。
圖9係一半導體裝置之一實施例之一示意圖。
圖10係一半導體裝置之一實施例之一示意圖。
圖11係彼此相鄰定位以形成一半導體裝置總成之半導體裝置及一基板之一實施例之一示意圖。
圖12係一半導體裝置總成之一實施例之一示意圖。
圖13係製造一半導體裝置總成之一方法之一實施例之一流程圖。
圖14係彼此相鄰定位以形成一半導體裝置總成之一半導體裝置及一基板之一實施例之一示意圖。
雖然本發明易於進行各種修改及替代形式，但特定實施例已在附圖中以實例方式展示且將在本文中詳細描述。然而，應理解，本發明並非意欲限於所揭示之特定形式。相反，意欲涵蓋落入如由隨附申請專利範圍界定之本發明之範疇內之所有修改、等效物及替代物。
110:半導體裝置
112:第二或底部側
120:電柱
130:虛設柱
135:流體

Claims (20)

  1. 一種半導體裝置總成，其包括：一基板，其具有一第一側及一第二側，該第一側具有至少一個虛設墊(dummy pad)及至少一個電墊，其中該至少一個虛設墊具有一第一面積且該至少一個電墊具有一第二面積，該第一面積係該第二面積之至少兩倍；一第一半導體裝置，其具有一第一側及一第二側；至少一個電柱，其自該第一半導體裝置之該第二側延伸，該至少一個電柱經由焊料連接至該至少一個電墊以在該第一半導體裝置與該基板之間形成一電互連件(electrical interconnect)；至少一個虛設柱，其自該第一半導體裝置之該第二側延伸；一第一液體，其經定位於該至少一個虛設柱之一端與該至少一個虛設墊之間，其中該第一液體之一表面張力將該至少一個虛設柱拉向該至少一個虛設墊。
  2. 如請求項1之半導體裝置總成，其中該第一液體之該表面張力減少該第一半導體裝置之一翹曲。
  3. 如請求項1之半導體裝置總成，其中該第一液體之該表面張力使該至少一個虛設柱與該至少一個虛設墊對準。
  4. 如請求項1之半導體裝置總成，其中該第一液體係焊料且該至少一個 虛設墊係一虛設金屬墊。
  5. 如請求項1之半導體裝置總成，其中該至少一個虛設墊經定位於該基板之該第一側上之一凹部內。
  6. 如請求項5之半導體裝置總成，其中該凹部係該基板之該第一側上之一焊料遮罩層內之一凹部。
  7. 如請求項1之半導體裝置總成，其中該第一半導體裝置之該第一側包含至少一個虛設墊及至少一個電墊。
  8. 如請求項7之半導體裝置總成，其包括：一第二半導體裝置，其具有一第一側及一第二側；至少一個電柱，其自該第二半導體裝置之該第二側延伸，自該第二半導體裝置之該第二側延伸之該至少一個電柱經由焊料連接至該第一半導體之該第一側上之該至少一個電墊，以在該第一半導體裝置與該第二半導體裝置之間形成一電互連件；至少一個虛設柱，其自該第二半導體裝置之該第二側延伸；一液體，其經定位於自該第二半導體裝置之該第二表面延伸之該至少一個虛設柱之一端與該第一半導體裝置之該第一表面上之該至少一個虛設墊之間，其中該液體之一表面張力將自該第二半導體裝置延伸之該至少一個虛設柱拉向該第一半導體裝置上之該至少一個虛設墊。
  9. 如請求項8之半導體裝置總成，其中該第二液體之該表面張力使該第二半導體裝置與該第一半導體裝置對準。
  10. 如請求項9之半導體裝置總成，其中該第二液體之該表面張力減少該第二半導體裝置之一翹曲。
  11. 一種半導體裝置，其包括：一基板，其具有一第一側及一第二側，該第一側具有一面積；複數個電墊，其等在該第一側上，該複數個電墊之各者經組態以連接至一電柱以形成一電互連件；及複數個虛設墊，其等在該第一側上，該複數個虛設墊之各者經組態以經由一流體之表面張力與複數個柱對準以定位於該複數個虛設墊之各者與該複數個柱之一對應(corresponding)柱之間。
  12. 如請求項11之半導體裝置，其中該複數個虛設墊具有係該基板之該第一側之該面積之至少1/8大之一組合面積。
  13. 如請求項11之半導體裝置，其中該流體之該表面張力施加大於該基板在一預定溫度下之一翹曲力之一力。
  14. 如請求項13之半導體裝置，其中該預定溫度係攝氏200攝度或更高。
  15. 一種製造一半導體裝置總成之方法，其包括：提供具有一第一表面及與該第一表面相對之一第二表面之一基板，該基板在該第一表面上具有至少一個虛設柱；提供具有一第一表面及與該第一表面相對之一第二表面之一第一半導體裝置，該第一半導體裝置具有自該第二表面延伸之至少一個虛設柱；將該至少一個虛設柱定位於該至少一個虛設墊附近，其中定位於該至少一個虛設柱與該至少一個虛設墊之間的一流體之一表面張力施加將該至少一個虛設柱及該至少一個虛設墊拉向彼此之一力。
  16. 如請求項15之方法，其進一步包括利用該流體之該表面張力之該力使該至少一個虛設柱與該至少一個虛設墊對準。
  17. 如請求項15之方法，其進一步包括利用該流體之該表面張力之該力減少該第一半導體裝置之一翹曲。
  18. 如請求項15之方法，其進一步包括：將該第一半導體裝置電連接至該基板；及在已將該第一半導體裝置電連接至該基板之後使該流體自該至少一個虛設柱與該至少一個虛設墊之間蒸發。
  19. 如請求項15之方法，其進一步包括：提供具有一第一表面及與該第一表面相對之一第二表面之一第二半導體裝置，其中至少一個虛設柱自該第二表面延伸；及 將自該第二半導體裝置之該第二表面延伸之該至少一個虛設柱定位於該第一半導體裝置之該第一表面上之至少一個虛設墊附近，其中定位於自該第二半導體裝置之該第二表面延伸之該至少一個虛設柱與該第一半導體裝置之該第一表面上之該至少一個虛設墊之間的一流體之一表面張力施加將該至少一個虛設柱及該至少一個虛設墊拉向彼此之一力。
  20. 如請求項15之方法，其中該流體包括焊料且該至少一個虛設墊包括一金屬墊。
TW108131230A 2018-09-11 2019-08-30 在晶粒接合期間用於自對準之晶粒特徵 TWI730389B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/127,769 2018-09-11
US16/127,769 US10748857B2 (en) 2018-09-11 2018-09-11 Die features for self-alignment during die bonding

Publications (2)

Publication Number Publication Date
TW202021025A TW202021025A (zh) 2020-06-01
TWI730389B true TWI730389B (zh) 2021-06-11

Family

ID=69720075

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108131230A TWI730389B (zh) 2018-09-11 2019-08-30 在晶粒接合期間用於自對準之晶粒特徵

Country Status (3)

Country Link
US (2) US10748857B2 (zh)
CN (1) CN110890347B (zh)
TW (1) TWI730389B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11164845B2 (en) * 2020-01-30 2021-11-02 International Business Machines Corporation Resist structure for forming bumps
US20210408354A1 (en) * 2020-06-29 2021-12-30 Nec Corporation Quantum device
US11688706B2 (en) * 2020-09-15 2023-06-27 Micron Technology, Inc. Semiconductor device assembly with embossed solder mask having non-planar features and associated methods and systems

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150380455A1 (en) * 2013-02-28 2015-12-31 Hamamatsu Photonics K.K. Semiconductor photodetection device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4669371B2 (ja) * 2005-10-12 2011-04-13 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置の製造装置
KR20130096990A (ko) * 2012-02-23 2013-09-02 삼성전자주식회사 반도체 장치
US9202714B2 (en) * 2012-04-24 2015-12-01 Micron Technology, Inc. Methods for forming semiconductor device packages
US9093446B2 (en) * 2013-01-21 2015-07-28 International Business Machines Corporation Chip stack with electrically insulating walls
US9355980B2 (en) * 2013-09-03 2016-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional chip stack and method of forming the same
HUE038343T2 (hu) * 2014-08-27 2018-10-29 Heraeus Deutschland Gmbh & Co Kg Eljárás forrasztott kapcsolat kialakítására
US10283480B2 (en) * 2015-08-06 2019-05-07 Qorvo Us, Inc. Substrate structure with selective surface finishes for flip chip assembly
US10276465B2 (en) * 2016-09-29 2019-04-30 Mediatek Inc. Semiconductor package assembly

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150380455A1 (en) * 2013-02-28 2015-12-31 Hamamatsu Photonics K.K. Semiconductor photodetection device

Also Published As

Publication number Publication date
CN110890347A (zh) 2020-03-17
US20200373252A1 (en) 2020-11-26
CN110890347B (zh) 2023-12-01
TW202021025A (zh) 2020-06-01
US10748857B2 (en) 2020-08-18
US11302653B2 (en) 2022-04-12
US20200083178A1 (en) 2020-03-12

Similar Documents

Publication Publication Date Title
TWI730389B (zh) 在晶粒接合期間用於自對準之晶粒特徵
TWI643268B (zh) 堆疊封裝結構的製造方法
US8772927B2 (en) Semiconductor package structures having liquid cooler integrated with first level chip package modules
US9860996B2 (en) Selective area heating for 3D chip stack
KR102011175B1 (ko) 플립칩 적층을 위한 방법
US11432372B2 (en) Warpage control in the packaging of integrated circuits
TWI724744B (zh) 半導體裝置及半導體裝置之製造方法
JP2012212786A (ja) 半導体装置の製造方法
RU2630706C2 (ru) Многоярусные микроэлектронные кристаллы, встроенные в микроэлектронную подложку
US9831191B2 (en) Electronic package, semiconductor substrate of the electronic package, and method for manufacturing the electronic package
TW202040760A (zh) 電子封裝件及其製法與承載結構
US10403578B2 (en) Electronic device package
US9478482B2 (en) Offset integrated circuit packaging interconnects
TWI802149B (zh) 電子封裝件及其散熱結構
US11658129B2 (en) Electrically or temperature activated shape-memory materials for warpage control
JP6792322B2 (ja) 半導体装置及び半導体装置の製造方法
KR102535108B1 (ko) 레이저 접합 방법
TWI430421B (zh) 覆晶接合方法
JP5187341B2 (ja) 半導体装置の製造方法
TWI514490B (zh) 半導體封裝件及其製法
TWI264101B (en) Method of flip-chip packaging including chip thermocompression
TW201517182A (zh) 封裝結構之製法
KR20130042938A (ko) 반도체 칩, 이를 포함하는 반도체 패키지 및 적층형 반도체 패키지 제조방법
US20080093734A1 (en) High Density IC Module
JPH11340619A (ja) フリップチップ実装装置及びその製造方法