TWI729525B - 半導體裝置及其製造方法 - Google Patents
半導體裝置及其製造方法 Download PDFInfo
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- TWI729525B TWI729525B TW108136234A TW108136234A TWI729525B TW I729525 B TWI729525 B TW I729525B TW 108136234 A TW108136234 A TW 108136234A TW 108136234 A TW108136234 A TW 108136234A TW I729525 B TWI729525 B TW I729525B
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Abstract
在一實施例中,一種裝置包含:從基底延伸的第一鰭片;設置在第一鰭片上的閘極堆疊;設置在第一鰭片中的源極/汲極區;設置在源極/汲極區上方的接觸蝕刻停止層(CESL);沿閘極堆疊的一側延伸的閘極間隔物;以及設置在接觸蝕刻停止層和閘極間隔物之間的介電插塞,其中介電插塞、接觸蝕刻停止層、閘極間隔物和源極/汲極區共同界定了將閘極堆疊與源極/汲極區物理性隔開的空隙。
Description
本發明實施例是關於半導體製造技術,特別是有關於半導體裝置及其製造方法。
半導體裝置用於多種電子應用中,舉例來說像是個人電腦、行動電話、數位相機及其他電子設備。通常藉由在半導體基底上方按順序地沉積絕緣或介電層、導電層和半導體層的材料,並使用微影將各種材料層圖案化,以形成電路組件及元件在半導體基底上而製造出半導體裝置。
半導體產業藉由不斷地縮減最小部件的尺寸,而持續改善了各種電子組件(例如電晶體、二極體、電阻器、電容器等)的積體密度,這使得更多組件可以被整合至指定的面積內。然而,隨著最小部件的尺寸縮減,其所衍生出的額外問題需要被解決。
根據本發明實施例中的一些實施例,提供半導體裝置的製造方法。此方法包含:形成從基底延伸的第一鰭片;在第一鰭片上形成閘極堆疊;沿著閘極堆疊的一側沉積第一閘極間隔物,此第一閘極間隔物包含第一介電材料;沿著第一閘極間隔物的一側沉積第二閘極間隔物,此第二閘極間隔物包含第二介電材料,第二介電材料不同於第一介電材料;在鄰近第二閘極間隔物的第一鰭片中形成源極/汲極區;沿著第二閘極間隔物的一側並在源極/汲極區上方沉積接觸蝕刻停止層,此接觸蝕刻停止層包含第三介電材料,第二介電材料不同於第三介電材料;移除第二閘極間隔物的至少一部分,以在第一閘極間隔物和接觸蝕刻停止層之間形成空隙;以及形成源極/汲極接觸件穿過接觸蝕刻停止層以耦合源極/汲極區,空隙將源極/汲極接觸件與閘極堆疊物理性隔開。
根據本發明實施例中的另一些實施例,提供半導體裝置的製造方法。此方法包含:形成從基底延伸的第一鰭片和第二鰭片;在第一鰭片上方形成第一閘極堆疊,並在第二鰭片上方形成第二閘極堆疊;沿著第一閘極堆疊的一側和沿著第二閘極堆疊的一側沉積第一閘極間隔層;在第一閘極間隔層上方沉積第二閘極間隔層,第二閘極間隔層具有靠近第一閘極堆疊的第一部分和靠近第二閘極堆疊的第二部分;在第一鰭片中形成第一源極/汲極區,並在第二鰭片中形成第二源極/汲極區,第一源極/汲極區鄰近第二閘極間隔層的第一部分,第二源極/汲極區鄰近第二閘極間隔層的第二部分;以及移除第二閘極間隔層的一部分以形成第一空隙和第二空隙,第一空隙將第一源極/汲極區與第一閘極間隔層隔開,第二空隙將第二源極/汲極區與第二閘極間隔層隔開,所述移除包含:以第一蝕刻速率蝕刻第一閘極間隔層;以第二蝕刻速率蝕刻第二閘極間隔層的第一部分;以及以第三蝕刻速率蝕刻第二閘極間隔層的第二部分,第二蝕刻速率大於第一蝕刻速率,第三蝕刻速率大於第二蝕刻速率。
根據本發明實施例中的又另一些實施例,提供半導體裝置。此半導體裝置包含:從基底延伸的第一鰭片;設置在第一鰭片上的閘極堆疊;設置在第一鰭片中的源極/汲極區;設置在源極/汲極區上方的接觸蝕刻停止層;沿著閘極堆疊的一側延伸的閘極間隔物;以及設置在接觸蝕刻停止層和閘極間隔物之間的介電插塞,其中介電插塞、接觸蝕刻停止層、閘極間隔物和源極/汲極區共同界定空隙,空隙將閘極堆疊與源極/汲極區物理性隔開。
以下內容提供許多不同實施例或範例,用於實施本發明實施例的不同部件。組件和配置的具體範例描述如下,以簡化本發明實施例。當然,這些僅僅是範例,並非用於限定本發明實施例。舉例來說,敘述中若提及第一部件形成於第二部件上或上方,可能包含形成第一部件和第二部件直接接觸的實施例,也可能包含額外的部件形成於第一部件和第二部件之間,使得第一部件和第二部件不直接接觸的實施例。另外,本發明實施例在不同範例中可重複使用參考數字及/或字母。此重複是為了簡化和清楚之目的,並非代表所討論的不同實施例及/或組態之間有特定的關係。
此外,本文可能使用空間相對用語,例如「在……之下」、「在……下方」、「下方的」、「在……上方」、「上方的」及類似的用詞,這些空間相對用語係為了便於描述如圖所示之一個(些)元件或部件與另一個(些)元件或部件之間的關係。這些空間相對用語包含使用中或操作中的裝置之不同方位,以及圖式中所描述的方位。當裝置被轉向不同方位時(旋轉90度或其他方位),在此所使用的空間相對形容詞也將依轉向後的方位來解釋。
根據一些實施例,形成用於鰭式場效電晶體的多個閘極間隔物,並移除這些閘極間隔物之一以在所得到的鰭式場效電晶體中界定空隙。空隙佔據了先前由被移除的閘極間隔物佔據的區域的至少一部分,並保留在最終的鰭式場效電晶體裝置中。空隙可以用空氣填充或可以處於真空,使得鰭式場效電晶體的閘極電極和源極/汲極區之間的區域具有較高的相對介電常數。因此可以降低鰭式場效電晶體的閘極電極與源極/汲極接觸件之間的電容,藉此降低鰭式場效電晶體中的電流洩漏。
第1圖以三維示意圖繪示根據一些實施例之簡化鰭式場效電晶體(FinFET)的範例。為了清楚起見,省略了鰭式場效電晶體的一些其他部件(如下所述)。繪示的鰭式場效電晶體可以使用以例如一個電晶體或多個電晶體(例如兩個電晶體)操作的方式電性連接或耦合。
鰭式場效電晶體包含從基底50延伸的鰭片52。在基底50上方設置隔離區56,且鰭片52從相鄰的隔離區56之間突出並突出於隔離區56之上。雖然將隔離區56描述/繪示為與基底50隔開,但是如在此所用,用語「基底」可以僅指半導體基底或包含隔離區的半導體基底。另外,雖然鰭片52被繪示為基底50之單一、連續材料,但鰭片52及/或基底50可以包含單一材料或多種材料。在本文中,鰭片52是指在相鄰的隔離區56之間延伸的部分。
閘極介電質106沿著鰭片52的側壁並位於鰭片52的頂表面上方,且閘極電極108位於閘極介電質106上方。源極/汲極區92相對於閘極介電質106和閘極電極108設置在鰭片52的兩側。閘極間隔物86將源極/汲極區92與閘極介電質106和閘極電極108隔開。在形成多個電晶體的實施例中,可以在不同電晶體之間共用源極/汲極區92。在一個電晶體由多個鰭片52形成的實施例中,可以電性連接相鄰的源極/汲極區92,例如經由磊晶成長將源極/汲極區92聚結(coalescing),或者經由以同一源極/汲極接觸件耦合源極/汲極區92。
第1圖進一步繪示幾個參考剖面。剖面A-A沿著相鄰的源極/汲極區92下方的隔離區56的一部分。剖面B-B平行於剖面A-A且沿著鰭片52的縱軸。剖面C-C平行於剖面A-A且沿著聚結的源極/汲極區92之間的隔離區56的一部分。剖面D-D垂直於剖面A-A且沿著閘極電極108的縱軸。剖面E-E垂直於剖面A-A且橫跨相鄰的源極/汲極區92。為了清楚起見,後續圖式參照這些參考剖面。
在此討論的一些實施例是在使用閘極後製(gate-last)製程形成的鰭式場效電晶體的背景下討論的。在其他實施例中,可以使用閘極先製(gate-first)製程。此外,一些實施例考慮了在例如平面場效電晶體的平面裝置中使用的面向。
第2、3、4、5和6圖是根據一些實施例之在鰭式場效電晶體的製造過程的中間階段的三維示意圖。
在第2圖中,提供基底50。基底50可以是半導體基底,例如塊體(bulk)半導體、絕緣體上覆半導體(semiconductor-on-insulator,SOI)基底或類似的基底,可以將基底50摻雜(例如以p型或n型摻質)或不摻雜。基底50可以是晶圓,例如矽晶圓。通常而言,絕緣體上覆半導體基底是在絕緣層上形成的半導體材料層。絕緣層可以是例如埋層氧化物(buried oxide,BOX)層、氧化矽層或類似的膜層。在通常是矽基底或玻璃基底的基底上提供絕緣層。也可以使用其他基底,例如多層基底或漸變基底。在一些實施例中,基底50的半導體材料可以包含矽;鍺;化合物半導體,包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦;合金半導體,包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP;或前述之組合。
基底50具有區域50N和區域50P。區域50N可用於形成n型裝置,例如N型金屬氧化物半導體(NMOS)電晶體,像是n型鰭式場效電晶體。區域50P可用於形成p型裝置,例如P型金屬氧化物半導體(PMOS)電晶體,像是p型鰭式場效電晶體。區域50N可以與區域50P物理性隔開,並且可以在區域50N與區域50P之間設置任何數量的裝置部件(例如其他主動裝置、摻雜區、隔離結構等)。
在第3圖中,在基底50中形成鰭片52。鰭片52是半導體條。在一些實施例中,可以藉由在基底50中蝕刻出溝槽來在基底50中形成鰭片52。蝕刻可以是任何合適的蝕刻製程,例如反應性離子蝕刻(reactive ion etch,RIE)、中性束蝕刻(neutral beam etch,NBE)、類似的蝕刻製程或前述之組合。蝕刻可以是非等向性的(anisotropic)。
可以藉由任何合適的方法將鰭片圖案化。舉例來說,鰭片的圖案化可以使用一或多種光學微影(photolithography)製程,包含雙重圖案化或多重圖案化製程。通常而言,雙重圖案化或多重圖案化製程結合光學微影和自對準製程,藉此允許產生的圖案的例如節距(pitches)小於使用單一、直接光學微影製程可獲得的圖案的節距。舉例來說,在一實施例中,在基底上方形成犧牲層,並使用光學微影製程將犧牲層圖案化。使用自對準製程在圖案化的犧牲層旁邊形成間隔物。然後移除犧牲層,接著可以使用剩餘的間隔物將鰭片圖案化。
在第4圖中,在基底50上方和相鄰鰭片52之間形成淺溝槽隔離(Shallow Trench Isolation,STI)區(又稱為隔離區)56。作為形成淺溝槽隔離區56的範例,在中間結構上方形成絕緣材料。絕緣材料可以是氧化物,例如氧化矽、氮化物、類似的材料或前述之組合,並且絕緣材料的形成可以藉由高密度電漿化學氣相沉積(high density plasma chemical vapor deposition,HDP-CVD)、可流動式化學氣相沉積(flowable chemical vapor deposition,FCVD)(例如在遠距電漿系統中的以化學氣相沉積(chemical vapor deposition,CVD)為主的材料沉積,以及後固化以使其轉化為另一種材料,例如氧化物)、類似的方法或前述之組合。可以使用藉由任何合適的方法形成的其他絕緣材料。在繪示的實施例中,絕緣材料是由可流動式化學氣相沉積製程所形成的氧化矽。一旦形成絕緣材料,就可以進行退火製程。在一實施例中,形成絕緣材料,使得多餘的絕緣材料覆蓋鰭片52。一些實施例可以利用多層結構。舉例來說,在一些實施例中,可以先沿著基底50和鰭片52的表面形成襯層(liner)(未繪示)。此後,可以在襯層上方形成填充材料,例如上述那些材料。對絕緣材料施加移除製程以移除鰭片52上方的多餘絕緣材料。在一些實施例中,可以利用平坦化製程,例如化學機械研磨(chemical mechanical polish ,CMP)、回蝕刻(etch back)製程、前述之組合或類似的製程。平坦化製程暴露出鰭片52,使得在完成平坦化製程之後,絕緣材料和鰭片52的頂表面是齊平的。然後凹蝕絕緣材料以形成淺溝槽隔離區56。凹蝕絕緣材料,使得區域50N和區域50P中的鰭片52的上部從相鄰的淺溝槽隔離區56之間突出。此外,淺溝槽隔離區56的頂表面可以具有如圖所示之平坦表面、凸表面、凹表面(例如碟狀(dishing))或前述之組合。可以藉由適當的蝕刻將淺溝槽隔離區56的頂表面形成為平坦的、凸的及/或凹的。淺溝槽隔離區56的凹蝕可以使用合適的蝕刻製程,例如對絕緣材料的材料具有選擇性的蝕刻製程(例如以比鰭片52的材料更快的速率蝕刻絕緣材料的材料)。舉例來說,以適當的蝕刻製程移除化學氧化物,蝕刻製程例如可以使用稀釋的氫氟酸(dilute hydrofluoric,dHF)。
以上描述的製程僅是可以如何形成鰭片52的一個範例。在一些實施例中,可以藉由磊晶成長製程形成鰭片。舉例來說,可以在基底50的頂表面上方形成介電層,並且可以蝕刻出穿過介電層的溝槽以暴露出下方的基底50。可以在溝槽中磊晶成長同質磊晶(Homoepitaxial)結構,並且可以凹蝕介電層,使得同質磊晶結構從介電層突出以形成鰭片。另外,在一些實施例中,異質磊晶(heteroepitaxial)結構可用於鰭片52。舉例來說,在淺溝槽隔離區56的絕緣材料與鰭片52平坦化之後,可以凹蝕鰭片52,並且可以在凹蝕的鰭片52上方磊晶成長與鰭片52不同的材料。在這樣的實施例中,鰭片52包含凹蝕的材料以及設置在凹蝕的材料上方的磊晶成長材料。在另一實施例中,可以在基底50的頂表面上方形成介電層,並且可以蝕刻出穿過介電層的溝槽。然後,可以使用不同於基底50的材料在溝槽中磊晶成長異質磊晶結構,並且可以凹蝕介電層,使得異質磊晶結構從介電層突出以形成鰭片52。在一些磊晶成長同質磊晶或異質磊晶結構的實施例中,可以在成長期間原位(in situ)摻雜磊晶成長的材料,其可以免除先前和後續的佈植,雖然可以一起使用原位和佈植摻雜。
更進一步,在區域50N(例如NMOS區域)中磊晶成長的材料不同於區域50P(例如PMOS區域)中的材料可以是有利的。在不同實施例中,鰭片52的上部可以由矽鍺(Six
Ge1-x
,其中x可以在0至1的範圍)、碳化矽、純或大致上純的鍺、III-V族化合物半導體、II-VI化合物半導體或類似的材料所形成。舉例來說,用於形成III-V族化合物半導體的可用材料包含但不限於InAs、AlAs、GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlP、GaP和類似的材料。
此外,可以在鰭片52及/或基底50中形成適當的井(未繪示)。在一些實施例中,可以在區域50N中形成P井,且可以在區域50P中形成N井。在一些實施例中,在區域50N和區域50P兩者中形成P井或N井。
在具有不同井類型的實施例中,可以使用光阻或其他遮罩(未繪示)來實現用於區域50N和區域50P的不同佈植步驟。舉例來說,可以在區域50N中的淺溝槽隔離區56和鰭片52上方形成光阻。將光阻圖案化以暴露出基底50的區域50P,例如PMOS區。可以藉由使用旋塗(spin-on)技術來形成光阻,並且可以使用合適的光學微影技術將光阻圖案化。一旦圖案化光阻,就在區域50P中進行n型雜質佈植,且光阻可以作為遮罩以大致上防止n型雜質被佈植到例如NMOS區的區域50N中。n型雜質可以是磷、砷或類似的雜質,佈植到區域中的濃度等於或小於1018
cm−3
,例如約1017
cm−3
至約1018
cm−3
。在佈植之後,例如藉由合適的灰化(ashing)製程來移除光阻。
在佈植區域50P之後,在區域50P中的淺溝槽隔離區56和鰭片52上方形成光阻。將光阻圖案化以暴露出基底50的區域50N,例如NMOS區。光阻的形成可以藉由使用旋塗技術,並且可以使用合適的光學微影技術將光阻圖案化。一旦圖案化光阻,就可以在區域50N中進行p型雜質佈植,且光阻可以作為遮罩以大致上防止p型雜質被佈植到例如PMOS區的區域50P中。p型雜質可以是硼、BF2
或類似的雜質,佈植到區域中的濃度等於或小於1018
cm−3
,例如約1017
cm−3
至約1018
cm−3
。在佈植之後,例如可以藉由合適的灰化製程來移除光阻。
在佈植區域50N和區域50P之後,可以進行退火以活化佈植的p型及/或n型雜質。在一些實施例中,可以在成長期間原位摻雜磊晶鰭片的成長材料,其可以免除佈植,雖然可以一起使用原位和佈植摻雜。
在第5圖中,在鰭片52上形成虛設介電層60。虛設介電層60可以是例如氧化矽、氮化矽、前述之組合或類似的材料,並且可以根據合適的技術沉積或熱成長。在虛設介電層60上方形成虛設閘極層62,並在虛設閘極層62上方形成遮罩層64。可以在虛設介電層60上方沉積虛設閘極層62,然後例如藉由化學機械研磨將虛設閘極層62平坦化。可以在虛設閘極層62上方沉積遮罩層64。虛設閘極層62可以是導電材料,並且可以選自包含非晶矽、多晶矽(polysilicon)、多晶矽鍺(poly-SiGe)、金屬氮化物、金屬矽化物、金屬氧化物和金屬的群組。虛設閘極層62的沉積可以藉由物理氣相沉積(physical vapor deposition,PVD)、化學氣相沉積、濺鍍(sputter)沉積或本領域已知且用於沉積導電材料的其他技術。虛設閘極層62可以由對隔離區的蝕刻具有高蝕刻選擇性的其他材料形成。遮罩層64可以包含例如SiN、SiON或類似的材料。在此範例中,橫跨區域50N和區域50P形成單個虛設閘極層62和單個遮罩層64。應注意的是,繪示的虛設介電層60僅覆蓋鰭片52僅用於說明的目的。在一些實施例中,可以沉積虛設介電層60,使得虛設介電層60覆蓋淺溝槽隔離區56、在虛設閘極層62和淺溝槽隔離區56之間延伸。
在第6圖中,使用合適的光學微影和蝕刻技術來將遮罩層64圖案化以形成遮罩74。然後,藉由合適的蝕刻技術將遮罩74的圖案轉移至虛設閘極層62以形成虛設閘極72。遮罩74的圖案可以進一步轉移至虛設介電層60以形成虛設閘極介電質70。虛設閘極72覆蓋鰭片52的各個通道區。遮罩74的圖案可用於將每個虛設閘極72與相鄰的虛設閘極物理性隔開。虛設閘極72的長度方向也可以大致上垂直於相應的磊晶鰭片52的長度方向。
第7A至17E圖是根據一些實施例之鰭式場效電晶體的製造過程的進一步中間階段的剖面示意圖。第7A至17E圖繪示區域50N和區域50P的任何一個內的部件。舉例來說,繪示的結構可適用於區域50N和區域50P兩者。在每個圖式伴隨的內文中描述區域50N和區域50P之結構上的差異(如果有的話)。第7A、8A、9A、10A、11A、12A、13A、14A、15A、16A和17A圖係沿著第1圖所示之參考剖面A-A繪示。第7B、8B、9B、10B、11B、12B、13B、14B、15B、15B、16B和17B圖係沿著第1圖所示之參考剖面B-B繪示。第7C、8C、9C、10C、11C、12C、13C、14C、15C、16C和17C圖係沿著第1圖所示之參考剖面C-C繪示。第7D、8D、9D、10D、11D、12D、13D、14D、15D、16D和17D圖係沿著第1圖所示之參考剖面D-D繪示。第7E、8E、9E、10E、11E、12E、13E、14E、15E、16E和17E圖係沿著沿第1圖所示之參考剖面E-E繪示。
在第7A至7E圖中,在遮罩74、虛設閘極72、虛設閘極介電質70、淺溝槽隔離區56及/或鰭片52的露出表面上形成第一閘極間隔層80。第一閘極間隔層80係由介電材料形成,例如氮化矽、氮碳化矽、氮碳氧化矽、碳氧化矽、矽、金屬氧化物、類似的材料或前述之組合,並且可以藉由順應性(conformal)沉積製程形成第一閘極間隔層80,例如化學氣相沉積、電漿輔助化學氣相沉積或類似的製程。
在形成第一閘極間隔層80之後,進行用於輕摻雜的源極/汲極(lightly doped source/drain,LDD)區82的佈植。在具有不同裝置類型的實施例中,可以在區域50N上方形成例如光阻的遮罩,同時暴露出區域50P,並且可以將適當類型(例如p型)的雜質佈植到區域50P中的露出鰭片52中。然後可以移除遮罩。隨後,可以在區域50P上方形成例如光阻的遮罩,同時暴露出區域50N,並且可以將適當類型的雜質(例如n型)佈植到區域50N中的暴露鰭片52中。然後可以移除遮罩。n型雜質可以是先前討論的任何n型雜質,且p型雜質可以是先前討論的任何p型雜質。輕摻雜的源極/汲極區可以具有約1015
cm−3
至約1016
cm−3
的雜質濃度。可以使用退火來活化佈植的雜質。
在形成輕摻雜的源極/汲極區82之後,在第一閘極間隔層80上形成第二閘極間隔層84。第二閘極間隔層84係由介電材料形成,例如氧化矽、氧氮化矽、氮碳氧化矽、氮化矽、氮化矽等或前述之組合,並且可以藉由順應性沉積製程形成第二閘極間隔層84,例如化學氣相沉積、電漿輔助化學氣相沉積或類似的製程。第二閘極間隔層84是被摻雜的,並且可以用n型雜質(例如磷)或p型雜質(例如硼)進行摻雜。應注意的是,第二閘極間隔層84是不同於第一閘極間隔層80的介電材料。第二閘極間隔層84和第一閘極間隔層80對於相同的蝕刻製程具有高蝕刻選擇性,舉例來說,在蝕刻製程期間,第二閘極間隔層84的蝕刻速率大於第一閘極間隔層80的蝕刻速率。如以下進一步討論的,在後續處理中摻雜第二閘極間隔層84,其進一步增加第二閘極間隔層84和第一閘極間隔層80之間的蝕刻選擇性。
在形成第二閘極間隔層84之後,在第二閘極間隔層84上形成第三閘極間隔層90。第三閘極間隔層90係由選自於第二閘極間隔層84的候選介電材料的介電材料形成,且第三閘極間隔層90的形成方法可以選自於形成第二閘極間隔層84的候選方法,或者可以藉由不同的方法形成。在一些實施例中,第三閘極間隔層90係由不同於第二閘極間隔層84的材料形成。
具體而言,第三閘極間隔層90由與第二閘極間隔層84相同的介電材料形成,使得第三閘極間隔層90還具有對第一閘極間隔層80的高蝕刻選擇性。如以下進一步討論的,第三閘極間隔層90也在隨後的處理中被摻雜,其進一步增加第三閘極間隔層90和第一閘極間隔層80之間的蝕刻選擇性。
在第8A至8E圖中,在鰭片52中形成磊晶源極/汲極區(又稱為源極/汲極區)92,以在各個通道區58中施加應力,藉此提高效能。磊晶源極/汲極區92形成於鰭片52中,使得每個虛設閘極72設置於磊晶源極/汲極區92的各個相鄰對之間。在一些實施例中,磊晶源極/汲極區92可以延伸至並且可以穿過鰭片52。第一閘極間隔層80、第二閘極間隔層84和第三閘極間隔層90用於將磊晶源極/汲極區92與虛設閘極72隔開適當的橫向距離,使得磊晶源極/汲極區92不會使隨後形成的鰭式場效電晶體的閘極短路。
區域50N(例如NMOS區域)中的磊晶源極/汲極區92的形成可以藉由遮蔽區域50P(例如PMOS區域),並蝕刻區域50N中的鰭片52的源極/汲極區以在鰭片52中形成凹槽。然後,可以在凹槽中磊晶成長區域50N中的磊晶源極/汲極區92。磊晶源極/汲極區92可以包含任何合適的材料,例如適合於n型鰭式場效電晶體。舉例來說,如果鰭片52是矽,則區域50N中的磊晶源極/汲極區92可以包含在通道區58中施加拉伸應變(tensile strain)的材料,例如矽、SiC、SiCP、SiP或類似的材料。區域50N中的磊晶源極/汲極區92可以具有從鰭片52的各個表面升高的表面,且可以具有刻面(facets)。
區域50P(例如PMOS區域)中的磊晶源極/汲極區92的形成可以藉由遮蔽區域50N(例如NMOS區域),並蝕刻區域50P中的鰭片52的源極/汲極區以在鰭片52中形成凹槽。然後,可以在凹槽中磊晶成長區域50P中的磊晶源極/汲極區92。磊晶源極/汲極區92可以包含任何合適的材料,例如適合於p型鰭式場效電晶體。舉例來說,如果鰭片52是矽,則區域50P中的磊晶源極/汲極區92可以包含在通道區58中施加壓縮應變的材料,例如SiGe、SiGeB、Ge、GeSn或類似的材料。區域50P中的磊晶源極/汲極區92可以具有從鰭片52的各個表面升高的表面,並且可以具有刻面。
在一些實施例中,在用於形成磊晶源極/汲極區92的製程期間形成第三閘極間隔層90,並且可以在每個區域中形成第三閘極間隔層90。舉例來說,第三閘極間隔層90可以在區域50N中形成有磊晶源極/汲極區92,同時遮蔽區域50P,並且第三閘極間隔層90可以在區域50P中形成有磊晶源極/汲極區92,同時遮蔽區域50N。第三閘極間隔層90在凹蝕鰭片52的源極/汲極區期間作為額外的蝕刻遮罩,在蝕刻鰭片52的源極/汲極區期間保護第二閘極間隔層84的垂直部分。因此,源極/汲極凹槽可以形成為更大的深度和更窄的寬度。
在凹蝕鰭片52的源極/汲極區期間,蝕刻第一閘極間隔層80、第二閘極間隔層84和第三閘極間隔層90。在第一閘極間隔層80、第二閘極間隔層84和第三閘極間隔層90中形成開口,暴露出鰭片52的源極/汲極區,且開口延伸到鰭片52中以形成用於磊晶源極/汲極區92的凹槽。蝕刻可以是例如非等向性蝕刻,像是乾式蝕刻。可以(或者可以不)用不同的製程蝕刻第一閘極間隔層80、第二閘極間隔層84和第三閘極間隔層90。
可以用摻質佈植磊晶源極/汲極區92及/或鰭片52以形成源極/汲極區,類似於前述用於形成輕摻雜的源極/汲極區的製程,然後進行退火。源極/汲極區的雜質濃度可以為約1019
cm−3
至約1021
cm−3
。用於源極/汲極區的n型及/或p型雜質可以是前述之任何雜質。在一些實施例中,可以在成長期間原位摻雜磊晶源極/汲極區92。
由於用於在區域50N和區域50P中形成磊晶源極/汲極區92的磊晶製程,磊晶源極/汲極區的上表面具有刻面,刻面橫向向外擴展超過鰭片52的側壁。在一些實施例中,這些刻面使得同一鰭式場效電晶體的相鄰磊晶源極/汲極區92合併,如圖所示。在相鄰鰭片52之間、在合併的磊晶源極/汲極區92下方形成空隙94。可以合併兩個或更多個相鄰區域。在其他實施例中(以下進一步討論),在完成磊晶製程之後,相鄰的磊晶源極/汲極區92保持分開。
在摻雜磊晶源極/汲極區92期間,也可能摻雜第一閘極間隔層80、第二閘極間隔層84和第三閘極間隔層90。舉例來說,當藉由佈植進行摻雜時,一些雜質可能被佈植到各個間隔物中。同樣地,當在成長期間原位進行摻雜時,各個間隔物可能暴露於磊晶製程的摻質前驅物。因為第三閘極間隔層90覆蓋第二閘極間隔層84,所以第二閘極間隔層84可以具有比第三閘極間隔層90低的摻質濃度。類似地,因為第二閘極間隔層84覆蓋第一閘極間隔層80,第一閘極間隔層80可以具有比第二閘極間隔層84低的摻質濃度。此外,第一閘極間隔層80、第二閘極間隔層84和第三閘極間隔層90的一些區域(例如上部區域)可以被摻雜到比間隔層的其他區域(例如下部區域)高的雜質濃度。由於前述的遮蔽步驟,區域50N中的第一閘極間隔層80、第二閘極間隔層84和第三閘極間隔層90被摻雜成與區域50N中的磊晶源極/汲極區92具有相同的雜質。同樣地,區域50P中的第一閘極間隔層80、第二閘極間隔層84和第三閘極間隔層90被摻雜成與區域50P中的磊晶源極/汲極區92具有相同的雜質。如此一來,每個磊晶源極/汲極區92的導電類型(例如多數載子類型)與第一閘極間隔層80、第二閘極間隔層84和第三閘極間隔層90之鄰近磊晶源極/汲極區92的部分相同。
在形成磊晶源極/汲極區92之後,第一閘極間隔層80和第二閘極間隔層84的剩餘部分分別形成第一閘極間隔物(又稱為閘極間隔物)86和第二閘極間隔物88。此外,第三閘極間隔層90被部分地移除。可以藉由適當的蝕刻製程來移除,例如使用熱H3
PO4
酸的濕式蝕刻。在一些實施例中,在移除之後保留第三閘極間隔層90的剩餘部分,此剩餘部分設置於第二閘極間隔物88與磊晶源極/汲極區92的突起表面之間,且位於磊晶源極/汲極區92的空隙94中。第三閘極間隔層90的剩餘部分稱為剩餘間隔物96。
在第9A至9E圖中,沿著第二閘極間隔物88並在磊晶源極/汲極區92和剩餘間隔物96上方形成接觸蝕刻停止層(contact etch stop layer,CESL)98。接觸蝕刻停止層98可以由選自於第一閘極間隔層80的候選介電材料的介電材料形成,或者可以包含不同的介電材料。接觸蝕刻停止層98的形成方法可以選自於形成第一閘極間隔層80的候選方法,或者可以藉由不同的方法形成。應注意的是,接觸蝕刻停止層98是不同於第二閘極間隔層84的介電材料。第二閘極間隔層84和接觸蝕刻停止層98相對於相同的蝕刻製程具有高蝕刻選擇性,舉例來說,在蝕刻製程期間,第二閘極間隔層84的蝕刻速率大於接觸蝕刻停止層98的蝕刻速率。在一些實施例中,接觸蝕刻停止層98和第一閘極間隔層80係由相同的介電材料形成。
此外,在接觸蝕刻停止層98上方沉積第一層間介電質(first inter-layer dielectric,ILD)100。第一層間介電質100可以由介電材料形成,並且第一層間介電質100的沉積可以藉由任何適當的方法,例如化學氣相沉積、電漿輔助化學氣相沉積(plasma-enhanced CVD,PECVD)或可流動式化學氣相。介電材料可以包含磷矽酸鹽玻璃(Phospho-Silicate Glass,PSG)、硼矽酸鹽玻璃(Boro-Silicate Glass,BSG)、摻雜硼的磷矽酸鹽玻璃(Boron-Doped Phospho-Silicate Glass,BPSG)、未摻雜的矽酸鹽玻璃(undoped Silicate Glass,USG)或類似的材料。可以使用藉由任何合適的方法形成的其他絕緣材料。
在第10A至10E圖中,可以進行例如化學機械研磨的平坦化製程以使得第一層間介電質100的頂表面與虛設閘極72或遮罩74的頂表面齊平。平坦化製程移除遮罩74上方的接觸蝕刻停止層98的一部分,並且還可以移除虛設閘極72上的遮罩74。在平坦化製程之後,虛設閘極72、第一閘極間隔物86、第二閘極間隔物88、接觸蝕刻停止層98和第一層間介電質100的頂表面齊平。因此,虛設閘極72的頂表面經由第一層間介電質100暴露出來。在一些實施例中,可以保留遮罩74,在這種情況下,平坦化製程使得第一層間介電質100的頂表面與遮罩74的頂表面齊平。
在第11A至11E圖中,在一或多個蝕刻步驟中移除虛設閘極72和遮罩74(如果存在),藉此形成凹槽104。也可以移除凹槽104中的虛設閘極介電質70。在一些實施例中,僅移除虛設閘極72,保留虛設閘極介電質70並且被凹槽104暴露出來。在一些實施例中,從晶粒(die)的第一區域(例如核心邏輯區)中的凹槽104移除虛設閘極介電質70並保留在晶粒的第二區域(例如輸入/輸出區)中的凹槽104中。在一些實施例中,藉由非等向性乾式蝕刻製程移除虛設閘極72。舉例來說,蝕刻製程可以包含使用反應氣體的乾式蝕刻製程,反應氣體選擇性地蝕刻虛設閘極72而不蝕刻第一閘極間隔物86、第二閘極間隔物88、接觸蝕刻停止層98或第一層間介電質100。每個凹槽104暴露出各個鰭片52的通道區58。每個通道區58設置於磊晶源極/汲極區92的相鄰對之間。在移除期間,當形成虛設閘極72時,虛設閘極介電質70可以作為蝕刻停止層。然後,在移除虛設閘極72之後,可以可選地移除虛設閘極介電質70。
在第12A至12E圖中,形成閘極介電質106和閘極電極108以替換閘極。第12F圖繪示第12B圖的區域10的詳細示意圖。閘極介電質106順應性地沉積於凹槽104中,例如在鰭片52的頂表面和側壁上以及在第一閘極間隔物86的側壁上。閘極介電質106也可以形成於第一層間介電質100的頂表面上。根據一些實施例,閘極介電質106包含氧化矽、氮化矽或前述之多層結構。在一些實施例中,閘極介電質106包含高介電常數介電材料,並且在這些實施例中,閘極介電質106可以具有大於約7.0的介電常數值,並且可以包含金屬氧化物或Hf、Al、Zr、La、Mg、Ba、Ti、Pb及前述之組合的矽酸鹽。閘極介電質106的形成方法可以包含分子束沉積(Molecular-Beam Deposition,MBD)、原子層沉積、電漿輔助化學氣相沉積和類似的方法。在虛設閘極介電質(又稱為虛設介電質)70留在凹槽104內的實施例中,閘極介電質106包含虛設閘極介電質70的材料(例如SiO2
)。
閘極電極108分別沉積於閘極介電質106上方,並填充凹槽104的剩餘部分。閘極電極108可以是含金屬的材料,例如TiN、TiO、TaN、TaC、Co、Ru、Al、W、前述之組合或前述之多層結構。舉例來說,雖然在第12A至12D圖中繪示單層閘極電極108,但閘極電極108可以包含任何數量的襯層108A、任何數量的功函數調整層108B和填充材料108C,如第12F圖所示。在填充閘極電極108之後,可以進行例如化學機械研磨的平坦化製程,以移除閘極電極108的材料和閘極介電質106的多餘部分,多餘部分位於第一層間介電質100的頂表面上方。閘極電極108和閘極介電質106的材料的剩餘部分因此形成所得到的鰭式場效電晶體的替換閘極。可以將閘極電極108和閘極介電質106統稱為「閘極堆疊」。閘極和閘極堆疊可以沿著鰭片52的通道區58的側壁延伸。
區域50N和區域50P中的閘極介電質106的形成可以同時發生,使得每個區域中的閘極介電質106係由相同的材料形成,並且閘極電極108的形成可以同時發生,使得每個區域中的閘極電極108係由相同的材料形成。在一些實施例中,每個區域中的閘極介電質106可以由不同的製程形成,使得閘極介電質106可以是不同的材料,及/或每個區域中的閘極電極108可以由不同的製程形成,使得閘極電極108可以是不同的材料。當使用不同的製程時,可以使用各種遮罩步驟來遮蔽和露出適當的區域。
在第13A至13E圖中,在第一層間介電質100上方形成保護蓋110。保護蓋110將在後續蝕刻製程中保護第一層間介電質100,防止移除第一層間介電質100。保護蓋110可以由包含金屬的材料形成,例如氮化鈦、鈦、氮化鉭、鉭或類似的材料。保護蓋110也可以由非金屬材料形成,例如氮化矽、碳化矽或類似的材料。作為形成保護蓋110的範例,可以使用例如回蝕刻製程來凹蝕第一層間介電質100。然後,可以藉由沉積製程將保護蓋110沉積於凹槽中,例如物理氣相沉積、射頻物理氣相沉積(Radio Frequency PVD,RFPVD)、原子層沉積(Atomic Layer Deposition,ALD)或類似的製程。在沉積保護蓋110之後,可以進行例如化學機械研磨的平坦化製程以移除保護蓋110的多餘部分,多餘部分位於閘極堆疊和閘極間隔物的頂表面上方。
在第14A至14E圖中,移除一些或全部的剩餘間隔物96和第二閘極間隔物88,以使空隙94沿著閘極堆疊延伸。因此,在移除之後,空隙94將閘極堆疊與磊晶源極/汲極區92隔開。具體而言,空隙94將第一閘極間隔物86的一部分與接觸蝕刻停止層98的一部分物理性隔開。此外,由於移除剩餘間隔物96,磊晶源極/汲極區92下方的空隙94被擴展。
藉由一或多個蝕刻製程移除剩餘間隔物96和第二閘極間隔物88。如前所述,剩餘的間隔物96和第二閘極間隔物88係由相同的材料形成,並且與第一閘極間隔物86和接觸蝕刻停止層98的材料具有高蝕刻選擇性。換句話說,相較於第一閘極間隔物86和接觸蝕刻停止層98的材料,一或多個蝕刻製程以較高的速率蝕刻剩餘間隔物96和第二閘極間隔物88的材料。在操作製程期間,保護蓋110防止(或至少減少)第一層間介電質100的移除,因為一或多個蝕刻製程也可以對第一層間介電質100的材料具有選擇性。
在一些實施例中,蝕刻製程是單一蝕刻製程。單一蝕刻製程是使用包含水(H2
O)和氫氟酸(HF)的蝕刻劑進行的濕式蝕刻,並在含有例如氮氣(N2
)的惰性氣體的環境中進行。在低壓(例如壓力在約1托至約25托的範圍)和低溫(例如溫度小於0°C)下進行單一蝕刻製程。當空隙94沿著閘極堆疊延伸時,閘極堆疊具有較少的橫向支撐。當降低橫向支撐時,在低溫和低壓下進行單一蝕刻製程可有助於避免閘極堆疊變形。
在一些實施例中,蝕刻製程包含第一蝕刻製程和第二蝕刻製程。如前所述,當形成磊晶源極/汲極區92時,可以用磊晶源極/汲極區92的雜質來摻雜剩餘間隔物96和第二閘極間隔物88,並且可以將上部區域摻雜成比下部區域高的雜質濃度。第一蝕刻製程在較高的雜質濃度下具有較高的蝕刻速率,並且用於移除第二閘極間隔物88和剩餘間隔物96的上部區域。在一些實施例中,第一蝕刻製程是使用包含氨(NH3
)和氫氟酸(HF)的蝕刻劑進行的濕式蝕刻,並且在含有例如氮氣(N2
)的惰性氣體的環境中進行。第二蝕刻製程在較低雜質濃度下具有較高蝕刻速率,並且用於移除第二閘極間隔物88和剩餘間隔物96的下部區域。在一些實施例中,第二蝕刻製程是使用包含三氟化氮(NF3
)和氨(NH3
)的蝕刻劑進行的濕式蝕刻,並在含有例如氮氣(N2
)的惰性氣體的環境中進行。也在低壓(例如壓力在約1托至約25托的範圍)和低溫(例如溫度小於0°C)下進行第一蝕刻製程和第二蝕刻製程。
在繪示的實施例中,剩餘間隔物96和第二閘極間隔物88被完全移除。在一些實施例中,剩餘間隔物96和第二閘極間隔物88被部分地移除,並保留剩餘間隔物96和第二閘極間隔物88的一些剩餘介電材料。此外,如下所述,一些剩餘間隔物96和第二閘極間隔物88可以被完全移除,且其他剩餘間隔物96和第二閘極間隔物88可以被部分地移除。
在第15A至15E圖中,在保護蓋110、第一閘極間隔物86、接觸蝕刻停止層98、閘極介電層106和閘極電極108上形成介電層114。介電層114可以由介電材料形成,例如氮化矽、氧化矽、氮碳化矽、氮碳氧化矽、碳氧化矽或類似的材料,並且介電層114的形成可以藉由例如原子層沉積的沉積製程。應注意的是,介電層114部分地填充空隙94的上部。因此密封空隙94,使得在後續的處理期間材料可以不沉積於空隙94中。
在第16A至16E圖中,可以進行平坦化製程以移除保護蓋110和覆蓋保護蓋110的介電層114的一部分。平坦化製程可以是磨削(grinding)、化學機械研磨或類似的製程。介電層114的剩餘部分形成介電插塞116密封空隙94。在平坦化製程之後,第一層間介電質100、介電插塞116、第一閘極間隔物86、接觸蝕刻停止層98、閘極介電質106和閘極電極108的頂表面是齊平的。
在一些實施例中(以下繪示於第18A、19A和20A圖),在形成介電層114之前進行平坦化製程,並省略介電層114的平坦化。舉例來說,可以進行單個平坦化製程以移除保護蓋110。在平坦化製程之後,可以在第一層間介電質100上方和空隙94的上部中形成介電層114。
在第17A至17E圖中,在第一層間介電質100上方沉積第二層間介電質118。在一些實施例中,第二層間介電質118是藉由可流動式化學氣相沉積方法形成的可流動膜。在一些實施例中,第二層間介電質118係由介電材料形成,例如磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃、未摻雜的矽酸鹽玻璃或類似的材料,並且第二層間介電質118的沉積可以藉由任何適當的方法,例如化學氣相沉積和電漿輔助化學氣相沉積。在省略介電層114的平坦化的實施例中,介電層114可以作為第一層間介電質100和第二層間介電質118之間的蝕刻停止層。
根據一些實施例,在形成第二層間介電質118之前,凹蝕閘極堆疊(包含閘極介電質106和相應的上方的閘極電極108),藉此在閘極堆疊正上方且在第一閘極間隔物86的相對部分之間形成凹槽。將包含一或多層介電材料(例如氮化矽、氮氧化矽或類似的材料)的閘極遮罩120填充於凹槽中,然後進行平坦化製程以移除在第一層間介電質100上延伸的介電材料的多餘的部分。閘極遮罩120橫向設置於多對第一閘極間隔物86之間。
此外,根據一些實施例,形成閘極接觸件122和源極/汲極接觸件124穿過第二層間介電質118和第一層間介電質100。形成用於源極/汲極接觸件124的開口穿過第一層間介電質100和第二層間介電質118,並且形成用於閘極接觸件122的開口穿過第二層間介電質118和閘極遮罩120。可以使用合適的光學微影和蝕刻技術來形成開口。在開口中形成襯層(liner)(例如擴散阻障層、黏著層或類似的膜層)以及導電材料。襯層可以包含鈦、氮化鈦、鉭、氮化鉭或類似的材料。導電材料可以是銅、銅合金、銀、金、鎢、鈷、鋁、鎳或類似的材料。介電插塞116防止襯層的任何材料或導電材料沉積於空隙94中,其有助於防止閘極電極108和磊晶源極/汲極區92的短路。可以進行例如化學機械研磨的平坦化製程,以從第二層間介電質118的表面移除多餘的材料。剩餘的襯層和導電材料在開口中形成源極/汲極接觸件124和閘極接觸件122。可以進行退火製程以在磊晶源極/汲極區92與源極/汲極接觸件124之間的界面形成矽化物。源極/汲極接觸件124物理性和電性耦合至磊晶源極/汲極區92。閘極接觸件122穿過閘極遮罩120以物理性和電性耦合閘極電極108。源極/汲極接觸件124和閘極接觸件122可以採用不同的製程形成,或者可以採用相同的製程形成。雖然繪示形成於相同的剖面,但是應理解的是,源極/汲極接觸件124和閘極接觸件122中的每一個可以形成於不同的剖面,其可以避免接觸件短路。
第18A至18C圖根據一些實施例繪示所得到的鰭式場效電晶體。第18A圖係沿第1圖所示之參考剖面E-E的剖面繪示,並繪示區域50N和區域50P兩者。第18B圖係沿第18A圖所示之參考剖面B’-B’繪示(例如在區域50N中),而第18C圖係沿第18A圖所示之參考剖面C’-C’繪示(例如在區域50P)。第18A至18C圖繪示其中鰭式場效電晶體已經合併相鄰的磊晶源極/汲極區92的實施例。鰭式場效電晶體可以具有兩個合併的磊晶源極/汲極區92,或者具有兩個以上的合併的磊晶源極/汲極區92,例如四個。
如上所述,可以用不同的速率移除區域50P和50N中的剩餘間隔物96和第二閘極間隔物88。具體而言,相較於以p型雜質摻雜的剩餘間隔物96和第二閘極間隔物88(例如在區域50P中),以較快的速率移除以n型雜質摻雜的剩餘間隔物96和第二閘極間隔物88(例如在區域50N中)。如此一來,一些剩餘物130保留在區域50P中而不在區域50N中。剩餘物130可以是剩餘間隔物96及/或第二閘極間隔物88的介電材料。
此外,在繪示的實施例中,在形成介電層114之前移除保護蓋110,並省略介電層114的平坦化。介電層114因此可以作為第一層間介電質100和第二層間介電質118之間的蝕刻停止層。此外,在形成源極/汲極接觸件124時,介電層114保護空隙94不被填充。
第19A至19C圖根據一些其他實施例繪示所得到的鰭式場效電晶體。第19A圖係沿第1圖所示之參考剖面E-E的剖面繪示,並繪示區域50N和區域50P兩者。第19B圖係沿第19A圖所示之參考剖面B’-B’繪示(例如在區域50N中),而第19C圖係沿第19A圖所示之參考剖面C’-C’繪示(例如在區域50P)。第19A到19C圖的實施例類似於第18A到18C圖的實施例,除了鰭式場效電晶體具有單個未合併的磊晶源極/汲極區92。
第20A至20C圖根據一些其他實施例繪示所得到的鰭式場效電晶體。第20A圖係沿第1圖所示之參考剖面E-E的剖面繪示,並繪示區域50N和區域50P兩者。第20B圖係沿第20A圖所示之參考剖面B’-B’繪示(例如在區域50N中),而第20C圖係沿第20A圖所示之參考剖面C’-C’繪示(例如在區域50P)。第20A至20C圖的實施例類似於第19A至19C圖的實施例,除了鰭式場效電晶體具有多個未合併的磊晶源極/汲極區92。在一些實施例中,當沉積接觸蝕刻停止層98的介電材料層時,可能在未合併的磊晶源極/汲極區92之間發生夾止(pinch-off),藉此在未合併的磊晶源極/汲極區92之間形成額外的空隙132。
一些實施例可以實現一些優點。空隙94包含空氣或真空,這兩者的相對介電常數皆低於被移除的第二閘極間隔物88的材料的介電材料。在較小的裝置尺寸下,源極/汲極接觸件124與閘極電極108之間的電容可能是電路電容的顯著來源。增加源極/汲極接觸件124和閘極電極108之間的空間的相對介電常數降低電容。降低電容可以提升所得到的鰭式場效電晶體的最終裝置效能。
在一實施例中,一種方法包含:形成從基底延伸的第一鰭片;在第一鰭片上形成閘極堆疊;沿著閘極堆疊的一側沉積第一閘極間隔物,此第一閘極間隔物包含第一介電材料;沿著第一閘極間隔物的一側沉積第二閘極間隔物,此第二閘極間隔物包含第二介電材料,第二介電材料不同於第一介電材料;在鄰近第二閘極間隔物的第一鰭片中形成源極/汲極區;沿著第二閘極間隔物的一側並在源極/汲極區上方沉積接觸蝕刻停止層(CESL),此接觸蝕刻停止層包含第三介電材料,第二介電材料不同於第三介電材料;移除第二閘極間隔物的至少一部分,以在第一閘極間隔物和接觸蝕刻停止層之間形成空隙;以及形成源極/汲極接觸件穿過接觸蝕刻停止層以耦合源極/汲極區,空隙將源極/汲極接觸件與閘極堆疊物理性隔開。
在此方法的一些實施例中,第一介電材料與第三介電材料不同。在此方法的一些實施例中,第一介電材料與第三介電材料相同。在此方法的一些實施例中,移除第二閘極間隔物包含:以濕式蝕刻製程蝕刻第二閘極間隔物,用包含水和氫氟酸的蝕刻劑進行濕式蝕刻製程,在低於0°C的溫度下且壓力為1托至25托進行濕式蝕刻製程。在此方法的一些實施例中,在含有惰性氣體的環境中進行濕式蝕刻製程。在此方法的一些實施例中,移除第二閘極間隔物包含:以濕式蝕刻製程蝕刻第二閘極間隔物的上部區域,用包含氨和氫氟酸的蝕刻劑進行濕式蝕刻製程,在低於0°C的溫度下且壓力為1托至25托進行濕式蝕刻製程;以及用電漿蝕刻製程蝕刻第二閘極間隔物的下部區域,用包含三氟化氮和氨的蝕刻劑進行電漿蝕刻製程,在低於0°C的溫度下且壓力為1托至25托進行電漿蝕刻製程。在此方法的一些實施例中,在含有惰性氣體的環境中進行濕式蝕刻製程和電漿蝕刻製程兩者。在此方法的一些實施例中,以p型雜質摻雜源極/汲極區和第二閘極間隔物,且其中第二閘極間隔物被部分地移除。在此方法的一些實施例中,以n型雜質摻雜源極/汲極區和第二閘極間隔物,且其中第二閘極間隔物被完全移除。在一些實施例中,此方法更包含:在接觸蝕刻停止層上方沉積第一層間介電質(ILD);以及在第一層間介電質上方形成蓋層,此蓋層在移除期間保護第一層間介電質。在一些實施例中,此方法更包含:在蓋層上方且部分地在空隙中沉積介電層;以及用平坦化製程移除設置在空隙以外的介電層的一部分和蓋層,所述介電層的剩餘部分形成密封空隙的介電插塞。在一些實施例中,此方法更包含:在第一層間介電質和介電插塞上方沉積第二層間介電質,源極/汲極接觸件更形成為穿過第一層間介電質和第二層間介電質。在一些實施例中,此方法更包含:形成從基底延伸的第二鰭片,閘極堆疊更形成於第二鰭片上,源極/汲極區更形成於第二鰭片中,空隙更在移除之後在源極/汲極下方延伸。
在一實施例中,一種方法包含:形成從基底延伸的第一鰭片和第二鰭片;在第一鰭片上方形成第一閘極堆疊,並在第二鰭片上方形成第二閘極堆疊;沿著第一閘極堆疊的一側和沿著第二閘極堆疊的一側沉積第一閘極間隔層;在第一閘極間隔層上方沉積第二閘極間隔層,第二閘極間隔層具有靠近第一閘極堆疊的第一部分和靠近第二閘極堆疊的第二部分;在第一鰭片中形成第一源極/汲極區,且在第二鰭片中形成第二源極/汲極區,第一源極/汲極區鄰近第二閘極間隔層的第一部分,第二源極/汲極區鄰近第二閘極間隔層的第二部分;以及移除第二閘極間隔層的一部分以形成第一空隙和第二空隙,第一空隙將第一源極/汲極區與第一閘極間隔層隔開,第二空隙將第二源極/汲極區與第二閘極間隔層隔開,所述移除包含:以第一蝕刻速率蝕刻第一閘極間隔層;以第二蝕刻速率蝕刻第二閘極間隔層的第一部分;以及以第三蝕刻速率蝕刻第二閘極間隔層的第二部分,第二蝕刻速率大於第一蝕刻速率,第三蝕刻速率大於第二蝕刻速率。
在此方法的一些實施例中,第一源極/汲極區的形成包含摻雜第一源極/汲極區和第二閘極間隔層的第一部分以具有第一導電類型,且其中第二源極/汲極的形成包含摻雜第二源極/汲極區和第二閘極間隔層的第二部分以具有第二導電類型。在此方法的一些實施例中,在所述移除期間,具有第一導電類型的部件以不同於具有第二導電類型的部件的速率被蝕刻。在此方法的一些實施例中,在所述移除之後,第二閘極間隔層的第一部分和第二閘極間隔層的第二部分被完全移除。在此方法的一些實施例中,在所述移除之後,第二閘極間隔層的第一部分被部分地移除,且第二閘極間隔層的第二部分被完全移除。
在一實施例中,一種裝置包含:從基底延伸的第一鰭片;設置在第一鰭片上的閘極堆疊;設置在第一鰭片中的源極/汲極區;設置在源極/汲極區上方的接觸蝕刻停止層(CESL);沿閘極堆疊的一側延伸的閘極間隔物;以及設置在接觸蝕刻停止層和閘極間隔物之間的介電插塞,其中介電插塞、接觸蝕刻停止層、閘極間隔物和源極/汲極區共同界定空隙,空隙將閘極堆疊與源極/汲極區物理性隔開。
在一些實施例中,此裝置更包含:從基底延伸的第二鰭片,源極/汲極區更設置於第二鰭片中,其中空隙在設置於第一鰭片和第二鰭片之間的源極/汲極區的部分下方延伸。
以上概述數個實施例之部件,使得發明所屬技術領域中具有通常知識者可以更加理解本發明實施例的面向。發明所屬技術領域中具有通常知識者應該理解,他們能以本發明實施例為基礎,設計或修改其他製程和結構,以達到與在此介紹的實施例相同之目的及/或優勢。發明所屬技術領域中具有通常知識者也應該理解,此類等效的結構並未悖離本發明實施例的精神與範圍,且他們能在不違背本發明實施例的精神與範圍下,做各式各樣的改變、置換或修改。
10:區域
50:基底
50N,50P:區域
52:鰭片
56:隔離區
58:通道區
60:虛設介電層
62:虛設閘極層
64:遮罩層
70:虛設介電質
72:虛設閘極
74:遮罩
80:第一閘極間隔層
82:輕摻雜的源極/汲極區
84:第二閘極間隔層
86:閘極間隔物
88:第二閘極間隔物
90:第三閘極間隔層
92:源極/汲極區
94:空隙
96:剩餘間隔物
98:接觸蝕刻停止層
100:第一層間介電質
104:凹槽
106:閘極介電質
108:閘極電極
108A:襯層
108B:功函數調整層
108C:填充材料
110:保護蓋
114:介電層
116:介電插塞
118:第二層間介電質
120:閘極遮罩
122:閘極接觸件
124:源極/汲極接觸件
130:剩餘物
132:額外的空隙
A-A,B-B,B’-B’,C-C,C’-C’,D-D,E-E:剖面
藉由以下的詳細描述配合所附圖式,可以更加理解本發明實施例的內容。需強調的是,根據產業上的標準慣例,許多部件並未按照比例繪製。事實上,為了能清楚地討論,各種部件的尺寸可能被任意地增加或減少。
第1圖根據一些實施例以三維示意圖繪示鰭式場效電晶體的範例。
第2、3、4、5、6、7A、7B、7C、7D、7E、8A、8B、8C、8D、8E、9A、9B、9C、9D、9E、10A、10B、10C、10D、10E、11A、11B、11C、11D、11E、12A、12B、12C、12D、12E、12F、13A、13B、13C、13D、13E、14A、14B、14C、14D、14E、15A、15B、15C、15D、15E、16A、16B、16C、16D、16E、17A、17B、17C、17D、17E、18A、18B、18C圖是根據一些實施例之鰭式場效電晶體的製造過程的中間階段的剖面示意圖。
第19A至19C圖根據一些實施例繪示鰭式場效電晶體。
第20A至20C圖根據一些其他實施例繪示鰭式場效電晶體。
50:基底
50N,50P:區域
52:鰭片
58:通道區
82:輕摻雜的源極/汲極區
86:閘極間隔物
92:源極/汲極區
94:空隙
98:接觸蝕刻停止層
100:第一層間介電質
106:閘極介電質
108:閘極電極
116:介電插塞
118:第二層間介電質
120:閘極遮罩
124:源極/汲極接觸件
Claims (15)
- 一種半導體裝置的製造方法,包括:形成從一基底延伸的一第一鰭片;在該第一鰭片上形成一閘極堆疊;沿著該閘極堆疊的一側沉積一第一閘極間隔物,該第一閘極間隔物包括一第一介電材料;沿著該第一閘極間隔物的一側沉積一第二閘極間隔物,該第二閘極間隔物包括一第二介電材料,該第二介電材料不同於該第一介電材料;在鄰近該第二閘極間隔物的該第一鰭片中形成一源極/汲極區;沿著該第二閘極間隔物的一側並在該源極/汲極區上方沉積一接觸蝕刻停止層,該接觸蝕刻停止層包括一第三介電材料,該第二介電材料不同於該第三介電材料;移除該第二閘極間隔物的至少一部分,以在該第一閘極間隔物和該接觸蝕刻停止層之間形成一空隙,且該空隙在該源極/汲極區下方延伸;以及形成一源極/汲極接觸件穿過該接觸蝕刻停止層以耦合該源極/汲極區,該空隙將該源極/汲極接觸件與該閘極堆疊物理性隔開。
- 如請求項1之半導體裝置的製造方法,其中移除該第二閘極間隔物包括:以一濕式蝕刻製程蝕刻該第二閘極間隔物,用包括水和氫氟酸的蝕刻劑進行該濕式蝕刻製程,在低於0℃的溫度下且壓力為1托至25托進行該濕式蝕刻製程。
- 如請求項2之半導體裝置的製造方法,其中在含有惰性氣體的 環境中進行該濕式蝕刻製程。
- 如請求項1至3中任一項之半導體裝置的製造方法,其中移除該第二閘極間隔物包括:以一濕式蝕刻製程蝕刻該第二閘極間隔物的一上部區域,用包括氨和氫氟酸的蝕刻劑進行該濕式蝕刻製程,在低於0℃的溫度下且壓力為1托至25托進行該濕式蝕刻製程;以及用一電漿蝕刻製程蝕刻該第二閘極間隔物的一下部區域,用包含三氟化氮和氨的蝕刻劑進行該電漿蝕刻製程,在低於0℃的溫度下且壓力為1托至25托進行該電漿蝕刻製程。
- 如請求項4之半導體裝置的製造方法,其中在含有惰性氣體的環境中進行該濕式蝕刻製程和該電漿蝕刻製程兩者。
- 如請求項1至3中任一項之半導體裝置的製造方法,其中以p型雜質摻雜該源極/汲極區和該第二閘極間隔物,且其中該第二閘極間隔物被部分地移除;或以n型雜質摻雜該源極/汲極區和該第二閘極間隔物,且其中該第二閘極間隔物被完全移除。
- 如請求項1至3中任一項之半導體裝置的製造方法,更包括:在該接觸蝕刻停止層上方沉積一第一層間介電質;以及在該第一層間介電質上方形成一蓋層,該蓋層在該移除期間保護該第一層間介電質。
- 如請求項7之半導體裝置的製造方法,更包括:在該蓋層上方且部分地在該空隙中沉積一介電層;以及 用平坦化製程移除設置在該空隙以外的該介電層的複數個部分和該蓋層,該介電層的複數個剩餘部分形成密封該空隙的複數個介電插塞。
- 如請求項1至3中任一項之半導體裝置的製造方法,更包括:形成從該基底延伸的一第二鰭片,該閘極堆疊更形成於該第二鰭片上,該源極/汲極區更形成於該第二鰭片中。
- 一種半導體裝置的製造方法,包括:形成從一基底延伸的一第一鰭片和一第二鰭片;在該第一鰭片上方形成一第一閘極堆疊,並在該第二鰭片上方形成一第二閘極堆疊;沿著該第一閘極堆疊的一側和沿著該第二閘極堆疊的一側沉積一第一閘極間隔層;在該第一閘極間隔層上方沉積一第二閘極間隔層,該第二閘極間隔層具有靠近該第一閘極堆疊的一第一部分和靠近該第二閘極堆疊的一第二部分;在該第一鰭片中形成一第一源極/汲極區,且在該第二鰭片中形成一第二源極/汲極區,該第一源極/汲極區鄰近該第二閘極間隔層的該第一部分,該第二源極/汲極區鄰近該第二閘極間隔層的該第二部分;以及移除該第二閘極間隔層的複數個部分以形成一第一空隙和一第二空隙,該第一空隙將該第一源極/汲極區與該第一閘極間隔層隔開,該第二空隙將該第二源極/汲極區與該第二閘極間隔層隔開,該移除包含:以一第一蝕刻速率蝕刻該第一閘極間隔層;以一第二蝕刻速率蝕刻該第二閘極間隔層的該第一部分;以及以一第三蝕刻速率蝕刻該第二閘極間隔層的該第二部分,該第二蝕刻速 率大於該第一蝕刻速率,該第三蝕刻速率大於該第二蝕刻速率。
- 如請求項10之半導體裝置的製造方法,其中該第一源極/汲極區的形成包括摻雜該第一源極/汲極區和該第二閘極間隔層的該第一部分以具有一第一導電類型,且其中該第二源極/汲極的形成包括摻雜該第二源極/汲極區和該第二閘極間隔層的該第二部分以具有一第二導電類型。
- 如請求項11之半導體裝置的製造方法,其中在該移除期間,具有該第一導電類型的部件以不同於具有該第二導電類型的部件的速率被蝕刻。
- 如請求項10至12中任一項之半導體裝置的製造方法,其中在該移除之後,該第二閘極間隔層的該第一部分和該第二閘極間隔層的該第二部分被完全移除;或在該移除之後,該第二閘極間隔層的該第一部分被部分地移除,且該第二閘極間隔層的該第二部分被完全移除。
- 一種半導體裝置,包括:一第一鰭片,從一基底延伸;一閘極堆疊,設置於該第一鰭片上;一源極/汲極區,設置於該第一鰭片中;一接觸蝕刻停止層,設置於該源極/汲極區上方;一閘極間隔物,沿著該閘極堆疊的一側延伸;以及一介電插塞,設置於該接觸蝕刻停止層和該閘極間隔物之間,其中該介電插塞、該接觸蝕刻停止層、該閘極間隔物和該源極/汲極區共同界定一空隙,該空隙將該閘極堆疊與該源極/汲極區物理性隔開且在該源極/汲 極區下方延伸。
- 如請求項14之半導體裝置,更包括:一第二鰭片,從該基底延伸,該源極/汲極區更設置於該第二鰭片中,其中該空隙在設置於該第一鰭片和該第二鰭片之間的該源極/汲極區的部分下方延伸。
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