TWI728650B - Semiconductor protection device - Google Patents

Abstract

The semiconductor protection device of the invention, comprises a first semiconductor, a second semiconductor, a third semiconductor and a time delay generation, constituting an application circuit with load overload or short-circuit protection function, and is equivalent to the characteristic of a single semiconductor, which avoids the damage caused by overload or short-circuit at both terminals of the load.

Description

Semiconductor protection device

The invention relates to the field of electronic technology, and in particular to a semiconductor protection device with a protective function when overload or short-circuit occurs at both ends of a load during the application of a direct current circuit.

As shown in Figure 1, it is a conventional invention battery discharge protection device. It can be seen from the figure that the collector C of the second semiconductor 14 is connected to the other end of the first collector resistor 15 and the gate G of the first semiconductor 12. One end of the collector resistor 15 is connected to the positive terminal V+ of the circuit, the emitter E of the second semiconductor 14 is connected to the source S of the first semiconductor 12, and the base B of the second semiconductor 14 is connected to one end of the first base resistor 16. The other end of a base resistor 16 is connected to the negative terminal V- of the circuit. The charging device 100 in the figure does not involve the charging principle in the present invention, so it will not be repeated; when the battery 11 discharges the load 200 when an overcurrent occurs, the first The potential between the drain D and the source S of a semiconductor 12 rises rapidly. At this time, the potential of the base B of the second semiconductor 14 is higher than the emitter E, so that the second semiconductor 14 is turned on, and the gate G of the first semiconductor 12 The positive potential is equal to the positive potential of the source S of the first semiconductor 12, so the first semiconductor 12 is open. At this time, the drain current of the first semiconductor 12 is cut off to protect the battery 11 from overcurrent. If you want to release the conduction state of the second semiconductor 14, you only need to release the load 200 to release the conduction state of the second semiconductor 14 and restore the normal state of the first semiconductor 12. The disadvantages are as follows:

1. After removing the cause of the short circuit between the two ends of the load 200, a switch should be set to open the load 200 (Off), and then the set switch can be turned on (On), so that the battery 11 can supply power to the load 200 again, thus increasing the device Cost and application inconvenience.

2. To restore normal circuit functions, it is necessary to remove the cause of the short circuit caused by the load 100, open the battery 11, and then retransmit the battery 11. A switch must be added, which will increase the cost of the device and cause application inconvenience.

The purpose of the present invention: the present invention uses the first semiconductor, the second semiconductor, the third semiconductor and the delay generator to achieve the three-electrode characteristics equivalent to the function of a single semiconductor, and it can be the first direct current when the load is short-circuited in the direct current power supply circuit. The power supply is protected.

When the load is short-circuited, the application of the second semiconductor in the present invention can perform the open-circuit action of the first semiconductor in a very short time, achieving the function of protecting the DC power circuit and avoiding various disasters caused by the short-circuit of the load.

The present invention uses the third semiconductor and the delay generator to perform the functions of the second semiconductor delay action and reset time control when the present invention is turned on, so as to achieve the action of re-sending the DC power when the cause of the short circuit is eliminated.

The present invention has the following characteristics:

1. The first semiconductor of the present invention is responsible for the open circuit and conduction of the DC power supply to supply power to the load.

2. The second semiconductor of the present invention is responsible for controlling the opening and conducting actions of the first semiconductor to achieve the purpose of protecting the DC power supply circuit when a short-circuit occurs at both ends of the load.

3. The third semiconductor of the present invention is responsible for controlling the opening and conducting actions of the second semiconductor to achieve the purpose of protecting the DC power supply circuit when a short-circuit occurs at both ends of the load.

4. The delay generator of the present invention is responsible for controlling the open circuit and conduction time of the third semiconductor, so as to control the time for the first semiconductor to perform the open circuit and conduction smoothly.

5. The first semiconductor of the present invention includes both N Channel Metal Oxide Semiconductor Field Effect Transistor (N Channel MOSFET) or Insulated Gate Bipolar Transistor (IGBT) You can choose it according to your needs.

6. The second semiconductor of the present invention includes N-type transistors or N-channel metal oxide semiconductor field effect transistors, which can be selected according to requirements.

7. The third semiconductor of the present invention includes N-type transistors or N-channel metal oxide semiconductor field effect transistors, which can be selected according to requirements.

8. The delay generator of the present invention is a single timer (Single Timer) integrated circuit or other equivalent delay control integrated circuit.

9. In the present invention, the first resistor, the second resistor, the third resistor, the first semiconductor, the second semiconductor, the third semiconductor and the delay generator can be selected to form a semiconductor monomer with three-terminal characteristics to facilitate application.

10‧‧‧Delay generator

11‧‧‧First Semiconductor

12‧‧‧Second Semiconductor

13‧‧‧The Third Semiconductor

14‧‧‧First Semiconductor

15‧‧‧Second Semiconductor

16‧‧‧The Third Semiconductor

21‧‧‧First resistor

22‧‧‧Second resistor

23‧‧‧Third resistor

30‧‧‧First end

40‧‧‧Second end

50‧‧‧Third end

60‧‧‧First switch

70‧‧‧Second switch

100‧‧‧Load

200‧‧‧The first DC power supply

300‧‧‧Second DC power supply

Fig. 1 is an embodiment of a conventional battery discharge protection device.

FIG. 2 shows the first embodiment of the semiconductor protection device of the present invention.

FIG. 3 is a second embodiment of the semiconductor protection device of the present invention.

As shown in FIG. 2, it is the first embodiment of the semiconductor protection device of the present invention. As can be seen from the figure, it includes a delay generator 10, a first semiconductor 11, a second semiconductor 12, a third semiconductor 13, and a first resistor 21 ( First Resistor, 21), second resistor 22 (Second Resistor, 22) and third resistor 23 (Third Resistor, 23), the first terminal 30 (FirstTermina, 30), the second terminal 40 (SecondTerminal, 40) And the third terminal 50 (Third Terminal. 50) is the external connection terminal, and its three terminals are externally connected with the first switch 60 (First Switch, 60), the second switch, the load 100 (Load, 100), and the first DC power supply. 200 (First DC Power Source, 200) and second DC Power Source 300 (Second DC Power Source, 300).

As shown in FIG. 2, the gate G (Gate, G) of the first semiconductor 11 is connected to the collector C (Collector, C) of the second semiconductor 12 and one end of the first resistor 21, and the other end of the first resistor 21 The positive voltage terminal VD of the delay generator is connected to form the first terminal 30.

As shown in FIG. 2, the base B (Base, B) of the second semiconductor 12 is connected to the collector C of the third semiconductor 13 and the other end of the second resistor 22, and one end of the second resistor 22 is connected to the first semiconductor 11 The drain D becomes the second terminal 40.

As shown in FIG. 2, the source S (Source, S) of the first semiconductor 11 is connected to the emitter E (Emitter, E) of the second semiconductor 12, the emitter E of the third semiconductor 13 and the ground terminal of the delay generator 10 VG becomes the third terminal 50.

As shown in Figure 2, one end of the third resistor 23 is connected to the third half The base B of the conductor 13 and the other end of the third resistor 23 are connected to the voltage output terminal VO of the delay generator 10, and the positive voltage terminal VD of the delay generator 10 is connected to the first terminal 30.

As shown in Figure 2, the other end of the load 100 is connected to the second end 40, one end of the load 100 is connected to the other end of the first switch 60, and one end of the first switch 60 is connected to the positive terminal of the first DC power supply 200. The negative terminal of the current source 200 is connected to the third terminal 50.

As shown in FIG. 2, the other end of the second switch 70 is connected to the first terminal 30, one end of the second switch 70 is connected to the positive terminal of the second DC power supply 300, and the negative terminal of the second DC power supply 300 is connected to the third terminal 50.

As shown in FIG. 2, the delay generator 10 is a single-time integrated circuit or other delay-controlled integrated circuit. The first semiconductor 11 is an N-channel metal oxide semiconductor field effect transistor, and the second semiconductor 12 is an N-type transistor. The third semiconductor 13 is an N-type transistor.

As shown in Figure 2, when the first switch 60 is turned on, the positive terminal of the first DC power supply 200 supplies power to the load 100 to the second terminal 40, and the negative terminal of the first DC power supply 200 is connected to the third terminal.端50.

As shown in FIG. 2, when the first switch 60 is turned on and the second switch 70 is turned on, the positive terminal of the second DC power supply 300 is supplied to the first terminal 30, and the power is supplied from the first terminal 30 to the first terminal 30. The resistor 21 is connected to the gate G of the first semiconductor 11 and the collector C of the second semiconductor 12, because the positive terminal of the second DC power supply 300 also supplies power to the positive terminal VD of the delay generator 10, at this time the delay generator The positive output terminal VO of 10 outputs a delayed positive voltage to supply power from the third resistor 23 to the base B of the third semiconductor 13. At this time, the collector C and the emitter E of the third semiconductor 13 are turned on, so the second semiconductor 12 The collector C and the emitter E of the first semiconductor 11 are open-circuited. At this time, the drain D and the source S of the first semiconductor 11 are turned on, and the first DC power supply 200 supplies power to the load 100. The delayed positive voltage supply time of the delay generator 10 is longer Short, it depends on the demand of the load 100 and the conduction time of the first semiconductor 11, and is not self-limiting.

As shown in FIG. 2, the power supply time of the delayed positive voltage of the delay generator 10 is after the drain D and the source S of the first semiconductor 11 are turned on, the power supply of the delayed positive voltage of the delay generator 10 is stopped. At this time, the collector C and the emitter E of the third semiconductor 13 are open, so the collector C and the emitter E of the second semiconductor 12 are open, the drain D and the source S of the first semiconductor 11 are turned on, and the first DC power supply 200 supplies power to the load 100.

As shown in FIG. 2, when the second DC power supply 300 is connected to the first end 30 and the first DC power supply 200 is connected to the second end 40, the first DC power supply 200 supplies power to both ends of the load 100. The two ends are short-circuited, which is equivalent to directly applying the first DC power source 200 to both ends of the drain D and the source S of the first semiconductor 11. At this time, the voltage drop across the drain D and the second source S of the first semiconductor 11 Rising, when the base B and the emitter E of the second semiconductor 12 reach the turn-on voltage, the collector C and the emitter E of the second semiconductor 12 are turned on, and the voltage across the gate G and the source S of the first semiconductor 11 is low. Therefore, the drain D and the source S of the first semiconductor 11 are open, and the first DC power supply 200 does not supply power to the load 100, so that the short-circuit protection of the first DC power supply 200 is achieved.

It can be seen from the above that when the first terminal 30 is connected to the second DC power source 300 and the second terminal 40 is connected to the first DC power source 200, the first DC power source 200 supplies power to both ends of the load 100. Short-circuit, the first DC power supply 200 is protected. If the cause of the short-circuit at both ends of the load 100 is removed, the second switch 70 is turned to open, and then turned on. At this time, the positive voltage output terminal VO of the delay generator 10 outputs a delay The positive voltage turns on the collector C and the emitter E of the third semiconductor 13 and the base B and the emitter E of the second semiconductor 12 The voltage at both ends is low, the collector C and the emitter E of the second semiconductor 12 are open, so the drain D and the source S of the first semiconductor 11 are turned on, that is, the first DC power supply 200 is re-powered to the load 100. The second switch 70 turns to open, the first resistor 21 does not supply power to the gate G of the first semiconductor 11, and the drain D and source S of the first semiconductor 11 are open, that is, the first DC power supply 200 does not supply power to the load. 100, and the first terminal 30 can achieve the function of conducting and opening the drain D and the source S of the first semiconductor 11.

As shown in FIG. 2, when the second DC power supply 300 is connected to the first end 30 and the first DC power supply 200 is connected to the second end 40, the first DC power supply 200 supplies power to both ends of the load 100. Increasing means increasing the amount of current of the load 100. At this time, when the voltage drop between the drain D and the source S of the first semiconductor 11 is greater than the base-emitter turn-on voltage of the second semiconductor 12, the collector of the second semiconductor 12 C and emitter E are turned on, the voltage across the gate G and source S of the first semiconductor 11 is low, so the drain D and source S of the first semiconductor 11 are open, and the first DC power supply 200 does not supply power to the load 100 , And achieve the purpose of protecting the first DC power supply 200 from overcurrent.

It can be seen from the above that when the second switch 70 is turned on and switched back and forth, it is as if the first terminal 30 is connected with a positive voltage pulse and zero voltage. Therefore, the first terminal 30 is like the gate or base of a semiconductor, and the second terminal 30 is like the gate or base of a semiconductor. The terminal 40 is connected to the load 100 as the drain or collector of a semiconductor, and the third terminal 50 is connected to the negative terminals of the first DC power source 200 and the second DC power source 300 as the source or emitter of the semiconductor.

As shown in FIG. 3, it is the second embodiment of the semiconductor protection device of the present invention. As can be seen from the figure, it includes a delay generator 10, a first semiconductor 14, a second semiconductor 15, a third semiconductor 16, a first resistor 21, The first end 30, the second end 40 and the third end 50 of the second resistor 22 and the third resistor 23 are external connection ends, and the three ends are The first switch 60, the second switch 70, the load 100, the first DC power supply 200, and the second DC power supply 300 are externally connected.

As shown in FIG. 3, the gate G of the first semiconductor 14 is connected to the drain D of the second semiconductor 15 and one end of the first resistor 21, and the other end of the first resistor 21 is connected to the positive terminal VD of the delay generator 10 And constitute the first end 30.

As shown in FIG. 3, the gate G of the second semiconductor 15 is connected to the drain D of the third semiconductor 16 and the other end of the second resistor 22, and one end of the second resistor 22 is connected to the collector C of the first semiconductor 14. Become the second end 40.

As shown in FIG. 3, the emitter E of the first semiconductor 14 is connected to the source S of the second semiconductor 15, the source S of the third semiconductor 16 and the ground terminal VG of the delay generator 10 to become the third terminal 50.

As shown in FIG. 3, one end of the third resistor 23 is connected to the gate G of the third semiconductor 16, the other end of the third resistor 23 is connected to the positive voltage output terminal VO of the delay generator 10, and the delay generator 10 The positive voltage terminal VD is connected to the first terminal 30.

As shown in FIG. 3, the other end of the load 100 is connected to the second end 40, one end of the load 100 is connected to the other end of the first switch 60, and one end of the first switch 60 is connected to the positive terminal of the first DC power supply 200. The negative terminal of the current source 200 is connected to the third terminal 50.

As shown in FIG. 3, the other end of the second switch 70 is connected to the first terminal 30, one end of the second switch 70 is connected to the positive terminal of the second DC power supply 300, and the negative terminal of the second DC power supply 300 is connected to the third terminal 50.

As shown in FIG. 3, the delay generator 10 is a single-time integrated circuit or other delay-controlled integrated circuit. The first semiconductor 14 is an insulated gate bipolar transistor, and the second semiconductor 15 is an N-channel metal oxide semiconductor field effect. Transistor, the third semiconductor 16 is an N-channel metal oxide semiconductor field effect transistor.

As shown in FIG. 3, when the first switch 60 is turned on, the positive terminal of the first DC power supply 200 supplies power to the load 100 to the second terminal 40, and the negative terminal of the first DC power supply 200 is connected to the third terminal.端50.

As shown in FIG. 3, when the first switch 60 is turned on and the second switch 70 is turned on, the positive terminal of the second DC power supply 300 is supplied to the first terminal 30, and the power is supplied from the first terminal 30 to the first terminal 30. The resistor 21 is connected to the gate G of the first semiconductor 14 and the drain D of the second semiconductor 15, because the positive terminal of the second DC power supply 300 also supplies power to the positive terminal VD of the delay generator 10, at this time the delay generator The positive output terminal VO of 10 outputs a delayed positive voltage to supply power from the third resistor 23 to the gate G of the third semiconductor 16. At this time, the drain D and the source S of the third semiconductor 16 are turned on, so the second semiconductor 15 The drain D and the source S of the open circuit, the collector C and the emitter E of the first semiconductor 14 are turned on, the first DC power supply 200 supplies power to the load 100, which delays the power supply time of the delayed positive voltage of the generator 10 The length control depends on the demand of the load 100 and the conduction time of the first semiconductor 14 and is not self-limiting.

As shown in FIG. 3, the power supply time of the delay positive voltage of the delay generator 10 is after the collector C and the emitter E of the first semiconductor 14 are turned on, the power supply of the delay positive voltage of the delay generator 10 is stopped. At this time, the drain D and the source S of the third semiconductor 16 are open, so the drain D and the source S of the second semiconductor 15 are open, the collector C and the emitter E of the first semiconductor 14 are turned on, and the first DC power supply 200 supplies power to the load 100.

As shown in FIG. 3, when the second DC power supply 300 is connected to the first end 30 and the first DC power supply 200 is connected to the second end 40, the first DC power supply 200 supplies power to both ends of the load 100. The two ends are short-circuited, which is equivalent to directly applying the first DC power source 200 to both ends of the collector C and the emitter E of the first semiconductor 14. At this time, the first semiconductor 11 The voltage drop across the collector C and the emitter E rises. When the gate G and the source S of the second semiconductor 15 reach the turn-on voltage, the drain D and the source S of the second semiconductor 15 are turned on, and the first semiconductor 14 The voltage across the gate G and the emitter E is low, so the collector C and the emitter E of the first semiconductor 14 are open, the first DC power supply 200 does not supply power to the load 100, and the short circuit protection of the first DC power supply 200 is achieved. the goal of.

It can be seen from the above that when the first terminal 30 is connected to the second DC power source 300 and the second terminal 40 is connected to the first DC power source 200, the first DC power source 200 supplies power to both ends of the load 100. Short-circuit, the first DC power supply 200 is protected. If the cause of the short-circuit at both ends of the load 100 is removed, the second switch 70 is turned to open, and then turned on. At this time, the positive voltage output terminal VO of the delay generator 10 outputs a delay The positive voltage causes the drain D and the source S of the third semiconductor 16 to be turned on. The voltage across the gate G and the source S of the second semiconductor 15 is low, and the drain D and the source S of the second semiconductor 15 are open. The collector C and the emitter E of a semiconductor 14 are turned on, that is, the first DC power supply 200 is re-powered to the load 100. If the second switch 70 is turned to open, the collector C and the emitter E of the first semiconductor 14 are open. That is, the first DC power source 200 does not supply power to the load 100, and the first terminal 30 can achieve the function of conducting and opening the collector C and the emitter E of the first semiconductor 14.

As shown in FIG. 3, when the second DC power supply 300 is connected to the first end 30 and the first DC power supply 200 is connected to the second end 40, the first DC power supply 200 supplies power to both ends of the load 100. Increasing means increasing the current of the load 100. At this time, if the voltage drop between the collector C and the emitter E of the first semiconductor 14 is greater than the gate-source turn-on voltage of the second semiconductor 15, the drain of the second semiconductor 15 The electrode D is connected to the source electrode S, and the gate electrode G and the emitter electrode E of the first semiconductor 14 are two The terminal voltage is low, so the collector C and the emitter E of the first semiconductor 14 are open, and the first DC power source 200 does not supply power to the load 100, and the purpose of protecting the first DC power source 200 from overcurrent is achieved.

It can be seen from the above that when the second switch 70 is turned on and switched back and forth, it is as if the first terminal 30 is connected with a positive voltage pulse and the zero voltage is interrupted. Therefore, the first terminal 30 is like the gate or base of a semiconductor, and The second terminal 40 is connected to the load 100 as the drain or collector of a semiconductor, and the third terminal 50 is connected to the negative terminals of the first DC power source 200 and the second DC power source 300 as the source or emitter of the semiconductor.

It can be seen from the above that the operating principles and functions of FIGS. 2 and 3 are the same. The first semiconductor 11 in FIG. 2 is an N-channel metal oxide semiconductor field effect transistor, and the first semiconductor 14 in FIG. 3 is an insulated gate bipolar transistor. Transistor, the difference between the two is only applied to different loads 100. For example, the application characteristics of N-channel metal oxide semiconductor field effect transistors are low voltage and high current, which is suitable for low voltage and high current loads. The application characteristic of the polar transistor is high voltage and high current, suitable for the load 100 of high voltage and high current. It can be known that it can be selected according to the demand of the load 100. Therefore, the first semiconductor 11 and the first semiconductor 14 can be replaced with each other. No self-limitation.

It can be seen from the above that the operating principles and functions of FIGS. 2 and 3 are the same. The second semiconductor 12 in FIG. 2 is an N-type transistor, and the second semiconductor 15 in FIG. 3 is an N-channel metal oxide semiconductor field effect transistor. It can be seen that it can be selected according to the demand of the load 100, so the second semiconductor 12 and the second semiconductor 15 can be replaced with each other, and are not self-limiting.

It can be seen from the above that the operating principles and functions of FIGS. 2 and 3 are the same. The third semiconductor 13 in FIG. 2 is an N-type transistor, and the third semiconductor 16 in FIG. 3 is an N-channel metal oxide semiconductor field effect transistor. It can be seen that it follows the third semiconductor 13, the third semiconductor 16 and The time delay generator 10 needs to be selected, so the third semiconductor 13 and the third semiconductor 16 can be replaced with each other without self-limiting.

The above-mentioned embodiments are only preferred embodiments for fully explaining the present invention. The protection scope of the present invention is not limited to this, including equivalent substitutions or transformations made by those skilled in the art on the basis of the present invention. All are within the protection scope of the present invention. The scope of protection of the present invention is subject to the scope of the patent application.

10‧‧‧Delay generator

11‧‧‧First Semiconductor

12‧‧‧Second Semiconductor

13‧‧‧The Third Semiconductor

21‧‧‧First resistor

22‧‧‧Second resistor

23‧‧‧Third resistor

30‧‧‧First end

40‧‧‧Second end

50‧‧‧Third end

60‧‧‧First switch

70‧‧‧Second switch

100‧‧‧Load

200‧‧‧The first DC power supply

300‧‧‧Second DC power supply

Claims (12)

A semiconductor protection device is applied to a DC circuit. When the load of the DC circuit is overloaded or short-circuited, its function is to protect the first DC power supply. It includes: a first semiconductor with a drain and a A source and a gate; a second semiconductor having a collector, an emitter and a base, the collector of the second semiconductor is connected to the gate of the first semiconductor, and the emitter of the second semiconductor is connected to the The source of the first semiconductor; a third semiconductor having a collector, an emitter and a base, the emitter of the third semiconductor is connected to the emitter of the second semiconductor, and the collector of the third semiconductor is connected to the The base of the second semiconductor; a first resistor with two connecting ends, one end of the first resistor is connected with the gate of the first semiconductor and the collector of the second semiconductor; a second resistor with Two connecting ends, one end of the second resistor is connected to the drain of the first semiconductor to become a second end, the second end has the function of providing the other end of the load, and one end of the load is connected to the first DC The positive terminal of the power supply, the other end of the second resistor is connected to the base of the second semiconductor and the collector of the third semiconductor; a third resistor has two connecting ends, one end of the third resistor Connected to the base of the third semiconductor; and a delay generator, which has the function of starting the first semiconductor to turn from open circuit to conduction, and has a positive voltage terminal, a positive voltage output terminal and a ground terminal, and the positive voltage terminal is connected to the first The other end of the resistor becomes the first end. The first end has the function of providing a positive terminal connected to the second DC power source. The positive voltage output end is connected to the other end of the third resistor, and the ground end is connected to the third end. The emitter of the semiconductor, the emitter of the second semiconductor, and the source of the first semiconductor become the third end, and the third The terminal has the function of providing a negative terminal connecting the first DC power source and the second DC power source. According to the semiconductor protection device described in claim 1, wherein the first semiconductor is an N-channel metal oxide semiconductor field-effect transistor or an N-type insulated gate bipolar transistor. According to the semiconductor protection device described in claim 1, wherein the second semiconductor is an N-type transistor or an N-channel metal oxide semiconductor field effect transistor. According to the semiconductor protection device described in claim 1, wherein the third semiconductor is an N-type transistor or an N-channel metal oxide semiconductor field effect transistor. The semiconductor protection device according to the first item of the scope of patent application, wherein the positive terminal of the first DC power supply is connected to one end of the load, the other end of the load is connected to the second terminal, and the negative terminal of the first DC power supply is The terminal is connected to the third terminal; the positive terminal of the second DC power source is connected to the first terminal, and the negative terminal of the second DC power source is connected to the third terminal. The semiconductor protection device according to item 5 of the scope of patent application further includes a first switch and a second switch, the first switch is located between the first DC power supply and the load; the second switch is located at the second DC Between the power supply and the first end. A semiconductor protection device, which is applied to a DC circuit. When the load of the DC circuit is overloaded or short-circuited, its function is to protect the first DC power supply. It includes: a first semiconductor with a collector, a An emitter and a gate; a second semiconductor having a drain, a source and a gate, the drain of the second semiconductor is connected to the gate of the first semiconductor, and the source of the second semiconductor is connected to the The emitter of the first semiconductor; a third semiconductor having a drain, a source and a gate, the source of the third semiconductor is connected to the source of the second semiconductor, the first The drain of three semiconductors is connected to the gate of the second semiconductor; a first resistor has two connecting ends, one end of the first resistor is connected to the gate of the first semiconductor and the drain of the second semiconductor; A second resistor has two connecting ends. One end of the second resistor is connected to the collector of the first semiconductor to become a second end. The second end has the function of providing the other end of the connected load. One end is connected to the positive terminal of the first DC power source, the other end of the second resistor is connected to the gate of the second semiconductor and the drain of the third semiconductor; a third resistor has two connecting ends, One end of the third resistor is connected to the gate of the third semiconductor; and a delay generator has the function of starting the first semiconductor to turn from open circuit to conduction, and has a positive voltage terminal, a positive voltage output terminal and a ground terminal. The positive voltage terminal is connected to the other end of the first resistor to become the first terminal. The first terminal has the function of providing a positive terminal connected to the second DC power supply. The positive voltage output terminal is connected to the other end of the third resistor, The ground terminal is connected to the source of the third semiconductor, the source of the second semiconductor, and the emitter of the first semiconductor to become a third terminal. The third terminal is provided to connect the first direct current power source and the second direct current source. The function of the negative terminal of the power supply. According to the semiconductor protection device described in item 7 of the scope of patent application, the first semiconductor is an N-type insulated gate bipolar transistor or an N-channel metal oxide semiconductor field effect transistor. According to the semiconductor protection device described in item 7 of the scope of patent application, the second semiconductor is an N-channel metal oxide semiconductor field-effect transistor or an N-type transistor. The semiconductor protection device according to item 7 of the scope of patent application, wherein the third semiconductor is an N-channel metal oxide semiconductor field effect transistor Or N-type transistor. The semiconductor protection device according to item 7 of the scope of patent application, wherein the positive terminal of the first DC power supply is connected to one end of the load, the other end of the load is connected to the second terminal, and the negative terminal of the first DC power supply is The terminal is connected to the third terminal; the positive terminal of the second DC power source is connected to the first terminal, and the negative terminal of the second DC power source is connected to the third terminal. The semiconductor protection device described in item 11 of the scope of the patent application further includes a first switch and a second switch, the first switch is located between the first DC power source and the load; the second switch is located at the second DC Between the power supply and the first end.

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